| commit | 3929743408eaab6b308cbb7c09d634249a6f3a52 | [log] [tgz] |
|---|---|---|
| author | Fabio Utzig <utzig@apache.org> | Wed May 08 18:51:10 2019 -0300 |
| committer | Fabio Utzig <utzig@utzig.org> | Thu May 16 14:01:19 2019 -0300 |
| tree | 616e011f7af5ceeeaa97619b2c3f4c254e5eb654 | |
| parent | 19fd79a496248c40f95d3359e1e60931df5e734f [diff] [blame] |
Add simulator support for RSA-3072 sigs Signed-off-by: Fabio Utzig <utzig@apache.org>
diff --git a/sim/src/caps.rs b/sim/src/caps.rs index 2751618..f316fd6 100644 --- a/sim/src/caps.rs +++ b/sim/src/caps.rs
@@ -12,6 +12,7 @@ EncRsa = (1 << 5), EncKw = (1 << 6), ValidatePrimarySlot = (1 << 7), + RSA3072 = (1 << 8), } impl Caps {