diff --git a/boot/cypress/BlinkyApp/BlinkyApp.mk b/boot/cypress/BlinkyApp/BlinkyApp.mk
index 0fd575f..5936e07 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.mk
+++ b/boot/cypress/BlinkyApp/BlinkyApp.mk
@@ -277,7 +277,7 @@
 
 # Disble wdt free hal call
 ifneq ($(DISABLE_WDT_FREE), 0)
-DEFINES_APP += -DISABLE_WDT_FREE
+DEFINES_APP += -DDISABLE_WDT_FREE
 endif
 
 pre_build:
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.md b/boot/cypress/MCUBootApp/MCUBootApp.md
index 410bd4a..b5bc044 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.md
+++ b/boot/cypress/MCUBootApp/MCUBootApp.md
@@ -583,6 +583,9 @@
 Misaligned application_1 (secondary slot) - suggested address 0x18030200
 ```
 This gives the nearest larger address that satisfies the slot location requirements. Other errors, such as overlapping flash areas, are also checked and reported.
+
+To improve boot time user may specify build variables `MCUBOOT_SWAP_STATUS_FAST_BOOT=1` `USE_BOOTSTRAP=0` and comment out `MCUBOOT_VALIDATE_PRIMARY_SLOT` in "mcuboot_config.h" to achieve faser boot.
+
 ### Hardware limitations
 
 This application is created to demonstrate the MCUboot library features and not as a reference example. So, some considerations are taken.
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.mk b/boot/cypress/MCUBootApp/MCUBootApp.mk
index 31dd40f..db0d950 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.mk
+++ b/boot/cypress/MCUBootApp/MCUBootApp.mk
@@ -42,6 +42,7 @@
 USE_SHARED_SLOT ?= 0
 FIH_PROFILE_LEVEL_LIST := OFF LOW MEDIUM HIGH
 FIH_PROFILE_LEVEL ?= MEDIUM
+MCUBOOT_SWAP_STATUS_FAST_BOOT ?= 0
 
 ifeq ($(BUILDCFG), Release)
 MCUBOOT_LOG_LEVEL ?= MCUBOOT_LOG_LEVEL_INFO
@@ -53,6 +54,10 @@
 $(error Only GCC ARM is supported at this moment)
 endif
 
+ifeq ($(MCUBOOT_SWAP_STATUS_FAST_BOOT), 1)
+DEFINES_APP += -DMCUBOOT_SWAP_STATUS_FAST_BOOT
+endif
+
 # Check FIH profile param
 ifneq ($(filter $(FIH_PROFILE_LEVEL), $(FIH_PROFILE_LEVEL_LIST)),)
 ifneq ($(FIH_PROFILE_LEVEL), OFF) 
diff --git a/boot/cypress/MCUBootApp/main.c b/boot/cypress/MCUBootApp/main.c
index 8c7bdd0..b526d77 100644
--- a/boot/cypress/MCUBootApp/main.c
+++ b/boot/cypress/MCUBootApp/main.c
@@ -25,13 +25,14 @@
 #include "cyhal.h"
 #include "cyhal_wdt.h"
 
+#include "cyw_platform_utils.h"
+
 #if defined CYW20829
 #include "cy_service_app.h"
 #endif
 
 #include "cybsp.h"
 #include "cy_retarget_io.h"
-#include "cyw_platform_utils.h"
 
 #if defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829)
 #include "flash_qspi.h"
diff --git a/boot/cypress/Makefile b/boot/cypress/Makefile
index e901317..a444c04 100644
--- a/boot/cypress/Makefile
+++ b/boot/cypress/Makefile
@@ -65,7 +65,7 @@
 
 # Defines whether or not make all compile warnings into errors for application
 # source code (but not for library source code)
-WARN_AS_ERR = 0
+WARN_AS_ERR ?= 1
 
 ifneq ($(filter $(APP_NAME), $(APPS)),)
 include ./$(APP_NAME)/$(APP_NAME).mk
diff --git a/boot/cypress/platforms/BSP/XMC7000/CAT1C_SMIF.FLM b/boot/cypress/platforms/BSP/XMC7000/CAT1C_SMIF.FLM
index 1153f5d..bd9781a 100644
--- a/boot/cypress/platforms/BSP/XMC7000/CAT1C_SMIF.FLM
+++ b/boot/cypress/platforms/BSP/XMC7000/CAT1C_SMIF.FLM
Binary files differ
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h b/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
index 1f9f0d6..30363dc 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
@@ -24,7 +24,7 @@
 #include "cyhal_pin_package.h"
 #endif
 /* CAT4 and CAT5 do not have configurators so the BSP defines pins in a non-generated header */
-#if defined(COMPONENT_CAT4) || defined(COMPONENT_CAT5)
+#if defined(COMPONENT_CAT4)
 #include "cybsp_pins.h"
 #else
 #include "cycfg.h"
@@ -357,11 +357,15 @@
 /** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE
  */
 
+#ifndef CYBSP_WIFI_HOST_WAKE_GPIO_DM
 /** WiFi host-wake GPIO drive mode */
 #define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
+#endif
+#ifndef CYBSP_WIFI_HOST_WAKE_IRQ_EVENT
 /** WiFi host-wake IRQ event */
 #define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
 #endif
+#endif // ifdef CYBSP_WIFI_HOST_WAKE
 #ifdef CYBSP_BT_UART_RX
 /** Pin: BT UART RX \def CYBSP_BT_UART_RX
  */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h b/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
index 580d49c..a6c9bad 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
@@ -28,6 +28,7 @@
 
 #include "cy_result.h"
 #include "cybsp_types.h"
+#include "cycfg_pins.h"
 
 #if defined(__cplusplus)
 extern "C" {
@@ -37,6 +38,13 @@
 #define CYBSP_USER_BTN_DRIVE          (CYHAL_GPIO_DRIVE_PULLUP)
 #endif
 
+#ifndef CYBSP_DEBUG_UART_CTS
+#define CYBSP_DEBUG_UART_CTS (NC)
+#endif
+#ifndef CYBSP_DEBUG_UART_RTS
+#define CYBSP_DEBUG_UART_RTS (NC)
+#endif
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.c b/boot/cypress/platforms/BSP/XMC7000/cycfg.c
index f61f95b..734470f 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.c
@@ -1,30 +1,31 @@
 /*******************************************************************************
-* File Name: cycfg.c
-*
-* Description:
-* Wrapper function to initialize all generated code.
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg.c
+ *
+ * Description:
+ * Simple wrapper containing all generated files and function to initialize
+ * all generated code.
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #include "cycfg.h"
 
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.h b/boot/cypress/platforms/BSP/XMC7000/cycfg.h
index c650151..9528ebe 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.h
@@ -1,38 +1,35 @@
 /*******************************************************************************
-* File Name: cycfg.h
-*
-* Description:
-* Simple wrapper header containing all generated files.
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg.h
+ *
+ * Description:
+ * Simple wrapper containing all generated files and function to initialize
+ * all generated code.
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #if !defined(CYCFG_H)
 #define CYCFG_H
 
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
 #include "cycfg_notices.h"
 #include "cycfg_system.h"
 #include "cycfg_clocks.h"
@@ -40,14 +37,16 @@
 #include "cycfg_peripherals.h"
 #include "cycfg_pins.h"
 
+#if defined(__cplusplus)
+extern "C" {
+#endif /* defined(__cplusplus) */
+
 void init_cycfg_all(void);
 void cycfg_config_init(void);
 void cycfg_config_reservations(void);
 
-
 #if defined(__cplusplus)
 }
-#endif
-
+#endif /* defined(__cplusplus) */
 
 #endif /* CYCFG_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp b/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp
index a2dfeb7..2f754ab 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp
@@ -1,28 +1,27 @@
 /*******************************************************************************
-* File Name: cycfg.timestamp
-*
-* Description:
-* Sentinel file for determining if generated source is up to date.
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
+ * File Name: cycfg.timestamp
+ *
+ * Description:
+ * Sentinel file for determining if generated source is up to date.
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
index 8d36f4e..4b16b75 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
@@ -1,73 +1,51 @@
 /*******************************************************************************
-* File Name: cycfg_clocks.c
-*
-* Description:
-* Clock configuration
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_clocks.c
+ *
+ * Description:
+ * Clock configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #include "cycfg_clocks.h"
 
 #if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t peri_0_group_0_div_16_0_obj = 
-    {
-        .type = CYHAL_RSC_CLOCK,
-        .block_num = peri_0_group_0_div_16_0_HW,
-        .channel_num = peri_0_group_0_div_16_0_NUM,
-    };
-    const cyhal_resource_inst_t peri_0_group_0_div_8_2_obj = 
-    {
-        .type = CYHAL_RSC_CLOCK,
-        .block_num = peri_0_group_0_div_8_2_HW,
-        .channel_num = peri_0_group_0_div_8_2_NUM,
-    };
-    const cyhal_resource_inst_t peri_0_group_1_div_24_5_0_obj = 
-    {
-        .type = CYHAL_RSC_CLOCK,
-        .block_num = peri_0_group_1_div_24_5_0_HW,
-        .channel_num = peri_0_group_1_div_24_5_0_NUM,
-    };
-#endif //defined (CY_USING_HAL)
-
+const cyhal_resource_inst_t CYBSP_TRACE_CLK_DIV_obj =
+{
+    .type = CYHAL_RSC_CLOCK,
+    .block_num = CYBSP_TRACE_CLK_DIV_HW,
+    .channel_num = CYBSP_TRACE_CLK_DIV_NUM,
+};
+#endif /* defined (CY_USING_HAL) */
 
 void init_cycfg_clocks(void)
 {
-    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_16_0_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U);
-    Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_16_0_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U, 0U);
-    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_16_0_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U);
-    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U);
-    Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U, 0U);
-    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U);
-    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_24_5_0_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U);
-    Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_24_5_0_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U, 105U, 11U);
-    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_24_5_0_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U);
+    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U);
+    Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U, 0U);
+    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 3U);
 }
-
 void reserve_cycfg_clocks(void)
 {
 #if defined (CY_USING_HAL)
-    cyhal_hwmgr_reserve(&peri_0_group_0_div_16_0_obj);
-    cyhal_hwmgr_reserve(&peri_0_group_0_div_8_2_obj);
-    cyhal_hwmgr_reserve(&peri_0_group_1_div_24_5_0_obj);
-#endif //defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_TRACE_CLK_DIV_obj);
+#endif /* defined (CY_USING_HAL) */
 }
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
index a066ddc..0bb0ba4 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
@@ -1,84 +1,67 @@
 /*******************************************************************************
-* File Name: cycfg_clocks.h
-*
-* Description:
-* Clock configuration
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_clocks.h
+ *
+ * Description:
+ * Clock configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #if !defined(CYCFG_CLOCKS_H)
 #define CYCFG_CLOCKS_H
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
+
 #if defined (CY_USING_HAL)
-    #include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
+#include "cyhal_hwmgr.h"
+#endif /* defined (CY_USING_HAL) */
 
 #if defined(__cplusplus)
 extern "C" {
-#endif
+#endif /* defined(__cplusplus) */
 
-#define peri_0_group_0_div_16_0_ENABLED 1U
-#if defined (CY_USING_HAL)
-    #define peri_0_group_0_div_16_0_HW CYHAL_CLOCK_BLOCK_PERIPHERAL0_16BIT
-#endif //defined (CY_USING_HAL)
-#if !defined (CY_USING_HAL)
-    #define peri_0_group_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
-#endif //!defined (CY_USING_HAL)
-#define peri_0_group_0_div_16_0_NUM 0U
-#define PERI_0_GROUP_0_DIV_16_0_GRP_NUM (0U << PERI_PCLK_GR_NUM_Pos)
-#define peri_0_group_0_div_8_2_ENABLED 1U
-#if defined (CY_USING_HAL)
-    #define peri_0_group_0_div_8_2_HW CYHAL_CLOCK_BLOCK_PERIPHERAL0_8BIT
-#endif //defined (CY_USING_HAL)
-#if !defined (CY_USING_HAL)
-    #define peri_0_group_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
-#endif //!defined (CY_USING_HAL)
-#define peri_0_group_0_div_8_2_NUM 2U
-#define PERI_0_GROUP_0_DIV_8_2_GRP_NUM (0U << PERI_PCLK_GR_NUM_Pos)
-#define peri_0_group_1_div_24_5_0_ENABLED 1U
-#if defined (CY_USING_HAL)
-    #define peri_0_group_1_div_24_5_0_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_24_5BIT
-#endif //defined (CY_USING_HAL)
-#if !defined (CY_USING_HAL)
-    #define peri_0_group_1_div_24_5_0_HW CY_SYSCLK_DIV_24_5_BIT
-#endif //!defined (CY_USING_HAL)
-#define peri_0_group_1_div_24_5_0_NUM 0U
-#define PERI_0_GROUP_1_DIV_24_5_0_GRP_NUM (1U << PERI_PCLK_GR_NUM_Pos)
+#define CYBSP_TRACE_CLK_DIV_ENABLED 1U
+
+#if defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE)
+#define CYBSP_TRACE_CLK_DIV_HW CYHAL_CLOCK_BLOCK_PERIPHERAL0_8BIT
+#endif /* defined (CY_USING_HAL) || defined (CY_USING_HAL_LITE) */
+
+#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
+#define CYBSP_TRACE_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
+
+#define CYBSP_TRACE_CLK_DIV_NUM 3U
+#define CYBSP_TRACE_CLK_DIV_GRP_NUM ((0U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
 
 #if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t peri_0_group_0_div_16_0_obj;
-    extern const cyhal_resource_inst_t peri_0_group_0_div_8_2_obj;
-    extern const cyhal_resource_inst_t peri_0_group_1_div_24_5_0_obj;
-#endif //defined (CY_USING_HAL)
+extern const cyhal_resource_inst_t CYBSP_TRACE_CLK_DIV_obj;
+#endif /* defined (CY_USING_HAL) */
 
 void init_cycfg_clocks(void);
 void reserve_cycfg_clocks(void);
 
 #if defined(__cplusplus)
 }
-#endif
-
+#endif /* defined(__cplusplus) */
 
 #endif /* CYCFG_CLOCKS_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
index 7499cf0..318279d 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
@@ -1,46 +1,53 @@
 /*******************************************************************************
-* File Name: cycfg_notices.h
-*
-* Description:
-* Contains warnings and errors that occurred while generating code for the
-* design.
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_notices.h
+ *
+ * Description:
+ * Contains warnings and errors that occurred while generating code for the
+ * design.
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #if !defined(CYCFG_NOTICES_H)
 #define CYCFG_NOTICES_H
 
-#ifdef CY_SUPPORTS_DEVICE_VALIDATION
-#ifndef XMC7100D_E272K4160
-    #error "Unexpected MPN; expected DEVICE:=XMC7100D-E272K4160. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
-#endif
-#endif
+#if defined(__cplusplus)
+extern "C" {
+#endif /* defined(__cplusplus) */
 
-#ifdef CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION
-#ifndef XMC7100D_E272K4160
-    #error "Unexpected MPN; expected DEVICE:=XMC7100D-E272K4160. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
-#endif
-#endif
+#if defined(CY_SUPPORTS_DEVICE_VALIDATION)
+#if !defined(XMC7200D_E272K8384)
+#error "Unexpected MPN; expected DEVICE:=XMC7200D-E272K8384. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif /* !defined(XMC7200D_E272K8384) */
+#endif /* defined(CY_SUPPORTS_DEVICE_VALIDATION) */
 
+#if defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION)
+#if !defined(XMC7200D_E272K8384)
+#error "Unexpected MPN; expected DEVICE:=XMC7200D-E272K8384. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif /* !defined(XMC7200D_E272K8384) */
+#endif /* defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION) */
+
+#if defined(__cplusplus)
+}
+#endif /* defined(__cplusplus) */
 
 #endif /* CYCFG_NOTICES_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
index 3e65c19..3701533 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
@@ -1,30 +1,29 @@
 /*******************************************************************************
-* File Name: cycfg_peripherals.c
-*
-* Description:
-* Peripheral Hardware Block configuration
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_peripherals.c
+ *
+ * Description:
+ * Peripheral Hardware Block configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #include "cycfg_peripherals.h"
-
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
index 2eec711..cb08758 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
@@ -1,43 +1,42 @@
 /*******************************************************************************
-* File Name: cycfg_peripherals.h
-*
-* Description:
-* Peripheral Hardware Block configuration
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_peripherals.h
+ *
+ * Description:
+ * Peripheral Hardware Block configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #if !defined(CYCFG_PERIPHERALS_H)
 #define CYCFG_PERIPHERALS_H
 
 #include "cycfg_notices.h"
+
 #if defined(__cplusplus)
 extern "C" {
-#endif
-
+#endif /* defined(__cplusplus) */
 
 #if defined(__cplusplus)
 }
-#endif
-
+#endif /* defined(__cplusplus) */
 
 #endif /* CYCFG_PERIPHERALS_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
index d4ad893..9724f7d 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
@@ -1,34 +1,34 @@
 /*******************************************************************************
-* File Name: cycfg_pins.c
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_pins.c
+ *
+ * Description:
+ * Pin configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #include "cycfg_pins.h"
 
-const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = 
+const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_ANALOG,
@@ -44,15 +44,17 @@
     .vrefSel = 0UL,
     .vohSel = 0UL,
 };
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_WCO_IN_PORT_NUM,
-        .channel_num = CYBSP_WCO_IN_PIN,
-    };
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
+{
+    .type = CYHAL_RSC_GPIO,
+    .block_num = CYBSP_WCO_IN_PORT_NUM,
+    .channel_num = CYBSP_WCO_IN_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_ANALOG,
@@ -68,15 +70,17 @@
     .vrefSel = 0UL,
     .vohSel = 0UL,
 };
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_WCO_OUT_PORT_NUM,
-        .channel_num = CYBSP_WCO_OUT_PIN,
-    };
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = 
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
+{
+    .type = CYHAL_RSC_GPIO,
+    .block_num = CYBSP_WCO_OUT_PORT_NUM,
+    .channel_num = CYBSP_WCO_OUT_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config =
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_ANALOG,
@@ -92,15 +96,17 @@
     .vrefSel = 0UL,
     .vohSel = 0UL,
 };
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_ECO_IN_obj = 
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_ECO_IN_PORT_NUM,
-        .channel_num = CYBSP_ECO_IN_PIN,
-    };
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = 
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t CYBSP_ECO_IN_obj =
+{
+    .type = CYHAL_RSC_GPIO,
+    .block_num = CYBSP_ECO_IN_PORT_NUM,
+    .channel_num = CYBSP_ECO_IN_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config =
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_ANALOG,
@@ -116,15 +122,17 @@
     .vrefSel = 0UL,
     .vohSel = 0UL,
 };
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_ECO_OUT_obj = 
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_ECO_OUT_PORT_NUM,
-        .channel_num = CYBSP_ECO_OUT_PIN,
-    };
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t CYBSP_ECO_OUT_obj =
+{
+    .type = CYHAL_RSC_GPIO,
+    .block_num = CYBSP_ECO_OUT_PORT_NUM,
+    .channel_num = CYBSP_ECO_OUT_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
@@ -140,15 +148,17 @@
     .vrefSel = 0UL,
     .vohSel = 0UL,
 };
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_SWO_obj = 
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_SWO_PORT_NUM,
-        .channel_num = CYBSP_SWO_PIN,
-    };
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t CYBSP_SWO_obj =
+{
+    .type = CYHAL_RSC_GPIO,
+    .block_num = CYBSP_SWO_PORT_NUM,
+    .channel_num = CYBSP_SWO_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_PULLDOWN,
@@ -164,15 +174,17 @@
     .vrefSel = 0UL,
     .vohSel = 0UL,
 };
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_SWDCK_PORT_NUM,
-        .channel_num = CYBSP_SWDCK_PIN,
-    };
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t CYBSP_SWDCK_obj =
+{
+    .type = CYHAL_RSC_GPIO,
+    .block_num = CYBSP_SWDCK_PORT_NUM,
+    .channel_num = CYBSP_SWDCK_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_PULLUP,
@@ -188,25 +200,22 @@
     .vrefSel = 0UL,
     .vohSel = 0UL,
 };
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_SWDIO_PORT_NUM,
-        .channel_num = CYBSP_SWDIO_PIN,
-    };
-#endif //defined (CY_USING_HAL)
 
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t CYBSP_SWDIO_obj =
+{
+    .type = CYHAL_RSC_GPIO,
+    .block_num = CYBSP_SWDIO_PORT_NUM,
+    .channel_num = CYBSP_SWDIO_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
 
 void init_cycfg_pins(void)
 {
-    Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config);
-    Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config);
     Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
     Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
     Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
 }
-
 void reserve_cycfg_pins(void)
 {
 #if defined (CY_USING_HAL)
@@ -217,5 +226,5 @@
     cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
     cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
     cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
-#endif //defined (CY_USING_HAL)
+#endif /* defined (CY_USING_HAL) */
 }
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
index 2acf412..29b5cd9 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
@@ -1,30 +1,30 @@
 /*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_pins.h
+ *
+ * Description:
+ * Pin configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #if !defined(CYCFG_PINS_H)
 #define CYCFG_PINS_H
@@ -32,66 +32,72 @@
 #include "cycfg_notices.h"
 #include "cy_gpio.h"
 #include "cycfg_routing.h"
+
 #if defined (CY_USING_HAL)
-    #include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
+#include "cyhal_hwmgr.h"
+#endif /* defined (CY_USING_HAL) */
+
+#if defined (CY_USING_HAL_LITE)
+#include "cyhal_hw_types.h"
+#endif /* defined (CY_USING_HAL_LITE) */
 
 #if defined(__cplusplus)
 extern "C" {
-#endif
+#endif /* defined(__cplusplus) */
 
-#if defined (CY_USING_HAL)
-    #define CYBSP_CAN_TX (P0_2)
-    #define CYBSP_CAN_RX (P0_3)
-    #define CYBSP_SPI_MISO (P10_0)
-    #define CYBSP_D12 CYBSP_SPI_MISO
-    #define CYBSP_SPI_MOSI (P10_1)
-    #define CYBSP_D11 CYBSP_SPI_MOSI
-    #define CYBSP_SPI_CLK (P10_2)
-    #define CYBSP_D13 CYBSP_SPI_CLK
-    #define CYBSP_SPI_CS (P10_3)
-    #define CYBSP_D10 CYBSP_SPI_CS
-    #define CYBSP_D9 (P10_4)
-    #define CYBSP_D8 (P10_5)
-    #define CYBSP_A8 (P12_0)
-    #define CYBSP_A9 (P12_1)
-    #define CYBSP_A10 (P12_2)
-    #define CYBSP_A11 (P12_3)
-    #define CYBSP_A12 (P12_4)
-    #define CYBSP_A13 (P12_5)
-    #define CYBSP_A14 (P12_6)
-    #define CYBSP_A15 (P12_7)
-    #define CYBSP_DEBUG_UART_RX (P13_0)
-    #define CYBSP_D0 CYBSP_DEBUG_UART_RX
-    #define CYBSP_DEBUG_UART_TX (P13_1)
-    #define CYBSP_D1 CYBSP_DEBUG_UART_TX
-    #define CYBSP_DEBUG_UART_RTS (P13_2)
-    #define CYBSP_D2 CYBSP_DEBUG_UART_RTS
-    #define CYBSP_DEBUG_UART_CTS (P13_3)
-    #define CYBSP_D3 CYBSP_DEBUG_UART_CTS
-    #define CYBSP_D4 (P13_4)
-    #define CYBSP_D5 (P13_5)
-    #define CYBSP_D6 (P13_6)
-    #define CYBSP_D7 (P13_7)
-    #define CYBSP_A0 (P14_0)
-    #define CYBSP_A1 (P14_1)
-    #define CYBSP_A2 (P14_2)
-    #define CYBSP_A3 (P14_3)
-    #define CYBSP_A4 (P14_4)
-    #define CYBSP_A5 (P14_5)
-    #define CYBSP_A6 (P14_6)
-    #define CYBSP_A7 (P14_7)
-    #define CYBSP_I2C_SDA (P15_1)
-    #define CYBSP_I2C_SCL (P15_2)
-    #define CYBSP_USER_LED (P16_1)
-    #define CYBSP_USER_LED1 CYBSP_USER_LED
-    #define LED1 CYBSP_USER_LED
-    #define CYBSP_USER_LED2 (P16_2)
-    #define LED2 CYBSP_USER_LED2
-    #define CYBSP_USER_LED3 (P16_3)
-    #define LED3 CYBSP_USER_LED3
-    #define CYBSP_USER_BTN2 (P17_3)
-#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define CYBSP_CAN_TX (P0_2)
+#define CYBSP_CAN_RX (P0_3)
+#define CYBSP_SPI_MISO (P10_0)
+#define CYBSP_D12 CYBSP_SPI_MISO
+#define CYBSP_SPI_MOSI (P10_1)
+#define CYBSP_D11 CYBSP_SPI_MOSI
+#define CYBSP_SPI_CLK (P10_2)
+#define CYBSP_D13 CYBSP_SPI_CLK
+#define CYBSP_SPI_CS (P10_3)
+#define CYBSP_D10 CYBSP_SPI_CS
+#define CYBSP_D9 (P10_4)
+#define CYBSP_D8 (P10_5)
+#define CYBSP_A8 (P12_0)
+#define CYBSP_A9 (P12_1)
+#define CYBSP_A10 (P12_2)
+#define CYBSP_A11 (P12_3)
+#define CYBSP_A12 (P12_4)
+#define CYBSP_A13 (P12_5)
+#define CYBSP_A14 (P12_6)
+#define CYBSP_A15 (P12_7)
+#define CYBSP_DEBUG_UART_RX (P13_0)
+#define CYBSP_D0 CYBSP_DEBUG_UART_RX
+#define CYBSP_DEBUG_UART_TX (P13_1)
+#define CYBSP_D1 CYBSP_DEBUG_UART_TX
+#define CYBSP_DEBUG_UART_RTS (P13_2)
+#define CYBSP_D2 CYBSP_DEBUG_UART_RTS
+#define CYBSP_DEBUG_UART_CTS (P13_3)
+#define CYBSP_D3 CYBSP_DEBUG_UART_CTS
+#define CYBSP_D4 (P13_4)
+#define CYBSP_D5 (P13_5)
+#define CYBSP_D6 (P13_6)
+#define CYBSP_D7 (P13_7)
+#define CYBSP_A0 (P14_0)
+#define CYBSP_A1 (P14_1)
+#define CYBSP_A2 (P14_2)
+#define CYBSP_A3 (P14_3)
+#define CYBSP_A4 (P14_4)
+#define CYBSP_A5 (P14_5)
+#define CYBSP_A6 (P14_6)
+#define CYBSP_A7 (P14_7)
+#define CYBSP_I2C_SDA (P15_1)
+#define CYBSP_I2C_SCL (P15_2)
+#define CYBSP_USER_LED (P16_1)
+#define CYBSP_USER_LED1 CYBSP_USER_LED
+#define LED1 CYBSP_USER_LED
+#define CYBSP_USER_LED2 (P16_2)
+#define LED2 CYBSP_USER_LED2
+#define CYBSP_USER_LED3 (P16_3)
+#define LED3 CYBSP_USER_LED3
+#define CYBSP_USER_BTN2 (P17_3)
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 #define CYBSP_WCO_IN_ENABLED 1U
 #define CYBSP_WCO_IN_PORT GPIO_PRT21
 #define CYBSP_WCO_IN_PORT_NUM 21U
@@ -104,13 +110,15 @@
 #endif
 #define CYBSP_WCO_IN_HSIOM ioss_0_port_21_pin_0_HSIOM
 #define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_21_IRQn
-#if defined (CY_USING_HAL)
-    #define CYBSP_WCO_IN_HAL_PORT_PIN P21_0
-    #define CYBSP_WCO_IN P21_0
-    #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define CYBSP_WCO_IN_HAL_PORT_PIN P21_0
+#define CYBSP_WCO_IN P21_0
+#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 #define CYBSP_WCO_OUT_ENABLED 1U
 #define CYBSP_WCO_OUT_PORT GPIO_PRT21
 #define CYBSP_WCO_OUT_PORT_NUM 21U
@@ -123,13 +131,15 @@
 #endif
 #define CYBSP_WCO_OUT_HSIOM ioss_0_port_21_pin_1_HSIOM
 #define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_21_IRQn
-#if defined (CY_USING_HAL)
-    #define CYBSP_WCO_OUT_HAL_PORT_PIN P21_1
-    #define CYBSP_WCO_OUT P21_1
-    #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define CYBSP_WCO_OUT_HAL_PORT_PIN P21_1
+#define CYBSP_WCO_OUT P21_1
+#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 #define CYBSP_ECO_IN_ENABLED 1U
 #define CYBSP_ECO_IN_PORT GPIO_PRT21
 #define CYBSP_ECO_IN_PORT_NUM 21U
@@ -142,13 +152,15 @@
 #endif
 #define CYBSP_ECO_IN_HSIOM ioss_0_port_21_pin_2_HSIOM
 #define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_21_IRQn
-#if defined (CY_USING_HAL)
-    #define CYBSP_ECO_IN_HAL_PORT_PIN P21_2
-    #define CYBSP_ECO_IN P21_2
-    #define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define CYBSP_ECO_IN_HAL_PORT_PIN P21_2
+#define CYBSP_ECO_IN P21_2
+#define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 #define CYBSP_ECO_OUT_ENABLED 1U
 #define CYBSP_ECO_OUT_PORT GPIO_PRT21
 #define CYBSP_ECO_OUT_PORT_NUM 21U
@@ -161,20 +173,22 @@
 #endif
 #define CYBSP_ECO_OUT_HSIOM ioss_0_port_21_pin_3_HSIOM
 #define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_21_IRQn
-#if defined (CY_USING_HAL)
-    #define CYBSP_ECO_OUT_HAL_PORT_PIN P21_3
-    #define CYBSP_ECO_OUT P21_3
-    #define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-    #define CYBSP_USER_BTN1 (P21_4)
-    #define CYBSP_USER_BTN CYBSP_USER_BTN1
-    #define CYBSP_TRACE_DATA0 (P21_5)
-    #define CYBSP_TRACE_DATA1 (P22_1)
-    #define CYBSP_TRACE_DATA2 (P22_2)
-    #define CYBSP_TRACE_DATA3 (P22_3)
-    #define CYBSP_TRACE_CLK (P22_4)
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define CYBSP_ECO_OUT_HAL_PORT_PIN P21_3
+#define CYBSP_ECO_OUT P21_3
+#define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+#define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#define CYBSP_USER_BTN1 (P21_4)
+#define CYBSP_USER_BTN CYBSP_USER_BTN1
+#define CYBSP_TRACE_DATA0 (P21_5)
+#define CYBSP_TRACE_DATA1 (P22_1)
+#define CYBSP_TRACE_DATA2 (P22_2)
+#define CYBSP_TRACE_DATA3 (P22_3)
+#define CYBSP_TRACE_CLK (P22_4)
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 #define CYBSP_SWO_ENABLED 1U
 #define CYBSP_SWO_PORT GPIO_PRT23
 #define CYBSP_SWO_PORT_NUM 23U
@@ -187,13 +201,15 @@
 #endif
 #define CYBSP_SWO_HSIOM ioss_0_port_23_pin_4_HSIOM
 #define CYBSP_SWO_IRQ ioss_interrupts_gpio_23_IRQn
-#if defined (CY_USING_HAL)
-    #define CYBSP_SWO_HAL_PORT_PIN P23_4
-    #define CYBSP_SWO P23_4
-    #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
-    #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define CYBSP_SWO_HAL_PORT_PIN P23_4
+#define CYBSP_SWO P23_4
+#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 #define CYBSP_SWDCK_ENABLED 1U
 #define CYBSP_SWDCK_PORT GPIO_PRT23
 #define CYBSP_SWDCK_PORT_NUM 23U
@@ -206,13 +222,15 @@
 #endif
 #define CYBSP_SWDCK_HSIOM ioss_0_port_23_pin_5_HSIOM
 #define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_23_IRQn
-#if defined (CY_USING_HAL)
-    #define CYBSP_SWDCK_HAL_PORT_PIN P23_5
-    #define CYBSP_SWDCK P23_5
-    #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
-    #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define CYBSP_SWDCK_HAL_PORT_PIN P23_5
+#define CYBSP_SWDCK P23_5
+#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 #define CYBSP_SWDIO_ENABLED 1U
 #define CYBSP_SWDIO_PORT GPIO_PRT23
 #define CYBSP_SWDIO_PORT_NUM 23U
@@ -225,72 +243,85 @@
 #endif
 #define CYBSP_SWDIO_HSIOM ioss_0_port_23_pin_6_HSIOM
 #define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_23_IRQn
-#if defined (CY_USING_HAL)
-    #define CYBSP_SWDIO_HAL_PORT_PIN P23_6
-    #define CYBSP_SWDIO P23_6
-    #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
-    #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
-    #define CYBSP_WIFI_SDIO_CLK (P24_2)
-    #define CYBSP_WIFI_SDIO_CMD (P24_3)
-    #define CYBSP_WIFI_SDIO_D0 (P25_0)
-    #define CYBSP_WIFI_SDIO_D1 (P25_1)
-    #define CYBSP_WIFI_SDIO_D2 (P25_2)
-    #define CYBSP_WIFI_SDIO_D3 (P25_3)
-    #define CYBSP_WIFI_HOST_WAKE (P25_4)
-    #define CYBSP_WIFI_WL_REG_ON (P25_6)
-    #define CYBSP_BT_UART_RX (P32_0)
-    #define CYBSP_BT_UART_TX (P32_1)
-    #define CYBSP_BT_UART_RTS (P32_2)
-    #define CYBSP_BT_UART_CTS (P32_3)
-    #define CYBSP_BT_HOST_WAKE (P32_4)
-    #define CYBSP_BT_DEVICE_WAKE (P32_5)
-    #define CYBSP_BT_POWER (P32_6)
-    #define CYBSP_QSPI_SCK (P6_3)
-    #define CYBSP_QSPI_SS (P6_5)
-    #define CYBSP_QSPI_FLASH_SSEL CYBSP_QSPI_SS
-    #define CYBSP_POT (P6_6)
-    #define CYBSP_QSPI_D0 (P7_1)
-    #define CYBSP_QSPI_D1 (P7_2)
-    #define CYBSP_QSPI_D2 (P7_3)
-    #define CYBSP_QSPI_D3 (P7_4)
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define CYBSP_SWDIO_HAL_PORT_PIN P23_6
+#define CYBSP_SWDIO P23_6
+#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#define CYBSP_WIFI_SDIO_CLK (P24_2)
+#define CYBSP_WIFI_SDIO_CMD (P24_3)
+#define CYBSP_WIFI_SDIO_D0 (P25_0)
+#define CYBSP_WIFI_SDIO_D1 (P25_1)
+#define CYBSP_WIFI_SDIO_D2 (P25_2)
+#define CYBSP_WIFI_SDIO_D3 (P25_3)
+#define CYBSP_WIFI_HOST_WAKE (P25_4)
+#define CYBSP_WIFI_WL_REG_ON (P25_6)
+#define CYBSP_BT_UART_RX (P32_0)
+#define CYBSP_BT_UART_TX (P32_1)
+#define CYBSP_BT_UART_RTS (P32_2)
+#define CYBSP_BT_UART_CTS (P32_3)
+#define CYBSP_BT_HOST_WAKE (P32_4)
+#define CYBSP_BT_DEVICE_WAKE (P32_5)
+#define CYBSP_BT_POWER (P32_6)
+#define CYBSP_QSPI_SCK (P6_3)
+#define CYBSP_QSPI_SS (P6_5)
+#define CYBSP_QSPI_FLASH_SSEL CYBSP_QSPI_SS
+#define CYBSP_POT (P6_6)
+#define CYBSP_QSPI_D0 (P7_1)
+#define CYBSP_QSPI_D1 (P7_2)
+#define CYBSP_QSPI_D2 (P7_3)
+#define CYBSP_QSPI_D3 (P7_4)
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
 
 extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj;
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj;
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj;
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj;
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_SWO_obj;
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
 extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
-#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
 
 void init_cycfg_pins(void);
 void reserve_cycfg_pins(void);
 
 #if defined(__cplusplus)
 }
-#endif
-
+#endif /* defined(__cplusplus) */
 
 #endif /* CYCFG_PINS_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
index f877724..9ab1bcf 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
@@ -1,35 +1,73 @@
 /*******************************************************************************
-* File Name: cycfg_qspi_memslot.c
-*
-* Description:
-* Provides definitions of the SMIF-driver memory configuration.
-* This file was automatically generated and should not be modified.
-* QSPI Configurator 4.0.0.974
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_qspi_memslot.c
+ *
+ * Description:
+ * Provides definitions of the SMIF-driver memory configuration.
+ * This file was automatically generated and should not be modified.
+ * QSPI Configurator 4.30.0.1865
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #include "cycfg_qspi_memslot.h"
 
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readCmd =
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x00U,
+    .command = 0xECU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_QUAD,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0x01U,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 4U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_PRESENT_1BYTE,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x06U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -60,14 +98,14 @@
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR
+    .cmdRate = CY_SMIF_SDR,
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeEnCmd =
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x00U,
+    .command = 0x04U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -98,14 +136,14 @@
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR
+    .cmdRate = CY_SMIF_SDR,
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeDisCmd =
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x00U,
+    .command = 0xDCU,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -136,14 +174,14 @@
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR
+    .cmdRate = CY_SMIF_SDR,
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_eraseCmd =
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x00U,
+    .command = 0x60U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -174,14 +212,52 @@
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR
+    .cmdRate = CY_SMIF_SDR,
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_chipEraseCmd =
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x00U,
+    .command = 0x34U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x35U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -212,14 +288,14 @@
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR
+    .cmdRate = CY_SMIF_SDR,
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_programCmd =
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x00U,
+    .command = 0x05U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -250,14 +326,14 @@
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR
+    .cmdRate = CY_SMIF_SDR,
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegQeCmd =
+cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
 {
     /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x00U,
+    .command = 0x01U,
     /* The width of the command transfer. */
     .cmdWidth = CY_SMIF_WIDTH_SINGLE,
     /* The width of the address transfer. */
@@ -288,183 +364,86 @@
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR
+    .cmdRate = CY_SMIF_SDR,
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegWipCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x00U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE,
-#if (CY_IP_MXSMIF_VERSION >= 2)
-    /* The Data rate of data */
-    .dataRate = CY_SMIF_SDR,
-    /* This specifies the presence of the dummy field */
-    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
-    /* This specifies the presence of the mode field */
-    .modePresence = CY_SMIF_NOT_PRESENT,
-    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
-    .modeH = 0x00,
-    /* The Data rate of mode */
-    .modeRate = CY_SMIF_SDR,
-    /* The Data rate of address */
-    .addrRate = CY_SMIF_SDR,
-    /* This specifies the width of the command field */
-    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
-    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
-    .commandH = 0x00,
-    /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR
-#endif /* CY_IP_MXSMIF_VERSION */
-};
-
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeStsRegQeCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x00U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE,
-#if (CY_IP_MXSMIF_VERSION >= 2)
-    /* The Data rate of data */
-    .dataRate = CY_SMIF_SDR,
-    /* This specifies the presence of the dummy field */
-    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
-    /* This specifies the presence of the mode field */
-    .modePresence = CY_SMIF_NOT_PRESENT,
-    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
-    .modeH = 0x00,
-    /* The Data rate of mode */
-    .modeRate = CY_SMIF_SDR,
-    /* The Data rate of address */
-    .addrRate = CY_SMIF_SDR,
-    /* This specifies the width of the command field */
-    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
-    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
-    .commandH = 0x00,
-    /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR
-#endif /* CY_IP_MXSMIF_VERSION */
-};
-
-cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readSfdpCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x5AU,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 8U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
-static cy_stc_smif_hybrid_region_info_t SFDP_SlaveSlot_0_regionInfoStorage[16];
-
-static cy_stc_smif_hybrid_region_info_t *SFDP_SlaveSlot_0_regionInfo[16] = {
-    &SFDP_SlaveSlot_0_regionInfoStorage[0],
-    &SFDP_SlaveSlot_0_regionInfoStorage[1],
-    &SFDP_SlaveSlot_0_regionInfoStorage[2],
-    &SFDP_SlaveSlot_0_regionInfoStorage[3],
-    &SFDP_SlaveSlot_0_regionInfoStorage[4],
-    &SFDP_SlaveSlot_0_regionInfoStorage[5],
-    &SFDP_SlaveSlot_0_regionInfoStorage[6],
-    &SFDP_SlaveSlot_0_regionInfoStorage[7],
-    &SFDP_SlaveSlot_0_regionInfoStorage[8],
-    &SFDP_SlaveSlot_0_regionInfoStorage[9],
-    &SFDP_SlaveSlot_0_regionInfoStorage[10],
-    &SFDP_SlaveSlot_0_regionInfoStorage[11],
-    &SFDP_SlaveSlot_0_regionInfoStorage[12],
-    &SFDP_SlaveSlot_0_regionInfoStorage[13],
-    &SFDP_SlaveSlot_0_regionInfoStorage[14],
-    &SFDP_SlaveSlot_0_regionInfoStorage[15]
-};
-#endif
-
-cy_stc_smif_mem_device_cfg_t deviceCfg_SFDP_SlaveSlot_0 =
+cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
 {
     /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x03U,
+    .numOfAddrBytes = 0x04U,
     /* The size of the memory. */
-    .memSize = 0x0000100U,
+    .memSize = 0x04000000U,
     /* Specifies the Read command. */
-    .readCmd = &SFDP_SlaveSlot_0_readCmd,
+    .readCmd = &S25FL512S_SlaveSlot_0_readCmd,
     /* Specifies the Write Enable command. */
-    .writeEnCmd = &SFDP_SlaveSlot_0_writeEnCmd,
+    .writeEnCmd = &S25FL512S_SlaveSlot_0_writeEnCmd,
     /* Specifies the Write Disable command. */
-    .writeDisCmd = &SFDP_SlaveSlot_0_writeDisCmd,
+    .writeDisCmd = &S25FL512S_SlaveSlot_0_writeDisCmd,
     /* Specifies the Erase command. */
-    .eraseCmd = &SFDP_SlaveSlot_0_eraseCmd,
+    .eraseCmd = &S25FL512S_SlaveSlot_0_eraseCmd,
     /* Specifies the sector size of each erase. */
-    .eraseSize = 0x0001000U,
+    .eraseSize = 0x00040000U,
     /* Specifies the Chip Erase command. */
-    .chipEraseCmd = &SFDP_SlaveSlot_0_chipEraseCmd,
+    .chipEraseCmd = &S25FL512S_SlaveSlot_0_chipEraseCmd,
     /* Specifies the Program command. */
-    .programCmd = &SFDP_SlaveSlot_0_programCmd,
+    .programCmd = &S25FL512S_SlaveSlot_0_programCmd,
     /* Specifies the page size for programming. */
-    .programSize = 0x0000100U,
+    .programSize = 0x00000200U,
     /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = &SFDP_SlaveSlot_0_readStsRegQeCmd,
+    .readStsRegQeCmd = &S25FL512S_SlaveSlot_0_readStsRegQeCmd,
     /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = &SFDP_SlaveSlot_0_readStsRegWipCmd,
-    /* Specifies the read SFDP command */
-    .readSfdpCmd = &SFDP_SlaveSlot_0_readSfdpCmd,
+    .readStsRegWipCmd = &S25FL512S_SlaveSlot_0_readStsRegWipCmd,
     /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = &SFDP_SlaveSlot_0_writeStsRegQeCmd,
+    .writeStsRegQeCmd = &S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
     /* The mask for the status register. */
-    .stsRegBusyMask = 0x00U,
+    .stsRegBusyMask = 0x01U,
     /* The mask for the status register. */
-    .stsRegQuadEnableMask = 0x00U,
+    .stsRegQuadEnableMask = 0x02U,
     /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 1U,
+    .eraseTime = 2600U,
     /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 16U,
+    .chipEraseTime = 460000U,
     /* The max time for the page-program cycle-time in us. */
-    .programTime = 8U,
+    .programTime = 1300U,
 #if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
     /* Points to NULL or to structure with info about sectors for hybrid memory. */
     .hybridRegionCount = 0U,
-    .hybridRegionInfo = SFDP_SlaveSlot_0_regionInfo
+    .hybridRegionInfo = 0,
+#endif
+    /* Specifies the command to read variable latency cycles configuration register */
+    .readLatencyCmd = 0,
+    /* Specifies the command to write variable latency cycles configuration register */
+    .writeLatencyCmd = 0,
+    /* Specifies the address for variable latency cycle address */
+    .latencyCyclesRegAddr = 0x00U,
+    /* Specifies variable latency cycles Mask */
+    .latencyCyclesMask = 0x00U,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* Specifies data for memory with hybrid sectors */
+    .octalDDREnableSeq = 0,
+    /* Specifies the command to read the OE-containing status register. */
+    .readStsRegOeCmd = 0,
+    /* Specifies the command to write the OE-containing status register. */
+    .writeStsRegOeCmd = 0,
+    /* QE mask for the status registers */
+    .stsRegOctalEnableMask = 0x00U,
+    /* Octal enable register address */
+    .octalEnableRegAddr = 0x00U,
+    /* Frequency of operation used in Octal mode */
+    .freq_of_operation = CY_SMIF_100MHZ_OPERATION,
 #endif
 };
 
-const cy_stc_smif_mem_config_t SFDP_SlaveSlot_0 =
+cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
 {
     /* Determines the slot number where the memory device is placed. */
     .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
     /* Flags. */
 #if (CY_IP_MXSMIF_VERSION >= 2)
-    .flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_CRYPTO_EN | CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MERGE_ENABLE,
+    .flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_CRYPTO_EN | CY_SMIF_FLAG_MERGE_ENABLE,
 #else
-    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_CRYPTO_EN | CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MERGE_ENABLE,
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_CRYPTO_EN | CY_SMIF_FLAG_MERGE_ENABLE,
 #endif /* CY_IP_MXSMIF_VERSION */
     /* The data-line selection options for a slave device. */
     .dataSelect = CY_SMIF_DATA_SEL0,
@@ -478,23 +457,23 @@
     Valid when the memory mapped mode is enabled. */
     .dualQuadSlots = 0,
     /* The configuration of the device. */
-    .deviceCfg = &deviceCfg_SFDP_SlaveSlot_0,
+    .deviceCfg = &deviceCfg_S25FL512S_SlaveSlot_0,
 #if (CY_IP_MXSMIF_VERSION >= 2)
     /** Continous transfer merge timeout.
      * After this period the memory device is deselected. A later transfer, even from a
      * continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
      * This configuration parameter is available for CAT1B devices. */
-    .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_256_CYCLES
+    .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_256_CYCLES,
 #else
 #error Features used by this file require CY_IP_MXSMIF_VERSION >= 2.
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
-const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM] = {
-   &SFDP_SlaveSlot_0
+cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM] = {
+   &S25FL512S_SlaveSlot_0,
 };
 
-const cy_stc_smif_block_config_t smifBlockConfig =
+cy_stc_smif_block_config_t smifBlockConfig =
 {
     /* The number of SMIF memories defined. */
     .memCount = CY_SMIF_DEVICE_NUM,
@@ -503,5 +482,5 @@
     /* The version of the SMIF driver. */
     .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
     /* The version of the SMIF driver. */
-    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+    .minorVersion = CY_SMIF_DRV_VERSION_MINOR,
 };
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
index d9b08eb..7507b44 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
@@ -1,34 +1,34 @@
 /*******************************************************************************
-* File Name: cycfg_qspi_memslot.h
-*
-* Description:
-* Provides declarations of the SMIF-driver memory configuration.
-* This file was automatically generated and should not be modified.
-* QSPI Configurator 4.0.0.974
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_qspi_memslot.h
+ *
+ * Description:
+ * Provides declarations of the SMIF-driver memory configuration.
+ * This file was automatically generated and should not be modified.
+ * QSPI Configurator 4.30.0.1865
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #ifndef CYCFG_QSPI_MEMSLOT_H
 #define CYCFG_QSPI_MEMSLOT_H
 #include "cy_smif_memslot.h"
 
-#define CY_SMIF_CFG_TOOL_VERSION           (400)
+#define CY_SMIF_CFG_TOOL_VERSION           (430)
 
 /* Supported QSPI Driver version */
 #define CY_SMIF_DRV_VERSION_REQUIRED       (100)
@@ -42,39 +42,28 @@
    #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
 #endif
 
+typedef cy_stc_smif_mem_config_t cy_serial_flash_mem_config_t;
+typedef cy_stc_smif_block_config_t cy_serial_flash_block_config_t;
+
 #define CY_SMIF_DEVICE_NUM 1
 
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readCmd;
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeEnCmd;
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeDisCmd;
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_eraseCmd;
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_chipEraseCmd;
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_programCmd;
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegQeCmd;
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegWipCmd;
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeStsRegQeCmd;
-extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readSfdpCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
+extern cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
 
-extern cy_stc_smif_mem_device_cfg_t deviceCfg_SFDP_SlaveSlot_0;
+extern cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
 
-extern const cy_stc_smif_mem_config_t SFDP_SlaveSlot_0;
+extern cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
 
-#define Auto_detect_SFDP_SlaveSlot_0_readCmd SFDP_SlaveSlot_0_readCmd
-#define Auto_detect_SFDP_SlaveSlot_0_writeEnCmd SFDP_SlaveSlot_0_writeEnCmd
-#define Auto_detect_SFDP_SlaveSlot_0_writeDisCmd SFDP_SlaveSlot_0_writeDisCmd
-#define Auto_detect_SFDP_SlaveSlot_0_eraseCmd SFDP_SlaveSlot_0_eraseCmd
-#define Auto_detect_SFDP_SlaveSlot_0_chipEraseCmd SFDP_SlaveSlot_0_chipEraseCmd
-#define Auto_detect_SFDP_SlaveSlot_0_programCmd SFDP_SlaveSlot_0_programCmd
-#define Auto_detect_SFDP_SlaveSlot_0_readStsRegQeCmd SFDP_SlaveSlot_0_readStsRegQeCmd
-#define Auto_detect_SFDP_SlaveSlot_0_readStsRegWipCmd SFDP_SlaveSlot_0_readStsRegWipCmd
-#define Auto_detect_SFDP_SlaveSlot_0_writeStsRegQeCmd SFDP_SlaveSlot_0_writeStsRegQeCmd
-#define Auto_detect_SFDP_SlaveSlot_0_readSfdpCmd SFDP_SlaveSlot_0_readSfdpCmd
-#define deviceCfg_Auto_detect_SFDP_SlaveSlot_0 deviceCfg_SFDP_SlaveSlot_0
-#define Auto_detect_SFDP_SlaveSlot_0 SFDP_SlaveSlot_0
+extern cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
 
-extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
-
-extern const cy_stc_smif_block_config_t smifBlockConfig;
+extern cy_stc_smif_block_config_t smifBlockConfig;
 
 
 #endif /*CYCFG_QSPI_MEMSLOT_H*/
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
index 2e8a2ce..0932043 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
@@ -1,50 +1,52 @@
 /*******************************************************************************
-* File Name: cycfg_routing.h
-*
-* Description:
-* Establishes all necessary connections between hardware elements.
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_routing.h
+ *
+ * Description:
+ * Establishes all necessary connections between hardware elements.
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #if !defined(CYCFG_ROUTING_H)
 #define CYCFG_ROUTING_H
 
+#include "cycfg_notices.h"
+
 #if defined(__cplusplus)
 extern "C" {
-#endif
-
-#include "cycfg_notices.h"
-static inline void init_cycfg_routing(void) {}
+#endif /* defined(__cplusplus) */
 
 #define ioss_0_port_21_pin_0_ANALOG P21_0_SRSS_WCO_IN
 #define ioss_0_port_21_pin_1_ANALOG P21_1_SRSS_WCO_OUT
+#define ioss_0_port_21_pin_2_ANALOG P21_2_SRSS_ECO_IN
+#define ioss_0_port_21_pin_3_ANALOG P21_3_SRSS_ECO_OUT
 #define ioss_0_port_23_pin_4_HSIOM P23_4_CPUSS_SWJ_SWO_TDO
 #define ioss_0_port_23_pin_5_HSIOM P23_5_CPUSS_SWJ_SWCLK_TCLK
 #define ioss_0_port_23_pin_6_HSIOM P23_6_CPUSS_SWJ_SWDIO_TMS
 
+static inline void init_cycfg_routing(void) {}
+
 #if defined(__cplusplus)
 }
-#endif
-
+#endif /* defined(__cplusplus) */
 
 #endif /* CYCFG_ROUTING_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
index ca14ba0..5debda7 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
@@ -1,30 +1,30 @@
 /*******************************************************************************
-* File Name: cycfg_system.c
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_system.c
+ *
+ * Description:
+ * System configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #include "cycfg_system.h"
 
@@ -33,54 +33,75 @@
 #define CY_CFG_SYSCLK_PLL_ERROR 3
 #define CY_CFG_SYSCLK_FLL_ERROR 4
 #define CY_CFG_SYSCLK_WCO_ERROR 5
+
+#if  (CY_CPU_CORTEX_M7)
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_IMO
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_INTERVAL 0
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_FREQUENCY 8000000
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS ((0)/1000000.0)*8000000
+#endif /*  (CY_CPU_CORTEX_M7) */
+
 #define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
 #define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
+#define CY_CFG_SYSCLK_ECO_ENABLED 1
+#define CY_CFG_SYSCLK_ECO_FREQ 16000000UL
+#define CY_CFG_SYSCLK_ECO_GPIO_IN_PRT GPIO_PRT21
+#define CY_CFG_SYSCLK_ECO_GPIO_IN_PIN 2
+#define CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT GPIO_PRT21
+#define CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN 3
+#define CY_CFG_SYSCLK_ECO_CLOAD 10UL
+#define CY_CFG_SYSCLK_ECO_ESR 150UL
+#define CY_CFG_SYSCLK_ECO_DRIVE_LEVEL 100UL
 #define CY_CFG_SYSCLK_CLKFAST_0_ENABLED 1
 #define CY_CFG_SYSCLK_CLKFAST_0_INT_DIVIDER 0
 #define CY_CFG_SYSCLK_CLKFAST_0_FRAC_DIVIDER 0
+#define CY_CFG_SYSCLK_CLKFAST_1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_1_INT_DIVIDER 0
+#define CY_CFG_SYSCLK_CLKFAST_1_FRAC_DIVIDER 0
 #define CY_CFG_SYSCLK_FLL_ENABLED 1
 #define CY_CFG_SYSCLK_FLL_MULT 500U
 #define CY_CFG_SYSCLK_FLL_REFDIV 40U
-#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE2
+#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4
 #define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true
-#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U
+#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 2U
 #define CY_CFG_SYSCLK_FLL_IGAIN 9U
-#define CY_CFG_SYSCLK_FLL_PGAIN 0U
-#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U
+#define CY_CFG_SYSCLK_FLL_PGAIN 5U
+#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 16U
 #define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
-#define CY_CFG_SYSCLK_FLL_CCO_FREQ 235U
-#define CY_CFG_SYSCLK_FLL_OUT_FREQ 50000000
+#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U
+#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000
 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
 #define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 50UL
-#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 200UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH3
 #define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
 #define CY_CFG_SYSCLK_CLKHF1_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 250UL
+#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 350UL
 #define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
 #define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
 #define CY_CFG_SYSCLK_CLKHF2_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 196UL
-#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
+#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4
 #define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 144UL
+#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
 #define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH3
 #define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4
+#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
+#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 125UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
 #define CY_CFG_SYSCLK_CLKHF5_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF5_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ 8UL
-#define CY_CFG_SYSCLK_CLKHF5_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH5
+#define CY_CFG_SYSCLK_CLKHF5_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
+#define CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ 125UL
+#define CY_CFG_SYSCLK_CLKHF5_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
 #define CY_CFG_SYSCLK_CLKHF6_ENABLED 1
 #define CY_CFG_SYSCLK_CLKHF6_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF6_FREQ_MHZ 8UL
-#define CY_CFG_SYSCLK_CLKHF6_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH5
+#define CY_CFG_SYSCLK_CLKHF6_FREQ_MHZ 200UL
+#define CY_CFG_SYSCLK_CLKHF6_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH3
 #define CY_CFG_SYSCLK_CLKHF7_ENABLED 1
 #define CY_CFG_SYSCLK_CLKHF7_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF7_FREQ_MHZ 8UL
+#define CY_CFG_SYSCLK_CLKHF7_FREQ_MHZ 0UL
 #define CY_CFG_SYSCLK_CLKHF7_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH5
 #define CY_CFG_SYSCLK_ILO0_ENABLED 1
 #define CY_CFG_SYSCLK_ILO0_HIBERNATE true
@@ -88,63 +109,65 @@
 #define CY_CFG_SYSCLK_ILO1_HIBERNATE true
 #define CY_CFG_SYSCLK_IMO_ENABLED 1
 #define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_CLKMEM_ENABLED 1
+#define CY_CFG_SYSCLK_CLKMEM_DIVIDER 0
 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 1UL
 #define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 1UL
 #define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 1UL
 #define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 1UL
 #define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_ECO
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 1UL
 #define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_ILO0
+#define CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM 6UL
 #define CY_CFG_SYSCLK_CLKPATH6_ENABLED 1
 #define CY_CFG_SYSCLK_CLKPATH6_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
 #define CY_CFG_SYSCLK_CLKPATH6_SOURCE_NUM 0UL
-#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0
 #define CY_CFG_SYSCLK_PLL0_ENABLED 1
-#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 62
+#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 43
 #define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1
 #define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 2
-#define CY_CFG_SYSCLK_PLL0_FRAC_DIV 8388608
+#define CY_CFG_SYSCLK_PLL0_FRAC_DIV 12582912
 #define CY_CFG_SYSCLK_PLL0_FRAC_DITHER_EN false
 #define CY_CFG_SYSCLK_PLL0_FRAC_EN true
 #define CY_CFG_SYSCLK_PLL0_LF_MODE false
 #define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
-#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 250000000
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 350000000
 #define CY_CFG_SYSCLK_PLL1_ENABLED 1
-#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 73
+#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 31
 #define CY_CFG_SYSCLK_PLL1_REFERENCE_DIV 1
-#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 3
-#define CY_CFG_SYSCLK_PLL1_FRAC_DIV 8388608
+#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 2
+#define CY_CFG_SYSCLK_PLL1_FRAC_DIV 4194304
 #define CY_CFG_SYSCLK_PLL1_FRAC_DITHER_EN false
 #define CY_CFG_SYSCLK_PLL1_FRAC_EN true
 #define CY_CFG_SYSCLK_PLL1_LF_MODE false
 #define CY_CFG_SYSCLK_PLL1_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
-#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 196000000
+#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 250000000
 #define CY_CFG_SYSCLK_PLL2_ENABLED 1
-#define CY_CFG_SYSCLK_PLL2_FEEDBACK_DIV 36
-#define CY_CFG_SYSCLK_PLL2_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL2_FEEDBACK_DIV 50
+#define CY_CFG_SYSCLK_PLL2_REFERENCE_DIV 2
 #define CY_CFG_SYSCLK_PLL2_OUTPUT_DIV 2
 #define CY_CFG_SYSCLK_PLL2_LF_MODE false
 #define CY_CFG_SYSCLK_PLL2_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
-#define CY_CFG_SYSCLK_PLL2_OUTPUT_FREQ 144000000
+#define CY_CFG_SYSCLK_PLL2_OUTPUT_FREQ 200000000
 #define CY_CFG_SYSCLK_PLL3_ENABLED 1
 #define CY_CFG_SYSCLK_PLL3_FEEDBACK_DIV 25
-#define CY_CFG_SYSCLK_PLL3_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL3_REFERENCE_DIV 2
 #define CY_CFG_SYSCLK_PLL3_OUTPUT_DIV 2
 #define CY_CFG_SYSCLK_PLL3_LF_MODE false
 #define CY_CFG_SYSCLK_PLL3_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
 #define CY_CFG_SYSCLK_PLL3_OUTPUT_FREQ 100000000
+#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
+#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 1
 #define CY_CFG_SYSCLK_WCO_ENABLED 1
 #define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT21
 #define CY_CFG_SYSCLK_WCO_IN_PIN 0U
@@ -154,169 +177,205 @@
 #define CY_CFG_PWR_ENABLED 1
 #define CY_CFG_PWR_INIT 1
 #define CY_CFG_PWR_VBACKUP_USING_VDDD 1
-#define CY_CFG_PWR_REGULATOR_MODE_MIN false
+#define CY_CFG_PWR_REGULATOR_MODE_MIN 0
 #define CY_CFG_PWR_USING_ULP 0
 
 #if (!defined(CY_DEVICE_SECURE))
-    static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = 
-    {
-        .fllMult = 500U,
-        .refDiv = 40U,
-        .ccoRange = CY_SYSCLK_FLL_CCO_RANGE2,
-        .enableOutputDiv = true,
-        .lockTolerance = 10U,
-        .igain = 9U,
-        .pgain = 0U,
-        .settlingCount = 8U,
-        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
-        .cco_Freq = 235U,
-    };
-#endif //(!defined(CY_DEVICE_SECURE))
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
-    {
-        .type = CYHAL_RSC_CLKPATH,
-        .block_num = 0U,
-        .channel_num = 0U,
-    };
-    const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
-    {
-        .type = CYHAL_RSC_CLKPATH,
-        .block_num = 1U,
-        .channel_num = 0U,
-    };
-    const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
-    {
-        .type = CYHAL_RSC_CLKPATH,
-        .block_num = 2U,
-        .channel_num = 0U,
-    };
-    const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = 
-    {
-        .type = CYHAL_RSC_CLKPATH,
-        .block_num = 3U,
-        .channel_num = 0U,
-    };
-    const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = 
-    {
-        .type = CYHAL_RSC_CLKPATH,
-        .block_num = 4U,
-        .channel_num = 0U,
-    };
-    const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = 
-    {
-        .type = CYHAL_RSC_CLKPATH,
-        .block_num = 5U,
-        .channel_num = 0U,
-    };
-    const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj = 
-    {
-        .type = CYHAL_RSC_CLKPATH,
-        .block_num = 6U,
-        .channel_num = 0U,
-    };
-#endif //defined (CY_USING_HAL)
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_0_pllConfig = 
+static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
 {
-    .feedbackDiv = 62,
+    .fllMult = 500U,
+    .refDiv = 40U,
+    .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
+    .enableOutputDiv = true,
+    .lockTolerance = 2U,
+    .igain = 9U,
+    .pgain = 5U,
+    .settlingCount = 16U,
+    .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+    .cco_Freq = 355U,
+};
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
+#if defined (CY_USING_HAL)
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
+{
+    .type = CYHAL_RSC_CLKPATH,
+    .block_num = 0U,
+    .channel_num = 0U,
+};
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
+{
+    .type = CYHAL_RSC_CLKPATH,
+    .block_num = 1U,
+    .channel_num = 0U,
+};
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
+{
+    .type = CYHAL_RSC_CLKPATH,
+    .block_num = 2U,
+    .channel_num = 0U,
+};
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
+{
+    .type = CYHAL_RSC_CLKPATH,
+    .block_num = 3U,
+    .channel_num = 0U,
+};
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
+{
+    .type = CYHAL_RSC_CLKPATH,
+    .block_num = 4U,
+    .channel_num = 0U,
+};
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj =
+{
+    .type = CYHAL_RSC_CLKPATH,
+    .block_num = 5U,
+    .channel_num = 0U,
+};
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj =
+{
+    .type = CYHAL_RSC_CLKPATH,
+    .block_num = 6U,
+    .channel_num = 0U,
+};
+#endif /* defined (CY_USING_HAL) */
+
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_0_pllConfig =
+{
+    .feedbackDiv = 43,
     .referenceDiv = 1,
     .outputDiv = 2,
     .lfMode = false,
     .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-    .fracDiv = 8388608,
+    .fracDiv = 12582912,
     .fracDitherEn = false,
     .fracEn = true,
 };
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_1_pllConfig = 
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_1_pllConfig =
 {
-    .feedbackDiv = 73,
+    .feedbackDiv = 31,
     .referenceDiv = 1,
-    .outputDiv = 3,
+    .outputDiv = 2,
     .lfMode = false,
     .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-    .fracDiv = 8388608,
+    .fracDiv = 4194304,
     .fracDitherEn = false,
     .fracEn = true,
 };
+
 #if (!defined(CY_DEVICE_SECURE))
-    static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
-    {
-        .feedbackDiv = 36,
-        .referenceDiv = 1,
-        .outputDiv = 2,
-        .lfMode = false,
-        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-    };
-    static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = 
-    {
-        .feedbackDiv = 25,
-        .referenceDiv = 1,
-        .outputDiv = 2,
-        .lfMode = false,
-        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-    };
-#endif //(!defined(CY_DEVICE_SECURE))
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
+{
+    .feedbackDiv = 50,
+    .referenceDiv = 2,
+    .outputDiv = 2,
+    .lfMode = false,
+    .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
+{
+    .feedbackDiv = 25,
+    .referenceDiv = 2,
+    .outputDiv = 2,
+    .lfMode = false,
+    .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+#endif /* (!defined(CY_DEVICE_SECURE)) */
 
 __WEAK void cycfg_ClockStartupError(uint32_t error)
 {
     (void)error; /* Suppress the compiler warning */
     while(1);
 }
+
 #if !defined (CY_CFG_SYSCLK_ILO0_ENABLED)
-    __STATIC_INLINE void Cy_SysClk_Ilo0DeInit()
+__STATIC_INLINE void Cy_SysClk_Ilo0DeInit()
+{
+    if(Cy_SysPm_IsBgRefCtrl())
     {
-        if(Cy_SysPm_IsBgRefCtrl())
-        {
-            Cy_SysPm_BgRefCtrl(false);
-            Cy_WDT_Unlock();
-            Cy_SysClk_IloSrcDisable(0);
-            Cy_SysClk_IloSrcHibernateOn(0, false);
-            Cy_WDT_Lock();
-            Cy_SysPm_BgRefCtrl(true);
-        }
-        else
-        {
-            Cy_WDT_Unlock();
-            Cy_SysClk_IloSrcDisable(0);
-            Cy_SysClk_IloSrcHibernateOn(0, false);
-            Cy_WDT_Lock();
-        }
+        Cy_SysPm_BgRefCtrl(false);
+        Cy_WDT_Unlock();
+        Cy_SysClk_IloSrcDisable(0);
+        Cy_SysClk_IloSrcHibernateOn(0, false);
+        Cy_WDT_Lock();
+        Cy_SysPm_BgRefCtrl(true);
     }
-#endif //!defined (CY_CFG_SYSCLK_ILO0_ENABLED)
+    else
+    {
+        Cy_WDT_Unlock();
+        Cy_SysClk_IloSrcDisable(0);
+        Cy_SysClk_IloSrcHibernateOn(0, false);
+        Cy_WDT_Lock();
+    }
+}
+#endif /* !defined (CY_CFG_SYSCLK_ILO0_ENABLED) */
+
 #if !defined (CY_CFG_SYSCLK_ILO1_ENABLED)
-    __STATIC_INLINE void Cy_SysClk_Ilo1DeInit()
-    {
-        Cy_SysClk_IloSrcDisable(1);
-        Cy_SysClk_IloSrcHibernateOn(1, false);
-    }
-#endif //!defined (CY_CFG_SYSCLK_ILO1_ENABLED)
+__STATIC_INLINE void Cy_SysClk_Ilo1DeInit()
+{
+    Cy_SysClk_IloSrcDisable(1);
+    Cy_SysClk_IloSrcHibernateOn(1, false);
+}
+#endif /* !defined (CY_CFG_SYSCLK_ILO1_ENABLED) */
+
+#if ((!defined(CY_DEVICE_SECURE)))
+__STATIC_INLINE void Cy_SysClk_FllDeInit()
+{
+    Cy_SysClk_FllDisable();
+}
+#endif /* ((!defined(CY_DEVICE_SECURE))) */
+
+#if  (CY_CPU_CORTEX_M7)
+__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
+{
+    Cy_SysTick_Init(CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE, CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS);
+}
+#endif /*  (CY_CPU_CORTEX_M7) */
+
 #if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_FllDeInit()
+__STATIC_INLINE void Cy_SysClk_ClkBakInit()
+{
+    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+}
+__STATIC_INLINE void Cy_SysClk_EcoInit()
+{
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 2, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 3, CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO);
+    if (CY_SYSCLK_BAD_PARAM == Cy_SysClk_EcoConfigure(CY_CFG_SYSCLK_ECO_FREQ, 17UL, 150UL, 100UL))
     {
-        Cy_SysClk_FllDisable();
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR);
     }
-    __STATIC_INLINE void Cy_SysClk_ClkBakInit()
+    if (CY_SYSCLK_TIMEOUT == Cy_SysClk_EcoEnable(3000UL))
     {
-        Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_ECO_ERROR);
     }
-#endif //(!defined(CY_DEVICE_SECURE))
+}
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
 __STATIC_INLINE void Cy_SysClk_ClkFast_0_Init()
 {
     Cy_SysClk_ClkFastSrcSetDivider(0, CY_CFG_SYSCLK_CLKFAST_0_INT_DIVIDER, CY_CFG_SYSCLK_CLKFAST_0_FRAC_DIVIDER);
 }
+__STATIC_INLINE void Cy_SysClk_ClkFast_1_Init()
+{
+    Cy_SysClk_ClkFastSrcSetDivider(1, CY_CFG_SYSCLK_CLKFAST_1_INT_DIVIDER, CY_CFG_SYSCLK_CLKFAST_1_FRAC_DIVIDER);
+}
+
 #if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_FllInit()
+__STATIC_INLINE void Cy_SysClk_FllInit()
+{
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
     {
-        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
-        {
-            cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-        }
-        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
-        {
-            cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-        }
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
     }
-#endif //(!defined(CY_DEVICE_SECURE))
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+    }
+}
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
 __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
 {
     Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
@@ -340,21 +399,21 @@
 __STATIC_INLINE void Cy_SysClk_ClkHf3Init()
 {
     Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
     Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF3, false);
     Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
 }
 __STATIC_INLINE void Cy_SysClk_ClkHf4Init()
 {
     Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
     Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF4, false);
     Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
 }
 __STATIC_INLINE void Cy_SysClk_ClkHf5Init()
 {
     Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF5, CY_CFG_SYSCLK_CLKHF5_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF5, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF5, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
     Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF5, false);
     Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF5);
 }
@@ -372,59 +431,67 @@
     Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF7, false);
     Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF7);
 }
+
 #if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_Ilo0Init()
-    {
-        /* The WDT is unlocked in the default startup code */
-        Cy_SysClk_IloSrcEnable(0);
-        Cy_SysClk_IloSrcHibernateOn(0, true);
-    }
-    __STATIC_INLINE void Cy_SysClk_Ilo1Init()
-    {
-        /* The WDT is unlocked in the default startup code */
-        Cy_SysClk_IloSrcEnable(1);
-        Cy_SysClk_IloSrcHibernateOn(1, true);
-    }
-#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_Ilo0Init()
+{
+    /* The WDT is unlocked in the default startup code */
+    Cy_SysClk_IloSrcEnable(0);
+    Cy_SysClk_IloSrcHibernateOn(0, true);
+}
+__STATIC_INLINE void Cy_SysClk_Ilo1Init()
+{
+    /* The WDT is unlocked in the default startup code */
+    Cy_SysClk_IloSrcEnable(1);
+    Cy_SysClk_IloSrcHibernateOn(1, true);
+}
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
 __STATIC_INLINE void Cy_SysClk_ClkLfInit()
 {
     /* The WDT is unlocked in the default startup code */
     Cy_SysClk_ClkLfSetSource(CY_CFG_SYSCLK_CLKLF_SOURCE);
 }
+__STATIC_INLINE void Cy_SysClk_ClkMemInit()
+{
+    Cy_SysClk_ClkMemSetDivider(0U);
+}
+
 #if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
-    {
-        Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
-    }
-    __STATIC_INLINE void Cy_SysClk_ClkPath1Init()
-    {
-        Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
-    }
-    __STATIC_INLINE void Cy_SysClk_ClkPath2Init()
-    {
-        Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
-    }
-    __STATIC_INLINE void Cy_SysClk_ClkPath3Init()
-    {
-        Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
-    }
-    __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
-    {
-        Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
-    }
-    __STATIC_INLINE void Cy_SysClk_ClkPath5Init()
-    {
-        Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE);
-    }
-    __STATIC_INLINE void Cy_SysClk_ClkPath6Init()
-    {
-        Cy_SysClk_ClkPathSetSource(6U, CY_CFG_SYSCLK_CLKPATH6_SOURCE);
-    }
-    __STATIC_INLINE void Cy_SysClk_ClkPeriInit()
-    {
-        Cy_SysClk_ClkPeriSetDivider(0U);
-    }
-#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
+{
+    Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
+{
+    Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
+{
+    Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath3Init()
+{
+    Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath4Init()
+{
+    Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath5Init()
+{
+    Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath6Init()
+{
+    Cy_SysClk_ClkPathSetSource(6U, CY_CFG_SYSCLK_CLKPATH6_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
+{
+    Cy_SysClk_ClkPeriSetDivider(1U);
+}
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
 __STATIC_INLINE void Cy_SysClk_Pll0Init()
 {
     Cy_SysClk_PllDisable(SRSS_PLL_400M_0_PATH_NUM);
@@ -477,17 +544,23 @@
         cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
     }
 }
+
 #if (!defined(CY_DEVICE_SECURE))
-    __STATIC_INLINE void Cy_SysClk_WcoInit()
+__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
+{
+    Cy_SysClk_ClkSlowSetDivider(1U);
+}
+__STATIC_INLINE void Cy_SysClk_WcoInit()
+{
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
     {
-        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-        if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
-        {
-            cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
-        }
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
     }
-#endif //(!defined(CY_DEVICE_SECURE))
+}
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
 __STATIC_INLINE void init_cycfg_power(void)
 {
     /* **Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD** */
@@ -502,7 +575,12 @@
         #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
     #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
 
-    /* **System Active Low Power Profile(LPACTIVE/LPSLEEP) Configuration** */
+    /* **REGHC Configuration** */
+    #if (CY_CFG_PWR_REGHC_ENABLED)
+        Cy_SysPm_ReghcConfigure(CY_CFG_PWR_REGHC_MODE, CY_CFG_PWR_REGHC_TRANS_VADJ_VOLT);
+    #endif /* CY_CFG_PWR_REGHC_ENABLED */
+
+     /* **System Active Low Power Profile(LPACTIVE/LPSLEEP) Configuration** */
     #if (CY_CFG_PWR_SYS_LP_PROFILE_MODE)
         Cy_SysPm_SystemLpActiveEnter();
     #endif /* CY_CFG_PWR_SYS_ACTIVE_MODE */
@@ -513,13 +591,12 @@
     #else
         Cy_SysPm_SystemSetNormalRegulatorCurrent();
     #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
-
 }
-
-
 void init_cycfg_system(void)
 {
-    Cy_SysClk_PeriPclkAssignDivider(PCLK_CPUSS_CLOCK_TRACE_IN, CY_SYSCLK_DIV_8_BIT, 2U);
+    Cy_SysClk_PeriPclkAssignDivider(PCLK_CPUSS_CLOCK_TRACE_IN, CY_SYSCLK_DIV_8_BIT, 3U);
+        /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
+        Cy_SysLib_SetWaitStates(false, 150UL);
     #ifdef CY_CFG_PWR_ENABLED
         #ifdef CY_CFG_PWR_INIT
             init_cycfg_power();
@@ -528,7 +605,7 @@
         #endif /* CY_CFG_PWR_INIT */
     #endif /* CY_CFG_PWR_ENABLED */
     
-        /* Disable FLL */
+    /* Disable FLL */
         Cy_SysClk_FllDeInit();
     
     #ifdef CY_CFG_SYSCLK_ILO0_ENABLED
@@ -568,9 +645,9 @@
         Cy_SysClk_AltHfInit();
     #endif
     
-        #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
-            Cy_SysClk_ClkPeriInit();
-        #endif
+    #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+        Cy_SysClk_ClkPeriInit();
+    #endif
     
     /* Configure Path Clocks */
     #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
@@ -742,6 +819,15 @@
         Cy_SysClk_ClkMfInit();
     #endif
     
+    #ifdef CY_CFG_SYSCLK_CLKPWR_ENABLED
+        Cy_SysClk_ClkPwrInit();
+    #endif
+    
+        /* Set accurate flash wait states */
+        #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF1_ENABLED))
+            Cy_SysLib_SetWaitStates(false, CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ);
+        #endif
+    
     #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
         Cy_SysClk_ClkPath0Init();
     #endif
@@ -770,20 +856,25 @@
     
 #if defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
         Cy_SysClk_EcoPrescalerInit();
-#endif //defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
+#endif /* defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED) */
+    #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+        Cy_SysClk_ClkAltSysTickInit();
+    #endif
+    
     /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
     SystemCoreClockUpdate();
+#if defined (CY_USING_HAL)
+    (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+    (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+    (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+    (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+    (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+    (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
+    (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_6_obj);
+#endif /* defined (CY_USING_HAL) */
 }
-
 void reserve_cycfg_system(void)
 {
-#if defined (CY_USING_HAL)
-    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
-    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
-    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
-    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
-    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
-    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
-    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_6_obj);
-#endif //defined (CY_USING_HAL)
+    Cy_SysClk_EcoSetFrequency(CY_CFG_SYSCLK_ECO_FREQ);
+    SystemCoreClockUpdate();
 }
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
index f66c1bb..e214cda 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
@@ -1,30 +1,30 @@
 /*******************************************************************************
-* File Name: cycfg_system.h
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* Configurator Backend 3.0.0
-* device-db 4.2.0.3480
-* mtb-pdl-cat1 3.3.0.21979
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_system.h
+ *
+ * Description:
+ * System configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.20.0
+ * device-db 4.12.0.5709
+ * mtb-pdl-cat1 3.600.0.33254
+ *
+ *******************************************************************************
+ * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
 
 #if !defined(CYCFG_SYSTEM_H)
 #define CYCFG_SYSTEM_H
@@ -32,42 +32,47 @@
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
 #include "cy_wdt.h"
-#if defined (CY_USING_HAL)
-    #include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
+#include "cy_systick.h"
 #include "cy_gpio.h"
 #include "cy_syspm.h"
 
+#if defined (CY_USING_HAL)
+#include "cyhal_hwmgr.h"
+#endif /* defined (CY_USING_HAL) */
+
 #if defined(__cplusplus)
 extern "C" {
-#endif
+#endif /* defined(__cplusplus) */
 
 #define cpuss_0_dap_0_ENABLED 1U
 #define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
 #define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_eco_0_ENABLED 1U
 #define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_1_ENABLED 1U
 #define srss_0_clock_0_fll_0_ENABLED 1U
 #define srss_0_clock_0_hfclk_0_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF0 0UL
-#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 3UL
 #define srss_0_clock_0_hfclk_1_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF1 1UL
 #define CY_CFG_SYSCLK_CLKHF1_CLKPATH_NUM 1UL
 #define srss_0_clock_0_hfclk_2_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF2 2UL
-#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 2UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 4UL
 #define srss_0_clock_0_hfclk_3_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF3 3UL
 #define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 3UL
 #define srss_0_clock_0_hfclk_4_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF4 4UL
-#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 4UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 2UL
 #define srss_0_clock_0_hfclk_5_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF5 5UL
-#define CY_CFG_SYSCLK_CLKHF5_CLKPATH_NUM 5UL
+#define CY_CFG_SYSCLK_CLKHF5_CLKPATH_NUM 2UL
 #define srss_0_clock_0_hfclk_6_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF6 6UL
-#define CY_CFG_SYSCLK_CLKHF6_CLKPATH_NUM 5UL
+#define CY_CFG_SYSCLK_CLKHF6_CLKPATH_NUM 3UL
 #define srss_0_clock_0_hfclk_7_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF7 7UL
 #define CY_CFG_SYSCLK_CLKHF7_CLKPATH_NUM 5UL
@@ -76,7 +81,8 @@
 #define srss_0_clock_0_imo_0_ENABLED 1U
 #define srss_0_clock_0_lfclk_0_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
-#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_ILO
+#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
+#define srss_0_clock_0_memclk_0_ENABLED 1U
 #define srss_0_clock_0_pathmux_0_ENABLED 1U
 #define srss_0_clock_0_pathmux_1_ENABLED 1U
 #define srss_0_clock_0_pathmux_2_ENABLED 1U
@@ -85,10 +91,13 @@
 #define srss_0_clock_0_pathmux_5_ENABLED 1U
 #define srss_0_clock_0_pathmux_6_ENABLED 1U
 #define srss_0_clock_0_periclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 1
 #define srss_0_clock_0_pll400m_0_ENABLED 1U
 #define srss_0_clock_0_pll400m_1_ENABLED 1U
 #define srss_0_clock_0_pll_0_ENABLED 1U
 #define srss_0_clock_0_pll_1_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
 #define srss_0_clock_0_timerclk_0_ENABLED 1U
 #define srss_0_clock_0_wco_0_ENABLED 1U
 #define srss_0_power_0_ENABLED 1U
@@ -100,28 +109,31 @@
 #define CY_CFG_PWR_MODE_DEEPSLEEP_RAM 0x11UL
 #define CY_CFG_PWR_MODE_DEEPSLEEP_OFF 0x12UL
 #define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
 #define CY_CFG_PWR_SYS_LP_PROFILE_MODE 0
 #define CY_CFG_PWR_VDDA_MV 3300
 #define CY_CFG_PWR_VDDD_MV 3300
 #define CY_CFG_PWR_VDDIO0_MV 3300
 #define CY_CFG_PWR_VDDIO1_MV 3300
+#define CY_CFG_PWR_REGHC_ENABLED false
+#define CY_CFG_PWR_REGHC_MODE 255
+#define CY_CFG_PWR_REGHC_TRANS_VADJ_VOLT 0
 
 #if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
-    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
-    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
-    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
-    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
-    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj;
-    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj;
-#endif //defined (CY_USING_HAL)
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj;
+#endif /* defined (CY_USING_HAL) */
 
 void init_cycfg_system(void);
 void reserve_cycfg_system(void);
 
 #if defined(__cplusplus)
 }
-#endif
-
+#endif /* defined(__cplusplus) */
 
 #endif /* CYCFG_SYSTEM_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg b/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg
index 24b90b9..295934a 100644
--- a/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg
+++ b/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg
@@ -4,10 +4,10 @@
 # Description:
 # This file contains a SMIF Bank layout for use with OpenOCD.
 # This file was automatically generated and should not be modified.
-# QSPI Configurator: 4.0.0.974
+# QSPI Configurator: 4.30.0.1865
 #
 ################################################################################
-# Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
 # an affiliate of Cypress Semiconductor Corporation.
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -25,5 +25,5 @@
 ################################################################################
 
 set SMIF_BANKS {
-  0 {addr 0x60000000 size 0x800000 psize 0x0000100 esize 0x0001000}
+  0 {addr 0x60000000 size 0x800000 psize 0x00000200 esize 0x00040000}
 }
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
index 3d691a3..f110bef 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
@@ -35,7 +35,6 @@
 
 
 #include <stdbool.h>
-#include "system_cat1c.h"
 #include "cy_device.h"
 #include "cy_device_headers.h"
 #include "cy_syslib.h"
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
index c2c36d9..0415a87 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
@@ -244,6 +244,10 @@
 void CM7_CpuIntr7_Handler   (void) __attribute__ ((weak, alias("Default_CpuIntr7_Handler")));
 
 extern const cy_israddress __Vectors[VECTORTABLE_SIZE];
+#if defined (__GNUC__)
+_Pragma("GCC diagnostic push")
+_Pragma("GCC diagnostic ignored \"-Wpedantic\"")
+#endif /* __GNUC__ */
 const cy_israddress __Vectors[VECTORTABLE_SIZE] __VECTOR_TABLE_ATTRIBUTE = {
     (cy_israddress)&__INITIAL_SP,
     (cy_israddress)Reset_Handler,               /* initial PC/Reset */
@@ -280,7 +284,9 @@
     (cy_israddress)Default_Handler,
     (cy_israddress)Default_Handler
 };
-
+#if defined (__GNUC__)
+_Pragma("GCC diagnostic pop")
+#endif /* __GNUC__ */
 
 /* Provide empty __WEAK implementation for the low-level initialization
    routine required by the RTOS-enabled applications.
@@ -342,6 +348,25 @@
     SCB->ITCMCR = SCB->ITCMCR | 0x7; /* Set ITCMCR.EN, .RMW and .RETEN fields */
     SCB->DTCMCR = SCB->DTCMCR | 0x7; /* Set DTCMCR.EN, .RMW and .RETEN fields */
 
+#ifdef CORE_NAME_CM7_0
+    CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos);
+    CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_TCM_EN_Pos);
+    CPUSS_CM7_0_CTL |= (0x1 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos);
+    CPUSS_CM7_0_CTL |= (0x2 << CPUSS_CM7_0_CTL_INIT_RMW_EN_Pos);
+#elif CORE_NAME_CM7_1
+    CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos);
+    CPUSS_CM7_1_CTL |= (0x2 << CPUSS_CM7_1_CTL_INIT_TCM_EN_Pos);
+    CPUSS_CM7_1_CTL |= (0x1 << CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos);
+    CPUSS_CM7_1_CTL |= (0x2 << CPUSS_CM7_1_CTL_INIT_RMW_EN_Pos);
+#else
+/**/
+#endif
+
+    // ITCMCR EN/RMW/RETEN enabled to access ITCM
+    __UNALIGNED_UINT32_WRITE(((void const *)0xE000EF90), 0x2F);
+    // DTCMCR EN/RMW/RETEN enabled to access DTCM
+    __UNALIGNED_UINT32_WRITE(((void const *)0xE000EF94), 0x2F);
+
     /* Enable FPU if present */
     FpuEnable();
 
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
index 650b3b9..488f191 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
@@ -23,7 +23,6 @@
 *******************************************************************************/
 
 #include <stdbool.h>
-#include "system_cat1c.h"
 #include "cy_device.h"
 #include "cy_device_headers.h"
 #include "cy_syslib.h"
@@ -219,31 +218,29 @@
 * The system interrupt mapped to CPU interrupt will be fetched and executed
 *
 *******************************************************************************/
+
 void CM7_CpuIntr_Handler(uint8_t intrNum)
 {
     uint32_t system_int_idx;
     cy_israddress handler;
 
-    if(CY_IS_CM7_CORE_0 && (_FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_0_INT_STATUS[intrNum])))
+#ifdef CORE_NAME_CM7_0
+    if((_FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_0_INT_STATUS[intrNum])))
     {
         system_int_idx = _FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_0_INT_STATUS[intrNum]);
         handler = Cy_SystemIrqUserTable[system_int_idx];
-        if(handler != NULL)
         handler(); // jump to system interrupt handler
     }
-    else if(CY_IS_CM7_CORE_1 && (_FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_1_INT_STATUS[intrNum])))
+#endif
+#ifdef CORE_NAME_CM7_1
+    if((_FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_1_INT_STATUS[intrNum])))
     {
         system_int_idx = _FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_1_INT_STATUS[intrNum]);
         handler = Cy_SystemIrqUserTable[system_int_idx];
-        if(handler != NULL)
         handler(); // jump to system interrupt handler
     }
-    else
-    {
-        // Triggered by software or because of software cleared a peripheral interrupt flag but did not clear the pending flag at NVIC
-    }
+#endif
     NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
 }
 
 
-
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
index 8c67ae9..3fe0771 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
@@ -268,6 +268,19 @@
 * Change the stack size by modifying the following line:\n
 * \code STACK_SIZE = 0x1000; \endcode
 *
+* \note Correct operation of malloc and related functions depends on the working
+* implementation of the 'sbrk' function. Newlib-nano (default C runtime library
+* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that
+* doesn't check for heap and stack collisions during excessive memory allocations.
+* To ensure the heap always remains within the range defined by __HeapBase and
+* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function:
+* \snippet startup/snippet/main.c snippet_sbrk
+* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include
+* clib-support library that provides newlib-compatible implementations of
+* 'sbrk', '__malloc_lock' and '__malloc_unlock':
+* <br>
+* https://github.com/Infineon/clib-support.
+*
 * \subsubsection group_system_config_heap_stack_config_mdk_cm7 ARM Compiler
 * <b>Editing source code files</b>\n
 * The stack size is defined in the linker script files: 'xx_yy_zz.sct',
@@ -425,6 +438,16 @@
 /** Error Selection */
 #define CORE_MAX                    (2U)
 
+/** Define start of the function placed to the ITCM area by the linker */
+#ifndef CY_SECTION_ITCM_BEGIN
+#define CY_SECTION_ITCM_BEGIN CY_SECTION(".cy_itcm")
+#endif
+
+/** Define end of the function placed to the ITCM area by the linker */
+#ifndef CY_SECTION_ITCM_END
+#define CY_SECTION_ITCM_END
+#endif
+
 extern uint32_t cy_delayFreqHz;
 extern uint32_t cy_delayFreqKhz;
 extern uint32_t  cy_delayFreqMhz;
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h b/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
index cd6530d..b6a3f2d 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
@@ -8,21 +8,41 @@
 #define SRAM_PRIVATE_FOR_SROM           0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
 
 /* RAM */
-#define SRAM_BASE_ADDRESS               0x28000000  /* SRAM START */
-#define CM0PLUS_SRAM_RESERVE            0x20000     /* 128K (SRAM0/128KB) -> cm0plus */
-#define CM7_0_SRAM_RESERVE              0x80000 - CM0PLUS_SRAM_RESERVE /* (SRAM0/384KB) -> cm7_0 */
+#define SRAM_BASE_ADDRESS               CY_SRAM_BASE  /* SRAM START */
+#define TOTAL_RAM                       CY_SRAM_SIZE
+#define CM0PLUS_SRAM_RESERVE            0x00004000  /* 16K cm0plus */
 
 /* FLASH */
-#define CODE_FLASH_BASE_ADDRESS         0x10000000  /* FLASH START */
-#define CM0PLUS_CODE_FLASH_RESERVE      0x80000     /* 512K CM0P FLASH SIZE */
-#define CM7_0_CODE_FLASH_RESERVE        0x200000    /* 2048K CM7_0 FLASH SIZE */
+#define CODE_FLASH_BASE_ADDRESS         CY_FLASH_LG_SBM_BASE  /* FLASH START */
+#define TOTAL_FLASH                     (CY_FLASH_LG_SBM_SIZE + CY_FLASH_SM_SBM_SIZE)
+#define CM0PLUS_CODE_FLASH_RESERVE      0x00080000     /* 512K CM0P FLASH SIZE */
+
+/* CM7_1 RAM and FLASH */
+#if defined (__CM7_1_PRESENT)
+    #define CM7_1_SRAM_RESERVE          0x00010000   /* (SRAM0/64KB) -> cm7_1 */
+#else
+    #define CM7_1_SRAM_RESERVE          0x00000000UL
+#endif
+
+#if (TOTAL_FLASH == 0x830000) /** 8M device */
+    #define CM7_0_CODE_FLASH_RESERVE    0x00200000
+#elif (TOTAL_FLASH == 0x410000) /** 4M device */
+    #define CM7_0_CODE_FLASH_RESERVE    0x00200000
+#elif (TOTAL_FLASH == 0x210000) /** 2M device */
+    #define CM7_0_CODE_FLASH_RESERVE    0x00100000
+#elif (TOTAL_FLASH == 0x110000) /** 1M device */
+    #define CM7_0_CODE_FLASH_RESERVE    0x00090000
+#else
+    #error "Invalid device"
+#endif
+
 
 /* SRAM reservations */
-#define BASE_SRAM_CM0P                  SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
-#define SIZE_SRAM_CM0P                  CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
-#define BASE_SRAM_CM7_0                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
-#define SIZE_SRAM_CM7_0                 CM7_0_SRAM_RESERVE
-#define BASE_SRAM_CM7_1                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE
+#define BASE_SRAM_CM0P                  (SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM)
+#define SIZE_SRAM_CM0P                  (CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM)
+#define BASE_SRAM_CM7_0                 (SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE)
+#define SIZE_SRAM_CM7_0                 TOTAL_RAM - CM0PLUS_SRAM_RESERVE - CM7_1_SRAM_RESERVE
+#define BASE_SRAM_CM7_1                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + SIZE_SRAM_CM7_0
 
 /* Code flash reservations */
 #define BASE_CODE_FLASH_CM0P            CODE_FLASH_BASE_ADDRESS
@@ -31,8 +51,6 @@
 #define SIZE_CODE_FLASH_CM7_0           CM7_0_CODE_FLASH_RESERVE
 #define BASE_CODE_FLASH_CM7_1           CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE
 
-
-
 #endif /* LAYOUT_CAT1C_H */
 
 
diff --git a/boot/cypress/platforms/CYW20829.mk b/boot/cypress/platforms/CYW20829.mk
index 54dad0f..f675610 100644
--- a/boot/cypress/platforms/CYW20829.mk
+++ b/boot/cypress/platforms/CYW20829.mk
@@ -75,6 +75,8 @@
 
 ifeq ($(APP_NAME), MCUBootApp)
 
+DEFINES += COMPONENT_CUSTOM_DESIGN_MODUS
+
 # Platform dependend utils files
 PLATFORM_APP_SOURCES := $(PRJ_DIR)/platforms/utils/$(FAMILY)/cyw_platform_utils.c
 PLATFORM_INCLUDE_DIRS_UTILS := $(PRJ_DIR)/platforms/utils/$(FAMILY)