diff --git a/boot/espressif/hal/src/bootloader_banner.c b/boot/espressif/hal/src/bootloader_banner.c
new file mode 100644
index 0000000..8e7d7fc
--- /dev/null
+++ b/boot/espressif/hal/src/bootloader_banner.c
@@ -0,0 +1,15 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mcuboot_config/mcuboot_logging.h>
+
+/**
+ * Override the bootloader's print banner function from IDF.
+ */
+void __wrap_bootloader_print_banner(void)
+{
+    MCUBOOT_LOG_INF("*** Booting MCUboot build %s ***", MCUBOOT_VER);
+}
diff --git a/boot/espressif/hal/src/bootloader_init_common.c b/boot/espressif/hal/src/bootloader_init_common.c
deleted file mode 100644
index 26a5af0..0000000
--- a/boot/espressif/hal/src/bootloader_init_common.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <string.h>
-#include <stdint.h>
-#include "sdkconfig.h"
-#include "esp_attr.h"
-#include "esp_log.h"
-#include "bootloader_init.h"
-#include "bootloader_common.h"
-
-#include "bootloader_flash_config.h"
-#include "bootloader_flash.h"
-#include "bootloader_flash_priv.h"
-
-static const char *TAG = "boot";
-
-esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
-
-void bootloader_clear_bss_section(void)
-{
-    memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
-}
-
-esp_err_t bootloader_read_bootloader_header(void)
-{
-    /* load bootloader image header */
-    if (bootloader_flash_read(ESP_BOOTLOADER_OFFSET, &bootloader_image_hdr, sizeof(esp_image_header_t), true) != ESP_OK) {
-        ESP_LOGE(TAG, "failed to load bootloader image header!");
-        return ESP_FAIL;
-    }
-    return ESP_OK;
-}
-
-esp_err_t bootloader_check_bootloader_validity(void)
-{
-    /* read chip revision from efuse */
-    uint8_t revision = bootloader_common_get_chip_revision();
-    ESP_LOGI(TAG, "chip revision: %d", revision);
-    /* compare with the one set in bootloader image header */
-    if (bootloader_common_check_chip_validity(&bootloader_image_hdr, ESP_IMAGE_BOOTLOADER) != ESP_OK) {
-        return ESP_FAIL;
-    }
-    return ESP_OK;
-}
diff --git a/boot/espressif/hal/src/bootloader_wdt.c b/boot/espressif/hal/src/bootloader_wdt.c
index 197043b..b9bcc6e 100644
--- a/boot/espressif/hal/src/bootloader_wdt.c
+++ b/boot/espressif/hal/src/bootloader_wdt.c
@@ -10,30 +10,8 @@
 
 void bootloader_wdt_feed(void)
 {
-    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+    wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
     wdt_hal_write_protect_disable(&rtc_wdt_ctx);
     wdt_hal_feed(&rtc_wdt_ctx);
     wdt_hal_write_protect_enable(&rtc_wdt_ctx);
 }
-
-void bootloader_config_wdt(void)
-{
-    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
-    wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-    wdt_hal_set_flashboot_en(&rtc_wdt_ctx, false);
-    wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-
-#ifdef CONFIG_ESP_MCUBOOT_WDT_ENABLE
-    wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
-    uint32_t stage_timeout_ticks = (uint32_t)((uint64_t)CONFIG_BOOTLOADER_WDT_TIME_MS * rtc_clk_slow_freq_get_hz() / 1000);
-    wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-    wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
-    wdt_hal_enable(&rtc_wdt_ctx);
-    wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-#endif
-
-    wdt_hal_context_t wdt_ctx = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
-    wdt_hal_write_protect_disable(&wdt_ctx);
-    wdt_hal_set_flashboot_en(&wdt_ctx, false);
-    wdt_hal_write_protect_enable(&wdt_ctx);
-}
diff --git a/boot/espressif/hal/src/esp32/bootloader_init.c b/boot/espressif/hal/src/esp32/bootloader_init.c
deleted file mode 100644
index 244648d..0000000
--- a/boot/espressif/hal/src/esp32/bootloader_init.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stdint.h>
-#include <string.h>
-#include "sdkconfig.h"
-#include "esp_attr.h"
-#include "esp_image_format.h"
-
-#include "bootloader_init.h"
-#include "bootloader_mem.h"
-#include "bootloader_console.h"
-#include "bootloader_clock.h"
-#include "bootloader_flash_config.h"
-#include "bootloader_flash.h"
-#include "bootloader_flash_priv.h"
-
-#include "soc/dport_reg.h"
-#include "soc/efuse_reg.h"
-#include "soc/rtc.h"
-
-#include "bootloader_wdt.h"
-#include "hal/wdt_hal.h"
-
-#include "esp32/rom/cache.h"
-#include "esp32/rom/spi_flash.h"
-#include "esp32/rom/uart.h"
-
-#include <esp_rom_uart.h>
-#include <esp_rom_gpio.h>
-#include <esp_rom_sys.h>
-#include <soc/uart_periph.h>
-#include <soc/gpio_struct.h>
-#include <hal/gpio_types.h>
-#include <hal/gpio_ll.h>
-#include <hal/uart_ll.h>
-
-extern esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
-
-#if CONFIG_ESP_CONSOLE_UART_CUSTOM
-static uart_dev_t *alt_console_uart_dev = (CONFIG_ESP_CONSOLE_UART_NUM == 0) ?
-                                          &UART0 :
-                                          (CONFIG_ESP_CONSOLE_UART_NUM == 1) ?
-                                          &UART1 :
-                                          &UART2;
-#endif
-
-
-static void bootloader_common_vddsdio_configure(void)
-{
-    rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
-    if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) {    /* VDDSDIO regulator is enabled @ 1.8V */
-        cfg.drefh = 3;
-        cfg.drefm = 3;
-        cfg.drefl = 3;
-        cfg.force = 1;
-        rtc_vddsdio_set_config(cfg);
-        esp_rom_delay_us(10); /* wait for regulator to become stable */
-    }
-}
-
-static void bootloader_reset_mmu(void)
-{
-    /* completely reset MMU in case serial bootloader was running */
-    Cache_Read_Disable(0);
-#if !CONFIG_FREERTOS_UNICORE
-    Cache_Read_Disable(1);
-#endif
-    Cache_Flush(0);
-#if !CONFIG_FREERTOS_UNICORE
-    Cache_Flush(1);
-#endif
-    mmu_init(0);
-#if !CONFIG_FREERTOS_UNICORE
-    /* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
-        necessary to work around a hardware bug. */
-    DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
-    mmu_init(1);
-    DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
-#endif
-
-    /* normal ROM boot exits with DROM0 cache unmasked,
-        but serial bootloader exits with it masked. */
-    DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
-#if !CONFIG_FREERTOS_UNICORE
-    DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
-#endif
-}
-
-static esp_err_t bootloader_check_rated_cpu_clock(void)
-{
-    int rated_freq = bootloader_clock_get_rated_freq_mhz();
-    if (rated_freq < 80) {
-        return ESP_FAIL;
-    }
-    return ESP_OK;
-}
-
-static void update_flash_config(const esp_image_header_t *bootloader_hdr)
-{
-    uint32_t size;
-    switch (bootloader_hdr->spi_size) {
-    case ESP_IMAGE_FLASH_SIZE_1MB:
-        size = 1;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_2MB:
-        size = 2;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_4MB:
-        size = 4;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_8MB:
-        size = 8;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_16MB:
-        size = 16;
-        break;
-    default:
-        size = 2;
-    }
-    Cache_Read_Disable(0);
-    /* Set flash chip size */
-    esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
-    /* TODO: set mode */
-    /* TODO: set frequency */
-    Cache_Flush(0);
-    Cache_Read_Enable(0);
-}
-
-static void IRAM_ATTR bootloader_init_flash_configure(void)
-{
-    bootloader_flash_gpio_config(&bootloader_image_hdr);
-    bootloader_flash_dummy_config(&bootloader_image_hdr);
-    bootloader_flash_cs_timing_config();
-}
-
-static esp_err_t bootloader_init_spi_flash(void)
-{
-    bootloader_init_flash_configure();
-    esp_rom_spiflash_unlock();
-
-    update_flash_config(&bootloader_image_hdr);
-    return ESP_OK;
-}
-
-#if CONFIG_ESP_CONSOLE_UART_CUSTOM
-void IRAM_ATTR esp_rom_uart_putc(char c)
-{
-    while (uart_ll_get_txfifo_len(alt_console_uart_dev) == 0);
-    uart_ll_write_txfifo(alt_console_uart_dev, (const uint8_t *) &c, 1);
-}
-#endif
-
-esp_err_t bootloader_init(void)
-{
-    esp_err_t ret = ESP_OK;
-
-    bootloader_init_mem();
-
-    /* check that static RAM is after the stack */
-#ifndef NDEBUG
-    {
-        assert(&_bss_start <= &_bss_end);
-        assert(&_data_start <= &_data_end);
-        assert(sp < &_bss_start);
-        assert(sp < &_data_start);
-    }
-#endif
-    /* clear bss section */
-    bootloader_clear_bss_section();
-    /* bootst up vddsdio */
-    bootloader_common_vddsdio_configure();
-    /* reset MMU */
-    bootloader_reset_mmu();
-    /* check rated CPU clock */
-    if ((ret = bootloader_check_rated_cpu_clock()) != ESP_OK) {
-        goto err;
-    }
-    /* config clock */
-    bootloader_clock_configure();
-    /* initialize uart console, from now on, we can use ets_printf */
-    bootloader_console_init();
-    /* read bootloader header */
-    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
-        goto err;
-    }
-    // read chip revision and check if it's compatible to bootloader
-    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
-        goto err;
-    }
-    /* initialize spi flash */
-    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
-        goto err;
-    }
-    /* config WDT */
-    bootloader_config_wdt();
-err:
-    return ret;
-}
diff --git a/boot/espressif/hal/src/esp32/console_uart_custom.c b/boot/espressif/hal/src/esp32/console_uart_custom.c
new file mode 100644
index 0000000..f004be9
--- /dev/null
+++ b/boot/espressif/hal/src/esp32/console_uart_custom.c
@@ -0,0 +1,24 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <esp_rom_uart.h>
+#include <hal/uart_ll.h>
+#include <soc/uart_periph.h>
+
+#if CONFIG_ESP_CONSOLE_UART_CUSTOM
+static uart_dev_t *alt_console_uart_dev = (CONFIG_ESP_CONSOLE_UART_NUM == 0) ?
+                                          &UART0 :
+                                          (CONFIG_ESP_CONSOLE_UART_NUM == 1) ?
+                                          &UART1 :
+                                          &UART2;
+
+void IRAM_ATTR esp_rom_uart_putc(char c)
+{
+    while (uart_ll_get_txfifo_len(alt_console_uart_dev) == 0);
+    uart_ll_write_txfifo(alt_console_uart_dev, (const uint8_t *) &c, 1);
+}
+#endif
+
diff --git a/boot/espressif/hal/src/esp32c3/bootloader_init.c b/boot/espressif/hal/src/esp32c3/bootloader_init.c
deleted file mode 100644
index d3808d8..0000000
--- a/boot/espressif/hal/src/esp32c3/bootloader_init.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <errno.h>
-
-#include "sdkconfig.h"
-#include "esp_attr.h"
-#include "esp_image_format.h"
-
-#include "esp_rom_efuse.h"
-#include "esp_rom_gpio.h"
-#include "esp_rom_uart.h"
-#include "esp_rom_sys.h"
-
-#include "bootloader_init.h"
-#include "bootloader_common.h"
-#include "bootloader_console.h"
-#include "bootloader_clock.h"
-#include "bootloader_flash_config.h"
-#include "bootloader_mem.h"
-#include "bootloader_flash.h"
-#include "bootloader_flash_priv.h"
-#include "regi2c_ctrl.h"
-
-#include "soc/extmem_reg.h"
-#include "soc/io_mux_reg.h"
-#include "soc/efuse_reg.h"
-#include "soc/rtc.h"
-
-#include "hal/gpio_hal.h"
-#include <hal/gpio_ll.h>
-#include <hal/uart_ll.h>
-
-#include "esp32c3/rom/cache.h"
-#include "esp32c3/rom/spi_flash.h"
-
-#include "bootloader_wdt.h"
-#include "hal/wdt_hal.h"
-
-extern esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
-
-#if CONFIG_ESP_CONSOLE_UART_CUSTOM
-static uart_dev_t *alt_console_uart_dev = (CONFIG_ESP_CONSOLE_UART_NUM == 0) ?
-                                          &UART0 :
-                                          &UART1;
-#endif
-
-void IRAM_ATTR bootloader_configure_spi_pins(int drv)
-{
-    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
-    uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
-    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
-    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
-    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
-    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
-    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
-    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
-    if (spiconfig != 0) {
-        clk_gpio_num = spiconfig         & 0x3f;
-        q_gpio_num = (spiconfig >> 6)    & 0x3f;
-        d_gpio_num = (spiconfig >> 12)   & 0x3f;
-        cs0_gpio_num = (spiconfig >> 18) & 0x3f;
-        hd_gpio_num = (spiconfig >> 24)  & 0x3f;
-        wp_gpio_num = wp_pin;
-    }
-    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
-    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
-    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
-    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
-    if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
-        esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
-    }
-    if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
-        esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
-    }
-}
-
-static void bootloader_reset_mmu(void)
-{
-    Cache_Suspend_ICache();
-    Cache_Invalidate_ICache_All();
-    Cache_MMU_Init();
-
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
-}
-
-static void update_flash_config(const esp_image_header_t *bootloader_hdr)
-{
-    uint32_t size;
-    switch (bootloader_hdr->spi_size) {
-    case ESP_IMAGE_FLASH_SIZE_1MB:
-        size = 1;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_2MB:
-        size = 2;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_4MB:
-        size = 4;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_8MB:
-        size = 8;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_16MB:
-        size = 16;
-        break;
-    default:
-        size = 2;
-    }
-    uint32_t autoload = Cache_Suspend_ICache();
-    // Set flash chip size
-    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
-    Cache_Resume_ICache(autoload);
-}
-
-static void IRAM_ATTR bootloader_init_flash_configure(void)
-{
-    bootloader_flash_dummy_config(&bootloader_image_hdr);
-    bootloader_flash_cs_timing_config();
-}
-
-static void bootloader_spi_flash_resume(void)
-{
-    bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
-    esp_rom_spiflash_wait_idle(&g_rom_flashchip);
-}
-
-static esp_err_t bootloader_init_spi_flash(void)
-{
-    bootloader_init_flash_configure();
-    bootloader_spi_flash_resume();
-    esp_rom_spiflash_unlock();
-    update_flash_config(&bootloader_image_hdr);
-
-    return ESP_OK;
-}
-
-static inline void bootloader_hardware_init(void)
-{
-    // This check is always included in the bootloader so it can
-    // print the minimum revision error message later in the boot
-    if (bootloader_common_get_chip_revision() < 3) {
-        REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
-        REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
-    }
-}
-
-static inline void bootloader_glitch_reset_disable(void)
-{
-    /*
-      For origin chip & ECO1: only support swt reset;
-      For ECO2: fix brownout reset bug, support swt & brownout reset;
-      For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
-    */
-    uint8_t chip_version = bootloader_common_get_chip_revision();
-    if (chip_version < 2) {
-        REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST);
-    } else if (chip_version == 2) {
-        REG_SET_FIELD(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SEL, RTC_CNTL_FIB_SUPER_WDT_RST | RTC_CNTL_FIB_BOR_RST);
-    }
-}
-
-static void bootloader_super_wdt_auto_feed(void)
-{
-    REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
-    REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
-    REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
-}
-
-#if CONFIG_ESP_CONSOLE_UART_CUSTOM
-void IRAM_ATTR esp_rom_uart_putc(char c)
-{
-    while (uart_ll_get_txfifo_len(alt_console_uart_dev) == 0);
-    uart_ll_write_txfifo(alt_console_uart_dev, (const uint8_t *) &c, 1);
-}
-#endif
-
-esp_err_t bootloader_init(void)
-{
-    esp_err_t ret = ESP_OK;
-
-    bootloader_hardware_init();
-    bootloader_glitch_reset_disable();
-    bootloader_super_wdt_auto_feed();
-    // protect memory region
-    bootloader_init_mem();
-    /* check that static RAM is after the stack */
-    assert(&_bss_start <= &_bss_end);
-    assert(&_data_start <= &_data_end);
-    // clear bss section
-    bootloader_clear_bss_section();
-    // reset MMU
-    bootloader_reset_mmu();
-    // config clock
-    bootloader_clock_configure();
-    /* initialize uart console, from now on, we can use ets_printf */
-    bootloader_console_init();
-    // update flash ID
-    bootloader_flash_update_id();
-    // read bootloader header
-    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
-        goto err;
-    }
-    // read chip revision and check if it's compatible to bootloader
-    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
-        goto err;
-    }
-    // initialize spi flash
-    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
-        goto err;
-    }
-    // config WDT
-    bootloader_config_wdt();
-err:
-    return ret;
-}
diff --git a/boot/espressif/hal/src/esp32c3/console_uart_custom.c b/boot/espressif/hal/src/esp32c3/console_uart_custom.c
new file mode 100644
index 0000000..214c60f
--- /dev/null
+++ b/boot/espressif/hal/src/esp32c3/console_uart_custom.c
@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <esp_rom_uart.h>
+#include <hal/uart_ll.h>
+#include <soc/uart_periph.h>
+
+#if CONFIG_ESP_CONSOLE_UART_CUSTOM
+static uart_dev_t *alt_console_uart_dev = (CONFIG_ESP_CONSOLE_UART_NUM == 0) ?
+                                          &UART0 :
+                                          &UART1;
+
+void IRAM_ATTR esp_rom_uart_putc(char c)
+{
+    while (uart_ll_get_txfifo_len(alt_console_uart_dev) == 0);
+    uart_ll_write_txfifo(alt_console_uart_dev, (const uint8_t *) &c, 1);
+}
+#endif
+
diff --git a/boot/espressif/hal/src/esp32s2/bootloader_init.c b/boot/espressif/hal/src/esp32s2/bootloader_init.c
deleted file mode 100644
index a3e4b2f..0000000
--- a/boot/espressif/hal/src/esp32s2/bootloader_init.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stdint.h>
-#include <string.h>
-#include "sdkconfig.h"
-#include "esp_attr.h"
-#include "esp_image_format.h"
-
-#include "esp_rom_efuse.h"
-#include "esp_rom_gpio.h"
-
-#include "bootloader_init.h"
-#include "bootloader_common.h"
-#include "bootloader_console.h"
-#include "bootloader_mem.h"
-#include "bootloader_clock.h"
-#include "bootloader_flash_config.h"
-#include "bootloader_flash.h"
-#include "bootloader_flash_priv.h"
-
-#include "soc/dport_reg.h"
-#include "soc/efuse_reg.h"
-#include "soc/rtc.h"
-#include "soc/extmem_reg.h"
-#include "soc/io_mux_reg.h"
-
-#include "bootloader_wdt.h"
-#include "hal/wdt_hal.h"
-
-#include "esp32s2/rom/cache.h"
-#include "esp32s2/rom/ets_sys.h"
-#include "esp32s2/rom/spi_flash.h"
-#include "esp32s2/rom/uart.h"
-
-extern esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
-
-static void bootloader_reset_mmu(void)
-{
-    Cache_Suspend_ICache();
-    Cache_Invalidate_ICache_All();
-    Cache_MMU_Init();
-
-    /* normal ROM boot exits with DROM0 cache unmasked,
-    but serial bootloader exits with it masked. */
-    REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
-}
-
-static void update_flash_config(const esp_image_header_t *bootloader_hdr)
-{
-    uint32_t size;
-    switch (bootloader_hdr->spi_size) {
-    case ESP_IMAGE_FLASH_SIZE_1MB:
-        size = 1;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_2MB:
-        size = 2;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_4MB:
-        size = 4;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_8MB:
-        size = 8;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_16MB:
-        size = 16;
-        break;
-    default:
-        size = 2;
-    }
-    uint32_t autoload = Cache_Suspend_ICache();
-    // Set flash chip size
-    esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
-    Cache_Resume_ICache(autoload);
-}
-
-void IRAM_ATTR bootloader_configure_spi_pins(int drv)
-{
-    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
-    uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
-    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
-    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
-    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
-    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
-    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
-    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
-    if (spiconfig != 0) {
-        clk_gpio_num = spiconfig         & 0x3f;
-        q_gpio_num = (spiconfig >> 6)    & 0x3f;
-        d_gpio_num = (spiconfig >> 12)   & 0x3f;
-        cs0_gpio_num = (spiconfig >> 18) & 0x3f;
-        hd_gpio_num = (spiconfig >> 24)  & 0x3f;
-        wp_gpio_num = wp_pin;
-    }
-    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
-    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
-    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
-    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
-    if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
-        esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
-    }
-    if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
-        esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
-    }
-}
-
-static void IRAM_ATTR bootloader_init_flash_configure(void)
-{
-    bootloader_flash_dummy_config(&bootloader_image_hdr);
-    bootloader_flash_cs_timing_config();
-}
-
-static esp_err_t bootloader_init_spi_flash(void)
-{
-    bootloader_init_flash_configure();
-    esp_rom_spiflash_unlock();
-
-    update_flash_config(&bootloader_image_hdr);
-    return ESP_OK;
-}
-
-static void bootloader_super_wdt_auto_feed(void)
-{
-    REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
-}
-
-esp_err_t bootloader_init(void)
-{
-    esp_err_t ret = ESP_OK;
-    bootloader_super_wdt_auto_feed();
-
-    bootloader_init_mem();
-
-    /* check that static RAM is after the stack */
-#ifndef NDEBUG
-    {
-        assert(&_bss_start <= &_bss_end);
-        assert(&_data_start <= &_data_end);
-    }
-#endif
-    /* clear bss section */
-    bootloader_clear_bss_section();
-    /* reset MMU */
-    bootloader_reset_mmu();
-    /* config clock */
-    bootloader_clock_configure();
-    /* initialize uart console, from now on, we can use ets_printf */
-    bootloader_console_init();
-    /* read bootloader header */
-    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
-        goto err;
-    }
-    // read chip revision and check if it's compatible to bootloader
-    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
-        goto err;
-    }
-    /* initialize spi flash */
-    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
-        goto err;
-    }
-    /* config WDT */
-    bootloader_config_wdt();
-err:
-    return ret;
-}
diff --git a/boot/espressif/hal/src/esp32s3/bootloader_init.c b/boot/espressif/hal/src/esp32s3/bootloader_init.c
deleted file mode 100644
index 455173b..0000000
--- a/boot/espressif/hal/src/esp32s3/bootloader_init.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stdint.h>
-#include <string.h>
-#include "sdkconfig.h"
-#include "esp_attr.h"
-#include "esp_image_format.h"
-#include "flash_qio_mode.h"
-#include "esp_rom_efuse.h"
-#include "esp_rom_gpio.h"
-#include "esp_rom_sys.h"
-#include "esp_rom_uart.h"
-#include "esp_efuse.h"
-
-#include "bootloader_init.h"
-#include "bootloader_common.h"
-#include "bootloader_console.h"
-#include "bootloader_mem.h"
-#include "bootloader_clock.h"
-#include "bootloader_flash_config.h"
-#include "bootloader_flash.h"
-#include "bootloader_flash_priv.h"
-#include "bootloader_soc.h"
-
-#include "soc/cpu.h"
-#include "soc/dport_reg.h"
-#include "soc/efuse_reg.h"
-#include "soc/rtc.h"
-#include "soc/rtc_cntl_reg.h"
-#include "soc/extmem_reg.h"
-#include "soc/io_mux_reg.h"
-#include "soc/assist_debug_reg.h"
-
-#include "bootloader_wdt.h"
-#include "hal/wdt_hal.h"
-
-#include "esp32s3/rom/cache.h"
-#include "esp32s3/rom/ets_sys.h"
-#include "esp32s3/rom/spi_flash.h"
-#include "esp32s3/rom/uart.h"
-
-#include "esp_log.h"
-#include "mcuboot_config/mcuboot_config.h"
-
-static const char *TAG = "boot.esp32s3";
-
-extern esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
-
-static void bootloader_reset_mmu(void)
-{
-    Cache_Suspend_DCache();
-    Cache_Invalidate_DCache_All();
-    Cache_MMU_Init();
-
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE0_BUS);
-    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_CORE1_BUS);
-}
-
-static void update_flash_config(const esp_image_header_t *bootloader_hdr)
-{
-    uint32_t size;
-    switch (bootloader_hdr->spi_size) {
-    case ESP_IMAGE_FLASH_SIZE_1MB:
-        size = 1;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_2MB:
-        size = 2;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_4MB:
-        size = 4;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_8MB:
-        size = 8;
-        break;
-    case ESP_IMAGE_FLASH_SIZE_16MB:
-        size = 16;
-        break;
-    default:
-        size = 2;
-    }
-    uint32_t autoload = Cache_Suspend_DCache();
-    // Set flash chip size
-    esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
-    Cache_Resume_DCache(autoload);
-}
-
-void IRAM_ATTR bootloader_configure_spi_pins(int drv)
-{
-    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
-    uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
-    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
-    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
-    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
-    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
-    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
-    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
-    if (spiconfig == 0) {
-
-    } else {
-        clk_gpio_num = spiconfig         & 0x3f;
-        q_gpio_num = (spiconfig >> 6)    & 0x3f;
-        d_gpio_num = (spiconfig >> 12)   & 0x3f;
-        cs0_gpio_num = (spiconfig >> 18) & 0x3f;
-        hd_gpio_num = (spiconfig >> 24)  & 0x3f;
-        wp_gpio_num = wp_pin;
-    }
-    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
-    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
-    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
-    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
-    if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
-        esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
-    }
-    if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
-        esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
-    }
-}
-
-static void IRAM_ATTR bootloader_init_flash_configure(void)
-{
-    bootloader_flash_dummy_config(&bootloader_image_hdr);
-    bootloader_flash_cs_timing_config();
-}
-
-static esp_err_t bootloader_init_spi_flash(void)
-{
-    bootloader_init_flash_configure();
-#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
-    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
-    if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
-        ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
-        return ESP_FAIL;
-    }
-#endif
-
-    bootloader_flash_unlock();
-    update_flash_config(&bootloader_image_hdr);
-    //ensure the flash is write-protected
-    bootloader_enable_wp();
-    return ESP_OK;
-}
-
-static void wdt_reset_cpu0_info_enable(void)
-{
-    REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
-    REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
-    REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG, 1);
-    REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG, 1);
-}
-
-#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_DEBUG
-static void wdt_reset_info_dump(int cpu)
-{
-    uint32_t inst = 0, pid = 0, stat = 0, data = 0, pc = 0,
-             lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
-    const char *cpu_name = cpu ? "APP" : "PRO";
-
-    stat = 0xdeadbeef;
-    pid = 0;
-    if (cpu == 0) {
-        inst    = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG);
-        dstat   = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG);
-        data    = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG);
-        pc      = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG);
-        lsstat  = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG);
-        lsaddr  = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG);
-        lsdata  = REG_READ(ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG);
-    } else {
-        inst    = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG);
-        dstat   = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG);
-        data    = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG);
-        pc      = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG);
-        lsstat  = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG);
-        lsaddr  = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG);
-        lsdata  = REG_READ(ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG);
-    }
-
-    ESP_LOGD(TAG, "WDT reset info: %s CPU STATUS        0x%08x", cpu_name, stat);
-    ESP_LOGD(TAG, "WDT reset info: %s CPU PID           0x%08x", cpu_name, pid);
-    ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGINST    0x%08x", cpu_name, inst);
-    ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGSTATUS  0x%08x", cpu_name, dstat);
-    ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGDATA    0x%08x", cpu_name, data);
-    ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGPC      0x%08x", cpu_name, pc);
-    ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0STAT 0x%08x", cpu_name, lsstat);
-    ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0ADDR 0x%08x", cpu_name, lsaddr);
-    ESP_LOGD(TAG, "WDT reset info: %s CPU PDEBUGLS0DATA 0x%08x", cpu_name, lsdata);
-}
-#endif
-
-static void bootloader_check_wdt_reset(void)
-{
-    int wdt_rst = 0;
-    soc_reset_reason_t rst_reas[2];
-
-    rst_reas[0] = esp_rom_get_reset_reason(0);
-    rst_reas[1] = esp_rom_get_reset_reason(1);
-    if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0 || rst_reas[0] == RESET_REASON_CORE_MWDT1 ||
-        rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_RTC_WDT) {
-        ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
-        wdt_rst = 1;
-    }
-    if (rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0 || rst_reas[1] == RESET_REASON_CORE_MWDT1 ||
-        rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_RTC_WDT) {
-        ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
-        wdt_rst = 1;
-    }
-    if (wdt_rst) {
-#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_DEBUG
-        // if reset by WDT dump info from trace port
-        wdt_reset_info_dump(0);
-        wdt_reset_info_dump(1);
-#endif
-    }
-    wdt_reset_cpu0_info_enable();
-}
-
-static void bootloader_super_wdt_auto_feed(void)
-{
-    REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
-    REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
-    REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);}
-
-static inline void bootloader_ana_reset_config(void)
-{
-    //Enable WDT, BOR, and GLITCH reset
-    bootloader_ana_super_wdt_reset_config(true);
-    bootloader_ana_bod_reset_config(true);
-    bootloader_ana_clock_glitch_reset_config(true);
-}
-
-esp_err_t bootloader_init(void)
-{
-    esp_err_t ret = ESP_OK;
-    bootloader_ana_reset_config();
-    bootloader_super_wdt_auto_feed();
-    // protect memory region
-    bootloader_init_mem();
-    /* check that static RAM is after the stack */
-#ifndef NDEBUG
-    {
-        assert(&_bss_start <= &_bss_end);
-        assert(&_data_start <= &_data_end);
-    }
-#endif
-    // clear bss section
-    bootloader_clear_bss_section();
-    // reset MMU
-    bootloader_reset_mmu();
-    // config clock
-    bootloader_clock_configure();
-    /* initialize uart console, from now on, we can use ets_printf */
-    bootloader_console_init();
-    // Check and run XMC startup flow
-    if ((ret = bootloader_flash_xmc_startup()) != ESP_OK) {
-       goto err;
-    }
-    // read bootloader header
-    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
-        goto err;
-    }
-    // read chip revision and check if it's compatible to bootloader
-    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
-        goto err;
-    }
-    // initialize spi flash
-    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
-        goto err;
-    }
-    // check whether a WDT reset happend
-    bootloader_check_wdt_reset();
-    // config WDT
-    bootloader_config_wdt();
-
-err:
-    return ret;
-}
diff --git a/boot/espressif/hal/src/flash_encrypt.c b/boot/espressif/hal/src/flash_encrypt.c
index 77f5992..222e32e 100644
--- a/boot/espressif/hal/src/flash_encrypt.c
+++ b/boot/espressif/hal/src/flash_encrypt.c
@@ -41,6 +41,36 @@
 static esp_err_t encrypt_bootloader(void);
 static esp_err_t encrypt_primary_slot(void);
 
+/**
+ * This former inlined function must not be defined in the header file anymore.
+ * As it depends on efuse component, any use of it outside of `bootloader_support`,
+ * would require the caller component to include `efuse` as part of its `REQUIRES` or
+ * `PRIV_REQUIRES` entries.
+ * Attribute IRAM_ATTR must be specified for the app build.
+ */
+bool IRAM_ATTR esp_flash_encryption_enabled(void)
+{
+    uint32_t flash_crypt_cnt = 0;
+#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    flash_crypt_cnt = efuse_ll_get_flash_crypt_cnt();
+#else
+#if CONFIG_IDF_TARGET_ESP32
+    esp_efuse_read_field_blob(ESP_EFUSE_FLASH_CRYPT_CNT, &flash_crypt_cnt, ESP_EFUSE_FLASH_CRYPT_CNT[0]->bit_count);
+#else
+    esp_efuse_read_field_blob(ESP_EFUSE_SPI_BOOT_CRYPT_CNT, &flash_crypt_cnt, ESP_EFUSE_SPI_BOOT_CRYPT_CNT[0]->bit_count);
+#endif
+#endif
+    /* __builtin_parity is in flash, so we calculate parity inline */
+    bool enabled = false;
+    while (flash_crypt_cnt) {
+        if (flash_crypt_cnt & 1) {
+            enabled = !enabled;
+        }
+        flash_crypt_cnt >>= 1;
+    }
+    return enabled;
+}
+
 esp_err_t esp_flash_encrypt_check_and_update(void)
 {
     size_t flash_crypt_cnt = 0;
@@ -360,7 +390,7 @@
         return ESP_FAIL;
     }
 
-    wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
+    wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
     for (size_t i = 0; i < data_length; i += FLASH_SECTOR_SIZE) {
         wdt_hal_write_protect_disable(&rtc_wdt_ctx);
         wdt_hal_feed(&rtc_wdt_ctx);
diff --git a/boot/espressif/hal/src/secure_boot.c b/boot/espressif/hal/src/secure_boot.c
index 9cb24be..5c6a475 100644
--- a/boot/espressif/hal/src/secure_boot.c
+++ b/boot/espressif/hal/src/secure_boot.c
@@ -15,6 +15,22 @@
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
 
+#if CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C3
+#include "esp32c3/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32S3
+#include "esp32s3/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32H4
+#include "esp32h4/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C2
+#include "esp32c2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP32C6
+#include "esp32c6/rom/secure_boot.h"
+#endif
+
 /* The following API implementations are used only when called
  * from the bootloader code.
  */