Cypress: Add entering deep sleep in MCUBootApp, code improvements
- improved code in MCUBootApp
- added possibility to enter deep sleep mode after mcuboot app execution
- minor refactoring
Signed-off-by: dmiv <dmiv@cypress.com>
Signed-off-by: Roman Okhrimenko <roman.okhrimenko@cypress.com>
Signed-off-by: Taras Boretskyy <taras.boretskyy@cypress.com>
diff --git a/boot/cypress/MCUBootApp/main.c b/boot/cypress/MCUBootApp/main.c
index 6fcc81f..eb0ee11 100644
--- a/boot/cypress/MCUBootApp/main.c
+++ b/boot/cypress/MCUBootApp/main.c
@@ -41,6 +41,55 @@
#define CYBSP_UART_HW SCB5
#define CYBSP_UART_IRQ scb_5_interrupt_IRQn
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+/* Choose SMIF slot number (slave select).
+ * Acceptable values are:
+ * 0 - SMIF disabled (no external memory);
+ * 1, 2, 3 or 4 - slave select line memory module is connected to.
+ */
+uint32_t smif_id = 1; /* Assume SlaveSelect_0 is used for External Memory */
+#endif
+
+extern cy_stc_scb_uart_context_t CYBSP_UART_context;
+
+/* Parameter structures for callback function */
+static cy_stc_syspm_callback_params_t deep_sleep_clbk_params =
+{
+ CYBSP_UART_HW,
+ &CYBSP_UART_context
+};
+
+static cy_stc_syspm_callback_params_t deep_sleep_sysclk_pm_clbk_param =
+{
+ NULL,
+ NULL
+};
+
+/* Callback structure */
+cy_stc_syspm_callback_t uart_deep_sleep =
+{
+ &Cy_SCB_UART_DeepSleepCallback,
+ CY_SYSPM_DEEPSLEEP,
+ CY_SYSPM_SKIP_BEFORE_TRANSITION ,
+ &deep_sleep_clbk_params,
+ NULL,
+ NULL,
+ 0
+};
+
+cy_stc_syspm_callback_t clk_deep_sleep =
+{
+ &Cy_SysClk_DeepSleepCallback,
+ CY_SYSPM_DEEPSLEEP,
+ CY_SYSPM_SKIP_BEFORE_TRANSITION ,
+ &deep_sleep_sysclk_pm_clbk_param,
+ NULL,
+ NULL,
+ 0
+};
+
+void hw_deinit(void);
+
static void do_boot(struct boot_rsp *rsp)
{
uint32_t app_addr = 0;
@@ -51,26 +100,36 @@
BOOT_LOG_INF("Start Address: 0x%08lx", app_addr);
Cy_SysLib_Delay(100);
- Cy_SysEnableCM4(app_addr);
+ hw_deinit();
- while (1)
- {
- __WFI() ;
- }
+ Cy_SysEnableCM4(app_addr);
}
int main(void)
{
struct boot_rsp rsp;
+ cy_rslt_t result = CY_RSLT_TYPE_ERROR;
init_cycfg_clocks();
init_cycfg_peripherals();
init_cycfg_pins();
+
+ /* register callback funtions that manage peripherals before going to deep sleep */
+ if (!Cy_SysPm_RegisterCallback(&uart_deep_sleep) ||
+ !Cy_SysPm_RegisterCallback(&clk_deep_sleep))
+ {
+ CY_ASSERT(0);
+ }
/* enable interrupts */
__enable_irq();
/* Initialize retarget-io to use the debug UART port (CYBSP_UART_HW) */
- cy_retarget_io_pdl_init(115200u);
+ result = cy_retarget_io_pdl_init(115200u);
+
+ if (result != CY_RSLT_SUCCESS)
+ {
+ CY_ASSERT(0);
+ }
BOOT_LOG_INF("MCUBoot Bootloader Started");
@@ -82,13 +141,8 @@
* available on PSoC062-2M in case of external
* memory usage */
#define MCUBOOT_MAX_IMG_SECTORS 4096
- int smif_id = 1; /* Assume SlaveSelect_0 is used for External Memory */
- /* Acceptable values are:
- * 0 - SMIF disabled (no external memory);
- * 1, 2, 3 or 4 - slave select line memory module is connected to.
- */
rc = qspi_init_sfdp(smif_id);
- if(rc == CY_SMIF_SUCCESS)
+ if (rc == CY_SMIF_SUCCESS)
{
BOOT_LOG_INF("External Memory initialized w/ SFDP.");
}
@@ -96,14 +150,35 @@
{
BOOT_LOG_ERR("External Memory initialization w/ SFDP FAILED: 0x%02x", (int)rc);
}
- if(0 == rc)
+ if (0 == rc)
#endif
{
- if (boot_go(&rsp) == 0) {
+ if (boot_go(&rsp) == 0)
+ {
BOOT_LOG_INF("User Application validated successfully");
do_boot(&rsp);
- } else
- BOOT_LOG_INF("MCUBoot Bootloader found none of bootable images") ;
+ }
+ else
+ {
+ BOOT_LOG_INF("MCUBoot Bootloader found none of bootable images");
+ }
}
+
+ while (1)
+ {
+ Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
+ }
+
return 0;
}
+
+void hw_deinit(void)
+{
+ cy_retarget_io_pdl_deinit();
+ Cy_GPIO_Port_Deinit(CYBSP_UART_RX_PORT);
+ Cy_GPIO_Port_Deinit(CYBSP_UART_TX_PORT);
+
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ qspi_deinit(smif_id);
+#endif
+}
diff --git a/boot/cypress/Makefile b/boot/cypress/Makefile
index 3868c80..9a7b43a 100644
--- a/boot/cypress/Makefile
+++ b/boot/cypress/Makefile
@@ -193,7 +193,7 @@
run_cppcheck:
@echo "Performing static code analysis with Cppcheck tool..."
- ../../scripts/cpp_check.sh ../../scripts/cpp_check.dat
+ cppcheck/cppcheck.sh $(APP_NAME) $(PLATFORM) "$(DEFINES)" "$(INCLUDE_DIRS)" "$(C_FILES)" $(CPP_CHECK_SCOPE) $(BUILDCFG)
gen_key_ecc256:
@echo Generate ECC256 keys: $(SIGN_KEY_FILE).pem and $(SIGN_KEY_FILE).pub
diff --git a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.c b/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.c
index 83e1855..1f9c51a 100644
--- a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.c
+++ b/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.c
@@ -473,3 +473,21 @@
return (*memCfg)->deviceCfg->memSize;
}
+void qspi_deinit(uint32_t smif_id)
+{
+ Cy_SMIF_MemDeInit(QSPIPort);
+
+ Cy_SMIF_Disable(QSPIPort);
+
+ Cy_SysClk_ClkHfDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
+
+ NVIC_DisableIRQ(smifIntConfig.intrSrc);
+ Cy_SysInt_DisconnectInterruptSource(smifIntConfig.intrSrc, smifIntConfig.cm0pSrc);
+
+ Cy_GPIO_Port_Deinit(qspi_SS_Configuration[smif_id-1].SS_Port);
+ Cy_GPIO_Port_Deinit(SCKPort);
+ Cy_GPIO_Port_Deinit(D0Port);
+ Cy_GPIO_Port_Deinit(D1Port);
+ Cy_GPIO_Port_Deinit(D2Port);
+ Cy_GPIO_Port_Deinit(D3Port);
+}
diff --git a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h b/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h
index e7e213b..80e0d51 100644
--- a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h
+++ b/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h
@@ -65,4 +65,6 @@
cy_stc_smif_mem_config_t *qspi_get_memory_config(int index);
void qspi_dump_device(cy_stc_smif_mem_device_cfg_t *dev);
+void qspi_deinit(uint32_t smif_id);
+
#endif /* __FLASH_QSPI_H__ */
diff --git a/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.c b/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.c
index 2561ee5..44cff43 100644
--- a/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.c
+++ b/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.c
@@ -197,7 +197,7 @@
static cy_rslt_t cy_retarget_io_pdl_setbaud(CySCB_Type *base, uint32_t baudrate)
{
- cy_rslt_t status;
+ cy_rslt_t result = CY_RSLT_TYPE_ERROR;
uint8_t oversample_value = 8u;
uint8_t frac_bits = 0u;
@@ -205,31 +205,40 @@
Cy_SCB_UART_Disable(base, NULL);
- Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0);
+ result = (cy_rslt_t) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0);
divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + ((baudrate * oversample_value) / 2)) / (baudrate * oversample_value) - 1;
- status = (cy_rslt_t) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, divider);
-
- Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
+ if (result == CY_RSLT_SUCCESS)
+ {
+ result = (cy_rslt_t) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, divider);
+ }
+
+ if (result == CY_RSLT_SUCCESS)
+ {
+ result = Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
+ }
Cy_SCB_UART_Enable(base);
- return status;
+ return result;
}
cy_rslt_t cy_retarget_io_pdl_init(uint32_t baudrate)
{
- cy_rslt_t result;
+ cy_rslt_t result = CY_RSLT_TYPE_ERROR;
- /* Configure and enable UART */
- (void)Cy_SCB_UART_Init(CYBSP_UART_HW, &CYBSP_UART_config, &CYBSP_UART_context);
+ result = (cy_rslt_t)Cy_SCB_UART_Init(CYBSP_UART_HW, &CYBSP_UART_config, &CYBSP_UART_context);
- cy_retarget_io_pdl_setbaud(CYBSP_UART_HW, baudrate);
+ if (result == CY_RSLT_SUCCESS)
+ {
+ result = cy_retarget_io_pdl_setbaud(CYBSP_UART_HW, baudrate);
+ }
- Cy_SCB_UART_Enable(CYBSP_UART_HW);
-
- result = CY_RSLT_SUCCESS;
+ if (result == CY_RSLT_SUCCESS)
+ {
+ Cy_SCB_UART_Enable(CYBSP_UART_HW);
+ }
return result;
}