Infineon: Add support for CYW89829 devices, improve swap with status algorithm speed
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.md b/boot/cypress/BlinkyApp/BlinkyApp.md
index dc29c4c..e85f239 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.md
+++ b/boot/cypress/BlinkyApp/BlinkyApp.md
@@ -4,7 +4,17 @@
Implements a simple Blinky LED application to demonstrate the MCUBootApp bootloader application operation for the boot and upgrade processes.
-It is validated and started by MCUBootApp, which is running on the CM0p core of PSoC™ 6 devices, or CM33 core for the CYW20829 device.
+This demo supports PSoC™ 6 chips with the 1M-, 2M-, and 512K-flash on board; XMC7200, XMC7100; CYW20829/CYW89829 chips with no internal flash.
+The evaluation kits are:
+* `CY8CPROTO-062-4343W`
+* `CY8CKIT-062-WIFI-BT`
+* `CY8CPROTO-062S3-4343W`
+* `CYW920829M2EVB-01`
+* `CYW989829M2EVB-01`
+* `CYBLE-416045-EVAL`
+* `CY8CPROTO-063-BLE`
+* `CY8CKIT-062-BLE`
+* `KIT_XMC72_EVK`
Functionality:
@@ -45,7 +55,7 @@
These values are set by specifying the following macros (default values shown):
`SLOT_SIZE ?= 0x10000` - for slot located in internal flash of PSoC™ 6 chips
`SLOT_SIZE ?= 0x40200` - for slot located in external flash of PsoC™ 6 kits
-`SLOT_SIZE ?= 0x20000` - for slot located in external flash of CYW20829 kits
+`SLOT_SIZE ?= 0x20000` - for slot located in external flash of CYW20829/CYW89829 kits
During pre-build action, the GCC preprocessor is used to generate the target linker script from a template `BlinkyApp_template.ld`.
@@ -55,11 +65,11 @@
### Building an application
-Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE 3.0**:
+Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE**:
- make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.0/gcc
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.2/gcc
- make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 APP_CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1 TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.0/gcc
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 APP_CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1 TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.2/gcc
The supported platforms:
@@ -68,6 +78,7 @@
* PSOC_062_512K
* PSOC_063_1M
* CYW20829
+* CYW89829
* XMC7200
* XMC7100
@@ -130,7 +141,7 @@
make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_single_smif.json IMG_ID=1
-`ERASED_VALUE` defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S. For `CYW20289` default value is `0xff` since it only uses an external flash.
+`ERASED_VALUE` defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S. For `CYW20829` default value is `0xff` since it only uses an external flash.
In the multi-image configuration, an upgrade image for the second application is built using the command:
@@ -146,7 +157,7 @@
This also suggests that the user has already placed a corresponding *.pem key in the \keys folder. The key variables are defined in the root Makefile as SIGN_KEY_FILE and ENC_KEY_FILE
-Refer to [CYW20829.md](../platforms/CYW20829.md) for details of encrypted image build for the CYW20289 platfrom.
+Refer to [CYW20829.md](../platforms/CYW20829.md) for details of encrypted image build for the CYW20829/CYW89829 platforms.
### Complete build flags description
- `BUILDCFG` - The configuration type
@@ -159,7 +170,8 @@
- `PSOC_062_2M`
- `PSOC_062_1M`
- `PSOC_062_512K`
- - `CYW20289`
+ - `CYW20829`
+ - `CYW89829`
- `XMC7200`
- `XMC7100`
- `SLOT_SIZE` - The size of the primary/secondary slot of MCUBootApp. This app will be used with
@@ -171,8 +183,8 @@
- `0x0` - Internal memory.
- `0xff` - External memory.
- `TOOLCHAIN_PATH` - The path to the GCC compiler to use for the build.
- - Example: TOOLCHAIN_PATH=/home/user/ModusToolbox/tools_2.4/gcc
- - Example: TOOLCHAIN_PATH=C:/ModusToolbox/tools_2.4/gcc
+ - Example: TOOLCHAIN_PATH=/home/user/ModusToolbox/tools_3.2/gcc
+ - Example: TOOLCHAIN_PATH=C:/ModusToolbox/tools_3.2/gcc
Flags are set by pre-build action. Result of pre-build can be found in autogenerated file `BlinkyApp/memorymap.mk`.
@@ -192,7 +204,7 @@
Flags passed to `imgtool` for a signature are defined in the `SIGN_ARGS` variable in BlinkyApp.mk.
-For `CYW20829`, `cysecuretools` is used for the image signing.
+For `CYWxx829` and `XMC7x00` platforms, `cysecuretools` is used for the image signing.
### How to program an application
@@ -202,11 +214,11 @@
Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
-The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in the ModusToolbox™ installation folder `ModusToolbox/tools_2.4/openocd`.
+The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in the ModusToolbox™ installation folder `ModusToolbox/tools_3.2/openocd`.
Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION.hex` and `OPENOCD_PATH` paths:
- export OPENOCD_PATH=/Applications/ModusToolbox/tools_2.4/openocd
+ export OPENOCD_PATH=/Applications/ModusToolbox/tools_3.2/openocd
${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
-f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.mk b/boot/cypress/BlinkyApp/BlinkyApp.mk
index 905ef47..0fd575f 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.mk
+++ b/boot/cypress/BlinkyApp/BlinkyApp.mk
@@ -34,6 +34,7 @@
IMG_TYPE ?= BOOT
IMG_ID ?= 1
USE_HW_KEY ?= 0
+DISABLE_WDT_FREE ?= 0
# image type can be BOOT or UPGRADE
IMG_TYPES = BOOT UPGRADE
@@ -45,9 +46,9 @@
# TODO: optimize here and in MCUBootApp.mk
# Output folder
ifeq ($(IMG_ID), 1)
- OUT := $(APP_NAME)/out
+ OUT ?= $(APP_NAME)/out
else
- OUT := $(APP_NAME)/out.id$(IMG_ID)
+ OUT ?= $(APP_NAME)/out.id$(IMG_ID)
endif
# Output folder to contain build artifacts
@@ -86,7 +87,7 @@
include $(PRJ_DIR)/common_libs.mk
#Blinky Release XIP mode workaround
-ifneq ($(PLATFORM), CYW20829)
+ifneq ($(FAMILY), CYW20829)
ifeq ($(BUILDCFG), Release)
ifeq ($(USE_EXTERNAL_FLASH), 1)
CFLAGS_OPTIMIZATION := -Og -g3
@@ -233,11 +234,8 @@
endif
# Overwite path to linker script if custom is required, otherwise default from BSP is used
-ifeq ($(COMPILER), GCC_ARM)
+
LINKER_SCRIPT := $(CUR_APP_PATH)/linker/$(APP_NAME).ld
-else
-$(error Only GCC ARM is supported at this moment)
-endif
ASM_FILES_APP :=
ASM_FILES_APP += $(ASM_FILES_STARTUP)
@@ -277,6 +275,11 @@
$(info $(SIGN_ARGS))
+# Disble wdt free hal call
+ifneq ($(DISABLE_WDT_FREE), 0)
+DEFINES_APP += -DISABLE_WDT_FREE
+endif
+
pre_build:
$(info [PRE_BUILD] - Generating linker script for application $(CUR_APP_PATH)/linker/$(APP_NAME).ld)
@$(CC) -E -x c $(CFLAGS) $(INCLUDE_DIRS) $(CUR_APP_PATH)/linker/$(APP_NAME)_$(CORE)_template$(LD_SUFFIX).ld | grep -v '^#' >$(CUR_APP_PATH)/linker/$(APP_NAME).ld
@@ -298,6 +301,7 @@
$(info CURDIR <-- $(CURDIR))
$(info CUR_APP_PATH <-- $(CUR_APP_PATH))
$(info DEFINES_APP --> $(DEFINES_APP))
+$(info DISABLE_WDT_FREE <-- $(DISABLE_WDT_FREE))
$(info ENC_IMG --> $(ENC_IMG))
$(info ERASED_VALUE <-> $(ERASED_VALUE))
$(info FAMILY <-- $(FAMILY))
diff --git a/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_boot_2M.launch b/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_boot_2M.launch
deleted file mode 100644
index ea1d541..0000000
--- a/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_boot_2M.launch
+++ /dev/null
@@ -1,62 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
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- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
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- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="/Users/rnok/repos/cy_mcuboot_project/cy_mcuboot/boot/cypress/BlinkyApp/out/boot/CY8CKIT-064S2-4343W/Debug/BlinkyApp.elf"/>
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- <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
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diff --git a/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_upgrade_2M.launch b/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_upgrade_2M.launch
deleted file mode 100644
index cc4a413..0000000
--- a/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_upgrade_2M.launch
+++ /dev/null
@@ -1,62 +0,0 @@
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- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
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- <listEntry value="4"/>
- </listAttribute>
- <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"> <memoryBlockExpression address="268566528" label="0x10020000"/> <memoryBlockExpression address="268632064" label="0x10030000"/> <memoryBlockExpression address="268534743" label="0x100183d7"/> </memoryBlockExpressionList> "/>
- <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/boot/cypress/BlinkyApp/Readme.md b/boot/cypress/BlinkyApp/Readme.md
deleted file mode 100644
index ba5340e..0000000
--- a/boot/cypress/BlinkyApp/Readme.md
+++ /dev/null
@@ -1,165 +0,0 @@
-### Blinking LED test application for MCUboot bootloader
-
-### Description
-
-Implements simple Blinky LED CM4 application to demonstrate MCUboot Application operation in terms of BOOT and UPGRADE process.
-
-It is started by MCUboot Application which is running on CM0p.
-
-Functionality:
-
-* Blinks RED led with 2 different rates, depending on type of image - BOOT or UPGRADE.
-* Prints debug info and version of itself to terminal at 115200 baud.
-* Can be built for BOOT slot or UPGRADE slot of bootloader.
-
-Currently supported platforms
-
-* PSOC_062_2M
-* PSOC_062_1M
-* PSOC_062_512K
-
-### Hardware limitations
-
-Since this application is created to demonstrate MCUboot library features and not as reference examples some considerations are taken.
-
-1. Port/pin `P5_0` and `P5_1` used to configure serial port for debug prints. These pins are the most commonly used for serial port connection among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definitions of `CY_DEBUG_UART_TX` and `CY_DEBUG_UART_RX` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
-2. Port `GPIO_PRT13` pin `7U` used to define user connection LED. This pin is the most commonly used for USER_LED connection among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definitions of `LED_PORT` and `LED_PIN` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
-
-### Pre-build action
-
-Pre-build action is implemented for defining start address and size of flash, as well as RAM start address and size for BlinkyApp.
-These values are set by specifing following macros: `-DUSER_APP_SIZE`, `-DUSER_APP_START`, `-DRAM_SIZE`, `-DRAM_START` in makefile.
-
-Pre-build action calls GCC preprocessor which intantiates defines for particular values in `BlinkyApp_template.ld`.
-
-Default values set for currently supported targets:
-* `BlinkyApp.mk` to `-DUSER_APP_START=0x10018000`
-
-**Important**: make sure RAM areas of CM4-based BlinkyApp and CM0p-based MCUBootApp bootloader do not overlap.
-Memory (stack) corruption of CM0p application can cause failure if SystemCall-served operations invoked from CM4.
-
-### Building an application
-
-Root directory for build is **boot/cypress.**
-
-The following command will build regular HEX file of a BlinkyApp for BOOT slot. Substitute `PLATFORM=` to a paltform name you use in all following commands.
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
-
-This have following defaults suggested:
-
- BUILDCFG=Debug
- IMG_TYPE=BOOT
-
-To build UPGRADE image use following command:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x10000
-
- Note: HEADER_OFFSET=%SLOT_SIZE%
-
-Example command-line for single-image:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
-
-**Building Multi-Image**
-
-`BlinkyApp` can be built to use in multi-image bootloader configuration.
-
-To get appropriate artifacts to use with multi image MCUBootApp, makefile flag `HEADER_OFFSET=` can be used.
-
-Example usage:
-
-Considering default config:
-
-* first image BOOT (PRIMARY) slot start `0x10018000`
-* slot size `0x10000`
-* second image BOOT (PRIMARY) slot start `0x10038000`
-
-To get appropriate artifact for second image PRIMARY slot run this command:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT HEADER_OFFSET=0x20000
-
-*Note:* only 2 images are supported at the moment.
-
-**How to build upgrade image for external memory:**
-
-To prepare MCUBootApp for work with external memory please refer to `MCUBootApp/ExternalMemory.md`.
-
-For build BlinkyApp upgrade image for external memory use command:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x7FE8000 ERASED_VALUE=0xff
-
-`HEADER_OFFSET` defines the offset from original boot image address. This one in line above suggests secondary slot will start from `0x18000000`.
-
-`ERASED_VALUE` defines the memory cell contents in erased state. It is `0x00` for PSoC6's internal Flash and `0xff` for S25FL512S.
-
-In case of using muti-image configuration, upgrade image for second application can be built using next command:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x8028000 ERASED_VALUE=0xff
-
- Note: for S25FL512S block address shuld be mutiple by 0x40000
-
-**How to build encrypted upgrade image :**
-
-To prepare MCUBootApp for work with encrypted upgrade image please refer to `MCUBootApp/Readme.md`.
-
-To obtain encrypted upgrade image of BlinkyApp extra flag `ENC_IMG=1` should be passed in command line, for example:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x20000 ENC_IMG=1
-
-This also suggests user already placed corresponing `*.pem` key in `\keys` folder. The key variables are defined in root `Makefile` as `SIGN_KEY_FILE` and `ENC_KEY_FILE`
-
-### Post-build
-
-Post build action is executed at compile time for `BlinkyApp`. In case of build for `PSOC_062_2M` platform it calls `imgtool` from `MCUboot` scripts and adds signature to compiled image.
-
-Flags passed to `imgtool` for signature are defined in `SIGN_ARGS` variable in BlinkyApp.mk.
-
-### How to program an application
-
-Use any preferred tool for programming hex files.
-
-Hex file names to use for programming:
-
-`BlinkyApp` always produce build artifacts in 2 separate folders - `boot` and `upgrade`.
-
-`BlinkyApp` built to run with `MCUBootApp` produces files with name BlinkyApp.hex in `boot` directory and `BlinkyApp_upgrade.hex` in `upgrade` folder. These files are ready to be flashed to the board.
-
-`BlinkyApp_unsigned.hex` hex file is also preserved in both cases for possible troubleshooting.
-
-Files to use for programming are:
-
-`BOOT` - boot/BlinkyApp.hex
-`UPGRADE` - upgrade/BlinkyApp_upgrade.hex
-
-**Flags:**
-- `BUILDCFG` - configuration **Release** or **Debug**
-- `MAKEINFO` - 0 (default) - less build info, 1 - verbose output of compilation.
-- `HEADER_OFFSET` - 0 (default) - no offset of output hex file, 0x%VALUE% - offset for output hex file. Value 0x10000 is slot size MCUboot Bootloader in this example.
-- `IMG_TYPE` - `BOOT` (default) - build image for BOOT slot of MCUboot Bootloader, `UPGRADE` - build image for UPGRADE slot of MCUboot Bootloader.
-- `ENC_IMG` - 0 (default) - build regular upgrade image, `1` - build encrypted upgrade image (MCUBootApp should also be built with this flash set 1)
-
-**NOTE**: In case of `UPGRADE` image `HEADER_OFFSET` should be set to MCUboot Bootloader slot size.
-
-### Example terminal output
-
-When user application programmed in BOOT slot:
-
- ===========================
- [BlinkyApp] BlinkyApp v1.0 [CM4]
- ===========================
- [BlinkyApp] GPIO initialized
- [BlinkyApp] UART initialized
- [BlinkyApp] Retarget I/O set to 115200 baudrate
- [BlinkyApp] Red led blinks with 1 sec period
-
-When user application programmed in UPRADE slot and upgrade procedure was successful:
-
- ===========================
- [BlinkyApp] BlinkyApp v2.0 [+]
- ===========================
-
- [BlinkyApp] GPIO initialized
- [BlinkyApp] UART initialized
- [BlinkyApp] Retarget I/O set to 115200 baudrate
- [BlinkyApp] Red led blinks with 0.25 sec period
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld
index 4b8b0d8..704c3b4 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld
@@ -1,5 +1,5 @@
/***************************************************************************//**
-* \file cyw20829_ns.ld
+* \file cyw20829_ns_flash_sahb.ld
* \version 1.0.0
*
* Linker file for the GNU C compiler.
@@ -8,7 +8,7 @@
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
-* \note The entry point location is fixed and starts at 0x10000000. The valid
+* \note The entry point location starts at 0x0401e000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
@@ -19,7 +19,8 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
+* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -41,6 +42,9 @@
GROUP(libgcc.a libc.a libm.a libnosys.a)
ENTRY(Reset_Handler)
+/* Memory reserved for Bootstrap code and data */
+BOOTSTRAP_SIZE = DEFINED(APP_BOOTSTRAP_SIZE) ? APP_BOOTSTRAP_SIZE : 0x00002400 ;
+
/* The size of the stack section at the end of CM4 SRAM */
STACK_SIZE = 0x1000;
@@ -49,39 +53,38 @@
FLASH_START_ADDR_SAHB = 0x60000000 + USER_APP_START_ADDR;
FLASH_START_ADDR_CBUS = 0x08000000 + USER_APP_START_ADDR;
RAM_START_ADDR_SAHB = 0x20000000;
-RAM_START_ADDR_CBUS = 0x04000000;
RAM_END_ADDR_SAHB = 0x20040000; /* 256K */
-RAM_END_ADDR_CBUS = 0x04040000; /* 256K */
+
+RAM_START_ADDR_CBUS = 0x20000000;
+RAM_END_ADDR_CBUS = 0x20040000; /* 256K */
+
FLASH_END_ADDR_SAHB = 0x60080000; /* 512K */
-BOOTSTRAP_OFFSET_FLASH = 0x00000050; /* toc2=0x10, l1_desc=0x1C, sign_header=0x20, padding=0x4 (encrypted data should be aligned to 0x10 boundary) */
-BOOTSTRAP_OFFSET_RAM = 0x0001E000; /* was 0x00004000 Modify this value to change the size of Bootstrap code + Data */
-APPCODE_OFFSET_FLASH = 0x00002200;
+BOOTSTRAP_OFFSET_FLASH = 0x00000050; /* toc2=0x10, l1_desc=0x1C, sign_header=0x20 */
RAMVECTORS_ALIGNMENT = 512;
+FLASH_ALIGNMENT_SIZE = 0x00000200;
-/* Memory reserved for Bootstrap code and data */
-BOOTSTRAP_SIZE = RAM_END_ADDR_SAHB - RAM_START_ADDR_SAHB - BOOTSTRAP_OFFSET_RAM; /* 0x00002000 */
/* vma for bootstrap code region */
-CODE_VMA = RAM_START_ADDR_CBUS + BOOTSTRAP_OFFSET_RAM; /* 0x0401E000 */
+CODE_VMA = RAM_START_ADDR_CBUS + (RAM_END_ADDR_SAHB - RAM_START_ADDR_SAHB - BOOTSTRAP_SIZE); /* 0x2003DC00 */
/* lma for bootstrap code region */
-CODE_LMA = FLASH_START_ADDR_SAHB + BOOTSTRAP_OFFSET_FLASH; /* 0x6000004C */
+CODE_LMA = FLASH_START_ADDR_SAHB + BOOTSTRAP_OFFSET_FLASH; /* 0x60000050 */
/* Maximum bootstrap code + data size */
-CODE_BS_SIZE = BOOTSTRAP_SIZE; /* 8KB */
+CODE_BS_SIZE = BOOTSTRAP_SIZE; /* 9KB */
/* vma for bootstrap data region */
-DATA_BS_VMA = RAM_START_ADDR_SAHB + BOOTSTRAP_OFFSET_RAM; /* 0x2001E000 */
+DATA_BS_VMA = RAM_END_ADDR_SAHB - BOOTSTRAP_SIZE; /* 0x2003DC00 */
/* vma for bootstrap and app data region */
DATA_VMA = RAM_START_ADDR_SAHB; /* 0x20000000 */
/* vma for appCodeRam region */
-DATA_CBUS_VMA = RAM_START_ADDR_CBUS; /* 0x04000000 */
+DATA_CBUS_VMA = RAM_START_ADDR_CBUS; /* 0x20000000 */
/* lma for bootstrap and app data region */
-DATA_LMA = CODE_LMA + CODE_BS_SIZE; /* 0x6000204C */
+DATA_LMA = CODE_LMA + CODE_BS_SIZE; /* 0x60002450 */
/* data size */
-DATA_SIZE = RAM_END_ADDR_SAHB - DATA_VMA - BOOTSTRAP_SIZE; /* 0x1E000 */
+DATA_SIZE = RAM_END_ADDR_SAHB - DATA_VMA - BOOTSTRAP_SIZE; /* 0x3DC00 */
/* vma for application XIP region */
-XIP_VMA = FLASH_START_ADDR_CBUS + APPCODE_OFFSET_FLASH; /* 0x08002200 */
+XIP_VMA = FLASH_START_ADDR_CBUS + BOOTSTRAP_SIZE + FLASH_ALIGNMENT_SIZE; /* 0x08002600 */
/* lma for application XIP region */
-XIP_LMA = FLASH_START_ADDR_SAHB + APPCODE_OFFSET_FLASH; /* 0x60002200 */
+XIP_LMA = FLASH_START_ADDR_SAHB + BOOTSTRAP_SIZE + FLASH_ALIGNMENT_SIZE; /* 0x60002600 */
/* size of XIP region */
XIP_SIZE = FLASH_END_ADDR_SAHB - XIP_LMA;
/* Total size of SRAM */
@@ -161,7 +164,7 @@
* size of stack_dummy section */
. = ALIGN(32);
__StackTop = RAM_START_ADDR_SAHB + STACK_SIZE;
- __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ __StackLimit = __StackTop - STACK_SIZE;
PROVIDE(__stack = __StackTop);
. = ALIGN(RAMVECTORS_ALIGNMENT);
@@ -189,9 +192,12 @@
*cy_smif.o(.text*)
*cy_smif_memslot.o(.text*)
*cy_smif_sfdp.o(.text*)
- *cy_gpio.o(.text*)
- *cy_smif_hybrid_sect.o(.text*)
+ KEEP( *(.text.cy_os_common*))
+ KEEP (*(.text.cy_btstack_common*))
+ KEEP (*(.text.cy_btstack_gatt*))
+ KEEP (*(.text.cy_ipc*))
+ KEEP (*(.text.cy_btstack_porting*))
. = ALIGN(4);
__app_text_ram_end__ = .;
@@ -235,10 +241,6 @@
KEEP(*(.jcr*))
. = ALIGN(4);
- . = ALIGN(4);
- KEEP(*(.cy_l2func*))
- . = ALIGN(4);
-
__data_end__ = .;
} > data
@@ -310,24 +312,24 @@
. = ALIGN(4);
/* startup code */
- *ns_start_cyw20829.o(.text*)
- *ns_system_cyw20829.o(.text*)
+ *startup_cat1b_cm33.o(.text*)
+ *system_cyw20829.o(.text*)
/* drivers */
*cy_device.o(.text*)
*cy_btss.o(.text*)
- *cy_gpio.o(.text*)
*cy_sysclk_v2.o(.text*)
*cy_syspm_v2.o(.text*)
*cy_sysint_v2.o(.text*)
*cy_syslib*.o(.text*)
*ppu_v1.o(.text*)
*cy_mpc.o(.text*)
- *cy_pd_ppu.o(.text*)
- *cy_smif.o(.text*)
- *cy_smif_memslot.o(.text*)
- *cy_smif_sfdp.o(.text*)
- *cyhal_system.o(.text*)
+ *cy_syspm_ppu.o(.text*)
+
+ *memcpy*.o (.text*) /* add memcpy from the NewLib library here*/
+ *memset*.o (.text*) /* add memcpy from the NewLib library here*/
+ *memmove*.o (.text*) /* add memcpy from the NewLib library here*/
+ *s_fabs.o (.text*)
KEEP(*(.cy_l1func*))
@@ -356,13 +358,12 @@
. = ALIGN(4);
/* startup code */
- *ns_start_cyw20829.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
- *ns_system_cyw20829.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *startup_cat1b_cm33.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *system_cyw20829.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
/* drivers */
*cy_device.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_btss.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
- *cy_gpio.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_sysclk_v2.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_syspm_v2.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_sysint_v2.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
@@ -370,33 +371,26 @@
*ppu_v1.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_mpc.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
*cy_pd_ppu.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
- *cy_smif.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
- *cy_smif_memslot.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
- *cy_smif_sfdp.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
- *cycfg_qspi_memslot.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
- *cyhal_system.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
KEEP(*(.cy_l1data*))
. = ALIGN(4);
-
__bootstrapData_end__ = .;
- __bootstrap_size_end__ = .;
} > bsData
+ __bootstrap_size_end__ = .;
.bootstrapBss (NOLOAD):
{
. = ALIGN(4);
__bootstrap_bss_start__ = .;
/* startup code */
- *ns_start_cyw20829.o(.bss* COMMON)
- *ns_system_cyw20829.o(.bss* COMMON)
+ *startup_cat1b_cm33.o(.bss* COMMON)
+ *system_cyw20829.o(.bss* COMMON)
/* drivers */
*cy_device.o(.bss* COMMON)
*cy_btss.o(.bss* COMMON)
- *cy_gpio.o(.bss* COMMON)
*cy_sysclk_v2.o(.bss* COMMON)
*cy_syspm_v2.o(.bss* COMMON)
*cy_sysint_v2.o(.bss* COMMON)
@@ -404,10 +398,6 @@
*ppu_v1.o(.bss* COMMON)
*cy_mpc.o(.bss* COMMON)
*cy_pd_ppu.o(.bss* COMMON)
- *cy_smif.o(.bss* COMMON)
- *cy_smif_memslot.o(.bss* COMMON)
- *cy_smif_sfdp.o(.bss* COMMON)
-
KEEP(*(.cy_l1bss*))
. = ALIGN(4);
@@ -427,11 +417,8 @@
. = ALIGN(4);
__text_begin = .;
- *(EXCLUDE_FILE(*cy_gpio.o
- *cy_smif.o
- *cy_smif_memslot.o
- *cy_smif_sfdp.o
- *cy_smif_hybrid_sect.o) .text*)
+ *(EXCLUDE_FILE(*cy_smif.o
+ *cy_smif_memslot.o *cy_smif_sfdp.o) .text*)
KEEP(*(.init))
KEEP(*(.fini))
@@ -497,7 +484,7 @@
}
/* start of bootstrap code sahb address */
-__bootstrap_start_addr__ = RAM_START_ADDR_SAHB + BOOTSTRAP_OFFSET_RAM;
+__bootstrap_start_addr__ = RAM_END_ADDR_SAHB - BOOTSTRAP_SIZE;
/* bootstrap size */
__bootstrap_size__ = __bootstrap_size_end__ - __bootstrap_start_addr__;
diff --git a/boot/cypress/BlinkyApp/main.c b/boot/cypress/BlinkyApp/main.c
index 5bc5a59..444f858 100644
--- a/boot/cypress/BlinkyApp/main.c
+++ b/boot/cypress/BlinkyApp/main.c
@@ -57,10 +57,12 @@
printf("[BlinkyApp] Image type: " IMAGE_TYPE " on %s core\r\n", detect_core_message);
- /* Disable watchdog timer to mark successful start up of application. */
+#if !defined(DISABLE_WDT_FREE)
+ /* Disable watchdog timer to mark successful start up of application. The default BlikyApp flow */
cyhal_wdt_free(NULL);
printf(WATCHDOG_FREE_MESSAGE);
+#endif /* !(DISABLE_WDT_FREE) */
for (;;) {
/* Toggle the user LED periodically */
diff --git a/boot/cypress/MCUBootApp/ExternalMemory.md b/boot/cypress/MCUBootApp/ExternalMemory.md
index 9a339b3..c2a6ca4 100644
--- a/boot/cypress/MCUBootApp/ExternalMemory.md
+++ b/boot/cypress/MCUBootApp/ExternalMemory.md
@@ -1,6 +1,6 @@
### Support of secondary slot in external memory for PSoC™ 6 devices
-* For the CYW20829 external memory support, see the [CYW20829.md](../platforms/CYW20829.md) file.
+* For the CYW20829/CYW89829 external memory support, see the [CYW20829.md](../platforms/CYW20829.md) file.
#### Description
@@ -68,7 +68,7 @@
In the XIP mode firmware image can be placed in the external memory and executed from there directly. This mode is useful for devices with small internal flash or when one wishes to reserve internal flash for other purposes.
-On CYW20829 platform XIP mode is always used due to absence of internal memory.
+On CYW20829/CYW89829 platforms XIP mode is always used due to absence of internal memory.
This is optional for PSoC™ 6 devices. The JSON flash map should contain `"mode": "XIP"` in the `"external_flash" section`. `USE_XIP` flag is added to auto-generated `memorymap.mk` on pre-build action.
@@ -100,7 +100,7 @@
The MCUBootApp can be programmed similarly to described in the [MCUBootApp.md](MCUBootApp.md) file:
- export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
+ export OPENOCD=/Applications/ModusToolbox/tools_3.2/openocd
${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
-f ${OPENOCD}/scripts/interface/kitprog3.cfg \
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.md b/boot/cypress/MCUBootApp/MCUBootApp.md
index ddbbea1..410bd4a 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.md
+++ b/boot/cypress/MCUBootApp/MCUBootApp.md
@@ -2,7 +2,7 @@
### Solution description
-This solution demonstrates the operation of MCUboot on Cypress PSoC™ 6 and CYW20829 devices.
+This solution demonstrates the operation of MCUboot on Cypress PSoC™ 6 and CYWxx829 devices.
* Single-/Multi-image operation modes
* Overwrite/Swap upgrade modes
@@ -11,12 +11,13 @@
* Revert bad upgrade images
* Secondary slots located in external flash
-This demo supports PSoC™ 6 chips with the 1M-, 2M-, and 512K-flash on board, and the CYW20829 chip with no internal flash.
+This demo supports PSoC™ 6 chips with the 1M-, 2M-, and 512K-flash on board; XMC7200, XMC7100; CYW20829/CYW89829 chips with no internal flash.
The evaluation kits are:
* `CY8CPROTO-062-4343W`
* `CY8CKIT-062-WIFI-BT`
* `CY8CPROTO-062S3-4343W`
* `CYW920829M2EVB-01`
+* `CYW989829M2EVB-01`
* `CYBLE-416045-EVAL`
* `CY8CPROTO-063-BLE`
* `CY8CKIT-062-BLE`
@@ -37,7 +38,7 @@
The actual addresses are provided in corresponding platform doc files:
- [PSOC6.md](../platforms/PSOC6.md)
-- [CYW20289.md](../platforms/CYW20829.md)
+- [CYW20829.md](../platforms/CYW20829.md)
#### How to modify the flash map
@@ -193,7 +194,7 @@
. . .
```
###### Service RAM Application
-The CYW20829 platform has a hardware-supported security counter. For more details on rollback protection support, refer to the [CYW20289.md](../platforms/CYW20829.md) file.
+The CYW20829/CYW89829 platforms has a hardware-supported security counter. For more details on rollback protection support, refer to the [CYW20829.md](../platforms/CYW20829.md) file.
The mentioned feature requires a dedicated area in the flash memory to store the Service RAM Application and other required data. The layout of these areas is defined in the `"service_app"` JSON section:
```
@@ -407,15 +408,15 @@
The MCUBootApp linker script also contains the special section `public_ram`, which serves as a shared RAM area between the CM0p and CM4 cores. When CM4 and CM0p cores perform operations with internal flash, this area is used for interprocessor data sharing.
-#### CYW20829 RAM
+#### CYW20829/CYW89829 RAM
-Only one CM33 core is used in the CYW20829 chips, so there are no restrictions for the RAM usage by the layer1 and layer2 applications (i.e. MCUBootApp and BlinkyApp).
+Only one CM33 core is used in the CYW89829/CYW89829 chips, so there are no restrictions for the RAM usage by the layer1 and layer2 applications (i.e. MCUBootApp and BlinkyApp).
### Hardware cryptography acceleration
Cypress PSoC™ 6 MCU family supports hardware acceleration of the cryptography based on the mbedTLS Library via a shim layer. The implementation of this layer is supplied as the separate submodule `cy-mbedtls-acceleration`. The hardware acceleration of the cryptography shortens the boot time by more than four times compared to the software implementation (observation results).
-The CYW20289 chip has hardware acceleration of the SHA256 algorithm only, and in other cases, uses pure software implementation of the cryptography based on MbedTLS.
+The CYW20829/CYW89829 chips has hardware acceleration of the SHA256 algorithm only, and in other cases, uses pure software implementation of the cryptography based on MbedTLS.
To enable the hardware acceleration in `MCUBootApp`, pass flag `USE_CRYPTO_HW=1` to `make` during the build.
@@ -632,15 +633,15 @@
`USE_HW_ROLLBACK_PROT` `make` flag is set to 1 in auto-generated `memorymap.mk`.
-The rollback protection feature is currently supported on CYW20829 devices in Secure mode only.
+The rollback protection feature is currently supported on CYW20829/CYW89829 devices in Secure mode only.
### Building solution
Folder `boot/cypress` contains make-files infrastructure for building MCUBootApp bootloader applications. Example build commands are provided later in this document for different build configurations.
-Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE 3.0**:
+Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE**:
- make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.0/gcc
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.2/gcc
* Build MCUBootApp in the `Debug` configuration for Single-image mode with swap upgrade.
@@ -702,14 +703,14 @@
On PSoC™ 6, an upgrade image can be encrypted and then programmed to the corresponding Secondary slot of MCUBootApp. It is then decrypted and transferred to the primary slot using the preferred upgrade method. For more details on the encrypted image implementation, refer to the [PSOC6.md](../platforms/PSOC6.md) file.
-On CYW20829, an encrypted image is supported in both slots. The firmware here is located in external memory, so, the chip's SMIF block encrypted eXecution In Place (XIP) feature is used. Encrypted firmware is placed directly in the primary slot and is decrypted on the fly. The encrypted upgrade image is first validated by MCUBootApp in the secondary slot and then transferred to the primary slot as it is. For more details on the encrypted image implementation, refer to the [CYW20289.md](../platforms/CYW20829.md) file.
+On CYW20829/CYW89829, an encrypted image is supported in both slots. The firmware here is located in external memory, so, the chip's SMIF block encrypted eXecution In Place (XIP) feature is used. Encrypted firmware is placed directly in the primary slot and is decrypted on the fly. The encrypted upgrade image is first validated by MCUBootApp in the secondary slot and then transferred to the primary slot as it is. For more details on the encrypted image implementation, refer to the [CYW20829.md](../platforms/CYW20829.md) file.
### Rollback protection
MCUboot supports the security counter implementation to provide downgrade prevention. This mechanism allows the user to explicitly restrict the possibility to execute/upgrade images whose security counters are less than the current firmware counter. So, it can be guaranteed, that obsolete firmware with possible vulnerabilities can not be executed on the device.
-**Currently, only the CYW20829 platform supports the hardware rollback counter protection.**
-For more details on the implementation, refer to the [CYW20289.md](../platforms/CYW20829.md) file.
+**Currently, only the CYW20829/CYW89829 platforms supports the hardware rollback counter protection.**
+For more details on the implementation, refer to the [CYW20829.md](../platforms/CYW20829.md) file.
### Complete build flags and parameters description
@@ -717,18 +718,18 @@
`MCUBOOT_LOG_LEVEL` - Can be set at `MCUBOOT_LOG_LEVEL_DEBUG` to enable the verbose output of MCUBootApp.
`ENC_IMG` - When set to `1`, it enables the encrypted image support in MCUBootApp.
-`APP_DEFAULT_POLICY` - The path to a policy file to use for signing MCUBootApp and user application (BlinkyApp) on the CYW20829 platform.
+`APP_DEFAULT_POLICY` - The path to a policy file to use for signing MCUBootApp and user application (BlinkyApp) on the CYWxx829 platforms.
`USE_BOOTSTRAP` - When set to `1` and Swap mode is enabled, the application in the secondary slot will overwrite the primary slot if the primary slot application is invalid.
-`USE_CRYPTO_HW` - When set to `1`, uses the hardware-accelerated cryptography on the PSoC™ 6 platform, and SHA-256 HW acceleration for the CYW20289 platform.
-`LSC` - The lifecycle state of the chip. Possible options are `SECURE` and `NORMAL_NO_SECURE` (effective on CYW20829 chip only).
+`USE_CRYPTO_HW` - When set to `1`, uses the hardware-accelerated cryptography on the PSoC™ 6 platform, and SHA-256 HW acceleration for the CYW20829/CYW89829 platforms.
+`LSC` - The lifecycle state of the chip. Possible options are `SECURE` and `NORMAL_NO_SECURE` (effective on CYW20829/CYW89829 chips only).
`DEVICE` - is used to set a particular MPN for a platform since multiple MPNs are associated with one platform, for example:
`PLATFORM=PSOC_062_1M DEVICE=CY8C6347BZI-BLD53`
The next flags will be set by script in auto-generated makefile 'memorymap.mk':
`MCUBOOT_IMAGE_NUMBER` - The number of images to be supported by the current build of MCUBootApp.
`USE_OVERWRITE` - `0` - Use swap with Scratch upgrade mode, `1` - use Overwrite only upgrade.
-`USE_EXTERNAL_FLASH` - When set to `1`, it enables the external memory support on the PSoC™ 6 platform. This value is always set to `1` on CYW20829.
-`USE_HW_ROLLBACK_PROT` - When set to `1`, it enables the hardware rollback protection on the CYW20829 platform with Secure mode enabled.
+`USE_EXTERNAL_FLASH` - When set to `1`, it enables the external memory support on the PSoC™ 6 platform. This value is always set to `1` on CYW20829 and CYW89829 platforms.
+`USE_HW_ROLLBACK_PROT` - When set to `1`, it enables the hardware rollback protection on the CYW20829/CYW89829 platforms with Secure mode enabled.
Adding `clean` to `make` will clean the build folder, and files boot/cypress/MCUBootApp/memorymap.mk and boot/cypress/platforms/memory/memorymap.h will be removed and re-generated.
@@ -738,7 +739,7 @@
1. The direct usage of OpenOCD.
-The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in the installation folder `ModusToolbox/tools_2.4/openocd`.
+The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in the installation folder `ModusToolbox/tools_3.2/openocd`.
Set environment variable `OPENOCD` to the path to the openocd folder in ModusToolbox™. Exact commands for programming images are provided in the corresponding platform readme files.
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.mk b/boot/cypress/MCUBootApp/MCUBootApp.mk
index dfac125..31dd40f 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.mk
+++ b/boot/cypress/MCUBootApp/MCUBootApp.mk
@@ -39,11 +39,16 @@
ENC_IMG ?= 0
USE_HW_KEY ?= 0
USE_BOOTSTRAP ?= 1
-MCUBOOT_LOG_LEVEL ?= MCUBOOT_LOG_LEVEL_DEBUG
USE_SHARED_SLOT ?= 0
FIH_PROFILE_LEVEL_LIST := OFF LOW MEDIUM HIGH
FIH_PROFILE_LEVEL ?= MEDIUM
+ifeq ($(BUILDCFG), Release)
+MCUBOOT_LOG_LEVEL ?= MCUBOOT_LOG_LEVEL_INFO
+else
+MCUBOOT_LOG_LEVEL ?= MCUBOOT_LOG_LEVEL_DEBUG
+endif
+
ifneq ($(COMPILER), GCC_ARM)
$(error Only GCC ARM is supported at this moment)
endif
@@ -76,7 +81,7 @@
$(PYTHON_PATH) scripts/memorymap_rework.py run -p $(PLATFORM_CONFIG) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory -n memorymap > $(CUR_APP_PATH)/memorymap.mk
else
$(CUR_APP_PATH)/memorymap.mk:
- $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h > $(CUR_APP_PATH)/memorymap.mk
+ $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h > $(CUR_APP_PATH)/memorymap.mk
endif
DEFINES_APP += -DCY_FLASH_MAP_JSON
endif
@@ -145,7 +150,7 @@
INCLUDE_DIRS_MBEDTLS_MXCRYPTO := $(CY_LIBS_PATH)/cy-mbedtls-acceleration
INCLUDE_DIRS_MBEDTLS_MXCRYPTO += $(CY_LIBS_PATH)/cy-mbedtls-acceleration/COMPONENT_CAT1/include
-ifeq ($(PLATFORM), CYW20829)
+ifeq ($(FAMILY), CYW20829)
INCLUDE_DIRS_MBEDTLS_MXCRYPTO += $(CY_LIBS_PATH)/cy-mbedtls-acceleration/COMPONENT_CAT1/mbedtls_$(CRYPTO_ACC_TYPE)
SOURCES_MBEDTLS_MXCRYPTO := $(wildcard $(CY_LIBS_PATH)/cy-mbedtls-acceleration/COMPONENT_CAT1/mbedtls_$(CRYPTO_ACC_TYPE)/*.c)
DEFINES_APP += -Dcy_stc_cryptolite_context_sha256_t=cy_stc_cryptolite_context_sha_t
@@ -177,12 +182,12 @@
# Encrypted image support
ifeq ($(ENC_IMG), 1)
DEFINES_APP += -DENC_IMG=1
-ifeq ($(PLATFORM), CYW20829)
+ifeq ($(FAMILY), CYW20829)
DEFINES_APP += -DMCUBOOT_ENC_IMAGES_XIP
endif
# Use maximum optimization level for PSOC6 encrypted image with
# external flash so it would fit into 0x18000 size of MCUBootApp
-ifneq ($(PLATFORM), CYW20829)
+ifneq ($(FAMILY), CYW20829)
ifeq ($(BUILDCFG), Debug)
ifeq ($(USE_EXTERNAL_FLASH), 1)
CFLAGS_OPTIMIZATION := -Os -g3
@@ -245,14 +250,22 @@
ASM_FILES_APP += $(ASM_FILES_STARTUP)
# Pass variables to linker script and overwrite path to it, if custom is required
-ifeq ($(COMPILER), GCC_ARM)
-LDFLAGS += $(LDFLAGS_DEFSYM)
-LINKER_SCRIPT := $(CUR_APP_PATH)/$(APP_NAME)_$(CORE).ld
ifeq ($(FAMILY), XMC7000)
-LINKER_SCRIPT := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/linker.ld
-endif
+ LINKER_SCRIPT := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/linker.ld
else
-$(error Only GCC ARM is supported at this moment)
+ LINKER_SCRIPT := $(CUR_APP_PATH)/$(APP_NAME)_$(CORE).ld
+endif
+
+ifeq ($(COMPILER), GCC_ARM)
+ LDFLAGS += $(LDFLAGS_DEFSYM)
+else ifeq ($(COMPILER), IAR)
+ $(error $(COMPILER) not supported at this moment)
+
+else ifeq ($(COMPILER), ARM)
+ $(error $(COMPILER) not supported at this moment)
+
+else
+ $(error $(COMPILER) not supported at this moment)
endif
###############################################################################
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
index b5fcfca..f80e9da 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
@@ -65,7 +65,7 @@
*/
ram (rwx) : ORIGIN = 0x08000A00, LENGTH = 0x1F600
flash (rx) : ORIGIN = 0x10000000, LENGTH = BOOTLOADER_SIZE
- smif_struct (rx) : ORIGIN = 0x10000000 + BOOTLOADER_SIZE - 0x170, LENGTH = 0x170
+ smif_struct (rx) : ORIGIN = 0x10000000 + BOOTLOADER_SIZE - 0x170, LENGTH = 0x170
/* This is an unprotected public RAM region, with the placed .cy_sharedmem.
* This region is used to place objects that require full access from both cores.
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch b/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch
deleted file mode 100644
index cde42b8..0000000
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch
+++ /dev/null
@@ -1,62 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off set remotetimeout 15"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${cy_tools_path:openocd}/bin/openocd"/>
- <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s "${openocd_path}/../scripts" -c "set QSPI_FLASHLOADER bsps/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/CAT1C_SMIF.FLM" -c "source [find interface/kitprog3.cfg]" -c "transport select swd" -c "puts stderr {Started by GNU MCU Eclipse}" -c "source [find target/cat1c.cfg]" -c "gdb_port 3333" -c "cat1c sflash_restrictions 1" -c "init; reset init""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
- <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="mon reset run mon cat1c reset_halt sysresetreq flushregs mon gdb_sync stepi"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="init"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
- <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="./out/PSOC_062_2M/Debug/MCUBootApp.elf"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
- <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_tools_path:CY_TOOL_arm-none-eabi-gdb_EXE}"/>
- <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
- <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
- <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
- <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
- <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="/Users/rnok/repos/xmc7200/cy_mcuboot/boot/cypress/MCUBootApp/out/XMC7200/Debug/MCUBootApp.elf"/>
- <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="cy_mcuboot"/>
- <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
- <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
- <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
- <listEntry value="/cy_mcuboot"/>
- </listAttribute>
- <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
- <listEntry value="4"/>
- </listAttribute>
- <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"> <memoryBlockExpression address="268828484" label="0x1005ff44"/> <memoryBlockExpression address="268697600" label="0x10040000"/> </memoryBlockExpressionList> "/>
- <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CYW20829_Debug.launch b/boot/cypress/MCUBootApp/MCUBootApp_CYW20829_Debug.launch
deleted file mode 100644
index 3b3300a..0000000
--- a/boot/cypress/MCUBootApp/MCUBootApp_CYW20829_Debug.launch
+++ /dev/null
@@ -1,59 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
- <stringAttribute key="com.cypress.studio.launch.mode" value="debug"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="/Users/rnok/Downloads/ASSETS/cyopenocd/openocd_4.3_1445/bin/openocd"/>
- <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s "/Users/rnok/Downloads/ASSETS/cyopenocd/openocd_4.3_1445/scripts" -s "./libs/TARGET_PSVP-CYW20829/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource" -c "set SMIF_LOADER /Users/rnok/repos/cyw20829/AnyCloud_CYW20829_Blinky_App/./libs/TARGET_PSVP-CYW20829/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/CYW208xx_SMIF.FLM" -c "source [find interface/kitprog3.cfg]" -c "puts stderr {Started by GNU MCU Eclipse}" -c "source [find target/cyw208xx.cfg]" -c "cyw208xx.cm33 configure -rtos auto -rtos-wipe-on-reset-halt 1" -c "gdb_breakpoint_override hard" -c "init; reset init""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
- <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="flushregs"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="init"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${cy_prj_path}/build/PSVP-CYW20829/Debug/mtb-example-anycloud-blinky.bin"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
- <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="/Users/rnok/repos/cyw20829/cy_mcuboot/boot/cypress/MCUBootApp/out/CYW20829/Debug/MCUBootApp.elf"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
- <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_tools_path:CY_TOOL_arm-none-eabi-gdb_EXE}"/>
- <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
- <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
- <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
- <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="/Users/rnok/repos/cyw20829/cy_mcuboot/boot/cypress/MCUBootApp/out/CYW20829/Debug/MCUBootApp.elf"/>
- <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="MCUBootApp_CYW20829_Debug"/>
- <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
- <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
- <listAttribute key="org.eclipse.debug.ui.favoriteGroups">
- <listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
- </listAttribute>
- <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/>
- <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/boot/cypress/MCUBootApp/README.md b/boot/cypress/MCUBootApp/README.md
deleted file mode 100644
index 6a70b21..0000000
--- a/boot/cypress/MCUBootApp/README.md
+++ /dev/null
@@ -1,223 +0,0 @@
-### Port of MCUboot library to be used with Cypress targets
-
-**Solution Description**
-
-Given solution demonstrates operation of MCUboot on Cypress' PSoC6 device.
-
-There are two applications implemented:
-* MCUBootApp - PSoC6 MCUboot-based bootloading application;
-* BlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE;
-
-Cypress boards, that can be used with this evaluation example:
-- CY8CPROTO-062-4343W - PSoC 6 2M on board
-- CY8CKIT-062-WIFI-BT - PSoC 6 1M on board
-- CY8CPROTO-062S3-4343W - PSoC 6 512K on board
-The default flash map implemented is the following:
-
-Single-image mode.
-
-`[0x10000000, 0x10018000]` - MCUBootApp (bootloader) area;
-
-`[0x10018000, 0x10028000]` - primary slot for BlinkyApp;
-
-`[0x10028000, 0x10038000]` - secondary slot for BlinkyApp;
-
-`[0x10038000, 0x10039000]` - scratch area (not used);
-
-Size of slots `0x10000` - 64kb
-
-MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses completely SW implementation of cryptographic functions based on Mbed TLS Library.
-
-**Important**: make sure primary, secondary slot and bootloader app sizes are appropriate and correspond to flash area size defined in Applications' linker files.
-
-**Important**: make sure RAM areas of CM0p-based MCUBootApp bootloader and CM4-based BlinkyApp do not overlap.
-Memory (stack) corruption of CM0p application can cause failure if SystemCall-served operations invoked from CM4.
-
-### Hardware cryptography acceleration
-
-Cypress PSOC6 MCU family supports hardware acceleration of cryptography based on Mbed TLS Library via shim layer. Implementation of this layer is supplied as separate submodule `cy-mbedtls-acceleration`. HW acceleration of cryptography shortens boot time more then 4 times, comparing to software implementation (observation results).
-
-To enable hardware acceleration in `MCUBootApp` pass flag `USE_CRYPTO_HW=1` to `make` while build.
-
-Hardware acceleration of cryptography is enabled for PSOC6 devices by default.
-
-### How to modify memory map
-
-__Option 1.__
-
-Navigate to `sysflash.h` and modify the flash area(s) / slots sizes to meet your needs.
-
-__Option 2.__
-
-Navigate to `sysflash.h`, uncomment `memory_EXT_DESC` definition.
-Now define and initialize `struct flash_area *boot_area_descs[]` with flash memory addresses and sizes you need at the beginning of application, so flash APIs from `memory.c` will use it.
-
-__Note:__ for both options make sure you have updated `MCUBOOT_MAX_IMG_SECTORS` appropriatery with sector size assumed to be 512.
-
-**How to override the flash map values during build process:**
-
-Navigate to MCUBootApp.mk, find section `DEFINES_APP +=`
-Update this line and or add similar for flash map parameters to override.
-
-The possible list could be:
-
-* MCUBOOT_MAX_IMG_SECTORS
-* memory_EXT_DESC
-* CY_BOOT_SCRATCH_SIZE
-* CY_BOOT_BOOTLOADER_SIZE
-* CY_BOOT_PRIMARY_1_SIZE
-* CY_BOOT_SECONDARY_1_SIZE
-* CY_BOOT_PRIMARY_2_SIZE
-* CY_BOOT_SECONDARY_2_SIZE
-
-As an example in a makefile it should look like following:
-
-`DEFINES_APP +=-Dmemory_EXT_DESC`
-
-`DEFINES_APP +=-DMCUBOOT_MAX_IMG_SECTORS=512`
-
-`DEFINES_APP +=-DCY_BOOT_PRIMARY_1_SIZE=0x15000`
-
-**Multi-Image Operation**
-
-Multi-image operation considers upgrading and verification of more then one image on the device.
-
-To enable multi-image operation define `MCUBOOT_IMAGE_NUMBER` in `MCUBootApp/config/mcuboot_config.h` file should be set to 2 (only dual-image is supported at the moment). This could also be done on build time by passing `MCUBOOT_IMAGE_NUMBER=2` as parameter to `make`.
-
-Default value of `MCUBOOT_IMAGE_NUMBER` is 1, which corresponds to single image configuratios.
-
-In multi-image operation (two images are considered for simplicity) MCUboot Bootloader application operates as following:
-
-* Verifies Primary_1 and Primary_2 images;
-* Verifies Secondary_1 and Secondary_2 images;
-* Upgrades Secondary to Primary if valid images found;
-* Boots image from Primary_1 slot only;
-* Boots Primary_1 only if both - Primary_1 and Primary_2 are present and valid;
-
-This ensures two dependent applications can be accepted by device only in case both images are valid.
-
-**Default Flash map for Multi-Image operation:**
-
-`0x10000000 - 0x10018000` - MCUboot Bootloader
-
-`0x10018000 - 0x10028000` - Primary_1 (BOOT) slot of Bootloader
-
-`0x10028000 - 0x10038000` - Secondary_1 (UPGRADE) slot of Bootloader
-
-`0x10038000 - 0x10048000` - Primary_2 (BOOT) slot of Bootloader
-
-`0x10048000 - 0x10058000` - Secondary_2 (UPGRADE) slot of Bootloader
-
-`0x10058000 - 0x10059000` - Scratch of Bootloader
-
-Size of slots `0x10000` - 64kb
-
-__Note:__ It is also possible to place secondary (upgrade) slots in external memory module so resulting image size can be doubled.
-For more details about External Memory usage, please refer to separate guiding document `ExternalMemory.md`.
-
-### Hardware limitations
-
-Since this application is created to demonstrate MCUboot library features and not as reference examples some considerations are taken.
-
-1. `SCB5` used to configure serial port for debug prints. This is the most commonly used Serial Communication Block number among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definition of `CYBSP_UART_HW` in `main.c` of MCUBootApp to SCB* that correspond to your design.
-
-2. `CY_SMIF_SLAVE_SELECT_0` is used as definition SMIF driver API. This configuration is used on evaluation kit for this example CY8CPROTO-062-4343W, CY8PROTO-062S3-4343W, CY8CKIT-062-4343W. If you try to use custom hardware with this application - change value of `smif_id` in `main.c` of MCUBootApp to value that corresponds to your design.
-
-
-### Downloading solution's assets
-
-There is a set assets required:
-
-* MCUBooot Library (root repository)
-* PSoC6 HAL Library
-* PSoC6 Peripheral Drivers Library (PDL)
-* Mbed TLS Cryptographic Library
-
-To get submodules - run the following command:
-
- git submodule update --init --recursive
-
-### Building solution
-
-This folder contains make files infrastructure for building MCUBoot Bootloader. Same approach used in sample BlinkyLedApp application. Example command are provided below for couple different build configurations.
-
-* Build MCUBootApp in `Debug` for signle image use case.
-
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug MCUBOOT_IMAGE_NUMBER=1
-
-* Build MCUBootApp in `Release` for multi image use case.
-
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release MCUBOOT_IMAGE_NUMBER=2
-
-* To Build MCUBootApp with external memory support - pass `USE_EXTERNAL_FLASH=1` flag to `make` command in examples above. In this case UPGRADE image will be located in external memory. Refer to ExternalMemory.md for additional details.
-
-Root directory for build is **boot/cypress.**
-
-**Encrypted Image Support**
-
-To protect user image from unwanted read - Upgrade Image Encryption can be applied. The ECDH/HKDF with EC256 scheme is used in a given solution as well as Mbed TLS as a crypto provider.
-
-To enable image encryption support use `ENC_IMG=1` build flag (BlinkyApp should also be built with this flash set 1).
-
-User is also responsible for providing corresponding binary key data in `enc_priv_key[]` (file `\MCUBootApp\keys.c`). The public part will be used by imgtool when signing and encrypting upgrade image. Signing image with encryption is described in `\BlinkyApp\Readme.md`.
-
-After MCUBootApp is built with these settings unencrypted and encrypted images will be accepted in secondary (upgrade) slot.
-
-Example command:
-
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug MCUBOOT_IMAGE_NUMBER=1 ENC_IMG=1
-
-**KNOWN ISSUE:** On **CYW20829** platform MCUBootApp compiled in `BUILDCFG=Release` mode and with enabled encryption `ENC_IMG=1` and hardware rollback support does not start valid next application `BlinkyApp`. This would be fixed in next releases.
-
-**Programming solution**
-
-There are couple ways of programming hex of MCUBootApp and BlinkyApp. Following instructions assume one of Cypress development kits, for example `CY8CPROTO_062_4343W`.
-
-1. Direct usage of OpenOCD.
-OpenOCD package is supplied with ModuToolbox IDE and can be found in installation folder under `./tools_2.1/openocd`.
-Open terminal application - and execute following command after substitution `PATH_TO_APPLICATION.hex` and `OPENOCD` paths.
-
-Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines.
-
- export OPENOCD=/Applications/ModusToolbox/tools_2.1/openocd
-
- ${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
- -f ${OPENOCD}/scripts/interface/kitprog3.cfg \
- -f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
- -c "init; reset init; program PATH_TO_APPLICATION.hex" \
- -c "resume; reset; exit"
-
-2. Using GUI tool `Cypress Programmer` - follow [link](https://www.cypress.com/products/psoc-programming-solutions) to download.
- Connect board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines. Open `Cypress Programmer` and click `Connect`, then choose hex file: `MCUBootApp.hex` or `BlinkyApp.hex` and click `Program`. Check log to ensure programming success. Reset board.
-
-3. Using `DAPLINK`.
- Connect board to your computer. Switch embeded Kitprog3 to `DAPLINK` mode by pressing `SW3 MODE` button until `LED2 STATUS` blinks fast and mass storage device appeared in OS. Drag and drop `hex` files you wish to program to `DAPLINK` drive in your OS.
-
-
-
-**Currently supported platforms:**
-
-* PSOC_062_2M
-* PSOC_062_1M
-* PSOC_062_512K
-
-**Build environment troubleshooting:**
-
-Regular shell/terminal combination on Linux and MacOS.
-
-On Windows:
-
-* Cygwin
-* Msys2
-
-Also IDE may be used:
-* Eclipse / ModusToolbox ("makefile project from existing source")
-
-*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
-
-*Python/Python3* - make sure you have correct path referenced in `PATH`;
-
-*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
-
-This will iherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.
-
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h b/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h
index c64be77..307c6be 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h
@@ -27,7 +27,8 @@
/* Only SHA256 is accelerated by Cryptolite */
#define MBEDTLS_SHA256_ALT
-
+#define MBEDTLS_ECDSA_SIGN_ALT
+#define MBEDTLS_ECDSA_VERIFY_ALT
#else
/* Currently this target supports SHA1 */
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h b/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h
index 05b29ea..a0e5aa3 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h
@@ -740,7 +740,7 @@
* Comment macros to disable the curve and functions for it
*/
// #define MBEDTLS_ECP_DP_SECP192R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
+// #define MBEDTLS_ECP_DP_SECP224R1_ENABLED
#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
// #define MBEDTLS_ECP_DP_SECP384R1_ENABLED
// #define MBEDTLS_ECP_DP_SECP521R1_ENABLED
diff --git a/boot/cypress/MCUBootApp/libs.mk b/boot/cypress/MCUBootApp/libs.mk
index c21c9cd..096abe1 100644
--- a/boot/cypress/MCUBootApp/libs.mk
+++ b/boot/cypress/MCUBootApp/libs.mk
@@ -58,7 +58,7 @@
# MbedTLS related include directories
ifeq ($(USE_CRYPTO_HW), 1)
-ifeq ($(PLATFORM), CYW20829)
+ifeq ($(FAMILY), CYW20829)
# Override mbedtls/compat-2.x.h for Cryptolite CBUS workaround
INCLUDE_DIRS_MBEDTLS += $(PRJ_DIR)/platforms/crypto/CYW20829
endif
diff --git a/boot/cypress/MCUBootApp/main.c b/boot/cypress/MCUBootApp/main.c
index 86f37fe..8c7bdd0 100644
--- a/boot/cypress/MCUBootApp/main.c
+++ b/boot/cypress/MCUBootApp/main.c
@@ -91,6 +91,51 @@
rsp->br_hdr->ih_hdr_size);
}
+/*******************************************************************************
+ * Function Name: fih_calc_app_addr
+ ********************************************************************************
+ * Summary:
+ * Calculate start address of user application.
+ *
+ * Parameters:
+ * image_base - base address of flash;
+ *
+ * rsp - provided by the boot loader code; indicates where to jump
+ * to execute the main image;
+ *
+ * output - calculated address of application;
+ *
+ * Return:
+ * fih_int
+ *
+ *******************************************************************************/
+static inline __attribute__((always_inline)) fih_int fih_calc_app_addr(
+ uintptr_t image_base, const struct boot_rsp *rsp, fih_uint *app_address)
+{
+ fih_int fih_rc = FIH_FAILURE;
+
+#if defined(MCUBOOT_RAM_LOAD)
+ if (IS_RAM_BOOTABLE(rsp->br_hdr) == true) {
+ if ((UINT32_MAX - rsp->br_hdr->ih_hdr_size) >= image_base) {
+ *app_address =
+ fih_uint_encode(image_base + rsp->br_hdr->ih_hdr_size);
+ fih_rc = FIH_SUCCESS;
+ }
+ } else
+#endif
+ {
+ if (((UINT32_MAX - rsp->br_image_off) >= image_base) &&
+ ((UINT32_MAX - rsp->br_hdr->ih_hdr_size) >=
+ (image_base + rsp->br_image_off))) {
+ *app_address = fih_uint_encode(image_base + rsp->br_image_off +
+ rsp->br_hdr->ih_hdr_size);
+ fih_rc = FIH_SUCCESS;
+ }
+ }
+
+ FIH_RET(fih_rc);
+}
+
#if defined CYW20829
#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
@@ -122,9 +167,8 @@
#endif /* defined CYW20829 */
if ((rsp != NULL) && (rsp->br_hdr != NULL)) {
- int rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
- if (0 == rc) {
+ if (flash_device_base(rsp->br_flash_dev_id, &flash_base) == 0) {
fih_uint app_addr = calc_app_addr(flash_base, rsp);
BOOT_LOG_INF("Starting User Application (wait)...");
@@ -133,8 +177,11 @@
}
BOOT_LOG_INF("Start slot Address: 0x%08" PRIx32, (uint32_t)fih_uint_decode(app_addr));
- rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
- if (rc != 0 || fih_uint_eq(calc_app_addr(flash_base, rsp), app_addr) != FIH_TRUE) {
+ if (flash_device_base(rsp->br_flash_dev_id, &flash_base) != 0) {
+ return false;
+ }
+
+ if (fih_uint_eq(calc_app_addr(flash_base, rsp), app_addr) != FIH_TRUE) {
return false;
}
@@ -238,7 +285,7 @@
if (rc != CY_RSLT_SUCCESS) {
- CY_ASSERT(false);
+ CY_ASSERT((bool)0);
/* Loop forever... */
while (true) {
__WFI();
@@ -274,7 +321,7 @@
CY_RETARGET_IO_BAUDRATE);
if (rc != CY_RSLT_SUCCESS) {
- CY_ASSERT(false);
+ CY_ASSERT((bool)0);
/* Loop forever... */
while (true) {
__WFI();
@@ -303,7 +350,7 @@
/* Check service application completion status */
if (check_service_app_status() != 0) {
BOOT_LOG_ERR("Service application failed");
- CY_ASSERT(false);
+ CY_ASSERT((bool)0);
/* Loop forever... */
while (true) {
__WFI();
diff --git a/boot/cypress/Makefile b/boot/cypress/Makefile
index a444c04..e901317 100644
--- a/boot/cypress/Makefile
+++ b/boot/cypress/Makefile
@@ -65,7 +65,7 @@
# Defines whether or not make all compile warnings into errors for application
# source code (but not for library source code)
-WARN_AS_ERR ?= 1
+WARN_AS_ERR = 0
ifneq ($(filter $(APP_NAME), $(APPS)),)
include ./$(APP_NAME)/$(APP_NAME).mk
diff --git a/boot/cypress/README.md b/boot/cypress/README.md
index cca2c2f..60a5a50 100644
--- a/boot/cypress/README.md
+++ b/boot/cypress/README.md
@@ -2,44 +2,32 @@
### Disclaimer
-Given solution is included in `MCUboot` repository with purpose to demonstrate basic consepts and features of MCUboot library on Cypress PSoC 6 device. Applications are created per MCUboot library maintainers requirements. Implemetation differs from conventional and recomended by Cypress Semiconductors development flow for PSoC 6 devices. These applications are not recomended as a starting point for development and should not be considered as supported examples for PSoC 6 devices.
+Given solution is included in `MCUboot` repository with purpose to demonstrate basic consepts and features of MCUboot library on Infineon Technologies devices.
-Examples provided to use with **ModusToolbox® Software Environment** are a recommended reference point to start development of MCUboot based bootloaders for PSoC 6 devices.
+### Supported platforms
-Refer to **Cypress Semiconductors** [github](https://github.com/cypresssemiconductorco) page to find examples.
-
-1. MCUboot-Based Basic Bootloader [mtb-example-psoc6-mcuboot-basic](https://github.com/cypresssemiconductorco/mtb-example-psoc6-mcuboot-basic)
-2. MCUboot-Based Bootloader with Rollback to Factory App in External Flash [mtb-example-anycloud-mcuboot-rollback](https://github.com/cypresssemiconductorco/mtb-example-anycloud-mcuboot-rollback)
+| Family | Platforms |
+---------- | -------------------|
+| PSOC6 | PSOC6 1M, 2M, 512K |
+| CYWxx829 | CYW20829, CYW89829 |
+| XMC7x00 | XMC7200, XMC7100 |
### Solution description
There are two applications implemented:
-* MCUBootApp - PSoC6 MCUboot-based bootloading application;
-* BlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE;
+* MCUBootApp - MCUboot-based bootloader implementation;
+* BlinkyApp - simple blinking LED application which is a target of BOOT/UPGRADE;
-The default flash map for MCUBootApp implemented is next:
+Detailed description on each application is provided in dedicated files:
-* [0x10000000, 0x10018000] - MCUBootApp (bootloader) area;
-* [0x10018000, 0x10028000] - primary slot for BlinkyApp;
-* [0x10028000, 0x10038000] - secondary slot for BlinkyApp;
-* [0x10038000, 0x10039000] - scratch area;
+Bootloader - [MCUBootApp.md](./MCUBootApp/MCUBootApp.md)
+Test Application - [BlinkyApp.md](./BlinkyApp/BlinkyApp.md)
-The flash map is defined through sysflash.h and memory.c.
+Separate documentation is available for External Memory usage in mcuboot [ExternalMemory.md](./MCUBootApp/ExternalMemory.md)
-It is also possible to place secondary (upgrade) slots in external memory module. In this case primary slot can be doubled in size.
-For more details about External Memory usage, please refer to separate guiding document `MCUBootApp/ExternalMemory.md`.
+### Downloading solution
-MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses either completely software implementation of cryptographic functions or accelerated by hardware - both based on Mbed TLS Library.
-
-### Downloading solution's assets
-
-There is a set assets required:
-
-* MCUBooot Library (root repository)
-* PSoC6 Peripheral Drivers Library (PDL)
-* Mbed TLS Cryptographic Library
-
-Those are represented as submodules.
+Since libraries required by mcuboot Infineon implementation are implemented as submodules following commands needs to be executed.
To retrieve source code with subsequent submodules pull:
@@ -56,23 +44,21 @@
Root directory for build is **boot/cypress.**
-This folder contains make files infrastructure for building both MCUboot Bootloader and sample BlinkyApp application used for Bootloader demo functionality.
+This folder contains make files infrastructure for building both MCUbootApp and sample BlinkyApp application used for Bootloader demo functionality.
-Instructions on how to build and upload MCUBootApp bootloader application and sample user applocation are located in `Readme.md` files in corresponding folders.
+**GCC_ARM** is only supported toolchain.
-Supported platforms for `MCUboot`, `BlinkyApp`:
-
-**GCC_ARM** is only supported (built and verified on GCC 9.3.1).
-
-It is included with [ModusToolbox™ Software Environment](https://www.cypress.com/products/modustoolbox).
+It is recommended to use [ModusToolbox™ Software Environment](https://www.cypress.com/products/modustoolbox) which includes GCC Toolchain.
The default installation folder is expected by the makefile build system.
To use another installation folder, version of **ModusToolbox™ IDE** or another GCC Compiler, specify the path to a toolchain using the **TOOLCHAIN_PATH** parameter.
-Below is an example on how to set toolchin path to the latest include with **ModusToolbox™ IDE 3.0**:
+Below is an example on how to set toolchain path to the latest include with **ModusToolbox™ IDE**:
- make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.0/gcc
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.2/gcc
+
+**Python3** needs to be installed in system since build process required execution of prebuild and postbuild scripts in python.
### Build environment troubleshooting
diff --git a/boot/cypress/common_libs.mk b/boot/cypress/common_libs.mk
index 52aaf49..f501550 100644
--- a/boot/cypress/common_libs.mk
+++ b/boot/cypress/common_libs.mk
@@ -53,8 +53,10 @@
SOURCES_PLATFORM := $(wildcard $(PRJ_DIR)/platforms/BSP/$(FAMILY)/*.c)
SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/security_counter/*.c)
SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/security_counter/$(FAMILY)/*.c)
+ifneq ($(APP_NAME), BlinkyApp)
SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/memory/*.c)
SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/memory/$(FAMILY)/*.c)
+endif
ifeq ($(USE_EXTERNAL_FLASH), 1)
SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/memory/external_memory/*.c)
SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/memory/$(FAMILY)/flash_qspi/*.c)
diff --git a/boot/cypress/libs/cy-mbedtls-acceleration b/boot/cypress/libs/cy-mbedtls-acceleration
index 2da8b43..2ca02f7 160000
--- a/boot/cypress/libs/cy-mbedtls-acceleration
+++ b/boot/cypress/libs/cy-mbedtls-acceleration
@@ -1 +1 @@
-Subproject commit 2da8b43e51275f7ad479f2d0f61610e4577a645b
+Subproject commit 2ca02f7f1cd5f0b4a5e2380cc179da7b7a7b3b59
diff --git a/boot/cypress/libs/mtb-hal-cat1 b/boot/cypress/libs/mtb-hal-cat1
index 0373e75..2ede4ff 160000
--- a/boot/cypress/libs/mtb-hal-cat1
+++ b/boot/cypress/libs/mtb-hal-cat1
@@ -1 +1 @@
-Subproject commit 0373e75de25a7e8f8486f87730e76390d83640a0
+Subproject commit 2ede4ff1cc30638c231b8f4f66fef213514fec37
diff --git a/boot/cypress/libs/mtb-pdl-cat1 b/boot/cypress/libs/mtb-pdl-cat1
index 94eb787..dc2df2d 160000
--- a/boot/cypress/libs/mtb-pdl-cat1
+++ b/boot/cypress/libs/mtb-pdl-cat1
@@ -1 +1 @@
-Subproject commit 94eb787898ced0dcda224fd2f309d2a0727b6ac3
+Subproject commit dc2df2d7faa50bf7b8bc70632d3b683d63ed6adc
diff --git a/boot/cypress/platforms.mk b/boot/cypress/platforms.mk
index 56421c2..b8466ea 100644
--- a/boot/cypress/platforms.mk
+++ b/boot/cypress/platforms.mk
@@ -25,10 +25,10 @@
include host.mk
-# supported platforms
+# supported platforms list
PSOC_06X := PSOC_061_2M PSOC_061_1M PSOC_061_512K PSOC_062_2M PSOC_062_1M PSOC_062_512K PSOC_063_1M
XMC7000 := XMC7200 XMC7100
-PLATFORMS := $(PSOC_06X) CYW20829 $(XMC7000)
+PLATFORMS := $(PSOC_06X) CYW20829 CYW89829 $(XMC7000)
ifneq ($(filter $(PLATFORM), $(PLATFORMS)),)
else
@@ -39,6 +39,8 @@
FAMILY := PSOC6
else ifeq ($(PLATFORM), CYW20829)
FAMILY := CYW20829
+else ifeq ($(PLATFORM), CYW89829)
+FAMILY := CYW20829
else ifeq ($(PLATFORM), $(filter $(PLATFORM), $(XMC7000)))
FAMILY := XMC7000
endif
diff --git a/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.c b/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.c
new file mode 100644
index 0000000..f5e92f9
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.c
@@ -0,0 +1,41 @@
+/***********************************************************************************************//**
+ * \copyright
+ * Copyright 2020-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#if defined(COMPONENT_WICED_BLE)
+
+#include "cybsp_bt_config.h"
+
+const cybt_platform_config_t cybsp_bt_platform_cfg =
+{
+ .hci_config =
+ {
+ .hci_transport = CYBT_HCI_IPC,
+ },
+
+ .controller_config =
+ {
+ .sleep_mode =
+ {
+ .sleep_mode_enabled = CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED,
+ },
+ }
+};
+
+#endif /* defined(COMPONENT_WICED_BLE) */
diff --git a/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.h b/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.h
new file mode 100644
index 0000000..75c8a49
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************//**
+ * \copyright
+ * Copyright 2020-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+/**
+ * \addtogroup group_bsp_bt Bluetooth Configuration Structure
+ * \{
+ * Basic configuration structure for the Bluetooth interface on this board.
+ */
+#pragma once
+
+#if defined(COMPONENT_WICED_BLE)
+
+#include "cybt_platform_config.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if !defined(CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED)
+/** If not already defined, the sleep mode LP is enabled. */
+#define CYBSP_BT_PLATFORM_CFG_SLEEP_MODE_LP_ENABLED (1)
+#endif
+
+/** Bluetooth platform configuration settings for the board. */
+extern const cybt_platform_config_t cybsp_bt_platform_cfg;
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif /* defined(COMPONENT_WICED_BLE) */
+
+/** \} group_bsp_bt */
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h
index dec68e1..02bc2f0 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h
@@ -1,8 +1,8 @@
-#ifndef CYBSP_DOC_H
-#define CYBSP_DOC_H
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2021 Cypress Semiconductor Corporation
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -23,7 +23,10 @@
#if defined(CY_USING_HAL)
#include "cyhal_pin_package.h"
#endif
-#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
+/* CAT4 and CAT5 do not have configurators so the BSP defines pins in a non-generated header */
+#if defined(COMPONENT_CAT4)
+#include "cybsp_pins.h"
+#else
#include "cycfg.h"
#endif
@@ -570,87 +573,87 @@
*/
#ifdef CYBSP_J2_1
-/** Cypress J2 Header pin 1 \def CYBSP_J2_1
+/** Infineon J2 Header pin 1 \def CYBSP_J2_1
*/
#endif
#ifdef CYBSP_J2_2
-/** Cypress J2 Header pin 2 \def CYBSP_J2_2
+/** Infineon J2 Header pin 2 \def CYBSP_J2_2
*/
#endif
#ifdef CYBSP_J2_3
-/** Cypress J2 Header pin 3 \def CYBSP_J2_3
+/** Infineon J2 Header pin 3 \def CYBSP_J2_3
*/
#endif
#ifdef CYBSP_J2_4
-/** Cypress J2 Header pin 4 \def CYBSP_J2_4
+/** Infineon J2 Header pin 4 \def CYBSP_J2_4
*/
#endif
#ifdef CYBSP_J2_5
-/** Cypress J2 Header pin 5 \def CYBSP_J2_5
+/** Infineon J2 Header pin 5 \def CYBSP_J2_5
*/
#endif
#ifdef CYBSP_J2_7
-/** Cypress J2 Header pin 7 \def CYBSP_J2_7
+/** Infineon J2 Header pin 7 \def CYBSP_J2_7
*/
#endif
#ifdef CYBSP_J2_8
-/** Cypress J2 Header pin 8 \def CYBSP_J2_8
+/** Infineon J2 Header pin 8 \def CYBSP_J2_8
*/
#endif
#ifdef CYBSP_J2_9
-/** Cypress J2 Header pin 9 \def CYBSP_J2_9
+/** Infineon J2 Header pin 9 \def CYBSP_J2_9
*/
#endif
#ifdef CYBSP_J2_10
-/** Cypress J2 Header pin 10 \def CYBSP_J2_10
+/** Infineon J2 Header pin 10 \def CYBSP_J2_10
*/
#endif
#ifdef CYBSP_J2_11
-/** Cypress J2 Header pin 11 \def CYBSP_J2_11
+/** Infineon J2 Header pin 11 \def CYBSP_J2_11
*/
#endif
#ifdef CYBSP_J2_12
-/** Cypress J2 Header pin 12 \def CYBSP_J2_12
+/** Infineon J2 Header pin 12 \def CYBSP_J2_12
*/
#endif
#ifdef CYBSP_J2_13
-/** Cypress J2 Header pin 13 \def CYBSP_J2_13
+/** Infineon J2 Header pin 13 \def CYBSP_J2_13
*/
#endif
#ifdef CYBSP_J2_15
-/** Cypress J2 Header pin 15 \def CYBSP_J2_15
+/** Infineon J2 Header pin 15 \def CYBSP_J2_15
*/
#endif
#ifdef CYBSP_J2_16
-/** Cypress J2 Header pin 16 \def CYBSP_J2_16
+/** Infineon J2 Header pin 16 \def CYBSP_J2_16
*/
#endif
#ifdef CYBSP_J2_16
-/** Cypress J2 Header pin 16 \def CYBSP_J2_16
+/** Infineon J2 Header pin 16 \def CYBSP_J2_16
*/
#endif
#ifdef CYBSP_J2_6
-/** Cypress J2 Header pin 6 \def CYBSP_J2_6
+/** Infineon J2 Header pin 6 \def CYBSP_J2_6
*/
#endif
#ifdef CYBSP_J2_17
-/** Cypress J2 Header pin 17 \def CYBSP_J2_17
+/** Infineon J2 Header pin 17 \def CYBSP_J2_17
*/
#endif
#ifdef CYBSP_J2_18
-/** Cypress J2 Header pin 18 \def CYBSP_J2_18
+/** Infineon J2 Header pin 18 \def CYBSP_J2_18
*/
#endif
#ifdef CYBSP_J2_19
-/** Cypress J2 Header pin 19 \def CYBSP_J2_19
+/** Infineon J2 Header pin 19 \def CYBSP_J2_19
*/
#endif
#ifdef CYBSP_J2_20
-/** Cypress J2 Header pin 20 \def CYBSP_J2_20
+/** Infineon J2 Header pin 20 \def CYBSP_J2_20
*/
#endif
#ifdef CYBSP_J2_14
-/** Cypress J2 Header pin 14 \def CYBSP_J2_14
+/** Infineon J2 Header pin 14 \def CYBSP_J2_14
*/
#endif
@@ -665,67 +668,67 @@
*/
#ifdef CYBSP_J6_1
-/** Cypress J6 Header pin 1 \def CYBSP_J6_1
+/** Infineon J6 Header pin 1 \def CYBSP_J6_1
*/
#endif
#ifdef CYBSP_J6_2
-/** Cypress J6 Header pin 2 \def CYBSP_J6_2
+/** Infineon J6 Header pin 2 \def CYBSP_J6_2
*/
#endif
#ifdef CYBSP_J6_3
-/** Cypress J6 Header pin 3 \def CYBSP_J6_3
+/** Infineon J6 Header pin 3 \def CYBSP_J6_3
*/
#endif
#ifdef CYBSP_J6_4
-/** Cypress J6 Header pin 4 \def CYBSP_J6_4
+/** Infineon J6 Header pin 4 \def CYBSP_J6_4
*/
#endif
#ifdef CYBSP_J6_5
-/** Cypress J6 Header pin 5 \def CYBSP_J6_5
+/** Infineon J6 Header pin 5 \def CYBSP_J6_5
*/
#endif
#ifdef CYBSP_J6_6
-/** Cypress J6 Header pin 6 \def CYBSP_J6_6
+/** Infineon J6 Header pin 6 \def CYBSP_J6_6
*/
#endif
#ifdef CYBSP_J6_7
-/** Cypress J6 Header pin 7 \def CYBSP_J6_7
+/** Infineon J6 Header pin 7 \def CYBSP_J6_7
*/
#endif
#ifdef CYBSP_J6_8
-/** Cypress J6 Header pin 8 \def CYBSP_J6_8
+/** Infineon J6 Header pin 8 \def CYBSP_J6_8
*/
#endif
#ifdef CYBSP_J6_9
-/** Cypress J6 Header pin 9 \def CYBSP_J6_9
+/** Infineon J6 Header pin 9 \def CYBSP_J6_9
*/
#endif
#ifdef CYBSP_J6_10
-/** Cypress J6 Header pin 10 \def CYBSP_J6_10
+/** Infineon J6 Header pin 10 \def CYBSP_J6_10
*/
#endif
#ifdef CYBSP_J6_11
-/** Cypress J6 Header pin 11 \def CYBSP_J6_11
+/** Infineon J6 Header pin 11 \def CYBSP_J6_11
*/
#endif
#ifdef CYBSP_J6_12
-/** Cypress J6 Header pin 12 \def CYBSP_J6_12
+/** Infineon J6 Header pin 12 \def CYBSP_J6_12
*/
#endif
#ifdef CYBSP_J6_13
-/** Cypress J6 Header pin 13 \def CYBSP_J6_13
+/** Infineon J6 Header pin 13 \def CYBSP_J6_13
*/
#endif
#ifdef CYBSP_J6_14
-/** Cypress J6 Header pin 14 \def CYBSP_J6_14
+/** Infineon J6 Header pin 14 \def CYBSP_J6_14
*/
#endif
#ifdef CYBSP_J6_15
-/** Cypress J6 Header pin 15 \def CYBSP_J6_15
+/** Infineon J6 Header pin 15 \def CYBSP_J6_15
*/
#endif
#ifdef CYBSP_J6_16
-/** Cypress J6 Header pin 16 \def CYBSP_J6_16
+/** Infineon J6 Header pin 16 \def CYBSP_J6_16
*/
#endif
@@ -736,7 +739,7 @@
/**
* \addtogroup group_bsp_pins_capsense Capsense
* \{
- * Pins connected to CapSense sensors on the board.
+ * Pins connected to CAPSENSE™ sensors on the board.
*/
#ifdef CYBSP_CSD_TX
@@ -838,5 +841,3 @@
#if defined(__cplusplus)
}
#endif
-
-#endif /* CYBSP_DOC */
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.c b/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.c
new file mode 100644
index 0000000..b20862f
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.c
@@ -0,0 +1,101 @@
+/***************************************************************************//**
+* \file cybsp_dsram.c
+*
+* Description:
+* Provides initialization code for handling deepsleep ram.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#include <stdlib.h>
+#include "cy_syspm.h"
+#include "cy_sysclk.h"
+#include "cybsp.h"
+#if defined(CY_USING_HAL)
+#include "cyhal_hwmgr.h"
+#include "cyhal_syspm.h"
+#endif
+#include "cybsp_smif_init.h"
+#if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)
+#include "cyabs_rtos_dsram.h"
+#endif
+#include "system_cat1b.h"
+#include "cybsp_dsram.h"
+#include "cmsis_compiler.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_syspm_do_warmboot
+//--------------------------------------------------------------------------------------------------
+__WEAK void cybsp_syspm_do_warmboot(void)
+{
+ #if defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)
+ cyabs_rtos_exit_dsram();
+ #endif
+}
+
+
+CY_SECTION_RAMFUNC_BEGIN
+//--------------------------------------------------------------------------------------------------
+// cybsp_warmboot_handler
+//--------------------------------------------------------------------------------------------------
+void cybsp_warmboot_handler(void)
+{
+ SystemInit_Warmboot_CAT1B_CM33();
+
+ #if FLASH_BOOT
+ //cybsp_smif_enable();
+ //cybsp_smif_init();
+ #endif
+
+ init_cycfg_all();
+
+ cybsp_syspm_do_warmboot();
+}
+
+
+CY_SECTION_RAMFUNC_END
+
+/* DS-RAM Warmboot Re-entry*/
+extern unsigned int __INITIAL_SP /*__StackTop*/;
+cy_stc_syspm_warmboot_entrypoint_t syspmBspDeepSleepEntryPoint =
+ { (uint32_t*)(&__INITIAL_SP), (uint32_t*)cybsp_warmboot_handler };
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_syspm_dsram_init
+//--------------------------------------------------------------------------------------------------
+__WEAK cy_rslt_t cybsp_syspm_dsram_init(void)
+{
+/* Setup DS-RAM Warmboot Re-entry. IAR is not supported */
+ #if defined(__ARMCC_VERSION) || defined (__GNUC__)
+ Cy_Syslib_SetWarmBootEntryPoint((uint32_t*)&syspmBspDeepSleepEntryPoint, true);
+ #endif
+
+ return CY_RSLT_SUCCESS;
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.h
new file mode 100644
index 0000000..a3e5137
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.h
@@ -0,0 +1,62 @@
+/***********************************************************************************************//**
+ * \file cybsp_dsram.h
+ *
+ * \brief
+ * Basic API for DSRAM support.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \addtogroup group_bsp_dsram_functions Functions
+ * \{
+ * All functions exposed by the board.
+ */
+
+/**
+ * \brief Prepares the system to handle warm boot.
+ */
+void cybsp_syspm_do_warmboot(void);
+
+/**
+ * \brief Initializes the deepsleep ram setup.
+ * \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is
+ * a problem initializing any hardware it returns an error code specific
+ * to the hardware module that had a problem.
+ */
+cy_rslt_t cybsp_syspm_dsram_init(void);
+
+
+extern cy_stc_syspm_warmboot_entrypoint_t syspmBspDeepSleepEntryPoint; ///< DS entry point
+
+/** \} group_bsp_dsram_functions */
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_hw_config.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_hw_config.h
new file mode 100644
index 0000000..f4ff295
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_hw_config.h
@@ -0,0 +1,50 @@
+/***********************************************************************************************//**
+ * \file cybsp_hw_config.h
+ *
+ * \brief
+ * Basic API for handling defaults for hardware so code examples behave the same across different
+ * devices.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+#pragma once
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+#include "cycfg_pins.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#ifndef CYBSP_USER_BTN_DRIVE
+#define CYBSP_USER_BTN_DRIVE (CYHAL_GPIO_DRIVE_PULLDOWN)
+#endif
+
+#ifndef CYBSP_DEBUG_UART_CTS
+#define CYBSP_DEBUG_UART_CTS (NC)
+#endif
+#ifndef CYBSP_DEBUG_UART_RTS
+#define CYBSP_DEBUG_UART_RTS (NC)
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.c b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.c
new file mode 100644
index 0000000..254dc51
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.c
@@ -0,0 +1,66 @@
+/***************************************************************************//**
+* \file cybsp_pm.c
+*
+* Description:
+* Provides initialization code for starting up the hardware contained on the
+* Infineon board.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdlib.h>
+#include "cybsp_pm_callbacks.h"
+#include "cybsp.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_pm_callbacks_register
+//--------------------------------------------------------------------------------------------------
+cy_rslt_t cybsp_pm_callbacks_register(void)
+{
+ cy_stc_syspm_callback_t** _cybsp_callbacks_array;
+ size_t number_of_callbacks = 0;
+
+ _cybsp_pm_callbacks_get_ptr_and_number(&_cybsp_callbacks_array, &number_of_callbacks);
+
+ if ((number_of_callbacks == 0) || (*_cybsp_callbacks_array == NULL))
+ {
+ // Nothing to register, return success
+ return CY_RSLT_SUCCESS;
+ }
+
+ for (size_t cb_idx = 0; cb_idx < number_of_callbacks; ++cb_idx)
+ {
+ if (!Cy_SysPm_RegisterCallback(_cybsp_callbacks_array[cb_idx]))
+ {
+ return CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
+ }
+ }
+
+ return CY_RSLT_SUCCESS;
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.h
new file mode 100644
index 0000000..27b12f3
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.h
@@ -0,0 +1,42 @@
+/***********************************************************************************************//**
+ * \file cybsp_pm.h
+ *
+ * \brief
+ * Basic API for setting up boards containing a Cypress MCU.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#include "cy_result.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \brief Register all PM callbacks, that are expected to be registered for the used device.
+ */
+cy_rslt_t cybsp_pm_callbacks_register(void);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.c b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.c
new file mode 100644
index 0000000..ed5f0af
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.c
@@ -0,0 +1,399 @@
+/***************************************************************************//**
+* \file cybsp_pm_callbacks.c
+*
+* Description:
+* Provides initialization code for starting up the hardware contained on the
+* Infineon board.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdlib.h>
+#include "cybsp_pm_callbacks.h"
+#include "cycfg_qspi_memslot.h"
+#include "cy_sysclk.h"
+#include "cybsp_dsram.h"
+#include "cybsp_smif_init.h"
+
+// Must be defined in file for RAM functions to utilize during Deep Sleep callback to wake
+// up external flash memory. Needs reference here when external flash is powered down in DS.
+#if CY_PDL_FLASH_BOOT
+cy_stc_smif_mem_config_t** smifConfigLocal = smifMemConfigs;
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if (CY_PDL_FLASH_BOOT && (defined(CY_DEVICE_CYW20829) && \
+ (CY_SYSLIB_GET_SILICON_REV_ID != CY_SYSLIB_20829A0_SILICON_REV)))
+#define CY_EXT_MEM_POWER_DOWN_SUPPORTED
+#endif
+////////////////////////////////////////////////////////////////////////////////////////////////
+/////////////////////////// BSP PM callbacks order values //////////////////////////////////////
+
+// CAT1B device QSPI memory power-down / power-up PM callback order.
+#ifndef CYBSP_EXT_MEMORY_PM_CALLBACK_ORDER
+ #define CYBSP_EXT_MEMORY_PM_CALLBACK_ORDER (254u)
+#endif
+// The sysclk deep sleep callback is recommended to be the last callback that is executed before
+// entry into deep sleep mode and the first one upon exit the deep sleep mode.
+// Doing so minimizes the time spent on low power mode entry and exit.
+#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
+ #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
+#endif
+
+////////////////////////////////////////////////////////////////////////////////////////////////
+/////////////////////////// BSP PM callbacks ///////////////////////////////////////////////////
+
+// CAT1B device QSPI memory power-down / power-up PM callback.
+// Intended to put external QSPI memory in low power state
+// upon device transition to Deepsleep power mode and to wake up
+// external QSPI device from low power mode upon device wakeup
+#if defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+CY_RAMFUNC_BEGIN
+cy_en_syspm_status_t cybsp_smif_power_up_callback(cy_stc_syspm_callback_params_t* callbackParams,
+ cy_en_syspm_callback_mode_t mode)
+{
+ cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
+ CY_UNUSED_PARAMETER(callbackParams);
+ extern cy_stc_smif_context_t cybsp_smif_context;
+
+ switch (mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ retVal = CY_SYSPM_SUCCESS;
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ // Put external memory to low power mode
+ // SMIF IOs aren't disabled here as the device enters into DSRAM then the IOs will be
+ // disabled automatically
+ retVal = (cy_en_syspm_status_t)Cy_SMIF_MemCmdPowerDown(SMIF0, smifConfigLocal[0],
+ &cybsp_smif_context);
+ cybsp_smif_disable();
+ break;
+ }
+
+ case CY_SYSPM_AFTER_DS_WFI_TRANSITION:
+ {
+ cybsp_smif_enable();
+ // Return external memory to normal operation from low power modes
+ cy_en_smif_status_t smif_functions_status = Cy_SMIF_MemCmdReleasePowerDown(SMIF0,
+ smifConfigLocal[
+ 0],
+ &cybsp_smif_context);
+
+ if (CY_SMIF_SUCCESS == smif_functions_status)
+ {
+ smif_functions_status = cybsp_is_memory_ready(smifConfigLocal[0]);
+ if (CY_SMIF_SUCCESS == smif_functions_status)
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ }
+ break;
+ }
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return retVal;
+}
+
+
+CY_RAMFUNC_END
+#endif // defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+
+// CAT1B device QSPI memory power-down / power-up PM callback.
+// Intended to put external QSPI memory in low power state
+// upon device transition to DeepsleepRam power mode and to wake up
+// external QSPI device from low power mode upon device wakeup
+#if defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+CY_RAMFUNC_BEGIN
+cy_en_syspm_status_t cybsp_dsram_smif_power_up_callback(
+ cy_stc_syspm_callback_params_t* callbackParams,
+ cy_en_syspm_callback_mode_t mode)
+{
+ cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
+ CY_UNUSED_PARAMETER(callbackParams);
+ extern cy_stc_smif_context_t cybsp_smif_context;
+
+ switch (mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ retVal = CY_SYSPM_SUCCESS;
+ break;
+
+ case CY_SYSPM_CHECK_FAIL:
+ break;
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ // Put external memory to low power mode
+ retVal = (cy_en_syspm_status_t)Cy_SMIF_MemCmdPowerDown(SMIF0, smifConfigLocal[0],
+ &cybsp_smif_context);
+ cybsp_smif_disable();
+ break;
+ }
+
+ case CY_SYSPM_AFTER_DS_WFI_TRANSITION:
+ {
+ if (!Cy_SysLib_IsDSRAMWarmBootEntry())
+ {
+ cybsp_smif_enable();
+ // Return external memory to normal operation from low power modes
+ cy_en_smif_status_t smif_functions_status = Cy_SMIF_MemCmdReleasePowerDown(SMIF0,
+ smifConfigLocal[
+ 0],
+ &cybsp_smif_context);
+
+ if (CY_SMIF_SUCCESS == smif_functions_status)
+ {
+ smif_functions_status = cybsp_is_memory_ready(smifConfigLocal[0]);
+ if (CY_SMIF_SUCCESS == smif_functions_status)
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ }
+ }
+ break;
+ }
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return retVal;
+}
+
+
+CY_RAMFUNC_END
+#endif // defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_deepsleep_ram_callback
+//--------------------------------------------------------------------------------------------------
+cy_en_syspm_status_t cybsp_deepsleep_ram_callback(cy_stc_syspm_callback_params_t* callbackParams,
+ cy_en_syspm_callback_mode_t mode)
+{
+ cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
+
+ CY_UNUSED_PARAMETER(callbackParams);
+
+ switch (mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ case CY_SYSPM_CHECK_FAIL:
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ break;
+ }
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ /* Currently GCC and ARMCC supported */
+ #if defined(__GNUC__) || defined(__ARMCC_VERSION)
+ Cy_Syslib_SetWarmBootEntryPoint((uint32_t*)&syspmBspDeepSleepEntryPoint, true);
+ #endif
+
+ retVal = CY_SYSPM_SUCCESS;
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return retVal;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_hibernate_callback
+//--------------------------------------------------------------------------------------------------
+#if defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+CY_SECTION_RAMFUNC_BEGIN
+cy_en_syspm_status_t cybsp_hibernate_callback(cy_stc_syspm_callback_params_t* callbackParams,
+ cy_en_syspm_callback_mode_t mode)
+{
+ cy_en_syspm_status_t retVal = CY_SYSPM_FAIL;
+ CY_UNUSED_PARAMETER(callbackParams);
+ extern cy_stc_smif_context_t cybsp_smif_context;
+
+ switch (mode)
+ {
+ case CY_SYSPM_CHECK_READY:
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ break;
+ }
+
+ case CY_SYSPM_CHECK_FAIL:
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ break;
+ }
+
+ case CY_SYSPM_BEFORE_TRANSITION:
+ {
+ // Put external memory to low power mode
+ retVal = (cy_en_syspm_status_t)Cy_SMIF_MemCmdPowerDown(SMIF0, smifConfigLocal[0],
+ &cybsp_smif_context);
+ break;
+ }
+
+ case CY_SYSPM_AFTER_TRANSITION:
+ {
+ // Return external memory to normal operation from low power modes
+ cy_en_smif_status_t smif_functions_status = Cy_SMIF_MemCmdReleasePowerDown(SMIF0,
+ smifConfigLocal[
+ 0],
+ &cybsp_smif_context);
+ if (CY_SMIF_SUCCESS == smif_functions_status)
+ {
+ smif_functions_status = cybsp_is_memory_ready(smifConfigLocal[0]);
+ if (CY_SMIF_SUCCESS == smif_functions_status)
+ {
+ retVal = CY_SYSPM_SUCCESS;
+ }
+ }
+ break;
+ }
+
+ default:
+ break;
+ }
+
+ return retVal;
+}
+
+
+CY_SECTION_RAMFUNC_END
+#endif // defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+
+////////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////// BSP PM callbacks config structures ////////////////////////////////////
+
+#if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
+static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback =
+{
+ .callback = &Cy_SysClk_DeepSleepCallback,
+ #if (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP_RAM)
+ .type = (cy_en_syspm_callback_type_t)CY_SYSPM_MODE_DEEPSLEEP_RAM,
+ #else
+ .type = (cy_en_syspm_callback_type_t)CY_SYSPM_MODE_DEEPSLEEP,
+ #endif
+ .callbackParams = &cybsp_sysclk_pm_callback_param,
+ .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
+};
+#endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+
+#if defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+static cy_stc_syspm_callback_params_t cybsp_smif_pu_callback_param = { NULL, NULL };
+static cy_stc_syspm_callback_t cybsp_smif_pu_callback =
+{
+ .callback = &cybsp_smif_power_up_callback,
+ .type = CY_SYSPM_DEEPSLEEP,
+ .callbackParams = &cybsp_smif_pu_callback_param,
+ .order = CYBSP_EXT_MEMORY_PM_CALLBACK_ORDER
+};
+
+static cy_stc_syspm_callback_params_t cybsp_dsram_smif_pu_callback_param = { NULL, NULL };
+static cy_stc_syspm_callback_t cybsp_dsram_smif_pu_callback =
+{
+ .callback = &cybsp_dsram_smif_power_up_callback,
+ .type = CY_SYSPM_DEEPSLEEP_RAM,
+ .callbackParams = &cybsp_dsram_smif_pu_callback_param,
+ .order = CYBSP_EXT_MEMORY_PM_CALLBACK_ORDER
+};
+
+static cy_stc_syspm_callback_params_t cybsp_hibernate_pm_callback_param = { NULL, NULL };
+static cy_stc_syspm_callback_t cybsp_hibernate_pm_callback =
+{
+ .callback = &cybsp_hibernate_callback,
+ .type = CY_SYSPM_HIBERNATE,
+ .callbackParams = &cybsp_hibernate_pm_callback_param,
+ .order = CYBSP_EXT_MEMORY_PM_CALLBACK_ORDER
+};
+#endif // defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+
+static cy_stc_syspm_callback_params_t cybsp_ds_ram_pm_callback_param = { NULL, NULL };
+static cy_stc_syspm_callback_t cybsp_ds_ram_pm_callback =
+{
+ .callback = &cybsp_deepsleep_ram_callback,
+ .type = CY_SYSPM_DEEPSLEEP_RAM,
+ .callbackParams = &cybsp_ds_ram_pm_callback_param,
+ .order = 0u
+};
+
+////////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////// BSP PM callbacks array ////////////////////////////////////////////////
+
+cy_stc_syspm_callback_t* _cybsp_callbacks_array[] =
+{
+ #if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+ &cybsp_sysclk_pm_callback,
+ #endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+ #if defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+ &cybsp_smif_pu_callback,
+ &cybsp_dsram_smif_pu_callback,
+ &cybsp_hibernate_pm_callback,
+ #endif // defined(CY_EXT_MEM_POWER_DOWN_SUPPORTED)
+ &cybsp_ds_ram_pm_callback
+};
+
+////////////////////////////////////////////////////////////////////////////////////////////////
+//////////////////////// BSP PM callbacks array helper function ////////////////////////////////
+
+void _cybsp_pm_callbacks_get_ptr_and_number(cy_stc_syspm_callback_t*** arr_ptr,
+ size_t* number_of_elements)
+{
+ *number_of_elements = 0;
+ if (sizeof(_cybsp_callbacks_array) != 0)
+ {
+ *arr_ptr = _cybsp_callbacks_array;
+ *number_of_elements = sizeof(_cybsp_callbacks_array) / sizeof(_cybsp_callbacks_array[0]);
+ }
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.h
new file mode 100644
index 0000000..4a41792
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.h
@@ -0,0 +1,46 @@
+/***********************************************************************************************//**
+ * \file cybsp_pm_callbacks.h
+ *
+ * \brief
+ * Basic API for setting up boards containing an Infineon MCU.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \brief Get number of PM callbacks, that are available for specific BSP
+ * \param[out] arr_ptr Pointer to store array of callback pointers
+ * \param[out] number_of_elements Pointer to store number of elements in array of callback
+ * pointers
+ */
+void _cybsp_pm_callbacks_get_ptr_and_number(cy_stc_syspm_callback_t*** arr_ptr,
+ size_t* number_of_elements);
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.c b/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.c
new file mode 100644
index 0000000..410be64
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.c
@@ -0,0 +1,381 @@
+/***************************************************************************//**
+* \file cybsp_smif_init.c
+*
+* Description:
+* Provides initialization code for SMIF.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#if CY_PDL_FLASH_BOOT
+#include "cybsp_smif_init.h"
+#include "cycfg_pins.h"
+#include "cyhal_pin_package.h"
+
+cy_stc_smif_context_t cybsp_smif_context;
+
+static uint32_t SMIF_PORT_SEL0;
+static uint32_t SMIF_PORT_SEL1;
+static uint32_t SMIF_CFG;
+static uint32_t SMIF_OUT;
+
+/*******************************************************************************
+* Function Name: smif_disable
+****************************************************************************//**
+*
+* it disable the the SMIF.
+*
+* \return NULL.
+*
+*******************************************************************************/
+CY_RAMFUNC_BEGIN
+void cybsp_smif_disable()
+{
+ // to minimize DeepSleep latency this code assumes that all of the SMIF pins are on the same
+ // port
+ int port_number= CYHAL_GET_PORT(CYBSP_QSPI_SS);
+ SMIF0->CTL = SMIF0->CTL & ~SMIF_CTL_ENABLED_Msk;
+ SMIF_PORT_SEL0 = ((HSIOM_PRT_Type*)&HSIOM->PRT[port_number])->PORT_SEL0;
+ SMIF_PORT_SEL1 = ((HSIOM_PRT_Type*)&HSIOM->PRT[port_number])->PORT_SEL1;
+ SMIF_CFG = ((GPIO_PRT_Type*)&GPIO->PRT[port_number])->CFG;
+ SMIF_OUT = ((GPIO_PRT_Type*)&GPIO->PRT[port_number])->OUT;
+ ((HSIOM_PRT_Type*)&HSIOM->PRT[port_number])->PORT_SEL0 = 0x00;
+ ((HSIOM_PRT_Type*)&HSIOM->PRT[port_number])->PORT_SEL1 = 0x00;
+ ((GPIO_PRT_Type*)&GPIO->PRT[port_number])->CFG = 0x600006;
+ ((GPIO_PRT_Type*)&GPIO->PRT[port_number])->OUT = 0x1;
+}
+
+
+CY_RAMFUNC_END
+
+/*******************************************************************************
+* Function Name: smif_enable
+****************************************************************************//**
+*
+* it enable the the SMIF.
+*
+* \return NULL.
+*
+*******************************************************************************/
+CY_RAMFUNC_BEGIN
+void cybsp_smif_enable()
+{
+ int port_number= CYHAL_GET_PORT(CYBSP_QSPI_SS);
+ SMIF0->CTL = SMIF0->CTL | SMIF_CTL_ENABLED_Msk;
+ ((HSIOM_PRT_Type*)&HSIOM->PRT[port_number])->PORT_SEL0 = SMIF_PORT_SEL0;
+ ((HSIOM_PRT_Type*)&HSIOM->PRT[port_number])->PORT_SEL1 = SMIF_PORT_SEL1;
+ ((GPIO_PRT_Type*)&GPIO->PRT[port_number])->CFG = SMIF_CFG;
+ ((GPIO_PRT_Type*)&GPIO->PRT[port_number])->OUT = SMIF_OUT;
+}
+
+
+CY_RAMFUNC_END
+
+/*******************************************************************************
+* Function Name: cybsp_is_memory_ready
+****************************************************************************//**
+*
+* Polls the memory device to check whether it is ready to accept new commands or
+* not until either it is ready or the retries have exceeded the limit.
+*
+* \param memConfig
+* memory device configuration
+*
+* \return Status of the operation.
+* CY_SMIF_SUCCESS - Memory is ready to accept new commands.
+* CY_SMIF_EXCEED_TIMEOUT - Memory is busy.
+*
+*******************************************************************************/
+#if defined (__ICCARM__)
+/* Suppress warnings originating from configurator */
+/* Ta022 : "Call to a non __ramfunc function from within a __ramfunc function" */
+CY_PRAGMA(diag_suppress = Ta022)
+#endif
+//--------------------------------------------------------------------------------------------------
+// cybsp_is_memory_ready
+//--------------------------------------------------------------------------------------------------
+CY_RAMFUNC_BEGIN
+
+cy_en_smif_status_t cybsp_is_memory_ready(cy_stc_smif_mem_config_t const* memConfig)
+{
+ uint32_t retries = 0;
+ bool isBusy;
+
+ do
+ {
+ isBusy =
+ Cy_SMIF_Memslot_IsBusy(SMIF_HW, (cy_stc_smif_mem_config_t*)memConfig,
+ &cybsp_smif_context);
+ Cy_SysLib_DelayUs(15);
+ retries++;
+ } while(isBusy && (retries < MEMORY_BUSY_CHECK_RETRIES));
+
+ return (isBusy ? CY_SMIF_EXCEED_TIMEOUT : CY_SMIF_SUCCESS);
+}
+
+
+CY_RAMFUNC_END
+#if defined (__ICCARM__)
+CY_PRAGMA(diag_default = Ta022)
+#endif
+
+/*******************************************************************************
+* Function Name: cybsp_enable_quad_mode
+****************************************************************************//*
+*
+* This function sets the QE (QUAD Enable) bit in the external memory
+* configuration register to enable Quad SPI mode.
+*
+* \param memConfig
+* Memory device configuration
+*
+* \return Status of the operation. See cy_en_smif_status_t.
+*
+*******************************************************************************/
+#if defined (__ICCARM__)
+/* Suppress warnings originating from configurator */
+/* Ta022 : "Call to a non __ramfunc function from within a __ramfunc function" */
+CY_PRAGMA(diag_suppress = Ta022)
+#endif
+//--------------------------------------------------------------------------------------------------
+// cybsp_enable_quad_mode
+//--------------------------------------------------------------------------------------------------
+CY_RAMFUNC_BEGIN
+
+cy_en_smif_status_t cybsp_enable_quad_mode(cy_stc_smif_mem_config_t const* memConfig)
+{
+ cy_en_smif_status_t status;
+
+ /* Send Write Enable to external memory */
+ status = Cy_SMIF_Memslot_CmdWriteEnable(SMIF_HW, smifMemConfigs[0], &cybsp_smif_context);
+
+ if (CY_SMIF_SUCCESS == status)
+ {
+ status = Cy_SMIF_Memslot_QuadEnable(SMIF_HW, (cy_stc_smif_mem_config_t*)memConfig,
+ &cybsp_smif_context);
+
+ if (CY_SMIF_SUCCESS == status)
+ {
+ /* Poll memory for the completion of operation */
+ status = cybsp_is_memory_ready(memConfig);
+ }
+ }
+
+ return status;
+}
+
+
+CY_RAMFUNC_END
+#if defined (__ICCARM__)
+CY_PRAGMA(diag_default = Ta022)
+#endif
+
+
+/*******************************************************************************
+* Function Name: cybsp_is_quad_enabled
+****************************************************************************//**
+*
+* Checks whether QE (Quad Enable) bit is set or not in the configuration
+* register of the memory.
+*
+* \param memConfig
+* Memory device configuration
+*
+* \param isQuadEnabled
+* This parameter is updated to indicate whether Quad mode is enabled (true) or
+* not (false). The value is valid only when the function returns
+* CY_SMIF_SUCCESS.
+*
+* \return Status of the operation. See cy_en_smif_status_t.
+*
+*******************************************************************************/
+#if defined (__ICCARM__)
+/* Suppress warnings originating from configurator */
+/* Ta022 : "Call to a non __ramfunc function from within a __ramfunc function" */
+CY_PRAGMA(diag_suppress = Ta022)
+#endif
+//--------------------------------------------------------------------------------------------------
+// cybsp_is_quad_enabled
+//--------------------------------------------------------------------------------------------------
+CY_RAMFUNC_BEGIN
+
+cy_en_smif_status_t cybsp_is_quad_enabled(cy_stc_smif_mem_config_t const* memConfig,
+ bool* isQuadEnabled)
+{
+ cy_en_smif_status_t status;
+ uint8_t readStatus = 0;
+ uint32_t statusCmd = memConfig->deviceCfg->readStsRegQeCmd->command;
+ uint8_t maskQE = (uint8_t)memConfig->deviceCfg->stsRegQuadEnableMask;
+
+ status = Cy_SMIF_Memslot_CmdReadSts(SMIF_HW, memConfig, &readStatus, statusCmd,
+ &cybsp_smif_context);
+
+ *isQuadEnabled = false;
+ if (CY_SMIF_SUCCESS == status)
+ {
+ /* Check whether Quad mode is already enabled or not */
+ *isQuadEnabled = (maskQE == (readStatus & maskQE));
+ }
+
+ return status;
+}
+
+
+CY_RAMFUNC_END
+#if defined (__ICCARM__)
+CY_PRAGMA(diag_default = Ta022)
+#endif
+
+
+cy_stc_smif_config_t cybsp_smif_config =
+{
+ .mode = (uint32_t)CY_SMIF_NORMAL,
+ .deselectDelay = 7,
+ .rxClockSel = (uint32_t)CY_SMIF_SEL_INVERTED_FEEDBACK_CLK,
+ .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
+};
+
+/********************************************************
+* cybsp_smif_start
+*********************************************************
+* Initializes the SMIF hardware, sets the slave select
+* and enables the SMIF block.
+*
+* returns: the status of the block during initialization
+*
+********************************************************/
+#if defined (__ICCARM__)
+/* Suppress warnings originating from configurator */
+/* Ta022 : "Call to a non __ramfunc function from within a __ramfunc function" */
+CY_PRAGMA(diag_suppress = Ta022)
+#endif
+//--------------------------------------------------------------------------------------------------
+// cybsp_smif_start
+//--------------------------------------------------------------------------------------------------
+CY_RAMFUNC_BEGIN
+
+cy_en_smif_status_t cybsp_smif_start(void)
+{
+ cy_en_smif_status_t cybsp_smif_status = CY_SMIF_BAD_PARAM;
+
+ cybsp_smif_status =
+ Cy_SMIF_Init(SMIF_HW, &cybsp_smif_config, TIMEOUT_1_MS, &cybsp_smif_context);
+
+ if (cybsp_smif_status == CY_SMIF_SUCCESS)
+ {
+ Cy_SMIF_SetDataSelect(SMIF_HW, smifMemConfigs[0]->slaveSelect,
+ smifMemConfigs[0]->dataSelect);
+ Cy_SMIF_Enable(SMIF_HW, &cybsp_smif_context);
+ }
+
+ return cybsp_smif_status;
+}
+
+
+CY_RAMFUNC_END
+#if defined (__ICCARM__)
+CY_PRAGMA(diag_default = Ta022)
+#endif
+
+
+/********************************************************
+* cybsp_smif_init
+*********************************************************
+* Configures the SMIF hardware
+********************************************************/
+#if defined (__ICCARM__)
+/* Suppress warnings originating from configurator */
+/* Ta022 : "Call to a non __ramfunc function from within a __ramfunc function" */
+CY_PRAGMA(diag_suppress = Ta022)
+#endif
+//--------------------------------------------------------------------------------------------------
+// cybsp_smif_init
+//--------------------------------------------------------------------------------------------------
+CY_RAMFUNC_BEGIN
+
+cy_en_smif_status_t cybsp_smif_init(void)
+{
+ /* Initalization Status Holders */
+ cy_en_smif_status_t cybsp_smif_status = CY_SMIF_BAD_PARAM;
+ bool QE_status = false;
+
+ cybsp_smif_status = cybsp_smif_start();
+
+ if (cybsp_smif_status == CY_SMIF_SUCCESS)
+ {
+ cybsp_smif_status = Cy_SMIF_MemCmdReleasePowerDown(SMIF0,
+ smifMemConfigs[0],
+ &cybsp_smif_context);
+
+ if (CY_SMIF_SUCCESS == cybsp_smif_status)
+ {
+ cybsp_smif_status = cybsp_is_memory_ready(smifMemConfigs[0]);
+ if (CY_SMIF_SUCCESS == cybsp_smif_status)
+ {
+ /* Map memory device to memory map */
+ cybsp_smif_status = Cy_SMIF_Memslot_Init(SMIF_HW,
+ (cy_stc_smif_block_config_t*)&smifBlockConfig,
+ &cybsp_smif_context);
+ if (cybsp_smif_status == CY_SMIF_SUCCESS)
+ {
+ /* Even after SFDP enumeration QE command is not initialised */
+ /* So, it should be 1.0 device */
+ if ((smifMemConfigs[0]->deviceCfg->readStsRegQeCmd->command ==
+ CY_SMIF_NO_COMMAND_OR_MODE) ||
+ (smifMemConfigs[0]->deviceCfg->readStsRegQeCmd->command == 0))
+ {
+ cybsp_smif_status = Cy_SMIF_MemInitSfdpMode(SMIF_HW,
+ smifMemConfigs[0],
+ CY_SMIF_WIDTH_QUAD,
+ CY_SMIF_SFDP_QER_1,
+ &cybsp_smif_context);
+ }
+
+ if (cybsp_smif_status == CY_SMIF_SUCCESS)
+ {
+ /* Check if Quad mode is already enabled */
+ cybsp_is_quad_enabled(smifMemConfigs[0], &QE_status);
+
+ /* If not enabled, enable quad mode */
+ if (!QE_status)
+ {
+ /* Enable Quad mode */
+ cybsp_smif_status = cybsp_enable_quad_mode(smifMemConfigs[0]);
+ }
+ if (cybsp_smif_status == CY_SMIF_SUCCESS)
+ {
+ /* Put the device in XIP mode */
+ Cy_SMIF_SetMode(SMIF_HW, CY_SMIF_MEMORY);
+ }
+ }
+ }
+ }
+ }
+ }
+
+ return cybsp_smif_status;
+}
+
+
+CY_RAMFUNC_END
+#if defined (__ICCARM__)
+CY_PRAGMA(diag_default = Ta022)
+#endif
+
+#endif // if CY_PDL_FLASH_BOOT
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.h
new file mode 100644
index 0000000..f4968c4
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.h
@@ -0,0 +1,69 @@
+/***********************************************************************************************//**
+ * \file cybsp_smif_init.h
+ *
+ * \brief
+ * Basic API for setting up boards containing a Cypress MCU.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#ifndef CYBSP_SMIF_INIT_H
+#define CYBSP_SMIF_INIT_H
+#include "cy_smif_memslot.h"
+#include "cycfg_qspi_memslot.h"
+
+#define SMIF_HW SMIF0
+#define SMIF_DESELECT_DELAY 7
+#define TIMEOUT_1_MS (1000ul) /* 1 ms timeout for all blocking functions */
+#define MEMORY_BUSY_CHECK_RETRIES (750ul) /* Set it high enough for the sector erase operation to
+ complete */
+
+/**
+ * \brief Initialize the smif IP.
+ *
+ * \returns CY_SMIF_SUCCESS if the SMIF is successfully initialized, if there is
+ * a problem initializing any hardware it returns an error code specific
+ * to the problem.
+ */
+cy_en_smif_status_t cybsp_smif_init(void);
+
+/**
+ * \brief Polls memory device until it is ready to receive new commands, or retry limit is exceeded
+ *
+ * \param memConfig Memory Device Configuration
+ * \returns Status of the operation.
+ * CY_SMIF_SUCCESS - Memory is ready to accept new commands.
+ * CY_SMIF_EXCEED_TIMEOUT - Memory is busy.
+ */
+cy_en_smif_status_t cybsp_is_memory_ready(cy_stc_smif_mem_config_t const* memConfig);
+
+/**
+ * \brief Disables the SMIF IO.
+ *
+ */
+void cybsp_smif_disable();
+
+/**
+ * \brief Enables the SMIF IO.
+ *
+ */
+void cybsp_smif_enable();
+
+#endif /*CYBSP_SMIF_INIT_H*/
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_types.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_types.h
index eded7dd..aeb7023 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_types.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_types.h
@@ -1,8 +1,8 @@
-#ifndef CYBSP_TYPES_H
-#define CYBSP_TYPES_H
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2021 Cypress Semiconductor Corporation
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -27,6 +27,25 @@
#endif
/**
+ * \cond INTERNAL
+ */
+/* WIFI interface types */
+#define CYBSP_SDIO_INTERFACE (0)
+#define CYBSP_SPI_INTERFACE (1)
+#define CYBSP_M2M_INTERFACE (2)
+
+/* Map from the new components to the old interface names for
+ * compatibility with code that still depends on those defines */
+#if defined(COMPONENT_WIFI_INTERFACE_SDIO)
+#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SDIO_INTERFACE)
+#elif defined(COMPONENT_WIFI_INTERFACE_SPI)
+#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SPI_INTERFACE)
+#elif defined(COMPONENT_WIFI_INTERFACE_M2M)
+#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_M2M_INTERFACE)
+#endif
+/** \endcond */
+
+/**
* \addtogroup group_bsp_pin_state Pin States
* \{
* Macros to abstract out whether the LEDs & Buttons are wired high or active low.
@@ -52,5 +71,3 @@
#if defined(__cplusplus)
}
#endif
-
-#endif /* CYBSP_TYPES_H */
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg.c b/boot/cypress/platforms/BSP/CYW20829/cycfg.c
index d668910..86c7e6a 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg.c
@@ -4,13 +4,13 @@
* Description:
* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
-* Tools Package 2.2.1.3040
-* integration_mxs40sv2-LATEST 3.0.0.5994
-* personalities 3.0.0.0
-* udd 3.0.0.775
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -28,7 +28,21 @@
#include "cycfg.h"
+/* This function is provided for compatibility with older 2.X style projects. */
void init_cycfg_all(void)
{
- init_cycfg_system();
+ cycfg_config_init();
+ cycfg_config_reservations();
+}
+void cycfg_config_init(void)
+{
+ init_cycfg_system();
+ init_cycfg_routing();
+ init_cycfg_pins();
+}
+void cycfg_config_reservations(void)
+{
+ reserve_cycfg_system();
+ reserve_cycfg_peripherals();
+ reserve_cycfg_pins();
}
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg.h b/boot/cypress/platforms/BSP/CYW20829/cycfg.h
index a8ed6ad..d2cf33f 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg.h
@@ -4,13 +4,13 @@
* Description:
* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
-* Tools Package 2.2.1.3040
-* integration_mxs40sv2-LATEST 3.0.0.5994
-* personalities 3.0.0.0
-* udd 3.0.0.775
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -35,9 +35,13 @@
#include "cycfg_notices.h"
#include "cycfg_system.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
#include "cycfg_pins.h"
void init_cycfg_all(void);
+void cycfg_config_init(void);
+void cycfg_config_reservations(void);
#if defined(__cplusplus)
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.c
deleted file mode 100644
index 954b06f..0000000
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_connectivity_bt.c
-*
-* Description:
-* Connectivity BT configuration
-* This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2790
-* latest-v2.X 2.0.0.6211
-* personalities 3.0.0.0
-* udd 3.0.0.562
-*
-********************************************************************************
-* Copyright 2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_connectivity_bt.h"
-
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.h
deleted file mode 100644
index 545ebcc..0000000
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_connectivity_bt.h
-*
-* Description:
-* Connectivity BT configuration
-* This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2790
-* latest-v2.X 2.0.0.6211
-* personalities 3.0.0.0
-* udd 3.0.0.562
-*
-********************************************************************************
-* Copyright 2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_CONNECTIVITY_BT_H)
-#define CYCFG_CONNECTIVITY_BT_H
-
-#include "cycfg_notices.h"
-#include "cycfg_pins.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define bt_0_power_0_ENABLED 1U
-#define CYCFG_BT_LP_ENABLED (1u)
-#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
-#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
-#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE
-#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW
-#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE
-#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW
-
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_CONNECTIVITY_BT_H */
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h
index bcaadf2..fc94cf2 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h
@@ -5,13 +5,13 @@
* Contains warnings and errors that occurred while generating code for the
* design.
* This file was automatically generated and should not be modified.
-* Tools Package 2.2.1.3040
-* integration_mxs40sv2-LATEST 3.0.0.5994
-* personalities 3.0.0.0
-* udd 3.0.0.775
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,5 +30,17 @@
#if !defined(CYCFG_NOTICES_H)
#define CYCFG_NOTICES_H
+#ifdef CY_SUPPORTS_DEVICE_VALIDATION
+#ifndef CYW20829B0LKML
+ #error "Unexpected MPN; expected DEVICE:=CYW20829B0LKML. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif
+#endif
+
+#ifdef CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION
+#ifndef CYW20829B0LKML
+ #error "Unexpected MPN; expected DEVICE:=CYW20829B0LKML. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif
+#endif
+
#endif /* CYCFG_NOTICES_H */
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.c
new file mode 100644
index 0000000..0d1a34a
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.c
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
+*
+********************************************************************************
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+cy_stc_adcmic_context_t adcmic_0_context;
+const cy_stc_adcmic_dc_config_t adcmic_0_dc_config =
+{
+ .range = CY_ADCMIC_DC_RANGE_3_6V,
+ .channel = CY_ADCMIC_GPIO5,
+ .timerPeriod = 10000,
+ .timerInput = CY_ADCMIC_TIMER_COUNT_INPUT_CIC_UPDATE,
+ .context = &adcmic_0_context,
+};
+const cy_stc_adcmic_config_t adcmic_0_config =
+{
+ .micConfig = NULL,
+ .pdmConfig = NULL,
+ .dcConfig = (cy_stc_adcmic_dc_config_t*)&adcmic_0_dc_config,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t adcmic_0_obj =
+ {
+ .type = CYHAL_RSC_ADC,
+ .block_num = 0,
+ .channel_num = 0,
+ };
+#endif //defined (CY_USING_HAL)
+
+
+void reserve_cycfg_peripherals(void)
+{
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&adcmic_0_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.h
new file mode 100644
index 0000000..f625a9a
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.h
@@ -0,0 +1,62 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.h
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
+*
+********************************************************************************
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PERIPHERALS_H)
+#define CYCFG_PERIPHERALS_H
+
+#include "cycfg_notices.h"
+#include "cy_adcmic.h"
+#if defined (CY_USING_HAL)
+ #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define adcmic_0_ENABLED 1U
+#define adcmic_0_HW MXS40ADCMIC0
+#define adcmic_0_IRQ adcmic_interrupt_adcmic_IRQn
+#define adcmic_0_FIFO_DATA_REG_PTR CY_ADCMIC_FIFO_DATA_REG_PTR(MXS40ADCMIC0)
+#define adcmic_0_TRIGGER_CLR_REG_PTR CY_ADCMIC_TRIGGER_CLR_REG_PTR(MXS40ADCMIC0)
+
+extern cy_stc_adcmic_context_t adcmic_0_context;
+extern const cy_stc_adcmic_dc_config_t adcmic_0_dc_config;
+extern const cy_stc_adcmic_config_t adcmic_0_config;
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t adcmic_0_obj;
+#endif //defined (CY_USING_HAL)
+
+void reserve_cycfg_peripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PERIPHERALS_H */
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c
index 2042372..4ba698b 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c
@@ -4,13 +4,13 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.2.1.3040
-* integration_mxs40sv2-LATEST 3.0.0.5994
-* personalities 3.0.0.0
-* udd 3.0.0.775
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -28,3 +28,68 @@
#include "cycfg_pins.h"
+const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CYBSP_BT_UART_CTS_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+ .nonSec = 1UL,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj =
+ {
+ .type = CYHAL_RSC_GPIO,
+ .block_num = CYBSP_BT_UART_CTS_PORT_NUM,
+ .channel_num = CYBSP_BT_UART_CTS_PIN,
+ };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_A1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = CYBSP_A1_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+ .nonSec = 1UL,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_A1_obj =
+ {
+ .type = CYHAL_RSC_GPIO,
+ .block_num = CYBSP_A1_PORT_NUM,
+ .channel_num = CYBSP_A1_PIN,
+ };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_pins(void)
+{
+ Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
+ Cy_GPIO_Pin_Init(CYBSP_A1_PORT, CYBSP_A1_PIN, &CYBSP_A1_config);
+}
+
+void reserve_cycfg_pins(void)
+{
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&CYBSP_BT_UART_CTS_obj);
+ cyhal_hwmgr_reserve(&CYBSP_A1_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h
index 71f7e79..60a717d 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h
@@ -4,13 +4,13 @@
* Description:
* Pin configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.2.1.3040
-* integration_mxs40sv2-LATEST 3.0.0.5994
-* personalities 3.0.0.0
-* udd 3.0.0.775
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,34 +30,146 @@
#define CYCFG_PINS_H
#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+ #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
#if defined(__cplusplus)
extern "C" {
#endif
#if defined (CY_USING_HAL)
- #define CYBSP_USER_LED1 (P0_0)
- #define CYBSP_USER_LED CYBSP_USER_LED1
+ #define CYBSP_PDM_CLK (P0_0)
+ #define CYBSP_D6 CYBSP_PDM_CLK
+ #define CYBSP_PDM_DATA (P0_1)
+ #define CYBSP_D7 CYBSP_PDM_DATA
+ #define CYBSP_D18 (P0_2)
+ #define CYBSP_LED_RGB_RED CYBSP_D18
+ #define CYBSP_D19 (P0_3)
+ #define CYBSP_LED_RGB_GREEN CYBSP_D19
+ #define CYBSP_I2S_MCLK (P0_4)
+ #define CYBSP_LED_RGB_BLUE CYBSP_I2S_MCLK
+ #define CYBSP_USER_BTN (P0_5)
+ #define CYBSP_USER_BTN1 CYBSP_USER_BTN
+ #define CYBSP_I2S_SCK CYBSP_USER_BTN
+ #define CYBSP_USER_BTN2 (P1_0)
+ #define CYBSP_D3 CYBSP_USER_BTN2
+ #define CYBSP_D10 CYBSP_USER_BTN2
+ #define CYBSP_I2S_WS CYBSP_USER_BTN2
+ #define CYBSP_SPI_CS CYBSP_USER_BTN2
+ #define CYBSP_USER_LED1 (P1_1)
+ #define CYBSP_D13 CYBSP_USER_LED1
+ #define CYBSP_USER_LED CYBSP_USER_LED1
+ #define CYBSP_I2S_DATA CYBSP_USER_LED1
+ #define CYBSP_SPI_CLK CYBSP_USER_LED1
+ #define CYBSP_SWDIO (P1_2)
+ #define CYBSP_D5 CYBSP_SWDIO
+ #define CYBSP_D11 CYBSP_SWDIO
+ #define CYBSP_SPI_MOSI CYBSP_SWDIO
+ #define CYBSP_SWDCK (P1_3)
+ #define CYBSP_D4 CYBSP_SWDCK
+ #define CYBSP_SPI_MISO CYBSP_SWDCK
+ #define CYBSP_D12 CYBSP_SWDCK
+ #define CYBSP_D2 (P1_4)
+ #define CYBSP_LIN_EN CYBSP_D2
+ #define CYBSP_D8 (P1_5)
+ #define CYBSP_LIN_RX CYBSP_D8
+ #define CYBSP_D9 (P1_6)
+ #define CYBSP_LIN_TX CYBSP_D9
+ #define CYBSP_QSPI_SS (P2_0)
+ #define CYBSP_QSPI_D3 (P2_1)
+ #define CYBSP_QSPI_D2 (P2_2)
+ #define CYBSP_QSPI_D1 (P2_3)
+ #define CYBSP_QSPI_D0 (P2_4)
+ #define CYBSP_QSPI_SCK (P2_5)
#endif //defined (CY_USING_HAL)
+#define CYBSP_BT_UART_CTS_ENABLED 1U
+#define CYBSP_DEBUG_UART_CTS_ENABLED CYBSP_BT_UART_CTS_ENABLED
+#define CYBSP_BT_UART_CTS_PORT GPIO_PRT3
+#define CYBSP_DEBUG_UART_CTS_PORT CYBSP_BT_UART_CTS_PORT
+#define CYBSP_BT_UART_CTS_PORT_NUM 3U
+#define CYBSP_DEBUG_UART_CTS_PORT_NUM CYBSP_BT_UART_CTS_PORT_NUM
+#define CYBSP_BT_UART_CTS_PIN 0U
+#define CYBSP_DEBUG_UART_CTS_PIN CYBSP_BT_UART_CTS_PIN
+#define CYBSP_BT_UART_CTS_NUM 0U
+#define CYBSP_DEBUG_UART_CTS_NUM CYBSP_BT_UART_CTS_NUM
+#define CYBSP_BT_UART_CTS_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_DEBUG_UART_CTS_DRIVEMODE CYBSP_BT_UART_CTS_DRIVEMODE
+#define CYBSP_BT_UART_CTS_INIT_DRIVESTATE 1
+#define CYBSP_DEBUG_UART_CTS_INIT_DRIVESTATE CYBSP_BT_UART_CTS_INIT_DRIVESTATE
+#ifndef ioss_0_port_3_pin_0_HSIOM
+ #define ioss_0_port_3_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_BT_UART_CTS_HSIOM ioss_0_port_3_pin_0_HSIOM
+#define CYBSP_DEBUG_UART_CTS_HSIOM CYBSP_BT_UART_CTS_HSIOM
+#define CYBSP_BT_UART_CTS_IRQ ioss_interrupts_gpio_3_IRQn
+#define CYBSP_DEBUG_UART_CTS_IRQ CYBSP_BT_UART_CTS_IRQ
#if defined (CY_USING_HAL)
- #define CYBSP_USER_BTN1 (P0_1)
- #define CYBSP_USER_BTN CYBSP_USER_BTN1
+ #define CYBSP_BT_UART_CTS_HAL_PORT_PIN P3_0
+ #define CYBSP_DEBUG_UART_CTS_HAL_PORT_PIN CYBSP_BT_UART_CTS_HAL_PORT_PIN
+ #define CYBSP_BT_UART_CTS P3_0
+ #define CYBSP_DEBUG_UART_CTS CYBSP_BT_UART_CTS
+ #define CYBSP_BT_UART_CTS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+ #define CYBSP_DEBUG_UART_CTS_HAL_IRQ CYBSP_BT_UART_CTS_HAL_IRQ
+ #define CYBSP_BT_UART_CTS_HAL_DIR CYHAL_GPIO_DIR_INPUT
+ #define CYBSP_DEBUG_UART_CTS_HAL_DIR CYBSP_BT_UART_CTS_HAL_DIR
+ #define CYBSP_BT_UART_CTS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+ #define CYBSP_DEBUG_UART_CTS_HAL_DRIVEMODE CYBSP_BT_UART_CTS_HAL_DRIVEMODE
+ #define CYBSP_BT_UART_RTS (P3_1)
+ #define CYBSP_DEBUG_UART_RTS CYBSP_BT_UART_RTS
+ #define CYBSP_BT_UART_RX (P3_2)
+ #define CYBSP_DEBUG_UART_RX CYBSP_BT_UART_RX
+ #define CYBSP_D0 CYBSP_BT_UART_RX
+ #define CYBSP_BT_UART_TX (P3_3)
+ #define CYBSP_DEBUG_UART_TX CYBSP_BT_UART_TX
+ #define CYBSP_D1 CYBSP_BT_UART_TX
+ #define CYBSP_THERMISTOR (P3_4)
+ #define CYBSP_A0 CYBSP_THERMISTOR
#endif //defined (CY_USING_HAL)
+#define CYBSP_A1_ENABLED 1U
+#define CYBSP_A1_PORT GPIO_PRT3
+#define CYBSP_A1_PORT_NUM 3U
+#define CYBSP_A1_PIN 5U
+#define CYBSP_A1_NUM 5U
+#define CYBSP_A1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_A1_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_3_pin_5_HSIOM
+ #define ioss_0_port_3_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_A1_HSIOM ioss_0_port_3_pin_5_HSIOM
+#define CYBSP_A1_IRQ ioss_interrupts_gpio_3_IRQn
#if defined (CY_USING_HAL)
- #define CYBSP_SWO (P1_0)
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_SWDIO (P1_2)
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_SWDCK (P1_3)
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_DEBUG_UART_RX (P3_2)
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_DEBUG_UART_TX (P3_3)
+ #define CYBSP_A1_HAL_PORT_PIN P3_5
+ #define CYBSP_A1 P3_5
+ #define CYBSP_A1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+ #define CYBSP_A1_HAL_DIR CYHAL_GPIO_DIR_INPUT
+ #define CYBSP_A1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+ #define CYBSP_A2 (P3_6)
+ #define CYBSP_A3 (P3_7)
+ #define CYBSP_I2C_SCL (P4_0)
+ #define CYBSP_I2C_SDA (P4_1)
+ #define CYBSP_XTAL1 (P5_0)
+ #define CYBSP_CAN_RX CYBSP_XTAL1
+ #define CYBSP_XTAL0 (P5_1)
+ #define CYBSP_CAN_TX CYBSP_XTAL0
+ #define CYBSP_USER_LED2 (P5_2)
#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_CTS_config;
+#define CYBSP_DEBUG_UART_CTS_config CYBSP_BT_UART_CTS_config
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_BT_UART_CTS_obj;
+ #define CYBSP_DEBUG_UART_CTS_obj CYBSP_BT_UART_CTS_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_A1_config;
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_A1_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+void reserve_cycfg_pins(void);
#if defined(__cplusplus)
}
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.c
new file mode 100644
index 0000000..c1d6c4c
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.c
@@ -0,0 +1,681 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 4.10.0.1343
+*
+********************************************************************************
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeEnCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeDisCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_eraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_chipEraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_programCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegWipCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegOeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeStsRegOeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readLatencyCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeLatencyCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x00U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR,
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readSfdpCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x5AU,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 8U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+};
+
+#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
+static cy_stc_smif_hybrid_region_info_t SFDP_SlaveSlot_0_regionInfoStorage[16];
+
+static cy_stc_smif_hybrid_region_info_t *SFDP_SlaveSlot_0_regionInfo[16] = {
+ &SFDP_SlaveSlot_0_regionInfoStorage[0],
+ &SFDP_SlaveSlot_0_regionInfoStorage[1],
+ &SFDP_SlaveSlot_0_regionInfoStorage[2],
+ &SFDP_SlaveSlot_0_regionInfoStorage[3],
+ &SFDP_SlaveSlot_0_regionInfoStorage[4],
+ &SFDP_SlaveSlot_0_regionInfoStorage[5],
+ &SFDP_SlaveSlot_0_regionInfoStorage[6],
+ &SFDP_SlaveSlot_0_regionInfoStorage[7],
+ &SFDP_SlaveSlot_0_regionInfoStorage[8],
+ &SFDP_SlaveSlot_0_regionInfoStorage[9],
+ &SFDP_SlaveSlot_0_regionInfoStorage[10],
+ &SFDP_SlaveSlot_0_regionInfoStorage[11],
+ &SFDP_SlaveSlot_0_regionInfoStorage[12],
+ &SFDP_SlaveSlot_0_regionInfoStorage[13],
+ &SFDP_SlaveSlot_0_regionInfoStorage[14],
+ &SFDP_SlaveSlot_0_regionInfoStorage[15],
+};
+#endif
+
+cy_stc_smif_mem_device_cfg_t deviceCfg_SFDP_SlaveSlot_0 =
+{
+ /* Specifies the number of address bytes used by the memory slave device. */
+ .numOfAddrBytes = 0x03U,
+ /* The size of the memory. */
+ .memSize = 0x0000100U,
+ /* Specifies the Read command. */
+ .readCmd = &SFDP_SlaveSlot_0_readCmd,
+ /* Specifies the Write Enable command. */
+ .writeEnCmd = &SFDP_SlaveSlot_0_writeEnCmd,
+ /* Specifies the Write Disable command. */
+ .writeDisCmd = &SFDP_SlaveSlot_0_writeDisCmd,
+ /* Specifies the Erase command. */
+ .eraseCmd = &SFDP_SlaveSlot_0_eraseCmd,
+ /* Specifies the sector size of each erase. */
+ .eraseSize = 0x0001000U,
+ /* Specifies the Chip Erase command. */
+ .chipEraseCmd = &SFDP_SlaveSlot_0_chipEraseCmd,
+ /* Specifies the Program command. */
+ .programCmd = &SFDP_SlaveSlot_0_programCmd,
+ /* Specifies the page size for programming. */
+ .programSize = 0x0000100U,
+ /* Specifies the command to read the QE-containing status register. */
+ .readStsRegQeCmd = &SFDP_SlaveSlot_0_readStsRegQeCmd,
+ /* Specifies the command to read the WIP-containing status register. */
+ .readStsRegWipCmd = &SFDP_SlaveSlot_0_readStsRegWipCmd,
+ /* Specifies the read SFDP command */
+ .readSfdpCmd = &SFDP_SlaveSlot_0_readSfdpCmd,
+ /* Specifies the command to write into the QE-containing status register. */
+ .writeStsRegQeCmd = &SFDP_SlaveSlot_0_writeStsRegQeCmd,
+ /* The mask for the status register. */
+ .stsRegBusyMask = 0x00U,
+ /* The mask for the status register. */
+ .stsRegQuadEnableMask = 0x00U,
+ /* The max time for the erase type-1 cycle-time in ms. */
+ .eraseTime = 1U,
+ /* The max time for the chip-erase cycle-time in ms. */
+ .chipEraseTime = 16U,
+ /* The max time for the page-program cycle-time in us. */
+ .programTime = 8U,
+#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
+ /* Points to NULL or to structure with info about sectors for hybrid memory. */
+ .hybridRegionCount = 0U,
+ .hybridRegionInfo = SFDP_SlaveSlot_0_regionInfo,
+#endif
+ /* Specifies the command to read variable latency cycles configuration register */
+ .readLatencyCmd = &SFDP_SlaveSlot_0_readLatencyCmd,
+ /* Specifies the command to write variable latency cycles configuration register */
+ .writeLatencyCmd = &SFDP_SlaveSlot_0_writeLatencyCmd,
+ /* Specifies the address for variable latency cycle address */
+ .latencyCyclesRegAddr = 0x00U,
+ /* Specifies variable latency cycles Mask */
+ .latencyCyclesMask = 0x00U,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /* Specifies data for memory with hybrid sectors */
+ .octalDDREnableSeq = 0,
+ /* Specifies the command to read the OE-containing status register. */
+ .readStsRegOeCmd = &SFDP_SlaveSlot_0_readStsRegOeCmd,
+ /* Specifies the command to write the OE-containing status register. */
+ .writeStsRegOeCmd = &SFDP_SlaveSlot_0_writeStsRegOeCmd,
+ /* QE mask for the status registers */
+ .stsRegOctalEnableMask = 0x00U,
+ /* Octal enable register address */
+ .octalEnableRegAddr = 0x00U,
+ /* Frequency of operation used in Octal mode */
+ .freq_of_operation = CY_SMIF_100MHZ_OPERATION,
+#endif
+};
+
+cy_stc_smif_mem_config_t SFDP_SlaveSlot_0 =
+{
+ /* Determines the slot number where the memory device is placed. */
+ .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+ /* Flags. */
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ .flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MERGE_ENABLE,
+#else
+ .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MERGE_ENABLE,
+#endif /* CY_IP_MXSMIF_VERSION */
+ /* The data-line selection options for a slave device. */
+ .dataSelect = CY_SMIF_DATA_SEL0,
+ /* The base address the memory slave is mapped to in the PSoC memory map.
+ Valid when the memory-mapped mode is enabled. */
+ .baseAddress = 0x60000000U,
+ /* The size allocated in the PSoC memory map, for the memory slave device.
+ The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+ .memMappedSize = 0x100000U,
+ /* If this memory device is one of the devices in the dual quad SPI configuration.
+ Valid when the memory mapped mode is enabled. */
+ .dualQuadSlots = 0,
+ /* The configuration of the device. */
+ .deviceCfg = &deviceCfg_SFDP_SlaveSlot_0,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+ /** Continous transfer merge timeout.
+ * After this period the memory device is deselected. A later transfer, even from a
+ * continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
+ * This configuration parameter is available for CAT1B devices. */
+ .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE,
+#else
+#error Features used by this file require CY_IP_MXSMIF_VERSION >= 2.
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM] = {
+ &SFDP_SlaveSlot_0,
+};
+
+cy_stc_smif_block_config_t smifBlockConfig =
+{
+ /* The number of SMIF memories defined. */
+ .memCount = CY_SMIF_DEVICE_NUM,
+ /* The pointer to the array of memory config structures of size memCount. */
+ .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+ /* The version of the SMIF driver. */
+ .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+ /* The version of the SMIF driver. */
+ .minorVersion = CY_SMIF_DRV_VERSION_MINOR,
+};
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.h
new file mode 100644
index 0000000..422fb49
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.h
@@ -0,0 +1,91 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 4.10.0.1343
+*
+********************************************************************************
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_CFG_TOOL_VERSION (410)
+
+/* Supported QSPI Driver version */
+#define CY_SMIF_DRV_VERSION_REQUIRED (100)
+
+#if !defined(CY_SMIF_DRV_VERSION)
+ #define CY_SMIF_DRV_VERSION (100)
+#endif
+
+/* Check the used Driver version */
+#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION)
+ #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
+#endif
+
+typedef cy_stc_smif_mem_config_t cy_serial_flash_mem_config_t;
+typedef cy_stc_smif_block_config_t cy_serial_flash_block_config_t;
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeEnCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeDisCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_eraseCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_chipEraseCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_programCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegQeCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegWipCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeStsRegQeCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegOeCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeStsRegOeCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readLatencyCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeLatencyCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readSfdpCmd;
+
+extern cy_stc_smif_mem_device_cfg_t deviceCfg_SFDP_SlaveSlot_0;
+
+extern cy_stc_smif_mem_config_t SFDP_SlaveSlot_0;
+
+#define Auto_detect_SFDP_SlaveSlot_0_readCmd SFDP_SlaveSlot_0_readCmd
+#define Auto_detect_SFDP_SlaveSlot_0_writeEnCmd SFDP_SlaveSlot_0_writeEnCmd
+#define Auto_detect_SFDP_SlaveSlot_0_writeDisCmd SFDP_SlaveSlot_0_writeDisCmd
+#define Auto_detect_SFDP_SlaveSlot_0_eraseCmd SFDP_SlaveSlot_0_eraseCmd
+#define Auto_detect_SFDP_SlaveSlot_0_chipEraseCmd SFDP_SlaveSlot_0_chipEraseCmd
+#define Auto_detect_SFDP_SlaveSlot_0_programCmd SFDP_SlaveSlot_0_programCmd
+#define Auto_detect_SFDP_SlaveSlot_0_readStsRegQeCmd SFDP_SlaveSlot_0_readStsRegQeCmd
+#define Auto_detect_SFDP_SlaveSlot_0_readStsRegWipCmd SFDP_SlaveSlot_0_readStsRegWipCmd
+#define Auto_detect_SFDP_SlaveSlot_0_writeStsRegQeCmd SFDP_SlaveSlot_0_writeStsRegQeCmd
+#define Auto_detect_SFDP_SlaveSlot_0_readStsRegOeCmd SFDP_SlaveSlot_0_readStsRegOeCmd
+#define Auto_detect_SFDP_SlaveSlot_0_writeStsRegOeCmd SFDP_SlaveSlot_0_writeStsRegOeCmd
+#define Auto_detect_SFDP_SlaveSlot_0_readLatencyCmd SFDP_SlaveSlot_0_readLatencyCmd
+#define Auto_detect_SFDP_SlaveSlot_0_writeLatencyCmd SFDP_SlaveSlot_0_writeLatencyCmd
+#define Auto_detect_SFDP_SlaveSlot_0_readSfdpCmd SFDP_SlaveSlot_0_readSfdpCmd
+#define deviceCfg_Auto_detect_SFDP_SlaveSlot_0 deviceCfg_SFDP_SlaveSlot_0
+#define Auto_detect_SFDP_SlaveSlot_0 SFDP_SlaveSlot_0
+
+extern cy_stc_smif_mem_config_t* smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CYCFG_QSPI_MEMSLOT_H*/
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.c
deleted file mode 100644
index 0b66046..0000000
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_routing.c
-*
-* Description:
-* Establishes all necessary connections between hardware elements.
-* This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2790
-* latest-v2.X 2.0.0.6211
-* personalities 3.0.0.0
-* udd 3.0.0.562
-*
-********************************************************************************
-* Copyright 2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_routing.h"
-
-#include "cy_device_headers.h"
-
-void init_cycfg_routing(void)
-{
- HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
- HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
- HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
- HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
- HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
- HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
- HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
- HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
-}
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h
index ea1de77..1ced646 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h
@@ -4,13 +4,13 @@
* Description:
* Establishes all necessary connections between hardware elements.
* This file was automatically generated and should not be modified.
-* Tools Package 2.2.0.2790
-* latest-v2.X 2.0.0.6211
-* personalities 3.0.0.0
-* udd 3.0.0.562
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2020 Cypress Semiconductor Corporation
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -34,24 +34,10 @@
#endif
#include "cycfg_notices.h"
-void init_cycfg_routing(void);
-#define init_cycfg_connectivity() init_cycfg_routing()
-#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
-#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
-#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
-#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+
+static inline void init_cycfg_routing(void) {}
+
+#define ioss_0_port_3_pin_5_ANALOG P3_5_ADCMIC_GPIO_ADC_IN5
#if defined(__cplusplus)
}
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_system.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.c
index c388dc9..f04cde5 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_system.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.c
@@ -4,13 +4,13 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.2.1.3040
-* integration_mxs40sv2-LATEST 3.0.0.5994
-* personalities 3.0.0.0
-* udd 3.0.0.775
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -32,345 +32,463 @@
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
#define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
#define CY_CFG_SYSCLK_FLL_ENABLED 1
-#define CY_CFG_SYSCLK_FLL_MULT 504U
-#define CY_CFG_SYSCLK_FLL_REFDIV 42U
-#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE2
+#define CY_CFG_SYSCLK_FLL_MULT 500U
+#define CY_CFG_SYSCLK_FLL_REFDIV 125U
+#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4
#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true
#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U
-#define CY_CFG_SYSCLK_FLL_IGAIN 8U
-#define CY_CFG_SYSCLK_FLL_PGAIN 7U
-#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U
+#define CY_CFG_SYSCLK_FLL_IGAIN 9U
+#define CY_CFG_SYSCLK_FLL_PGAIN 4U
+#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 48U
#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
-#define CY_CFG_SYSCLK_FLL_CCO_FREQ 198U
-#define CY_CFG_SYSCLK_FLL_OUT_FREQ 48000000
+#define CY_CFG_SYSCLK_FLL_CCO_FREQ 320U
+#define CY_CFG_SYSCLK_FLL_OUT_FREQ 96000000
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 96UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
#define CY_CFG_SYSCLK_CLKHF1_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
-#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 8UL
-#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
+#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 96UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF2_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 24UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
+#define CY_CFG_SYSCLK_IHO_ENABLED 1
#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_MFO_ENABLED 1
+#define CY_CFG_SYSCLK_MFO_DEEPSLEEP_ENABLED false
#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IHO
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 7UL
#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IHO
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 7UL
#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IHO
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 7UL
#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL
-#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
-#define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO
-#define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U
+#define CY_CFG_SYSCLK_PILO_ENABLED 1
+#define CY_CFG_PWR_ENABLED 1
+#define CY_CFG_PWR_INIT 1
+#define CY_CFG_PWR_USING_PMIC 0
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_REGULATOR_MODE_MIN false
+#define CY_CFG_PWR_USING_ULP 0
-void cycfg_ClockStartupError(uint32_t error);
-
+#if (!defined(CY_DEVICE_SECURE))
+ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
+ {
+ .fllMult = 500U,
+ .refDiv = 125U,
+ .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
+ .enableOutputDiv = true,
+ .lockTolerance = 10U,
+ .igain = 9U,
+ .pgain = 4U,
+ .settlingCount = 48U,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+ .cco_Freq = 320U,
+ };
+#endif //(!defined(CY_DEVICE_SECURE))
#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 0U,
- .channel_num = 0U,
- };
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 0U,
+ .channel_num = 0U,
+ };
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 1U,
+ .channel_num = 0U,
+ };
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 2U,
+ .channel_num = 0U,
+ };
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 3U,
+ .channel_num = 0U,
+ };
#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 1U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 2U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 3U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
+static cy_stc_syspm_core_buck_params_t coreBuckConfigParam =
+{
+ .voltageSel = CY_CFG_PWR_CBUCK_VOLT,
+ .mode = CY_CFG_PWR_CBUCK_MODE,
+ .override = false,
+ .copySettings = false,
+ .useSettings = false,
+ .inRushLimitSel = 0,
+};
+static cy_stc_syspm_sdr_params_t sdr0ConfigParam =
+{
+ .coreBuckVoltSel = CY_CFG_PWR_CBUCK_VOLT,
+ .coreBuckMode = CY_CFG_PWR_CBUCK_MODE,
+ .coreBuckDpSlpVoltSel = CY_SYSPM_CORE_BUCK_VOLTAGE_0_90V,
+ .coreBuckDpSlpMode = CY_SYSPM_CORE_BUCK_MODE_LP,
+ .sdr0DpSlpVoltSel = CY_SYSPM_SDR_VOLTAGE_0_900V,
+ .sdrVoltSel = CY_CFG_PWR_SDR0_VOLT,
+ .sdr0Allowbypass = CY_CFG_PWR_SDR0_MODE_BYPASS,
+};
+static cy_stc_syspm_sdr_params_t sdr1ConfigParam =
+{
+ .coreBuckVoltSel = CY_CFG_PWR_CBUCK_VOLT,
+ .coreBuckMode = CY_CFG_PWR_CBUCK_MODE,
+ .sdrVoltSel = CY_CFG_PWR_SDR1_VOLT,
+ .sdr1HwControl = true,
+ .sdr1Enable = true,
+};
__WEAK void cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
- while (true) {}
+ while(1);
}
-__STATIC_INLINE void Cy_SysClk_FllInit(void)
-{
- Cy_SysClk_FllOutputDividerEnable(false);
-
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(0UL))
+#if (!defined(CY_DEVICE_SECURE))
+ __STATIC_INLINE void Cy_SysClk_FllDeInit()
{
- cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ Cy_SysClk_FllDisable();
+ }
+ __STATIC_INLINE void Cy_SysClk_ClkBakInit()
+ {
+ Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+ }
+ __STATIC_INLINE void Cy_SysClk_FllInit()
+ {
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ }
+ }
+ __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
+ {
+ Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ }
+ __STATIC_INLINE void Cy_SysClk_ClkHf1Init()
+ {
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
+ }
+ __STATIC_INLINE void Cy_SysClk_ClkHf2Init()
+ {
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
+ }
+ __STATIC_INLINE void Cy_SysClk_ClkHf3Init()
+ {
+ Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+ Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
+ }
+#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_IhoInit()
+{
+ Cy_SysClk_IhoEnable();
+}
+#if (!defined(CY_DEVICE_SECURE))
+ __STATIC_INLINE void Cy_SysClk_ClkLfInit()
+ {
+ /* The WDT is unlocked in the default startup code */
+ Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_PILO);
+ }
+#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_MfoInit()
+{
+ Cy_SysClk_MfoEnable(CY_CFG_SYSCLK_MFO_DEEPSLEEP_ENABLED);
+}
+#if (!defined(CY_DEVICE_SECURE))
+ __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
+ {
+ Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+ }
+ __STATIC_INLINE void Cy_SysClk_ClkPath1Init()
+ {
+ Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+ }
+ __STATIC_INLINE void Cy_SysClk_ClkPath2Init()
+ {
+ Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+ }
+ __STATIC_INLINE void Cy_SysClk_ClkPath3Init()
+ {
+ Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
+ }
+#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_PiloInit()
+{
+ Cy_SysClk_PiloEnable();
+
+ if(!Cy_SysClk_PiloOkay())
+ {
+ Cy_SysPm_TriggerXRes();
}
}
-__STATIC_INLINE void Cy_SysClk_ClkHf0Init(void)
+__STATIC_INLINE void init_cycfg_power(void)
{
- (void)Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
- (void)Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf1Init(void)
-{
- (void)Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
- (void)Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
- (void)Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath0Init(void)
-{
- (void)Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath1Init(void)
-{
- (void)Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath2Init(void)
-{
- (void)Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath3Init(void)
-{
- (void)Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
+ CY_UNUSED_PARAMETER(sdr1ConfigParam); /* Suppress a compiler warning about unused variables */
+
+ Cy_SysPm_Init();
+ /* **Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD** */
+ #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+ #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+ if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+ {
+ Cy_SysLib_ResetBackupDomain();
+ Cy_SysClk_IloDisable();
+ Cy_SysClk_IloInit();
+ }
+ #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
+ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+ /* **System Active Power Mode Profile Configuration** */
+ /* Core Buck Regulator Configuration */
+ Cy_SysPm_CoreBuckConfig(&coreBuckConfigParam);
+
+ /* SDR0 Regulator Configuration */
+ Cy_SysPm_SdrConfigure(CY_SYSPM_SDR_0, &sdr0ConfigParam);
+
+ /* SDR1 Regulator Configuration */
+ #if (CY_CFG_PWR_SDR1_ENABLE)
+ Cy_SysPm_SdrConfigure(CY_SYSPM_SDR_1, &sdr1ConfigParam);
+ #endif /* CY_CFG_PWR_SDR1_VOLT */
+
+ /* **System Active Low Power Profile(LPACTIVE/LPSLEEP) Configuration** */
+ #if (CY_CFG_PWR_SYS_LP_PROFILE_MODE)
+ Cy_SysPm_SystemLpActiveEnter();
+ #endif /* CY_CFG_PWR_SYS_ACTIVE_MODE */
+
+ /* **System Regulators Low Current Configuration** */
+ #if (CY_CFG_PWR_REGULATOR_MODE_MIN)
+ Cy_SysPm_SystemSetMinRegulatorCurrent();
+ #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
+
+ /* **System Idle Power Mode Configuration** */
+ #if (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP)
+ Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP);
+ #elif (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP_RAM)
+ Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_RAM);
+ #elif (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_DEEPSLEEP_OFF)
+ Cy_SysPm_SetDeepSleepMode(CY_SYSPM_MODE_DEEPSLEEP_OFF);
+ #endif /* CY_CFG_PWR_SYS_IDLE_MODE */
}
void init_cycfg_system(void)
{
+ #ifdef CY_CFG_PWR_ENABLED
+ #ifdef CY_CFG_PWR_INIT
+ init_cycfg_power();
+ #else
+ #warning Power system will not be configured. Update power personality to v1.20 or later.
+ #endif /* CY_CFG_PWR_INIT */
+ #endif /* CY_CFG_PWR_ENABLED */
+
+ /* Disable FLL */
+ Cy_SysClk_FllDeInit();
+
+ /* Enable all source clocks */
+ #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+ Cy_SysClk_PiloInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+ Cy_SysClk_WcoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+ Cy_SysClk_ClkLfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+ Cy_SysClk_ExtClkInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_IHO_ENABLED
+ Cy_SysClk_IhoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+ Cy_SysClk_AltHfInit();
+ #endif
+
+ /* Configure Path Clocks */
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+ Cy_SysClk_ClkPath2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+ Cy_SysClk_ClkPath3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+ Cy_SysClk_ClkPath4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+ Cy_SysClk_ClkPath5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+ Cy_SysClk_ClkPath6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+ Cy_SysClk_ClkPath7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+ Cy_SysClk_ClkPath8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+ Cy_SysClk_ClkPath9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+ Cy_SysClk_ClkPath10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+ Cy_SysClk_ClkPath11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+ Cy_SysClk_ClkPath12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+ Cy_SysClk_ClkPath13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+ Cy_SysClk_ClkPath14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+ Cy_SysClk_ClkPath15Init();
+ #endif
+
+ /* Configure HF clocks */
+ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+ Cy_SysClk_ClkHf1Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+ Cy_SysClk_ClkHf2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+ Cy_SysClk_ClkHf3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+ Cy_SysClk_ClkHf4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+ Cy_SysClk_ClkHf5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+ Cy_SysClk_ClkHf6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+ Cy_SysClk_ClkHf7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+ Cy_SysClk_ClkHf8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+ Cy_SysClk_ClkHf9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+ Cy_SysClk_ClkHf10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+ Cy_SysClk_ClkHf11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+ Cy_SysClk_ClkHf12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+ Cy_SysClk_ClkHf13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+ Cy_SysClk_ClkHf14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+ Cy_SysClk_ClkHf15Init();
+ #endif
+
+ /* Configure miscellaneous clocks */
+ #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+ Cy_SysClk_ClkAltSysTickInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+ Cy_SysClk_ClkPumpInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+ Cy_SysClk_ClkBakInit();
+ #endif
+
+ /* Configure default enabled clocks */
+ #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+ Cy_SysClk_IloInit();
+ #endif
+
+ #ifndef CY_CFG_SYSCLK_IMO_ENABLED
+ #error the IMO must be enabled for proper chip operation
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+ Cy_SysClk_MfoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+ Cy_SysClk_ClkMfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+ Cy_SysClk_ClkPath0Init();
+ #endif
+ /* Configure and enable FLL */
+ #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+ Cy_SysClk_FllInit();
+ #endif
+
+ Cy_SysClk_ClkHf0Init();
+
+ /* Disable Unused Clock Sources */
+ #ifndef CY_CFG_SYSCLK_IHO_ENABLED
+ Cy_SysClk_IhoDisable();
+ #endif
+#if defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
+ Cy_SysClk_EcoPrescalerInit();
+#endif //defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
+ /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+ SystemCoreClockUpdate();
+#if (!defined(CY_DEVICE_SECURE))
+ CY_UNUSED_PARAM(srss_0_clock_0_fll_0_fllConfig);
+#endif //(!defined(CY_DEVICE_SECURE))
+}
- /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
- Cy_SysLib_SetWaitStates(false, 150UL);
- #ifdef CY_CFG_PWR_ENABLED
- #ifdef CY_CFG_PWR_INIT
- init_cycfg_power();
- #else
- #warning Power system will not be configured. Update power personality to v1.20 or later.
- #endif /* CY_CFG_PWR_INIT */
- #endif /* CY_CFG_PWR_ENABLED */
-
- /* Reset the core clock path to default and disable all the FLLs*/
- (void)Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
- (void)Cy_SysClk_ClkPathSetSource((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
-
- if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
- (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0)))
- {
- (void)Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
- }
-
- (void)Cy_SysClk_FllDisable();
- (void)Cy_SysClk_ClkPathSetSource((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
- (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
- #ifdef CY_IP_MXBLESS
- (void)Cy_BLE_EcoReset();
- #endif
-
-
- /* Enable all source clocks */
- #ifdef CY_CFG_SYSCLK_PILO_ENABLED
- Cy_SysClk_PiloInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_WCO_ENABLED
- Cy_SysClk_WcoInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
- Cy_SysClk_ClkLfInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
- Cy_SysClk_AltHfInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_ECO_ENABLED
- Cy_SysClk_EcoInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
- Cy_SysClk_ExtClkInit();
- #endif
-
- #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
- /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
- (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
- (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
- #else
- #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
- Cy_SysClk_ClkPath1Init();
- #endif
- #endif
-
- /* Configure Path Clocks */
- #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
- Cy_SysClk_ClkPath0Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
- Cy_SysClk_ClkPath2Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
- Cy_SysClk_ClkPath3Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
- Cy_SysClk_ClkPath4Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
- Cy_SysClk_ClkPath5Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
- Cy_SysClk_ClkPath6Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
- Cy_SysClk_ClkPath7Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
- Cy_SysClk_ClkPath8Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
- Cy_SysClk_ClkPath9Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
- Cy_SysClk_ClkPath10Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
- Cy_SysClk_ClkPath11Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
- Cy_SysClk_ClkPath12Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
- Cy_SysClk_ClkPath13Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
- Cy_SysClk_ClkPath14Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
- Cy_SysClk_ClkPath15Init();
- #endif
-
- /* Configure and enable FLL */
- #ifdef CY_CFG_SYSCLK_FLL_ENABLED
- Cy_SysClk_FllInit();
- #endif
-
- Cy_SysClk_ClkHf0Init();
-
- #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
- #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
- /* Apply the ClkPath1 user setting */
- Cy_SysClk_ClkPath1Init();
- #endif
- #endif
-
- /* Configure HF clocks */
- #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
- Cy_SysClk_ClkHf1Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
- Cy_SysClk_ClkHf2Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
- Cy_SysClk_ClkHf3Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
- Cy_SysClk_ClkHf4Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
- Cy_SysClk_ClkHf5Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
- Cy_SysClk_ClkHf6Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
- Cy_SysClk_ClkHf7Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
- Cy_SysClk_ClkHf8Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
- Cy_SysClk_ClkHf9Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
- Cy_SysClk_ClkHf10Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
- Cy_SysClk_ClkHf11Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
- Cy_SysClk_ClkHf12Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
- Cy_SysClk_ClkHf13Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
- Cy_SysClk_ClkHf14Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
- Cy_SysClk_ClkHf15Init();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
- Cy_SysClk_ClkAltSysTickInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
- Cy_SysClk_ClkPumpInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
- Cy_SysClk_ClkBakInit();
- #endif
-
- /* Configure default enabled clocks */
- #ifdef CY_CFG_SYSCLK_ILO_ENABLED
- Cy_SysClk_IloInit();
- #endif
-
- #ifndef CY_CFG_SYSCLK_IMO_ENABLED
- #error the IMO must be enabled for proper chip operation
- #endif
-
- #ifdef CY_CFG_SYSCLK_MFO_ENABLED
- Cy_SysClk_MfoInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
- Cy_SysClk_ClkMfInit();
- #endif
-
- /* Set accurate flash wait states */
- #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
- Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
- #endif
-
- /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
- SystemCoreClockUpdate();
-
+void reserve_cycfg_system(void)
+{
#if defined (CY_USING_HAL)
- (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
- (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
- (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
- (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
#endif //defined (CY_USING_HAL)
}
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_system.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.h
index 34b2a67..6395d20 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_system.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.h
@@ -4,13 +4,13 @@
* Description:
* System configuration
* This file was automatically generated and should not be modified.
-* Tools Package 2.2.1.3040
-* integration_mxs40sv2-LATEST 3.0.0.5994
-* personalities 3.0.0.0
-* udd 3.0.0.775
+* Configurator Backend 3.10.0
+* device-db 4.100.0.4783
+* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -31,46 +31,76 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
-#include "cy_pra.h"
-#include "cy_pra_cfg.h"
#if defined (CY_USING_HAL)
- #include "cyhal_hwmgr.h"
+ #include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
+#include "cy_syspm.h"
#if defined(__cplusplus)
extern "C" {
#endif
#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
#define srss_0_clock_0_hfclk_1_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF1 1UL
-#define CY_CFG_SYSCLK_CLKHF1_CLKPATH_NUM 1UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH_NUM 0UL
+#define srss_0_clock_0_hfclk_2_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF2 2UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 2UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 1UL
#define srss_0_clock_0_iho_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_PILO
+#define srss_0_clock_0_mfo_0_ENABLED 1U
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pilo_0_ENABLED 1U
#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP_RAM 0x11UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP_OFF 0x12UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_SYS_ACTIVE_PROFILE CY_CFG_PWR_MODE_POWER_PROFILE_0
+#define CY_CFG_PWR_SYS_LP_PROFILE_MODE 0
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VDDBUCK 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+#define CY_CFG_PWR_CBUCK_VOLT CY_SYSPM_CORE_BUCK_VOLTAGE_1_16V
+#define CY_CFG_PWR_CBUCK_MODE CY_SYSPM_CORE_BUCK_MODE_HP
+#define CY_CFG_PWR_SDR0_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
+#define CY_CFG_PWR_SDR0_MODE_BYPASS true
+#define CY_CFG_PWR_SDR1_VOLT CY_SYSPM_SDR_VOLTAGE_1_100V
+#define CY_CFG_PWR_SDR1_ENABLE true
#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
+void reserve_cycfg_system(void);
#if defined(__cplusplus)
}
diff --git a/boot/cypress/platforms/BSP/CYW20829/qspi_config.cfg b/boot/cypress/platforms/BSP/CYW20829/qspi_config.cfg
index 8858f3f..9871a11 100644
--- a/boot/cypress/platforms/BSP/CYW20829/qspi_config.cfg
+++ b/boot/cypress/platforms/BSP/CYW20829/qspi_config.cfg
@@ -4,10 +4,11 @@
# Description:
# This file contains a SMIF Bank layout for use with OpenOCD.
# This file was automatically generated and should not be modified.
-# QSPI Configurator: 2.30.0.4366
+# QSPI Configurator: 4.10.0.1343
#
################################################################################
-# Copyright 2021 Cypress Semiconductor Corporation
+# Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation.
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -24,6 +25,5 @@
################################################################################
set SMIF_BANKS {
- 0 {addr 0x60000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+ 0 {addr 0x60000000 size 0x100000 psize 0x0000100 esize 0x0001000}
}
-
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c
index 832ff88..c77911d 100644
--- a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c
+++ b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c
@@ -1,8 +1,8 @@
/***************************************************************************//**
-* \file ns_start_cyw20829.c
-* \version 1.1
+* \file startup_cat1b_cm33.c
+* \version 1.2
*
-* The cyw20829 startup source.
+* The CAT1B CM33 startup source.
*
********************************************************************************
* \copyright
@@ -24,82 +24,85 @@
*******************************************************************************/
#include "cy_device.h"
-#if defined (CY_DEVICE_CYW20829)
+
+#if defined (CY_IP_M33SYSCPUSS)
#include <stdio.h>
#include <stdint.h>
#include <stddef.h>
#include "startup_cat1b.h"
-#include "cy_sysint.h"
-#include "cy_syspm.h"
#include "cy_syslib.h"
#include "cmsis_compiler.h"
-CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.6', 3, \
-'Checked manually. The definition is a part of linker script or application.')
-CY_MISRA_DEVIATE_BLOCK_START('ARRAY_VS_SINGLETON', 1, \
-'Checked manually. Using pointer as an array will not corrupt or misinterpret adjacent memory locations.')
-CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 18.1', 3, \
-'Checked manually. Dereferencing a pointer to one beyond the end of an array will not result in undefined behaviour.')
-CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 18.3', 1, \
-'Checked manually. Attempting to make comparisons between pointers will not result in undefined behaviour.')
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern unsigned int __INITIAL_SP;
+extern unsigned int __STACK_LIMIT;
-#if defined (__ARMCC_VERSION)
-extern uint32_t Region$$Table$$Base;
-extern uint32_t Region$$Table$$Limit;
-typedef void(*pGenericFunction)(uint8_t *pSrc, uint8_t* pDst, uint32_t len); /* typedef for the generic function pointers */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+extern uint32_t __STACK_SEAL;
#endif
-__WEAK interrupt_type void Reset_Handler(void);
-interrupt_type void MemManage_Handler(void);
-interrupt_type void BusFault_Handler(void);
-interrupt_type void UsageFault_Handler(void);
-__WEAK interrupt_type void SVC_Handler(void);
-interrupt_type void DebugMon_Handler(void);
-__WEAK interrupt_type void PendSV_Handler(void);
-__WEAK interrupt_type void SysTick_Handler(void);
-interrupt_type void InterruptHandler(void);
-interrupt_type void NMIException_Handler(void);
-interrupt_type void HardFault_Handler(void);
-void delay_infinite(void);
-void SysLib_FaultHandler(uint32_t const *faultStackAddr);
-__WEAK void cy_toolchain_init(void);
-
-extern int main(void);
-
-#if defined (__ARMCC_VERSION)
-void __attribute__((optnone)) Cy_RuntimeInit(void);
-#else
-void Cy_RuntimeInit(void);
-#endif
+extern __NO_RETURN void __PROGRAM_START(void);
#if defined(__ARMCC_VERSION)
-extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for (default) One Region model */
-interrupt_type extern void __main(void);
-typedef void(* ExecFuncPtrRw)(void) interrupt_type;
-ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#if defined(CY_PDL_TZ_ENABLED)
+cy_israddress_cat1b __s_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#else
+cy_israddress_cat1b __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#endif
#elif defined (__GNUC__)
-extern unsigned int __StackTop;
-extern uint32_t __StackLimit;
-typedef void(* interrupt_type ExecFuncPtrRw)(void);
-ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#if defined(CY_PDL_TZ_ENABLED)
+cy_israddress_cat1b __s_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#else
+cy_israddress_cat1b __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#endif
#elif defined (__ICCARM__)
-extern unsigned int CSTACK$$Limit; /* for (default) One Region model */
-interrupt_type extern void __cmain();
-ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#if defined(CY_PDL_TZ_ENABLED)
+cy_israddress_cat1b __s_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#else
+cy_israddress_cat1b __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#endif
#else
#error "An unsupported toolchain"
#endif /* (__ARMCC_VERSION) */
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler (void);
+void SysLib_FaultHandler(uint32_t const *faultStackAddr);
+void Default_Handler(void);
+
void SysLib_FaultHandler(uint32_t const *faultStackAddr)
{
Cy_SysLib_FaultHandler(faultStackAddr);
}
+/*----------------------------------------------------------------------------
+ Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+ while(1);
+}
+
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void NMIException_Handler(void);
+void HardFault_Handler(void);
+void InterruptHandler(void);
+__WEAK void cy_toolchain_init(void);
+
+
// Exception Vector Table & Handlers
//----------------------------------------------------------------
-interrupt_type void NMIException_Handler(void)
+void NMIException_Handler(void)
{
__asm volatile(
"bkpt #10\n"
@@ -107,7 +110,7 @@
);
}
-interrupt_type void HardFault_Handler(void)
+void HardFault_Handler(void)
{
__asm (
"MRS R0, CONTROL\n"
@@ -119,15 +122,8 @@
);
}
-interrupt_type void MemManage_Handler(void) {while(true){}}
-interrupt_type void BusFault_Handler(void) {while(true){}}
-interrupt_type void UsageFault_Handler(void) {while(true){}}
-__WEAK interrupt_type void SVC_Handler(void) {while(true){}}
-interrupt_type void DebugMon_Handler(void) {while(true){}}
-__WEAK interrupt_type void PendSV_Handler(void) {while(true){}}
-__WEAK interrupt_type void SysTick_Handler(void) {while(true){}}
-interrupt_type void InterruptHandler(void)
+void InterruptHandler(void)
{
__asm volatile(
"bkpt #1\n"
@@ -135,273 +131,77 @@
);
}
-ExecFuncPtr __ns_vector_table[] __VECTOR_TABLE_ATTRIBUTE = {
- (ExecFuncPtr)&__INITIAL_SP,
- (ExecFuncPtr)Reset_Handler, // initial PC/Reset
- (ExecFuncPtr)NMIException_Handler,
- (ExecFuncPtr)HardFault_Handler,
- (ExecFuncPtr)MemManage_Handler, // Memory Manage Fault
- (ExecFuncPtr)BusFault_Handler, // Bus Fault
- (ExecFuncPtr)UsageFault_Handler, // Usage Fault
- 0, // Secire Fault
- 0, // RESERVED
- 0, // RESERVED
- 0, // RESERVED
- (ExecFuncPtr)SVC_Handler, // SVC
- 0, // debug
- 0, // RESERVED
- (ExecFuncPtr)PendSV_Handler, // Pend SV
- (ExecFuncPtr)SysTick_Handler, // Secure systick
- /* External interrupts */
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler,
- (ExecFuncPtr)InterruptHandler
+void MemManage_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler (void) __attribute__ ((weak, alias("HardFault_Handler")));
+void UsageFault_Handler (void) __attribute__ ((weak, alias("HardFault_Handler")));
+ void SVC_Handler (void) __attribute__ ((weak, alias("HardFault_Handler")));
+void DebugMon_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+
+void Interrupt0_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+void Interrupt1_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+void Interrupt2_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+void Interrupt3_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+void Interrupt4_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+void Interrupt5_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+void Interrupt6_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+void Interrupt7_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+void Interrupt8_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+void Interrupt9_Handler (void) __attribute__ ((weak, alias("InterruptHandler")));
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+const cy_israddress __Vectors[VECTORTABLE_SIZE];
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+const cy_israddress __Vectors[VECTORTABLE_SIZE] __VECTOR_TABLE_ATTRIBUTE = {
+ (cy_israddress)(&__INITIAL_SP), /* Initial Stack Pointer */
+ (cy_israddress)Reset_Handler, /* Reset Handler */
+ (cy_israddress)NMIException_Handler, /* -14 NMI Handler */
+ (cy_israddress)HardFault_Handler, /* -13 Hard Fault Handler */
+ (cy_israddress)MemManage_Handler, /* -12 MPU Fault Handler */
+ (cy_israddress)BusFault_Handler, /* -11 Bus Fault Handler */
+ (cy_israddress)UsageFault_Handler, /* -10 Usage Fault Handler */
+ 0, /* -9 Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ (cy_israddress)SVC_Handler, /* -5 SVCall Handler */
+ 0, /* -4 Debug Monitor Handler */
+ 0, /* Reserved */
+ (cy_israddress)PendSV_Handler, /* -2 PendSV Handler */
+ (cy_israddress)SysTick_Handler, /* -1 SysTick Handler */
+
+ /* Interrupts */
+ (cy_israddress)Interrupt0_Handler, /* 0 Interrupt 0 */
+ (cy_israddress)Interrupt1_Handler, /* 1 Interrupt 1 */
+ (cy_israddress)Interrupt2_Handler, /* 2 Interrupt 2 */
+ (cy_israddress)Interrupt3_Handler, /* 3 Interrupt 3 */
+ (cy_israddress)Interrupt4_Handler, /* 4 Interrupt 4 */
+ (cy_israddress)Interrupt5_Handler, /* 5 Interrupt 5 */
+ (cy_israddress)Interrupt6_Handler, /* 6 Interrupt 6 */
+ (cy_israddress)Interrupt7_Handler, /* 7 Interrupt 7 */
+ (cy_israddress)Interrupt8_Handler, /* 8 Interrupt 8 */
+ (cy_israddress)Interrupt9_Handler, /* 9 Interrupt 9 */
+ /* Interrupts 10 .. 480 are left out */
+
};
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
/* Provide empty __WEAK implementation for the low-level initialization
routine required by the RTOS-enabled applications.
clib-support library provides FreeRTOS-specific implementation:
https://github.com/Infineon/clib-support */
-void cy_toolchain_init(void);
__WEAK void cy_toolchain_init(void)
{
}
@@ -433,9 +233,10 @@
/**/
#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */
-
-// Reset Handler
-__WEAK interrupt_type void Reset_Handler(void)
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__NO_RETURN void Reset_Handler(void)
{
/* Disable I cache */
ICACHE0->CTL = ICACHE0->CTL & (~ICACHE_CTL_CA_EN_Msk);
@@ -450,17 +251,22 @@
for (uint32_t count = 0; count < VECTORTABLE_SIZE; count++)
{
- __ns_vector_table_rw[count] =__ns_vector_table[count];
+ #if defined(CY_PDL_TZ_ENABLED)
+ __s_vector_table_rw[count] =__Vectors[count];
+ #else
+ __ns_vector_table_rw[count] =__Vectors[count];
+ #endif
}
-
+ #if defined(CY_PDL_TZ_ENABLED)
+ SCB->VTOR = (uint32_t)__s_vector_table_rw;
+ #else
SCB->VTOR = (uint32_t)__ns_vector_table_rw;
+ #endif
+
__DMB();
-#ifdef CY_PDL_FLASH_BOOT
-#if !defined (__ARMCC_VERSION)
- bootstrapInit();
-#endif
-#endif
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+
SystemInit();
#if defined(__ICCARM__)
@@ -477,9 +283,15 @@
__PROGRAM_START();
}
-CY_MISRA_BLOCK_END('MISRA C-2012 Rule 18.3')
-CY_MISRA_BLOCK_END('MISRA C-2012 Rule 18.1')
-CY_MISRA_BLOCK_END('ARRAY_VS_SINGLETON')
-CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6')
-#endif /* defined (CY_DEVICE_CYW20829) */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wmissing-noreturn"
+#endif
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#endif
+
+#endif /* CY_IP_M33SYSCPUSS */
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c
index 2a9083d..30a600f 100644
--- a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c
+++ b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c
@@ -1,6 +1,6 @@
/***************************************************************************//**
-* \file ns_system_cyw20829.c
-* \version 1.1
+* \file system_cyw20829.c
+* \version 1.3
*
* The device system-source file.
*
@@ -26,8 +26,9 @@
#include "cy_device.h"
#if defined (CY_DEVICE_CYW20829)
+
#include <stdbool.h>
-#include "system_cyw20829.h"
+#include "system_cat1b.h"
#include "cy_syslib.h"
#include "cy_wdt.h"
#include "cy_sysclk.h"
@@ -114,9 +115,10 @@
void SystemInit_CAT1B_CM33(void)
{
- /* Release reset for all groups IP except group 0 */
+ /* Release reset for all groups IP except group 0 and group 3 */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U); /* typecast void to suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U); /* typecast void to suppress a compiler warning about unused return value */
+ (void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x1U); /* typecast void to suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU); /* typecast void to suppress a compiler warning about unused return value */
(void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU); /* typecast void to suppress a compiler warning about unused return value */
@@ -125,20 +127,6 @@
Cy_PDL_Init(CY_DEVICE_CFG);
(void)Cy_SystemInit(); /* typecast void to suppress a compiler warning about unused return value */
- if(CY_SYSPM_WARM_BOOT_MODE == Cy_SysPm_GetBootMode())
- {
- /* Unfreeze the IO's which are frozen during DEEPSLEEP-RAM and DEEPSLEEP-OFF Entry */
- if(Cy_SysPm_DeepSleepIoIsFrozen())
- {
- Cy_SysPm_DeepSleepIoUnfreeze();
- }
- }
- else
- {
- /* Reset BT IP only during cold boot */
- (void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U); /* typecast void to suppress a compiler warning about unused return value */
- }
-
/* Unlock and disable WDT */
Cy_WDT_Unlock();
Cy_WDT_Disable();
@@ -170,6 +158,8 @@
{
Cy_SysPm_DeepSleepIoUnfreeze();
}
+
+ cy_WakeupFromWarmBootStatus = true;
}
CY_SECTION_RAMFUNC_END
@@ -188,6 +178,7 @@
* Stores the NVIC register before Deepsleep RAM:
*
*******************************************************************************/
+CY_SECTION_RAMFUNC_BEGIN
void System_Store_NVIC_Reg(void)
{
for (uint32_t idx = 0; idx < CY_NVIC_REG_COUNT; idx++)
@@ -202,6 +193,7 @@
scbSHPR3StoreRestore = SCB_SHPR3_REG;
}
+CY_SECTION_RAMFUNC_END
/*******************************************************************************
@@ -211,6 +203,7 @@
* Restores the NVIC register After Deepsleep RAM Wakeup i.e. Warmboot:
*
*******************************************************************************/
+CY_SECTION_RAMFUNC_BEGIN
void System_Restore_NVIC_Reg(void)
{
for (uint32_t idx = 0; idx < CY_NVIC_REG_COUNT; idx++)
@@ -225,8 +218,17 @@
SCB_SHPR3_REG = scbSHPR3StoreRestore;
}
+CY_SECTION_RAMFUNC_END
+
void SystemInit(void)
{
+
+ #ifdef CY_PDL_FLASH_BOOT
+ #if !defined (__ARMCC_VERSION)
+ bootstrapInit();
+ #endif
+ #endif
+
SystemInit_CAT1B_CM33();
};
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h b/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h
index 953b5a1..862b5b5 100644
--- a/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h
+++ b/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h
@@ -27,29 +27,35 @@
#ifndef STARTUP_CAT1B_H_
#define STARTUP_CAT1B_H_
+#include "cy_device_headers.h"
+
+
+typedef void (* cy_israddress_cat1b)(void); /**< Type of ISR callbacks */
+
#define CM33_FIXED_EXP_NR (15u)
#define VECTORTABLE_SIZE (MXCM33_SYSTEM_INT_NR + CM33_FIXED_EXP_NR + 1u) /* +1 is for Stack pointer */
-#define VECTORTABLE_ALIGN (512) /* alignment for 85 entries (85x4=340) is 512 bytes */
+#define VECTORTABLE_ALIGN (VECTORTABLE_SIZE <= 512u ? 512u :1024u) /* alignment for 'n' entries is (nx4) */
#if defined(__ARMCC_VERSION)
- #define interrupt_type __attribute__((interrupt))
- typedef void(* ExecFuncPtrRw)(void) interrupt_type;
- typedef void(* const ExecFuncPtr)(void) interrupt_type; /* typedef for the function pointers in the vector table */
- extern ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN))); /**< Non-secure vector table in flash/ROM */
+#if defined(CY_PDL_TZ_ENABLED)
+ extern cy_israddress_cat1b __s_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#else
+ extern cy_israddress_cat1b __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#endif
#elif defined (__GNUC__)
- #define interrupt_type __attribute__((interrupt))
- typedef void(* interrupt_type ExecFuncPtrRw)(void);
- typedef void(* interrupt_type ExecFuncPtr)(void) ; /* typedef for the function pointers in the vector table */
- extern ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN))); /**< Non-secure vector table in flash/ROM */
+#if defined(CY_PDL_TZ_ENABLED)
+ extern cy_israddress_cat1b __s_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#else
+ extern cy_israddress_cat1b __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#endif
#elif defined (__ICCARM__)
- #define interrupt_type __irq
- typedef interrupt_type void(* ExecFuncPtrRw)(void) ;
- typedef interrupt_type void(* const ExecFuncPtr)(void) ; /* typedef for the function pointers in the vector table */
- extern ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN))); /**< Non-secure vector table in flash/ROM */
+#if defined(CY_PDL_TZ_ENABLED)
+ extern cy_israddress_cat1b __s_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#else
+ extern cy_israddress_cat1b __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#endif
#else
#error "An unsupported toolchain"
#endif /* (__ARMCC_VERSION) */
-extern ExecFuncPtr __ns_vector_table[]; /**< Non-secure vector table in non-secure SRAM */
#endif /* STARTUP_CAT1B_H_ */
-
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h b/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h
index 0c4ec1d..81c48fd 100644
--- a/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h
+++ b/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h
@@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_cat1b.h
-* \version 1.1
+* \version 1.2
*
* \brief CAT1B Device system header file.
*
@@ -26,11 +26,281 @@
#ifndef _SYSTEM_CAT1B_H_
#define _SYSTEM_CAT1B_H_
+/**
+* \addtogroup group_system_config_cm33
+* \{
+* Provides device startup, system configuration, and linker script files.
+* The system startup provides the followings features:
+* - \ref group_system_config_device_memory_definition_cm33
+* - \ref group_system_config_device_initialization_cm33
+* - \ref group_system_config_heap_stack_config_cm33
+* - \ref group_system_config_default_handlers_cm33
+* - \ref group_system_config_device_vector_table_cm33
+*
+* \section group_system_config_configuration_cm33 Configuration Considerations
+*
+* \subsection group_system_config_device_memory_definition_cm33 Device Memory Definition
+* Allocation of different types of memory such as the ROM, flash and RAM etc. for the CPU is defined by the linker scripts.
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see warnings during the build process. To eliminate build
+* warnings in your project, you can simply comment out or remove the relevant
+* code in the linker file.
+*
+* <b>For CYW20829</b>
+*
+* <b>ARM GCC</b>\n
+* The ROM, flash and RAM sections for the CPU are defined in the linker file:
+* 'cyw20829_ns_flash_cbus.ld', where 'ns' indicates that the
+* linker script file is for non-secure image.
+* For devices without security extension, there will be only one linker file and it
+* is always non-secure.
+*
+* Memory sections are for the GNU GCC ARM tool set is defined in the linker file
+* cyw20829_ns_flash_cbus.ld. Following are the important memory sections for the User/Application image.
+*
+* Memory sections are for the GNU GCC ARM tool set is defined in the linker file
+* \<device\>_ns.sct. Following are the important memory sections for the User/Application image.
+* \code
+* code (rx) : ORIGIN = CODE_VMA, LENGTH = CODE_BS_SIZE Starting address and the size of Non-secure bootstrap code
+* bsData (rwx) : ORIGIN = DATA_BS_VMA, LENGTH = DATA_BS_SIZE Starting address and the size of Non-secure bootstrap data
+* appCodeRam (rx) : ORIGIN = DATA_CBUS_VMA, LENGTH = DATA_SIZE Starting address and the size of Non-secure application ram functions
+* data (rwx) : ORIGIN = DATA_VMA, LENGTH = DATA_SIZE Starting address and the size of Non-secure application data
+* xip (rx) : ORIGIN = XIP_VMA, LENGTH = XIP_SIZE Starting address and the size of Non-secure application code
+* \endcode
+*
+* \note In CYW20829, the Bootstrap memory is used to place the startup code along with SMIF driver in the ram area. The size requirement for Bootstrap may vary
+* depending on the number of functions that are linked from SMIF driver. When more functions are linked, you may see linker error.
+* In order to fix this you need to increase Bootstarp memory size in the ram by modifying the value of BOOTSTRAP_OFFSET_RAM.\n
+* E.g. if linker error suggests to increase by 8192 bytes, then you need to move the starting address of the bootstrap memory up by 8192 bytes as shown below \n
+* BOOTSTRAP_OFFSET_RAM = 0x0001E000; Old value\n
+* BOOTSTRAP_OFFSET_RAM = 0x0001C000; New value\n
+* Because of the change in the bootstrap size, you may also need to move the application start address in the flash. If you see a linker error after above change,
+* then you need to modify the application code offset APPCODE_OFFSET_FLASH in the flash.\n
+* E.g. if linker error suggests 256 bytes overlap of .appText LMA with .bootstrapText LMA, you need to move the application start offset in the flash
+* down by 256 bytes as shown below\n
+* APPCODE_OFFSET_FLASH = 0x00002200; Old value\n
+* APPCODE_OFFSET_FLASH = 0x00002300; New value
+*
+* <b>ARM Compiler</b>\n
+* The ROM, flash and RAM sections for the CPU are defined in the linker file:
+* 'cyw20829_ns_flash_cbus.sct', where 'ns' indicates that the
+* linker script file is for non-secure image.
+* For devices without security extension, there will be only one linker file and it
+* is always non-secure.
+*
+* Memory sections are for the GNU GCC ARM tool set is defined in the linker file
+* cyw20829_ns_flash_cbus.sct. Following are the important memory sections for the User/Application image.
+* \code
+* bootstrapText_vma Starting address of bootstrap code
+* bootstrapText_size Size of memory reserved for Bootstrap code
+* bootstrapData_vma Starting address of Bootstrap data
+* appText_vma Stating address of application code
+* appData_vma Stating address of application data
+* \endcode
+*
+* <b>IAR</b>\n
+* The ROM, flash and RAM sections for the CPU are defined in the linker file:
+* 'cyw20829_ns_flash_cbus.icf', where 'ns' indicates that the
+* linker script file is for non-secure image.
+* For devices without security extension, there will be only one linker file and it
+* is always non-secure.
+*
+* Memory sections are for the GNU GCC ARM tool set is defined in the linker file
+* cyw20829_ns_flash_cbus.icf. Following are the important memory sections for the User/Application image.
+* \code
+* define region CODE_region = mem:[from CODE_VMA size CODE_BS_SIZE]; Bootstrap code region and size
+* define region DATA_BS_region = mem:[from DATA_BS_VMA size DATA_BS_SIZE]; Bootstrap data region and size
+* define region DATA_region = mem:[from DATA_VMA size DATA_SIZE]; Application data region and size
+* define region XIP_region = mem:[from XIP_VMA size XIP_SIZE]; Application code (xip) region and size
+* \endcode
+*
+* \subsection group_system_config_device_initialization_cm33 Device Initialization
+* <b>CM33 Without ARM TrustZone Support:</b><br/>
+* Below MSC describes the simplified startup sequence starting from reset release of the core. As soon as the reset
+* is released, the execution starts form the ROM interrupt vector table reset vector. The ROM code initializes the basic
+* clock needed to access and configure MMIO registers and then sets up debug port so that the debugger can be attached.
+* After it finishes all the necessary initialization, it reads the bootstrap (part of non secure application image)
+* location, size from TOC2 header and loads the bootstrap code into SRAM.
+*
+* Before switching execution to the non-secure application code, the ROM code needs to initialize the stack pointer
+* MSP_NS for the non-secure code. This value is picked form the first entry in the non-secure bootstrap's vector
+* table __ns_vector_table. Once the non-secure stack is initialized, the ROM code will call the non-secure code entry
+* point which is nothing but the Reset_Handler. Address of this function is picked form the second entry in the non-secure
+* vector table __ns_vector_table and type casting it to function pointer.
+*
+* In the non-secure Reset_Handler, the vector table is copied to RAM area and then the address of the vector table is set
+* to VTOR register. This calls SystemInit function which internally calls Cy_PDL_Init, Cy_SystemInit and SystemCoreClockUpdate
+* functions. Then it calls C runtime initialization function which calls main function of the application code.
+*
+* Below sequence diagram captures the initialization process in the startup code.
+* 
+*
+* \subsection group_system_config_heap_stack_config_cm33 Heap and Stack Configuration
+* By default, the stack size is set to 0x00001000 and the entire remaining ram is used for the heap
+*
+* \subsubsection group_system_config_heap_stack_config_gcc_cm33 ARM GCC
+* - <b>Editing source code files for non-secure image</b>\n
+* The stack and heap sizes are defined in the linker script file: 'cyw20829_ns_flash_cbus.ld'.
+* Change the stack size by modifying the following line:\n
+* \code STACK_SIZE = 0x00001000; \endcode
+* Remaining free RAM is used as heap.
+*
+* \note Correct operation of malloc and related functions depends on the working
+* implementation of the 'sbrk' function. Newlib-nano (default C runtime library
+* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that
+* doesn't check for heap and stack collisions during excessive memory allocations.
+* To ensure the heap always remains within the range defined by __HeapBase and
+* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function:
+* \snippet startup/snippet/main.c snippet_sbrk_cm33
+* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include
+* clib-support library that provides newlib-compatible implementations of
+* 'sbrk', '__malloc_lock' and '__malloc_unlock':
+* <br>
+* https://github.com/Infineon/clib-support.
+*
+* \subsubsection group_system_config_heap_stack_config_arm_cm33 ARM Compiler
+* - <b>Editing source code files for non-secure image</b>\n
+* The stack sizes are defined in the linker script file: 'cyw20829_ns_flash_cbus.sct'.
+* Change the stack by modifying the following lines:\n
+* \code #define STACK_SIZE 0x00001000 \endcode
+* Remaining free RAM is used as heap.
+*
+* \subsubsection group_system_config_heap_stack_config_iar_cm33 IAR
+* - <b>Editing source code files for non-secure image</b>\n
+* The stack and heap sizes are defined in the linker script file: 'cyw20829_ns_flash_cbus.icf'.
+* Change the stack size by modifying the following line:\n
+* \code define symbol STACK_SIZE = 0x00001000; \endcode
+* Remaining free RAM is used as heap.
+*
+* \subsection group_system_config_default_handlers_cm33 Default Interrupt Handlers Definition
+* The default interrupt handler functions are dummy handler in the startup file.\n
+* Below is the default handler for the non-secure interrupts:\n
+* \code interrupt_type void InterruptHandler(void) {
+* while(1);
+* } \endcode
+*
+* \subsection group_system_config_device_vector_table_cm33 Vectors Table Copy from ROM/Flash to RAM
+* This process uses memory sections defined in the linker script. The startup code copies the
+* default vector table contents to the non-secure SRAM region specified by the linker script.
+* APIs are provided in the sysint driver to hook user implemented handler replacing the default
+* handler for the corresponding interrupt.
+*
+* Following tables provide the address of the default and non-secure SRAM interrupt vector
+* table for different supported compilers.
+* \subsubsection group_system_config_device_vector_table_gcc_cm33 ARM GCC
+* The linker script file is 'cyw20829_ns_flash_cbus.ld'.
+* For non-secure world, it uses the following variable.\n
+* Copy interrupt vectors from ROM/flash to RAM: \n
+* From: \code __ns_vector_table \endcode
+* To: \code __ns_vector_table_rw \endcode
+* The vector table address (and the vector table itself) are defined in the
+* ns_start_<device>.c startup file corresponding to non-secure world.
+* The code in these files copies the vector table from ROM/Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_mdk_cm33 ARM Compiler
+* The linker script file is 'cyw20829_ns_flash_cbus.sct'.
+* For non-secure world, it uses the following variable.\n
+* Copy interrupt vectors from ROM/flash to RAM: \n
+* From: \code __ns_vector_table \endcode
+* To: \code __ns_vector_table_rw \endcode
+* The vector table address (and the vector table itself) are defined in the
+* ns_start_<device>.c startup file corresponding to non-secure world.
+* The code in these files copies the vector table from ROM/Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_iar_cm33 IAR
+* The linker script file is 'cyw20829_ns_flash_cbus.icf'.
+* For non-secure world, it uses the following variable.\n
+* Copy interrupt vectors from ROM/flash to RAM: \n
+* From: \code __ns_vector_table \endcode
+* To: \code __ns_vector_table_rw \endcode
+* The vector table address (and the vector table itself) are defined in the
+* ns_start_<device>.c startup file corresponding to non-secure worlds.
+* The code in these files copies the vector table from ROM/Flash to RAM.
+*
+* \section group_system_config_changelog_cm33 Changelog
+* <table class="doxtable">
+* <tr>
+* <th>Version</th>
+* <th>Changes</th>
+* <th>Reason for Change</th>
+* </tr>
+* <tr>
+* <td>1.2</td>
+* <td>Added new internal functions.</td>
+* <td>Added support for DSRAM Setup for CAT1B devices.</td>
+* </tr>
+* <tr>
+* <td>1.1</td>
+* <td>Restructured documentation and internal function behaviour.</td>
+* <td>User experience enhancement.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+*
+* \defgroup group_system_config_macro_cm33 Macros
+* \{
+* \defgroup group_system_config_system_macro_cm33 System Macros
+* \}
+*
+* \}
+*/
+
+
#ifdef __cplusplus
extern "C" {
#endif
-#include "system_cyw20829.h"
+/*******************************************************************************
+* Include files
+*******************************************************************************/
+#include <stdint.h>
+#include <stdbool.h>
+
+#define CY_SYSTEM_CPU_CM33 1UL
+
+/*******************************************************************************
+* Global preprocessor symbols/macros ('define')
+*******************************************************************************/
+
+/**
+* \addtogroup group_system_config_system_macro_cm33
+* \{
+*/
+#if (CY_SYSTEM_CPU_CM33 == 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M33 startup driver identifier */
+ #define CY_STARTUP_M33_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
+#endif /* (CY_SYSTEM_CPU_CM33 == 1UL) */
+/** \} group_system_config_system_macro_cm33 */
+
+/** \cond */
+void SystemInit(void);
+void SystemInit_Warmboot_CAT1B_CM33(void);
+void System_Store_NVIC_Reg(void);
+void System_Restore_NVIC_Reg(void);
+extern void SystemCoreClockUpdate(void);
+
+extern void Cy_SystemInit(void);
+extern void bootstrapInit(void);
+
+extern uint32_t cy_delayFreqHz;
+extern uint32_t cy_delayFreqKhz;
+extern uint8_t cy_delayFreqMhz;
+
+extern uint32_t SystemCoreClock;
+extern uint32_t cy_Hfclk0FreqHz;
+extern uint32_t cy_PeriClkFreqHz;
+extern uint32_t cy_AhbFreqHz;
+extern bool cy_WakeupFromWarmBootStatus;
+
+/** \endcond */
+
#ifdef __cplusplus
}
diff --git a/boot/cypress/platforms/CYW20829.md b/boot/cypress/platforms/CYW20829.md
index c499a8a..a870898 100644
--- a/boot/cypress/platforms/CYW20829.md
+++ b/boot/cypress/platforms/CYW20829.md
@@ -1,10 +1,10 @@
-## CYW20829 platform description
+## CYW20829/CYW89829 platform description
### Prerequisites
#### Cysecuretools
-The CYW20829 chip has a set of security features. A special tool called `cysecuretools` is required to use most of them.
+The CYW20829/CYW89829 devices have a set of security features. A special tool called `cysecuretools` is required to use most of them.
`Cysecuretools` is a Python3 package, which can be installed using the conventional `python pip` packet manager:
@@ -15,22 +15,22 @@
Invocation of cysecuretools is build-in post-build jobs for `MCUBootApp` and `BlinkyApp`, so the user gets ready to use images after build.
### MCUBootApp specifics
-The PSoC CYW20829 can work in two modes - Non-Secure and Secure. In the Non-Secure (NORMAL_NO_SECURE) mode the CYW20829 works as a 'usual' Infineon chip. In the SECURE mode the following functionality becomes available:
+The PSoC CYW20829/CYW89829 can work in two modes - Non-Secure and Secure. In the Non-Secure (NORMAL_NO_SECURE) mode the CYW20829/CYW89829 works as a 'usual' Infineon chip. In the SECURE mode the following functionality becomes available:
- signing of images;
- rollback protection (hardware secure counter).
-The work with the CYW20829 chip begins from the initialization of the project with the following device provisioning in the desired lifecycle - Non-Secure on Secure.
+The work with the CYW20829/CYW89829 chips begin from the initialization of the project with the following device provisioning in the desired lifecycle - Non-Secure on Secure.
### Device and environment initialization
For the cysecuretools environment setup, the MCUboot `boot/cypress` folder is used.
-To create a common CYW20829 configuration, use:
+To create a common configuration, use:
cysecuretools -t cyw20829 init
To configure an OpenOCD package patch (via ModusToolbox™ by default):
- cysecuretools set-ocd --name openocd --path C:/Users/%USERNAME%/ModusToolbox/tools_2.4/openocd
+ cysecuretools set-ocd --name openocd --path C:/Users/%USERNAME%/ModusToolbox/tools_3.2/openocd
This is enough for a NORMAL_NO_SECURE lifecycle. But for SECURE `LCS`, a few more steps are necessary.
@@ -46,7 +46,7 @@
where N is the key number, zero or one.
-### CYW20829 provisioning and reprovisioning
+### CYW20829/CYW89829 provisioning and reprovisioning
For the first provision of the CYW20829 chip, use:
@@ -66,11 +66,11 @@
### Encrypted image support
-CYW20829 does not have internal flash memory, so both primary and secondary images are located in external memory.
+CYW20829/CYW89829 does not have internal flash memory, so both primary and secondary images are located in external memory.
To protect the firmware from reading, place it in external memory in the encrypted form.
-CYW20829 can execute encrypted firmware directly using the onboard hardware interface (SMIF) with special mode XIP (eXecute-In-Place). In this mode, all code is decrypted transparently by the AES algorithm.
+CYW20829/CYW89829 can execute encrypted firmware directly using the onboard hardware interface (SMIF) with special mode XIP (eXecute-In-Place). In this mode, all code is decrypted transparently by the AES algorithm.
MCUboot has its own Encrypted image mode to encrypt the firmware and transfer it with the AES session key included in the HKDF data block.
@@ -108,7 +108,7 @@
### Rollback protection Support
-As mentioned above, to use the rollback protection feature the device must be transferred to the SECURE lifecycle. The CYW20829 platform has a hardware-supported feature - a non-volatile counter (NV-counter). This feature is used by the MCUboot library to implement the rollback protection counter (security counter). NV-counter on CYW20829 is implemented as an Efuse-type region that can only be incremented. This means, that each time a new counter value is updated - a corresponding number of Efuse is burned.
+As mentioned above, to use the rollback protection feature the device must be transferred to the SECURE lifecycle. The CYW20829/CYW89829 platform has a hardware-supported feature - a non-volatile counter (NV-counter). This feature is used by the MCUboot library to implement the rollback protection counter (security counter). NV-counter on CYW20829/CYW89829 is implemented as an Efuse-type region that can only be incremented. This means, that each time a new counter value is updated - a corresponding number of Efuse is burned.
The initial value of the rollback counter is programmed into the chip at the provisioning stage. The provisioning policy for Secure mode contains a corresponding field (file `policy/policy_secure.json`):
@@ -143,7 +143,7 @@
`"value": [2, 3]` filed sets corresponding value for image ids. Here `4` would be assigned to image id `1` and `5` to image id `2`.
-If the `nv_counter` value is encreased in `policy/policy_secure.json` at the provisioning stage, the `nv_counter` value in `policy/policy_reprovisioning_secure.json` must start from the value not less than the value in `policy/policy_secure.json` file.
+If the `nv_counter` value is increased in `policy/policy_secure.json` at the provisioning stage, the `nv_counter` value in `policy/policy_reprovisioning_secure.json` must start from the value not less than the value in `policy/policy_secure.json` file.
More details about provisioning and reprovisioning processes you can find in [README_CYW20829.md](https://github.com/Infineon/cysecuretools/blob/master/docs/README_CYW20829.md#command-provision-device)
When preparing an image for MCUBootApp with the rollback counter support, the `cysecuretools` signs it with `policy/policy_secure.json` in the post-build stage of `make`. The `nv_counter` value remains the same as one in the chip or sets higher. When `cysecuretools` signs an image, it places the `nv-counter` value and the reprovisioning packet in TLVs with tags 0x50 (bit mask representation of the counter) and 0x51 (reprovisioning packet). MCUBootApp then parses these tags and compares the value supplied with the image against the one stored in the Efuse counter.
@@ -170,20 +170,20 @@
To update NV-counter for an appropriate image you have to increase NV-counter in the reprovisioning policy `/policy/policy_reprovisioning_secure.json`, after that re-build the `BlinkyApp` and re-program your device.
-The CYW20829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of Efuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `cysecuretools` under `targets/cyw20829/packets/apps`. The `reprovisioning` application is used for NV-counter updates.
+The CYW20829/CYW89829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of Efuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `cysecuretools` under `targets/cyw20829/packets/apps`. The `reprovisioning` application is used for NV-counter updates.
To enable the rollback counter feaure, one have to use a JSON flash map with the `"service_app"` section. Sample flash maps are located in `boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot`.
The service application is supplied as a precompiled binary executed from RAM by BootROM. User should program either `cyapp_reprovisioning_signed.hex` (located at `./MCUBootApp/out/CYW20829/Debug/cyapp_reprovisioning_signed.hex`) or similar binary `./packets/apps/reprovisioning/cyapp_reprovisioning_signed.bin` (with the `"address"` specified in the `"service_app"` section of JSON flash map). Some other data is required for BootROM to execute the service app - this data is prepared by MCUBootApp.
-When MCUBootApp detects that the rollback counter must be updated on CYW20829, it executes the function, which prepares input data and service application descriptor data and places it in flash at addresses `"params_address"` and `"desc_address"`, respectively (see the `"service_app"` section in JSON flash map). Then, it sets the special flag in the service register, which signalizes BootROM to launch the service application and calls a system reset. BootROM then detects the service app with its data, copies it to the corresponding addresses in RAM, and executes it. Reprovisioning app then updates the `nv-counter` value in Efuse. An automatic reset can (and for convenience should) be initiated after that. To allow this value, `sys_reset_req` is set to `true` (`false` by default).
+When MCUBootApp detects that the rollback counter must be updated on CYW20829/CYW89829, it executes the function, which prepares input data and service application descriptor data and places it in flash at addresses `"params_address"` and `"desc_address"`, respectively (see the `"service_app"` section in JSON flash map). Then, it sets the special flag in the service register, which signalizes BootROM to launch the service application and calls a system reset. BootROM then detects the service app with its data, copies it to the corresponding addresses in RAM, and executes it. Reprovisioning app then updates the `nv-counter` value in Efuse. An automatic reset can (and for convenience should) be initiated after that. To allow this value, `sys_reset_req` is set to `true` (`false` by default).
"sys_reset_req": {
"description": "Resets a device after RAM application finishes execution.",
"value": true
}
-For more details on BootROM service applications, refer to the CYW20829 documentation.
+For more details on BootROM service applications, refer to the CYW20829/CYW89829 documentation.
#### Rollback counter behavior
@@ -261,7 +261,7 @@
Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION` and `OPENOCD` variables:
- export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
+ export OPENOCD=/Applications/ModusToolbox/tools_3.2/openocd
$OPENOCD_PATH/bin/openocd -s $OPENOCD_PATH/scripts -c "set ENABLE_ACQUIRE 0" -f $OPENOCD_PATH/scripts/interface/kitprog3.cfg -c "set SMIF_BANKS { 0 {addr 0x60000000 size 0x4000000 psize 0x1000 esize 0x40000} }" -f $OPENOCD_PATH/scripts/target/cyw20829.cfg -c "init; reset init; cmsis_flash init; flash write_image %PATH_TO_APPLICATION%/BlinkyApp.hex; shutdown"
diff --git a/boot/cypress/platforms/CYW20829.mk b/boot/cypress/platforms/CYW20829.mk
index 93b06d4..54dad0f 100644
--- a/boot/cypress/platforms/CYW20829.mk
+++ b/boot/cypress/platforms/CYW20829.mk
@@ -36,7 +36,11 @@
# MCU device selection, based on target device.
# Default chips are used for supported platforms
# This can be redefined in case of other chip usage
+ifeq ($(PLATFORM), CYW20829)
DEVICE ?= CYW20829B0LKML
+else ifeq ($(PLATFORM), CYW89829)
+DEVICE ?= CYW89829B01MKSBG
+endif
#Led pin default config
LED_PORT_DEFAULT ?= GPIO_PRT0
@@ -51,10 +55,6 @@
# Add device name to defines
DEFINES += $(DEVICE)
-# A0 compatibility workaround
-DEFINES += CY_XIP_REMAP_OFFSET=0x08000000UL
-DEFINES += CY_SRAM0_REMAP_OFFSET=0x04000000UL
-
# Default upgrade method
PLATFORM_DEFAULT_USE_OVERWRITE ?= 0
@@ -146,8 +146,8 @@
post_build: $(OUT_CFG)/$(APP_NAME).elf
ifeq ($(POST_BUILD_ENABLE), 1)
$(info [TOC2_Generate] - Execute toc2 generator script for $(APP_NAME))
- @echo $(SHELL) $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM_SERVICE_APP_DESC_OFFSET)
- $(shell $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM_SERVICE_APP_DESC_OFFSET))
+ @echo $(SHELL) $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM) $(PLATFORM_SERVICE_APP_DESC_OFFSET)
+ $(shell $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM) $(PLATFORM_SERVICE_APP_DESC_OFFSET))
# Convert binary to hex and rename
$(shell mv -f $(OUT_CFG)/$(APP_NAME).final.bin $(OUT_CFG)/$(APP_NAME).bin || rm -f $(OUT_CFG)/$(APP_NAME).bin)
diff --git a/boot/cypress/platforms/PSOC6.md b/boot/cypress/platforms/PSOC6.md
index 64814f2..88d3f24 100644
--- a/boot/cypress/platforms/PSOC6.md
+++ b/boot/cypress/platforms/PSOC6.md
@@ -65,8 +65,6 @@
```
to remind about the necessary padding.
-**Attention**: shared slot feature support two images only.
-
### Encrypted Image Support
To protect the user's image from unwanted read, Upgrade Image Encryption can be applied. The ECDH/HKDF with the EC256 scheme is used in a given solution as well as mbedTLS as a crypto provider.
@@ -93,7 +91,7 @@
Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION.hex` and `OPENOCD` paths:
- export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
+ export OPENOCD=/Applications/ModusToolbox/tools_3.2/openocd
${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
-f ${OPENOCD}/scripts/interface/kitprog3.cfg \
diff --git a/boot/cypress/platforms/PSOC6.mk b/boot/cypress/platforms/PSOC6.mk
index c21b249..9119a7f 100644
--- a/boot/cypress/platforms/PSOC6.mk
+++ b/boot/cypress/platforms/PSOC6.mk
@@ -151,10 +151,12 @@
PLATFORM_APP_SOURCES += $(PRJ_DIR)/platforms/utils/$(FAMILY)/psoc6_02_cm0p_sleep.c
endif
-ifeq ($(USE_EXTERNAL_FLASH), 1)
-PLATFORM_SOURCES_FLASH += cy_serial_flash_prog.c
-PLATFORM_SOURCES_FLASH += $(PRJ_DIR)/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.c
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/memory/PSOC6/smif_cfg_dbg
+ifeq ($(USE_SMIF_CONFIG), 1)
+ ifeq ($(USE_EXTERNAL_FLASH), 1)
+ PLATFORM_SOURCES_FLASH += cy_serial_flash_prog.c
+ PLATFORM_SOURCES_FLASH += $(PRJ_DIR)/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.c
+ PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/memory/PSOC6/smif_cfg_dbg
+ endif
endif
# Post build job to execute for platform
diff --git a/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h b/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h
index e4497fd..e52e975 100644
--- a/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h
+++ b/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h
@@ -20,18 +20,27 @@
#include <string.h>
+struct mbedtls_sha256_context;
+
#define mbedtls_sha256_starts_ret mbedtls_sha256_starts
#define mbedtls_sha256_finish_ret mbedtls_sha256_finish
-static inline int mbedtls_sha256_update_ret(struct mbedtls_sha256_context *ctx,
+#define MBEDTLS_ERR_SHA256_BAD_INPUT_DATA -0x0074 /**< SHA-256 input data was malformed. */
+
+int mbedtls_sha256_update( struct mbedtls_sha256_context *ctx,
+ const unsigned char *input,
+ size_t ilen );
+
+static inline int mbedtls_sha256_update_ret(void *ctx,
+
const unsigned char *input,
size_t ilen)
{
/* Cryptolite accelerator does not work on CBUS! */
- if (input >= (const unsigned char *)CY_XIP_REMAP_OFFSET &&
- input < (const unsigned char *)(CY_XIP_REMAP_OFFSET + CY_XIP_SIZE)) {
+ if (input >= (const unsigned char *)CY_XIP_CBUS_BASE &&
+ input < (const unsigned char *)(CY_XIP_CBUS_BASE + CY_XIP_SIZE)) {
- if (input + ilen > (const unsigned char *)(CY_XIP_REMAP_OFFSET + CY_XIP_SIZE)) {
+ if (input + ilen > (const unsigned char *)(CY_XIP_CBUS_BASE + CY_XIP_SIZE)) {
return -MBEDTLS_ERR_SHA256_BAD_INPUT_DATA;
}
else {
diff --git a/boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c b/boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c
index 89bdd89..275dfd6 100644
--- a/boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c
+++ b/boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c
@@ -18,6 +18,7 @@
#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
#include "set_img_ok.h"
+#include "flash_qspi.h"
static uint8_t row_buff[FLASH_ROW_BUF_SZ];
diff --git a/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c b/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c
index 83c0581..c8901c0 100644
--- a/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c
+++ b/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c
@@ -17,7 +17,13 @@
#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
+#include "string.h"
#include "set_img_ok.h"
+#include "cy_flash.h"
+
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH)
+#include "flash_qspi.h"
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) */
static uint8_t row_buff[FLASH_ROW_BUF_SZ];
diff --git a/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c b/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c
index ee78156..b95cf32 100644
--- a/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c
+++ b/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c
@@ -18,7 +18,8 @@
#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
#include "set_img_ok.h"
-
+#include "cy_flash.h"
+#include <string.h>
static uint8_t row_buff[FLASH_ROW_BUF_SZ];
#ifndef USE_XIP
diff --git a/boot/cypress/platforms/img_confirm/set_img_ok.h b/boot/cypress/platforms/img_confirm/set_img_ok.h
index ee9f424..08ecb04 100644
--- a/boot/cypress/platforms/img_confirm/set_img_ok.h
+++ b/boot/cypress/platforms/img_confirm/set_img_ok.h
@@ -18,11 +18,7 @@
#if !defined(SET_IMG_OK_H)
#define SET_IMG_OK_H
-#include "cy_flash.h"
-#if defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829)
-#include "flash_qspi.h"
-#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829) */
-#include <string.h>
+#include <stdint.h>
#define FLASH_ROW_BUF_SZ MEMORY_ALIGN
#define IMG_TRAILER_SZ MEMORY_ALIGN
@@ -31,6 +27,8 @@
#define USER_SWAP_IMAGE_OK (1)
#define IMG_OK_ADDR (PRIMARY_IMG_START + USER_APP_SIZE - USER_SWAP_IMAGE_OK_OFFS)
+
+#define IMG_OK_SET_UNDEFINED 0x55
#define IMG_OK_SET_FAILED -1
#define IMG_OK_ALREADY_SET 1
#define IMG_OK_SET_SUCCESS 0
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_overwrite_multi2.json b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_overwrite_multi2.json
new file mode 100644
index 0000000..8366917
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_overwrite_multi2.json
@@ -0,0 +1,57 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60030000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60050000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_overwrite_single.json b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_overwrite_single.json
new file mode 100644
index 0000000..8c98f08
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_overwrite_single.json
@@ -0,0 +1,39 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_swap_multi2.json b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_swap_multi2.json
new file mode 100644
index 0000000..8031750
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_swap_multi2.json
@@ -0,0 +1,73 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x6007E000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x60060000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x14000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60030000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60050000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_swap_shared.json b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_swap_shared.json
new file mode 100644
index 0000000..40593c3
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_swap_shared.json
@@ -0,0 +1,81 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x6007E000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x6005C000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x1C000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "shared_slot": {
+ "description": "Using shared secondary slot",
+ "value": true
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60030000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "shared_slot": {
+ "description": "Using shared secondary slot",
+ "value": true
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60041000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_swap_single.json b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_swap_single.json
new file mode 100644
index 0000000..3fb2ac2
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/cyw89829_xip_swap_single.json
@@ -0,0 +1,55 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x6007E000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x60060000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0xC000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_overwrite_multi2.json b/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_overwrite_multi2.json
new file mode 100644
index 0000000..b8f0835
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_overwrite_multi2.json
@@ -0,0 +1,83 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "service_app": {
+ "address": {
+ "description": "Address of the service application",
+ "value": "0x60070000"
+ },
+ "size": {
+ "description": "Size of the service application",
+ "value": "0x8000"
+ },
+ "params_address": {
+ "description": "Address of the service application input parameters",
+ "value": "0x60078000"
+ },
+ "params_size": {
+ "description": "Size of the service application input parameters",
+ "value": "0x400"
+ },
+ "desc_address": {
+ "description": "Address of the service application descriptor",
+ "value": "0x60078400"
+ },
+ "desc_size": {
+ "description": "Size of the service application descriptor",
+ "value": "0x20"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60030000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60050000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_overwrite_single.json b/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_overwrite_single.json
new file mode 100644
index 0000000..d46066d
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_overwrite_single.json
@@ -0,0 +1,65 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "service_app": {
+ "address": {
+ "description": "Address of the service application",
+ "value": "0x60070000"
+ },
+ "size": {
+ "description": "Size of the service application",
+ "value": "0x8000"
+ },
+ "params_address": {
+ "description": "Address of the service application input parameters",
+ "value": "0x60078000"
+ },
+ "params_size": {
+ "description": "Size of the service application input parameters",
+ "value": "0x400"
+ },
+ "desc_address": {
+ "description": "Address of the service application descriptor",
+ "value": "0x60078400"
+ },
+ "desc_size": {
+ "description": "Size of the service application descriptor",
+ "value": "0x20"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_swap_multi2.json b/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_swap_multi2.json
new file mode 100644
index 0000000..242f7cc
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_swap_multi2.json
@@ -0,0 +1,99 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x6007E000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x6005C000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x14000"
+ }
+ },
+ "service_app": {
+ "address": {
+ "description": "Address of the service application",
+ "value": "0x60070000"
+ },
+ "size": {
+ "description": "Size of the service application",
+ "value": "0x8000"
+ },
+ "params_address": {
+ "description": "Address of the service application input parameters",
+ "value": "0x60078000"
+ },
+ "params_size": {
+ "description": "Size of the service application input parameters",
+ "value": "0x400"
+ },
+ "desc_address": {
+ "description": "Address of the service application descriptor",
+ "value": "0x60078400"
+ },
+ "desc_size": {
+ "description": "Size of the service application descriptor",
+ "value": "0x20"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0xF000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x6003E000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0xF000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x6002F000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0xF000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x6004D000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0xF000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_swap_single.json b/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_swap_single.json
new file mode 100644
index 0000000..addeee1
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW89829/flashmap/hw_rollback_prot/cyw89829_xip_swap_single.json
@@ -0,0 +1,81 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x6007E000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x60060000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0xC000"
+ }
+ },
+ "service_app": {
+ "address": {
+ "description": "Address of the service application",
+ "value": "0x60070000"
+ },
+ "size": {
+ "description": "Size of the service application",
+ "value": "0x8000"
+ },
+ "params_address": {
+ "description": "Address of the service application input parameters",
+ "value": "0x60078000"
+ },
+ "params_size": {
+ "description": "Size of the service application input parameters",
+ "value": "0x400"
+ },
+ "desc_address": {
+ "description": "Address of the service application descriptor",
+ "value": "0x60078400"
+ },
+ "desc_size": {
+ "description": "Size of the service application descriptor",
+ "value": "0x20"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c
index 0f33265..222ad66 100644
--- a/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c
+++ b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c
@@ -362,9 +362,9 @@
(void)Cy_GPIO_Pin_Init(SCKPort, SCKPin, &QSPI_SCK_config);
Cy_GPIO_SetHSIOM(SCKPort, SCKPin, SCKMuxPort);
- (void)Cy_SysClk_ClkHfSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SYSCLK_CLKHF_IN_CLKPATH0);
- (void)Cy_SysClk_ClkHfSetDivider(CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SMIF_SYSCLK_HFCLK_DIVIDER);
- (void)Cy_SysClk_ClkHfEnable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
+ (void)Cy_SysClk_ClkHfSetSource((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+ (void)Cy_SysClk_ClkHfSetDivider((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SMIF_SYSCLK_HFCLK_DIVIDER);
+ (void)Cy_SysClk_ClkHfEnable((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2);
/*
* Setup the interrupt for the SMIF block. For the CM0 there
@@ -505,7 +505,7 @@
Cy_SMIF_Disable(QSPIPort);
- (void)Cy_SysClk_ClkHfDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
+ (void)Cy_SysClk_ClkHfDisable((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2);
#ifdef BOOT_CM0P
NVIC_DisableIRQ(smifIntConfig.intrSrc);
diff --git a/boot/cypress/platforms/memory/PSOC6/internal_memory.c b/boot/cypress/platforms/memory/PSOC6/internal_memory.c
index a207a3a..28ffe4b 100644
--- a/boot/cypress/platforms/memory/PSOC6/internal_memory.c
+++ b/boot/cypress/platforms/memory/PSOC6/internal_memory.c
@@ -126,7 +126,7 @@
rc = 0;
}
- row_addr += (uint32_t) CY_FLASH_SIZEOF_ROW;
+ row_addr += CY_FLASH_SIZEOF_ROW;
row_ptr = row_ptr + CY_FLASH_SIZEOF_ROW / 4U;
}
@@ -164,7 +164,7 @@
while (row_number != 0u) {
row_number--;
- row_addr = row_start_addr + row_number * (uint32_t) CY_FLASH_SIZEOF_ROW;
+ row_addr = row_start_addr + (row_number * CY_FLASH_SIZEOF_ROW);
if (Cy_Flash_EraseRow(row_addr) != CY_FLASH_DRV_SUCCESS) {
rc = BOOT_EFLASH;
break;
diff --git a/boot/cypress/platforms/memory/XMC7000/flashmap/platform.json b/boot/cypress/platforms/memory/XMC7000/flashmap/platform.json
index f768d1c..9e59374 100644
--- a/boot/cypress/platforms/memory/XMC7000/flashmap/platform.json
+++ b/boot/cypress/platforms/memory/XMC7000/flashmap/platform.json
@@ -6,7 +6,7 @@
"size" : "0x7F0000",
"erase_size" : "0x8000",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_CODE_LARGE"
+ "mem_type" : "INTERNAL_FLASH_CODE_LARGE"
},
{
@@ -14,7 +14,7 @@
"size" : "0x40000",
"erase_size" : "0x2000",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_CODE_SMALL"
+ "mem_type" : "INTERNAL_FLASH_CODE_SMALL"
},
{
@@ -22,7 +22,7 @@
"size" : "0x30000",
"erase_size" : "0x800",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_WORK_LARGE"
+ "mem_type" : "INTERNAL_FLASH_WORK_LARGE"
},
{
@@ -30,7 +30,7 @@
"size" : "0x30000",
"erase_size" : "0x80",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_WORK_SMALL"
+ "mem_type" : "INTERNAL_FLASH_WORK_SMALL"
}
],
diff --git a/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7100_platform.json b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7100_platform.json
index 047bd37..4996e35 100644
--- a/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7100_platform.json
+++ b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7100_platform.json
@@ -6,7 +6,7 @@
"size" : "0x3F0000",
"erase_size" : "0x8000",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_CODE_LARGE"
+ "mem_type" : "INTERNAL_FLASH_CODE_LARGE"
},
{
@@ -14,7 +14,7 @@
"size" : "0x20000",
"erase_size" : "0x2000",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_CODE_SMALL"
+ "mem_type" : "INTERNAL_FLASH_CODE_SMALL"
},
{
@@ -22,7 +22,7 @@
"size" : "0x30000",
"erase_size" : "0x800",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_WORK_LARGE"
+ "mem_type" : "INTERNAL_FLASH_WORK_LARGE"
},
{
@@ -30,7 +30,7 @@
"size" : "0x10000",
"erase_size" : "0x80",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_WORK_SMALL"
+ "mem_type" : "INTERNAL_FLASH_WORK_SMALL"
}
],
diff --git a/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7200_platform.json b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7200_platform.json
index 6fbbc0e..c8eeb29 100644
--- a/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7200_platform.json
+++ b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7200_platform.json
@@ -6,7 +6,7 @@
"size" : "0x7F0000",
"erase_size" : "0x8000",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_CODE_LARGE"
+ "mem_type" : "INTERNAL_FLASH_CODE_LARGE"
},
{
@@ -14,7 +14,7 @@
"size" : "0x40000",
"erase_size" : "0x2000",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_CODE_SMALL"
+ "mem_type" : "INTERNAL_FLASH_CODE_SMALL"
},
{
@@ -22,7 +22,7 @@
"size" : "0x30000",
"erase_size" : "0x800",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_WORK_LARGE"
+ "mem_type" : "INTERNAL_FLASH_WORK_LARGE"
},
{
@@ -30,7 +30,7 @@
"size" : "0x10000",
"erase_size" : "0x80",
"erase_value" : "0xFF",
- "type" : "INTERNAL_FLASH_WORK_SMALL"
+ "mem_type" : "INTERNAL_FLASH_WORK_SMALL"
}
],
diff --git a/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c b/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c
index f5fa320..4ba5fea 100644
--- a/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c
+++ b/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c
@@ -1,28 +1,23 @@
-/*
- * Copyright (c) 2018 Nordic Semiconductor ASA
- * Copyright (c) 2020 Cypress Semiconductor Corporation
- * Copyright (c) 2022 Infineon Technologies AG
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
+/********************************************************************************
+* \copyright
+* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
#include <stdint.h>
#include "bootutil/bootutil.h"
diff --git a/boot/cypress/platforms/memory/cy_flash_map.c b/boot/cypress/platforms/memory/cy_flash_map.c
index bd57ec0..451cdd2 100644
--- a/boot/cypress/platforms/memory/cy_flash_map.c
+++ b/boot/cypress/platforms/memory/cy_flash_map.c
@@ -261,7 +261,7 @@
*/
uint8_t flash_area_erased_val(const struct flash_area *fa)
{
- if ((fa != NULL) && (flash_area_get_api(fa->fa_device_id))) {
+ if ((fa != NULL) && (flash_area_get_api(fa->fa_device_id) != NULL)) {
return flash_area_get_api(fa->fa_device_id)->get_erase_val(fa->fa_device_id);
} else {
return 0u;
diff --git a/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c b/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c
index 3d52bd0..63d07e3 100644
--- a/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c
+++ b/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c
@@ -29,10 +29,10 @@
#ifdef CYW20829
-#define CY_GET_XIP_REMAP_ADDR(addr) ((addr) - CY_XIP_BASE + CY_XIP_REMAP_OFFSET)
+#define CY_GET_XIP_REMAP_ADDR(addr) ((addr) - CY_XIP_BASE + CY_XIP_CBUS_BASE)
#define CY_GET_XIP_REMAP_ADDR_FIH(addr) fih_uint_encode(CY_GET_XIP_REMAP_ADDR(addr))
-#define CY_GET_SRAM0_REMAP_ADDR(addr) ((addr) - CY_SRAM0_BASE + CY_SRAM0_REMAP_OFFSET)
+#define CY_GET_SRAM0_REMAP_ADDR(addr) ((addr) - CY_SRAM0_BASE + CY_SRAM0_CBUS_BASE)
/* TOC2 */
#define TOC2_SIZE 16u
@@ -233,7 +233,7 @@
/* Wipe MCUBoot's RAM to prevent information leakage (Pt. 1) */
" mov r0, #0\n"
" ldr r1, =(hsiniFppAnuR_92802wyc-" /* Should be remapped from */
- QUOTE(CY_SRAM0_REMAP_OFFSET)"+" /* C-bus to S-AHB! */
+ QUOTE(CY_SRAM0_CBUS_BASE)"+" /* C-bus to S-AHB! */
QUOTE(CY_SRAM0_BASE)")\n" /* Avoid self-destruction */
" ldr r2, =__HeapLimit\n"
"1: str r0, [r1]\n"
@@ -271,7 +271,7 @@
" mov r0, #0\n"
" ldr r1, =__StackLimit\n"
" ldr r2, =(5f-" /* Should be remapped from C-bus to S-AHB! */
- QUOTE(CY_SRAM0_REMAP_OFFSET)"+"
+ QUOTE(CY_SRAM0_CBUS_BASE)"+"
QUOTE(CY_SRAM0_BASE)")\n" /* Final self-destruction */
" b 5f\n" /* Skip the constant pool */
/* Put the constant pool here (to avoid premature self-destruction) */
@@ -346,7 +346,7 @@
/* Validate L1 Application Descriptor in external memory */
if (!is_aligned((uintptr_t)fih_uint_decode(l1_app_descr_addr), 4u) ||
!fits_into((uintptr_t)fih_uint_decode(l1_app_descr_addr), L1_APP_DESCR_SIZE,
- (uintptr_t)CY_XIP_REMAP_OFFSET, CY_XIP_SIZE) ||
+ (uintptr_t)CY_XIP_CBUS_BASE, CY_XIP_SIZE) ||
fih_ptr_word(l1_app_descr_addr, L1_APP_DESCR_SIZE_IDX) != L1_APP_DESCR_SIZE) {
FIH_PANIC;
@@ -374,10 +374,9 @@
/* Validate bootstrap destination in SRAM (starts with the NS Vector Table) */
if (bootstrap_size < NS_VECTOR_TABLE_SIZE ||
- !is_aligned((uintptr_t)bootstrap_dst_addr, NS_VECTOR_TABLE_ALIGNMENT) ||
- !fits_into((uintptr_t)bootstrap_dst_addr, bootstrap_size,
- (uintptr_t)BOOTSTRAP_SRAM0_ADDR, BOOTSTRAP_SRAM0_SIZE)) {
-
+ !is_aligned((uintptr_t)bootstrap_dst_addr, NS_VECTOR_TABLE_ALIGNMENT)
+ )
+ {
FIH_PANIC;
}
@@ -387,7 +386,7 @@
/* Validate bootstrap source image in external memory */
if (!is_aligned((uintptr_t)fih_uint_decode(ns_vect_tbl_addr), 4u) ||
!fits_into((uintptr_t)fih_uint_decode(ns_vect_tbl_addr), bootstrap_size,
- (uintptr_t)CY_XIP_REMAP_OFFSET, CY_XIP_SIZE)) {
+ (uintptr_t)CY_XIP_CBUS_BASE, CY_XIP_SIZE)) {
FIH_PANIC;
}
@@ -405,9 +404,9 @@
/* Extract app's Reset Handler from the image of NS Vector Table and validate it */
reset_handler = fih_ptr_word(ns_vect_tbl_addr, L1_APP_RESET_HANDLER_IDX);
- if ((reset_handler & 1u) != 1u /* i.e., thumb function */ ||
- !fits_into((uintptr_t)(reset_handler & ~1u), 2u, /* should lay in the remapped SRAM */
- (uintptr_t)CY_GET_SRAM0_REMAP_ADDR(bootstrap_dst_addr), bootstrap_size)) {
+ if ((reset_handler & 1u) != 1u /* i.e., thumb function */
+ )
+ {
FIH_PANIC;
}
diff --git a/boot/cypress/run_toc2_generator.sh b/boot/cypress/run_toc2_generator.sh
index 4b47cba..c8f65f3 100755
--- a/boot/cypress/run_toc2_generator.sh
+++ b/boot/cypress/run_toc2_generator.sh
@@ -18,7 +18,8 @@
# 8. path to policy
# 9. default application slot size
# 10. enable encryption
-# 11. service application descriptor address
+# 11. platform (CYW20829 or CYW89829)
+# 12. service application descriptor address
# Combined image configuration
LCS=$1
@@ -86,7 +87,9 @@
ENC_OPTION=""
fi
-SERVICE_APP_DESCR_ADDR=${11}
+TARGET_PLATFORM=${11}
+
+SERVICE_APP_DESCR_ADDR=${12}
: ${SERVICE_APP_DESCR_ADDR:=0x0}
######################## Validate Input Args #################################
@@ -338,7 +341,7 @@
fi
# Sign l1 user app L1_USER_APP_BIN_SIGN
- cysecuretools -q -t cyw20829 -p $POLICY_PATH sign-image --image-format bootrom_next_app -i $L1_USER_APP_BIN -k 0 -o $L1_USER_APP_BIN_SIGN --slot-size $SLOT_SIZE --app-addr 0x08000030 $ENC_OPTION
+ cysecuretools -q -t $TARGET_PLATFORM -p $POLICY_PATH sign-image --image-format bootrom_next_app -i $L1_USER_APP_BIN -k 0 -o $L1_USER_APP_BIN_SIGN --slot-size $SLOT_SIZE --app-addr 0x08000030 $ENC_OPTION
if [ ! -f "$L1_USER_APP_BIN_SIGN" ]; then
echo "Error: $L1_USER_APP_BIN_SIGN has not been created." > /dev/tty
diff --git a/boot/cypress/scripts/feature.py b/boot/cypress/scripts/feature.py
index 4bc428c..01dbb1e 100644
--- a/boot/cypress/scripts/feature.py
+++ b/boot/cypress/scripts/feature.py
@@ -33,7 +33,7 @@
except FileNotFoundError:
print(f'\nERROR: Cannot find {file_path}')
- sys.exit(-1)
+ sys.exit(1)
return data_json
@@ -66,19 +66,24 @@
if f_security_setup:
if p_security_setup is None:
- raise AttributeError("This platform doesn't have any 'secure_setup' features")
+ print("\nThis platform doesn't have any 'secure_setup' features")
+ sys.exit(1)
if f_security_setup.get('hw_rollback_prot'):
if p_security_setup.get('hw_rollback_prot') is None:
- raise AttributeError("This platform doesn't have HW anti roll-back counter")
+ print("\nThis platform doesn't have HW anti roll-back counter")
+ sys.exit(1)
if f_security_setup.get('hw_crypto_acceleration'):
if p_security_setup.get('hw_crypto_acceleration') is None:
- raise AttributeError("The platform doesn't support HW crypto acceleration")
+ print("\nThe platform doesn't support HW crypto acceleration")
+ sys.exit(1)
if f_security_setup.get('validate_upgrade').get('value') is False:
- raise AttributeError("Deactivation of image validation during the upgrade \
- process isn't implemented yet")
+ if f_security_setup.get('validate_boot').get('value'):
+ print("\nERROR: Boot slot validation cannot be enabled if upgrade "\
+ "slot validation is disabled")
+ sys.exit(1)
class FeatureProcessor:
@@ -88,10 +93,11 @@
"""
settings_dict = {
- 'validate_boot' : 'MCUBOOT_SKIP_IMAGE_VALIDATION',
+ 'validate_boot' : 'MCUBOOT_SKIP_BOOT_VALIDATION',
'validate_upgrade' : 'MCUBOOT_SKIP_UPGRADE_VALIDATION',
'dependency_check' : 'MCUBOOT_DEPENDENCY_CHECK',
'serial_logging' : 'MCUBOOT_LOG_LEVEL',
+ 'watch_dog_timer' : 'USE_WDT',
'hw_rollback_prot' : 'USE_HW_ROLLBACK_PROT',
'hw_crypto_acceleration' : "USE_CRYPTO_HW",
'sw_downgrade_prev' : 'USE_SW_DOWNGRADE_PREV',
diff --git a/boot/cypress/scripts/memorymap.py b/boot/cypress/scripts/memorymap.py
index 5511c9a..d0799d6 100644
--- a/boot/cypress/scripts/memorymap.py
+++ b/boot/cypress/scripts/memorymap.py
@@ -8,6 +8,8 @@
from enum import Enum
import os.path
+MAX_IMAGE_NUMBERS = 16
+
class Error(Enum):
''' Application error codes '''
ARG = 1
@@ -77,9 +79,20 @@
'appCore': 'Cortex-M4'
}
+common_CYW20829 = {
+ 'flashSize': 0, # n/a
+ 'smifAddr': 0x60000000,
+ 'smifSize': 0x8000000, # i.e., window size
+ 'VTAlign': 0x200, # Vector Table alignment
+ 'allCores': cm33Core,
+ 'bootCore': 'Cortex-M33',
+ 'appCore': 'Cortex-M33',
+ 'bitsPerCnt': False
+}
+
common_XMC7000 = {
'flashAddr': 0x10000000,
- 'eraseSize': 0x8000, # 512 bytes
+ 'eraseSize': 0x8000, # 32k
'smifAddr': 0x18000000,
'smifSize': 0x8000000, # i.e., window size
'VTAlign': 0x400, # Vector Table alignment
@@ -88,18 +101,6 @@
'appCore': 'Cortex-M7'
}
-common_PSE84 = {
- 'flashAddr': 0x32000000,
- 'flashSize': 0x40000,
- 'eraseSize': 0x20, # 32 bytes
- 'smifAddr': 0x60000000, #secure address
- 'smifSize': 0x4000000, # i.e., window size
- 'VTAlign': 0x400, # Vector Table alignment
- 'allCores': cm33Core,
- 'bootCore': 'Cortex-M33',
- 'appCore': 'Cortex-M33'
-}
-
platDict = {
'PSOC_061_2M': {
'flashSize': 0x200000, # 2 MBytes
@@ -143,22 +144,11 @@
},
'CYW20829': {
- 'flashSize': 0, # n/a
- 'smifAddr': 0x60000000,
- 'smifSize': 0x8000000, # i.e., window size
- 'VTAlign': 0x200, # Vector Table alignment
- 'allCores': cm33Core,
- 'bootCore': 'Cortex-M33',
- 'appCore': 'Cortex-M33',
- 'bitsPerCnt': False
+ **common_CYW20829
},
- 'PSE84_L4': {
- **common_PSE84
- },
-
- 'PSE84_L2': {
- **common_PSE84
+ 'CYW89829': {
+ **common_CYW20829
}
}
@@ -632,7 +622,6 @@
if not over: # images in shared slot should overlap
print(title, 'is not shared with', area['title'],
file=sys.stderr)
- sys.exit(Error.CONFIG_MISMATCH)
elif over:
print(title, 'overlaps with', area['title'],
file=sys.stderr)
@@ -646,7 +635,7 @@
'fa_size': fa_size})
return slot_sectors
- def generate_c_source(self, params):
+ def generate_c_source(self, params, boot_and_upgrade):
'''
Generate C source
Parameters:
@@ -686,7 +675,24 @@
'struct flash_area *boot_area_descs[] = {\n')
for area_index in range(area_count):
out_f.write(f' &{c_array}[{area_index}U],\n')
- out_f.write(' NULL\n};\n')
+ out_f.write(' NULL\n};\n')
+
+ image_boot_mode = None
+
+ if params.image_boot_config:
+ image_boot_mode = process_boot_type(boot_and_upgrade)
+
+ if image_boot_mode:
+ out_f.write('\nimage_boot_config_t image_boot_config[BOOT_IMAGE_NUMBER] = {\n')
+ for mode in image_boot_mode:
+ out_f.writelines('\n'.join([
+ '\t{\n'
+ f"\t\t.mode = {mode['mode']},",
+ f"\t\t.address = {mode['address']},",
+ f"\t\t.size = {mode['size']},",
+ '\t},\n']))
+ out_f.write('};\n')
+
out_f.close()
except (FileNotFoundError, OSError):
@@ -709,11 +715,11 @@
try:
with open(params.fa_file, "w", encoding='UTF-8') as fa_f:
- fa_f.write("#ifndef MEMORYMAP_H\n")
- fa_f.write("#define MEMORYMAP_H\n\n")
+ fa_f.write("#pragma once\n")
fa_f.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
' ALL CHANGES WILL BE LOST! */\n')
fa_f.write(f'#include "flash_map_backend.h"\n\n')
+ fa_f.write('#include "bootutil/bootutil.h"\n')
fa_f.write(f'extern struct flash_area {c_array}[];\n')
fa_f.write(f'extern struct flash_area *boot_area_descs[];\n')
@@ -749,15 +755,29 @@
fa_f.write(f"#define FLASH_AREA_IMG_{img}_PRIMARY ( {img_id_primary}u)\n")
fa_f.write(f"#define FLASH_AREA_IMG_{img}_SECONDARY ( {img_id_secondary}u)\n\n")
-
+
if self.plat.get('bitsPerCnt'):
- fa_f.close()
-
list_counters = process_policy_20829(params.policy)
if list_counters is not None:
- form_max_counter_array(list_counters, params.fa_file)
- else:
- fa_f.write("#endif /* MEMORYMAP_H */")
+ form_max_counter_array(list_counters, fa_f)
+
+ fa_f.writelines('\n'.join([
+ '',
+ 'typedef enum',
+ '{',
+ '\tIMAGE_BOOT_MODE_FLASH = 0U,',
+ '\tIMAGE_BOOT_MODE_RAM = 1U,',
+ '} image_boot_mode_t;',
+ '',
+ 'typedef struct image_boot_config_s {',
+ '\timage_boot_mode_t mode;',
+ '\tuint32_t address;',
+ '\tuint32_t size;',
+ '} image_boot_config_t;',
+ '',
+ 'extern image_boot_config_t image_boot_config[BOOT_IMAGE_NUMBER];'
+ ]))
+
fa_f.close()
except (FileNotFoundError, OSError):
@@ -906,67 +926,28 @@
application = boot_and_upgrade.get(app_ident)
if application:
- ram = application.get('ram', application.get('ram_boot'))
+ mem = application.get('ram_boot')
- if ram:
+ if mem:
image_boot_mode.append(
{
- 'mode': 'IMAGE_BOOT_MODE_FLASH' if application.get('ram') else 'IMAGE_BOOT_MODE_RAM',
- 'address': ram.get('address', {}).get('value', 0),
- 'size': ram.get('size', {}).get('value', 0),
+ 'mode': 'IMAGE_BOOT_MODE_RAM',
+ 'address': mem.get('address', {}).get('value', 0),
+ 'size': mem.get('size', {}).get('value', 0),
+ }
+ )
+ else :
+ mem = application.get('flash')
+ image_boot_mode.append(
+ {
+ 'mode': 'IMAGE_BOOT_MODE_FLASH',
+ 'address': mem.get('address', {}).get('value', 0),
+ 'size': mem.get('size', {}).get('value', 0),
}
)
return image_boot_mode
-def generate_boot_type(image_boot_mode):
- c_file = "image_boot_config.c"
- h_file = "image_boot_config.h"
- try:
- with open(c_file, "w", encoding='UTF-8') as out_f:
- out_f.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
- ' ALL CHANGES WILL BE LOST! */\n')
-
- out_f.write(f'#include "{h_file}"\n')
- out_f.write('\nimage_boot_config_t image_boot_config[BOOT_IMAGE_NUMBER] = {\n')
- for mode in image_boot_mode:
- out_f.writelines('\n'.join([
- '\t{\n'
- f"\t\t.mode = {mode['mode']},",
- f"\t\t.address = {mode['address']},",
- f"\t\t.size = {mode['size']},",
- '\t},\n']))
- out_f.write('};\n')
-
- with open(h_file, "w", encoding='UTF-8') as out_f:
- out_f.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
- ' ALL CHANGES WILL BE LOST! */\n')
- out_f.write('#ifndef IMAGE_BOOT_CONFIG_H\n')
- out_f.write('#define IMAGE_BOOT_CONFIG_H\n')
- out_f.write('#include "bootutil/bootutil.h"\n')
- out_f.writelines('\n'.join([
- ' ',
- 'typedef enum',
- '{',
- '\tIMAGE_BOOT_MODE_FLASH = 0U,',
- '\tIMAGE_BOOT_MODE_RAM = 1U,',
- '} image_boot_mode_t;',
- '',
- 'typedef struct image_boot_config_s {',
- '\timage_boot_mode_t mode;',
- '\tuint32_t address;',
- '\tuint32_t size;',
- '} image_boot_config_t;',
- '',
- 'extern image_boot_config_t image_boot_config[BOOT_IMAGE_NUMBER];'
- ]))
- out_f.write('\n#endif /* IMAGE_BOOT_CONFIG_H */\n')
-
- except (FileNotFoundError, OSError):
- print('Cannot create', out_f, file=sys.stderr)
- sys.exit(Error.IO)
-
-
def process_images(area_list, boot_and_upgrade):
"""Process images"""
app_count = 0
@@ -978,7 +959,7 @@
apps_ram_map = [None, ]
for stage in range(2):
- for app_index in range(1, 5):
+ for app_index in range(1, MAX_IMAGE_NUMBERS):
app_flash_map = {}
app_ram_map = {}
@@ -1152,10 +1133,8 @@
return list_counters
-def form_max_counter_array(in_list, out_file):
- '''Write bit_per_count array to output file
- There is expected, that "out_file" already exists'''
-
+def form_max_counter_array(in_list, fa_f):
+ '''Write bit_per_count array to output file '''
#ifdef here is needed to fix Rule 12.2 MISRA violation
out_array_str = "\n#ifdef NEED_MAX_COUNTERS\nstatic const uint8_t bits_per_cnt[] = {"
@@ -1166,13 +1145,7 @@
out_array_str += ", "
out_array_str += "};\n#endif\n"
- try:
- with open(out_file, "a", encoding='UTF-8') as out_f:
- out_f.write(out_array_str)
- out_f.write("\n#endif /* MEMORYMAP_H */")
- except (FileNotFoundError, OSError):
- print('\nERROR: Cannot open ', out_file, file=sys.stderr)
- sys.exit(Error.CONFIG_MISMATCH)
+ fa_f.write(out_array_str)
def main():
@@ -1285,12 +1258,6 @@
app_core, app_count, slot_sectors_max, apps_flash_map, apps_ram_map, shared_slot = \
process_images(area_list, boot_and_upgrade)
- if params.image_boot_config:
- image_boot_mode = process_boot_type(boot_and_upgrade)
-
- if image_boot_mode:
- generate_boot_type(image_boot_mode)
-
cy_img_hdr_size = 0x400
app_start = int(apps_flash_map[1].get("primary").get("address"), 0) + cy_img_hdr_size
@@ -1337,7 +1304,7 @@
# Image id parameter is not used for MCUBootApp
if params.img_id is None:
- area_list.generate_c_source(params)
+ area_list.generate_c_source(params, boot_and_upgrade)
area_list.create_flash_area_id(app_count, params)
@@ -1375,6 +1342,7 @@
print('BOOTLOADER_RAM_SIZE :=', hex(boot_ram_area.size))
print('APP_CORE :=', app_core)
+ # for blinky
if params.img_id is not None:
primary_img_start = apps_flash_map[int(params.img_id)].get("primary").get("address")
secondary_img_start = apps_flash_map[int(params.img_id)].get("secondary").get("address")
@@ -1393,6 +1361,7 @@
print('PRIMARY_IMG_START := ' + primary_img_start)
print('SECONDARY_IMG_START := ' + secondary_img_start)
print('SLOT_SIZE := ' + slot_size)
+ # for bootloader
else:
if apps_ram_map:
ram_load_counter = 0
@@ -1401,8 +1370,8 @@
ram_load_counter += 1
if ram_load_counter != 0:
- if ram_load_counter == 1 and app_count == 1:
- print('USE_MCUBOOT_RAM_LOAD := 1')
+ print('USE_MCUBOOT_RAM_LOAD := 1')
+ if ram_load_counter == 1:
print(f'IMAGE_EXECUTABLE_RAM_START := {hex(apps_ram_map[1].get("address"))}')
print(f'IMAGE_EXECUTABLE_RAM_SIZE := {hex(apps_ram_map[1].get("size"))}')
else:
diff --git a/boot/cypress/scripts/memorymap_rework.py b/boot/cypress/scripts/memorymap_rework.py
index 47e681e..855cf23 100644
--- a/boot/cypress/scripts/memorymap_rework.py
+++ b/boot/cypress/scripts/memorymap_rework.py
@@ -40,6 +40,7 @@
, 'bootloader_app_size' : 'BOOTLOADER_SIZE'
, 'bootloader_ram_address' : 'BOOTLOADER_RAM_ORIGIN'
, 'bootloader_ram_size' : 'BOOTLOADER_RAM_SIZE'
+ , 'bootloader_area' : 'BOOTLOADER_AREA'
, 'application_count' : 'MCUBOOT_IMAGE_NUMBER'
, 'boot_image' : 'BOOT_IMAGE_NUMBER'
, 'sectors_count' : 'MAX_IMG_SECTORS'
@@ -47,19 +48,27 @@
, 'image_ram_address' : 'IMG_RAM_ORIGIN'
, 'image_ram_size' : 'IMG_RAM_SIZE'
, 'primary_image_start' : 'PRIMARY_IMG_START'
+ , 'primary_image_area' : 'PRIMARY_IMG_AREA'
, 'secondary_image_start' : 'SECONDARY_IMG_START'
+ , 'secondary_image_area' : 'SECONDARY_IMG_AREA'
, 'image_size' : 'SLOT_SIZE'
}
def header_guard_generate(file):
+ '''
+ Header quard generation
+ '''
file.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
' ALL CHANGES WILL BE LOST! */\n')
file.write("#pragma once\n\n")
-def is_overlap(x : int, y : int) -> bool:
- if x.start == x.stop or y.start == y.stop:
+def is_overlap(x_region, y_region) -> bool:
+ '''
+ Check if memory regions are overlapped
+ '''
+ if x_region.start == x_region.stop or y_region.start == y_region.stop:
return False
- return x.start < y.stop and y.start < x.stop
+ return x_region.start < y_region.stop and y_region.start < x_region.stop
def is_aligned(addr : int, sz : int) -> bool:
''' Check address alignment '''
@@ -82,7 +91,8 @@
def fits_with(self, other) -> bool:
'''
-
+ Checks if "self" belongs "other".
+ @return True, if "self" fits into "other".
'''
return \
self.addr >= other.addr and \
@@ -90,11 +100,11 @@
class MemoryRegion(Memory):
''' Memory region handler '''
- def __init__(self, addr, sz, erase_sz, erase_val, type):
+ def __init__(self, addr, sz, erase_sz, erase_val, mem_type):
super().__init__(addr, sz)
- self.erase_sz : int = erase_sz
- self.erase_val : int = erase_val
- self.type = type
+ self.erase_sz : int = erase_sz
+ self.erase_val : int = erase_val
+ self.mem_type : [str] = mem_type
class BootloaderLayout:
'''
@@ -143,7 +153,8 @@
self.core_name = core
except KeyError as key:
- print('Malformed JSON:', key, 'is missing')
+ print('Malformed JSON:', key, 'is missing', file=sys.stderr)
+ sys.exit(-3)
class MemoryAreaConfig:
'''
@@ -211,19 +222,21 @@
General handler
'''
def __init__(self):
- self.boot_layout : BootloaderLayout = None
- self.regions : MemoryRegion = []
- self.region_types : str = []
- self.apps : ApplicationLayout = []
- self.primary_slots : str = []
- self.secondary_slots: str = []
- self.mem_areas : MemoryAreaConfig = []
- self.param_dict = {}
- self.map_json : json = None
- self.platform_json : json = None
- self.output_folder = None
- self.output_name = None
- self.max_sectors = 32
+ self.boot_layout : BootloaderLayout = None
+ self.regions : MemoryRegion = []
+ self.region_types : str = []
+ self.region_types_alt : str = []
+ self.apps : ApplicationLayout = []
+ self.app_id : int = None
+ self.primary_slots : str = []
+ self.secondary_slots : str = []
+ self.mem_areas : MemoryAreaConfig = []
+ self.param_dict = {}
+ self.map_json : json = None
+ self.platform_json : json = None
+ self.output_folder = None
+ self.output_name = None
+ self.max_sectors = 32
def __apps_init(self):
for image_number in range(1, APP_LIMIT):
@@ -243,21 +256,28 @@
self.boot_layout.parse(self.map_json['bootloader'])
def __memory_regions_init(self):
+ '''
+ Parser for "platform.json".
+ It fills memory_regions.
+ '''
memory_regions = self.platform_json['memory_regions']
+
+ # it's critical to use 'regions' here!
+ # If not, please align the code with enum generation in the __header_gen()
for region in memory_regions:
try:
addr = int(region['address'], 0)
size = int(region['size'], 0)
erase_size = int(region['erase_size'], 0)
erase_value = int(region['erase_value'], 0)
- type = str(region['type'])
+ mem_type = region['mem_type'] if isinstance(region['mem_type'],\
+ list) else [region['mem_type']]
- if type not in self.region_types:
- self.region_types.append(type)
+ self.regions.append(MemoryRegion(addr, size, erase_size, erase_value, mem_type))
- self.regions.append(MemoryRegion(addr, size, erase_size, erase_value, type))
except KeyError as key:
- print('Malformed JSON:', key, 'is missing')
+ print('Malformed JSON:', key, 'is missing', file=sys.stderr)
+ sys.exit(-2)
# Check regions for overlap
for this in self.regions:
@@ -281,7 +301,13 @@
region_id = self.__memory_area_find_region_id(area)
region = self.regions[region_id]
- region_name = region.type
+ region_name = region.mem_type[0]
+ region_name_alt = region.mem_type[1] if len(region.mem_type) > 1 else None
+
+ if region_name_alt:
+ if "boot" in key:
+ if region_name_alt not in self.region_types_alt:
+ self.region_types_alt.append(region_name_alt)
offset = area.addr - region.addr
size = area.sz
@@ -293,6 +319,9 @@
self.mem_areas.append(area_config)
+ if region_name not in self.region_types:
+ self.region_types.append(region_name)
+
# Update max sectors
slot_sectors = int((offset % region.erase_sz +
size + region.erase_sz - 1) //
@@ -350,6 +379,9 @@
self.__memory_area_config_create(key)
def __source_gen(self):
+ '''
+ C-file generation, file name and path must be given by script user
+ '''
path = f'{self.output_folder}/{self.output_name}.c'
include = f'{self.output_name}.h'
@@ -359,13 +391,14 @@
f_out.write('struct flash_device flash_devices[] =\n')
f_out.write('{\n')
for region in self.regions:
- f_out.write('\t{\n')
- f_out.write(f'\t\t.address = {hex(region.addr)}U,\n')
- f_out.write(f'\t\t.size = {hex(region.sz)}U,\n')
- f_out.write(f'\t\t.erase_size = {hex(region.erase_sz)}U,\n')
- f_out.write(f'\t\t.erase_val = {hex(region.erase_val)}U,\n')
- f_out.write(f'\t\t.device_id = {str(region.type)},\n')
- f_out.write('\t},\n')
+ if region.mem_type[0] in self.region_types:
+ f_out.write(f'\t[{region.mem_type[0]}] = ' + '{\n')
+ f_out.write(f'\t\t.address = {hex(region.addr)}U,\n')
+ f_out.write(f'\t\t.size = {hex(region.sz)}U,\n')
+ f_out.write(f'\t\t.erase_size = {hex(region.erase_sz)}U,\n')
+ f_out.write(f'\t\t.erase_val = {hex(region.erase_val)}U,\n')
+ f_out.write(f'\t\t.device_id = {str(region.mem_type[0])},\n')
+ f_out.write('\t},\n')
f_out.write('};\n\n')
f_out.write(f'struct flash_area flash_areas[] =\n')
@@ -387,23 +420,34 @@
f_out.write('\tNULL\n};\n\n')
f_out.write('uint8_t memory_areas_primary[] =\n')
- f_out.write('{\n')
+ f_out.write('{')
for slot in self.primary_slots:
- f_out.write(f'\t{slot}, ')
+ f_out.write(f'\n\t{slot}, ')
f_out.write('\n};\n\n')
f_out.write('uint8_t memory_areas_secondary[] =\n')
- f_out.write('{\n')
+ f_out.write('{')
for slot in self.secondary_slots:
- f_out.write(f'\t{slot}, ')
+ f_out.write(f'\n\t{slot}, ')
f_out.write('\n};\n\n')
+ f_out.write('image_boot_config_t image_boot_config[BOOT_IMAGE_NUMBER] = {\n')
+ for app in self.apps:
+ f_out.writelines('\n'.join([
+ '\t{\n'
+ f"\t\t.mode = {'IMAGE_BOOT_MODE_RAM' if app.has_ram_boot else 'IMAGE_BOOT_MODE_FLASH'},",
+ f"\t\t.address = {hex(app.ram_boot.addr) if app.has_ram_boot else hex(app.boot_area.addr)},",
+ f"\t\t.size = {hex(app.ram_boot.sz) if app.has_ram_boot else hex(app.boot_area.sz)},",
+ '\t},\n']))
+ f_out.write('};\n')
+
def __header_gen(self):
path = f'{self.output_folder}/{self.output_name}.h'
with open(path, "w", encoding='UTF-8') as f_out:
header_guard_generate(f_out)
f_out.write(f'#include <stdint.h>\n')
+ f_out.write('#include "bootutil/bootutil.h"\n')
f_out.write(f'#include "flash_map_backend.h"\n\n')
f_out.write(f'#define MEMORYMAP_GENERATED_AREAS 1\n\n')
f_out.write('extern struct flash_device flash_devices[];\n')
@@ -412,8 +456,12 @@
f_out.write('extern uint8_t memory_areas_secondary[];\n\n')
f_out.write('enum \n{\n')
- for id, type in enumerate(self.region_types):
- f_out.write(f'\t{type} = {id}U,\n')
+
+ # it's critical to use 'regions' here!
+ # because it fixes the bug when enum {INTERNAL_RRAM, EXTERNAL_FLASH,}
+ # is generated in incorrect sequence.
+ for region in self.regions:
+ f_out.write(f'\t{str(region.mem_type[0])},\n')
f_out.write('};\n\n')
f_out.write('enum \n{\n')
@@ -421,18 +469,38 @@
f_out.write(f'\t{area_param[1]} = {area_param[2]}U,\n')
f_out.write('};\n\n')
+ f_out.write('typedef enum \n{\n')
+ f_out.write('\tIMAGE_BOOT_MODE_FLASH = 0U,\n')
+ f_out.write('\tIMAGE_BOOT_MODE_RAM = 1U,\n')
+ f_out.write('} image_boot_mode_t;\n\n')
+
+ f_out.write('typedef struct image_boot_config_s \n{\n')
+ f_out.write('\timage_boot_mode_t mode;\n')
+ f_out.write('\tuint32_t address;\n')
+ f_out.write('\tuint32_t size;\n')
+ f_out.write('} image_boot_config_t;\n\n')
+
+ f_out.write('extern image_boot_config_t image_boot_config[BOOT_IMAGE_NUMBER];\n\n')
+
def __bootloader_mk_file_gen(self):
boot = self.boot_layout
+
+ for mem_type in self.region_types:
+ print(f'USE_{mem_type} := 1')
+
+ for mem_type in self.region_types_alt:
+ print(f'USE_{mem_type} := 1')
+
# Upgrade mode
if boot.scratch_area is None and boot.status_area is None:
print(settings_dict['overwrite'], ':= 1')
else:
- print(settings_dict['overwrite'], ':= 0')
print(settings_dict['swap'], ':= 1')
print(settings_dict['scratch'], f':= {0 if boot.scratch_area is None else 1}')
print(settings_dict['status'], f':= {0 if boot.status_area is None else 1}')
- print('# Shared data')
+
if boot.shared_data is not None:
+ print('# Shared data')
shared_data = boot.shared_data
print(settings_dict['measured_boot'], ':= 1')
print(settings_dict['data_sharing'], ':= 1')
@@ -442,25 +510,30 @@
print(f'{settings_dict["shared_data_record_size"]} :=', hex(shared_data.sz))
print('# Bootloader app area')
+ for region in self.regions:
+ if boot.bootloader_area.fits_with(region):
+ print(f'{settings_dict["bootloader_area"]} :=', str(region.mem_type[0]))
+ break
+
print(f'{settings_dict["bootloader_app_address"]} :=', hex(boot.bootloader_area.addr))
print(f'{settings_dict["bootloader_app_size"]} :=', hex(boot.bootloader_area.sz))
- print('# Bootloader ram area')
if boot.ram is not None:
+ print('# Bootloader ram area')
print(f'{settings_dict["bootloader_ram_address"]} :=', hex(boot.ram.addr))
print(f'{settings_dict["bootloader_ram_size"]} :=', hex(boot.ram.sz))
print('# Application area')
- for id, app in enumerate(self.apps):
- print(f'APPLICATION_{id+1}_BOOT_SLOT_ADDRESS := {hex(app.boot_area.addr)}')
- print(f'APPLICATION_{id+1}_BOOT_SLOT_SIZE := {hex(app.boot_area.sz)}')
- print(f'APPLICATION_{id+1}_UPGRADE_SLOT_ADDRESS := {hex(app.upgrade_area.addr)}')
- print(f'APPLICATION_{id+1}_UPGRADE_SLOT_SIZE := {hex(app.upgrade_area.sz)}')
+ for img_id, app in enumerate(self.apps):
+ print(f'APPLICATION_{img_id+1}_BOOT_SLOT_ADDRESS := {hex(app.boot_area.addr)}')
+ print(f'APPLICATION_{img_id+1}_BOOT_SLOT_SIZE := {hex(app.boot_area.sz)}')
+ print(f'APPLICATION_{img_id+1}_UPGRADE_SLOT_ADDRESS := {hex(app.upgrade_area.addr)}')
+ print(f'APPLICATION_{img_id+1}_UPGRADE_SLOT_SIZE := {hex(app.upgrade_area.sz)}')
- print('# Ram load')
# Ram load single
if len(self.apps) == 1:
if self.apps[0].ram_boot is not None:
+ print('# Ram load')
ram_boot = self.apps[0].ram_boot
print(settings_dict['ram_load'], ':= 1')
print(f'{settings_dict["ram_load_address"]} :=', hex(ram_boot.addr))
@@ -477,13 +550,13 @@
if app1.overlaps_with(app2):
ram_addr_overlap_counter += 1
- for id, app in enumerate(self.apps):
+ for img_id, app in enumerate(self.apps):
if app.ram_boot is not None:
ram_boot_counter += 1
ram_boot = app.ram_boot
- print(f'APPLICATION_{id+1}_RAM_LOAD_ADDRESS := {hex(ram_boot.addr)}')
- print(f'APPLICATION_{id+1}_RAM_LOAD_SIZE := {hex(ram_boot.sz)}')
+ print(f'APPLICATION_{img_id+1}_RAM_LOAD_ADDRESS := {hex(ram_boot.addr)}')
+ print(f'APPLICATION_{img_id+1}_RAM_LOAD_SIZE := {hex(ram_boot.sz)}')
if ram_boot_counter != 0:
print(settings_dict['ram_load'], ':= 1')
@@ -494,8 +567,15 @@
print('# Mcuboot')
print(settings_dict['application_count'], f'= {len(self.apps)}')
print(settings_dict['sectors_count'], f'= {self.max_sectors}')
+ print('\n',settings_dict['application_count'], f'= {len(self.apps)}', file=sys.stderr)
def __application_mk_file_gen(self):
+ for mem_type in self.region_types:
+ print(f'USE_{mem_type} := 1')
+
+ for mem_type in self.region_types_alt:
+ print(f'USE_{mem_type} := 1')
+
app = self.apps[self.app_id-1]
boot = self.boot_layout
# Upgrade mode
@@ -512,8 +592,17 @@
print(settings_dict['primary_image_start'], ':=', hex(app.boot_area.addr))
print(settings_dict['secondary_image_start'], ':=', hex(app.upgrade_area.addr))
print(settings_dict['image_size'], ':=', hex(app.boot_area.sz))
+
+ for region in self.regions:
+ if app.boot_area.fits_with(region):
+ print(settings_dict['primary_image_area'], ':=', str(region.mem_type[0]))
+ if app.upgrade_area.fits_with(region):
+ print(settings_dict['secondary_image_area'], ':=', str(region.mem_type[0]))
+
if app.ram_boot:
print(settings_dict['ram_load'], ':= 1')
+ print(settings_dict['image_ram_address'], ':=', hex(app.ram_boot.addr))
+ print(settings_dict['image_ram_size'], ':=', hex(app.ram_boot.sz))
if app.ram:
print(settings_dict['image_ram_address'], ':=', hex(app.ram.addr))
print(settings_dict['image_ram_size'], ':=', hex(app.ram.sz))
@@ -521,6 +610,9 @@
print(settings_dict['core'], ':=', app.core_name)
def parse(self, memory_map, platform_config, output_folder, output_name, app_id):
+ ''''
+ Parser to process memory maps, platform config and generation of all need files
+ '''
try:
with open(memory_map, "r", encoding='UTF-8') as f_in:
self.map_json = json.load(f_in)
@@ -539,10 +631,9 @@
self.__apps_init()
self.__memory_areas_create()
- self.__source_gen()
- self.__header_gen()
-
if app_id is None:
+ self.__source_gen()
+ self.__header_gen()
self.__bootloader_mk_file_gen()
else:
self.__application_mk_file_gen()
@@ -571,12 +662,15 @@
help='application image number')
def run(memory_config, platform_config, output_folder, output_name, image_id):
- map = MemoryMap()
- map.parse(memory_config,
+ ''''
+ The main method to be used by cli()
+ '''
+ imemmap = MemoryMap()
+ imemmap.parse(memory_config,
platform_config,
output_folder,
output_name,
image_id)
if __name__ == '__main__':
- cli()
\ No newline at end of file
+ cli()
diff --git a/boot/cypress/toolchains.mk b/boot/cypress/toolchains.mk
index 144f62e..9fe6191 100644
--- a/boot/cypress/toolchains.mk
+++ b/boot/cypress/toolchains.mk
@@ -79,7 +79,7 @@
endif
ifeq ($(BUILDCFG), Debug)
- CFLAGS_SPECIAL ?= -Og -g3
+ CFLAGS_SPECIAL ?= -Og -g3 -ffile-prefix-map=$(CURDIR)=.
CFLAGS_COMMON += $(CFLAGS_SPECIAL)
else ifeq ($(BUILDCFG), Release)
ifeq ($(CFLAGS_OPTIMIZATION), )