Infineon: Add cyw20829 platform, shared slot feature, json memory map, psoc6 xip
Based in 1.8.0 release of MCUBoot library
This commit adds CYW20829 Infineon platform support with following capabilities:
1. Overwrite and swap upgrade mode support
2. Multi-image with up to 4 images
3. Hardware security counter is supported for CYW20829 platform
Add XIP support for PSOC6 platform - place BOOT slot in external memory and execute it in place using SMIF in XIP mode
and some new features for Infineon devices.
1. Shared upgrade slot feature - use one shared area for upgrade slots of multiple images
2. Memory map defined using JSON file - define memory regions for bootloader and user app in conventional way using JSON file
diff --git a/boot/cypress/.gitignore b/boot/cypress/.gitignore
index 9a2c99f..e8f03b4 100644
--- a/boot/cypress/.gitignore
+++ b/boot/cypress/.gitignore
@@ -26,6 +26,11 @@
/scripts/*.egg-info
/scripts/*.egg
+# Pre_build autogenerated files
+MCUBootApp/flashmap.mk
+BlinkyApp/flashmap.mk
+cy_flash_pal/cy_flash_map.h
+
# Build dirs
*out/*/*
*out/obj/*
@@ -38,4 +43,13 @@
*.bin
*.hex
*.log
-*.lst
\ No newline at end of file
+*.lst
+*.objdump
+
+packets/*
+policy/*
+keys/*
+
+BlinkyApp.ld
+*.modus
+*.cysecuretools
\ No newline at end of file
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.md b/boot/cypress/BlinkyApp/BlinkyApp.md
index d380673..f3f20da 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.md
+++ b/boot/cypress/BlinkyApp/BlinkyApp.md
@@ -1,191 +1,184 @@
-### Blinking LED Test Application For Mcubootapp Bootloading Application
+## Blinking LED test application for MCUBootApp bootloading application
### Description
-Implements simple Blinky LED CM4 application to demonstrate MCUBootApp bootloading application operation in terms of boot and upgrade processes.
+Implements a simple Blinky LED application to demonstrate the MCUBootApp bootloading application operation for the boot and upgrade processes.
-It is validated and started by MCUBootApp which is running on CM0p core of PSoC 6 device.
+It is validated and started by MCUBootApp, which is running on the CM0p core of PSoC™ 6 devices, or CM33 core for the CYW20829 device.
Functionality:
-* Blinks RED led with 2 different rates, depending on type of image - BOOT or UPGRADE.
-* Prints debug info and version of itself to terminal at 115200 baud rate.
-* Manages watchdog timer started in MCUBootApp as one of confirmation mechanisms.
-* Sets special bit in flash to confirm image is operable (UPGRADE image).
-* Can be built for BOOT slot or UPGRADE slot of bootloader.
+* Blinks red LED with 2 different rates, depending on the image type - BOOT or UPGRADE.
+* Prints debug info and the appplication version to the terminal at baud rate 115200.
+* Manages the watchdog-timer start in MCUBootApp as one of the confirmation mechanisms.
+* Sets a special bit in flash to confirm that the image is operable (UPGRADE image).
+* Can be built for boot slot or UPGRADE slot of the bootloader.
* Can be used to evaluate `swap` and `overwrite only` upgrade modes.
-### Hardware Limitations
+### Hardware limitations
-Since this application is created to demonstrate MCUBoot library features and not as reference examples some considerations are taken.
+This application is created to demonstrate the MCUboot library features.
-1. Port/pin `P5_0` and `P5_1` used to configure serial port for debug prints. These pins are the most commonly used for serial port connection among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definitions of `CY_DEBUG_UART_TX` and `CY_DEBUG_UART_RX` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
-2. Port `GPIO_PRT13` pin `7U` used to define user connection LED. This pin is the most commonly used for USER_LED connection among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definitions of `LED_PORT` and `LED_PIN` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
+1. Port/pin `P5_0` and `P5_1` are used to configure a serial port for debug prints. These pins are the most commonly used for serial port connection among available Cypress PSoC™ 6 kits. To use custom hardware with this application, change the definitions of `CY_DEBUG_UART_TX` and `CY_DEBUG_UART_RX` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
+2. Port `GPIO_PRT13` pin `7U` is used to define the user connection-LED. This pin is the most commonly used for USER_LED connection among available Cypress PSoC™ 6 kits. To use custom hardware with this application, change the definitions of `LED_PORT` and `LED_PIN` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
-### Pre-build Action
+### Pre-build action
-Pre-build action is implemented to define start address and size of flash, as well as RAM start address and size for BlinkyApp.
+Pre-build action is implemented to define the start address and flash size, as well as the RAM start address and BlinkyApp size.
-These values are set by specifing following macros (default values shown):
-`SLOT_SIZE ?= 0x10000` - for slot located in internal flash
-`SLOT_SIZE ?= 0x40200` - for slot located in external flash
+`FLASH_MAP` `make` parameter is used to provide an input file for pre-build action. Refer to `MCUBootApp.md` for details.
-For PSoC 6 2M devices:
-`DEFINES_APP += -DRAM_START=0x08040000`
-`DEFINES_APP += -DRAM_SIZE=0x10000`
+The result of pre-build script is auto-generated `flashmap.mk` file with a set of makefile flags:
-For PSoC 6 1M and 512K devices:
-`DEFINES_APP += -DRAM_START=0x08020000`
-`DEFINES_APP += -DRAM_SIZE=0x10000`
+`PRIMARY_IMG_START` - start address of primary image in flash, this value is defined in the JSON flash map as the `"value"` field of the address section for `"application_#"`.
-For all devices:
-`DEFINES_APP += -DUSER_APP_START=0x10018000`
+`SECONDARY_IMG_START`- start address of secondary image in flash, this value is defined in the JSON flash map as the `"upgrade_address"` field of the `"address"` section for `"application_#"`.
-in `boot/cypress/BlinkyApp.mk`.
+`SLOT_SIZE` - slot size for the primary and the secondary images, this value is taken from `"value"` field of `"size"` section of `"application_#"` from JSON file.
-Pre-build action calls GCC preprocessor which replaces defines to particular values in `BlinkyApp_template.ld`.
+`BOOTLOADER_SIZE` - size of Bootloader application, this value is defined in the JSON flash map as the `"size"` field of the address section for `"bootloader"`.
-**Important**: make sure RAM areas of CM4-based BlinkyApp and CM0p-based MCUBootApp bootloader do not overlap.
+`USE_EXTERNAL_FLASH` - is set to 1 if flash map with `_smif` suffix is chosen.
-Memory (stack) corruption of CM0p application can cause failure if SystemCall-served operations invoked from CM4.
+`USE_XIP` - is set to 1 if the "external_flash" section with "mode": "XIP" is present in the flash map file.
-### Building An Application
+These values are set by specifying the following macros (default values shown):
+`SLOT_SIZE ?= 0x10000` - for slot located in internal flash of PSoC™ 6 chips
+`SLOT_SIZE ?= 0x40200` - for slot located in external flash of PsoC™ 6 kits
+`SLOT_SIZE ?= 0x20000` - for slot located in external flash of CYW20829 kits
-Supported platforms:
+The pre-build action also calls the GCC preprocessor, which replaces the defines to particular values in `BlinkyApp_template.ld`.
+
+**Important (PSoC™ 6)**: ensure that the RAM areas of CM4-based BlinkyApp and CM0p-based MCUBootApp bootloader do not overlap.
+
+Memory (stack) corruption of the CM0p application can cause a failure if SystemCall-served operations were invoked from CM4.
+
+### Building an application
+
+The supported platforms:
* PSOC_062_2M
* PSOC_062_1M
* PSOC_062_512K
+* CYW20829
-Root directory for build is **boot/cypress.**
+The root directory for build is **boot/cypress.**
-**Single image**
+**Single-image**
-The following command will build regular HEX file of a BlinkyApp for primary (BOOT) slot:
+The following command will build BlinkyApp as a regular HEX file for the primary (BOOT) slot to be used in single image case with `swap` upgrade type of Bootloader:
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json IMG_ID=1
-_Note: HEADER_OFFSET=%SLOT_SIZE%_
+To build an image for the secondary (UPGRADE) slot to be used in single image case with `swap` upgrade type of Bootloader:
-To build image for secondary (UPGRADE) slot to use in `swap` upgrade:
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json IMG_ID=1
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x10000 SWAP_UPGRADE=1
+To build an image for the secondary (UPGRADE) slot to be used in single image case with `overwrite` upgrade type of Bootloader:
-To build image for secondary (UPGRADE) slot to use in `overwrite only` upgrade:
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single.json IMG_ID=1
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x10000 SWAP_UPGRADE=0
+**Multi-image**
-To build image for primary (BOOT) image for custom slot size `0x70000`:
+`BlinkyApp` can be built in multi-image bootloader configuration for PSoC™ 6 chips only.
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT SLOT_SIZE=0x70000
+To obtain the appropriate hex files to use with multi-image MCUBootApp, makefile flag `IMG_ID` is used.
-To build image for secondary (UPGRADE) image for custom slot size `0x70000` to use in `swap` upgrade:
+`IMG_ID` flag value should correspond to `application_#` number of JSON file used for build. For example to build `BlinkyApp` for UPGRADE slot of second image following command is used:
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE SLOT_SIZE=0x70000 HEADER_OFFSET=0x70000 SWAP_UPGRADE=1
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single.json IMG_ID=2
-**Multi image**
-
-`BlinkyApp` can be built to use in multi image bootloader configuration.
-
-To obtain appropriate hex files to use with multi image MCUBootApp, makefile flag `HEADER_OFFSET=` can be used.
-
-Example usage:
-
-Considering default config:
-
-* first image BOOT (PRIMARY) slot starts `0x10018000`
-* slot size `0x10000`
-* second image BOOT (PRIMARY) slot starts at `0x10038000`
-
-To obtain appropriate artifact for second image PRIMARY slot run this command:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT HEADER_OFFSET=0x20000
-
-*Note:* only 2 images are supported at the moment.
+When this option is omitted, `IMG_ID=1` is assumed.
**Upgrade mode dependency**
-`MCUBootApp` can upgrade image either by overwriting an image from a secondary slot to a primary slot or by swapping the two images.
+`MCUBootApp` can upgrade an image either by overwriting the image from a secondary slot to a primary slot or by swapping the two images.
-To build `BlinkyApp` for different upgrade mode `SWAP_UPGRADE` flag is used.
+To build `BlinkyApp` for different upgrade mode choose flash map JSON file with the corresponding suffix - either _swap_ or _overwrite_.
-`SWAP_UPGRADE=0` - for overwrite mode.
-`SWAP_UPGRADE=1` - for swap upgrade mode (default).
+**Upgrade image for external memory (PSoC™ 6)**
-**Upgrade image for external memory**
+To prepare MCUBootApp for work with external memory, refer to [ExternalMemory.md](../MCUBootApp/ExternalMemory.md).
-To prepare MCUBootApp for work with external memory refer to `MCUBootApp/ExternalMemory.md`.
+To build a `BlinkyApp` upgrade image for external memory to be used in single image configuration with overwrite upgrade mode, use command:
-To build `BlinkyApp` upgrade image for external memory use command:
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single_smif.json IMG_ID=1
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x7FE8000 ERASED_VALUE=0xff USE_EXTERNAL_FLASH=1
+`ERASED_VALUE` defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S. For `CYW20289` default value is `0xff` since it only uses an external flash.
-`HEADER_OFFSET` defines the offset from original boot image address. This one in line above suggests secondary slot will start from `0x18000000`, which is a start of external memory related addreses on PSoC 6 devices.
+In multi-image configuration, an upgrade image for the second application is built using command:
-`ERASED_VALUE` defines the memory cell contents in erased state. It is `0x00` for PSoC 6 internal Flash and `0xff` for S25FL512S.
-
-In case of using muti-image configuration, upgrade image for second application can be built using next command:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x8228000 ERASED_VALUE=0xff USE_EXTERNAL_FLASH=1
-
-Note: for S25FL512S block address should be mutiple of 0x40000.
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi_smif.json IMG_ID=2
**Encrypted upgrade image**
-To prepare MCUBootApp for work with encrypted upgrade image please refer to `MCUBootApp/Readme.md`.
+To prepare MCUBootApp for work with an encrypted upgrade image, refer to [MCUBootApp.md](../MCUBootApp/MCUBootApp.md).
-To obtain encrypted upgrade image of BlinkyApp extra flag ENC_IMG=1 should be passed in command line, for example:
+To obtain an encrypted upgrade image of BlinkyApp, pass extra flag `ENC_IMG=1` in the command line, for example:
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x20000 ENC_IMG=1
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single_smif.json IMG_ID=1 ENC_IMG=1
-This also suggests user already placed corresponing *.pem key in \keys folder. The key variables are defined in root Makefile as SIGN_KEY_FILE and ENC_KEY_FILE
+This also suggests that the user has already placed a corresponding *.pem key in the \keys folder. The key variables are defined in root Makefile as SIGN_KEY_FILE and ENC_KEY_FILE
-### Complete Build Flags Description
-- `BUILDCFG` - configuration type
+Refer to [CYW20829.md](../platforms/CYW20829/CYW20829.md) for details of encrypted image build for the CYW20289 platfrom.
+
+### Complete build flags description
+- `BUILDCFG` - The configuration type
- Release
- Debug
-- `MAKEINFO` - build verbosity level
+- `VERBOSE` - The build verbosity level
- 0 (default) - less build info
- 1 - verbose output of compilation
- `PLATFORM`
- - `PSOC_062_2M` - only supported now
-- `SLOT_SIZE` - size of primary/secondary slot of MCUBootApp this app will be used with
+ - `PSOC_062_2M`
+ - `PSOC_062_1M`
+ - `PSOC_062_512K`
+ - `CYW20289`
+- `SLOT_SIZE` - The size of the primary/secondary slot of MCUBootApp. This app will be used with
- 0x%VALUE%
-- `HEADER_OFFSET` - shift start address of image by value
- - 0 (default) - no offset of output hex file
- - 0x%VALUE% - offset for output hex file
-- `IMG_TYPE` - for which slot of MCUBootApp image is build
- - `BOOT` (default) - build image for primary (BOOT) slot
- - `UPGRADE` - build image for secondary (UPGRADE) slot
-- `SWAP_UPGRADE` - define upgrade mode type on `MCUBootApp` this app will be used with
- - `0` - for overwrite mode.
- - `1` - (default) for swap upgrade mode
-- `ERASED_VALUE` - define memory cell contents in erased state
- - `0x0` - internal memory
- - `0xff` - external memory
-- `TOOLCHAIN_PATH` - path to gcc compiler to use for build
- - Example: TOOLCHAIN_PATH=/home/fw-security/ModusToolbox/tools_2.0/gcc-7.2.1
- - Example: TOOLCHAIN_PATH=C:\gcc
+- `IMG_TYPE` - The slot of MCUBootApp, for which the image is being built.
+ - `BOOT` (default) - A build image for the primary (BOOT) slot.
+ - `UPGRADE` - A build image for the secondary (UPGRADE) slot.
+- `ERASED_VALUE` - Define memory cell contents in the erased state.
+ - `0x0` - Internal memory.
+ - `0xff` - External memory.
+- `TOOLCHAIN_PATH` - The path to the GCC compiler to use for build.
+ - Example: TOOLCHAIN_PATH=/home/user/ModusToolbox/tools_2.4/gcc
+ - Example: TOOLCHAIN_PATH=C:/ModusToolbox/tools_2.4/gcc
-### Post-Build
+Flags set by pre-build action.
-Post build action is executed at compile time for `BlinkyApp`. In case of build for `PSOC_062_2M`, `PSOC_062_1M`, `PSOC_062_512K` platforms it calls `imgtool` from `MCUBoot` scripts and adds signature to compiled image.
+- `USE_OVERWRITE` - Define the Upgrade mode type of `MCUBootApp` to use with this app.
+ - `1` - For Overwrite mode.
+ - `0` - (default) For Swap Upgrade mode.
+- `USE_EXTERNAL_FLASH` - Define support of external flash.
+ - `1` - external flash is present.
+ - `0` - external flash is absent.
+- `USE_XIP` - Define support of eXecute in Place mode.
+ - `0` - Not used
+ - `1` - Used
-Flags passed to `imgtool` for signature are defined in `SIGN_ARGS` variable in BlinkyApp.mk.
+### Post-build
-### How To Program An Application
+The post-build action is executed at the compile time for `BlinkyApp`. For the `PSOC_062_2M`, `PSOC_062_1M`, `PSOC_062_512K` platforms, it calls `imgtool` from `MCUboot` scripts and adds a signature to the compiled image.
-There are couple ways of programming BlinkyApp firmware. Following instructions assume usage of one of Cypress development kits, for example `CY8CPROTO_062_4343W`.
+Flags passed to `imgtool` for a signature are defined in the `SIGN_ARGS` variable in BlinkyApp.mk.
+
+For `CYW20829`, `cysecuretools` is used for the image signing.
+
+### How to program an application
+
+BlinkyApp firmware can be programmed in different ways. The following instructions assume the usage of one of Cypress development kits, for example `CY8CPROTO_062_4343W`.
1. Direct usage of OpenOCD.
-OpenOCD package is supplied with ModusToolbox IDE and can be found in installation folder under `./tools_2.1/openocd`.
+Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
-Open terminal application - and execute following command after substitution `PATH_TO_APPLICATION.hex` and `OPENOCD` paths.
+The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in the ModusToolbox™ installation folder `ModusToolbox/tools_2.4/openocd`.
-Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines.
+Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION.hex` and `OPENOCD` paths:
- export OPENOCD=/Applications/ModusToolbox/tools_2.1/openocd
+ export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
-f ${OPENOCD}/scripts/interface/kitprog3.cfg \
@@ -197,48 +190,48 @@
Follow [link](https://www.cypress.com/products/psoc-programming-solutions) to download.
-Connect board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines. Open `Cypress Programmer` and click `Connect`, then choose hex file: `MCUBootApp.hex` or `BlinkyApp.hex` and click `Program`. Check log to ensure programming success. Reset board.
+Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines. Open `Cypress Programmer` and click `Connect`, then choose the hex file `MCUBootApp.hex` or `BlinkyApp.hex`, and finally click `Program`. Check the log to ensure that the programming is successful. Reset the board.
3. Using `DAPLINK`.
-Connect board to your computer. Switch embeded Kitprog3 to `DAPLINK` mode by pressing `SW3 MODE` button until `LED2 STATUS` blinks fast and mass storage device appeared in OS. Drag and drop `hex` files you wish to program to `DAPLINK` drive in your OS.
+Connect the board to your computer. Switch embedded Kitprog3 to `DAPLINK` mode by clicking the `SW3 MODE` button until `LED2 STATUS` blinks fast and the USB mass storage device displays in the OS. Drag and drop the `hex` files to be programmed to the `DAPLINK` drive in your OS.
**Hex file names to use for programming**
-`BlinkyApp` always produce build artifacts in 2 separate folders: `BlinkyApp/out/PSOC_062_2M/Debug/boot` and `BlinkyApp/out/PSOC_062_2M/Debug/upgrade`.
+`BlinkyApp` always produces build artifacts in two separate folders: `BlinkyApp/out/PSOC_062_2M/Debug/boot` and `BlinkyApp/out/PSOC_062_2M/Debug/upgrade`.
These files are ready to be flashed to the board:
-* **BlinkyApp.hex** from `boot` folder
-* **BlinkyApp_upgrade.hex** from `upgrade` folder
+* **BlinkyApp.hex** from the `boot` folder
+* **BlinkyApp_upgrade.hex** from the `upgrade` folder
-`BlinkyApp_unsigned.hex` hex file is also preserved in both cases for possible troubleshooting.
+The `BlinkyApp_unsigned.hex` hex file is also preserved in both cases for possible troubleshooting.
-**Important: When swap status upgrade mode used**
+**Important: When Swap status Upgrade mode is used**
- In case of using this application in a system with `swap` type of upgrade refer first to `MCUBootApp.md` section **SWAP/Expected lifecycle**.
+ While using this application in a system with the `swap` type of upgrade, refer first to the [MCUBootApp.md](../MCUBootApp/MCUBootApp.md) section **SWAP/Expected lifecycle**.
-**BlinkyApp.hex** should be programmed to a device once. All firmware upgrades should be delivered using secondary (UPGRADE) slot thus **BlinkyApp_upgrade.hex** image.
+**BlinkyApp.hex** can be programmed to a device once. All firmware upgrades are delivered using the secondary (UPGRADE) slot, thus a **BlinkyApp_upgrade.hex** image.
-If user for some reason tries to program **BlinkyApp.hex** to primary slot directly second time - **system state should be reset**.
+If the user tries to program **BlinkyApp.hex** to the primary slot directly for the second time - **system state should be reset**.
-To reset system state at least `swap status partition` area in flash should be erased - see addresses in `MCUBootApp.md` paragraph **Memory maps**.
+To reset the system state, erase at least the `swap status partition` area in flash - see the addresses in the [MCUBootApp.md](../MCUBootApp/MCUBootApp.md) paragraph **Memory maps**.
-To erase swap status partition area in MCUBootApp with a single image configuration with default memory map using `OpenOCD` execute command:
+To erase the swap status partition area in MCUBootApp with single-image configuration with the default memory map, use the `OpenOCD` command:
$OPENOCD_PATH/bin/openocd -s "$OPENOCD_PATH/scripts" -f "$OPENOCD_PATH/ scripts/interface/kitprog3.cfg" -f "$OPENOCD_PATH/scripts/target/psoc6_2m.cfg" -c "init; reset init" -c "flash erase_address 0x10038000 0x1000" -c "reset; shutdown"
-To erase swap status partition area in MCUBootApp with a multi image configuration with default memory map using `OpenOCD` execute command:
+To erase the swap status partition area in MCUBootApp with multi-image configuration with the default memory map, use the `OpenOCD` command:
$OPENOCD_PATH/bin/openocd -s "$OPENOCD_PATH/scripts" -f "$OPENOCD_PATH/ scripts/interface/kitprog3.cfg" -f "$OPENOCD_PATH/scripts/target/psoc6_2m.cfg" -c "init; reset init" -c "flash erase_address 0x10078000 0x2000" -c "reset; shutdown"
-In both cases it is easier to erase all device flash or all flash after MCUBootApp. This command erases all flash after MCUBootApp including primary, secondary and swap status partiton.
+In both cases, it is easier to erase the whole device flash or all flash after MCUBootApp. This command erases all flash after MCUBootApp, including the primary, secondary, and swap status partiton:
- $OPENOCD_PATH/bin/openocd -s "$OPENOCD_PATH/scripts" -f "$OPENOCD_PATH/ scripts/interface/kitprog3.cfg" -f "$OPENOCD_PATH/scripts/target/psoc6_2m.cfg" -c "init; reset init" -c "flash erase_address 0x10018000" -c "reset; shutdown"
+ $OPENOCD_PATH/bin/openocd -s "$OPENOCD_PATH/scripts" -f "$OPENOCD_PATH/ scripts/interface/kitprog3.cfg" -f "$OPENOCD_PATH/scripts/target/psoc6_2m.cfg" -c "init; reset init" -c "flash erase_address 0x10018000 0x1E8000" -c "reset; shutdown"
-### Example Terminal Output
+### Example terminal output
-When user application programmed in BOOT slot:
+When the user application is programmed in the boot slot:
===========================
[BlinkyApp] BlinkyApp v1.0 [CM4]
@@ -250,7 +243,7 @@
[BlinkyApp] Update watchdog timer started in MCUBootApp to mark sucessful start of user app
[BlinkyApp] Turn off watchdog timer
-When user application programmed in UPRADE slot and upgrade procedure was successful:
+When the user application is programmed in the upgrade slot and the upgrade procedure was successful:
===========================
[BlinkyApp] BlinkyApp v2.0 [+]
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.mk b/boot/cypress/BlinkyApp/BlinkyApp.mk
index edfaed6..d06cd99 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.mk
+++ b/boot/cypress/BlinkyApp/BlinkyApp.mk
@@ -32,89 +32,21 @@
# - image type to BOOT
COMPILER ?= GCC_ARM
IMG_TYPE ?= BOOT
-
-# For which core this application is built
-CORE ?= CM4
+IMG_ID ?= 1
# image type can be BOOT or UPGRADE
IMG_TYPES = BOOT UPGRADE
-# use SWAP_UPGRADE = 0 for overwrite only mode
-# use SWAP_UPGRADE = 1 for swap upgrade mode
-SWAP_UPGRADE ?= 1
-
-# possible values are 0 and 0xff
-# internal Flash by default
-ERASED_VALUE ?= 0
-
-ifneq ($(COMPILER), GCC_ARM)
-$(error Only GCC ARM is supported at this moment)
-endif
-
CUR_APP_PATH = $(PRJ_DIR)/$(APP_NAME)
-include $(PRJ_DIR)/platforms.mk
-include $(PRJ_DIR)/common_libs.mk
-include $(PRJ_DIR)/toolchains.mk
-
-# Application-specific DEFINES
-ifeq ($(IMG_TYPE), BOOT)
- DEFINES_APP := -DBOOT_IMG
-else
- DEFINES_APP := -DUPGRADE_IMG
- DEFINES_APP += -DSWAP_ENABLED=$(SWAP_UPGRADE)
+ifneq ($(FLASH_MAP), )
+$(CUR_APP_PATH)/flashmap.mk:
+ $(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/cy_flash_pal/cy_flash_map.h -d $(IMG_ID) > $(CUR_APP_PATH)/flashmap.mk
+include $(CUR_APP_PATH)/flashmap.mk
+DEFINES_APP := -DCY_FLASH_MAP_JSON
endif
-# Define start of application, RAM start and size, slot size
-ifeq ($(PLATFORM), PSOC_062_2M)
- DEFINES_APP += -DRAM_START=0x08040000
- DEFINES_APP += -DRAM_SIZE=0x10000
-else ifeq ($(PLATFORM), PSOC_062_1M)
- DEFINES_APP += -DRAM_START=0x08020000
- DEFINES_APP += -DRAM_SIZE=0x10000
-else ifeq ($(PLATFORM), PSOC_062_512K)
- DEFINES_APP += -DRAM_START=0x08020000
- DEFINES_APP += -DRAM_SIZE=0x10000
-endif
-ifeq ($(USE_EXTERNAL_FLASH), 1)
-$(warning You are trying to build BlinkyApp for MCUBootApp with external memory support. Ensure you build MCUBootApp with USE_EXTERNAL_FLASH=1 flag!)
- SLOT_SIZE ?= 0x40200
-else
- SLOT_SIZE ?= 0x10000
-endif
-
-DEFINES_APP += -DUSER_APP_SIZE=$(SLOT_SIZE)
-DEFINES_APP += -DUSER_APP_START=0x10018000
-
-# Collect Test Application sources
-SOURCES_APP_SRC := $(wildcard $(CUR_APP_PATH)/*.c)
-# Collect all the sources
-SOURCES_APP += $(SOURCES_APP_SRC)
-
-# Collect includes for BlinkyApp
-INCLUDE_DIRS_APP := $(addprefix -I, $(CURDIR))
-INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH))
-
-# Overwite path to linker script if custom is required, otherwise default from BSP is used
-ifeq ($(COMPILER), GCC_ARM)
-LINKER_SCRIPT := $(subst /cygdrive/c,c:,$(CUR_APP_PATH)/linker/$(APP_NAME).ld)
-else
-$(error Only GCC ARM is supported at this moment)
-endif
-
-ASM_FILES_APP :=
-ASM_FILES_APP += $(ASM_FILES_STARTUP)
-
-# We still need this for MCUBoot apps signing
-IMGTOOL_PATH ?= ../../scripts/imgtool.py
-
-# add flag to imgtool if not using swap for upgrade
-ifeq ($(SWAP_UPGRADE), 0)
-UPGRADE_TYPE := --overwrite-only
-endif
-
-SIGN_ARGS := sign --header-size 1024 --pad-header --align 8 -v "2.0" -S $(SLOT_SIZE) -M 512 $(UPGRADE_TYPE) -R $(ERASED_VALUE) -k keys/$(SIGN_KEY_FILE).pem
-
+# TODO: optimize here and in MCUBootApp.mk
# Output folder
OUT := $(APP_NAME)/out
# Output folder to contain build artifacts
@@ -122,25 +54,201 @@
OUT_CFG := $(OUT_TARGET)/$(BUILDCFG)
+BOOTLOADER_SIZE ?= $(PLATFORM_BOOTLOADER_SIZE)
+
# Set build directory for BOOT and UPGRADE images
ifeq ($(IMG_TYPE), UPGRADE)
- ifeq ($(ENC_IMG), 1)
- SIGN_ARGS += --encrypt ../../$(ENC_KEY_FILE).pem
- SIGN_ARGS += --use-random-iv
- endif
- SIGN_ARGS += --pad
- UPGRADE_SUFFIX :=_upgrade
OUT_CFG := $(OUT_CFG)/upgrade
else
OUT_CFG := $(OUT_CFG)/boot
endif
+# Set parameters needed for signing
+ifeq ($(IMG_TYPE), UPGRADE)
+ UPGRADE_SUFFIX :=_upgrade
+endif
+
+include $(PRJ_DIR)/platforms.mk
+include $(PRJ_DIR)/common_libs.mk
+include $(PRJ_DIR)/toolchains.mk
+
+# use USE_OVERWRITE = 1 for overwrite only mode
+# use USE_OVERWRITE = 0 for swap upgrade mode
+ifeq ($(USE_OVERWRITE), )
+USE_OVERWRITE ?= $(PLATFORM_DEFAULT_USE_OVERWRITE)
+endif
+
+# possible values are 0 and 0xff
+# internal Flash by default
+ifeq ($(ERASED_VALUE), )
+ERASED_VALUE ?= $(PLATFORM_DEFAULT_ERASED_VALUE)
+endif
+
+# Application-specific DEFINES
+ifeq ($(IMG_TYPE), BOOT)
+ DEFINES_APP := -DBOOT_IMAGE
+ ENC_IMG := 0
+else
+ DEFINES_APP := -DUPGRADE_IMAGE
+ DEFINES_APP += -DSWAP_DISABLED=$(USE_OVERWRITE)
+endif
+
+# Inherit platform default values for application start
+# if not set directly as make command argument
+# App start may vary, depending on mode of operation
+# for example in XIP mode image start adress and app start
+# address may be different
+USER_APP_START ?= $(PLATFORM_USER_APP_START)
+
+ifeq ($(USER_APP_RAM_START), )
+USER_APP_RAM_START ?= $(PLATFORM_DEFAULT_RAM_START)
+endif
+ifeq ($(USER_APP_RAM_SIZE), )
+USER_APP_RAM_SIZE ?= $(PLATFORM_DEFAULT_RAM_SIZE)
+endif
+
+DEFINES_APP += -DUSER_APP_RAM_START=$(USER_APP_RAM_START)
+DEFINES_APP += -DUSER_APP_RAM_SIZE=$(USER_APP_RAM_SIZE)
+DEFINES_APP += -DUSER_APP_START=$(USER_APP_START)
+DEFINES_APP += -DPRIMARY_IMG_START=$(PRIMARY_IMG_START)
+DEFINES_APP += -DUSER_APP_SIZE=$(SLOT_SIZE)
+DEFINES_APP += $(PLATFORM_DEFINES_APP)
+
+ifeq ($(USE_XIP), 1)
+DEFINES_APP += -DUSE_XIP
+LD_SUFFIX = _xip
+endif
+
+# Add version metadata to image
+ifneq ($(IMG_VER), )
+IMG_VER_ARG = -v "$(IMG_VER)"
+else
+IMG_VER_ARG = $(PLATFORM_DEFAULT_IMG_VER_ARG)
+$(info WARNING - setting platform default version number, to set custom value - pass IMG_VER=x.x.x argument to make command)
+endif
+
+# Add dependencies metadata to image
+ifneq ($(IMG_DEPS_ID), )
+ifneq ($(IMG_DEPS_VER), )
+IMG_DEPS_ARG = -d "($(IMG_DEPS_ID), $(IMG_DEPS_VER))"
+endif
+endif
+
+# Collect Test Application sources
+SOURCES_APP_SRC := $(wildcard $(CUR_APP_PATH)/*.c)
+
+# Include confirmation flag setting (img_ok) implementation
+ifeq ($(IMG_TYPE), UPGRADE)
+ifeq ($(USE_OVERWRITE), 0)
+SOURCES_APP_SRC += $(PRJ_DIR)/platforms/$(FAMILY)/img_confirm/set_img_ok.c
+endif
+endif
+
+# Set offset for secondary image
+ifeq ($(IMG_TYPE), UPGRADE)
+HEADER_OFFSET := $(SECONDARY_IMG_START)
+else
+HEADER_OFFSET := $(PRIMARY_IMG_START)
+endif
+
+# Collect all the sources
+SOURCES_APP += $(SOURCES_APP_SRC)
+SOURCES_APP += $(PLATFORM_SOURCES_FLASH)
+
+# Collect includes for BlinkyApp
+INCLUDE_DIRS_APP := $(addprefix -I, $(CURDIR))
+INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH))
+INCLUDE_DIRS_APP += $(addprefix -I, $(PLATFORM_INCLUDE_DIRS_FLASH))
+
+# ++++
+INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/MCUBootApp/config)
+INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/MCUBootApp)
+INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/../bootutil/include)
+INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/../bootutil/src)
+INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/../bootutil/include/bootutil)
+# +++
+
+# Overwite path to linker script if custom is required, otherwise default from BSP is used
+ifeq ($(COMPILER), GCC_ARM)
+LINKER_SCRIPT := $(CUR_APP_PATH)/linker/$(APP_NAME).ld
+else
+$(error Only GCC ARM is supported at this moment)
+endif
+
+ASM_FILES_APP :=
+ASM_FILES_APP += $(ASM_FILES_STARTUP)
+
+# add flag to imgtool if not using swap for upgrade
+ifeq ($(USE_OVERWRITE), 1)
+UPGRADE_TYPE := --overwrite-only
+endif
+
+SIGN_ARGS := $(PLATFORM_SIGN_ARGS) $(IMG_VER_ARG) $(IMG_DEPS_ARG)
+
+# Set parameters needed for signing
+ifeq ($(IMG_TYPE), UPGRADE)
+ # Set img_ok flag to trigger swap type permanent
+ ifeq ($(CONFIRM), 1)
+ SIGN_ARGS += --confirm
+ endif
+ SIGN_ARGS += --pad
+endif
+
+$(info $(SIGN_ARGS))
+
pre_build:
$(info [PRE_BUILD] - Generating linker script for application $(CUR_APP_PATH)/linker/$(APP_NAME).ld)
- @$(CC) -E -x c $(CFLAGS) $(INCLUDE_DIRS) $(CUR_APP_PATH)/linker/$(APP_NAME)_template.ld | grep -v '^#' >$(CUR_APP_PATH)/linker/$(APP_NAME).ld
+ @$(CC) -E -x c $(CFLAGS) $(INCLUDE_DIRS) $(CUR_APP_PATH)/linker/$(APP_NAME)_$(CORE)_template$(LD_SUFFIX).ld | grep -v '^#' >$(CUR_APP_PATH)/linker/$(APP_NAME).ld
-# Post build action to execute after main build job
-post_build: $(OUT_CFG)/$(APP_NAME).hex
- $(info [POST_BUILD] - Executing post build script for $(APP_NAME))
- mv -f $(OUT_CFG)/$(APP_NAME).hex $(OUT_CFG)/$(APP_NAME)_unsigned.hex
- $(PYTHON_PATH) $(IMGTOOL_PATH) $(SIGN_ARGS) $(OUT_CFG)/$(APP_NAME)_unsigned.hex $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### BlinkyApp.mk ####)
+$(info APP_NAME <-- $(APP_NAME))
+$(info ASM_FILES_APP <-> $(ASM_FILES_APP))
+$(info ASM_FILES_STARTUP <-- $(ASM_FILES_STARTUP))
+$(info BUILDCFG <-- $(BUILDCFG))
+$(info CC <-- $(CC))
+$(info CFLAGS <-- $(CFLAGS))
+$(info COMPILER <-> $(COMPILER))
+$(info CONFIRM <-- $(CONFIRM))
+$(info CORE <-- $(CORE))
+$(info CURDIR <-- $(CURDIR))
+$(info CUR_APP_PATH <-- $(CUR_APP_PATH))
+$(info DEFINES_APP <-> $(DEFINES_APP))
+$(info ENC_IMG --> $(ENC_IMG))
+$(info ERASED_VALUE <-> $(ERASED_VALUE))
+$(info IMG_TYPE <-> $(IMG_TYPE))
+$(info INCLUDE_DIRS <-- $(INCLUDE_DIRS))
+$(info INCLUDE_DIRS_APP <-> $(INCLUDE_DIRS_APP))
+$(info LINKER_SCRIPT <-> $(LINKER_SCRIPT))
+$(info OUT <-> $(OUT))
+$(info OUT_CFG <-> $(OUT_CFG))
+$(info OUT_TARGET <-> $(OUT_TARGET))
+$(info PLATFORM <-- $(PLATFORM))
+$(info PLATFORM_DEFAULT_ERASED_VALUE <-- $(PLATFORM_DEFAULT_ERASED_VALUE))
+$(info PLATFORM_DEFAULT_RAM_SIZE <-- $(PLATFORM_DEFAULT_RAM_SIZE))
+$(info PLATFORM_DEFAULT_RAM_START <-- $(PLATFORM_DEFAULT_RAM_START))
+$(info PLATFORM_DEFAULT_SLOT_SIZE <-- $(PLATFORM_DEFAULT_SLOT_SIZE))
+$(info PLATFORM_DEFAULT_USER_APP_START <-- $(PLATFORM_DEFAULT_USER_APP_START))
+$(info PLATFORM_DEFAULT_PRIMARY_IMG_START <-- $(PLATFORM_DEFAULT_PRIMARY_IMG_START))
+$(info PLATFORM_DEFAULT_USE_OVERWRITE <-- $(PLATFORM_DEFAULT_USE_OVERWRITE))
+$(info PLATFORM_DEFINES_APP <-- $(PLATFORM_DEFINES_APP))
+$(info PLATFORM_INCLUDE_DIRS_FLASH <-- $(PLATFORM_INCLUDE_DIRS_FLASH))
+$(info PLATFORM_SIGN_ARGS <-- $(PLATFORM_SIGN_ARGS))
+$(info PLATFORM_SOURCES_FLASH <-- $(PLATFORM_SOURCES_FLASH))
+$(info PRJ_DIR <-- $(PRJ_DIR))
+$(info IMG_VER_ARG <-- $(IMG_VER_ARG))
+$(info IMG_DEPS_ARG <-- $(IMG_DEPS_ARG))
+$(info SIGN_ARGS <-> $(SIGN_ARGS))
+$(info SLOT_SIZE <-> $(SLOT_SIZE))
+$(info SOURCES_APP <-> $(SOURCES_APP))
+$(info SOURCES_APP_SRC <-> $(SOURCES_APP_SRC))
+$(info UPGRADE_SUFFIX --> $(UPGRADE_SUFFIX))
+$(info UPGRADE_TYPE --> $(UPGRADE_TYPE))
+$(info USER_APP_RAM_SIZE <-> $(USER_APP_RAM_SIZE))
+$(info USER_APP_RAM_START <-> $(USER_APP_RAM_START))
+$(info USER_APP_START <-> $(USER_APP_START))
+$(info PRIMARY_IMG_START <-> $(PRIMARY_IMG_START))
+$(info USE_OVERWRITE <-> $(USE_OVERWRITE))
+endif
diff --git a/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug.launch b/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug.launch
deleted file mode 100644
index 34a173b..0000000
--- a/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug.launch
+++ /dev/null
@@ -1,62 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${cy_tools_path:openocd}/bin/openocd"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s "${cy_tools_path:openocd}/scripts" -s "${workspace_loc}/BlinkyLED_config/GeneratedSource" -c "source [find interface/kitprog3.cfg]" -c "source [find target/psoc6_2m.cfg]" -c "gdb_port 3332" -c "puts stderr {Started by GNU MCU Eclipse}" -c "init; reset init""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="/Users/rnok/repos/cy_mcuboot_project/cy_mcuboot/boot/cypress/BlinkyApp/out/boot/CY8CKIT-064S2-4343W/Debug/BlinkyApp.elf"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="false"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="/Users/rnok/repos/cy_mcuboot_project/cy_mcuboot/boot/cypress/BlinkyApp/out/CY8CKIT-064S2-4343W/Debug/boot/BlinkyApp.elf"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_sdk_install_dir}/tools/gcc-7.2.1-1.0/bin/arm-none-eabi-gdb${cy_exe_platform_ext}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="boot/cypress/BlinkyApp/out/PSOC_062_2M/Debug/boot/BlinkyApp.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="cy_mcuboot"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.1139973781"/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/cy_mcuboot"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"> <memoryBlockExpression address="268566528" label="0x10020000"/> <memoryBlockExpression address="268632064" label="0x10030000"/> </memoryBlockExpressionList> "/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/boot/cypress/BlinkyApp/libs.mk b/boot/cypress/BlinkyApp/libs.mk
index 6e1ba7a..08fc130 100644
--- a/boot/cypress/BlinkyApp/libs.mk
+++ b/boot/cypress/BlinkyApp/libs.mk
@@ -31,31 +31,59 @@
CUR_LIBS_PATH = $(PRJ_DIR)/libs
# Collect source files for Retarget-io
+ifneq ($(PLATFORM), CYW20829)
SOURCES_RETARGET_IO := $(wildcard $(CUR_LIBS_PATH)/retarget-io/*.c)
+endif
SOURCES_WATCHDOG := $(wildcard $(CUR_LIBS_PATH)/watchdog/*.c)
# Collect source files for HAL
-SOURCES_HAL := $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/*.c)
-SOURCES_HAL += $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/triggers/*.c)
-SOURCES_HAL += $(wildcard $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/pin_packages/*.c)
+ifneq ($(PLATFORM), CYW20829)
+SOURCES_HAL_BLINKY := $(wildcard $(CUR_LIBS_PATH)/mtb-hal-cat1/source/*.c)
+SOURCES_HAL_BLINKY += $(wildcard $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/*.c)
+SOURCES_HAL_BLINKY += $(wildcard $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/*.c)
+endif
# Retarget-io related include directories
INCLUDE_DIRS_RETARGET_IO := $(CUR_LIBS_PATH)/retarget-io
INCLUDE_DIRS_WATCHDOG := $(CUR_LIBS_PATH)/watchdog
# Collect dirrectories containing headers for PSOC6 HAL
-INCLUDE_DIRS_HAL := $(CUR_LIBS_PATH)/psoc6hal/include
-INCLUDE_DIRS_HAL += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include
-INCLUDE_DIRS_HAL += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include/pin_packages
-INCLUDE_DIRS_HAL += $(CUR_LIBS_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include/triggers
+ifneq ($(PLATFORM), CYW20829)
+INCLUDE_DIRS_HAL_BLINKY := $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A
+INCLUDE_DIRS_HAL_BLINKY := $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include
+INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/include
+INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/include_pvt
+INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages
+INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/triggers
+endif
# Collected source files for libraries
-SOURCES_LIBS += $(SOURCES_RETARGET_IO)
SOURCES_LIBS += $(SOURCES_WATCHDOG)
-SOURCES_LIBS += $(SOURCES_HAL)
+ifneq ($(PLATFORM), CYW20829)
+SOURCES_LIBS += $(SOURCES_RETARGET_IO)
+SOURCES_LIBS += $(SOURCES_HAL_BLINKY)
+endif
# Collected include directories for libraries
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_WATCHDOG))
+ifneq ($(PLATFORM), CYW20829)
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_RETARGET_IO))
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_WATCHDOG))
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL))
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_WATCHDOG))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL_BLINKY))
+endif
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### libs.mk ####)
+$(info CUR_LIBS_PATH <-- $(CUR_LIBS_PATH))
+$(info INCLUDE_DIRS_HAL_BLINKY <-> $(INCLUDE_DIRS_HAL_BLINKY))
+$(info INCLUDE_DIRS_LIBS --> $(INCLUDE_DIRS_LIBS))
+$(info INCLUDE_DIRS_RETARGET_IO <-> $(INCLUDE_DIRS_RETARGET_IO))
+$(info INCLUDE_DIRS_WATCHDOG <-> $(INCLUDE_DIRS_WATCHDOG))
+$(info PLATFORM <-- $(PLATFORM))
+$(info PRJ_DIR <-- $(PRJ_DIR))
+$(info SOURCES_HAL_BLINKY <-> $(SOURCES_HAL_BLINKY))
+$(info SOURCES_LIBS --> $(SOURCES_LIBS))
+$(info SOURCES_RETARGET_IO <-> $(SOURCES_RETARGET_IO))
+$(info SOURCES_WATCHDOG <-> $(SOURCES_WATCHDOG))
+endif
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld
new file mode 100644
index 0000000..bf7ea08
--- /dev/null
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld
@@ -0,0 +1,503 @@
+/***************************************************************************//**
+* \file cyw20829_ns.ld
+* \version 1.0.0
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+GROUP(-lgcc -lc -lnosys )
+SEARCH_DIR(.)
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM4 SRAM */
+STACK_SIZE = 0x1000;
+
+USER_APP_START_ADDR = 0x400 + USER_APP_START_OFF;
+
+FLASH_START_ADDR_SAHB = 0x60000000 + USER_APP_START_ADDR;
+FLASH_START_ADDR_CBUS = 0x08000000 + USER_APP_START_ADDR;
+RAM_START_ADDR_SAHB = 0x20000000;
+RAM_START_ADDR_CBUS = 0x04000000;
+RAM_END_ADDR_SAHB = 0x20020000; /* 128K */
+RAM_END_ADDR_CBUS = 0x04020000; /* 128K */
+FLASH_END_ADDR_SAHB = 0x60080000; /* 512K */
+
+BOOTSTRAP_OFFSET_FLASH = 0x00000050; /* toc2=0x10, l1_desc=0x1C, sign_header=0x20, padding=0x4 (encrypted data should be aligned to 0x10 boundary) */
+BOOTSTRAP_OFFSET_RAM = 0x0001E000; /* was 0x00004000 Modify this value to change the size of Bootstrap code + Data */
+APPCODE_OFFSET_FLASH = 0x00002200;
+
+RAMVECTORS_ALIGNMENT = 512;
+
+/* Memory reserved for Bootstrap code and data */
+BOOTSTRAP_SIZE = RAM_END_ADDR_SAHB - RAM_START_ADDR_SAHB - BOOTSTRAP_OFFSET_RAM; /* 0x00002000 */
+/* vma for bootstrap code region */
+CODE_VMA = RAM_START_ADDR_CBUS + BOOTSTRAP_OFFSET_RAM; /* 0x0401E000 */
+/* lma for bootstrap code region */
+CODE_LMA = FLASH_START_ADDR_SAHB + BOOTSTRAP_OFFSET_FLASH; /* 0x6000004C */
+/* Maximum bootstrap code + data size */
+CODE_BS_SIZE = BOOTSTRAP_SIZE; /* 8KB */
+/* vma for bootstrap data region */
+DATA_BS_VMA = RAM_START_ADDR_SAHB + BOOTSTRAP_OFFSET_RAM; /* 0x2001E000 */
+/* vma for bootstrap and app data region */
+DATA_VMA = RAM_START_ADDR_SAHB; /* 0x20000000 */
+/* vma for appCodeRam region */
+DATA_CBUS_VMA = RAM_START_ADDR_CBUS; /* 0x04000000 */
+/* lma for bootstrap and app data region */
+DATA_LMA = CODE_LMA + CODE_BS_SIZE; /* 0x6000204C */
+/* data size */
+DATA_SIZE = RAM_END_ADDR_SAHB - DATA_VMA - BOOTSTRAP_SIZE; /* 0x1E000 */
+/* vma for application XIP region */
+XIP_VMA = FLASH_START_ADDR_CBUS + APPCODE_OFFSET_FLASH; /* 0x08002200 */
+/* lma for application XIP region */
+XIP_LMA = FLASH_START_ADDR_SAHB + APPCODE_OFFSET_FLASH; /* 0x60002200 */
+/* size of XIP region */
+XIP_SIZE = FLASH_END_ADDR_SAHB - XIP_LMA;
+/* Total size of SRAM */
+RAM_SIZE = RAM_END_ADDR_SAHB - RAM_START_ADDR_SAHB; /* 0x00020000 */
+/* Size of Bootstrap data is kept same as BOOTSTRAP_SIZE */
+DATA_BS_SIZE = BOOTSTRAP_SIZE;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM33 core.
+ */
+ code (rx) : ORIGIN = CODE_VMA, LENGTH = CODE_BS_SIZE
+ bsData (rwx) : ORIGIN = DATA_BS_VMA, LENGTH = DATA_BS_SIZE
+ appCodeRam (rx) : ORIGIN = DATA_CBUS_VMA, LENGTH = DATA_SIZE
+ data (rwx) : ORIGIN = DATA_VMA, LENGTH = DATA_SIZE
+ xip (rx) : ORIGIN = XIP_VMA, LENGTH = XIP_SIZE
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+SECTIONS
+{
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy RAM_START_ADDR_SAHB (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > data
+
+ /* Set stack top beginning of RAM minus the size of stack, and stack limit move down by
+ * size of stack_dummy section */
+ . = ALIGN(32);
+ __StackTop = RAM_START_ADDR_SAHB + STACK_SIZE;
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ . = ALIGN(RAMVECTORS_ALIGNMENT);
+ __ramVectors_vma__ = RAM_START_ADDR_SAHB + STACK_SIZE;
+
+ .ramVectors __ramVectors_vma__ (NOLOAD):
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ . = ALIGN(4);
+ __ram_vectors_end__ = .;
+ } > data
+
+ __appTextRam_vma__ = (__ram_vectors_end__ - RAM_START_ADDR_SAHB) + RAM_START_ADDR_CBUS;
+ __appTextRam_lma__ = (__zero_table_end__ - FLASH_START_ADDR_CBUS) + FLASH_START_ADDR_SAHB;
+ __ezerotable = __zero_table_end__;
+
+ .appTextRam __appTextRam_vma__ : AT (__appTextRam_lma__)
+ {
+ . = ALIGN(4);
+ __app_text_ram_begin__ = .;
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ *cy_smif.o(.text*)
+ *cy_smif_memslot.o(.text*)
+ *cy_smif_sfdp.o(.text*)
+ *cy_gpio.o(.text*)
+ *cy_smif_hybrid_sect.o(.text*)
+
+ . = ALIGN(4);
+ __app_text_ram_end__ = .;
+
+ } > appCodeRam
+
+ __data_vma__ = (__app_text_ram_end__ - RAM_START_ADDR_CBUS) + RAM_START_ADDR_SAHB;
+ __data_lma__ = (__app_text_ram_end__ - __app_text_ram_begin__) + __appTextRam_lma__;
+ __etext = __data_lma__ - FLASH_START_ADDR_SAHB + FLASH_START_ADDR_CBUS;
+
+ .data __data_vma__ : AT (__data_lma__)
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ . = ALIGN(4);
+ KEEP(*(.cy_l2func*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > data
+
+ /* Check if data is exceeding the flash size */
+ ASSERT((__data_lma__ + (__data_end__ - __data_start__)) <= FLASH_END_ADDR_SAHB, "data section exceeds Flash size !")
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > data
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > data
+
+ /* Use ramining RAM for Heap */
+ __heap_size__ = (RAM_SIZE - ((__bss_end__ - RAM_START_ADDR_SAHB) + (RAM_END_ADDR_CBUS - __bootstrapText_vma__)) - 4);
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ __end1__ = .;
+ end = __end1__;
+ KEEP(*(.heap*))
+ . += __heap_size__;
+ __HeapLimit = .;
+ } > data
+
+ __bootstrapText_vma__ = ORIGIN(code);
+ __bootstrapText_lma__ = CODE_LMA;
+
+ /* Cortex-M33 bootstrap code area */
+ .bootstrapText __bootstrapText_vma__ : AT (__bootstrapText_lma__)
+ {
+ /* Cortex-M33 code vector table */
+ . = ALIGN(4);
+ __bootstrapText_begin = .;
+
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+
+ /* startup code */
+ *ns_start_cyw20829.o(.text*)
+ *ns_system_cyw20829.o(.text*)
+
+ /* drivers */
+ *cy_device.o(.text*)
+ *cy_btss.o(.text*)
+ *cy_gpio.o(.text*)
+ *cy_sysclk_v2.o(.text*)
+ *cy_syspm_v2.o(.text*)
+ *cy_sysint_v2.o(.text*)
+ *cy_syslib*.o(.text*)
+ *ppu_v1.o(.text*)
+ *cy_mpc.o(.text*)
+ *cy_pd_ppu.o(.text*)
+ *cy_smif.o(.text*)
+ *cy_smif_memslot.o(.text*)
+ *cy_smif_sfdp.o(.text*)
+ *cyhal_system.o(.text*)
+
+ KEEP(*(.cy_l1func*))
+
+ . = ALIGN(4);
+ __bootstrapText_end = .;
+ } > code
+
+ __bootstrap_zerotable_lma__ = (CODE_LMA + (__bootstrapText_end - __bootstrapText_begin));
+
+ .bootstrapzero.table : AT (__bootstrap_zerotable_lma__)
+ {
+ . = ALIGN(4);
+ __bootstrapzero_table_start__ = .;
+ LONG (__bootstrap_bss_start__)
+ LONG ((__bootstrap_bss_end__ - __bootstrap_bss_start__)/4)
+ . = ALIGN(4);
+ __bootstrapzero_table_end__ = .;
+ } > code
+
+ __bootstrapData_vma__ = ((__bootstrapzero_table_end__ - RAM_START_ADDR_CBUS) + RAM_START_ADDR_SAHB);
+ __bootstrapData_lma__ = (__bootstrap_zerotable_lma__ + (__bootstrapzero_table_end__ - __bootstrapzero_table_start__));
+
+ .bootstrapData __bootstrapData_vma__ : AT (__bootstrapData_lma__)
+ {
+ __bootstrapData_start__ = .;
+ . = ALIGN(4);
+
+ /* startup code */
+ *ns_start_cyw20829.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *ns_system_cyw20829.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ /* drivers */
+ *cy_device.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_btss.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_gpio.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_sysclk_v2.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_syspm_v2.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_sysint_v2.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_syslib.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *ppu_v1.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_mpc.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_pd_ppu.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_smif.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_smif_memslot.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_smif_sfdp.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cycfg_qspi_memslot.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cyhal_system.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.cy_l1data*))
+
+ . = ALIGN(4);
+
+ __bootstrapData_end__ = .;
+ __bootstrap_size_end__ = .;
+ } > bsData
+
+ .bootstrapBss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bootstrap_bss_start__ = .;
+
+ /* startup code */
+ *ns_start_cyw20829.o(.bss* COMMON)
+ *ns_system_cyw20829.o(.bss* COMMON)
+
+ /* drivers */
+ *cy_device.o(.bss* COMMON)
+ *cy_btss.o(.bss* COMMON)
+ *cy_gpio.o(.bss* COMMON)
+ *cy_sysclk_v2.o(.bss* COMMON)
+ *cy_syspm_v2.o(.bss* COMMON)
+ *cy_sysint_v2.o(.bss* COMMON)
+ *cy_syslib.o(.bss* COMMON)
+ *ppu_v1.o(.bss* COMMON)
+ *cy_mpc.o(.bss* COMMON)
+ *cy_pd_ppu.o(.bss* COMMON)
+ *cy_smif.o(.bss* COMMON)
+ *cy_smif_memslot.o(.bss* COMMON)
+ *cy_smif_sfdp.o(.bss* COMMON)
+
+ KEEP(*(.cy_l1bss*))
+
+ . = ALIGN(4);
+ __bootstrap_bss_end__ = .;
+ } > bsData
+
+ /* Check if bootstrap code + data exceeds RAM limit */
+ ASSERT(__bootstrap_bss_end__ < RAM_END_ADDR_SAHB, "bootstrap region exceeds RAM size !")
+
+ __app_text_vma__ = ORIGIN(xip);
+ __app_text_lma__ = XIP_LMA;
+
+ /* Cortex-M33 application flash area */
+ .appText (__app_text_vma__) : AT (__app_text_lma__)
+ {
+ /* Cortex-M33 flash vector table */
+ . = ALIGN(4);
+ __text_begin = .;
+
+ *(EXCLUDE_FILE(*cy_gpio.o
+ *cy_smif.o
+ *cy_smif_memslot.o
+ *cy_smif_sfdp.o
+ *cy_smif_hybrid_sect.o) .text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ . = ALIGN(4);
+ __text_end = .;
+
+ } > xip
+
+
+ .copy.table : AT (__app_text_lma__ + (__text_end - __text_begin))
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG ((__data_end__ - __data_start__)/4) /* Size */
+
+ /* Copy appTextRam section to RAM */
+ LONG (__ezerotable) /* From */
+ LONG (__ram_vectors_end__) /* To */
+ LONG ((__app_text_ram_end__ - __app_text_ram_begin__)/4) /* Size */
+
+ . = ALIGN(4);
+ __copy_table_end__ = .;
+ } > xip
+
+
+
+ .ARM.extab : AT (__app_text_lma__ + (__text_end - __text_begin) + (__copy_table_end__ - __copy_table_start__))
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > xip
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > xip
+ __exidx_end = .;
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in CAT1B devices */
+ .zero.table : AT (__exidx_end - __app_text_vma__ + __app_text_lma__)
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG ((__bss_end__ - __bss_start__)/4)
+
+ . = ALIGN(4);
+ __zero_table_end__ = .;
+ } > xip
+}
+
+/* start of bootstrap code sahb address */
+__bootstrap_start_addr__ = RAM_START_ADDR_SAHB + BOOTSTRAP_OFFSET_RAM;
+/* bootstrap size */
+__bootstrap_size__ = __bootstrap_size_end__ - __bootstrap_start_addr__;
+
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template.ld
similarity index 76%
rename from boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld
rename to boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template.ld
index 81fbc22..4324012 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template.ld
@@ -1,6 +1,6 @@
/***************************************************************************//**
-* \file cy8c6xxa_cm4_dual.ld
-* \version 2.60
+* \file cyb06xxa_cm4.ld
+* \version 2.91
*
* Linker file for the GNU C compiler.
*
@@ -8,7 +8,7 @@
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
-* \note The entry point location is fixed and starts at 0x10000000. The valid
+* \note The entry point location is fixed and starts at 0x100E0000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -61,13 +61,8 @@
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing the 'ram' and 'flash' regions.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
- ram (rwx) : ORIGIN = RAM_START, LENGTH = RAM_SIZE
+ ram (rwx) : ORIGIN = USER_APP_RAM_START, LENGTH = USER_APP_RAM_SIZE
flash (rx) : ORIGIN = USER_APP_START, LENGTH = USER_APP_SIZE
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
@@ -78,13 +73,7 @@
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
- sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
- sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
- sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
- sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
- sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
- efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
@@ -129,6 +118,7 @@
/* Cortex-M4 application flash area */
.text ORIGIN(flash) + BOOT_HEADER_SIZE :
{
+ /* Cortex-M4 flash vector table */
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
@@ -223,8 +213,9 @@
} > ram
- .data __ram_vectors_end__ : AT (__etext)
+ .data __ram_vectors_end__ :
{
+ . = ALIGN(4);
__data_start__ = .;
*(vtable)
@@ -258,7 +249,7 @@
__data_end__ = .;
- } > ram
+ } > ram AT>flash
/* Place variables in the section that should not be initialized during the
@@ -338,88 +329,18 @@
} > em_eeprom
- /* Supervisory Flash: User data */
- .cy_sflash_user_data :
- {
- KEEP(*(.cy_sflash_user_data))
- } > sflash_user_data
-
-
- /* Supervisory Flash: Normal Access Restrictions (NAR) */
- .cy_sflash_nar :
- {
- KEEP(*(.cy_sflash_nar))
- } > sflash_nar
-
-
- /* Supervisory Flash: Public Key */
- .cy_sflash_public_key :
- {
- KEEP(*(.cy_sflash_public_key))
- } > sflash_public_key
-
-
- /* Supervisory Flash: Table of Content # 2 */
- .cy_toc_part2 :
- {
- KEEP(*(.cy_toc_part2))
- } > sflash_toc_2
-
-
- /* Supervisory Flash: Table of Content # 2 Copy */
- .cy_rtoc_part2 :
- {
- KEEP(*(.cy_rtoc_part2))
- } > sflash_rtoc_2
-
-
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
- .cy_xip :
+ cy_xip :
{
+ __cy_xip_start = .;
KEEP(*(.cy_xip))
+ __cy_xip_end = .;
} > xip
- /* eFuse */
- .cy_efuse :
- {
- KEEP(*(.cy_efuse))
- } > efuse
-
-
- /* These sections are used for additional metadata (silicon revision,
- * Silicon/JTAG ID, etc.) storage.
- */
- .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-__cy_memory_0_start = 0x10000000;
-__cy_memory_0_length = 0x00200000;
-__cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-__cy_memory_1_start = 0x14000000;
-__cy_memory_1_length = 0x8000;
-__cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-__cy_memory_2_start = 0x16000000;
-__cy_memory_2_length = 0x8000;
-__cy_memory_2_row_size = 0x200;
-
-/* XIP */
-__cy_memory_3_start = 0x18000000;
-__cy_memory_3_length = 0x08000000;
-__cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-__cy_memory_4_start = 0x90700000;
-__cy_memory_4_length = 0x100000;
-__cy_memory_4_row_size = 1;
-
/* EOF */
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
similarity index 75%
copy from boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld
copy to boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
index 81fbc22..55b307a 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_template.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
@@ -1,6 +1,6 @@
/***************************************************************************//**
-* \file cy8c6xxa_cm4_dual.ld
-* \version 2.60
+* \file BlinkyApp.ld
+* \version 2.91
*
* Linker file for the GNU C compiler.
*
@@ -8,7 +8,7 @@
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
-* \note The entry point location is fixed and starts at 0x10000000. The valid
+* \note The entry point location is fixed and starts at 0x100E0000. The valid
* application image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
@@ -19,7 +19,8 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* Copyright 2022 Infineon Technologies AG
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -43,7 +44,6 @@
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = 0x1000;
-
/* The size of the MCU boot header area at the start of FLASH */
BOOT_HEADER_SIZE = 0x400;
@@ -61,15 +61,11 @@
MEMORY
{
/* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
- * You can change the memory allocation by editing the 'ram' and 'flash' regions.
- * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
- * Using this memory region for other purposes will lead to unexpected behavior.
- * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
- * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
*/
- ram (rwx) : ORIGIN = RAM_START, LENGTH = RAM_SIZE
+ ram (rwx) : ORIGIN = USER_APP_RAM_START, LENGTH = USER_APP_RAM_SIZE
flash (rx) : ORIGIN = USER_APP_START, LENGTH = USER_APP_SIZE
+ public_ram (rw) : ORIGIN = 0x08000000, LENGTH = 0x800
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
@@ -78,13 +74,7 @@
em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
/* The following regions define device specific memory regions and must not be changed. */
- sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
- sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
- sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
- sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
- sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
- efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Library configurations */
@@ -126,9 +116,11 @@
SECTIONS
{
+
/* Cortex-M4 application flash area */
.text ORIGIN(flash) + BOOT_HEADER_SIZE :
{
+ /* Cortex-M4 flash vector table */
. = ALIGN(4);
__Vectors = . ;
KEEP(*(.vectors))
@@ -136,9 +128,11 @@
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
-
. = ALIGN(4);
- *(.text*)
+
+ EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o
+ *cy_sysclk.o *cy_smif_hybrid_sect.o *flash_qspi.o
+ *cy_syslib.o *cy_syslib_gcc.o *system_psoc6_cm4.o) *(.text)
KEEP(*(.init))
KEEP(*(.fini))
@@ -223,8 +217,9 @@
} > ram
- .data __ram_vectors_end__ : AT (__etext)
+ .data __ram_vectors_end__ :
{
+ . = ALIGN(4);
__data_start__ = .;
*(vtable)
@@ -256,9 +251,18 @@
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
+ *cy_smif.o(.text*)
+ *cy_smif_memslot.o(.text*)
+ *cy_smif_sfdp.o(.text*)
+ *cy_sysclk.o(.text*)
+ *cy_smif_hybrid_sect.o(.text*)
+ *flash_qspi.o(.text*)
+ *cy_syslib.o(.text*)
+ *cy_syslib_gcc.o(.text*)
+
__data_end__ = .;
- } > ram
+ } > ram AT>flash
/* Place variables in the section that should not be initialized during the
@@ -303,6 +307,14 @@
__HeapLimit = .;
} > ram
+ .cy_sharedmem (NOLOAD):
+ {
+ . = ALIGN(4);
+ __public_ram_start__ = .;
+ KEEP(*(.cy_sharedmem))
+ . = ALIGN(4);
+ __public_ram_end__ = .;
+ } > public_ram
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
@@ -338,88 +350,18 @@
} > em_eeprom
- /* Supervisory Flash: User data */
- .cy_sflash_user_data :
- {
- KEEP(*(.cy_sflash_user_data))
- } > sflash_user_data
-
-
- /* Supervisory Flash: Normal Access Restrictions (NAR) */
- .cy_sflash_nar :
- {
- KEEP(*(.cy_sflash_nar))
- } > sflash_nar
-
-
- /* Supervisory Flash: Public Key */
- .cy_sflash_public_key :
- {
- KEEP(*(.cy_sflash_public_key))
- } > sflash_public_key
-
-
- /* Supervisory Flash: Table of Content # 2 */
- .cy_toc_part2 :
- {
- KEEP(*(.cy_toc_part2))
- } > sflash_toc_2
-
-
- /* Supervisory Flash: Table of Content # 2 Copy */
- .cy_rtoc_part2 :
- {
- KEEP(*(.cy_rtoc_part2))
- } > sflash_rtoc_2
-
-
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
- .cy_xip :
+ cy_xip :
{
+ __cy_xip_start = .;
KEEP(*(.cy_xip))
+ __cy_xip_end = .;
} > xip
- /* eFuse */
- .cy_efuse :
- {
- KEEP(*(.cy_efuse))
- } > efuse
-
-
- /* These sections are used for additional metadata (silicon revision,
- * Silicon/JTAG ID, etc.) storage.
- */
- .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
}
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-__cy_memory_0_start = 0x10000000;
-__cy_memory_0_length = 0x00200000;
-__cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-__cy_memory_1_start = 0x14000000;
-__cy_memory_1_length = 0x8000;
-__cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-__cy_memory_2_start = 0x16000000;
-__cy_memory_2_length = 0x8000;
-__cy_memory_2_row_size = 0x200;
-
-/* XIP */
-__cy_memory_3_start = 0x18000000;
-__cy_memory_3_length = 0x08000000;
-__cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-__cy_memory_4_start = 0x90700000;
-__cy_memory_4_length = 0x100000;
-__cy_memory_4_row_size = 1;
-
/* EOF */
diff --git a/boot/cypress/BlinkyApp/main.c b/boot/cypress/BlinkyApp/main.c
index 1679bf2..59cee6a 100644
--- a/boot/cypress/BlinkyApp/main.c
+++ b/boot/cypress/BlinkyApp/main.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2021 Infineon Technologies AG
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,21 +22,37 @@
* specific language governing permissions and limitations
* under the License.
*/
- /*******************************************************************************/
+#ifdef CYW20829
+#include <inttypes.h>
+#include "cybsp.h"
+#include "cycfg_pins.h"
+#include "cyhal_wdt.h"
+#else
#include "system_psoc6.h"
+#endif /* CYW20829 */
+
#include "cy_pdl.h"
-#include "cyhal.h"
#include "cy_retarget_io.h"
+#include "cyhal.h"
#include "watchdog.h"
-/* Define pins for UART debug output */
+#include "flash_qspi.h"
+#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
+#include "set_img_ok.h"
+#endif
+
+/* Define pins for UART debug output */
+#ifdef CYW20829
+#define CY_DEBUG_UART_TX (CYBSP_DEBUG_UART_TX)
+#define CY_DEBUG_UART_RX (CYBSP_DEBUG_UART_RX)
+#else
#define CY_DEBUG_UART_TX (P5_1)
#define CY_DEBUG_UART_RX (P5_0)
+#endif /* CYW20829 */
#if defined(PSOC_062_2M)
-#warning "Check if User LED is correct for your target board."
#define LED_PORT GPIO_PRT13
#define LED_PIN 7U
#elif defined(PSOC_062_1M)
@@ -44,12 +61,11 @@
#elif defined(PSOC_062_512K)
#define LED_PORT GPIO_PRT11
#define LED_PIN 1U
+#elif defined(CYW20829)
+#define LED_PORT GPIO_PRT0
+#define LED_PIN 0U
#endif
-#define LED_NUM 5U
-#define LED_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define LED_INIT_DRIVESTATE 1
-
const cy_stc_gpio_pin_config_t LED_config =
{
.outVal = 1,
@@ -67,53 +83,31 @@
.vohSel = 0UL,
};
-#define WATCHDOG_UPD_MESSAGE "[BlinkyApp] Update watchdog timer started in MCUBootApp to mark successful start of user app\r\n"
-#define WATCHDOG_FREE_MESSAGE "[BlinkyApp] Turn off watchdog timer\r\n"
+uint32_t smif_id = 1; /* Assume SlaveSelect_0 is used for External Memory */
-#ifdef BOOT_IMG
+#ifdef BOOT_IMAGE
#define BLINK_PERIOD (1000u)
#define GREETING_MESSAGE_VER "[BlinkyApp] BlinkyApp v1.0 [CM4]\r\n"
#define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 1 sec period\r\n"
-#elif defined(UPGRADE_IMG)
+#elif defined(UPGRADE_IMAGE)
#define BLINK_PERIOD (250u)
#define GREETING_MESSAGE_VER "[BlinkyApp] BlinkyApp v2.0 [+]\r\n"
#define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 0.25 sec period\r\n"
#else
- #error "[BlinkyApp] Please specify type of image: -DBOOT_IMG or -DUPGRADE_IMG\r\n"
+ #error "[BlinkyApp] Please specify type of image: -DBOOT_IMAGE or -DUPGRADE_IMAGE\r\n"
#endif
-void check_result(int res)
+#define WATCHDOG_FREE_MESSAGE "[BlinkyApp] Turn off watchdog timer\r\n"
+
+static void check_result(int res)
{
if (res != CY_RSLT_SUCCESS) {
CY_ASSERT(0);
+ /* Loop forever... */
+ for (;;) {}
}
}
-/*
-* Writes 1 byte `src` into flash memory at `address`
-* It does a sequence of RD/Modify/WR of data in a Flash Row.
- */
-int flash_write_byte(uint32_t address, uint8_t src)
-{
- cy_en_flashdrv_status_t rc = CY_FLASH_DRV_SUCCESS;
- uint32_t row_addr = 0;
- uint8_t row_buff[512];
-
- /* accepting arbitrary address */
- row_addr = (address/CY_FLASH_SIZEOF_ROW)*CY_FLASH_SIZEOF_ROW;
-
- /* preserving Row */
- memcpy(row_buff, (void *)row_addr, sizeof(row_buff));
-
- /* Modifying the target byte */
- row_buff[address%CY_FLASH_SIZEOF_ROW] = src;
-
- /* Programming updated row back */
- rc = Cy_Flash_WriteRow(row_addr, (const uint32_t *)row_buff);
-
- return (int) rc;
-}
-
void test_app_init_hardware(void)
{
/* enable interrupts */
@@ -121,6 +115,7 @@
/* Disabling watchdog so it will not interrupt normal flow later */
Cy_GPIO_Pin_Init(LED_PORT, LED_PIN, &LED_config);
+
/* Initialize retarget-io to use the debug UART port */
check_result(cy_retarget_io_init(CY_DEBUG_UART_TX, CY_DEBUG_UART_RX,
CY_RETARGET_IO_BAUDRATE));
@@ -133,50 +128,63 @@
printf("[BlinkyApp] UART initialized \r\n");
printf("[BlinkyApp] Retarget I/O set to 115200 baudrate \r\n");
+#ifdef CYW20829
+ cy_en_smif_status_t rc = CY_SMIF_CMD_NOT_FOUND;
+
+ rc = qspi_init_sfdp(smif_id);
+ if (CY_SMIF_SUCCESS == rc) {
+ printf("[BlinkyApp] External Memory initialized w/ SFDP. \r\n");
+ }
+ else {
+ printf("[BlinkyApp] External Memory initialization w/ SFDP FAILED: 0x%" PRIx32 " \r\n", (uint32_t)rc);
+ }
+#endif /* CYW20829 */
}
int main(void)
{
uint32_t blinky_period = BLINK_PERIOD;
+#if defined CYW20829
+ cybsp_init();
+#endif /* CYW20829 */
+
test_app_init_hardware();
printf(GREETING_MESSAGE_INFO);
- /* Update watchdog timer to mark successful start up of application */
- printf(WATCHDOG_UPD_MESSAGE);
- cy_wdg_kick();
+ /* Disable watchdog timer to mark successful start up of application.
+ * For PSOC6 WDT is disabled in SystemInit() function.
+ */
printf(WATCHDOG_FREE_MESSAGE);
+#ifdef CYW20829
+ cyhal_wdt_t *cyw20829_wdt = NULL;
+ cyhal_wdt_free(cyw20829_wdt);
+#else
cy_wdg_free();
+#endif /* CYW20829 */
-#if defined(SWAP_ENABLED) && defined(UPGRADE_IMG)
-
- #define USER_SWAP_IMAGE_OK_OFFS (24)
- #define USER_SWAP_IMAGE_OK (1)
- uint32_t img_ok_addr;
- int rc;
+#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
+ int rc = -1;
printf("[BlinkyApp] Try to set img_ok to confirm upgrade image\r\n");
/* Write Image OK flag to the slot trailer, so MCUBoot-loader
- * will not revert new image */
- img_ok_addr = USER_APP_START + USER_APP_SIZE - USER_SWAP_IMAGE_OK_OFFS;
- if (*((uint8_t *)img_ok_addr) != USER_SWAP_IMAGE_OK)
- {
- rc = flash_write_byte(img_ok_addr, USER_SWAP_IMAGE_OK);
- if (0 == rc)
- {
- printf("[BlinkyApp] SWAP Status : Image OK was set at 0x%08lx.\r\n", img_ok_addr);
- }
- else
- {
- printf("[BlinkyApp] SWAP Status : Failed to set Image OK.\r\n");
- }
- } else
- {
+ * will not revert new image
+ */
+ rc = set_img_ok(IMG_OK_ADDR, USER_SWAP_IMAGE_OK);
+
+ if (IMG_OK_ALREADY_SET == rc) {
printf("[BlinkyApp] Img_ok is already set in trailer\r\n");
}
-#endif
+ else if (IMG_OK_SET_SUCCESS == rc) {
+ printf("[BlinkyApp] SWAP Status : Image OK was set at 0x%08x.\r\n", IMG_OK_ADDR);
+ }
+ else {
+ printf("[BlinkyApp] SWAP Status : Failed to set Image OK.\r\n");
+ }
+
+#endif /* !(SWAP_DISABLED) && defined(UPGRADE_IMAGE) */
for (;;)
{
@@ -186,5 +194,6 @@
/* Invert the USER LED state */
Cy_GPIO_Inv(LED_PORT, LED_PIN);
}
+
return 0;
}
diff --git a/boot/cypress/BlinkyApp/set_img_ok.h b/boot/cypress/BlinkyApp/set_img_ok.h
new file mode 100644
index 0000000..68d4ac2
--- /dev/null
+++ b/boot/cypress/BlinkyApp/set_img_ok.h
@@ -0,0 +1,39 @@
+/********************************************************************************
+* Copyright 2021 Infineon Technologies AG
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(SET_IMG_OK_H)
+#define SET_IMG_OK_H
+
+#include "cy_flash.h"
+#include "flash_qspi.h"
+#include "sysflash/sysflash.h"
+#include <string.h>
+
+#define FLASH_ROW_BUF_SZ CY_FLASH_ALIGN
+#define IMG_TRAILER_SZ CY_FLASH_ALIGN
+
+#define USER_SWAP_IMAGE_OK_OFFS (24)
+#define USER_SWAP_IMAGE_OK (1)
+#define IMG_OK_ADDR (PRIMARY_IMG_START + USER_APP_SIZE - USER_SWAP_IMAGE_OK_OFFS)
+
+#define IMG_OK_SET_FAILED -1
+#define IMG_OK_ALREADY_SET 1
+#define IMG_OK_SET_SUCCESS 0
+
+int set_img_ok(uint32_t address, uint8_t value);
+
+#endif /* SET_IMG_OK_H */
\ No newline at end of file
diff --git a/boot/cypress/MCUBootApp/ExternalMemory.md b/boot/cypress/MCUBootApp/ExternalMemory.md
index ce1cb7e..70f862d 100644
--- a/boot/cypress/MCUBootApp/ExternalMemory.md
+++ b/boot/cypress/MCUBootApp/ExternalMemory.md
@@ -1,88 +1,106 @@
-### External Memory Support For Secondary Slot
+### Support of secondary slot in external memory for PSoC™ 6 devices
+
+* For the CYW20829 external memory support, see the [CYW20829.md](../platforms/CYW20829/CYW20829.md) file.
#### Description
-Given document describes the use of external memory module as a secondary (upgrade) slot with Cypress' PSoC 6 devices.
+This document describes the use of the external memory module as a secondary (upgrade) slot with Cypress PSoC™ 6 devices.
-The demonstration device is `CY8CPROTO-062-4343W` board which is PSoC 6 device with 2M of Flash available, but other kits with 1M (CY8CKIT-062-WIFI-BT) or 512K (CY8CPROTO-062S3-4343W) chips can be used as well.
-The memory module present on boards is S25FL512SAGMFI010 512-Mbit external Quad SPI NOR Flash.
+The demonstration device is the `CY8CPROTO-062-4343W` board, which is a PSoC™ 6 device with 2M-flash, but other kits with 1M (CY8CKIT-062-WIFI-BT) or 512K (CY8CPROTO-062S3-4343W) chips can be used as well.
+The memory module on boards is S25FL512SAGMFI010 512-Mbit external Quad SPI NOR flash.
-Using external memory for secondary slot allows to nearly double the size of Boot Image.
+Using external memory for secondary slots allows nearly doubling the Boot Image size.
-#### Operation Design and Flow
+#### Operation design and flow
-The design is based on using SFDP command's auto-discovery functionality of memory module IC and Cypress' SMIF PDL driver.
+The design is based on using the SFDP command's auto-discovery functionality of memory module IC and Cypress SMIF PDL driver.
-It is assumed that user's design meets following:
-* The memory-module used is SFDP-compliant;
-* There only one module is being used for secondary slot;
-* The address for secondary slot should start from 0x18000000.
-This corresponds to PSoC 6's SMIF (Serial Memory InterFace) IP block mapping.
-* The slot size and start address for upgrade slot meets requirements, when using swap upgrade.
+A user's design example:
+* The memory-module is SFDP-compliant.
+* Only one module is used for the secondary slot.
+* The address for the secondary slot starts from 0x18000000.
+This corresponds to PSoC™ 6 SMIF (Serial Memory InterFace) IP block mapping.
+* The slot size and start address for the upgrade slot meet the requirements, when using swap upgrade.
-The default flash map can be foung in MCUBootApp.md.
+The default flash map can be found in the [MCUBootApp.md](MCUBootApp.md) file.
-MCUBootApp's `main.c` contains the call to Init-SFDP API which performs required GPIO configurations, SMIF IP block configurations, SFDP protocol read and memory-config structure initialization.
+MCUBootApp's `main.c` contains the call to Init-SFDP API, which performs the required GPIO configurations, SMIF IP block configuration, SFDP protocol read and memory-config structure initialization.
-After that MCUBootApp is ready to accept upgrade image from external memory module.
+Now, MCUBootApp is ready to accept an upgrade image from the external memory module.
Upgrades from external memory are supported for both `overwrite only` and `swap with status partition` modes of MCUBootApp.
-##### Requirements to size and start address of upgrade slot when using swap mode.
+##### Requirements to size and start address of upgrade slot when using Swap mode
-Due to mcuboot image structure some restrictions applies when using upgrades from external flash. The main requirement is the following:
+Due to the MCUboot image structure, some restrictions apply when using upgrades from external flash. The main requirement:
-**Trailer portion of UPGRADE image should be possible to erase separately.**
+**The trailer portion of an upgrade image can be erased separately.**
-To achive this requirement image trailer should be placed separately on full flash page, which equls 0x40200 in case of S25FL512SAGMFI010. Considering default slot size for external memory case described in MCUBootApp.md, occupied external flash would look as follows:
+To meet this requirement, the image trailer is placed separately on a full flash page, which equals 0x40200 for S25FL512SAGMFI010.
+Considering the default slot size for the external memory case described in the [MCUBootApp.md](MCUBootApp.md) file, occupied external flash looks as follows:
0x18000000 [xxxxxxxxxxxxxxxx][ttfffffffffffff][fffffffffffffff]
Here:
-`0x18000000` - start address of external memory
-`[xxxxxxxxxxxxxxxx]` - first flash page of minimum erase size 0x40000 occupied by firmware.
-`[tt]` - trailer portion (last 0x200 of image) of upgrade slot placed on separate flash page.
-`[fffff]` - remained portion of flash page, used to store image trailer - this area should not be used for anything else.
+`0x18000000` - The start address of external memory.
+`[xxxxxxxxxxxxxxxx]` - The first flash page of minimum erase size 0x40000 occupied by the firmware.
+`[tt]` - The trailer portion (last 0x200 of image) of the upgrade slot placed on a separate flash page.
+`[fffff]` - The remained portion of the flash page, used to store the image trailer - this area cannot be used for anything else.
-When using slots sizes other, then default `0x40200` described above shoulb be considered.
+When using slots sizes other than default, consider the above-described `0x40200`.
-When slot size does not aligned to `0x40000`, start address of UPGRADE image in external flash should be calculated starting from image trailer location. Consider example below.
+When the slot size is not aligned to `0x40200`, the start address of the upgrade image in the external flash is calculated starting from the image trailer location. Consider the following example:
-Primary slot size required is 590336 bytes (576k + 512b).
+The primary slot size required is 590336 bytes (576k + 512b).
-4 flash pages are required to fit secondary slot (P1-P4):
+Four flash pages are required to fit the secondary slot (P1-P4):
0x1800 0000 - 0x1804 0000 - P1
0x1804 0000 - 0x1808 0000 - P2
0x1808 0000 - 0x180C 0000 - P3
0x1808 0000 - 0x180C 0000 - P4
-Primary slot consist of 512 bytes of image trailer, it goes to P4, 2 full sectors of 256k goes in P3 and P2, reminded 64k is resided in P1.
+The primary slot consists of 512 bytes of the image trailer, it goes to P4, 2 full sectors of 256k goes in P3 and P2, the remainder of 64k is resided in P1.
-Thus start address of secondary slot is: 0x1804 0000 - 0x10000 (64k) = 0x1803 0000. Size occupied is 4 * 256k = 786k
+Thus, the start address of the secondary slot is: 0x1804 0000 - 0x10000 (64k) = 0x1803 0000. The size occupied is 4 * 256k = 786k
-##### How to enable external memory support:
+#### Execute in place (XIP) mode
-1. Pass `USE_EXTERNAL_FLASH=1` flag to `make` command when building MCUBootApp.
-2. Navigate to `cy_flash_map.c` and check if secondary slot start address and size meet the application's needs.
-3. Define which slave select is used for external memory on a board by setting `smif_id` value in `main.c`.
-4. Build MCUBootApp as described in `Readme.md`.
+In the XIP mode firmware image can be placed in the external memory and executed from there directly. This mode is useful for devices with small internal flash or when one wishes to reserve internal flash for other purposes.
-**Note 3**: External memory code is developed basing on PDL and can be run on CM0p core only. It may require modifications if used on CM4.
+On CYW20829 platform XIP mode is always used due to absence of internal memory.
-**How to build upgrade image for external memory:**
+This is optional for PSoC™ 6 devices. The JSON flash map should contain `"mode": "XIP"` in the `"external_flash" section`. `USE_XIP` flag is added to auto-generated `flashmap.mk` on pre-build action.
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x7FE8000 ERASED_VALUE=0xff
+When XIP mode is used primary slot of an image can be placed in external memory.
-`HEADER_OFFSET` defines the offset from original boot image address. This one in line above suggests secondary slot will start from `0x18000000`.
+This repository provides default flash map files with suffix _xip_ to be used for XIP mode in `cy_flash_pal/flash_%platform_name%/flashmap`.
-`ERASED_VALUE` defines the memory cell contents in erased state. It is `0x00` for PSoC 6's internal Flash and `0xff` for S25FL512S.
+#### How to enable external memory support
-**Programming to external memory**
+External memory is enabled when `make` flag `USE_EXTERNAL_FLASH` is set to `1`. Value of this flag is set in auto-generated `flashmap.mk` files when field `"external_flash"` is present in JSON file.
-The MCUBootApp programming can be done similarly to described in `Readme.md`:
+Default flash maps with suffix _smif_ are provided in `cy_flash_pal/flash_psoc6/flashmap` folder for PSoC™ 6 devices, where presense of external memory in system is optional.
- export OPENOCD=/Applications/ModusToolbox/tools_2.1/openocd
+Build MCUBootApp as described in the [MCUBootApp.md](MCUBootApp.md) file.
+
+**Building an upgrade image for external memory:**
+
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE ERASED_VALUE=0xff FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single_smif.json IMG_ID=1
+
+`ERASED_VALUE` - Defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S.
+
+**Programming external memory**
+
+Programming tools require configuration of SMIF block to debug/program external memory. When `MCUBootApp` is built with `BUILDCFG=Debug` flag SMIF configuration structures are added to the `MCUBootApp.hex` image. Additional sections:
+
+At SFlash address `0x16000800` address of SMIF configuration structure is placed.
+
+At SFlash address `0x16007c00` updated content of TOC2 structure is placed.
+
+The MCUBootApp can be programmed similarly to described in the [MCUBootApp.md](MCUBootApp.md) file:
+
+ export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
-f ${OPENOCD}/scripts/interface/kitprog3.cfg \
@@ -91,11 +109,11 @@
-c "init; reset init; program PATH_TO_APPLICATION.hex" \
-c "resume; reset; exit"
-There is a NULL-pointer placed for SMIF configuration pointer in TOC2 (Table Of Contents, `cy_serial_flash_prog.c`).
-This is done to force CY8PROTO-062-4343W DAP Link firmware to program external memory with hardcoded values.
+There is a NULL-pointer placed for the SMIF configuration pointer in TOC2 (Table Of Contents, `cy_serial_flash_prog.c`).
+This is done to force the CY8PROTO-062-4343W DAP Link firmware to program external memory with hardcoded values.
-1. Press SW3 Mode button on a board to switch the board into DAP Link mode.
-2. Once DAP Link removable disk appeared drop (copy) the upgrade image HEX file to it.
-This will invoke firmware to program external memory.
+1. Click the SW3 Mode button on the board to switch the board to DAP Link mode.
+2. Once DAP Link removable disk displays, drop (copy) the upgrade image HEX file to it.
+This will invoke the firmware to program external memory.
-**Note 3:** the programming of external memory is limited to S25FL512S p/n only at this moment.
+**Note :** the programming of external memory is limited to S25FL512S p/n only at this moment.
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.md b/boot/cypress/MCUBootApp/MCUBootApp.md
index f4337c7..d15f667 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.md
+++ b/boot/cypress/MCUBootApp/MCUBootApp.md
@@ -1,234 +1,430 @@
-## MCUBootApp - demo bootloading application to be used with Cypress targets
+## MCUBootApp - demo bootloading application to use with Cypress targets
-### Solution Description
+### Solution description
-MCUBootApp is created to demonstrate operation of MCUBoot library on Cypress' PSoC 6 device. It supports various operation modes and features of MCUBoot library.
+This solution demonstrates operation of MCUboot on Cypress PSoC™ 6 and CYW20829 devices.
-* single/multi image operation modes
-* overwrite/swap upgrade modes
-* interrupted upgrade recovery for swap upgrades
-* upgrade image confirmation
-* reverting of bad upgrade images
-* secondary slots located in external flash
+* Single-/Multi-image operation modes
+* Overwrite/Swap upgrade modes
+* Interrupted upgrade recovery for swap upgrades
+* Upgrade image confirmation
+* Reverting of bad upgrade images
+* Secondary slots located in external flash
-This demo supports PSoC 6 chips with 1M, 2M and 512K Flash on board.
-Evaluation kits are:
+This demo supports PSoC™ 6 chips with the 1M-, 2M-, and 512K-flash on board, and the CYW20829 chip with no internal flash.
+The evaluation kits are:
* `CY8CPROTO-062-4343W`
* `CY8CKIT-062-WIFI-BT`
-* `CY8CPROTO-062S3-4343W`.
+* `CY8CPROTO-062S3-4343W`
+* `CYW920829M2EVB-01`
-### Memory Maps
+### Platfrom specifics
-MCUBoot terminology assumes a slot from which **boot** is happening to be named **primary**, and a slot where **upgrade** image is placed - **secondary**.
+MCUBootApp can be built for different platforms. So, the main application makefile `MCUBootApp.mk` operates with common build variables and flags. Most of them can be passed to build system as a `make` command parameter and each platform defines the default value prefixed with `PLATFORM_` in the corresponding makefile - `PSOC6.mk` or `CYW20829.mk`. The build flags and variables are described in detail in the following paragraphs.
-#### Internal Flash
+### Memory maps
-The flash map is defined at compile time. It can be configured through makefiles and `MCUBootApp/sysflash/sysflash.h` and `cypress/cy_flash_pal/cy_flash_map.c`.
+The MCUboot terminology names a slot from which **boot** occurs as **primary** and a slot where an **upgrade** image is placed as **secondary**. Some platforms support both internal and external flash, some only external flash.
-The default `MCUBootApp` flash map is defined for demonstration purpose. Sizes of slots are adjusted to be compatible with all supported device families: 1M, 2M and 512K.
+The flash map of bootloader is defined at compile time and cannot be changed dynamically. Flash map is prepared in the industry-accepted JSON (JavaScript Object Notation) format. It should follow the rules described in section **How to modify flash map**.
-Actual addresses provided below are calculated by preprocessor in `sysflash.h` and `cy_flash_map.c` per slot sizes set.
+`MCUBootApp` contains JSON templates for flash maps with commonly used configurations. They can be found in `cy_flash_pal/flash_%platform_name%/flashmap` The slots' sizes are defined per platform to be compatible with all supported device families.
-##### Single Image Mode
+The actual addresses are provided in corresponding platform doc files:
-| Start addr | End addr | Size | Description |
-|------------|------------|---------|-------------------------------------------|
-| 0x10000000 | 0x10018000 | 0x18000 | MCUBootApp (bootloader) area; |
-| 0x10018000 | 0x10028000 | 0x10000 | Primary_1 (BOOT) slot for BlinkyApp; |
-| 0x10028000 | 0x10038000 | 0x10000 | Secondary_1 (UPGRADE) slot for BlinkyApp; |
+- [PSOC6.md](../platforms/PSOC6/PSOC6.md)
+- [CYW20289.md](../platforms/CYW20829/CYW20829.md)
-If upgrade type is swap using scratch:
+#### How to modify flash map
-| Start addr | Size | Description |
-|------------|-----------|---------------------------------|
-| 0x10038000 | 0x1800 | Start of swap status partition; |
-| 0x10039800 | 0x1000 | Start of scratch area partition;|
+When modifying slots sizes, ensure aligning new values with the linker script files for appropriate applications.
-##### Multi Image Mode
+##### Flash map definition
+Flash map describes what flash memory areas are allocated and defines their addresses and sizes. Also, it specifies the type of external flash memory, if applicable.
-| Start addr | End addr | Size | Description |
-|------------|------------|---------|-------------------------------------------|
-| 0x10000000 | 0x10018000 | 0x18000 | MCUBootApp (bootloader) area; |
-| 0x10018000 | 0x10028000 | 0x10000 | Primary_1 (BOOT) slot for BlinkyApp; |
-| 0x10028000 | 0x10038000 | 0x10000 | Secondary_1 (UPGRADE) slot for BlinkyApp; |
-| 0x10038000 | 0x10058000 | 0x20000 | Primary_2 (BOOT) slot of Bootloader |
-| 0x10058000 | 0x10078000 | 0x20000 | Secondary_2 (UPGRADE) slot of Bootloader |
+To build `MCUBootApp` with the given flash map (e.g., `flash_map.json`), supply the following parameter to `make`:
+`FLASH_MAP=flash_map.json`
-If upgrade type swap:
+###### Flash map format
+Flash map must have the `"boot_and_upgrade"` section, define the location of `MCUBootApp` and at least one image. For instance:
+```
+{
+ "boot_and_upgrade": {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18030200"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
+```
+Here an application identifier should follow the pattern, i.e., the 2nd image in the multi-image case is `"application_2"`, the 3rd is `"application_3"`, and so on. Up to four applications are supported at this moment.
-| Start addr | Size | Description |
-|------------|-----------|---------------------------------|
-| 0x10078000 | 0x2800 | Start of swap status partition; |
-| 0x1007a800 | 0x1000 | Start of scratch area partition;|
+For each image the location and size of its primary slot is given in the `"address"` and `"size"` parameters. The location and size of the secondary slot is specified in the `"upgrade_address"` and `"upgrade_size"`. All four values described above are mandatory.
-**SWAP upgrade from external memory**
+There also should be a mandatory `"bootloader"` section, describing the location and size of `MCUBootApp` in the `"address"` and `"size"` parameters, respectively.
-When MCUBootApp is configured to support upgrade images places in external memory following fixed addresses are predefined:
+Under some circumstances (e.g., PSoC™ 62 with application slots in both internal and external flash memories), the slot address must be properly aligned, as the image trailer should start exactly at the erase block boundary. When an improper address is specified, `make` will fail with a message like:
+```
+Misaligned application_1 (secondary slot) - suggested address 0x18030200
+```
+This gives the nearest larger address that satisfy the slot location requirements. Other errors, such as overlapping flash areas, are also checked and reported.
-| SMIF base address | Offset | Description |
-|-------------------|-------------|---------------------------------|
-| 0x18000000 | 0x0 | Start of Secondary_1 (UPGRADE) image; |
-| 0x18000000 | 0x240000 | Start of Secondary_2 (UPGRADE) image; |
-| 0x18000000 | 0x440000 | Start of scratch area partition;|
+###### Scratch area
+If there is a scratch area, what is generally true, its location and size is given in the `"scratch_address"` and `"scratch_size"` parameters of the `"bootloader"` subsection. For example:
+```
+{
+ "boot_and_upgrade": {
+ "bootloader": {
+ . . .
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x18440000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x10000"
+ },
+ },
+ . . .
+```
-##### Single Image Mode
+###### Swap status partition
+If the desired upgrade mode is `swap scratch with status partition`, one should define the `"status_address"` and `"status_size"` parameters in the `"bootloader"` subsection, e.g.:
+```
+{
+ "boot_and_upgrade": {
+ "bootloader": {
+ . . .
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x10038000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x3800"
+ }
+ },
+ . . .
+```
+The required size of the status partition relies on many factors. If an insufficient size is given in the flash map, `make` will fail with a message such as:
+```
+Insufficient swap status area - suggested size 0x3800
+```
+To calculate the minimal correct size of the status partition, one could specify `"value": "0"` for the `"status_size"`. After the intentional `make` failure, copy the correct size from the error message.
-| Start addr | End addr | Size | Description |
-|------------|------------|---------|-------------------------------------------|
-| 0x10000000 | 0x10018000 | 0x18000 | MCUBootApp (bootloader) area; |
-| 0x10018000 | 0x10058200 | 0x40200 | Primary_1 (BOOT) slot for BlinkyApp; |
-| 0x18000000 | 0x18040200 | 0x40200 | Secondary_1 (UPGRADE) slot for BlinkyApp; |
+###### External flash
+If an external flash memory is used, one should specify its parameters. The first way is specyfing the exact model:
+```
+{
+ "external_flash": [
+ {
+ "model": "S25HS256T"
+ }
+ ],
+ "boot_and_upgrade": {
+ . . .
+```
+However, the supported model list is incomplete. The known models are Infineon `S25HS256T`/`S25HS512T`/`S25HS01GT` SEMPER™ NOR Flash ICs, and a couple of SPI Flash ICs from other vendors. Another way is specyfing the important parameters, like:
+```
+{
+ "external_flash": [
+ {
+ "flash-size": "0x100000",
+ "erase-size": "0x1000"
+ }
+ ],
+ "boot_and_upgrade": {
+ . . .
+```
+for a typical 8-Mbit SPI flash with uniform 4-KByte erase blocks. While JSON list syntax is used for the `"external_flash"` section, only single instance is supported at this moment.
-If upgrade type swap:
+If the main application image is located in the external flash, `XIP` (eXecute In Place) mode should be turned on. To do so, supply the corresponding `"mode"` parameter:
+```
+{
+ "external_flash": [
+ {
+ "model": "S25HS256T",
+ "mode": "XIP"
+ }
+ ],
+ . . .
+```
+###### Service RAM Application
+The CYW20829 platform has a hardware-supported security counter. For more details on rollback protection support, refer to the [CYW20289.md](../platforms/CYW20829/CYW20829.md) file.
+The mentioned feature requires a dedicated area in the flash memory to store the Service RAM Application and other required data. The layout of these areas is defined in the `"service_app"` JSON section:
+```
+ . . .
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ . . .
+ },
+ "service_app": {
+ "address": {
+ "description": "Address of the service application",
+ "value": "0x60070000"
+ },
+ "size": {
+ "description": "Size of the service application",
+ "value": "0x8000"
+ },
+ "params_address": {
+ "description": "Address of the service application input parameters",
+ "value": "0x60078000"
+ },
+ "params_size": {
+ "description": "Size of the service application input parameters",
+ "value": "0x400"
+ },
+ "desc_address": {
+ "description": "Address of the service application descriptor",
+ "value": "0x60078400"
+ },
+ "desc_size": {
+ "description": "Size of the service application descriptor",
+ "value": "0x20"
+ }
+ },
+ "application_1": {
+ . . .
+```
+###### Shared secondary slot
+In the multi-image case, one can reduce the utilization of flash memory by placing secondary images into the same area. This area is reffered to as **Shared secondary slot**. This is especially desirable if there are more than two images.
-| Start addr | Size | Description |
-|------------|-----------|---------------------------------|
-| 0x10058200 | 0x3c00 | Start of swap status partition; |
+Important consideration is that this option assumes updates are performed in sequential manner (consider the Swap upgrade method): place the 1st image into the shared slot, reset to MCUBoot, check the updated image and set the Image OK flag for the 1st image, reset to MCUBoot for permanent swap. Then place the 2nd image into the shared slot, reset to MCUBoot, check the updated image and set the Image OK flag for the 2nd image, reset to MCUBoot for permanent swap, etc.
-##### Multi Image Mode
+Take into account that it is possible to revert only the last updated image, as its previous version resides in the Shared secondary slot. There is no way to revert changes for previous images, as their backups are gone! That is trade-off of the Shared secondary slot.
-| Start addr | End addr | Size | Description |
-|------------|------------|---------|-------------------------------------------|
-| 0x10000000 | 0x10018000 | 0x18000 | MCUBootApp (bootloader) area; |
-| 0x10018000 | 0x10058200 | 0x40200 | Primary_1 (BOOT) slot for BlinkyApp; |
-| 0x10058200 | 0x10098400 | 0x40200 | Primary_2 (BOOT) slot of Bootloader |
-| 0x18000000 | 0x18040200 | 0x40200 | Secondary_1 (UPGRADE) slot for BlinkyApp; |
-| 0x18240000 | 0x18280200 | 0x40200 | Secondary_2 (UPGRADE) slot of Bootloader; |
+Shared secondary slot is rather a virtual concept, we still create individual flash areas for all secondary images. However, this areas are now overlapped (this is prohibited in the standard multi-image scenario). Moreover, special placing of secondary slots is required, as described below. Consider the triple-image example:
+```
+| |---------| |\
+| | | | \
+|---------| | | \
+| | | | \
+| Image 1 | Image 2 |---------| \
+| | | | Shared
+|---------| | | Secondary
+| Trailer | | Image 3 | Slot
+|---------|---------| | /
+| | Trailer | | /
+| |---------|---------| /
+| | | Trailer | /
+| | |---------|/
+```
+The purpose of such layout is to allow MCUBoot to understand what image is placed in the shared secondary slot. While secondary images now can (and should) overlap, their trailers must under no circumstances share the same address!
-If upgrade type is swap using scratch:
+Normally image trailer occupies the whole erase block (e.g. 512 bytes for PSoC™ 62 internal Flash, or 256 kilobytes for SEMPER™ Secure NOR Flash). There is a specific case when images are placed in both memory types, refer to the [PSOC6.md](../platforms/PSOC6/PSOC6.md) file.
-| Start addr | Size | Description |
-|------------|-----------|---------------------------------|
-| 0x10098400 | 0x6400 | Start of swap status partition; |
+One can declare all secondary slots as shared using the following JSON syntax:
+```
+ "boot_and_upgrade": {
+ "bootloader": {
+ . . .
+ "shared_slot": {
+ "description": "Using shared secondary slot",
+ "value": true
+ }
+ },
+```
+Alternatively, this can be done for each application:
+```
+ "boot_and_upgrade": {
+ "bootloader": {
+ . . .
+ },
+ "application_1": {
+ . . .
+ "shared_slot": {
+ "description": "Using shared secondary slot",
+ "value": true
+ }
+ },
+ "application_2": {
+ . . .
+ "shared_slot": {
+ "description": "Using shared secondary slot",
+ "value": true
+ }
+ },
+ . . .
+```
+where `true` marks the shared slot, `false` marks the normal (non-shared) secondary slot. In theory, one can use a separate secondary slot for the 1st image, and shared secondary slot for all other images.
-##### How To Modify Flash Map
+When the `shared_slot` flag is set, different checks are performed at the pre-build stage. For instance, the following error is reported if image trailers appear at the same address:
+```
+Same trailer address for application_3 (secondary slot) and application_2 (secondary slot)
+```
+As mentioned above, shared secondary slot is a virtual concept, so overlapped flash areas are created for each image's secondary slot. No separate flash area is created for the shared slot itself.
-When modifying slots sizes - make sure to align new values with linker script files for appropriate applications.
+**Upgrade process deviations**
-**Option 1**
+Shared slot feature has some differences and limitations in the update algorithm when there is one or more invalid images in primary slots and upgrade of these images is initiated through the shared upgrade slot (so-called **bootstrap** mode of bootloader). In this case, the bootloader allows to update the image even if other images are not valid (unlike the classic multi-image case). Bootloader however does not transfer control to these images until all primary slots become valid. ImageOK flag is set by updated images only after their successful validation and start.
-Navigate to `sysflash.h` and modify slots sizes directly to meet your needs.
+Considering above there is a certain limitation for the shared slot mode. For **swap mode**, an update of valid slots is not possible as long as there is at least one image with an invalid prime slot.
-`CY_BOOT_BOOTLOADER_SIZE` defines size of MCUBootApp.
-`CY_BOOT_IMAGE_1_SIZE` defines slot size for single image case.
-`CY_BOOT_IMAGE_2_SIZE` defines slot size of second image in multi image case.
+Attempting to upgrade a valid primary slot of one image with an invalid primary slot of another image may run a revert procedure the next time the bootloader is started (provided that the data of shared slot has not been changed before). Therefore, for the shared slot, it is recommended to first make all invalid primary slots valid and only then update other images through the shared slot.
-__Option 2.__
+###### JSON syntax rules
+| Group | Item | Description |
+|--------------------|-------------------|----------------------------------------------------------|
+| `external_flash` | `model` | External flash model (if supported), e.g. `S25HS256T` |
+| `external_flash` | `flash-size` | External flash size in bytes (if model is not supported) |
+| `external_flash` | `erase-size` | Erase block size in bytes (if model is not supported) |
+| `external_flash` | `mode` | Set to `XIP` for eXecute In Place |
+| `boot_and_upgrade` | `bootloader` | Contains flash areas used by the `MCUBootApp` |
+| `bootloader` | `address` | Absolute address of the `MCUBootApp` |
+| `bootloader` | `size` | Size of the `MCUBootApp` in bytes |
+| `bootloader` | `scratch_address` | Absolute address of the Scratch Area |
+| `bootloader` | `scratch_size` | Size of the Scratch Area in bytes |
+| `bootloader` | `status_address` | Absolute address of the Swap Status Partition |
+| `bootloader` | `status_size` | Size of the Swap Status Partition in bytes |
+| `bootloader` | `shared_slot` | Marking the shared secondary slot for all images |
+| `boot_and_upgrade` | `service_app` | Reserves flash space for Service RAM Application |
+| `service_app` | `address` | Address of the Service RAM Application |
+| `service_app` | `size` | Size of the Service RAM Application |
+| `service_app` | `params_address` | Address of the input parameters (follows the app) |
+| `service_app` | `params_size` | Size of the service application input parameters |
+| `service_app` | `desc_address` | Address of the app descriptor (follows the parameters) |
+| `service_app` | `desc_size` | Size of the service application descriptor (always 0x20) |
+| `boot_and_upgrade` | `application_1` | Contains flash areas of the 1st application image |
+| `boot_and_upgrade` | `application_2` | 2nd image, see the description of `application_1` |
+| `boot_and_upgrade` | `application_3` | 3rd image, see the description of `application_1` |
+| `boot_and_upgrade` | `application_4` | 4th image, see the description of `application_1` |
+| `application_1` | `address` | Absolute address of the Primary Slot of the 1st image |
+| `application_1` | `size` | Size (in bytes) of the Primary Slot of the 1st image |
+| `application_1` | `upgrade_address` | Absolute address of the Secondary Slot of the 1st image |
+| `application_1` | `upgrade_size` | Size (in bytes) of the Secondary Slot of the 1st image |
+| `application_1` | `shared_slot` | Marking the shared secondary slot for the 1st image |
+| `address` | `value` | Value of the given address (hex or decimal) |
+| `scratch_address` | `value` | Value of the Scratch Area address (hex or decimal) |
+| `status_address` | `value` | Value of the Status Partition address (hex or decimal) |
+| `upgrade_address` | `value` | Value of the Secondary Slot address (hex or decimal) |
+| `size` | `value` | Value of the given size (hex or decimal) |
+| `scratch_size` | `value` | Value of the Scratch Area size (hex or decimal) |
+| `status_size` | `value` | Value of the Status Partition size (hex or decimal) |
+| `upgrade_size` | `value` | Value of the Secondary Slot size (hex or decimal) |
+| `shared_slot` | `value` | Set to `true` for the Shared secondary slot |
-Navigate to `sysflash/sysflash.h` and uncomment `CY_FLASH_MAP_EXT_DESC` definition.
-Now define and initialize `struct flash_area *boot_area_descs[]` in a code with flash memory addresses and sizes you need at the beginning of application, so flash APIs from `cy_flash_pal/cy_flash_map.c` will use it.
+###### Flash map internals
+When the `FLASH_MAP=` option is supplied to `make`, it involves the Python script `boot/cypress/scripts/flashmap.py`. It takes the JSON file and converts flash map into the C header file `boot/cypress/MCUBootApp/cy_flash_pal/cy_flash_map.h`.
-__Note:__ for both options make sure to use correct `MCUBOOT_MAX_IMG_SECTORS`. This should correspond to slot size used. Maximum value of sectors can be set by passing a flag `MAX_IMG_SECTORS=__number__` to `make`. By default it is set to 256 sectors, which corresponds to `0x20000` slot size in multi image use case. Sector size assumed to be 512 bytes, so 128 sectors needed to fill `0x10000`, 256 sectors for `0x20000` and so on.
+At the same time it creates the `boot/cypress/MCUBootApp/flashmap.mk`, which is conditionally included from the `boot/cypress/MCUBootApp/MCUBootApp.mk`. The generated file contains various definitions derived from the flash map, such as `MCUBOOT_IMAGE_NUMBER`, `MAX_IMG_SECTORS`, `USE_EXTERNAL_FLASH`, and `USE_XIP`. So, there is no need to specify these and similar parameters manually.
-###### How To Override The Flash Map Values During Build Process
+Do not edit neither `sysflash/cy_flash_map.h` nor `flashmap.mk`, as both files are overwritten on every build.
-It is possible to override MCUBootApp definitions from build system. Navigate to `MCUBootApp.mk`, find section `DEFINES_APP +=`
-Using this construction macros can be defined and passed to compiler.
+#### External flash
-The full list of macros used to configure the custom multi image case with upgrade from external memory:
+Some Cypress devices, for example `CYW20829`, only have external flash, so all memory areas are located in external flash.
-* MCUBOOT_MAX_IMG_SECTORS
-* CY_FLASH_MAP_EXT_DESC
-* CY_BOOT_SCRATCH_SIZE
-* CY_BOOT_BOOTLOADER_SIZE
-* CY_BOOT_IMAGE_1_SIZE
-* CY_BOOT_IMAGE_2_SIZE
-* CY_BOOT_EXTERNAL_FLASH_SECONDARY_1_OFFSET
-* CY_BOOT_EXTERNAL_FLASH_SECONDARY_2_OFFSET
-* CY_BOOT_EXTERNAL_FLASH_SCRATCH_OFFSET
+Hoewever, PSoC™ 6 chips has internal flash and, additionally, support the external memory connection. Thus, it is possible to place secondary (upgrade) slots in the external memory module and use most of internal flash for the primary image.
+For more details on External Memory usage, refer to the [ExternalMemory.md](ExternalMemory.md) file.
-As an example in a makefile slots sizes redefinition should look like following:
+#### PSoC™ 6 RAM
-`DEFINES_APP +=-DCY_BOOT_EXTERNAL_FLASH_SCRATCH_OFFSET=0x18780000`
-`DEFINES_APP +=-DMCUBOOT_MAX_IMG_SECTORS=168`
-`DEFINES_APP +=-DCY_BOOT_IMAGE_1_SIZE=0x15000`
-`DEFINES_APP +=-DCY_BOOT_IMAGE_2_SIZE=0x15000`
+RAM areas in the MCUBootApp bootloading application and BlinkyApp are defined as an example pair. If your user application requires a different RAM area, ensure that it is not overlapped with the MCUBootApp RAM area. The memory (stack) corruption of the bootloading application can cause a failure if SystemCall-served operations were invoked from the user app.
-#### External Flash
+The MCUBootApp linker script also contains the special section `public_ram`, which serves as a shared RAM area between the CM0p and CM4 cores. When CM4 and CM0p cores perform operations with internal flash, this area is used for the interprocessor data sharing.
-It is also possible to place secondary (upgrade) slots in external memory module and use most of internal for primary image.
-Details about External Memory usage are described in separate guiding document `MCUBootApp/ExternalMemory.md`.
+#### CYW20829 RAM
-#### RAM
+Only one CM33 core is used in the CYW20829 chips, so there are no restrictions for the RAM usage by the layer1 and layer2 applications (i.e. MCUBootApp and BlinkyApp).
-RAM areas in CM0p-based MCUBootApp bootloading application and CM4-based BlinkyApp are defined as an example pair. If your CM4 user application requires different RAM area make sure it is not overlap with MCUBootApp ram area. Memory (stack) corruption of CM0p application can cause failure if SystemCall-served operations invoked from CM4.
+### Hardware cryptography acceleration
-MCUBootApp linker script also contains special section `public_ram`. This section serves for shared ram area between CM0p and CM4 cores. When CM4 and CM0p cores perform operations with internal flash, this area is used for interprocessor connection data sharing.
+Cypress PSoC™ 6 MCU family supports hardware acceleration of the cryptography based on the mbedTLS Library via a shim layer. The implementation of this layer is supplied as the separate submodule `cy-mbedtls-acceleration`. The hardware acceleration of the cryptography shortens the boot time by more than four times compared to the software implementation (observation results).
-### Hardware Cryptography Acceleration
+The CYW20289 chip has hardware acceleration of the SHA256 algorithm only, and in other cases, uses pure software implementation of the cryptography based on MbedTLS.
-Cypress PSoC 6 MCU family supports hardware acceleration of cryptography based on mbedTLS Library via shim layer. Implementation of this layer is supplied as separate submodule `cy-mbedtls-acceleration`. HW acceleration of cryptography shortens boot time in more then 4 times, comparing to software implementation (observation results).
+To enable the hardware acceleration in `MCUBootApp`, pass flag `USE_CRYPTO_HW=1` to `make` during build.
-To enable hardware acceleration in `MCUBootApp` pass flag `USE_CRYPTO_HW=1` to `make` while build.
+The hardware cryptographic acceleration is disabled for all devices at the moment. `USE_CRYPTO_HW` flag is set to 0 by default. This package will be updated in next version.
-Hardware acceleration of cryptography is enabled for PSoC 6 devices by default.
+__NOTE__: Hardware acceleration is not available in current version of mcuboot since `cy-mbedtls-acceleration` does not support `mbedTLS 3.0` yet.
-### Multi Image Mode
+### Multi-image mode
-Multi image operation considers upgrading and verification of more then one image on the device.
+Multi-image operation considers upgrading and verification of more than one image on a device.
-By default MCUBootApp is configured for single image mode. To enable multi image operation pass `MCUBOOT_IMAGE_NUMBER=2` as parameter to `make`.
+Single or multi-image mode is dictated by `MCUBOOT_IMAGE_NUMBER` `make` flag. This flag's value is set in auto-generated `flashmap.mk` file per flash map used. There is no need to pass it manually.
- `MCUBOOT_IMAGE_NUMBER` can also be changed permanently in `MCUBootApp/config/mcuboot_config.h` file. This value can only be set to 2 (only dual-image is supported at the moment).
+In Multi-image operation up to four images are supported.
-In multi image operation (two images are considered for simplicity) MCUBootApp bootloading application operates as following:
+Consider MCUBootApp with 2 images supported. Operation is the following:
-1. Verifies Primary_1 and Primary_2 images;
-2. Verifies Secondary_1 and Secondary_2 images;
-3. Upgrades Secondary to Primary if valid images found;
-4. Boots image from Primary_1 slot only;
-5. Boots Primary_1 only if both - Primary_1 and Primary_2 are present and valid;
+1. Verification of the Secondary_1 and Secondary_2 images.
+2. Upgrades Secondary to Primary if valid images found.
+3. Verification of the Primary_1 and Primary_2 images.
+4. Boots the image from the Primary_1 slot only.
+5. Boots Primary_1 only if both - Primary_1 and Primary_2 are present and valid.
-This ensures two dependent applications can be accepted by device only in case both images are valid.
+This ensures that two dependent applications can be accepted by the device only if both images are valid.
-### Upgrade Modes
+### Upgrade modes
-There are two different types of upgrade process supported by MCUBootApp. In case of `overwrite only` type of upgrade - secondary image is simply copied to primary slot after successful validation. No way to revert upgrade in a case when secondary image is inoperable.
+There are two different types of the upgrade process supported by MCUBootApp. For the `overwrite only` type of upgrade - the secondary image is simply copied to the primary slot after successful validation. No way to revert upgrade if the secondary image is inoperable.
-In case of `swap` upgrade mode - images in primary and secondary slots are swaped. Upgrade can be reverted if secondary image did not confirm its operation.
+For `swap` upgrade mode - images in the primary and secondary slots are swapped. Upgrade can be reverted if the secondary image did not confirm its operation.
-Upgrade mode is the same for all images in multi image mode.
+Upgrade mode is the same for all images in Multi-image mode.
-#### Overwrite Only
+#### Overwrite only
-To build MCUBootApp for overwrite upgrades only `MCUBootApp/config/mcuboot_config/mcuboot_config.h` should contain following define:
+To build MCUBootApp for overwrite upgrades only, `MCUBootApp/config/mcuboot_config/mcuboot_config.h` must contain the following definition:
`#define MCUBOOT_OVERWRITE_ONLY 1`
-This define can also be set in `MCUBootApp/MCUBootApp.mk`:
+This flag's value is set in auto-generated `flashmap.mk` file per flash map used. There is no need to pass it manually.
-`DEFINES_APP +=-DMCUBOOT_OVERWRITE_ONLY=1`
+In Overwrite-only mode, MCUBootApp first checks if any upgrade image is present in the secondary slot(s), then validates the digital signature of the upgrade image in the secondary slot(s). If validation is successful, MCUBootApp starts copying the secondary slot content to the primary slot. After the copy is done, MCUBootApp starts the upgrade image execution from the primary slot.
-In ovewrite only mode MCUBootApp first checks if any upgrade image is present in secondary slot(s), then validates digital signature of upgrade image in secondary slot(s). If validation is successful MCUBootApp starts copying secondary slot content to primary slot. After copy is done MCUBootApp starts upgrade image execution from primary slot.
+If the upgraded application does not work - there is no way to revert back to the previous working version. Only the new upgrade firmware can fix the previous broken upgrade.
-If upgraded application does not work - there is no way no revert back to previous working version. In this case only new upgrade firmware can fix previous broken upgrade.
+#### Swap mode
-#### Swap Mode
-
-There are 2 basic types of swap modes supported in MCUBoot:
-* scratch
-* move
-
-For devices with large minimum erase size like PSoC 6 with 512 bytes and also for configurations which use external flash with even bigger minimum erase size there is an additional option in MCUBoot to use dedicated `status partition` for robust storage of swap related information.
+For devices with a large minimum-erase size like PSoC™ 6 with 512 bytes and also for configurations, which use external flash with an even bigger minimum-erase size, there is an additional option in MCUBoot to use the dedicated `status partition` for robust storage of swap-related information.
##### Why use swap with status partition
-Originally MCUBoot library has been designed with a consideration, that minimum write/erase size of flash would always be 8 bytes or less. This value is critical, because swap algorithms use it to align portions of data that contain swap operation status of each flash sector in slot before writing to flash. Data alignment is also performed before writes of special purpose data to image trailer.
+Originally, the MCUboot library has been designed with a consideration that the minimum write/erase size of flash is always 8 bytes or less. This value is critical, because the swap algorithms use it to align portions of data that contain the swap operation status of each flash sector in a slot before writing to flash. Data alignment is also performed before writes of special-purpose data to the image trailer.
-Writing of flash sector status or image trailer data should be `single cycle` operation to ensure power loss and unpredicted resets robustness of bootloading applications. This requirement eliminates usage of `read-modify-write` type of operations with flash.
+Writing of the flash sector status or image trailer data will be the `single cycle` operation to ensure that the power loss and unpredicted resets robustness of bootloading applications. This requirement eliminates the usage of the `read-modify-write` type of operations with flash.
-`Swap with status partition` is implemented specifically to address devices with large write/erase size. It is based on existing mcuboot swap algorithms, but does not have restriction of 8 bytes alignment. Instead minimum write/erase size can be specified by user and algorithm will calculate sizes of status partition, considering this value. All write/erase operations are aligned to this minimum write/erase size as well.
+`Swap with status partition` is implemented specifically to address devices with a large write/erase size. It is based on existing MCUboot swap algorithms, but does not have restriction of the 8-byte alignment. Instead, the minimum write/erase size can be specified by the user and the algorithm will calculate sizes of the status partition considering this value. All write/erase operations are aligned to this minimum write/erase size as well.
-##### Swap Status Partition Description
+##### Swap status partition description
-The main distinction of `swap with status partition` is that separate flash area (partition) is used to store swap status values and image trailer instead of using free flash area at the end of primary/secondary image slot.
+The main distinction of `swap with status partition` is that a separate flash area (partition) is used to store the swap status values and image trailer instead of using the free flash area at the end of the primary/secondary image slot.
This partition consists of separate areas:
-* area to store swap status values
+* the area to store swap status values
* swap_status_0
* ...
* swap_status_x
-* area to store image trailer data:
+* the area to store image trailer data:
* Encryption key 0
* Encryption key 1
* Swap size
@@ -237,7 +433,7 @@
* Image ok
* Boot image magic
-Principal diagram of status partition:
+The principal diagram of the status partition:
```
+-+-+-+-+-+-+ +-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ \
@@ -278,146 +474,167 @@
```
**Scheme legend:**
-`PRIMARY` and `SECONRADY` are areas in status partition to contain data regarding corresponding slot in mcuboot.
-`D0`, `D1` and `Dx` are duplicates of data described on the left. At least 2 duplicates should be present in system. This duplication is used to eliminate flash wear. Each of `Dx` contains valid data for `current swap step - 1`. Each swap operation for flash sector updates status for this sector in current `Dx` and value on `CNT` inreases. Next operation checks least value of `CNT` in available `Dx`'s, copies there data from `Dx` with `CNT+1` and updates status of current sector. This continues until all sectors in slot are moved and then swaped.
-`CRC` - 4 bytes value - checksum of data contaited in area.
-`CNT` - 4 bytes value.
-`swap_status_0`, `swap_status_1`- one byte values, that contain status for corresponding image sector.
-`swap_status_x` - last sector of `BOOT_MAX_IMAGE_SECTORS`.
-`swap_status_max` - maximum number of sectors that fits in min write/erase size for particular flash hardware. If `swap_status_max` is less then `swap_status_x` additional slice of min write/erase flash area is allocated to store swap status data.
-`Image trailer` - should be at least 64 bytes. Code calculates how many min write/erase sizes need to be allocated to store image trailer data.m.
+`PRIMARY` and `SECONDARY` are areas in the status partition to contain data regarding a corresponding slot in MCUboot.
+`D0`, `D1`, and `Dx` are duplicates of data described on the left. At least 2 duplicates are present in the system. This duplication is used to eliminate flash wear. Each of `Dx` contains valid data for `current swap step - 1`. Each swap operation for the flash sector updates the status for this sector in the current `Dx` and the value on `CNT` increases. The next operation checks the least value of `CNT` in the available `Dx`s, copies the data from `Dx` with `CNT+1` and updates the status of the current sector. This continues until all sectors in the slot are moved and then swapped.
+`CRC` - A 4-byte value - the checksum of data contained in the area.
+`CNT` - A 4-byte value.
+`swap_status_0`, `swap_status_1` - 1-byte values that contain the status for a corresponding image sector.
+`swap_status_x` - The last sector of `BOOT_MAX_IMAGE_SECTORS`.
+`swap_status_max` - The maximum number of sectors that fits in the min write/erase size for particular flash hardware. If `swap_status_max` is less than `swap_status_x`, an additional slice of the min write/erase flash area is allocated to store swap status data.
+`Image trailer` - No less than 64 bytes. The code calculates how many min write/erase sizes to allocate for storing image trailer data.
-**Calculation example for PSoC 6 with minimum write/erase size of 512 bytes is used.**
+**A calculation example for PSoC™ 6 with the minimum write/erase size of 512 bytes.**
-Following considered:
-* Single image case
+The following are considered:
+* Single-image case
* Minimum write/erase size 512 bytes
* PRIMARY/SECONDARY slots size `0x50000`
* BOOT_MAX_IMG_SECTORS 0x50000 / 512 = 640
* Number of duplicates `Dx = 2`
-One slice of `min write/erase` size can store data for maximum number of 500 sectors: 512 - 4 (CRC) - 4 (CNT) - 4 (area magic) = 500. Since BOOT_MAX_IMG_SECTORS is 640 - 2 slices of `min write/erase` is allocated. Total size is 1024 bytes.
-Image trailer data fits in 64 bytes, so one slice of `min write/erase` size is allocated. Total size is 1024 + 512 = 1536 bytes.
-Duplicates number equals 2. Total size is 1536 * 2 = 3072 bytes.
-2 slots are used in particular case PRIMARY and SECONDARY, each needs 3072 bytes to store swap status data. Tolal is 3072 * 2 = 6144 bytes.
+One slice of the `min write/erase` size can store data for the maximum number of 500 sectors: 512 - 4 (CRC) - 4 (CNT) - 4 (area magic) = 500. BOOT_MAX_IMG_SECTORS is 640, so 2 slices of `min write/erase` are allocated. The total size is 1024 bytes.
+Image trailer data fits in 64 bytes, so one slice of the `min write/erase` size is allocated. The total size is 1024 + 512 = 1536 bytes.
+The number of duplicates 2. The total size is 1536 * 2 = 3072 bytes.
+2 slots are used in the particular case PRIMARY and SECONDARY, each needs 3072 bytes to store swap status data. The total is 3072 * 2 = 6144 bytes.
-Swap status partition occupies 6144 bytes of flash area in this case.
+The swap status partition occupies 6144 bytes of the flash area.
**Expected lifecycle**
-Since bootloading application that uses swap using status partition upgrade mode stores system state in separate flash area following product lifecycle is expected:
-`Empty` - Fully erased device
-`Ready` - `Empty` device is programmed with MCUBoot based bootloading application - MCUBootApp in this case.
-`Flashed` - Initial version v1.0 of user applicatio, BlinkyApp is this case, flashed to primary (BOOT) slot.
-`Upgraded` - updated firmware image of user application is delivered to secondary slot (UPGRADE) and bootloading application performs upgrade.
+The bootloading application uses the swap using the status partition, so Upgrade mode stores the system state in a separate flash area and the following product lifecycle is expected:
-It is expected that product stays in `Upgraded` state ultil end of its lifecycle.
+`Empty` - A fully-erased device.
+`Ready` - `Empty` -The device is programmed with the MCUboot-based bootloading application - MCUBootApp in this case.
+`Flashed` - Initial version v1.0 of the user application, BlinkyApp in this case, is flashed to the primary (BOOT) slot.
+`Upgraded` - The updated firmware image of the user application is delivered to the secondary slot (UPGRADE) and the bootloading application performs upgrade.
-In case there is a need to wipe out product and flash new firmware directly to primary (BOOT) slot - device should be transfered to `Empty` or `Ready` state and then walk through all states again.
+It is expected that the product stays in the `Upgraded` state until the end of its lifecycle.
-### Hardware Limitations
+If there is a need to wipe out product and flash new firmware directly to the primary (BOOT) slot, the device is transferred to the `Empty` or `Ready` state and then walks through all the states again.
-Since this application is created to demonstrate MCUBoot library features and not as reference examples some considerations are taken.
+### Hardware limitations
-1. `SCB5` used to configure serial port for debug prints. This is the most commonly used Serial Communication Block number among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definition of `CYBSP_UART_HW` in `main.c` of MCUBootApp to SCB* that correspond to your design.
+This application is created to demonstrate the MCUboot library features and not as a reference examples. So, some considerations are taken.
-2. `CY_SMIF_SLAVE_SELECT_0` is used as definition SMIF driver API. This configuration is used on evaluation kit for this example CY8CPROTO-062-4343W. If you try to use custom hardware with this application - change value of `smif_id` in `main.c` of MCUBootApp to value that corresponds to your design.
+1. `SCB5` is used to configure a serial port for debug prints. This is the most commonly used Serial Communication Block number among available Cypress PSoC™ 6 kits. To use custom hardware with this application, set custom `SCB*` and pins in the `cypress/MCUBootApp/custom_debug_uart_cfg.h` file and pass the `USE_CUSTOM_DEBUG_UART=1` parameter to the `make` command upon MCUBootApp build.
-### Downloading Solution's Assets
+The `custom_debug_uart_cfg.h` file description:
-There is a set assets required:
+`CUSTOM_UART_HW` - Sets a custom SCB name used as the debug serial port. (e.g. `SCB1`, `SCB2`, ...)
+`CUSTOM_UART_SCB_NUMBER` - Sets the number of SCB. It is `x` in the custom SCBx, which is set in `CUSTOM_UART_HW`.
+ (e.g. `1` if `CUSTOM_UART_HW` is set to SCB1, `2` if `CUSTOM_UART_HW`is set to SCB2, ...)
+`CUSTOM_UART_PORT` - Sets the GPIO port number whose pins are used as RX and TX of the debug serial port.
+`CUSTOM_UART_RX_PIN` - Sets the pin number in the GPIO port used as RX of the debug serial port.
+`CUSTOM_UART_TX_PIN` - Sets the pin number in the GPIO port used as TX of the debug serial port.
+
+The above-described applies only to the `PSoC™ 062` platform.
+
+2. `CY_SMIF_SLAVE_SELECT_0` is used to define the chip select for the SMIF driver. This configuration is used on the evaluation kit for this example CY8CPROTO-062-4343W. To use custom hardware with this application, change the value of `smif_id` in `main.c` of MCUBootApp to a value that corresponds to your design.
+
+### Downloading solution assets
+
+The required set of assets:
* MCUBooot Library (root repository)
-* PSoC 6 HAL Library (submodule)
-* PSoC 6 Peripheral Drivers Library (PDL) (submodule)
+* HAL Library (submodule)
+* Peripheral Drivers Library (PDL) (submodule)
* mbedTLS Cryptographic Library (submodule)
To get submodules - run the following command:
git submodule update --init --recursive
-### Configuring MCUBootApp Bootloading Application
+### Configuring MCUBootApp bootloading application
-1. Choose upgrade mode:
-
-`SWAP` - this mode is set by default in `MCUBootApp/config/mcuboot_config/mcuboot_config.h`. `MCUBOOT_SWAP_USING_STATUS` preprocessor symbol is defined to enable this mode.
+1. Choose Upgrade mode and number of images.
-`Ovewrite only` - pass `USE_OVERWRITE=1` parameter to `make` for overwrite mode compilation.
-
-2. Change memory map
+`cy_flash_pal/flash_%platform_name%/flashmap` folder contains a set of predefined flash map JSON files with suffixes _overwrite_ or _swap_ for upgrade methods and _single_ or _multi_ for images number in its names. Depending on the file chosen upgrade method and images number is configured:
-Check paragraph **How to modify Flash map** above.
+`USE_OVERWRITE` `make` flag is set to 1 or 0 for `overwrite` or `swap` mode;
+`MCUBOOT_IMAGE_NUMBER` flag is set to number of corresponding `application_#` sections in flash map file.
-3. Enable hardware acceleration of cryptography
+These flags values are set in auto-generated `flashmap.mk` file per flash map used. There is no need to pass them manually.
-Pass `USE_CRYPTO_HW=1` to `make` command. This option is enabled by default.
+2. Enable the hardware acceleration of the cryptography on devices that support this feature.
-4. Change number of images - single or multi image configuration
+Pass `USE_CRYPTO_HW=1` to the `make` command. This option is temporarily disabled by default - see paragraph **Hardware cryptography acceleration**.
+
+Additionally user can configure hardware rollback protection on the supported platforms. To do this flash map file from `cy_flash_pal/flash_%platform_name%/flashmap/hw_rollback_prot` folder should be used.
+
+`USE_HW_ROLLBACK_PROT` `make` flag is set to 1 in auto-generated `flashmap.mk`.
+
+Rollback protection feature is currently supported on CYW20829 devices in Secure mode only.
+
+### Building solution
+
+Folder `boot/cypress` contains make-files infrastructure for building MCUBootApp bootloader applications. Example build commands are provided later in this document for different build configurations.
+
+* Build MCUBootApp in the `Debug` configuration for Single-image mode with swap upgrade.
+
+ make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json
+
+* Build MCUBootApp in `Release` configuration for Multi-image mode with overwrite update.
+
+ make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi.json
+
+The root directory for build is `boot/cypress`.
+
+### Encrypted image support
+
+To protect firmware content from read, plain binary data can be encrypted. MCUBootApp supports the encrypted image in some implementations, depending on the platform.
+
+On PSoC™ 6, an upgrade image can be encrypted and then programmed to corresponding Secondary slot of MCUBootApp. It is then decrypted and transferred to the primary slot using the preferred upgrade method. For more details on the encrypted image implementation, refer to the [PSOC6.md](../platforms/PSOC6/PSOC6.md) file.
+
+On CYW20829, an encrypted image is supported in both slots. The firmware here is located in external memory, so, the chip's SMIF block encrypted eXecution In Place (XIP) feature is used. Encrypted firmware is placed directly in the primary slot and is decrypted on the fly. The encrypted upgrade image is first validated by MCUBootApp in the secondary slot and then transferred to the primary slot as it is. For more details on the encrypted image implementation, refer to the [CYW20289.md](../platforms/CYW20829/CYW20829.md) file.
+
+### Rollback protection
+
+MCUboot supports the security counter implementation to provide downgrade prevention. This mechanism allows the user to explicitly restrict the possibility to execute/upgrade images whose security counters are less than the current firmware counter. So, it can be guaranteed, that obsolete firmware with possible vulnerabilities can not be executed on the device.
+
+**Currently, only the CYW20829 platform supports the hardware rollback counter protection.**
+For more details on the implementation, refer to the [CYW20289.md](../platforms/CYW20829/CYW20829.md) file.
+
+### Complete build flags and parameters description
-Pass `MCUBOOT_IMAGE_NUMBER=1` for single image configuration
-Pass `MCUBOOT_IMAGE_NUMBER=2` for multi image configuration
+Can be passed to `make` or set in makefiles.
-### Building Solution
+`MCUBOOT_LOG_LEVEL` - Can be set at `MCUBOOT_LOG_LEVEL_DEBUG` to enable the verbose output of MCUBootApp.
+`ENC_IMG` - When set to `1`, enables the encrypted image support in MCUBootApp.
+`APP_DEFAULT_POLICY` - The path to a policy file to use for signing MCUBootApp and user application (BlinkyApp) on the CYW20829 platform.
+`USE_BOOTSTRAP` - When set to `1` and Swap mode is enabled, the application in the secondary slot will overwrite the primary slot, if the primary slot application is invalid.
+`USE_CRYPTO_HW` - When set to `1`, uses the hardware accelerated cryptography on the PSoC™ 6 platform, and SHA-256 HW acceleration for the CYW20289 platform.
+`LSC` - The lifecycle state of the chip. Possible options are `SECURE` and `NORMAL_NO_SECURE` (effective on CYW20829 chip only).
-This folder `boot/cypress` contains make files infrastructure for building MCUBootApp bootloader application. Example build command are provided below for couple different build configurations.
+Set by script in auto-generated makefile file.
-* Build MCUBootApp in `Debug` configuration for single image use case.
+`MCUBOOT_IMAGE_NUMBER` - The number of images to be supported by the current build of MCUBootApp.
+`USE_OVERWRITE` - `0` - Use swap with Scratch upgrade mode, `1` - use Overwrite only upgrade.
+`USE_EXTERNAL_FLASH` - When set to `1`, enables the external memory support on the PSoC™ 6 platform. This value is always set to `1` on CYW20829.
+`USE_HW_ROLLBACK_PROT` - When set to `1`, enables the hardware rollback protection on the CYW20829 platform with Secure mode enabled.
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug MCUBOOT_IMAGE_NUMBER=1
+### Programming solution
-* Build MCUBootApp in `Release` configuration for multi image use case.
+The MCUBootApp firmware can be programmed in different ways.
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release MCUBOOT_IMAGE_NUMBER=2
+1. The direct usage of OpenOCD.
-Root directory for build is `boot/cypress`.
+The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in installation folder `ModusToolbox/tools_2.4/openocd`.
-### Encrypted Image Support
+Set environment variable `OPENOCD` to the path to the openocd folder in ModusToolbox™. Exact commands for programming images are provided in the corresponding platform readme files.
-To protect user image from unwanted read - Upgrade Image Encryption can be applied. The ECDH/HKDF with EC256 scheme is used in a given solution as well as mbedTLS as a crypto provider.
-
-To enable image encryption support use `ENC_IMG=1` build flag (BlinkyApp should also be built with this flash set 1).
-
-User is also responsible for providing corresponding binary key data in `enc_priv_key[]` (file `\MCUBootApp\keys.c`). The public part will be used by imgtool when signing and encrypting upgrade image. Signing image with encryption is described in `\BlinkyApp\Readme.md`.
-
-After MCUBootApp is built with these settings unencrypted and encrypted images will be accepted in secondary (upgrade) slot.
-
-Example command:
-
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug MCUBOOT_IMAGE_NUMBER=1 ENC_IMG=1
-
-__NOTE__: Debug configuration of MCUBootApp with multi image encrypted upgrades in external flash (built with flags `BUILDCFG=Debug` `MCUBOOT_IMG_NUMBER=2 USE_EXTERNAL_FLASH=1 ENC_IMG=1`) is set to use optimization level `-O2 -g3` to fit into `0x18000` allocated for `MCUBootApp`.
-
-### Programming Solution
-
-There are couple ways of programming MCUBootApp firmware. Following instructions assume usage of one of Cypress development kits `CY8CPROTO_062_4343W`.
-
-1. Direct usage of OpenOCD.
-
-OpenOCD package is supplied with ModuToolbox IDE and can be found in installation folder under `./tools_2.1/openocd`.
-
-Open terminal application - and execute following command after substitution `PATH_TO_APPLICATION.hex` and `OPENOCD` paths.
-
-Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines.
-
- export OPENOCD=/Applications/ModusToolbox/tools_2.1/openocd
-
- ${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
- -f ${OPENOCD}/scripts/interface/kitprog3.cfg \
- -f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
- -c "init; reset init; program PATH_TO_APPLICATION.hex" \
- -c "resume; reset; exit"
-
-2. Using GUI tool `Cypress Programmer`
+2. Using the GUI tool `Cypress Programmer`
Follow [link](https://www.cypress.com/products/psoc-programming-solutions) to download.
-Connect board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines. Open `Cypress Programmer` and click `Connect`, then choose hex file: `MCUBootApp.hex` or `BlinkyApp.hex` and click `Program`. Check log to ensure programming success. Reset board.
+Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines. Open `Cypress Programmer` and click `Connect`, then choose hex file: `MCUBootApp.hex` or `BlinkyApp.hex` and click `Program`. Check the log to ensure the programming is successful. Reset the board.
3. Using `DAPLINK`.
-Connect board to your computer. Switch embeded Kitprog3 to `DAPLINK` mode by pressing `SW3 MODE` button until `LED2 STATUS` blinks fast and mass storage device appeared in OS. Drag and drop `hex` files you wish to program to `DAPLINK` drive in your OS.
+This mode is currently supported only on PSoC™ 6 development kits.
-### Build Environment Troubleshooting
+Connect the board to your computer. Switch the embedded Kitprog3 to `DAPLINK` mode by clicking the `SW3 MODE` button until `LED2 STATUS` blinks fast and the mass storage device displays on the OS. Drag and drop `hex` files you wish to program to the `DAPLINK` drive in your OS.
+
+### Build environment troubleshooting
Regular shell/terminal combination on Linux and MacOS.
@@ -426,18 +643,11 @@
* Cygwin
* Msys2
-Also IDE may be used:
-* Eclipse / ModusToolbox ("makefile project from existing source")
+Also, an IDE can be used:
+* Eclipse / ModusToolbox™ ("makefile project from existing source")
-*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
+*Make* - ensure that it is added to the system's `PATH` variable and the correct path is the first on the list.
-*Python/Python3* - make sure you have correct path referenced in `PATH`;
+*Python/Python3* - ensure that you have the correct path referenced in `PATH`.
-*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
-
-*Cygwin* - add following to build command `CURDIR=pwd | cygpath --mixed -f -` so that build command looks like that:
-
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M CURDIR=`pwd | cygpath --mixed -f -`
-
-This will iherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.
-
+*Msys2* - To use the systems path, navigate to the msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart the MSYS2 shell. This will inherit the system's path and find `python` installed in the regular way as well as `imgtool` and its dependencies.
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.mk b/boot/cypress/MCUBootApp/MCUBootApp.mk
index 7b9a48a..e6ed9ed 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.mk
+++ b/boot/cypress/MCUBootApp/MCUBootApp.mk
@@ -25,111 +25,31 @@
include host.mk
+APP_NAME := MCUBootApp
+
# Cypress' MCUBoot Application supports GCC ARM only at this moment
# Set default compiler to GCC if not specified from command line
COMPILER ?= GCC_ARM
-USE_CRYPTO_HW ?= 1
-USE_EXTERNAL_FLASH ?= 0
-USE_OVERWRITE ?= 0
+CUR_APP_PATH = $(PRJ_DIR)/$(APP_NAME)
+
+ifneq ($(FLASH_MAP), )
+$(CUR_APP_PATH)/flashmap.mk:
+ $(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/cy_flash_pal/cy_flash_map.h > $(CUR_APP_PATH)/flashmap.mk
+include $(CUR_APP_PATH)/flashmap.mk
+DEFINES_APP := -DCY_FLASH_MAP_JSON
+endif
+
MCUBOOT_IMAGE_NUMBER ?= 1
ENC_IMG ?= 0
-
-# For which core this application is built
-CORE ?= CM0P
+USE_BOOTSTRAP ?= 1
+MCUBOOT_LOG_LEVEL ?= MCUBOOT_LOG_LEVEL_DEBUG
+USE_SHARED_SLOT ?= 0
ifneq ($(COMPILER), GCC_ARM)
$(error Only GCC ARM is supported at this moment)
endif
-CUR_APP_PATH = $(PRJ_DIR)/$(APP_NAME)
-
-include $(PRJ_DIR)/platforms.mk
-include $(PRJ_DIR)/common_libs.mk
-include $(PRJ_DIR)/toolchains.mk
-
-# default slot size is 0x10000 for single image
-# larger slot size is 0x20000 for multi image, 512bytes per row/sector, so 256 sectors will work for both
-MAX_IMG_SECTORS ?= 256
-
-# define slot sizes for IMAGE1 and IMAGE2 in case of usage with
-# external memory upgrade. 0x40000 slot size is acceptable for
-# all platforms in single image case with external upgrade
-ifeq ($(USE_EXTERNAL_FLASH), 1)
-IMAGE_1_SLOT_SIZE ?= 0x40200
-ifeq ($(MCUBOOT_IMAGE_NUMBER), 2)
-IMAGE_2_SLOT_SIZE ?= 0x40200
-endif
-endif
-
-# Application-specific DEFINES
-DEFINES_APP := -DMBEDTLS_CONFIG_FILE="\"mcuboot_crypto_config.h\""
-DEFINES_APP += -DECC256_KEY_FILE="\"keys/$(SIGN_KEY_FILE).pub\""
-DEFINES_APP += -DCORE=$(CORE)
-DEFINES_APP += -DMCUBOOT_IMAGE_NUMBER=$(MCUBOOT_IMAGE_NUMBER)
-
-ifeq ($(USE_OVERWRITE), 1)
-DEFINES_APP += -DMCUBOOT_OVERWRITE_ONLY
-endif
-
-ifeq ($(USE_EXTERNAL_FLASH), 1)
-DEFINES_APP += -DCY_BOOT_USE_EXTERNAL_FLASH
-MAX_IMG_SECTORS = 1536
-DEFINES_APP += -DCY_BOOT_IMAGE_1_SIZE=$(IMAGE_1_SLOT_SIZE)
-ifeq ($(MCUBOOT_IMAGE_NUMBER), 2)
-DEFINES_APP += -DCY_BOOT_IMAGE_2_SIZE=$(IMAGE_2_SLOT_SIZE)
-endif
-endif
-
-DEFINES_APP += -DMCUBOOT_MAX_IMG_SECTORS=$(MAX_IMG_SECTORS)
-# Hardrware acceleration support
-ifeq ($(USE_CRYPTO_HW), 1)
-DEFINES_APP += -DMBEDTLS_USER_CONFIG_FILE="\"mcuboot_crypto_acc_config.h\""
-DEFINES_APP += -DCY_CRYPTO_HAL_DISABLE
-DEFINES_APP += -DCY_MBEDTLS_HW_ACCELERATION
-endif
-# Encrypted image support
-ifeq ($(ENC_IMG), 1)
-DEFINES_APP += -DENC_IMG=1
-# Use higher optimization level for enc image in multi image mode
-# with external flash so it would fit into 0x18000 size of MCUBootApp
-ifeq ($(BUILDCFG), Debug)
-ifeq ($(MCUBOOT_IMAGE_NUMBER), 2)
-ifeq ($(USE_EXTERNAL_FLASH), 1)
-CFLAGS_OPTIMIZATION := -O2 -g3
-endif
-endif
-endif
-endif
-
-# Collect MCUBoot sourses
-SOURCES_MCUBOOT := $(wildcard $(CURDIR)/../bootutil/src/*.c)
-# Collect MCUBoot Application sources
-SOURCES_APP_SRC := $(wildcard $(CUR_APP_PATH)/*.c)
-
-# Collect Flash Layer port sources
-SOURCES_FLASH_PORT := $(wildcard $(CURDIR)/cy_flash_pal/*.c)
-SOURCES_FLASH_PORT += $(wildcard $(CURDIR)/cy_flash_pal/flash_qspi/*.c)
-# Collect all the sources
-SOURCES_APP := $(SOURCES_MCUBOOT)
-SOURCES_APP += $(SOURCES_APP_SRC)
-SOURCES_APP += $(SOURCES_FLASH_PORT)
-
-INCLUDE_DIRS_MCUBOOT := $(addprefix -I, $(CURDIR)/../bootutil/include)
-INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(CURDIR)/../bootutil/src)
-INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(CURDIR)/..)
-
-INCLUDE_DIRS_APP := $(addprefix -I, $(CURDIR))
-INCLUDE_DIRS_APP += $(addprefix -I, $(CURDIR)/cy_flash_pal/flash_qspi)
-INCLUDE_DIRS_APP += $(addprefix -I, $(CURDIR)/cy_flash_pal/include)
-INCLUDE_DIRS_APP += $(addprefix -I, $(CURDIR)/cy_flash_pal/include/flash_map_backend)
-INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH))
-INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH)/config)
-INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH)/os)
-
-ASM_FILES_APP :=
-ASM_FILES_APP += $(ASM_FILES_STARTUP)
-
# Output folder
OUT := $(APP_NAME)/out
# Output folder to contain build artifacts
@@ -137,9 +57,198 @@
OUT_CFG := $(OUT_TARGET)/$(BUILDCFG)
-# Overwite path to linker script if custom is required
+include $(PRJ_DIR)/platforms.mk
+include $(PRJ_DIR)/common_libs.mk
+include $(PRJ_DIR)/toolchains.mk
+
+ifeq ($(MAX_IMG_SECTORS), )
+MAX_IMG_SECTORS ?= $(PLATFORM_MAX_IMG_SECTORS)
+endif
+
+# Application-specific DEFINES
+DEFINES_APP += -DMBEDTLS_CONFIG_FILE="\"mcuboot_crypto_config.h\""
+DEFINES_APP += -DECC256_KEY_FILE="\"keys/$(SIGN_KEY_FILE).pub\""
+DEFINES_APP += -D$(CORE)
+DEFINES_APP += -DMCUBOOT_IMAGE_NUMBER=$(MCUBOOT_IMAGE_NUMBER)
+DEFINES_APP += -DUSE_SHARED_SLOT=$(USE_SHARED_SLOT)
+
+# Define MCUboot size and pass it to linker script
+BOOTLOADER_SIZE ?= $(PLATFORM_BOOTLOADER_SIZE)
+LDFLAGS_DEFSYM += -Wl,--defsym,BOOTLOADER_SIZE=$(BOOTLOADER_SIZE)
+
+
+APP_DEFAULT_POLICY ?= $(PLATFORM_APP_DEFAULT_POLICY)
+
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+ifeq ($(USE_XIP), 1)
+DEFINES_APP += -DUSE_XIP
+endif
+DEFINES_APP += -DCY_BOOT_USE_EXTERNAL_FLASH
+DEFINES_APP += -DCY_MAX_EXT_FLASH_ERASE_SIZE=$(PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE)
+endif
+
+ifeq ($(USE_OVERWRITE), 1)
+DEFINES_APP += -DMCUBOOT_OVERWRITE_ONLY
+ifeq ($(USE_SW_DOWNGRADE_PREV), 1)
+DEFINES_APP += -DMCUBOOT_DOWNGRADE_PREVENTION
+endif
+else
+ifeq ($(USE_BOOTSTRAP), 1)
+DEFINES_APP += -DMCUBOOT_BOOTSTRAP
+endif
+endif
+DEFINES_APP += -DMCUBOOT_MAX_IMG_SECTORS=$(MAX_IMG_SECTORS)
+DEFINES_APP += -DMCUBOOT_LOG_LEVEL=$(MCUBOOT_LOG_LEVEL)
+ifeq ($(USE_HW_ROLLBACK_PROT), 1)
+DEFINES_APP += -DMCUBOOT_HW_ROLLBACK_PROT
+# Service RAM app address (size 0x8000)
+DEFINES_APP += -DSERVICE_APP_OFFSET=$(PLATFORM_SERVICE_APP_OFFSET)
+# Service RAM app input parameters address (size 0x400)
+DEFINES_APP += -DSERVICE_APP_INPUT_PARAMS_OFFSET=$(PLATFORM_SERVICE_APP_INPUT_PARAMS_OFFSET)
+# Service RAM app descriptor addr (size 0x20)
+DEFINES_APP += -DSERVICE_APP_DESC_OFFSET=$(PLATFORM_SERVICE_APP_DESC_OFFSET)
+# Service RAM app size
+DEFINES_APP += -DSERVICE_APP_SIZE=$(PLATFORM_SERVICE_APP_SIZE)
+endif
+# Hardrware acceleration support
+ifeq ($(USE_CRYPTO_HW), 1)
+DEFINES_APP += -DMBEDTLS_USER_CONFIG_FILE="\"mcuboot_crypto_acc_config.h\""
+DEFINES_APP += -DCY_CRYPTO_HAL_DISABLE
+DEFINES_APP += -DCY_MBEDTLS_HW_ACCELERATION
+endif
+
+# Compile with user redefined values for UART HW, port, pins
+ifeq ($(USE_CUSTOM_DEBUG_UART), 1)
+DEFINES_APP += -DUSE_CUSTOM_DEBUG_UART=1
+endif
+
+# Encrypted image support
+ifeq ($(ENC_IMG), 1)
+DEFINES_APP += -DENC_IMG=1
+ifeq ($(PLATFORM), CYW20829)
+DEFINES_APP += -DMCUBOOT_ENC_IMAGES_XIP
+endif
+# Use maximum optimization level for PSOC6 encrypted image with
+# external flash so it would fit into 0x18000 size of MCUBootApp
+ifneq ($(PLATFORM), CYW20829)
+ifeq ($(BUILDCFG), Debug)
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+CFLAGS_OPTIMIZATION := -Os -g3
+endif
+endif
+endif
+endif
+
+
+# Collect MCUBoot sourses
+SOURCES_MCUBOOT := $(wildcard $(PRJ_DIR)/../bootutil/src/*.c)
+# Collect MCUBoot Application sources
+SOURCES_APP_SRC := main.c cy_security_cnt.c keys.c
+
+# Collect Flash Layer sources and header files dirs
+INCLUDE_DIRS_FLASH := $(PLATFORM_INCLUDE_DIRS_FLASH)
+INCLUDE_DIRS_UTILS := $(PLATFORM_INCLUDE_DIRS_UTILS)
+SOURCES_FLASH := $(PLATFORM_SOURCES_FLASH)
+
+# Collect all the sources
+SOURCES_APP := $(SOURCES_MCUBOOT)
+SOURCES_APP += $(SOURCES_FLASH)
+SOURCES_APP += $(addprefix $(CUR_APP_PATH)/, $(SOURCES_APP_SRC))
+SOURCES_APP += $(PLATFORM_APP_SOURCES)
+
+INCLUDE_DIRS_MCUBOOT := $(addprefix -I, $(PRJ_DIR)/../bootutil/include)
+INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(PRJ_DIR)/../bootutil/src)
+INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(PRJ_DIR)/..)
+
+INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR))
+INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH))
+INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH)/config)
+INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH)/os)
+INCLUDE_DIRS_APP += $(addprefix -I, $(INCLUDE_DIRS_FLASH))
+INCLUDE_DIRS_APP += $(addprefix -I, $(INCLUDE_DIRS_UTILS))
+
+ASM_FILES_APP :=
+ASM_FILES_APP += $(ASM_FILES_STARTUP)
+
+# Pass variables to linker script and overwrite path to it, if custom is required
ifeq ($(COMPILER), GCC_ARM)
-LINKER_SCRIPT := $(subst /cygdrive/c,c:,$(CUR_APP_PATH)/$(APP_NAME).ld)
+LDFLAGS += $(LDFLAGS_DEFSYM)
+LINKER_SCRIPT := $(CUR_APP_PATH)/$(APP_NAME)_$(CORE).ld
else
$(error Only GCC ARM is supported at this moment)
-endif
\ No newline at end of file
+endif
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### MCUBootApp.mk ####)
+$(info APP_DEFAULT_POLICY --> $(APP_DEFAULT_POLICY))
+$(info APP_NAME <-> $(APP_NAME))
+$(info ASM_FILES_APP --> $(ASM_FILES_APP))
+$(info ASM_FILES_STARTUP <-- $(ASM_FILES_STARTUP))
+$(info BOOTLOADER_SIZE <-> $(BOOTLOADER_SIZE))
+$(info BUILDCFG <-- $(BUILDCFG))
+$(info CFLAGS_OPTIMIZATION --> $(CFLAGS_OPTIMIZATION))
+$(info COMPILER <-> $(COMPILER))
+$(info CORE <-- $(CORE))
+$(info CUR_APP_PATH <-- $(CUR_APP_PATH))
+$(info DEFINES_APP --> $(DEFINES_APP))
+$(info ENC_IMG <-> $(ENC_IMG))
+$(info EXTERNAL_FLASH_PRIMARY_2_OFFSET <-> $(EXTERNAL_FLASH_PRIMARY_2_OFFSET))
+$(info EXTERNAL_FLASH_SCRATCH_OFFSET <-> $(EXTERNAL_FLASH_SCRATCH_OFFSET))
+$(info EXTERNAL_FLASH_SECONDARY_1_OFFSET <-> $(EXTERNAL_FLASH_SECONDARY_1_OFFSET))
+$(info EXTERNAL_FLASH_SECONDARY_2_OFFSET <-> $(EXTERNAL_FLASH_SECONDARY_2_OFFSET))
+$(info FLASH_MAP <-- $(FLASH_MAP))
+$(info IMAGE_1_SLOT_SIZE <-> $(IMAGE_1_SLOT_SIZE))
+$(info IMAGE_2_SLOT_SIZE <-> $(IMAGE_2_SLOT_SIZE))
+$(info INCLUDE_DIRS_APP --> $(INCLUDE_DIRS_APP))
+$(info INCLUDE_DIRS_FLASH <-> $(INCLUDE_DIRS_FLASH))
+$(info INCLUDE_DIRS_MCUBOOT --> $(INCLUDE_DIRS_MCUBOOT))
+$(info LDFLAGS --> $(LDFLAGS))
+$(info LDFLAGS_DEFSYM <-> $(LDFLAGS_DEFSYM))
+$(info LINKER_SCRIPT --> $(LINKER_SCRIPT))
+$(info MAX_IMG_SECTORS <-> $(MAX_IMG_SECTORS))
+$(info MCUBOOT_IMAGE_NUMBER <-> $(MCUBOOT_IMAGE_NUMBER))
+$(info MCUBOOT_LOG_LEVEL <-> $(MCUBOOT_LOG_LEVEL))
+$(info OUT <-> $(OUT))
+$(info OUT_CFG --> $(OUT_CFG))
+$(info OUT_TARGET <-> $(OUT_TARGET))
+$(info PLATFORM <-- $(PLATFORM))
+$(info PLATFORM_APP_DEFAULT_POLICY <-- $(PLATFORM_APP_DEFAULT_POLICY))
+$(info PLATFORM_APP_SOURCES <-- $(PLATFORM_APP_SOURCES))
+$(info PLATFORM_BOOTLOADER_SIZE <-- $(PLATFORM_BOOTLOADER_SIZE))
+$(info PLATFORM_CHUNK_SIZE <-- $(PLATFORM_CHUNK_SIZE))
+$(info PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE <-- $(PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE))
+$(info PLATFORM_EXTERNAL_FLASH_PRIMARY_2_OFFSET <-- $(PLATFORM_EXTERNAL_FLASH_PRIMARY_2_OFFSET))
+$(info PLATFORM_EXTERNAL_FLASH_SCRATCH_OFFSET <-- $(PLATFORM_EXTERNAL_FLASH_SCRATCH_OFFSET))
+$(info PLATFORM_EXTERNAL_FLASH_SECONDARY_1_OFFSET <-- $(PLATFORM_EXTERNAL_FLASH_SECONDARY_1_OFFSET))
+$(info PLATFORM_EXTERNAL_FLASH_SECONDARY_2_OFFSET <-- $(PLATFORM_EXTERNAL_FLASH_SECONDARY_2_OFFSET))
+$(info PLATFORM_IMAGE_1_SLOT_SIZE <-- $(PLATFORM_IMAGE_1_SLOT_SIZE))
+$(info PLATFORM_IMAGE_2_SLOT_SIZE <-- $(PLATFORM_IMAGE_2_SLOT_SIZE))
+$(info PLATFORM_INCLUDE_DIRS_FLASH <-- $(PLATFORM_INCLUDE_DIRS_FLASH))
+$(info PLATFORM_MAX_IMG_SECTORS <-- $(PLATFORM_MAX_IMG_SECTORS))
+$(info PLATFORM_SCRATCH_SIZE <-- $(PLATFORM_SCRATCH_SIZE))
+$(info PLATFORM_SERVICE_APP_DESC_OFFSET <-- $(PLATFORM_SERVICE_APP_DESC_OFFSET))
+$(info PLATFORM_SERVICE_APP_INPUT_PARAMS_OFFSET <-- $(PLATFORM_SERVICE_APP_INPUT_PARAMS_OFFSET))
+$(info PLATFORM_SERVICE_APP_OFFSET <-- $(PLATFORM_SERVICE_APP_OFFSET))
+$(info PLATFORM_SERVICE_APP_SIZE <-- $(PLATFORM_SERVICE_APP_SIZE))
+$(info PLATFORM_SOURCES_FLASH <-- $(PLATFORM_SOURCES_FLASH))
+$(info PLATFORM_STATUS_PARTITION_OFFSET <-- $(PLATFORM_STATUS_PARTITION_OFFSET))
+$(info PRJ_DIR <-- $(PRJ_DIR))
+$(info PYTHON_PATH <-- $(PYTHON_PATH))
+$(info SCRATCH_SIZE <-> $(SCRATCH_SIZE))
+$(info SIGN_KEY_FILE <-- $(SIGN_KEY_FILE))
+$(info SOURCES_APP --> $(SOURCES_APP))
+$(info SOURCES_APP_SRC <-> $(SOURCES_APP_SRC))
+$(info SOURCES_FLASH <-> $(SOURCES_FLASH))
+$(info SOURCES_MCUBOOT <-> $(SOURCES_MCUBOOT))
+$(info STATUS_PARTITION_OFFSET <-> $(STATUS_PARTITION_OFFSET))
+$(info USE_BOOTSTRAP <-> $(USE_BOOTSTRAP))
+$(info USE_CRYPTO_HW <-- $(USE_CRYPTO_HW))
+$(info USE_CUSTOM_DEBUG_UART <-- $(USE_CUSTOM_DEBUG_UART))
+$(info USE_CUSTOM_MEMORY_MAP <-- $(USE_CUSTOM_MEMORY_MAP))
+$(info USE_EXTERNAL_FLASH <-- $(USE_EXTERNAL_FLASH))
+$(info USE_HW_ROLLBACK_PROT <-- $(USE_HW_ROLLBACK_PROT))
+$(info USE_OVERWRITE <-- $(USE_OVERWRITE))
+$(info USE_XIP <-- $(USE_XIP))
+endif
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
similarity index 87%
rename from boot/cypress/MCUBootApp/MCUBootApp.ld
rename to boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
index c78c598..9d9a32d 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
@@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cy8c6xxa_cm0plus.ld
-* \version 2.60
+* \version 2.91
*
* Linker file for the GNU C compiler.
*
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -40,7 +40,7 @@
GROUP(-lgcc -lc -lnosys)
ENTRY(Reset_Handler)
-/* Size of the stack section at the end of CM0+ SRAM */
+/* The size of the stack section at the end of CM0+ SRAM */
STACK_SIZE = 0x1000;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
@@ -63,9 +63,16 @@
* Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
*/
- public_ram (rw) : ORIGIN = 0x08000000, LENGTH = 0x800
ram (rwx) : ORIGIN = 0x08000800, LENGTH = 0x1F800
- flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x18000
+ flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x17E90
+ smif_struct (rx) : ORIGIN = 0x10017E90, LENGTH = 0x170
+
+ /* This is an unprotected public RAM region, with the placed .cy_sharedmem.
+ * This region is used to place objects that require full access from both cores.
+ * Uncomment the following line, define the region origin and length, and uncomment the placement of
+ * the .cy_sharedmem section below.
+ */
+ public_ram (rw) : ORIGIN = 0x08000000, LENGTH = 0x800
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
@@ -165,6 +172,11 @@
KEEP(*(.eh_frame*))
} > flash
+ /* place SMIF config structures here */
+ .smif_struct ORIGIN(smif_struct) :
+ {
+ KEEP(*(.smif_struct)) /* keep my variable even if not referenced */
+ } > smif_struct
.ARM.extab :
{
@@ -216,16 +228,6 @@
__etext = . ;
- /* Set stack top to end of RAM, and stack limit move down by
- * size of stack_dummy section */
- __StackTop = ORIGIN(ram) + LENGTH(ram);
- __StackLimit = __StackTop - STACK_SIZE ;
- PROVIDE(__stack = __StackTop);
-
- .stackSpace (NOLOAD) : ALIGN(8)
- {
- . = . + STACK_SIZE ;
- } > ram
.ramVectors (NOLOAD) : ALIGN(8)
{
@@ -234,18 +236,10 @@
__ram_vectors_end__ = .;
} > ram
- /* Unprotected public RAM */
- .cy_sharedmem (NOLOAD):
- {
- . = ALIGN(4);
- __public_ram_start__ = .;
- KEEP(*(.cy_sharedmem))
- . = ALIGN(4);
- __public_ram_end__ = .;
- } > public_ram
- .data __ram_vectors_end__ : AT (__etext)
+ .data __ram_vectors_end__ :
{
+ . = ALIGN(4);
__data_start__ = .;
*(vtable)
@@ -279,7 +273,12 @@
__data_end__ = .;
- } > ram
+ } > ram AT>flash
+
+
+ /* Check if code and .data region exceeds FLASH image limit */
+ __FlashImageSize = __etext - ORIGIN(flash) + SIZEOF(.data);
+ ASSERT( __FlashImageSize <= BOOTLOADER_SIZE, "Resulting image does not fit into MCUboot flash region")
/* Place variables in the section that should not be initialized during the
@@ -313,17 +312,49 @@
__bss_end__ = .;
} > ram
+
.heap (NOLOAD):
{
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
- . = ORIGIN(ram) + LENGTH(ram);
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
+ /* To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.*/
+ /*
+ .cy_sharedmem (NOLOAD):
+ {
+ . = ALIGN(4);
+ __public_ram_start__ = .;
+ KEEP(*(.cy_sharedmem))
+ . = ALIGN(4);
+ __public_ram_end__ = .;
+ } > public_ram
+ */
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
/* Emulated EEPROM Flash area */
.cy_em_eeprom :
{
@@ -369,9 +400,11 @@
/* Places the code in the Execute in Place (XIP) section. See the smif driver
* documentation for details.
*/
- .cy_xip :
+ cy_xip :
{
+ __cy_xip_start = .;
KEEP(*(.cy_xip))
+ __cy_xip_end = .;
} > xip
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch b/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch
deleted file mode 100644
index c23487b..0000000
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch
+++ /dev/null
@@ -1,62 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="false"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
-<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${cy_tools_path:openocd}/bin/openocd"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s "${cy_tools_path:openocd}/scripts" -s "${workspace_loc}/boot/cypress" -c "source [find interface/kitprog3.cfg]" -c "source [find target/psoc6_2m.cfg]" -c "puts stderr {Started by GNU MCU Eclipse}""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
-<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value=""/>
-<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="./out/PSOC_062_2M/Debug/MCUBootApp.elf"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="false"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="./out/PSOC_062_2M/Debug/MCUBootApp.elf"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_sdk_install_dir}/tools/gcc-7.2.1-1.0/bin/arm-none-eabi-gdb${cy_exe_platform_ext}"/>
-<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="boot/cypress/MCUBootApp/out/PSOC_062_2M/Debug/MCUBootApp.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="cy_mcuboot"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/cy_mcuboot"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"> <memoryBlockExpression address="268566528" label="0x10020000"/> <memoryBlockExpression address="268632064" label="0x10030000"/> </memoryBlockExpressionList> "/>
-<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld
new file mode 100644
index 0000000..e98f9e5
--- /dev/null
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld
@@ -0,0 +1,494 @@
+/***************************************************************************//**
+* \file cyw20829_ns.ld
+* \version 1.0.0
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+GROUP(-lgcc -lc -lnosys )
+SEARCH_DIR(.)
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM33 SRAM */
+STACK_SIZE = 0x2400;
+
+FLASH_START_ADDR_SAHB = 0x60000000;
+FLASH_START_ADDR_CBUS = 0x08000000;
+RAM_START_ADDR_SAHB = 0x20000000;
+RAM_START_ADDR_CBUS = 0x04000000;
+RAM_END_ADDR_SAHB = 0x20020000; /* 128K */
+RAM_END_ADDR_CBUS = 0x04020000; /* 128K */
+FLASH_END_ADDR_SAHB = 0x60080000; /* 512K */
+
+BOOTSTRAP_OFFSET_FLASH = 0x00000050; /* toc2=0x10, l1_desc=0x1C, sign_header=0x20, padding=0x4 (encrypted data should be aligned to 0x10 boundary) */
+BOOTSTRAP_OFFSET_RAM = 0x0001E000; /* was 0x00004000 Modify this value to change the size of Bootstrap code + Data */
+APPCODE_OFFSET_FLASH = 0x00002200;
+
+RAMVECTORS_ALIGNMENT = 512;
+
+/* Memory reserved for Bootstrap code and data */
+BOOTSTRAP_SIZE = RAM_END_ADDR_SAHB - RAM_START_ADDR_SAHB - BOOTSTRAP_OFFSET_RAM; /* 0x00002000 */
+/* vma for bootstrap code region */
+CODE_VMA = RAM_START_ADDR_CBUS + BOOTSTRAP_OFFSET_RAM; /* 0x0401E000 */
+/* lma for bootstrap code region */
+CODE_LMA = FLASH_START_ADDR_SAHB + BOOTSTRAP_OFFSET_FLASH; /* 0x6000004C */
+/* Maximum bootstrap code + data size */
+CODE_BS_SIZE = BOOTSTRAP_SIZE; /* 8KB */
+/* vma for bootstrap data region */
+DATA_BS_VMA = RAM_START_ADDR_SAHB + BOOTSTRAP_OFFSET_RAM; /* 0x2001E000 */
+/* vma for bootstrap and app data region */
+DATA_VMA = RAM_START_ADDR_SAHB; /* 0x20000000 */
+/* vma for appCodeRam region */
+DATA_CBUS_VMA = RAM_START_ADDR_CBUS; /* 0x04000000 */
+/* lma for bootstrap and app data region */
+DATA_LMA = CODE_LMA + CODE_BS_SIZE; /* 0x6000204C */
+/* data size */
+DATA_SIZE = RAM_END_ADDR_SAHB - DATA_VMA - BOOTSTRAP_SIZE; /* 0x1E000 */
+/* vma for application XIP region */
+XIP_VMA = FLASH_START_ADDR_CBUS + APPCODE_OFFSET_FLASH; /* 0x08002200 */
+/* lma for application XIP region */
+XIP_LMA = FLASH_START_ADDR_SAHB + APPCODE_OFFSET_FLASH; /* 0x60002200 */
+/* size of XIP region */
+XIP_SIZE = FLASH_END_ADDR_SAHB - XIP_LMA;
+/* Total size of SRAM */
+RAM_SIZE = RAM_END_ADDR_SAHB - RAM_START_ADDR_SAHB; /* 0x00020000 */
+/* Size of Bootstrap data is kept same as BOOTSTRAP_SIZE */
+DATA_BS_SIZE = BOOTSTRAP_SIZE;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM33 core.
+ */
+ code (rx) : ORIGIN = CODE_VMA, LENGTH = CODE_BS_SIZE
+ bsData (rwx) : ORIGIN = DATA_BS_VMA, LENGTH = DATA_BS_SIZE
+ appCodeRam (rx) : ORIGIN = DATA_CBUS_VMA, LENGTH = DATA_SIZE
+ data (rwx) : ORIGIN = DATA_VMA, LENGTH = DATA_SIZE
+ xip (rx) : ORIGIN = XIP_VMA, LENGTH = XIP_SIZE
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+SECTIONS
+{
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy RAM_START_ADDR_SAHB (NOLOAD):
+ {
+ __StackLimit = .;
+ KEEP(*(.stack*))
+ . = STACK_SIZE;
+ __StackTop = .;
+ } > data
+
+PROVIDE(__stack = __StackTop);
+
+ __ramVectors_vma__ = ALIGN(RAMVECTORS_ALIGNMENT);
+
+ .ramVectors __ramVectors_vma__ (NOLOAD):
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ . = ALIGN(4);
+ __ram_vectors_end__ = .;
+ } > data
+
+ __appTextRam_vma__ = (__ram_vectors_end__ - RAM_START_ADDR_SAHB) + RAM_START_ADDR_CBUS;
+ __appTextRam_lma__ = (__zero_table_end__ - FLASH_START_ADDR_CBUS) + FLASH_START_ADDR_SAHB;
+ __ezerotable = __zero_table_end__;
+
+ .appTextRam __appTextRam_vma__ : AT (__appTextRam_lma__)
+ {
+ . = ALIGN(4);
+ __app_text_ram_begin__ = .;
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ *cy_smif.o(.text*)
+ *cy_smif_memslot.o(.text*)
+ *cy_smif_sfdp.o(.text*)
+ *cy_gpio.o(.text*)
+ *cy_smif_hybrid_sect.o(.text*)
+
+ . = ALIGN(4);
+ __app_text_ram_end__ = .;
+
+ } > appCodeRam
+
+ __data_vma__ = (__app_text_ram_end__ - RAM_START_ADDR_CBUS) + RAM_START_ADDR_SAHB;
+ __data_lma__ = (__app_text_ram_end__ - __app_text_ram_begin__) + __appTextRam_lma__;
+ __etext = __data_lma__ - FLASH_START_ADDR_SAHB + FLASH_START_ADDR_CBUS;
+
+ .data __data_vma__ : AT (__data_lma__)
+ {
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > data
+
+ /* Check if data is exceeding the flash size */
+ ASSERT((__data_lma__ + (__data_end__ - __data_start__)) <= FLASH_END_ADDR_SAHB, "data section exceeds Flash size !")
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > data
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > data
+
+ /* Use ramining RAM for Heap */
+ __heap_size__ = (RAM_SIZE - ((__bss_end__ - RAM_START_ADDR_SAHB) + (RAM_END_ADDR_CBUS - __bootstrapText_vma__)) - 4);
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ __end1__ = .;
+ end = __end1__;
+ KEEP(*(.heap*))
+ . += __heap_size__;
+ __HeapLimit = .;
+ } > data
+
+ __bootstrapText_vma__ = ORIGIN(code);
+ __bootstrapText_lma__ = CODE_LMA;
+
+ /* Cortex-M33 bootstrap code area */
+ .bootstrapText __bootstrapText_vma__ : AT (__bootstrapText_lma__)
+ {
+ /* Cortex-M33 code vector table */
+ . = ALIGN(4);
+ __bootstrapText_begin = .;
+
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+
+ /* startup code */
+ *ns_start_cyw20829.o(.text*)
+ *ns_system_cyw20829.o(.text*)
+
+ /* drivers */
+ *cy_device.o(.text*)
+ *cy_btss.o(.text*)
+ *cy_sysclk_v2.o(.text*)
+ *cy_syspm_v2.o(.text*)
+ *cy_sysint_v2.o(.text*)
+ *cy_syslib*.o(.text*)
+ *ppu_v1.o(.text*)
+ *cy_mpc.o(.text*)
+ *cy_pd_ppu.o(.text*)
+ *cy_smif.o(.text*)
+ *cy_smif_memslot.o(.text*)
+ *cy_smif_sfdp.o(.text*)
+ *cy_gpio.o(.text*)
+ *cyhal_system.o(.text*)
+ *lib_a-memset.o(.text*)
+ *lib_a-memcpy-stub.o(.text*)
+
+ KEEP(*(.cy_l1func*))
+
+ . = ALIGN(4);
+ __bootstrapText_end = .;
+ } > code
+
+ __bootstrap_zerotable_lma__ = (CODE_LMA + (__bootstrapText_end - __bootstrapText_begin));
+
+ .bootstrapzero.table : AT (__bootstrap_zerotable_lma__)
+ {
+ . = ALIGN(4);
+ __bootstrapzero_table_start__ = .;
+ LONG (__bootstrap_bss_start__)
+ LONG ((__bootstrap_bss_end__ - __bootstrap_bss_start__)/4)
+ . = ALIGN(4);
+ __bootstrapzero_table_end__ = .;
+ } > code
+
+ __bootstrapData_vma__ = ((__bootstrapzero_table_end__ - RAM_START_ADDR_CBUS) + RAM_START_ADDR_SAHB);
+ __bootstrapData_lma__ = (__bootstrap_zerotable_lma__ + (__bootstrapzero_table_end__ - __bootstrapzero_table_start__));
+
+ .bootstrapData __bootstrapData_vma__ : AT (__bootstrapData_lma__)
+ {
+ __bootstrapData_start__ = .;
+ . = ALIGN(4);
+
+ /* startup code */
+ *ns_start_cyw20829.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *ns_system_cyw20829.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ /* drivers */
+ *cy_device.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_btss.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_sysclk_v2.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_syspm_v2.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_sysint_v2.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_syslib.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *ppu_v1.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_mpc.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_pd_ppu.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_smif.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_smif_memslot.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_smif_sfdp.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cy_gpio.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cycfg_qspi_memslot.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *cyhal_system.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *lib_a-memset.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+ *lib_a-memcpy-stub.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.cy_l1data*))
+
+ . = ALIGN(4);
+
+ __bootstrapData_end__ = .;
+ __bootstrap_size_end__ = .;
+ } > bsData
+
+ .bootstrapBss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bootstrap_bss_start__ = .;
+
+ /* startup code */
+ *ns_start_cyw20829.o(.bss* COMMON)
+ *ns_system_cyw20829.o(.bss* COMMON)
+
+ /* drivers */
+ *cy_device.o(.bss* COMMON)
+ *cy_btss.o(.bss* COMMON)
+ *cy_sysclk_v2.o(.bss* COMMON)
+ *cy_syspm_v2.o(.bss* COMMON)
+ *cy_sysint_v2.o(.bss* COMMON)
+ *cy_syslib.o(.bss* COMMON)
+ *ppu_v1.o(.bss* COMMON)
+ *cy_mpc.o(.bss* COMMON)
+ *cy_pd_ppu.o(.bss* COMMON)
+ *cy_smif.o(.bss* COMMON)
+ *cy_smif_memslot.o(.bss* COMMON)
+ *cy_smif_sfdp.o(.bss* COMMON)
+ *cy_gpio.o(.bss* COMMON)
+ *lib_a-memset.o(.bss* COMMON)
+ *lib_a-memcpy-stub.o(.bss* COMMON)
+ KEEP(*(.cy_l1bss*))
+
+ . = ALIGN(4);
+ __bootstrap_bss_end__ = .;
+ } > bsData
+
+ /* Check if bootstrap code + data exceeds RAM limit */
+ ASSERT(__bootstrap_bss_end__ < RAM_END_ADDR_SAHB, "bootstrap region exceeds RAM size !")
+
+ __app_text_vma__ = ORIGIN(xip);
+ __app_text_lma__ = XIP_LMA;
+
+ /* Cortex-M33 application flash area */
+ .appText (__app_text_vma__) : AT (__app_text_lma__)
+ {
+ /* Cortex-M33 flash vector table */
+ . = ALIGN(4);
+ __text_begin = .;
+
+ *(EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o *cy_gpio.o *cy_smif_hybrid_sect.o) .text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ . = ALIGN(4);
+ __text_end = .;
+
+ } > xip
+
+
+ .copy.table : AT (__app_text_lma__ + (__text_end - __text_begin))
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG ((__data_end__ - __data_start__)/4) /* Size */
+
+ /* Copy appTextRam section to RAM */
+ LONG (__ezerotable) /* From */
+ LONG (__ram_vectors_end__) /* To */
+ LONG ((__app_text_ram_end__ - __app_text_ram_begin__)/4) /* Size */
+
+ . = ALIGN(4);
+ __copy_table_end__ = .;
+ } > xip
+
+
+
+ .ARM.extab : AT (__app_text_lma__ + (__text_end - __text_begin) + (__copy_table_end__ - __copy_table_start__))
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > xip
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > xip
+ __exidx_end = .;
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in CAT1B devices */
+ .zero.table : AT (__exidx_end - __app_text_vma__ + __app_text_lma__)
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG ((__bss_end__ - __bss_start__)/4)
+
+ . = ALIGN(4);
+ __zero_table_end__ = .;
+ } > xip
+}
+
+/* start of bootstrap code sahb address */
+__bootstrap_start_addr__ = RAM_START_ADDR_SAHB + BOOTSTRAP_OFFSET_RAM;
+/* bootstrap size */
+__bootstrap_size__ = __bootstrap_size_end__ - __bootstrap_start_addr__;
diff --git a/boot/cypress/MCUBootApp/config/custom_debug_uart_cfg.h b/boot/cypress/MCUBootApp/config/custom_debug_uart_cfg.h
new file mode 100644
index 0000000..9d99c58
--- /dev/null
+++ b/boot/cypress/MCUBootApp/config/custom_debug_uart_cfg.h
@@ -0,0 +1,41 @@
+/********************************************************************************
+* Copyright 2021 Infineon Technologies AG
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CUSTOM_DEBUG_UART_CFG_H)
+#define CUSTOM_DEBUG_UART_CFG_H
+
+#if defined(USE_CUSTOM_DEBUG_UART)
+
+/* Define SCB which will be used as UART. */
+#define CUSTOM_UART_HW SCB1
+
+/* Define SCB number which will be used as UART.
+ * It is 'x' in SCBx
+ * */
+#define CUSTOM_UART_SCB_NUMBER 1
+
+#define CUSTOM_UART_PORT 10
+
+/* define RX pin */
+#define CUSTOM_UART_RX_PIN 0
+
+/* define TX pin */
+#define CUSTOM_UART_TX_PIN 1
+
+#endif /* defined(USE_CUSTOM_DEBUG_UART) */
+
+#endif /* CUSTOM_DEBUG_UART_CFG_H */
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
index eeb15bc..c2b2348 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
@@ -22,7 +22,7 @@
/* Default maximum number of flash sectors per image slot; change
* as desirable. */
#ifndef MCUBOOT_MAX_IMG_SECTORS
-#define MCUBOOT_MAX_IMG_SECTORS 128u
+#define MCUBOOT_MAX_IMG_SECTORS 128U
#endif
/*
@@ -39,6 +39,8 @@
// #define MCUBOOT_SIGN_EC
+//#define MCUBOOT_OVERWRITE_ONLY 1
+
/*
* Upgrade mode
*
@@ -52,10 +54,18 @@
/* #define MCUBOOT_OVERWRITE_ONLY_FAST */
#else
/* Using SWAP w Scratch by default.
- * Comment/Uncomment which is needed. */
-#define MCUBOOT_SWAP_USING_SCRATCH 1
-/* #define MCUBOOT_SWAP_USING_MOVE 1 */
-#define MCUBOOT_SWAP_USING_STATUS 1
+ * Uncomment which is needed. */
+#define MCUBOOT_SWAP_USING_SCRATCH 1
+/* #define MCUBOOT_SWAP_USING_MOVE 1 */
+#define MCUBOOT_SWAP_USING_STATUS 1
+#endif
+
+/* This definition is used in boot_copy_region function to define
+ * minimum size of data chunk to be copied. This most likely is equal
+ * to erase size of target hardware.
+ */
+#ifndef MCUBOOT_PLATFORM_CHUNK_SIZE
+#define MCUBOOT_PLATFORM_CHUNK_SIZE 4096U
#endif
/*
@@ -94,6 +104,12 @@
#endif
/*
+ * Currently there is no configuration option, for this platform,
+ * that enables the system specific mcumgr commands in mcuboot
+ */
+#define MCUBOOT_PERUSER_MGMT_GROUP_ENABLED 0
+
+/*
* Logging
*/
@@ -151,7 +167,30 @@
#ifdef ENC_IMG
#define MCUBOOT_ENC_IMAGES
#define MCUBOOT_ENCRYPT_EC256
-#define NUM_ECC_BYTES (256 / 8)
#endif /* ENC_IMG */
+/*
+ * No direct idle call implemented
+ */
+#define MCUBOOT_CPU_IDLE() \
+ do { \
+ } while (0)
+
+/*
+ * Do not save ENCTLV by default
+ */
+//#define MCUBOOT_SWAP_SAVE_ENCTLV 1
+
+/* INFO: Misc functionality defines */
+/*
+#define MCUBOOT_HW_KEY
+#define MCUBOOT_HW_ROLLBACK_PROT
+#define MCUBOOT_MEASURED_BOOT
+#define MCUBOOT_DATA_SHARING
+*/
+/* Use basic fault injection hardening profile */
+//#define MCUBOOT_FIH_PROFILE_LOW
+
+//#define MCUBOOT_FIH_PROFILE_MEDIUM
+
#endif /* MCUBOOT_CONFIG_H */
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
index 8a91f3f..9869e33 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
@@ -28,6 +28,7 @@
#ifndef MCUBOOT_LOGGING_H
#define MCUBOOT_LOGGING_H
+#include <stdbool.h>
#include <stdio.h>
#define MCUBOOT_LOG_LEVEL_OFF 0
@@ -46,17 +47,23 @@
#define MCUBOOT_LOG_LEVEL MCUBOOT_LOG_LEVEL_INFO
#endif
+#ifdef __BOOTSIM__
int sim_log_enabled(int level);
+#else
+static inline int sim_log_enabled(int level) {
+ (void)level;
+ return 1;
+}
+#endif
-#define sim_log_enabled(x) 1
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_ERROR
#define MCUBOOT_LOG_ERR(_fmt, ...) \
do { \
- if (sim_log_enabled(MCUBOOT_LOG_LEVEL_ERROR)) { \
- fprintf(stderr, "[ERR] " _fmt "\n\r", ##__VA_ARGS__); \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_ERROR) != 0) { \
+ (void)fprintf(stderr, "[ERR] " _fmt "\n\r", ##__VA_ARGS__); \
} \
- } while (0)
+ } while ((bool)0)
#else
#define MCUBOOT_LOG_ERR(...) IGNORE(__VA_ARGS__)
#endif
@@ -64,10 +71,10 @@
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_WARNING
#define MCUBOOT_LOG_WRN(_fmt, ...) \
do { \
- if (sim_log_enabled(MCUBOOT_LOG_LEVEL_WARNING)) { \
- fprintf(stderr, "[WRN] " _fmt "\n\r", ##__VA_ARGS__); \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_WARNING) != 0) { \
+ (void)fprintf(stderr, "[WRN] " _fmt "\n\r", ##__VA_ARGS__); \
} \
- } while (0)
+ } while ((bool)0)
#else
#define MCUBOOT_LOG_WRN(...) IGNORE(__VA_ARGS__)
#endif
@@ -75,10 +82,10 @@
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_INFO
#define MCUBOOT_LOG_INF(_fmt, ...) \
do { \
- if (sim_log_enabled(MCUBOOT_LOG_LEVEL_INFO)) { \
- fprintf(stderr, "[INF] " _fmt "\n\r", ##__VA_ARGS__); \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_INFO) != 0) { \
+ (void)fprintf(stderr, "[INF] " _fmt "\n\r", ##__VA_ARGS__); \
} \
- } while (0)
+ } while ((bool)0)
#else
#define MCUBOOT_LOG_INF(...) IGNORE(__VA_ARGS__)
#endif
@@ -86,10 +93,10 @@
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_DEBUG
#define MCUBOOT_LOG_DBG(_fmt, ...) \
do { \
- if (sim_log_enabled(MCUBOOT_LOG_LEVEL_DEBUG)) { \
- fprintf(stderr, "[DBG] " _fmt "\n\r", ##__VA_ARGS__); \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_DEBUG) != 0) { \
+ (void)fprintf(stderr, "[DBG] " _fmt "\n\r", ##__VA_ARGS__); \
} \
- } while (0)
+ } while ((bool)0)
#else
#define MCUBOOT_LOG_DBG(...) IGNORE(__VA_ARGS__)
#endif
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h b/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h
index b172740..c64be77 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h
@@ -23,6 +23,13 @@
#ifndef MCUBOOT_MBEDTLS_DEVICE_H
#define MCUBOOT_MBEDTLS_DEVICE_H
+#ifdef CYW20829
+
+/* Only SHA256 is accelerated by Cryptolite */
+#define MBEDTLS_SHA256_ALT
+
+#else
+
/* Currently this target supports SHA1 */
// #define MBEDTLS_SHA1_C
@@ -51,4 +58,6 @@
#define MBEDTLS_ECDSA_SIGN_ALT
#define MBEDTLS_ECDSA_VERIFY_ALT
+#endif /* CYW20829 */
+
#endif /* MCUBOOT_MBEDTLS_DEVICE_H */
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h b/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h
index efb1bda..05b29ea 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h
@@ -1607,30 +1607,6 @@
//#define MBEDTLS_SSL_PROTO_SSL3
/**
- * \def MBEDTLS_SSL_PROTO_TLS1
- *
- * Enable support for TLS 1.0.
- *
- * Requires: MBEDTLS_MD5_C
- * MBEDTLS_SHA1_C
- *
- * Comment this macro to disable support for TLS 1.0
- */
-#define MBEDTLS_SSL_PROTO_TLS1
-
-/**
- * \def MBEDTLS_SSL_PROTO_TLS1_1
- *
- * Enable support for TLS 1.1 (and DTLS 1.0 if DTLS is enabled).
- *
- * Requires: MBEDTLS_MD5_C
- * MBEDTLS_SHA1_C
- *
- * Comment this macro to disable support for TLS 1.1 / DTLS 1.0
- */
-#define MBEDTLS_SSL_PROTO_TLS1_1
-
-/**
* \def MBEDTLS_SSL_PROTO_TLS1_2
*
* Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled).
@@ -1762,15 +1738,6 @@
#define MBEDTLS_SSL_SERVER_NAME_INDICATION
/**
- * \def MBEDTLS_SSL_TRUNCATED_HMAC
- *
- * Enable support for RFC 6066 truncated HMAC in SSL.
- *
- * Comment this macro to disable support for truncated HMAC in SSL
- */
-#define MBEDTLS_SSL_TRUNCATED_HMAC
-
-/**
* \def MBEDTLS_SSL_TRUNCATED_HMAC_COMPAT
*
* Fallback to old (pre-2.7), non-conforming implementation of the truncated
@@ -2980,6 +2947,7 @@
* This module is required for the SSL/TLS 1.2 PRF function.
*/
#define MBEDTLS_SHA256_C
+#define MBEDTLS_SHA224_C
/**
* \def MBEDTLS_SHA512_C
diff --git a/boot/cypress/MCUBootApp/cy_security_cnt.c b/boot/cypress/MCUBootApp/cy_security_cnt.c
index 81aa54e..d658345 100644
--- a/boot/cypress/MCUBootApp/cy_security_cnt.c
+++ b/boot/cypress/MCUBootApp/cy_security_cnt.c
@@ -14,8 +14,12 @@
* limitations under the License.
*/
-#include "bootutil/security_cnt.h"
+#if defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT
+
#include <stdint.h>
+#include <string.h>
+#include "bootutil/security_cnt.h"
+#include "cy_security_cnt_platform.h"
fih_int
boot_nv_security_counter_init(void)
@@ -25,20 +29,27 @@
}
fih_int
-boot_nv_security_counter_get(uint32_t image_id, fih_int *security_cnt)
+boot_nv_security_counter_get(uint32_t image_id, fih_uint *security_cnt)
{
(void)image_id;
- *security_cnt = 30;
+ fih_int fih_ret = FIH_FAILURE;
- return 0;
+ if (NULL != security_cnt) {
+ FIH_CALL(platform_security_counter_get, fih_ret, security_cnt);
+ }
+
+ FIH_RET(fih_ret);
}
int32_t
-boot_nv_security_counter_update(uint32_t image_id, uint32_t img_security_cnt)
+boot_nv_security_counter_update(uint32_t image_id, uint32_t img_security_cnt, void * custom_data)
{
(void)image_id;
- (void)img_security_cnt;
+
+ int32_t rc = platform_security_counter_update(img_security_cnt, (uint8_t *)custom_data);
/* Do nothing. */
- return 0;
+ return rc;
}
+
+#endif /* defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/MCUBootApp/cy_serial_flash_prog.c b/boot/cypress/MCUBootApp/cy_serial_flash_prog.c
index 512df93..8bf7d8e 100644
--- a/boot/cypress/MCUBootApp/cy_serial_flash_prog.c
+++ b/boot/cypress/MCUBootApp/cy_serial_flash_prog.c
@@ -42,6 +42,10 @@
extern "C" {
#endif
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
typedef struct
{
const cy_stc_smif_block_config_t * smifCfg; /* Pointer to SMIF top-level configuration */
@@ -64,7 +68,11 @@
CY_SECTION(".cy_sflash_user_data") __attribute__( (used) )
/* const stc_smif_ipblocks_arr_t smifIpBlocksArr = {&smifBlockConfig_sfdp, 0x00000000}; */
/* if used zero-pointer to config, DAP link will use hardcoded config for CY8CPROTO-062-4343W */
-const stc_smif_ipblocks_arr_t smifIpBlocksArr = {0x00000000, 0x00000000};
+static const stc_smif_ipblocks_arr_t smifIpBlocksArr =
+{
+ .smifCfg = &smifBlockConfig,
+ .null_t = 0x00000000
+};
/**
* This data is used to populate the table of contents part 2. When present, it is used by the boot
@@ -75,7 +83,7 @@
* or by running 'cymcuelftool -S' to recompute the checksum.
*/
CY_SECTION(".cy_toc_part2") __attribute__( (used) )
-const uint32_t cyToc[128] =
+static const uint32_t cyToc[128] =
{
0x200-4, /* Offset=0x0000: Object Size, bytes */
0x01211220, /* Offset=0x0004: Magic Number (TOC Part 2, ID) */
@@ -93,6 +101,8 @@
/** \} group_serial_flash_variables */
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+
#if defined(__cplusplus)
}
#endif
diff --git a/boot/cypress/MCUBootApp/keys.c b/boot/cypress/MCUBootApp/keys.c
index 4dbd5af..a3d00a2 100644
--- a/boot/cypress/MCUBootApp/keys.c
+++ b/boot/cypress/MCUBootApp/keys.c
@@ -55,6 +55,7 @@
*
********************************************************************************/
#include <bootutil/sign_key.h>
+#include <bootutil/enc_key.h>
#include <mcuboot_config/mcuboot_config.h>
#if !defined(MCUBOOT_HW_KEY)
@@ -175,7 +176,7 @@
const int bootutil_key_cnt = 1;
#endif /* !MCUBOOT_HW_KEY */
-unsigned char enc_priv_key[] = {
+static const unsigned char enc_priv_key[] = {
0x30, 0x81, 0x87, 0x02, 0x01, 0x00, 0x30, 0x13, 0x06, 0x07, 0x2a, 0x86,
0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x08, 0x2a, 0x86, 0x48, 0xce, 0x3d,
0x03, 0x01, 0x07, 0x04, 0x6d, 0x30, 0x6b, 0x02, 0x01, 0x01, 0x04, 0x20,
diff --git a/boot/cypress/MCUBootApp/libs.mk b/boot/cypress/MCUBootApp/libs.mk
index 3fe8220..da58c88 100644
--- a/boot/cypress/MCUBootApp/libs.mk
+++ b/boot/cypress/MCUBootApp/libs.mk
@@ -26,71 +26,74 @@
################################################################################
# PDL library
################################################################################
+
PDL_VERSION = 121
THIS_APP_PATH = $(PRJ_DIR)/libs
MBEDTLS_PATH = $(PRJ_DIR)/../../ext
-# Add platform folder to build
-SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/*.c)
+# Add watchdog folder to build
SOURCES_WATCHDOG := $(wildcard $(THIS_APP_PATH)/watchdog/*.c)
# Add retartget IO implementation using pdl
-SOURCES_RETARGET_IO_PDL += $(wildcard $(THIS_APP_PATH)/retarget_io_pdl/*.c)
+SOURCES_RETARGET_IO_PDL := $(PLATFORM_SOURCES_RETARGET_IO_PDL)
# Collect dirrectories containing headers for PLATFORM
-INCLUDE_RETARGET_IO_PDL += $(THIS_APP_PATH)/retarget_io_pdl
+INCLUDE_RETARGET_IO_PDL := $(PLATFORM_INCLUDE_RETARGET_IO_PDL)
# PSOC6HAL source files
-SOURCES_HAL += $(THIS_APP_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/cyhal_crypto_common.c
-SOURCES_HAL += $(THIS_APP_PATH)/psoc6hal/COMPONENT_PSOC6HAL/source/cyhal_hwmgr.c
+SOURCES_HAL_MCUB := $(PLATFORM_SOURCES_HAL_MCUB)
+
+# PSOC6HAL include dirs
+INCLUDE_DIRS_HAL_MCUB := $(PLATFORM_INCLUDE_DIRS_HAL_MCUB)
# MbedTLS source files
SOURCES_MBEDTLS := $(wildcard $(MBEDTLS_PATH)/mbedtls/library/*.c)
-SOURCES_MBEDTLS += $(wildcard $(MBEDTLS_PATH)/mbedtls/crypto/library/*.c)
# Collected source files for libraries
-SOURCES_LIBS += $(SOURCES_HAL)
SOURCES_LIBS += $(SOURCES_MBEDTLS)
SOURCES_LIBS += $(SOURCES_WATCHDOG)
-SOURCES_LIBS += $(SOURCES_PLATFORM)
+
+# Collect source files for platform dependent libraries
+SOURCES_LIBS += $(SOURCES_HAL_MCUB)
SOURCES_LIBS += $(SOURCES_RETARGET_IO_PDL)
-# Include platforms folder
-INCLUDE_DIRS_PLATFORM := $(PRJ_DIR)/platforms
-
-# needed for Crypto HW Acceleration and headers inclusion, do not use for peripherals
-# peripherals should be accessed
-INCLUDE_DIRS_HAL := $(THIS_APP_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include
-INCLUDE_DIRS_HAL += $(THIS_APP_PATH)/psoc6hal/include
-INCLUDE_DIRS_HAL += $(THIS_APP_PATH)/psoc6hal/COMPONENT_PSOC6HAL/include/pin_packages
-
-# MbedTLS related include directories
-INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include
-INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include/mbedtls
-INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/crypto/include
-INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/crypto/include/mbedtls
-
# Watchdog related includes
INCLUDE_DIRS_WATCHDOG := $(THIS_APP_PATH)/watchdog
+# MbedTLS related include directories
+INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include
+INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include/mbedtls
+INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include/psa
+INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/library
+
# Collected include directories for libraries
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_WATCHDOG))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS))
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_RETARGET_IO_PDL))
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_PLATFORM))
-################################################################################
-# mbedTLS hardware acceleration settings
-################################################################################
-ifeq ($(USE_CRYPTO_HW), 1)
-# cy-mbedtls-acceleration related include directories
-INCLUDE_DIRS_MBEDTLS_MXCRYPTO := $(THIS_APP_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO
-# Collect source files for MbedTLS acceleration
-SOURCES_MBEDTLS_MXCRYPTO := $(wildcard $(THIS_APP_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO/*.c)
-#
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS_MXCRYPTO))
-# Collected source files for libraries
-SOURCES_LIBS += $(SOURCES_MBEDTLS_MXCRYPTO)
+# Collect platform dependent include dirs
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL_MCUB))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_RETARGET_IO_PDL))
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### libs.mk ####)
+$(info INCLUDE_DIRS_HAL_MCUB <-> $(INCLUDE_DIRS_HAL_MCUB))
+$(info INCLUDE_DIRS_LIBS --> $(INCLUDE_DIRS_LIBS))
+$(info INCLUDE_DIRS_MBEDTLS <-> $(INCLUDE_DIRS_MBEDTLS))
+$(info INCLUDE_DIRS_WATCHDOG <-> $(INCLUDE_DIRS_WATCHDOG))
+$(info INCLUDE_RETARGET_IO_PDL <-> $(INCLUDE_RETARGET_IO_PDL))
+$(info MBEDTLS_PATH <-- $(MBEDTLS_PATH))
+$(info PLATFORM_INCLUDE_DIRS_HAL_MCUB <-- $(PLATFORM_INCLUDE_DIRS_HAL_MCUB))
+$(info PLATFORM_INCLUDE_RETARGET_IO_PDL <-- $(PLATFORM_INCLUDE_RETARGET_IO_PDL))
+$(info PLATFORM_SOURCES_HAL_MCUB <-- $(PLATFORM_SOURCES_HAL_MCUB))
+$(info PLATFORM_SOURCES_RETARGET_IO_PDL <-- $(PLATFORM_SOURCES_RETARGET_IO_PDL))
+$(info PRJ_DIR <-- $(PRJ_DIR))
+$(info SOURCES_HAL_MCUB <-> $(SOURCES_HAL_MCUB))
+$(info SOURCES_LIBS --> $(SOURCES_LIBS))
+$(info SOURCES_MBEDTLS <-> $(SOURCES_MBEDTLS))
+$(info SOURCES_RETARGET_IO_PDL <-> $(SOURCES_RETARGET_IO_PDL))
+$(info SOURCES_WATCHDOG <-> $(SOURCES_WATCHDOG))
+$(info THIS_APP_PATH <-- $(THIS_APP_PATH))
endif
diff --git a/boot/cypress/MCUBootApp/main.c b/boot/cypress/MCUBootApp/main.c
index dee1e1a..6097173 100644
--- a/boot/cypress/MCUBootApp/main.c
+++ b/boot/cypress/MCUBootApp/main.c
@@ -17,16 +17,28 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
+#include <inttypes.h>
+#include <stdbool.h>
+
/* Cypress pdl headers */
#include "cy_pdl.h"
-#include "cy_retarget_io_pdl.h"
-#include "cy_result.h"
+#ifdef CYW20829
+#include "cy_retarget_io.h"
+#include "cybsp.h"
+#include "cyhal_wdt.h"
+#include "cyw_20829_utils.h"
+#include "cy_service_app.h"
+#else
+#include "cy_retarget_io_pdl.h"
#include "cycfg_clocks.h"
#include "cycfg_peripherals.h"
-#include "cycfg_pins.h"
+#endif /* CYW20829 */
#include "flash_qspi.h"
+
+#include "cycfg_pins.h"
+#include "cy_result.h"
#include "sysflash/sysflash.h"
#include "flash_map_backend/flash_map_backend.h"
@@ -40,137 +52,261 @@
#include "watchdog.h"
+#define CY_RSLT_MODULE_MCUBOOTAPP 0x500U
+#define CY_RSLT_MODULE_MCUBOOTAPP_MAIN 0x51U
+
+/** General module error */
+#define MCUBOOTAPP_RSLT_ERR \
+ (CY_RSLT_CREATE_EX(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_MCUBOOTAPP, CY_RSLT_MODULE_MCUBOOTAPP_MAIN, 0))
+
/* WDT time out for reset mode, in milliseconds. */
#define WDT_TIME_OUT_MS 4000
-/* Define pins for UART debug output */
-#define CYBSP_UART_ENABLED 1U
-#define CYBSP_UART_HW SCB5
-#define CYBSP_UART_IRQ scb_5_interrupt_IRQn
-
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
/* Choose SMIF slot number (slave select).
* Acceptable values are:
* 0 - SMIF disabled (no external memory);
* 1, 2, 3 or 4 - slave select line memory module is connected to.
*/
-uint32_t smif_id = 1; /* Assume SlaveSelect_0 is used for External Memory */
-#endif
+#define SMIF_ID (1U) /* Assume SlaveSelect_0 is used for External Memory */
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+#define BOOT_MSG_FINISH "MCUBoot Bootloader finished.\n" \
+ "Deinitializing hardware..."
-void hw_deinit(void);
+static void hw_deinit(void);
-static void do_boot(struct boot_rsp *rsp)
+static inline __attribute__((always_inline))
+fih_uint calc_app_addr(uintptr_t flash_base, const struct boot_rsp *rsp)
{
- uint32_t app_addr = 0;
+ return fih_uint_encode(flash_base +
+ rsp->br_image_off +
+ rsp->br_hdr->ih_hdr_size);
+}
- app_addr = (rsp->br_image_off + rsp->br_hdr->ih_hdr_size);
+#ifdef CYW20829
- BOOT_LOG_INF("Starting User Application on CM4 (wait)...");
- BOOT_LOG_INF("Start Address: 0x%08lx", app_addr);
- BOOT_LOG_INF("Deinitializing hardware...");
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
+CY_RAMFUNC_BEGIN /* SMIF will be deinitialized in this case! */
+#else
+inline __attribute__((always_inline))
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
+__NO_RETURN
+static void cyw20829_launch_app(fih_uint app_addr, uint32_t *key, uint32_t *iv)
+{
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
+ qspi_deinit(SMIF_ID);
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
+ cyw20829_RunApp(app_addr, key, iv);
+}
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
+CY_RAMFUNC_END /* SMIF will be deinitialized in this case! */
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
- cy_retarget_io_wait_tx_complete(CYBSP_UART_HW, 10);
+#endif /* CYW20829 */
- hw_deinit();
+static bool do_boot(struct boot_rsp *rsp)
+{
+ uintptr_t flash_base = 0;
- Cy_SysEnableCM4(app_addr);
+#ifdef CYW20829
+ uint32_t *key = NULL;
+ uint32_t *iv = NULL;
+#endif /* CYW20829 */
+
+ if (rsp != NULL) {
+ int rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
+
+ if (0 == rc) {
+ fih_uint app_addr = calc_app_addr(flash_base, rsp);
+
+ BOOT_LOG_INF("Starting User Application (wait)...");
+ if (IS_ENCRYPTED(rsp->br_hdr)) {
+ BOOT_LOG_DBG(" * User application is encrypted");
+ }
+ BOOT_LOG_INF("Start slot Address: 0x%08" PRIx32, (uint32_t)fih_uint_decode(app_addr));
+
+ rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
+ if ((rc != 0) || fih_uint_not_eq(calc_app_addr(flash_base, rsp), app_addr)) {
+ return false;
+ }
+
+#ifdef CYW20829
+#ifdef MCUBOOT_ENC_IMAGES_XIP
+ if (IS_ENCRYPTED(rsp->br_hdr)) {
+ key = rsp->xip_key;
+ iv = rsp->xip_iv;
+ } else {
+ BOOT_LOG_ERR("User image is not encrypted, while MCUBootApp is compiled with encryption support.");
+ return false;
+ }
+#endif /* MCUBOOT_ENC_IMAGES_XIP */
+ /* This function does not return */
+ BOOT_LOG_INF(BOOT_MSG_FINISH);
+ hw_deinit();
+ cyw20829_launch_app(app_addr, key, iv);
+#else
+ /* This function turns on CM4 and returns */
+ BOOT_LOG_INF(BOOT_MSG_FINISH);
+
+ hw_deinit();
+#ifdef USE_XIP
+ BOOT_LOG_DBG("XIP: Switch to SMIF XIP mode");
+ qspi_set_mode(CY_SMIF_MEMORY);
+#endif
+ Cy_SysEnableCM4(fih_uint_decode(app_addr));
+ return true;
+#endif /* CYW20829 */
+ } else {
+ BOOT_LOG_ERR("Flash device ID not found");
+ return false;
+ }
+ }
+
+ return false;
}
int main(void)
{
struct boot_rsp rsp;
- cy_rslt_t rc = CY_RSLT_TYPE_ERROR;
+ cy_rslt_t rc = MCUBOOTAPP_RSLT_ERR;
bool boot_succeeded = false;
fih_int fih_rc = FIH_FAILURE;
+#ifdef CYW20829
+ rc = cybsp_init();
+ if (rc != CY_RSLT_SUCCESS) {
+ CY_ASSERT((bool)0);
+ /* Loop forever... */
+ while (true) {
+ __WFI();
+ }
+ }
+#else
SystemInit();
- //init_cycfg_clocks();
init_cycfg_peripherals();
init_cycfg_pins();
+#endif /* CYW20829 */
+ /* enable interrupts */
+ __enable_irq();
- /* Certain PSoC 6 devices enable CM4 by default at startup. It must be
+ /* Certain PSoC 6 devices enable CM4 by default at startup. It must be
* either disabled or enabled & running a valid application for flash write
* to work from CM0+. Since flash write may happen in boot_go() for updating
* the image before this bootloader app can enable CM4 in do_boot(), we need
* to keep CM4 disabled. Note that debugging of CM4 is not supported when it
* is disabled.
*/
- #if defined(CY_DEVICE_PSOC6ABLE2)
- if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status())
- {
+#ifndef CYW20829
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()) {
Cy_SysDisableCM4();
}
- #endif /* #if defined(CY_DEVICE_PSOC6ABLE2) */
-
- /* enable interrupts */
- __enable_irq();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
/* Initialize retarget-io to use the debug UART port (CYBSP_UART_HW) */
- rc = cy_retarget_io_pdl_init(115200u);
-
- if (rc != CY_RSLT_SUCCESS)
- {
- CY_ASSERT(0);
+ rc = cy_retarget_io_pdl_init(CY_RETARGET_IO_BAUDRATE);
+#else
+ /* Initialize retarget-io to use the debug UART port */
+ rc = cy_retarget_io_init(CYBSP_DEBUG_UART_TX,
+ CYBSP_DEBUG_UART_RX,
+ CY_RETARGET_IO_BAUDRATE);
+#endif /* CYW20829 */
+ if (rc != CY_RSLT_SUCCESS) {
+ CY_ASSERT((bool)0);
+ /* Loop forever... */
+ while (true) {
+ __WFI();
+ }
}
BOOT_LOG_INF("MCUBoot Bootloader Started");
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- rc = CY_SMIF_CMD_NOT_FOUND;
+ {
+ cy_en_smif_status_t qspi_status = qspi_init_sfdp(SMIF_ID);
- rc = qspi_init_sfdp(smif_id);
- if (rc == CY_SMIF_SUCCESS)
- {
- BOOT_LOG_INF("External Memory initialized w/ SFDP.");
+ if (CY_SMIF_SUCCESS == qspi_status) {
+ rc = CY_RSLT_SUCCESS;
+ BOOT_LOG_INF("External Memory initialized w/ SFDP.");
+ } else {
+ rc = MCUBOOTAPP_RSLT_ERR;
+ BOOT_LOG_ERR("External Memory initialization w/ SFDP FAILED: 0x%08" PRIx32, (uint32_t)qspi_status);
+ }
}
- else
- {
- BOOT_LOG_ERR("External Memory initialization w/ SFDP FAILED: 0x%02x", (int)rc);
- }
- if (CY_SMIF_SUCCESS == rc)
-#endif
- {
+ if (CY_RSLT_SUCCESS == rc)
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ {
+#if defined(CYW20829) && defined(MCUBOOT_HW_ROLLBACK_PROT)
+ /* Check service application completion status */
+ if (check_service_app_status() != 0) {
+ BOOT_LOG_ERR("Service application failed");
+ CY_ASSERT((bool)0);
+ /* Loop forever... */
+ while (true) {
+ __WFI();
+ }
+ }
+#endif /* CYW20829 && MCUBOOT_HW_ROLLBACK_PROT */
+
+ (void)memset(&rsp, 0, sizeof(rsp));
FIH_CALL(boot_go, fih_rc, &rsp);
- if (fih_eq(fih_rc, FIH_SUCCESS))
- {
+ if (true == fih_eq(fih_rc, FIH_SUCCESS)) {
BOOT_LOG_INF("User Application validated successfully");
/* initialize watchdog timer. it should be updated from user app
* to mark successful start up of this app. if the watchdog is not updated,
* reset will be initiated by watchdog timer and swap revert operation started
* to roll back to operable image.
*/
- cy_wdg_init(WDT_TIME_OUT_MS);
- do_boot(&rsp);
- boot_succeeded = true;
- }
- else
- {
- BOOT_LOG_INF("MCUBoot Bootloader found none of bootable images");
+#ifdef CYW20829
+ cyhal_wdt_t *cyw20829_wdt = NULL;
+
+ rc = cyhal_wdt_init(cyw20829_wdt, WDT_TIME_OUT_MS);
+#else
+ rc = cy_wdg_init(WDT_TIME_OUT_MS);
+#endif /* CYW20829 */
+ if (CY_RSLT_SUCCESS == rc) {
+
+ boot_succeeded = do_boot(&rsp);
+
+ if (!boot_succeeded) {
+ BOOT_LOG_ERR("Boot of next app failed");
+ }
+ } else {
+ BOOT_LOG_ERR("Failed to init WDT");
+ }
+ } else {
+ BOOT_LOG_ERR("MCUBoot Bootloader found none of bootable images");
}
}
- while (1)
- {
+ while (true) {
if (boot_succeeded) {
- Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
- }
- else {
+ (void)Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
+ } else {
__WFI();
}
}
-
- return 0;
}
-void hw_deinit(void)
+static void hw_deinit(void)
{
+#ifdef CYW20829
+ /* Flush the TX buffer, need to be fixed in retarget_io */
+ Cy_SysLib_Delay(50);
+
+ cy_retarget_io_deinit();
+ cy_wdg_stop();
+ cy_wdg_free();
+ /* Note: qspi_deinit() is called (if needed) in cyw20829_launch_app() above */
+#else
+ cy_retarget_io_wait_tx_complete(CYBSP_UART_HW, 10);
cy_retarget_io_pdl_deinit();
Cy_GPIO_Port_Deinit(CYBSP_UART_RX_PORT);
Cy_GPIO_Port_Deinit(CYBSP_UART_TX_PORT);
-
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- qspi_deinit(smif_id);
-#endif
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) && !defined(USE_XIP)
+ qspi_deinit(SMIF_ID);
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
+#endif /* CYW20829 */
}
diff --git a/boot/cypress/MCUBootApp/sysflash/sysflash.h b/boot/cypress/MCUBootApp/sysflash/sysflash.h
deleted file mode 100644
index 961e74e..0000000
--- a/boot/cypress/MCUBootApp/sysflash/sysflash.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/* Manual version of auto-generated version. */
-
-#ifndef SYSFLASH_H
-#define SYSFLASH_H
-
-#include <stdint.h>
-#include "cy_syslib.h"
-
-#define FLASH_AREA_BOOTLOADER (0)
-#define FLASH_AREA_IMAGE_0 (1u)
-#define FLASH_AREA_IMAGE_1 (2u)
-#define FLASH_AREA_IMAGE_SCRATCH (3u)
-#define FLASH_AREA_IMAGE_2 (5u)
-#define FLASH_AREA_IMAGE_3 (6u)
-#define FLASH_AREA_IMAGE_SWAP_STATUS (7u)
-
-/* it is related to multi-image case */
-#define FLASH_AREA_IMAGE_IDX_1 (0u)
-#define FLASH_AREA_IMAGE_IDX_2 (1u)
-
-/* This defines if External Flash (SMIF) will be used for Upgrade Slots */
-/* #define CY_BOOT_USE_EXTERNAL_FLASH */
-
-/* use PDL-defined offset or one from SMFI config */
-#define CY_SMIF_BASE_MEM_OFFSET (0x18000000)
-
-#define CY_FLASH_ALIGN (CY_FLASH_SIZEOF_ROW)
-#define CY_FLASH_DEVICE_BASE (CY_FLASH_BASE)
-
-#ifndef CY_BOOT_SCRATCH_SIZE
-#ifndef CY_BOOT_USE_EXTERNAL_FLASH
-#define CY_BOOT_SCRATCH_SIZE (0x1000u)
-#else /* CY_BOOT_USE_EXTERNAL_FLASH */
-#define CY_BOOT_SCRATCH_SIZE (0x80000)
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-#endif /* CY_BOOT_SCRATCH_SIZE */
-
-#ifndef CY_BOOT_SWAP_STATUS_SIZE
-#define CY_BOOT_SWAP_STATUS_SIZE (BOOT_SWAP_STATUS_SZ_PRIM + BOOT_SWAP_STATUS_SZ_SEC)
-#endif
-
-#ifndef CY_BOOT_BOOTLOADER_SIZE
-#define CY_BOOT_BOOTLOADER_SIZE (0x18000)
-#endif
-
-/* Sizes of CY_BOOT_IMAGE_1_SIZE and CY_BOOT_IMAGE_2_SIZE
- * can be defined from build system. Use default values otherwise
-*/
-#ifndef CY_BOOT_USE_EXTERNAL_FLASH
-#ifndef CY_BOOT_IMAGE_1_SIZE
-#define CY_BOOT_IMAGE_1_SIZE (0x10000)
-#endif /* CY_BOOT_IMAGE_1_SIZE */
-#if (MCUBOOT_IMAGE_NUMBER == 2)
-#ifndef CY_BOOT_IMAGE_2_SIZE
-#define CY_BOOT_IMAGE_2_SIZE (0x20000)
-#endif /* CY_BOOT_IMAGE_2_SIZE */
-#endif /* (MCUBOOT_IMAGE_NUMBER == 2) */
-#else /* CY_BOOT_USE_EXTERNAL_FLASH */
-#ifndef CY_BOOT_IMAGE_1_SIZE
-#define CY_BOOT_IMAGE_1_SIZE (0xC0000)
-#endif /* CY_BOOT_IMAGE_1_SIZE */
-#if (MCUBOOT_IMAGE_NUMBER == 2)
-#ifndef CY_BOOT_IMAGE_2_SIZE
-#define CY_BOOT_IMAGE_2_SIZE (0xC0000)
-#endif /* CY_BOOT_IMAGE_2_SIZE */
-#endif /* (MCUBOOT_IMAGE_NUMBER == 2) */
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-
-#ifndef CY_BOOT_PRIMARY_1_SIZE
-#define CY_BOOT_PRIMARY_1_SIZE CY_BOOT_IMAGE_1_SIZE
-#endif
-
-#ifndef CY_BOOT_SECONDARY_1_SIZE
-#define CY_BOOT_SECONDARY_1_SIZE CY_BOOT_IMAGE_1_SIZE
-#endif
-
-#if (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
-#ifndef CY_BOOT_PRIMARY_2_SIZE
-#define CY_BOOT_PRIMARY_2_SIZE CY_BOOT_IMAGE_2_SIZE
-#endif
-
-#ifndef CY_BOOT_SECONDARY_2_SIZE
-#define CY_BOOT_SECONDARY_2_SIZE CY_BOOT_IMAGE_2_SIZE
-#endif
-#endif
-
-#ifndef CY_BOOT_EXTERNAL_FLASH_SECONDARY_1_OFFSET
-#define CY_BOOT_EXTERNAL_FLASH_SECONDARY_1_OFFSET (0x0u)
-#endif
-
-#ifndef CY_BOOT_EXTERNAL_FLASH_SECONDARY_2_OFFSET
-#define CY_BOOT_EXTERNAL_FLASH_SECONDARY_2_OFFSET (0x240000u)
-#endif
-
-#ifndef CY_BOOT_EXTERNAL_FLASH_SCRATCH_OFFSET
-#define CY_BOOT_EXTERNAL_FLASH_SCRATCH_OFFSET (0x440000u)
-#endif
-
-#ifndef CY_BOOT_SECONDARY_1_EXT_MEM_OFFSET
-#define CY_BOOT_SECONDARY_1_EXT_MEM_OFFSET (CY_SMIF_BASE_MEM_OFFSET + CY_BOOT_EXTERNAL_FLASH_SECONDARY_1_OFFSET)
-#endif
-
-#ifndef CY_BOOT_SECONDARY_2_EXT_MEM_OFFSET
-#define CY_BOOT_SECONDARY_2_EXT_MEM_OFFSET (CY_SMIF_BASE_MEM_OFFSET + CY_BOOT_EXTERNAL_FLASH_SECONDARY_2_OFFSET)
-#endif
-
-#define BOOT_MAX_SWAP_STATUS_SECTORS (64)
-
-#if (MCUBOOT_IMAGE_NUMBER == 1)
-#define FLASH_AREA_IMAGE_PRIMARY(x) (((x) == 0) ? \
- FLASH_AREA_IMAGE_0 : \
- FLASH_AREA_IMAGE_0)
-#define FLASH_AREA_IMAGE_SECONDARY(x) (((x) == 0) ? \
- FLASH_AREA_IMAGE_1 : \
- FLASH_AREA_IMAGE_1)
-
-#elif (MCUBOOT_IMAGE_NUMBER == 2)
-
-#ifndef CY_FLASH_MAP_EXT_DESC
-#define FLASH_AREA_IMAGE_PRIMARY(x) (((x) == 0) ? \
- FLASH_AREA_IMAGE_0 : \
- ((x) == 1) ? \
- FLASH_AREA_IMAGE_2 : \
- 255)
-#define FLASH_AREA_IMAGE_SECONDARY(x) (((x) == 0) ? \
- FLASH_AREA_IMAGE_1 : \
- ((x) == 1) ? \
- FLASH_AREA_IMAGE_3 : \
- 255)
-#else
-__STATIC_INLINE uint8_t FLASH_AREA_IMAGE_PRIMARY(uint32_t areaID)
-{
- uint8_t result;
-
- if (0U == areaID)
- {
- result = FLASH_AREA_IMAGE_0;
- }
- else
- if (1U == areaID)
- {
- result = FLASH_AREA_IMAGE_2;
- }
- else
- {
- result = 0xFF;
- }
-
- return result;
-}
-
-__STATIC_INLINE uint8_t FLASH_AREA_IMAGE_SECONDARY(uint32_t areaID)
-{
- uint8_t result;
-
- if (0U == areaID)
- {
- result = FLASH_AREA_IMAGE_1;
- }
- else
- if (1U == areaID)
- {
- result = FLASH_AREA_IMAGE_3;
- }
- else
- {
- result = 0xFF;
- }
-
- return result;
-}
-#endif
-#endif
-
-// #else
-// #warning "Image slot and flash area mapping is not defined"
-// #endif
-
-#define CY_IMG_HDR_SIZE 0x400
-
-#ifndef CY_FLASH_MAP_EXT_DESC
-/* Uncomment in case you want to use separately defined table of flash area descriptors */
-/* #define CY_FLASH_MAP_EXT_DESC */
-#endif
-
-#endif /* SYSFLASH_H */
diff --git a/boot/cypress/Makefile b/boot/cypress/Makefile
index b9952c5..d1c9b00 100644
--- a/boot/cypress/Makefile
+++ b/boot/cypress/Makefile
@@ -36,11 +36,14 @@
################################################################################
# Defines whether or not show verbose build output
-MAKEINFO ?= 1
+VERBOSE ?= 0
# Application name by default
APP_NAME ?= MCUBootApp
# Weather or now execute post build script after build - set to 0 for CI
-POST_BUILD ?= 1
+POST_BUILD_ENABLE ?= 1
+
+# Default number of GCC compilation threads
+THREADS_NUM ?= 8
SIGN_KEY_FILE ?= cypress-test-ec-p256
ENC_KEY_FILE ?= enc-ec256-pub
@@ -53,11 +56,20 @@
BUILDCFG ?= Debug
+ifeq ($(PLATFORM), CYW20829)
+# until mbedtls.3.0 support
+USE_CRYPTO_HW ?= 0
+endif
+
# Set of supported applications
APPS := MCUBootApp BlinkyApp
HEADER_OFFSET ?= 0
+# Defines whether or not make all compile warnings into errors for application
+# source code (but not for library source code)
+WARN_AS_ERR ?= 1
+
ifneq ($(filter $(APP_NAME), $(APPS)),)
include ./$(APP_NAME)/$(APP_NAME).mk
include ./$(APP_NAME)/libs.mk
@@ -69,7 +81,8 @@
ASM_FILES += $(ASM_FILES_LIBS)
C_FILES := $(SOURCES_APP)
-C_FILES += $(SOURCES_LIBS)
+C_FILES += $(SOURCES_PLATFORM)
+C_LIBS := $(SOURCES_LIBS)
INCLUDE_DIRS := $(INCLUDE_DIRS_APP)
INCLUDE_DIRS += $(INCLUDE_DIRS_MCUBOOT)
@@ -80,12 +93,13 @@
#INCLUDES := $(addprefix -include , $(INCLUDE_FILES))
O_FILES := $(notdir $(C_FILES:.c=.o)) $(addsuffix .o, $(notdir $(basename $(ASM_FILES))))
+O_LIBS := $(notdir $(C_LIBS:.c=.o))
-DEFINES := $(DEFINES_APP)
+DEFINES := $(DEFINES_APP) -D$(APP_NAME)
DEFINES += $(DEFINES_LIBS)
AS_FLAGS += $(DEFINES)
-ifeq ($(MAKEINFO), 1)
+ifeq ($(VERBOSE), 1)
$(info ==============================================================================)
$(info = Directories to look for header files: =)
$(info ==============================================================================)
@@ -100,26 +114,12 @@
# updating CFLAGS at this point as DEFINES are completed
CFLAGS += $(DEFINES) $(CFLAGS_OPTIMIZATION)
-VPATH = $(dir $(C_FILES) $(ASM_FILES))
+ifeq ($(WARN_AS_ERR), 1)
+CC_WARN_IN_ERR_FLAGS := -Werror
+endif
-#
-# STDE: For cygwin, adjust paths for compiler
-#
-MY_FILES := $(subst /cygdrive/c,c:,$(C_FILES))
-#$(info MY_FILES $(MY_FILES))
-C_FILES=$(MY_FILES)
+VPATH = $(dir $(C_FILES) $(ASM_FILES) $(C_LIBS))
-MY_DIRS := $(subst /cygdrive/c,c:,$(INCLUDE_DIRS))
-#$(info MY_DIRS $(MY_DIRS))
-INCLUDE_DIRS=$(MY_DIRS)
-
-MY_ASM_FILES := $(subst /cygdrive/c,c:,$(ASM_FILES))
-#$(info MY_ASM_FILES $(MY_ASM_FILES))
-ASM_FILES=$(MY_ASM_FILES)
-
-MY_LDFLAGS := $(subst /cygdrive/c,c:,$(LDFLAGS))
-#$(info MY_LDFLAGS $(MY_LDFLAGS))
-LDFLAGS=$(MY_LDFLAGS)
LDFLAGS += $(LDFLAGS_OPTIMIZATION)
# Default name pattern for output files
@@ -127,6 +127,7 @@
OUT_FILE_NAME ?= $(OUT_APP)/$(APP_NAME)
OUT_OBJ := $(OUT_CFG)/obj
+OUT_OBJ_LIBS_DIR := $(OUT_CFG)/obj/libs
OUT_APP := $(OUT_CFG)
.PHONY: all app build clean pre_build post_build
@@ -138,40 +139,62 @@
@`mkdir -p ./$(OUT_TARGET)`
@`mkdir -p ./$(OUT_CFG)`
@`mkdir -p ./$(OUT_OBJ)`
+ @`mkdir -p ./$(OUT_OBJ_LIBS_DIR)`
+ifeq ($(VERBOSE) , 1)
+ @echo
+ @echo ======================== PRE_BUILD STAGE ========================
+ @echo =================================================================
+ @echo
+endif
$(MAKE) pre_build
- $(MAKE) build -j8
+ifeq ($(VERBOSE) , 1)
+ @echo
+ @echo ======================== BUILD STAGE ========================
+ @echo =============================================================
+ @echo
+endif
+ $(MAKE) build -j $(THREADS_NUM)
+ifeq ($(VERBOSE) , 1)
+ @echo
+ @echo ======================== POST_BUILD STAGE ========================
+ @echo ==================================================================
+ @echo
+endif
$(MAKE) post_build
-build: $(OUT_APP)/$(APP_NAME).hex
+build: $(OUT_APP)/$(APP_NAME)_unsigned.hex
$(GCC_PATH)/bin/arm-none-eabi-objdump $(OUT_APP)/$(APP_NAME).elf -S --disassemble > $(OUT_APP)/$(APP_NAME).lst
$(GCC_PATH)/bin/arm-none-eabi-objdump -h $(OUT_APP)/$(APP_NAME).elf
$(GCC_PATH)/bin/arm-none-eabi-size --format=SysV $(OUT_APP)/$(APP_NAME).elf
-$(OUT_APP)/$(APP_NAME).hex: $(OUT_APP)/$(APP_NAME).elf
- $(GCC_PATH)/bin/arm-none-eabi-objcopy --change-addresses=$(HEADER_OFFSET) -O ihex $(OUT_APP)/$(APP_NAME).elf $(OUT_APP)/$(APP_NAME).hex
+$(OUT_APP)/$(APP_NAME)_unsigned.hex: $(OUT_APP)/$(APP_NAME).bin
+ $(GCC_PATH)/bin/arm-none-eabi-objcopy --change-addresses=$(HEADER_OFFSET) -O ihex $(OUT_APP)/$(APP_NAME).elf $(OUT_APP)/$(APP_NAME)_unsigned.hex
-$(OUT_APP)/$(APP_NAME).elf: $(addprefix $(OUT_OBJ)/, $(O_FILES))
+$(OUT_APP)/$(APP_NAME).bin: $(OUT_APP)/$(APP_NAME).elf
+ $(GCC_PATH)/bin/arm-none-eabi-objcopy $(OUT_APP)/$(APP_NAME).elf -S -O binary $(OUT_APP)/$(APP_NAME).bin --remove-section .cy_sflash_user_data --remove-section .cy_toc_part2
+
+$(OUT_APP)/$(APP_NAME).elf: $(addprefix $(OUT_OBJ)/, $(O_FILES)) $(addprefix $(OUT_OBJ_LIBS_DIR)/, $(O_LIBS))
@echo "LD $@"
-ifeq ($(MAKEINFO), 1)
+ifeq ($(VERBOSE), 1)
+ @echo
@echo $(LD) $(O_FILES) $(CC_DEPEND) $(@:.o=.d) -o $@ $(LDFLAGS) -T $(LINKER_SCRIPT) -Wl,-Map,$(OUT_FILE_NAME).map
endif
- @$(LD) $(addprefix $(OUT_OBJ)/, $(O_FILES)) $(CC_DEPEND) $(@:.o=.d) -o $@ $(LDFLAGS) -T $(LINKER_SCRIPT) -Wl,-Map,$(OUT_FILE_NAME).map
+ @$(LD) $(addprefix $(OUT_OBJ)/, $(O_FILES)) $(addprefix $(OUT_OBJ_LIBS_DIR)/, $(O_LIBS)) $(CC_DEPEND) $(@:.o=.d) -o $@ $(LDFLAGS) -T $(LINKER_SCRIPT) -Wl,-Map,$(OUT_FILE_NAME).map
$(OUT_OBJ)/%.o: %.c
@echo "CC $<"
-ifeq ($(MAKEINFO), 1)
- @echo $(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
-endif
- @$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
-ifeq ($(MAKEINFO), 1)
+ifeq ($(VERBOSE), 1)
@echo
+ @echo $(CC) $(CFLAGS) $(CC_WARN_IN_ERR_FLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
endif
+ @$(CC) $(CFLAGS) $(CC_WARN_IN_ERR_FLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
$(OUT_OBJ)/%.o: %.S
@echo "AS $<"
ifeq ($(COMPILER), GCC_ARM)
-ifeq ($(MAKEINFO), 1)
+ifeq ($(VERBOSE), 1)
+ @echo
@echo @$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
endif
@$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
@@ -179,20 +202,28 @@
@echo $(AS) $< -o $@ $(AS_FLAGS)
@$(AS) $< -o $@ $(AS_FLAGS)
endif
-ifeq ($(MAKEINFO), 1)
+
+$(OUT_OBJ_LIBS_DIR)/%.o: %.c
+ @echo "CC $<"
+ifeq ($(VERBOSE), 1)
@echo
+ @echo $(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
endif
+ @$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
clean:
@echo "Cleanup out directory..."
+ rm -f ./$(APP_NAME)/flashmap.mk ./cy_flash_pal/cy_flash_map.h
rm -rf $(OUT_TARGET)/$(BUILDCFG)
clean_boot:
@echo "Cleanup out BOOT directory of $(APP_NAME)..."
+ rm -f ./$(APP_NAME)/flashmap.mk
rm -rf $(OUT_TARGET)/$(BUILDCFG)/boot
clean_upgrade:
@echo "Cleanup out UPGRADE directory of $(APP_NAME)..."
+ rm -f ./$(APP_NAME)/flashmap.mk
rm -rf $(OUT_TARGET)/$(BUILDCFG)/upgrade
run_cppcheck:
@@ -204,10 +235,63 @@
../../scripts/imgtool.py keygen -k keys/$(SIGN_KEY_FILE).pem -t ecdsa-p256
../../scripts/imgtool.py getpub -k keys/$(SIGN_KEY_FILE).pem > keys/$(SIGN_KEY_FILE).pub
-ifeq ($(MAKEINFO) , 1)
-$(info ASM_FILES: $(ASM_FILES))
-$(info C_FILES: $(C_FILES))
-$(info INCLUDE_DIRS: $(INCLUDE_DIRS))
-$(info DEFINES: $(DEFINES))
-$(info CC: $(CC))
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### Makefile ####)
+$(info APPS <-> $(APPS))
+$(info APP_NAME <-> $(APP_NAME))
+$(info AS <-- $(AS))
+$(info ASM_FILES <-> $(ASM_FILES))
+$(info ASM_FILES_APP <-- $(ASM_FILES_APP))
+$(info ASM_FILES_LIBS <-- $(ASM_FILES_LIBS))
+$(info AS_FLAGS <-> $(AS_FLAGS))
+$(info BUILDCFG <-> $(BUILDCFG))
+$(info CC <-- $(CC))
+$(info CC_DEPEND <-- $(CC_DEPEND))
+$(info CC_WARN_IN_ERR_FLAGS <-> $(CC_WARN_IN_ERR_FLAGS))
+$(info CFLAGS <-> $(CFLAGS))
+$(info CFLAGS_OPTIMIZATION <-- $(CFLAGS_OPTIMIZATION))
+$(info COMPILER <-- $(COMPILER))
+$(info CPP_CHECK_SCOPE <-- $(CPP_CHECK_SCOPE))
+$(info CURDIR <-- $(CURDIR))
+$(info CY_SEC_TOOLS_PATH --> $(CY_SEC_TOOLS_PATH))
+$(info C_FILES <-> $(C_FILES))
+$(info C_LIBS <-> $(C_LIBS))
+$(info DEFINES <-> $(DEFINES))
+$(info DEFINES_APP <-- $(DEFINES_APP))
+$(info DEFINES_LIBS <-- $(DEFINES_LIBS))
+$(info ENC_IMG --> $(ENC_IMG))
+$(info ENC_KEY_FILE --> $(ENC_KEY_FILE))
+$(info GCC_PATH <-- $(GCC_PATH))
+$(info HEADER_OFFSET <-> $(HEADER_OFFSET))
+$(info INCLUDE_DIRS <-> $(INCLUDE_DIRS))
+$(info INCLUDE_DIRS_APP <-- $(INCLUDE_DIRS_APP))
+$(info INCLUDE_DIRS_LIBS <-- $(INCLUDE_DIRS_LIBS))
+$(info INCLUDE_DIRS_MCUBOOT <-- $(INCLUDE_DIRS_MCUBOOT))
+$(info LD <-- $(LD))
+$(info LDFLAGS <-> $(LDFLAGS))
+$(info LDFLAGS_OPTIMIZATION <-- $(LDFLAGS_OPTIMIZATION))
+$(info LINKER_SCRIPT <-- $(LINKER_SCRIPT))
+$(info MAKE <-- $(MAKE))
+$(info OS <-- $(OS))
+$(info OUT <-- $(OUT))
+$(info OUT_APP <-> $(OUT_APP))
+$(info OUT_CFG <-- $(OUT_CFG))
+$(info OUT_FILE_NAME <-> $(OUT_FILE_NAME))
+$(info OUT_OBJ <-> $(OUT_OBJ))
+$(info OUT_OBJ_LIBS_DIR <-> $(OUT_OBJ_LIBS_DIR))
+$(info OUT_TARGET <-- $(OUT_TARGET))
+$(info O_FILES <-> $(O_FILES))
+$(info O_LIBS <-> $(O_LIBS))
+$(info PLATFORM <-- $(PLATFORM))
+$(info POST_BUILD_ENABLE --> $(POST_BUILD_ENABLE))
+$(info PYTHON_PATH <-> $(PYTHON_PATH))
+$(info SIGN_KEY_FILE <-> $(SIGN_KEY_FILE))
+$(info SOURCES_APP <-- $(SOURCES_APP))
+$(info SOURCES_LIBS <-- $(SOURCES_LIBS))
+$(info SOURCES_PLATFORM <-- $(SOURCES_PLATFORM))
+$(info THREADS_NUM <-> $(THREADS_NUM))
+$(info USE_CRYPTO_HW --> $(USE_CRYPTO_HW))
+$(info WARN_AS_ERR <-> $(WARN_AS_ERR))
endif
diff --git a/boot/cypress/README.md b/boot/cypress/README.md
index f2db991..8227da6 100644
--- a/boot/cypress/README.md
+++ b/boot/cypress/README.md
@@ -1,60 +1,56 @@
-### Port Of Mcuboot Library For Evaluation With Cypress PSoC 6 Chips
+## Port of MCUboot library for evaluation with Cypress PSoC™ 6 and CYW20829 chips
### Disclaimer
-Given solution is included in `mcuboot` repository with purpose to demonstrate basic consepts and features of MCUBoot library on Cypress PSoC 6 device. Applications are created per mcuboot library maintainers requirements. Implemetation differs from conventional and recomended by Cypress Semiconductors development flow for PSoC 6 devices. These applications are not recomended as a starting point for development and should not be considered as supported examples for PSoC 6 devices.
+This solution is included in the `MCUboot` repository in order to demonstrate the basic concepts and features of the MCUboot library on PSoC™ 6 and CYW20829 devices. Applications are created per MCUboot library maintainers requirements. The implementation differs from conventional and recommended by Cypress Semiconductors development flow for PSoC™ 6 and CYW20829 devices. These applications are not recommended as a starting point for development because they are not supported examples.
-Examples provided to use with **ModusToolbox® Software Environment** are a recommended reference point to start development of MCUBoot based bootloaders for PSoC 6 devices.
+Examples provided to use with **ModusToolbox™ Software Environment** are a recommended reference point to start development of MCUboot based bootloaders for PSoC™ 6 and CYW20829 devices.
-Refer to **Cypress Semiconductors** [github](https://github.com/cypresssemiconductorco) page to find examples.
+For examples, refer to the **Infineon Technologies AG** [github](https://github.com/Infineon/Code-Examples-for-ModusToolbox-Software) page.
-1. MCUboot-Based Basic Bootloader [mtb-example-psoc6-mcuboot-basic](https://github.com/cypresssemiconductorco/mtb-example-psoc6-mcuboot-basic)
-2. MCUboot-Based Bootloader with Rollback to Factory App in External Flash [mtb-example-anycloud-mcuboot-rollback](https://github.com/cypresssemiconductorco/mtb-example-anycloud-mcuboot-rollback)
+1. MCUboot-based basic bootloader [mtb-example-psoc6-mcuboot-basic](https://github.com/Infineon/mtb-example-psoc6-mcuboot-basic)
+2. MCUboot-based bootloader with rollback to factory app in external flash [mtb-example-anycloud-mcuboot-rollback](https://github.com/Infineon/mtb-example-anycloud-mcuboot-rollback)
-### Solution Description
+### Solution description
-There are two applications implemented:
-* MCUBootApp - PSoC 6 MCUBoot-based bootloading application;
-* BlinkyApp - simple PSoC 6 blinking LED application which is a target of BOOT/UPGRADE;
+The two applications implemented:
+* MCUBootApp - PSoC™ 6 and CYW20829 MCUboot-based bootloading application
+* BlinkyApp - a simple PSoC™ 6 and CYW20829 blinking LED application, which is a target of BOOT/UPGRADE
#### MCUBootApp
-* There are two types of upgrade operation supported:
- * **Overwrite only** - secondady image is only copied to primary slot after validation
- * **Swap** - seconrady and primary slots images are swapped in process of upgrade. Upgrade operation can be reverted in case of bad secondary image.
+* The two types of upgrade operation supported:
+ * **Overwrite only** - The secondary image is only copied to the primary slot after validation.
+ * **Swap** - The secondary and primary slots images are swapped during the upgrade process. Upgrade operation can be reverted if the secondary image is bad. "Bad image" does not set the imageOK flag in the image trailer. If imageOK is not set, MCUBootApp does not turn off WatchDog Timer and WDT resets the device to start the REVERT procedure.
-* There are two types of operation modes supported:
- * single image
- * multi image
+* The two types of operation modes supported:
+ * Single image
+ * Multi image
-* Secondary (upgrade) slot(s) can be placed in external memory. For more details about External Memory usage refer to separate guiding document `MCUBootApp/ExternalMemory.md`.
+* Some or all partitions (slots) can be placed in external memory. For more details about external memory usage, refer to [ExternalMemory.md](MCUBootApp/ExternalMemory.md).
-* MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification
-* Cryptographic functions can be based on completely software implementation or be hardware accelerated. mbedTLS library is used in both cases.
+* MCUBootApp checks the image integrity with SHA256, image authenticity with EC256 digital signature verification.
+* Cryptographic functions can be based on completely software implementation or be hardware accelerated on some platforms. The mbedTLS library is used in both cases.
-Detailed description of **MCUBootApp** is provided in `MCUBootApp/MCUBootApp.md`
-
-MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses either completely software implementation of cryptographic functions or accelerated by hardware - both based on mbedTLS Library.
+For more details on **MCUBootApp**, refer to [MCUBootApp.md](MCUBootApp/MCUBootApp.md).
#### BlinkyApp
-* Can be built to use as primary or secondary image for both internal and external flash memory
-* Primary and secondary images differ in text printed to serial terminal and led blinking frequency.
-* Watchdog timer functionality is supported to confirm successful start/upgrade of application
-* User application side of mcuboot swap operation is demonstrated for secondary image build.
+* Can be built to use either primary or secondary image for both internal and external flash memory.
+* Primary and secondary images differ in text printed to the serial terminal and LED-blinking frequency.
+* The watchdog timer functionality is supported to confirm successful start/upgrade of the application.
+* The user-application side of MCUboot swap operation is demonstrated by two kinds of user images, compiled for the primary and secondary slot.
-Detailed description of **BlinkyApp** is provided in `BlinkyApp/BlinkyApp.md`
+For more details on **BlinkyApp**, refer to [BlinkyApp.md](BlinkyApp/BlinkyApp.md).
-### Downloading Solution's Assets
+### Downloading solution's assets
-There is a set assets required:
+The set of required libraries represented as submodules:
-* MCUBooot Library (root repository)
-* PSoC 6 Peripheral Drivers Library (PDL)
-* mbedTLS Cryptographic Library
+* MCUBooot library (root repository)
+* Peripheral Drivers library (PDL)
+* mbedTLS Cryptographic library
-Those are represented as submodules.
-
-To retrieve source code with subsequent submodules pull:
+To retrieve source code with subsequent submodules, pull:
git clone --recursive https://github.com/mcu-tools/mcuboot.git
@@ -63,47 +59,34 @@
cd mcuboot
git submodule update --init --recursive
-### Building Solution
+### Building solution
-Root directory for build is `boot/cypress`.
+The root directory for build is `boot/cypress`.
-Root folder contains make files infrastructure for building both MCUBootApp bootloading application and BlinkyApp user application.
+The root folder contains a make-files infrastructure for building both MCUBootApp bootloading-application and BlinkyApp user-application.
-Instructions on how to build and upload MCUBootApp bootloading application and sample user application are located in `MCUBootApp.md` and `BlinkyApp.md` files in corresponding folders.
+For instructions on how to build and upload MCUBootApp bootloading-application and sample user-application, refer to the [MCUBootApp.md](MCUBootApp/MCUBootApp.md) and [BlinkyApp.md](BlinkyApp/BlinkyApp.md) files in corresponding folders.
**Toolchain**
-**GCC_ARM** is the only supported (built and verified on GCC 7.2.1).
+**GCC_ARM** is only supported (built and verified on GCC 9.3.1).
-It is inluded with [ModusToolbox® Software Environment](https://www.cypress.com/products/modustoolbox-software-environment) and can be found in folder `./ModusToolbox/tools_2.1/gcc-7.2.1`.
+It is included with [ModusToolbox™ Software Environment](https://www.cypress.com/products/modustoolbox) and can be found in folder `./ModusToolbox/tools_2.4/gcc`.
-Default installation folder is expected by makefile build system.
+The default installation folder is expected by the makefile build system.
-In case of using another installation folder, version of **ModusToolbox IDE** or another GCC Compiler - path to a toolchain should be specified to a build system using **TOOLCHAIN_PATH** flag.
+To use another installation folder, version of **ModusToolbox™ IDE** or another GCC Compiler, specify the path to a toolchain using the **TOOLCHAIN_PATH** parameter.
-**Example:**
+### Build environment troubleshooting
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT TOOLCHAIN_PATH=/home/fw-security/ModusToolbox/tools_2.0/gcc-7.2.1
-
-Supported platforms for `MCUBoot`, `BlinkyApp`:
-
-* PSOC_062_2M
-* PSOC_062_1M
-* PSOC_062_512K
-
-### Build Environment Troubleshooting
-
-Following CLI / IDE are supported for project build:
+The following CLI/IDE are supported for project build:
* Cygwin on Windows systems
* unix style shells on *nix systems
-* Eclipse / ModusToolbox ("makefile project from existing source")
+* Eclipse / ModusToolbox™ ("makefile project from existing source")
-*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
+*Make* - Ensure that it is added to the system's `PATH` variable and the correct path is the first on the list.
-*Python/Python3* - make sure you have correct path referenced in `PATH`;
+*Python/Python3* - Ensure that you have the correct path referenced in `PATH`.
-*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
-
-This will inherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.
-
+*Msys2* - To use the system's path, navigate to the msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart the MSYS2 shell. This will inherit the system's path and find `python` installed in a regular way as well as `imgtool` and its dependencies.
diff --git a/boot/cypress/common_libs.mk b/boot/cypress/common_libs.mk
index f5d11f8..d380107 100644
--- a/boot/cypress/common_libs.mk
+++ b/boot/cypress/common_libs.mk
@@ -28,62 +28,124 @@
################################################################################
# PDL library
################################################################################
-PSOC6_LIBS_PATH = $(PRJ_DIR)/libs
+CY_LIBS_PATH = $(PRJ_DIR)/libs
-ifeq ($(CORE),CM0P)
-CORE_SIFFX=m0plus
-else
-CORE_SIFFX=m4
-endif
+# Collect common source files for PDL
+SOURCES_PDL := $(wildcard $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/source/*.c)
+SOURCES_PDL += $(wildcard $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/*.c)
-# Collect source files for PDL
-SOURCES_PDL := $(wildcard $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/drivers/source/*.c)
-SOURCES_PDL += $(wildcard $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/*.c)
+COMPONENT_CORE_PATH := $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/templates/COMPONENT_MTB/COMPONENT_$(CORE)
# PDL startup related files
-SOURCES_PDL_STARTUP := $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_$(CORE)/system_psoc6_c$(CORE_SIFFX).c
+SYSTEM_FILE_NAME := $(PLATFORM_SYSTEM_FILE_NAME)
+SOURCES_PDL_SYSTEM := $(COMPONENT_CORE_PATH)/$(SYSTEM_FILE_NAME)
+SOURCES_PDL_STARTUP := $(COMPONENT_CORE_PATH)/$(PLATFORM_SOURCES_PDL_STARTUP)
+
+# Collect source files for Retarget-io
+SOURCES_RETARGET_IO := $(PLATFORM_SOURCES_RETARGET_IO)
+
+# HAL source files
+SOURCES_HAL := $(PLATFORM_SOURCES_HAL)
+
+# Add platform folder to build
+SOURCES_PLATFORM := $(wildcard $(PRJ_DIR)/platforms/$(FAMILY)/*.c)
+SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/$(FAMILY)/secure/*.c)
# PDL related include directories
-INCLUDE_DIRS_PDL := $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/drivers/include
-INCLUDE_DIRS_PDL += $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip
-INCLUDE_DIRS_PDL += $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include
-INCLUDE_DIRS_PDL += $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/cmsis/include
-
-# PDL startup related files
-INCLUDE_DIRS_PDL_STARTUP := $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB
+INCLUDE_DIRS_PDL := $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/include
+INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/ip
+INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include
+INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/cmsis/include
+INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/templates/COMPONENT_MTB
# core-libs related include directories
-INCLUDE_DIRS_CORE_LIB := $(PSOC6_LIBS_PATH)/core-lib/include
+INCLUDE_DIRS_CORE_LIB := $(CY_LIBS_PATH)/core-lib/include
-STARTUP_FILE := $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/startup_psoc6_$(PLATFORM_SUFFIX)_c$(CORE_SIFFX)
+# PDL startup related files
+INCLUDE_DIRS_PDL_STARTUP += $(COMPONENT_CORE_PATH)/HEADER_FILES
-ifeq ($(COMPILER), GCC_ARM)
- ASM_FILES_STARTUP := $(STARTUP_FILE).S
-else
-$(error Only GCC ARM is supported at this moment)
-endif
+# Retarget-io related include directories
+INCLUDE_DIRS_RETARGET_IO := $(PLATFORM_INCLUDE_DIRS_RETARGET_IO)
+# HAL include directories files
+INCLUDE_DIRS_HAL := $(PLATFORM_INCLUDE_DIRS_HAL)
+
+# Include platforms folder
+INCLUDE_DIRS_PLATFORM := $(PRJ_DIR)/platforms/$(FAMILY)
+INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/$(FAMILY)/secure
+
+# Assembler startup file for platform
+ASM_FILES_STARTUP := $(PLATFORM_STARTUP_FILE)
# Collected source files for libraries
SOURCES_LIBS := $(SOURCES_PDL)
+SOURCES_LIBS += $(SOURCES_PDL_SYSTEM)
SOURCES_LIBS += $(SOURCES_PDL_STARTUP)
+SOURCES_LIBS += $(SOURCES_PDL_RUNTIME)
+SOURCES_LIBS += $(SOURCES_HAL)
+SOURCES_LIBS += $(SOURCES_RETARGET_IO)
# Collected include directories for libraries
INCLUDE_DIRS_LIBS := $(addprefix -I,$(INCLUDE_DIRS_PDL))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_PDL_STARTUP))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_CORE_LIB))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_PLATFORM))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_RETARGET_IO))
-ASM_FILES_PDL :=
-ifeq ($(COMPILER), GCC_ARM)
-ASM_FILES_PDL += $(PSOC6_LIBS_PATH)/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S
-else
-$(error Only GCC ARM is supported at this moment)
-endif
+# Syslib files
+ASM_FILES_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S
ASM_FILES_LIBS := $(ASM_FILES_PDL)
# Add define for PDL version
DEFINES_PDL += -DPDL_VERSION=$(PDL_VERSION)
-DEFINES_LIBS := $(DEFINES_PLATFORM)
+DEFINES_LIBS := $(PLATFORM_DEFINES)
+DEFINES_LIBS += $(PLATFORM_DEFINES_LIBS)
DEFINES_LIBS += $(DEFINES_PDL)
+DEFINES_LIBS += -DCOMPONENT_CAT1
+DEFINES_LIBS += -DCOMPONENT_CAT$(PDL_CAT_SUFFIX)
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### common_libs.mk ####)
+$(info ASM_FILES_LIBS --> $(ASM_FILES_LIBS))
+$(info ASM_FILES_PDL <-> $(ASM_FILES_PDL))
+$(info ASM_FILES_STARTUP --> $(ASM_FILES_STARTUP))
+$(info COMPONENT_CORE_PATH <-> $(COMPONENT_CORE_PATH))
+$(info CORE <-- $(CORE))
+$(info CY_LIBS_PATH <-- $(CY_LIBS_PATH))
+$(info DEFINES_LIBS --> $(DEFINES_LIBS))
+$(info DEFINES_PDL <-> $(DEFINES_PDL))
+$(info FAMILY <-- $(FAMILY))
+$(info INCLUDE_DIRS_CORE_LIB <-> $(INCLUDE_DIRS_CORE_LIB))
+$(info INCLUDE_DIRS_HAL <-> $(INCLUDE_DIRS_HAL))
+$(info INCLUDE_DIRS_LIBS --> $(INCLUDE_DIRS_LIBS))
+$(info INCLUDE_DIRS_PDL <-> $(INCLUDE_DIRS_PDL))
+$(info INCLUDE_DIRS_PDL_STARTUP <-> $(INCLUDE_DIRS_PDL_STARTUP))
+$(info INCLUDE_DIRS_PLATFORM <-> $(INCLUDE_DIRS_PLATFORM))
+$(info INCLUDE_DIRS_RETARGET_IO <-> $(INCLUDE_DIRS_RETARGET_IO))
+$(info PDL_CAT_SUFFIX <-- $(PDL_CAT_SUFFIX))
+$(info PDL_VERSION <-- $(PDL_VERSION))
+$(info PLATFORM_DEFINES <-- $(PLATFORM_DEFINES))
+$(info PLATFORM_DEFINES_LIBS <-- $(PLATFORM_DEFINES_LIBS))
+$(info PLATFORM_INCLUDE_DIRS_HAL <-- $(PLATFORM_INCLUDE_DIRS_HAL))
+$(info PLATFORM_INCLUDE_DIRS_RETARGET_IO <-- $(PLATFORM_INCLUDE_DIRS_RETARGET_IO))
+$(info PLATFORM_SOURCES_HAL <-- $(PLATFORM_SOURCES_HAL))
+$(info PLATFORM_SOURCES_PDL_STARTUP <-- $(PLATFORM_SOURCES_PDL_STARTUP))
+$(info PLATFORM_SOURCES_RETARGET_IO <-- $(PLATFORM_SOURCES_RETARGET_IO))
+$(info PLATFORM_STARTUP_FILE <-- $(PLATFORM_STARTUP_FILE))
+$(info PLATFORM_SYSTEM_FILE_NAME <-- $(PLATFORM_SYSTEM_FILE_NAME))
+$(info PRJ_DIR <-- $(PRJ_DIR))
+$(info SOURCES_HAL <-> $(SOURCES_HAL))
+$(info SOURCES_LIBS --> $(SOURCES_LIBS))
+$(info SOURCES_PDL <-> $(SOURCES_PDL))
+$(info SOURCES_PDL_RUNTIME <-- $(SOURCES_PDL_RUNTIME))
+$(info SOURCES_PDL_STARTUP <-> $(SOURCES_PDL_STARTUP))
+$(info SOURCES_PDL_SYSTEM <-> $(SOURCES_PDL_SYSTEM))
+$(info SOURCES_PLATFORM --> $(SOURCES_PLATFORM))
+$(info SOURCES_RETARGET_IO <-> $(SOURCES_RETARGET_IO))
+$(info SYSTEM_FILE_NAME <-> $(SYSTEM_FILE_NAME))
+endif
diff --git a/boot/cypress/cy_flash_pal/cy_flash_map.c b/boot/cypress/cy_flash_pal/cy_flash_map.c
deleted file mode 100644
index 11113fb..0000000
--- a/boot/cypress/cy_flash_pal/cy_flash_map.c
+++ /dev/null
@@ -1,712 +0,0 @@
-/*
- * Copyright (c) 2018 Nordic Semiconductor ASA
- * Copyright (c) 2020 Cypress Semiconductor Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
- /*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
- /*******************************************************************************/
-
-#ifdef MCUBOOT_HAVE_ASSERT_H
-#include "mcuboot_config/mcuboot_assert.h"
-#else
-#include <assert.h>
-#endif
-
-#include <stdbool.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <string.h>
-
-#include "mcuboot_config/mcuboot_config.h"
-#include "flash_map_backend/flash_map_backend.h"
-#include <sysflash/sysflash.h>
-
-#include "bootutil/bootutil_log.h"
-
-#include "cy_flash.h"
-
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
-#include "cy_smif_psoc6.h"
-#endif
-
-#ifdef MCUBOOT_SWAP_USING_STATUS
-#include "swap_status.h"
-#endif
-/*
- * For now, we only support one flash device.
- *
- * Pick a random device ID for it that's unlikely to collide with
- * anything "real".
- */
-#define FLASH_DEVICE_ID 111
-#define FLASH_MAP_ENTRY_MAGIC (0xd00dbeefU)
-
-#define FLASH_AREA_IMAGE_SECTOR_SIZE FLASH_AREA_IMAGE_SCRATCH_SIZE
-
-#ifndef CY_BOOTLOADER_START_ADDRESS
-#define CY_BOOTLOADER_START_ADDRESS (0x10000000u)
-#endif
-
-#ifndef CY_BOOT_INTERNAL_FLASH_ERASE_VALUE
-/* This is the value of internal flash bytes after an erase */
-#define CY_BOOT_INTERNAL_FLASH_ERASE_VALUE (0x00u)
-#endif
-
-#ifndef CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE
-/* This is the value of external flash bytes after an erase */
-#define CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE (0xffu)
-#endif
-
-#ifdef CY_FLASH_MAP_EXT_DESC
-/* Nothing to be there when external FlashMap Descriptors are used */
-#else
-static struct flash_area bootloader =
-{
- .fa_id = FLASH_AREA_BOOTLOADER,
- .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
- .fa_off = CY_BOOTLOADER_START_ADDRESS,
- .fa_size = CY_BOOT_BOOTLOADER_SIZE
-};
-
-static struct flash_area primary_1 =
-{
- .fa_id = FLASH_AREA_IMAGE_PRIMARY(0),
- .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
- .fa_off = CY_FLASH_BASE + CY_BOOT_BOOTLOADER_SIZE,
- .fa_size = CY_BOOT_PRIMARY_1_SIZE
-};
-
-static struct flash_area secondary_1 =
-{
- .fa_id = FLASH_AREA_IMAGE_SECONDARY(0),
-#ifndef CY_BOOT_USE_EXTERNAL_FLASH
- .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
- .fa_off = CY_FLASH_BASE +\
- CY_BOOT_BOOTLOADER_SIZE +\
- CY_BOOT_PRIMARY_1_SIZE,
-#else
- .fa_device_id = FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX),
- .fa_off = CY_BOOT_SECONDARY_1_EXT_MEM_OFFSET,
-#endif
- .fa_size = CY_BOOT_SECONDARY_1_SIZE
-};
-
-#if (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
-static struct flash_area primary_2 =
-{
- .fa_id = FLASH_AREA_IMAGE_PRIMARY(1),
- .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
-#ifndef CY_BOOT_USE_EXTERNAL_FLASH
- .fa_off = CY_FLASH_BASE +\
- CY_BOOT_BOOTLOADER_SIZE +\
- CY_BOOT_PRIMARY_1_SIZE +\
- CY_BOOT_SECONDARY_1_SIZE,
-#else
- .fa_off = CY_FLASH_BASE +\
- CY_BOOT_BOOTLOADER_SIZE +\
- CY_BOOT_PRIMARY_1_SIZE,
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
- .fa_size = CY_BOOT_PRIMARY_2_SIZE
-};
-
-static struct flash_area secondary_2 =
-{
- .fa_id = FLASH_AREA_IMAGE_SECONDARY(1),
-#ifndef CY_BOOT_USE_EXTERNAL_FLASH
- .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
- .fa_off = CY_FLASH_BASE +\
- CY_BOOT_BOOTLOADER_SIZE +\
- CY_BOOT_PRIMARY_1_SIZE +\
- CY_BOOT_SECONDARY_1_SIZE +\
- CY_BOOT_PRIMARY_2_SIZE,
-#else
- .fa_device_id = FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX),
- .fa_off = CY_BOOT_SECONDARY_2_EXT_MEM_OFFSET,
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
- .fa_size = CY_BOOT_SECONDARY_2_SIZE
-};
-#endif /* MCUBOOT_IMAGE_NUMBER == 2 */
-#endif /* CY_FLASH_MAP_EXT_DESC */
-
-#ifdef MCUBOOT_SWAP_USING_STATUS
-#define SWAP_STATUS_PARTITION_SIZE (CY_BOOT_SWAP_STATUS_SIZE * BOOT_IMAGE_NUMBER)
-
-#ifndef CY_BOOT_USE_EXTERNAL_FLASH
-#if (MCUBOOT_IMAGE_NUMBER == 1) /* if single image, internal flash */
-#define SWAP_STATUS_PARTITION_OFF (CY_FLASH_BASE + \
- CY_BOOT_BOOTLOADER_SIZE + \
- CY_BOOT_PRIMARY_1_SIZE + \
- CY_BOOT_SECONDARY_1_SIZE)
-#elif (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image, internal flash */
-#define SWAP_STATUS_PARTITION_OFF (CY_FLASH_BASE + \
- CY_BOOT_BOOTLOADER_SIZE + \
- CY_BOOT_PRIMARY_1_SIZE + \
- CY_BOOT_SECONDARY_1_SIZE + \
- CY_BOOT_PRIMARY_2_SIZE + \
- CY_BOOT_SECONDARY_2_SIZE)
-#endif /* MCUBOOT_IMAGE_NUMBER */
-#else /* CY_BOOT_USE_EXTERNAL_FLASH */
-#if (MCUBOOT_IMAGE_NUMBER == 1) /* if single image, external flash */
-#define SWAP_STATUS_PARTITION_OFF (CY_FLASH_BASE + \
- CY_BOOT_BOOTLOADER_SIZE + \
- CY_BOOT_PRIMARY_1_SIZE)
-#elif (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image, external flash */
-#define SWAP_STATUS_PARTITION_OFF (CY_FLASH_BASE + \
- CY_BOOT_BOOTLOADER_SIZE + \
- CY_BOOT_PRIMARY_1_SIZE + \
- CY_BOOT_PRIMARY_2_SIZE)
-#endif /* MCUBOOT_IMAGE_NUMBER */
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-static struct flash_area status =
-{
- .fa_id = FLASH_AREA_IMAGE_SWAP_STATUS,
- .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
- .fa_off = SWAP_STATUS_PARTITION_OFF,
-#ifdef MCUBOOT_SWAP_USING_SCRATCH
- .fa_size = (SWAP_STATUS_PARTITION_SIZE + BOOT_SWAP_STATUS_SZ_SCRATCH)
-#else
- .fa_size = (SWAP_STATUS_PARTITION_SIZE)
-#endif /* MCUBOOT_SWAP_USING_SCRATCH */
-
-};
-#endif /* MCUBOOT_SWAP_USING_STATUS */
-
-#ifdef MCUBOOT_SWAP_USING_SCRATCH
-#ifndef CY_BOOT_SCRATCH_SIZE
-#ifndef CY_BOOT_USE_EXTERNAL_FLASH
-#define CY_BOOT_SCRATCH_SIZE (CY_FLASH_SIZEOF_ROW)
-#else
-#define CY_BOOT_SCRATCH_SIZE (CY_BOOT_SCRATCH_SIZE)
-#endif
-#endif
-static struct flash_area scratch =
-{
- .fa_id = FLASH_AREA_IMAGE_SCRATCH,
-#ifndef CY_BOOT_USE_EXTERNAL_FLASH
- .fa_device_id = FLASH_DEVICE_INTERNAL_FLASH,
-#if (MCUBOOT_IMAGE_NUMBER == 1) /* if single image */
- .fa_off = CY_FLASH_BASE +\
- CY_BOOT_BOOTLOADER_SIZE +\
- CY_BOOT_PRIMARY_1_SIZE +\
- CY_BOOT_SECONDARY_1_SIZE + \
- (SWAP_STATUS_PARTITION_SIZE + BOOT_SWAP_STATUS_SZ_SCRATCH),
-#elif (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
- .fa_off = CY_FLASH_BASE +\
- CY_BOOT_BOOTLOADER_SIZE +\
- CY_BOOT_PRIMARY_1_SIZE +\
- CY_BOOT_SECONDARY_1_SIZE +\
- CY_BOOT_PRIMARY_2_SIZE +\
- CY_BOOT_SECONDARY_2_SIZE + \
- (SWAP_STATUS_PARTITION_SIZE + BOOT_SWAP_STATUS_SZ_SCRATCH),
-#endif /* MCUBOOT_IMAGE_NUMBER */
-#else /* CY_BOOT_USE_EXTERNAL_FLASH */
- .fa_device_id = FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX),
- .fa_off = CY_SMIF_BASE_MEM_OFFSET + CY_BOOT_EXTERNAL_FLASH_SCRATCH_OFFSET,
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
- .fa_size = CY_BOOT_SCRATCH_SIZE
-};
-#endif
-
-#ifdef CY_FLASH_MAP_EXT_DESC
-/* Use external Flash Map Descriptors */
-extern struct flash_area *boot_area_descs[];
-#else
-struct flash_area *boot_area_descs[] =
-{
- &bootloader,
- &primary_1,
- &secondary_1,
-#if (MCUBOOT_IMAGE_NUMBER == 2) /* if dual-image */
- &primary_2,
- &secondary_2,
-#endif
-#ifdef MCUBOOT_SWAP_USING_SCRATCH
- &scratch,
-#endif
-#ifdef MCUBOOT_SWAP_USING_STATUS
- &status,
-#endif
- NULL
-};
-#endif /* CY_FLASH_MAP_EXT_DESC */
-
-/*
-* Returns device flash start based on supported fa_id
-*/
-int flash_device_base(uint8_t fd_id, uintptr_t *ret)
-{
- if (fd_id != (uint8_t)FLASH_DEVICE_INTERNAL_FLASH) {
- BOOT_LOG_ERR("invalid flash ID %d; expected %d",
- fd_id, FLASH_DEVICE_INTERNAL_FLASH);
- return -1;
- }
- *ret = CY_FLASH_BASE;
- return 0;
-}
-
-/*
-* Opens the area for use. id is one of the `fa_id`s
-*/
-int flash_area_open(uint8_t id, const struct flash_area **fa)
-{
- int ret = -1;
- uint32_t i = 0;
-
- while(NULL != boot_area_descs[i])
- {
- if(id == boot_area_descs[i]->fa_id)
- {
- *fa = boot_area_descs[i];
- ret = 0;
- break;
- }
- i++;
- }
-
- return ret;
-}
-
-/*
-* Clear pointer to flash area fa
-*/
-void flash_area_close(const struct flash_area *fa)
-{
- (void)fa; /* Nothing to do there */
-}
-
-/*
-* Reads `len` bytes of flash memory at `off` to the buffer at `dst`
-*/
-int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
- uint32_t len)
-{
- int rc = 0;
- size_t addr;
-
- /* check if requested offset not less then flash area (fa) start */
- assert((int)(off < fa->fa_off));
- assert((int)(off + len < fa->fa_off));
- /* convert to absolute address inside a device*/
- addr = fa->fa_off + off;
-
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
- {
- /* flash read by simple memory copying */
- (void)memcpy((void *)dst, (const void*)addr, (size_t)len);
- }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
- {
- rc = psoc6_smif_read(fa, (int32_t)addr, dst, len);
- }
-#endif
- else
- {
- /* incorrect/non-existing flash device id */
- rc = -1;
- }
-
- if ((rc != 0) && (fa->fa_device_id != FLASH_DEVICE_UNDEFINED))
- {
- BOOT_LOG_ERR("Flash area read error, rc = %d", (int)rc);
- }
- return rc;
-}
-
-/*
-* Writes `len` bytes of flash memory at `off` from the buffer at `src`
- */
-int flash_area_write(const struct flash_area *fa, uint32_t off,
- const void *src, uint32_t len)
-{
- cy_en_flashdrv_status_t rc = CY_FLASH_DRV_SUCCESS;
- size_t write_start_addr;
- size_t write_end_addr;
- const uint32_t * row_ptr = NULL;
-
- assert((int)(off < fa->fa_off));
- assert((int)(off + len < fa->fa_off));
-
- /* convert to absolute address inside a device */
- write_start_addr = fa->fa_off + off;
- write_end_addr = fa->fa_off + off + len;
-
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
- {
- uint32_t row_number = 0;
- uint32_t row_addr = 0;
-
- assert((int)((len % CY_FLASH_SIZEOF_ROW) == 0U));
- assert((int)((write_start_addr % CY_FLASH_SIZEOF_ROW) == 0U));
-
- row_number = (write_end_addr - write_start_addr) / CY_FLASH_SIZEOF_ROW;
- row_addr = write_start_addr;
-
- row_ptr = (const uint32_t *) src;
-
- for (uint32_t i = 0; i < row_number; i++)
- {
- rc = (int)Cy_Flash_WriteRow(row_addr, row_ptr);
-
- row_addr += (uint32_t) CY_FLASH_SIZEOF_ROW;
- row_ptr = row_ptr + CY_FLASH_SIZEOF_ROW / 4U;
- }
- }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
- {
- rc = psoc6_smif_write(fa, (int32_t)write_start_addr, src, len);
- }
-#endif
- else
- {
- /* incorrect/non-existing flash device id */
- rc = -1;
- }
-
- return (int) rc;
-}
-
-/*< Erases `len` bytes of flash memory at `off` */
-int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
-{
- cy_en_flashdrv_status_t rc = CY_FLASH_DRV_SUCCESS;
- size_t erase_start_addr;
- size_t erase_end_addr;
-
- assert((int)(len <= fa->fa_size));
- assert((int)(off < fa->fa_size));
- assert((int)(off + len < fa->fa_off + fa->fa_size));
-
- /* convert to absolute address inside a device*/
- erase_start_addr = fa->fa_off + off;
- erase_end_addr = fa->fa_off + off + len;
-
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
- {
- int row_number = 0;
- uint32_t row_addr = 0;
- uint32_t row_start_addr = (erase_start_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;
- uint32_t row_end_addr = (erase_end_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;
-
- /* assume single row needs to be erased */
- if (row_start_addr == row_end_addr) {
- rc = (int)Cy_Flash_EraseRow(row_start_addr);
- } else {
- row_number = (int)((row_end_addr - row_start_addr) / CY_FLASH_SIZEOF_ROW);
-
- while (row_number != 0)
- {
- row_number--;
- row_addr = row_start_addr + (uint32_t) row_number * (uint32_t) CY_FLASH_SIZEOF_ROW;
- rc = (int)Cy_Flash_EraseRow(row_addr);
- }
- }
- }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
- {
- rc = psoc6_smif_erase((int)erase_start_addr, len);
- }
-#endif
- else
- {
- /* incorrect/non-existing flash device id */
- rc = -1;
- }
- return (int) rc;
-}
-
-/*< Returns this `flash_area`s alignment */
-size_t flash_area_align(const struct flash_area *fa)
-{
- size_t ret = (size_t)-1;
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
- {
- ret = CY_FLASH_ALIGN;
- }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
- {
- ret = qspi_get_prog_size();
- }
-#endif
- else
- {
- /* incorrect/non-existing flash device id */
- ret = (size_t)-1;
- }
- return ret;
-}
-
-#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
-/*< Initializes an array of flash_area elements for the slot's sectors */
-int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa)
-{
- int rc = 0;
-
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
- {
- (void)idx;
- (void)cnt;
- rc = 0;
- }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
- {
- (void)idx;
- (void)cnt;
- rc = 0;
- }
-#endif
- else
- {
- /* incorrect/non-existing flash device id */
- rc = -1;
- }
- return rc;
-}
-#endif
-
-/*
- * This depends on the mappings defined in sysflash.h.
- * MCUBoot uses continuous numbering for the primary slot, the secondary slot,
- * and the scratch while zephyr might number it differently.
- */
-int flash_area_id_from_multi_image_slot(int image_index, int slot)
-{
- int rc;
- switch (slot) {
- case 0:
- rc = (int)FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index);
- break;
- case 1:
- rc = (int)FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index);
- break;
- case 2:
- rc = (int)FLASH_AREA_IMAGE_SCRATCH;
- break;
- default:
- rc = -1; /* flash_area_open will fail on that */
- break;
- }
- return rc;
-}
-
-int flash_area_id_from_image_slot(int slot)
-{
- return flash_area_id_from_multi_image_slot(0, slot);
-}
-
-int flash_area_id_to_multi_image_slot(int image_index, int area_id)
-{
- if (area_id == (int) FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index)) {
- return 0;
- }
- if (area_id == (int) FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index)) {
- return 1;
- }
-
- return -1;
-}
-
-int flash_area_id_to_image_slot(int area_id)
-{
- return flash_area_id_to_multi_image_slot(0, area_id);
-}
-
-/*
- * Erases aligned row of flash, where passed address resided
- */
-int flash_erase_row(uint32_t address)
-{
- cy_en_flashdrv_status_t rc = CY_FLASH_DRV_SUCCESS;
- uint32_t row_addr = 0;
-
- /* Calculate start of row arbitrary address */
- row_addr = (address/CY_FLASH_SIZEOF_ROW)*CY_FLASH_SIZEOF_ROW;
-
- /* Erase whole row of flash */
- rc = Cy_Flash_EraseRow(row_addr);
-
- return (int) rc;
-}
-
-uint8_t flash_area_erased_val(const struct flash_area *fa)
-{
- uint8_t ret = 0;
-
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
- {
- ret = (uint8_t) CY_BOOT_INTERNAL_FLASH_ERASE_VALUE;
- }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
- {
- ret = (uint8_t) CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE;
- }
-#endif
- else
- {
- assert(false);
- }
-
- return ret ;
-}
-
-int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off,
- void *dst, uint32_t len)
-{
- /* The disabled flash area always tracts as empty */
- if (fa->fa_device_id != FLASH_DEVICE_UNDEFINED)
- {
- int rc;
- uint8_t *mem_dest = (uint8_t *)dst;
- uint8_t val = flash_area_erased_val(fa);
-
- rc = flash_area_read(fa, off, dst, len);
- if (rc != 0) {
- return -1;
- }
-
- for (uint8_t i = 0; i < len; i++) {
- if (mem_dest[i] != val) {
- return 0;
- }
- }
- }
- return 1;
-}
-
-#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
-int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
-{
- int rc = 0;
- uint32_t i = 0u;
- struct flash_area *fa = NULL;
-
- while(NULL != boot_area_descs[i])
- {
- if(idx == (int) boot_area_descs[i]->fa_id)
- {
- fa = boot_area_descs[i];
- break;
- }
- i++;
- }
-
- if(NULL != fa)
- {
- size_t sector_size = 0;
- size_t area_size = fa->fa_size;
-
- if(fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH)
- {
-#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && defined(MCUBOOT_SWAP_USING_STATUS) \
- && !defined(MCUBOOT_SWAP_USING_SCRATCH)
- if(idx == (int) FLASH_AREA_IMAGE_SWAP_STATUS)
- {
- sector_size = CY_FLASH_SIZEOF_ROW;
- }
- else
- {
- sector_size = qspi_get_erase_size();
-#else
- sector_size = CY_FLASH_SIZEOF_ROW;
-#endif /* MCUBOOT_SWAP_USING_STATUS && CY_BOOT_USE_EXTERNAL_FLASH */
- }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG)
- {
- /* implement for SMIF */
- /* lets assume they are equal */
-#ifdef MCUBOOT_SWAP_USING_STATUS
- sector_size = qspi_get_erase_size();
-#else
- sector_size = CY_FLASH_SIZEOF_ROW;
-#endif /* MCUBOOT_SWAP_USING_STATUS */
- }
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
- else
- {
- /* fa->fa_device_id = FLASH_DEVICE_UNDEFINED,
- in this case the area should be empty with a very simple sector size of 1 byte */
- area_size = 0u;
- sector_size = 1u;
- }
-
- if(0 == rc)
- {
- size_t sectors_n;
- uint32_t my_sector_addr = 0U;
- uint32_t my_sector_size;
-
- sectors_n = (area_size + (sector_size - 1U)) / sector_size;
-
- if (sectors_n > MCUBOOT_MAX_IMG_SECTORS)
- {
- sector_size *= 2;
- }
-
- sectors_n = 0;
- my_sector_addr = fa->fa_off;
- while (area_size > 0)
- {
- my_sector_size = sector_size;
-#ifdef MCUBOOT_SWAP_USING_SCRATCH
- uint32_t my_sector_offs = my_sector_addr % my_sector_size;
-
- if (my_sector_offs != 0)
- {
- my_sector_size = sector_size - my_sector_offs;
- }
-
- if (my_sector_size > area_size)
- {
- my_sector_size = area_size;
- }
-#endif
- ret[sectors_n].fs_size = my_sector_size;
- ret[sectors_n].fs_off = my_sector_addr;
-
- my_sector_addr += my_sector_size;
- area_size -= my_sector_size;
- sectors_n++;
- }
-
- if (sectors_n <= *cnt)
- {
- *cnt = sectors_n;
- }
- else
- {
- rc = -1;
- }
- }
- }
- else
- {
- rc = -1;
- }
-
- return rc;
-}
-#endif
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/cy_flash_map.c b/boot/cypress/cy_flash_pal/flash_cyw208xx/cy_flash_map.c
new file mode 100644
index 0000000..21b9e60
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/cy_flash_map.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2022 Infineon Technologies AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "mcuboot_config/mcuboot_config.h"
+#include "flash_map_backend/flash_map_backend.h"
+#include "sysflash/sysflash.h"
+
+#include "bootutil/bootutil_log.h"
+#include "bootutil/bootutil_public.h"
+
+#include "cy_flash.h"
+#include "cy_flash_map.h"
+
+#include "cy_smif_cyw20829.h"
+
+#ifdef MCUBOOT_SWAP_USING_STATUS
+#include "swap_status.h"
+#endif
+
+#ifndef CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE
+/* This is the value of external flash bytes after an erase */
+#define CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE (0xFFu)
+#endif
+
+/*
+ * Returns device flash start based on supported fd_id
+ */
+int flash_device_base(uint8_t fd_id, uintptr_t *ret)
+{
+ int rc = -1;
+
+ if (NULL != ret) {
+
+ if (FLASH_DEVICE_INTERNAL_FLASH == fd_id) {
+ *ret = CY_FLASH_BASE;
+ rc = 0;
+ }
+ else if ((fd_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ *ret = CY_FLASH_BASE;
+ rc = 0;
+ }
+ else {
+ BOOT_LOG_ERR("invalid flash ID %u; expected %u or %u",
+ (unsigned)fd_id, FLASH_DEVICE_INTERNAL_FLASH,
+ FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX));
+ }
+ }
+
+ return rc;
+}
+
+/*
+ * Opens the area for use. id is one of the `fa_id`s
+ */
+int flash_area_open(uint8_t id, const struct flash_area **fa)
+{
+ int ret = -1;
+ uint32_t i = 0u;
+
+ if (NULL != fa) {
+ while (NULL != boot_area_descs[i]) {
+ if (id == boot_area_descs[i]->fa_id) {
+ *fa = boot_area_descs[i];
+ ret = 0;
+ break;
+ }
+ i++;
+ }
+
+ if (ret == 0 &&
+ ((*fa)->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) != 0u) {
+
+ qspi_enable();
+ }
+ }
+
+ return ret;
+}
+
+/*
+ * Clear pointer to flash area fa
+ */
+void flash_area_close(const struct flash_area *fa)
+{
+ (void)fa; /* Nothing to do there */
+
+ if (NULL != fa) {
+ if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ qspi_disable();
+ }
+ }
+}
+
+/*
+ * Reads `len` bytes of flash memory at `off` to the buffer at `dst`
+ */
+int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
+ uint32_t len)
+{
+ int rc = -1;
+ size_t addr;
+ uintptr_t flash_base = 0u;
+
+ if ( (NULL != fa) && (NULL != dst) ) {
+
+ if (off > fa->fa_size ||
+ len > fa->fa_size ||
+ off + len > fa->fa_size) {
+
+ return BOOT_EBADARGS;
+ }
+
+ rc = flash_device_base(fa->fa_device_id, &flash_base);
+
+ if (0 == rc) {
+ /* Convert to absolute address inside a device */
+ addr = flash_base + fa->fa_off + off;
+ rc = cyw20829_smif_read(fa, addr, dst, len);
+ }
+ }
+
+ return rc;
+}
+
+/*
+ * Writes `len` bytes of flash memory at `off` from the buffer at `src`
+ */
+int flash_area_write(const struct flash_area *fa, uint32_t off,
+ const void *src, uint32_t len)
+{
+ int rc = -1;
+ size_t write_start_addr = 0u;
+ uintptr_t flash_base = 0u;
+
+ if ( (NULL != fa) && (NULL != src) ) {
+
+ if (off > fa->fa_size ||
+ len > fa->fa_size ||
+ off + len > fa->fa_size) {
+
+ return BOOT_EBADARGS;
+ }
+
+ rc = flash_device_base(fa->fa_device_id, &flash_base);
+
+ if (0 == rc) {
+ /* Convert to absolute address inside a device */
+ write_start_addr = flash_base + fa->fa_off + off;
+ rc = cyw20829_smif_write(fa, write_start_addr, src, len);
+ }
+ }
+
+ return (int) rc;
+}
+
+/*< Erases `len` bytes of flash memory at `off` */
+int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
+{
+ int rc = -1;
+ size_t erase_start_addr = 0u;
+ uintptr_t flash_base = 0u;
+
+ if (NULL != fa) {
+
+ if (off > fa->fa_size ||
+ len > fa->fa_size ||
+ off + len > fa->fa_size) {
+
+ return BOOT_EBADARGS;
+ }
+
+ rc = flash_device_base(fa->fa_device_id, &flash_base);
+
+ if (0 == rc) {
+ /* Convert to absolute address inside a device */
+ erase_start_addr = flash_base + fa->fa_off + off;
+ rc = cyw20829_smif_erase(erase_start_addr, len);
+ }
+ }
+
+ return rc;
+}
+
+/*< Returns this `flash_area`s alignment */
+size_t flash_area_align(const struct flash_area *fa)
+{
+ size_t rc = 0u; /* error code (alignment cannot be zero) */
+
+ if (NULL != fa) {
+
+ if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ rc = qspi_get_erase_size();
+ }
+ }
+
+ return rc;
+}
+
+#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+/*< Initializes an array of flash_area elements for the slot's sectors */
+int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa)
+{
+ int rc = -1;
+
+ if (fa != NULL && cnt != NULL) {
+ if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ (void)idx;
+ (void)cnt;
+ rc = 0;
+ }
+ }
+
+ return rc;
+}
+#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
+
+/*
+ * This depends on the mappings defined in sysflash.h.
+ * MCUBoot uses continuous numbering for the primary slot, the secondary slot,
+ * and the scratch while zephyr might number it differently.
+ */
+int flash_area_id_from_multi_image_slot(int image_index, int slot)
+{
+ int rc;
+ if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
+ return -1;
+ }
+
+ switch (slot) {
+ case 0:
+ rc = (int)FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index);
+ break;
+ case 1:
+ rc = (int)FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index);
+ break;
+ case 2:
+ rc = (int)FLASH_AREA_IMAGE_SCRATCH;
+ break;
+ default:
+ rc = -1; /* flash_area_open will fail on that */
+ break;
+ }
+ return rc;
+}
+
+int flash_area_id_from_image_slot(int slot)
+{
+ return flash_area_id_from_multi_image_slot(0, slot);
+}
+
+int flash_area_id_to_multi_image_slot(int image_index, int area_id)
+{
+ if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
+ return -1;
+ }
+
+ if (area_id == (int) FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index)) {
+ return 0;
+ }
+ if (area_id == (int) FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index)) {
+ return 1;
+ }
+
+ return -1;
+}
+
+int flash_area_id_to_image_slot(int area_id)
+{
+ return flash_area_id_to_multi_image_slot(0, area_id);
+}
+
+uint8_t flash_area_erased_val(const struct flash_area *fa)
+{
+ uint8_t rc = 0;
+
+ if (NULL != fa) {
+ if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ rc = (uint8_t) CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE;
+ }
+ }
+
+ return rc;
+}
+
+#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
+{
+ int rc = 0;
+ uint32_t i = 0u;
+ struct flash_area *fa = NULL;
+ size_t sectors_n = 0u;
+ uint32_t my_sector_addr = 0u;
+ uint32_t my_sector_size = 0u;
+
+ while (NULL != boot_area_descs[i]) {
+ if (idx == (int) boot_area_descs[i]->fa_id) {
+ fa = boot_area_descs[i];
+ break;
+ }
+ i++;
+ }
+
+ if ( (NULL != fa) && (NULL != cnt) && (NULL != ret) ) {
+
+ size_t sector_size = 0;
+ size_t area_size = fa->fa_size;
+
+ if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) != 0u) {
+ /* implement for SMIF */
+ /* lets assume they are equal */
+#ifdef MCUBOOT_SWAP_USING_STATUS
+ int32_t qspi_status = qspi_get_status();
+
+ if (EXT_FLASH_DEV_DISABLED != qspi_status) {
+ sector_size = qspi_get_erase_size();
+ }
+ else {
+ sector_size = CY_FLASH_SIZEOF_ROW;
+ }
+#else /* MCUBOOT_SWAP_USING_STATUS */
+ sector_size = CY_FLASH_SIZEOF_ROW;
+#endif /* MCUBOOT_SWAP_USING_STATUS */
+ }
+ else {
+ /* fa->fa_device_id = FLASH_DEVICE_UNDEFINED,
+ in this case the area should be empty with a very simple sector size of 1 byte */
+ area_size = 0u;
+ sector_size = 1u;
+ }
+
+ sectors_n = (area_size + (sector_size - 1U)) / sector_size;
+
+ BOOT_LOG_DBG(" * FA: %u, off = 0x%" PRIx32
+ ", area_size = %lu, sector_size = %lu, sectors_n = %lu",
+ (unsigned)fa->fa_id, fa->fa_off, (unsigned long)area_size,
+ (unsigned long)sector_size, (unsigned long)sectors_n);
+
+ if (sectors_n > (size_t)MCUBOOT_MAX_IMG_SECTORS) {
+
+ BOOT_LOG_DBG(" + FA: %u, sectors_n(%lu) > MCUBOOT_MAX_IMG_SECTORS(%u) -> sector_size * 2",
+ (unsigned)fa->fa_id, (unsigned long)sectors_n,
+ (unsigned int) MCUBOOT_MAX_IMG_SECTORS);
+ sector_size *= 2u;
+ }
+
+ sectors_n = 0u;
+ my_sector_addr = fa->fa_off;
+
+ while (area_size > 0u) {
+
+ my_sector_size = sector_size;
+#ifdef MCUBOOT_SWAP_USING_SCRATCH
+ uint32_t my_sector_offs = my_sector_addr % my_sector_size;
+
+ if (my_sector_offs != 0u) {
+ my_sector_size = sector_size - my_sector_offs;
+ }
+
+ if (my_sector_size > area_size) {
+ my_sector_size = area_size;
+ }
+#endif /* MCUBOOT_SWAP_USING_SCRATCH */
+ ret[sectors_n].fs_size = my_sector_size;
+ ret[sectors_n].fs_off = my_sector_addr;
+
+ my_sector_addr += my_sector_size;
+ area_size -= my_sector_size;
+ sectors_n++;
+ }
+
+ if (sectors_n <= *cnt) {
+ *cnt = sectors_n;
+ }
+ else {
+ rc = -1;
+ }
+ }
+ else {
+ rc = -1;
+ }
+
+ return rc;
+}
+#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
diff --git a/boot/cypress/cy_flash_pal/cy_smif_psoc6.c b/boot/cypress/cy_flash_pal/flash_cyw208xx/cy_smif_cyw20829.c
similarity index 74%
copy from boot/cypress/cy_flash_pal/cy_smif_psoc6.c
copy to boot/cypress/cy_flash_pal/flash_cyw208xx/cy_smif_cyw20829.c
index c2dd5c3..f8daf7d 100644
--- a/boot/cypress/cy_flash_pal/cy_smif_psoc6.c
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/cy_smif_cyw20829.c
@@ -49,30 +49,24 @@
#include "stdlib.h"
#include "stdbool.h"
-#ifdef MCUBOOT_HAVE_ASSERT_H
-#include "mcuboot_config/mcuboot_assert.h"
-#else
-#include <assert.h>
-#endif
-
#include "flash_map_backend/flash_map_backend.h"
#include <sysflash/sysflash.h>
#include "cy_device_headers.h"
-#include "cy_smif_psoc6.h"
+#include "cy_smif_cyw20829.h"
#include "cy_flash.h"
#include "cy_syspm.h"
#include "flash_qspi.h"
-#define PSOC6_WR_SUCCESS (0)
-#define PSOC6_WR_ERROR_INVALID_PARAMETER (1)
-#define PSOC6_WR_ERROR_FLASH_WRITE (2)
+#define CYW20829_WR_SUCCESS (0)
+#define CYW20829_WR_ERROR_INVALID_PARAMETER (1)
+#define CYW20829_WR_ERROR_FLASH_WRITE (2)
-#define PSOC6_FLASH_ERASE_BLOCK_SIZE CY_FLASH_SIZEOF_ROW /* PSoC6 Flash erases by Row */
+#define CYW20829_FLASH_ERASE_BLOCK_SIZE CY_FLASH_SIZEOF_ROW /* CYW20829 Flash erases by Row */
-int psoc6_smif_read(const struct flash_area *fap,
- off_t addr,
+int cyw20829_smif_read(const struct flash_area *fap,
+ offset_t addr,
void *data,
size_t len)
{
@@ -83,7 +77,7 @@
cfg = qspi_get_memory_config(FLASH_DEVICE_GET_EXT_INDEX(fap->fa_device_id));
- address = (uint32_t) addr - CY_SMIF_BASE_MEM_OFFSET;
+ address = (uint32_t) addr - CY_XIP_BASE;
st = Cy_SMIF_MemRead(qspi_get_device(), cfg, address, data, len, qspi_get_context());
if (st == CY_SMIF_SUCCESS) {
@@ -92,8 +86,8 @@
return rc;
}
-int psoc6_smif_write(const struct flash_area *fap,
- off_t addr,
+int cyw20829_smif_write(const struct flash_area *fap,
+ offset_t addr,
const void *data,
size_t len)
{
@@ -104,22 +98,29 @@
cfg = qspi_get_memory_config(FLASH_DEVICE_GET_EXT_INDEX(fap->fa_device_id));
- address = (uint32_t) addr - CY_SMIF_BASE_MEM_OFFSET;
+ address = (uint32_t) addr - CY_XIP_BASE;
- st = Cy_SMIF_MemWrite(qspi_get_device(), cfg, address, data, len, qspi_get_context());
+ /* NOTE:
+ * External flash chip used on PSVP for 20829 requires memory
+ * to be erased before write for correct operation.
+ */
+ st = Cy_SMIF_MemEraseSector(qspi_get_device(), cfg, address, qspi_get_erase_size(), qspi_get_context());
+
+ if (st == CY_SMIF_SUCCESS) {
+ st = Cy_SMIF_MemWrite(qspi_get_device(), cfg, address, data, len, qspi_get_context());
+ }
if (st == CY_SMIF_SUCCESS) {
rc = 0;
}
return rc;
}
-int psoc6_smif_erase(off_t addr, size_t size)
+int cyw20829_smif_erase(offset_t addr, size_t size)
{
int rc = -1;
cy_en_smif_status_t st = CY_SMIF_SUCCESS;
- uint32_t address;
- if (size > 0)
+ if (size > 0u)
{
/* It is erase sector-only
*
@@ -128,19 +129,20 @@
* eraseSectorSize far from each other;
*/
cy_stc_smif_mem_config_t *memCfg = qspi_get_memory_config(0);
+ uint32_t eraseSize = qspi_get_erase_size();
- address = ((uint32_t)addr - CY_SMIF_BASE_MEM_OFFSET ) & ~((uint32_t)(memCfg->deviceCfg->eraseSize - 1u));
+ uint32_t address = ((uint32_t)addr - CY_XIP_BASE) & ~((uint32_t)(eraseSize - 1u));
- while ((size > 0) && (CY_SMIF_SUCCESS == st))
+ while ((size > 0u) && (CY_SMIF_SUCCESS == st))
{
st = Cy_SMIF_MemEraseSector(qspi_get_device(),
memCfg,
address,
- memCfg->deviceCfg->eraseSize,
+ eraseSize,
qspi_get_context());
- size -= (size >= memCfg->deviceCfg->eraseSize) ? memCfg->deviceCfg->eraseSize : size;
- address += memCfg->deviceCfg->eraseSize;
+ size -= (size >= eraseSize) ? eraseSize : size;
+ address += eraseSize;
}
if (st == CY_SMIF_SUCCESS) {
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.c b/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.c
new file mode 100644
index 0000000..0643ea1
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.c
@@ -0,0 +1,350 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+/*******************************************************************************
+* \file cy_smif_hybrid_sect.c
+* \version 1.0
+*
+* \brief
+* This is the source file of external flash driver for Semper Flash with
+* hybrid sectors.
+*
+********************************************************************************
+* \copyright
+*
+* (c) 2020, Cypress Semiconductor Corporation
+* or a subsidiary of Cypress Semiconductor Corporation. All rights
+* reserved.
+*
+* This software, including source code, documentation and related
+* materials ("Software"), is owned by Cypress Semiconductor
+* Corporation or one of its subsidiaries ("Cypress") and is protected by
+* and subject to worldwide patent protection (United States and foreign),
+* United States copyright laws and international treaty provisions.
+* Therefore, you may use this Software only as provided in the license
+* agreement accompanying the software package from which you
+* obtained this Software ("EULA").
+*
+* If no EULA applies, Cypress hereby grants you a personal, non-
+* exclusive, non-transferable license to copy, modify, and compile the
+* Software source code solely for use in connection with Cypress?s
+* integrated circuit products. Any reproduction, modification, translation,
+* compilation, or representation of this Software except as specified
+* above is prohibited without the express written permission of Cypress.
+*
+* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
+* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
+* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+* PARTICULAR PURPOSE. Cypress reserves the right to make
+* changes to the Software without notice. Cypress does not assume any
+* liability arising out of the application or use of the Software or any
+* product or circuit described in the Software. Cypress does not
+* authorize its products for use in any products where a malfunction or
+* failure of the Cypress product may reasonably be expected to result in
+* significant property damage, injury or death ("High Risk Product"). By
+* including Cypress's product in a High Risk Product, the manufacturer
+* of such system or application assumes all risk of such use and in doing
+* so agrees to indemnify Cypress against all liability.
+*
+******************************************************************************/
+
+#include "flash_qspi.h"
+#include "cy_smif_hybrid_sect.h"
+
+#define SMIF_TRANSFER_TIMEOUT (1000UL) /* The timeout (microseconds) to use in polling of
+ * the transfer status of the SMIF block
+ */
+
+#define SEMPER_ID_MANUF (0x34U)
+#define SEMPER_ID_DEV_MSB1 (0x2AU)
+#define SEMPER_ID_DEV_MSB2 (0x2BU)
+#define SEMPER_ID_DEV_LSB1 (0x19U)
+#define SEMPER_ID_DEV_LSB2 (0x1AU)
+#define SEMPER_ID_DEV_LSB3 (0x1BU)
+#define SEMPER_ID_LEN (0x0FU)
+#define SEMPER_ID_SECTARCH (0x03U)
+#define SEMPER_ID_FAMILY (0x90U)
+
+#define SEMPER_WRARG_CMD (0x71U) /* Write Any Register command */
+#define SEMPER_RDARG_CMD (0x65U) /* Read Any Register command */
+#define SEMPER_EN4BA_CMD (0xB7U) /* Enter 4 Byte Address Mode */
+#define SEMPER_ER256_CMD (0xD8U) /* Erase 256-KB Sector */
+#define SEMPER_RDIDN_CMD (0x9FU) /* Read manufacturer and device identification */
+
+#define SEMPER_CFR2N_ADDR (0x00000003UL) /* Non-volatile Configuration Register 2 address */
+#define SEMPER_CFR3N_ADDR (0x00000004UL) /* Non-volatile Configuration Register 3 address */
+
+#define SEMPER_CFR2N_ADRBYT (1U << 7U) /* Address Byte Length selection bit offset in CFR2N register */
+#define SEMPER_CFR3N_UNHYSA (1U << 3U) /* Uniform or Hybrid Sector Architecture selection bit offset in CFR3N register */
+
+#define SEMPER_WRARG_DATA_INDEX (4U) /* Input data index for WRARG command */
+
+#define SEMPER_WR_NV_TIMEOUT (500000U) /* Nonvolatile Register Write operation timeout */
+#define SEMPER_ERASE_256KB_TIME (6000U) /* 256 KB Sector Erase Time in ms */
+
+#define SEMPER_ADDR_LEN (4U)
+
+#define SEMPER_ERASE_SIZE (262144u) /* Erase size for Semper Flash is 256KB */
+
+#define PARAM_ID_MSB_OFFSET (0x08U) /* The offset of Parameter ID MSB */
+#define PARAM_ID_LSB_MASK (0xFFUL) /* The mask of Parameter ID LSB */
+
+static cy_en_smif_status_t qspi_read_register(uint32_t address, uint8_t *value);
+static cy_en_smif_status_t qspi_write_register(uint32_t address, uint8_t value);
+static cy_en_smif_status_t qspi_enter_4byte_addr_mode(void);
+static void value_to_byte_array(uint32_t value, uint8_t *byteArray,
+ uint32_t startPos, uint32_t size);
+
+/* Checks device and manufacturer ID. Expects ID buffer to be 6 byte length */
+bool qspi_is_semper_flash(uint8_t const id[], uint16_t length)
+{
+ bool isSemper = false;
+
+ if(id != NULL)
+ {
+ isSemper = true;
+
+ /* Check Manufacturer and Device ID if it is Semper flash */
+ if(id[length - 6u] != SEMPER_ID_MANUF)
+ {
+ isSemper = false;
+ }
+
+ if(isSemper && ((id[length - 5u] != SEMPER_ID_DEV_MSB1) &&
+ (id[length - 5u] != SEMPER_ID_DEV_MSB2)))
+ {
+ isSemper = false;
+ }
+
+ if(isSemper && ((id[length - 4u] != SEMPER_ID_DEV_LSB1) &&
+ (id[length - 4u] != SEMPER_ID_DEV_LSB2) &&
+ (id[length - 4u] != SEMPER_ID_DEV_LSB3)))
+ {
+ isSemper = false;
+ }
+
+ if(isSemper && (id[length - 3u] != SEMPER_ID_LEN))
+ {
+ isSemper = false;
+ }
+
+ if(isSemper && (id[length - 2u] != SEMPER_ID_SECTARCH))
+ {
+ isSemper = false;
+ }
+
+ if(isSemper && (id[length - 1u] != SEMPER_ID_FAMILY))
+ {
+ isSemper = false;
+ }
+ }
+
+ return isSemper;
+}
+
+cy_en_smif_status_t qspi_configure_semper_flash(void)
+{
+ cy_en_smif_status_t status;
+ uint8_t regVal;
+ cy_stc_smif_mem_config_t *memCfg;
+
+ status = qspi_enter_4byte_addr_mode();
+
+ if(CY_SMIF_SUCCESS == status)
+ {
+ /* Set Address Byte Length selection to 4 bytes for instructions */
+ status = qspi_read_register(SEMPER_CFR2N_ADDR, ®Val);
+ if((CY_SMIF_SUCCESS == status) &&
+ ((regVal & SEMPER_CFR2N_ADRBYT) == 0U))
+ {
+ regVal |= SEMPER_CFR2N_ADRBYT;
+ status = qspi_write_register(SEMPER_CFR2N_ADDR, regVal);
+ }
+
+ /* Enable Uniform Sector Architecture selection */
+ if(CY_SMIF_SUCCESS == status)
+ {
+ status = qspi_read_register(SEMPER_CFR3N_ADDR, ®Val);
+ if((CY_SMIF_SUCCESS == status) &&
+ ((regVal & SEMPER_CFR3N_UNHYSA) == 0U))
+ {
+ regVal |= SEMPER_CFR3N_UNHYSA;
+ status = qspi_write_register(SEMPER_CFR3N_ADDR, regVal);
+ }
+ }
+
+ if(CY_SMIF_SUCCESS == status)
+ {
+ memCfg = qspi_get_memory_config(0);
+ memCfg->deviceCfg->eraseSize = SEMPER_ERASE_SIZE;
+ memCfg->deviceCfg->eraseCmd->command = SEMPER_ER256_CMD;
+ memCfg->deviceCfg->eraseTime = SEMPER_ERASE_256KB_TIME;
+ }
+ }
+
+ return status;
+}
+
+/* Read 6 bytes of Manufacturer and Device ID */
+cy_en_smif_status_t qspi_read_memory_id(uint8_t *id, uint16_t length)
+{
+ cy_en_smif_status_t status;
+ cy_stc_smif_mem_config_t *memCfg;
+ SMIF_Type *QSPIPort;
+ cy_stc_smif_context_t *QSPI_context;
+ uint16_t dummyCycles = 64u;
+
+ memCfg = qspi_get_memory_config(0);
+ QSPIPort = qspi_get_device();
+ QSPI_context = qspi_get_context();
+
+ status = Cy_SMIF_TransmitCommand(QSPIPort,
+ SEMPER_RDIDN_CMD,
+ CY_SMIF_WIDTH_SINGLE,
+ NULL,
+ 0u,
+ CY_SMIF_WIDTH_SINGLE,
+ memCfg->slaveSelect,
+ CY_SMIF_TX_NOT_LAST_BYTE,
+ QSPI_context);
+
+ if(CY_SMIF_SUCCESS == status)
+ {
+ status = Cy_SMIF_SendDummyCycles(QSPIPort, dummyCycles);
+ }
+
+ if(CY_SMIF_SUCCESS == status)
+ {
+ status = Cy_SMIF_ReceiveDataBlocking(QSPIPort, id, length,
+ CY_SMIF_WIDTH_SINGLE,
+ QSPI_context);
+ }
+
+ return status;
+}
+
+static cy_en_smif_status_t qspi_read_register(uint32_t address, uint8_t *value)
+{
+ cy_en_smif_status_t status;
+ cy_stc_smif_mem_config_t *memCfg;
+ SMIF_Type *QSPIPort;
+ cy_stc_smif_context_t *QSPI_context;
+ uint8_t addressArray[SEMPER_ADDR_LEN];
+ uint16_t dummyCycles = 8u;
+
+ value_to_byte_array(address, addressArray, 0u, sizeof(addressArray));
+
+ memCfg = qspi_get_memory_config(0);
+ QSPIPort = qspi_get_device();
+ QSPI_context = qspi_get_context();
+
+ status = Cy_SMIF_TransmitCommand(QSPIPort,
+ SEMPER_RDARG_CMD,
+ CY_SMIF_WIDTH_SINGLE,
+ addressArray,
+ sizeof(addressArray),
+ CY_SMIF_WIDTH_SINGLE,
+ memCfg->slaveSelect,
+ CY_SMIF_TX_NOT_LAST_BYTE,
+ QSPI_context);
+
+ if(CY_SMIF_SUCCESS == status)
+ {
+ status = Cy_SMIF_SendDummyCycles(QSPIPort, dummyCycles);
+ }
+
+ if(CY_SMIF_SUCCESS == status)
+ {
+ status = Cy_SMIF_ReceiveDataBlocking(QSPIPort, value,
+ CY_SMIF_READ_ONE_BYTE, CY_SMIF_WIDTH_SINGLE, QSPI_context);
+ }
+
+ return status;
+}
+
+static cy_en_smif_status_t qspi_write_register(uint32_t address, uint8_t value)
+{
+ cy_en_smif_status_t status;
+ cy_stc_smif_mem_config_t *memCfg;
+ SMIF_Type *QSPIPort;
+ cy_stc_smif_context_t *QSPI_context;
+ uint8_t data[SEMPER_ADDR_LEN + 1u];
+
+ value_to_byte_array(address, data, 0u, SEMPER_ADDR_LEN);
+
+ data[SEMPER_WRARG_DATA_INDEX] = value;
+
+ memCfg = qspi_get_memory_config(0);
+ QSPIPort = qspi_get_device();
+ QSPI_context = qspi_get_context();
+
+ status = Cy_SMIF_MemCmdWriteEnable(QSPIPort, memCfg, QSPI_context);
+
+ if(CY_SMIF_SUCCESS == status)
+ {
+ status = Cy_SMIF_TransmitCommand(QSPIPort, SEMPER_WRARG_CMD,
+ CY_SMIF_WIDTH_SINGLE,
+ data, sizeof(data),
+ CY_SMIF_WIDTH_SINGLE,
+ memCfg->slaveSelect,
+ CY_SMIF_TX_LAST_BYTE,
+ QSPI_context);
+ }
+
+ if(CY_SMIF_SUCCESS == status)
+ {
+ status = Cy_SMIF_MemIsReady(QSPIPort, memCfg, SEMPER_WR_NV_TIMEOUT,
+ QSPI_context);
+ }
+
+ return status;
+}
+
+static cy_en_smif_status_t qspi_enter_4byte_addr_mode(void)
+{
+ cy_en_smif_status_t status;
+ cy_stc_smif_mem_config_t *memCfg;
+ SMIF_Type *QSPIPort;
+ cy_stc_smif_context_t *QSPI_context;
+
+ memCfg = qspi_get_memory_config(0);
+ QSPIPort = qspi_get_device();
+ QSPI_context = qspi_get_context();
+
+ status = Cy_SMIF_TransmitCommand(QSPIPort, SEMPER_EN4BA_CMD,
+ CY_SMIF_WIDTH_SINGLE,
+ NULL,
+ CY_SMIF_CMD_WITHOUT_PARAM,
+ CY_SMIF_WIDTH_SINGLE,
+ memCfg->slaveSelect,
+ CY_SMIF_TX_LAST_BYTE,
+ QSPI_context);
+
+ return status;
+}
+
+static void value_to_byte_array(uint32_t value, uint8_t *byteArray, uint32_t startPos, uint32_t size)
+{
+ do
+ {
+ size--;
+ byteArray[size + startPos] = (uint8_t)(value & PARAM_ID_LSB_MASK);
+ value >>= PARAM_ID_MSB_OFFSET; /* Shift to get the next byte */
+ } while (size > 0U);
+}
diff --git a/boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h b/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.h
similarity index 78%
copy from boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h
copy to boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.h
index fe1150d..7e44118 100644
--- a/boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.h
@@ -1,14 +1,14 @@
-/***************************************************************************//**
-* \file cy_smif_psoc6.h
+/*******************************************************************************
+* \file cy_smif_hybrid_sect.h
* \version 1.0
*
* \brief
-* This is the header file for PSoC6 SMIF driver adoption layer.
+* This is the header file for Semper external flash driver.
*
********************************************************************************
* \copyright
*
-* © 2019, Cypress Semiconductor Corporation
+* © 2020, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
@@ -45,20 +45,13 @@
*
******************************************************************************/
-#ifndef CY_SMIF_PSOC6_H_
-#define CY_SMIF_PSOC6_H_
+#ifndef CY_SMIF_HYBRID_SECT_H
+#define CY_SMIF_HYBRID_SECT_H
-#include "stddef.h"
-#include "stdbool.h"
+#define EXT_MEMORY_ID_LENGTH (6U)
-#include "flash_qspi.h"
+bool qspi_is_semper_flash(uint8_t const id[], uint16_t length);
+cy_en_smif_status_t qspi_configure_semper_flash(void);
+cy_en_smif_status_t qspi_read_memory_id(uint8_t *id, uint16_t length);
-#ifndef off_t
-typedef long int off_t;
#endif
-
-int psoc6_smif_read(const struct flash_area *fap, off_t addr, void *data, size_t len);
-int psoc6_smif_write(const struct flash_area *fap, off_t addr, const void *data, size_t len);
-int psoc6_smif_erase(off_t addr, size_t size);
-
-#endif /* CY_SMIF_PSOC6_H_ */
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.c b/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.c
new file mode 100644
index 0000000..4bb8391
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.c
@@ -0,0 +1,634 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+/*******************************************************************************
+* \file flash_qspi.c
+* \version 1.0
+*
+* \brief
+* This is the source file of external flash driver adaptation layer between pdl
+* and standard MCUBoot code.
+*
+********************************************************************************
+* \copyright
+*
+* (c) 2020, Cypress Semiconductor Corporation
+* or a subsidiary of Cypress Semiconductor Corporation. All rights
+* reserved.
+*
+* This software, including source code, documentation and related
+* materials ("Software"), is owned by Cypress Semiconductor
+* Corporation or one of its subsidiaries ("Cypress") and is protected by
+* and subject to worldwide patent protection (United States and foreign),
+* United States copyright laws and international treaty provisions.
+* Therefore, you may use this Software only as provided in the license
+* agreement accompanying the software package from which you
+* obtained this Software ("EULA").
+*
+* If no EULA applies, Cypress hereby grants you a personal, non-
+* exclusive, non-transferable license to copy, modify, and compile the
+* Software source code solely for use in connection with Cypress?s
+* integrated circuit products. Any reproduction, modification, translation,
+* compilation, or representation of this Software except as specified
+* above is prohibited without the express written permission of Cypress.
+*
+* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
+* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
+* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+* PARTICULAR PURPOSE. Cypress reserves the right to make
+* changes to the Software without notice. Cypress does not assume any
+* liability arising out of the application or use of the Software or any
+* product or circuit described in the Software. Cypress does not
+* authorize its products for use in any products where a malfunction or
+* failure of the Cypress product may reasonably be expected to result in
+* significant property damage, injury or death ("High Risk Product"). By
+* including Cypress's product in a High Risk Product, the manufacturer
+* of such system or application assumes all risk of such use and in doing
+* so agrees to indemnify Cypress against all liability.
+*
+******************************************************************************/
+#include <stdio.h>
+
+#include "cy_sysclk.h"
+#include "cy_gpio.h"
+#include "cy_gpio.h"
+#include "cy_smif.h"
+
+#include "flash_qspi.h"
+#include "cy_smif_hybrid_sect.h"
+
+#define CY_SMIF_SYSCLK_HFCLK_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_4
+
+#define CY_SMIF_INIT_TRY_COUNT (10U)
+#define CY_SMIF_INIT_TRY_DELAY (500U)
+
+/* This is the board specific stuff that should align with your board.
+ *
+ * QSPI resources:
+ *
+ * SS0 - P11_2
+ * SS1 - P11_1
+ * SS2 - P11_0
+ * SS3 - P12_4
+ *
+ * D3 - P11_3
+ * D2 - P11_4
+ * D1 - P11_5
+ * D0 - P11_6
+ *
+ * SCK - P11_7
+ *
+ * SMIF Block - SMIF0
+ *
+ */
+
+/* HSIOM values for SMIF pins */
+#define CYBOOT_SMIF_SPI_CLOCK_HSIOM (P2_5_SMIF_SPIHB_CLK)
+#define CYBOOT_SMIF_SS0_HSIOM (P2_0_SMIF_SPIHB_SELECT0)
+#define CYBOOT_SMIF_SS1_HSIOM (P0_5_SMIF_SPIHB_SELECT1)
+#define CYBOOT_SMIF_DATA0_HSIOM (P2_4_SMIF_SPIHB_DATA0)
+#define CYBOOT_SMIF_DATA1_HSIOM (P2_3_SMIF_SPIHB_DATA1)
+#define CYBOOT_SMIF_DATA2_HSIOM (P2_2_SMIF_SPIHB_DATA2)
+#define CYBOOT_SMIF_DATA3_HSIOM (P2_1_SMIF_SPIHB_DATA3)
+
+/* SMIF ports and pins */
+#define CYBOOT_SMIF_SPI_CLOCK_PORT (GPIO_PRT2)
+#define CYBOOT_SMIF_SPI_CLOCK_PIN (5U)
+#define CYBOOT_SMIF_SS0_PORT (GPIO_PRT2)
+#define CYBOOT_SMIF_SS0_PIN (0U)
+#define CYBOOT_SMIF_SS1_PORT (GPIO_PRT0)
+#define CYBOOT_SMIF_SS1_PIN (5U)
+#define CYBOOT_SMIF_DATA0_PORT (GPIO_PRT2)
+#define CYBOOT_SMIF_DATA0_PIN (4U)
+#define CYBOOT_SMIF_DATA1_PORT (GPIO_PRT2)
+#define CYBOOT_SMIF_DATA1_PIN (3U)
+#define CYBOOT_SMIF_DATA2_PORT (GPIO_PRT2)
+#define CYBOOT_SMIF_DATA2_PIN (2U)
+#define CYBOOT_SMIF_DATA3_PORT (GPIO_PRT2)
+#define CYBOOT_SMIF_DATA3_PIN (1U)
+
+/* SMIF SlaveSelect Configurations */
+struct qspi_ss_config
+{
+ GPIO_PRT_Type* SS_Port;
+ uint32_t SS_Pin;
+ en_hsiom_sel_t SS_Mux;
+};
+
+#if (defined(PSOC_064_2M) || \
+ defined(PSOC_064_1M) || \
+ defined(PSOC_062_2M))
+ #define CY_BOOTLOADER_SMIF_SS_CFG_NUM 4
+#elif defined(PSOC_064_512K)
+ #define CY_BOOTLOADER_SMIF_SS_CFG_NUM 3
+#elif defined(CYW20829)
+ #define CY_BOOTLOADER_SMIF_SS_CFG_NUM 2
+#else
+#error "Platform device name is unsupported."
+#endif
+
+static cy_stc_smif_context_t QSPI_context;
+
+static cy_stc_smif_block_config_t *smif_blk_config;
+
+#ifndef CYW20829
+static struct qspi_ss_config qspi_SS_Configuration[CY_BOOTLOADER_SMIF_SS_CFG_NUM] =
+{
+ {
+ .SS_Port = GPIO_PRT11,
+ .SS_Pin = 2U,
+ .SS_Mux = P11_2_SMIF_SPI_SELECT0
+ },
+ {
+ .SS_Port = GPIO_PRT11,
+ .SS_Pin = 1U,
+ .SS_Mux = P11_1_SMIF_SPI_SELECT1
+ },
+#if(CY_BOOTLOADER_SMIF_SS_CFG_NUM > 2)
+ {
+ .SS_Port = GPIO_PRT11,
+ .SS_Pin = 0U,
+ .SS_Mux = P11_0_SMIF_SPI_SELECT2
+ },
+#endif
+#if(CY_BOOTLOADER_SMIF_SS_CFG_NUM > 3)
+ {
+ .SS_Port = GPIO_PRT12,
+ .SS_Pin = 4U,
+ .SS_Mux = P12_4_SMIF_SPI_SELECT3
+ }
+#endif
+};
+
+static GPIO_PRT_Type *D3Port = GPIO_PRT11;
+static uint32_t D3Pin = 3U;
+static en_hsiom_sel_t D3MuxPort = P11_3_SMIF_SPI_DATA3;
+
+static GPIO_PRT_Type *D2Port = GPIO_PRT11;
+static uint32_t D2Pin = 4U;
+static en_hsiom_sel_t D2MuxPort = P11_4_SMIF_SPI_DATA2;
+
+static GPIO_PRT_Type *D1Port = GPIO_PRT11;
+static uint32_t D1Pin = 5U;
+static en_hsiom_sel_t D1MuxPort = P11_5_SMIF_SPI_DATA1;
+
+static GPIO_PRT_Type *D0Port = GPIO_PRT11;
+static uint32_t D0Pin = 6U;
+static en_hsiom_sel_t D0MuxPort = P11_6_SMIF_SPI_DATA0;
+
+static GPIO_PRT_Type *SCKPort = GPIO_PRT11;
+static uint32_t SCKPin = 7U;
+static en_hsiom_sel_t SCKMuxPort = P11_7_SMIF_SPI_CLK;
+
+#else
+
+static struct qspi_ss_config qspi_SS_Configuration[CY_BOOTLOADER_SMIF_SS_CFG_NUM] =
+{
+ {
+ .SS_Port = GPIO_PRT2,
+ .SS_Pin = 0U,
+ .SS_Mux = P2_0_SMIF_SPIHB_SELECT0
+ },
+ {
+ .SS_Port = GPIO_PRT0,
+ .SS_Pin = 5U,
+ .SS_Mux = P0_5_SMIF_SPIHB_SELECT1
+ }
+};
+
+static GPIO_PRT_Type *D3Port = GPIO_PRT2;
+static uint32_t D3Pin = 1U;
+static en_hsiom_sel_t D3MuxPort = P2_1_SMIF_SPIHB_DATA3;
+
+static GPIO_PRT_Type *D2Port = GPIO_PRT2;
+static uint32_t D2Pin = 2U;
+static en_hsiom_sel_t D2MuxPort = P2_2_SMIF_SPIHB_DATA2;
+
+static GPIO_PRT_Type *D1Port = GPIO_PRT2;
+static uint32_t D1Pin = 3U;
+static en_hsiom_sel_t D1MuxPort = P2_3_SMIF_SPIHB_DATA1;
+
+static GPIO_PRT_Type *D0Port = GPIO_PRT2;
+static uint32_t D0Pin = 4U;
+static en_hsiom_sel_t D0MuxPort = P2_4_SMIF_SPIHB_DATA0;
+
+static GPIO_PRT_Type *SCKPort = GPIO_PRT2;
+static uint32_t SCKPin = 5U;
+static en_hsiom_sel_t SCKMuxPort = P2_5_SMIF_SPIHB_CLK;
+#endif
+
+static GPIO_PRT_Type *SS_Port;
+static uint32_t SS_Pin;
+static en_hsiom_sel_t SS_MuxPort;
+
+static SMIF_Type *QSPIPort = SMIF0;
+
+static cy_stc_smif_mem_cmd_t sfdpcmd =
+{
+ .command = 0x5A,
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ .mode = 0xFFFFFFFFU,
+ .dummyCycles = 8,
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+};
+
+static cy_stc_smif_mem_cmd_t rdcmd0;
+static cy_stc_smif_mem_cmd_t wrencmd0;
+static cy_stc_smif_mem_cmd_t wrdiscmd0;
+static cy_stc_smif_mem_cmd_t erasecmd0;
+static cy_stc_smif_mem_cmd_t chiperasecmd0;
+static cy_stc_smif_mem_cmd_t pgmcmd0;
+static cy_stc_smif_mem_cmd_t readsts0;
+static cy_stc_smif_mem_cmd_t readstsqecmd0;
+static cy_stc_smif_mem_cmd_t writestseqcmd0;
+
+static cy_stc_smif_mem_device_cfg_t dev_sfdp_0 =
+{
+ .numOfAddrBytes = 4,
+ .readSfdpCmd = &sfdpcmd,
+ .readCmd = &rdcmd0,
+ .writeEnCmd = &wrencmd0,
+ .writeDisCmd = &wrdiscmd0,
+ .programCmd = &pgmcmd0,
+ .eraseCmd = &erasecmd0,
+ .chipEraseCmd = &chiperasecmd0,
+ .readStsRegWipCmd = &readsts0,
+ .readStsRegQeCmd = &readstsqecmd0,
+ .writeStsRegQeCmd = &writestseqcmd0,
+};
+
+static cy_stc_smif_mem_config_t mem_sfdp_0 =
+{
+ /* The base address the memory slave is mapped to in the PSoC memory map.
+ Valid when the memory-mapped mode is enabled. */
+ .baseAddress = CY_XIP_BASE,
+ /* The size allocated in the PSoC memory map, for the memory slave device.
+ The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+/* .memMappedSize = 0x4000000U, */
+ .flags = CY_SMIF_FLAG_DETECT_SFDP,
+ .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+ .dataSelect = CY_SMIF_DATA_SEL0,
+ .deviceCfg = &dev_sfdp_0
+};
+
+static cy_stc_smif_mem_config_t *mems_sfdp[1] =
+{
+ &mem_sfdp_0
+};
+
+static cy_stc_smif_block_config_t smifBlockConfig_sfdp =
+{
+ .memCount = 1,
+ .memConfig = mems_sfdp,
+};
+
+static cy_stc_smif_config_t const QSPI_config =
+{
+ .mode = (uint32_t)CY_SMIF_NORMAL,
+ .deselectDelay = 1,
+#ifdef CYW20829
+ .rxClockSel = (uint32_t)CY_SMIF_SEL_INVERTED_FEEDBACK_CLK,
+#else
+ .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
+#endif
+ .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR
+};
+
+/* SMIF pinouts configurations */
+static cy_stc_gpio_pin_config_t QSPI_SS_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = P2_0_SMIF_SPIHB_SELECT0, /* lets use SS0 by default */
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+static const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = P2_1_SMIF_SPIHB_DATA3,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+static const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = P2_2_SMIF_SPIHB_DATA2,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+static const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = P2_3_SMIF_SPIHB_DATA1,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+static const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = P2_4_SMIF_SPIHB_DATA0,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+static const cy_stc_gpio_pin_config_t QSPI_SCK_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG,
+ .hsiom = P2_5_SMIF_SPIHB_CLK,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+
+static bool qspiInitiallyEnabled = false;
+static int32_t qspiReservations = EXT_FLASH_DEV_FAILED;
+
+static void qspi_get_initial_status(void)
+{
+ qspiInitiallyEnabled = (SMIF_CTL(QSPIPort) & SMIF_CTL_ENABLED_Msk) != 0u;
+}
+
+static bool qspi_is_configured(void)
+{
+ return qspiInitiallyEnabled;
+}
+
+cy_en_smif_status_t qspi_init_hardware(void)
+{
+ cy_en_smif_status_t st;
+
+ qspi_get_initial_status();
+
+ if (!qspi_is_configured()) {
+ (void)Cy_GPIO_Pin_Init(D3Port, D3Pin, &QSPI_DATA3_config);
+ Cy_GPIO_SetHSIOM(D3Port, D3Pin, D3MuxPort);
+
+ (void)Cy_GPIO_Pin_Init(D2Port, D2Pin, &QSPI_DATA2_config);
+ Cy_GPIO_SetHSIOM(D2Port, D2Pin, D2MuxPort);
+
+ (void)Cy_GPIO_Pin_Init(D1Port, D1Pin, &QSPI_DATA1_config);
+ Cy_GPIO_SetHSIOM(D1Port, D1Pin, D1MuxPort);
+
+ (void)Cy_GPIO_Pin_Init(D0Port, D0Pin, &QSPI_DATA0_config);
+ Cy_GPIO_SetHSIOM(D0Port, D0Pin, D0MuxPort);
+
+ (void)Cy_GPIO_Pin_Init(SCKPort, SCKPin, &QSPI_SCK_config);
+ Cy_GPIO_SetHSIOM(SCKPort, SCKPin, SCKMuxPort);
+
+ (void)Cy_GPIO_Pin_Init(SS_Port, SS_Pin, &QSPI_SS_config);
+ Cy_GPIO_SetHSIOM(SS_Port, SS_Pin, SS_MuxPort);
+
+ (void)Cy_SysClk_ClkHfSetSource((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+ (void)Cy_SysClk_ClkHfSetDivider((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SMIF_SYSCLK_HFCLK_DIVIDER);
+ (void)Cy_SysClk_ClkHfEnable((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH2);
+
+ st = Cy_SMIF_Init(QSPIPort, &QSPI_config, 1000, &QSPI_context);
+ if (st != CY_SMIF_SUCCESS) {
+ return st;
+ }
+ }
+ qspiReservations = EXT_FLASH_DEV_DISABLED;
+
+ return CY_SMIF_SUCCESS;
+}
+
+void qspi_enable(void)
+{
+ if (EXT_FLASH_DEV_FAILED != qspiReservations) {
+ if (EXT_FLASH_DEV_DISABLED == qspiReservations) {
+ /*
+ * Setup the interrupt for the SMIF block. For the CM33 there
+ * is a two stage process to setup the interrupts.
+ */
+ if (!qspi_is_configured()) {
+ Cy_SMIF_Enable(QSPIPort, &QSPI_context);
+ }
+ }
+ qspiReservations++;
+ }
+}
+
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
+CY_RAMFUNC_BEGIN /* SMIF is deinitialized inside! */
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
+void qspi_disable(void)
+{
+ if (EXT_FLASH_DEV_FAILED != qspiReservations) {
+ if (qspiReservations > EXT_FLASH_DEV_DISABLED) {
+ qspiReservations--;
+ if (EXT_FLASH_DEV_DISABLED == qspiReservations) {
+ if (!qspi_is_configured()) {
+ Cy_SMIF_Disable(QSPIPort);
+ }
+ }
+ }
+ }
+}
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
+CY_RAMFUNC_END /* SMIF will be deinitialized in this case! */
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
+
+cy_stc_smif_mem_config_t *qspi_get_memory_config(uint8_t index)
+{
+ return smif_blk_config->memConfig[index];
+}
+
+SMIF_Type *qspi_get_device(void)
+{
+ return QSPIPort;
+}
+
+cy_stc_smif_context_t *qspi_get_context(void)
+{
+ return &QSPI_context;
+}
+
+cy_en_smif_status_t qspi_init(cy_stc_smif_block_config_t *blk_config)
+{
+ cy_en_smif_status_t st;
+ uint8_t devIdBuff[EXT_MEMORY_ID_LENGTH];
+
+ st = qspi_init_hardware();
+ if (st == CY_SMIF_SUCCESS) {
+ qspi_enable();
+
+ smif_blk_config = blk_config;
+ st = Cy_SMIF_MemInit(QSPIPort, smif_blk_config, &QSPI_context);
+
+ if(st == CY_SMIF_SUCCESS) {
+ st = qspi_read_memory_id(devIdBuff, EXT_MEMORY_ID_LENGTH);
+ }
+
+ if(st == CY_SMIF_SUCCESS) {
+ if(qspi_is_semper_flash(devIdBuff, EXT_MEMORY_ID_LENGTH) == true) {
+ st = qspi_configure_semper_flash();
+ }
+ }
+
+ qspi_disable();
+ }
+
+ if(st != CY_SMIF_SUCCESS) {
+ qspiReservations = EXT_FLASH_DEV_FAILED;
+ }
+ return st;
+}
+
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
+CY_RAMFUNC_BEGIN /* SMIF is deinitialized inside! */
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
+void qspi_deinit(uint32_t smif_id)
+{
+ qspiReservations = EXT_FLASH_DEV_DISABLED + 1;
+
+ qspi_disable();
+
+ if (!qspi_is_configured()) {
+ Cy_SMIF_MemDeInit(QSPIPort);
+
+ (void)Cy_SysClk_ClkHfDisable((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1);
+
+ Cy_GPIO_Port_Deinit(qspi_SS_Configuration[smif_id-1U].SS_Port);
+ Cy_GPIO_Port_Deinit(SCKPort);
+ Cy_GPIO_Port_Deinit(D0Port);
+ Cy_GPIO_Port_Deinit(D1Port);
+ Cy_GPIO_Port_Deinit(D2Port);
+ Cy_GPIO_Port_Deinit(D3Port);
+ }
+}
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
+CY_RAMFUNC_END /* SMIF will be deinitialized in this case! */
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
+
+cy_en_smif_status_t qspi_init_sfdp(uint32_t smif_id)
+{
+ cy_en_smif_status_t stat = CY_SMIF_SUCCESS;
+
+ cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
+
+
+ switch(smif_id) {
+ case 1:
+ (*memCfg)->slaveSelect = CY_SMIF_SLAVE_SELECT_0;
+ break;
+ case 2:
+ (*memCfg)->slaveSelect = CY_SMIF_SLAVE_SELECT_1;
+ break;
+ default:
+ stat = CY_SMIF_BAD_PARAM;
+ break;
+ }
+
+ if(CY_SMIF_SUCCESS == stat) {
+ SS_Port = qspi_SS_Configuration[smif_id-1U].SS_Port;
+ SS_Pin = qspi_SS_Configuration[smif_id-1U].SS_Pin;
+ SS_MuxPort = qspi_SS_Configuration[smif_id-1U].SS_Mux;
+
+ QSPI_SS_config.hsiom = SS_MuxPort;
+
+
+ uint32_t try_count = CY_SMIF_INIT_TRY_COUNT;
+ do {
+ stat = qspi_init(&smifBlockConfig_sfdp);
+
+ try_count--;
+ if (stat != CY_SMIF_SUCCESS) {
+ Cy_SysLib_Delay(CY_SMIF_INIT_TRY_DELAY);
+ }
+ } while ((stat != CY_SMIF_SUCCESS) && (try_count > 0U));
+ }
+ return stat;
+}
+
+uint32_t qspi_get_prog_size(void)
+{
+ cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
+ return (*memCfg)->deviceCfg->programSize;
+}
+
+uint32_t qspi_get_erase_size(void)
+{
+ cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
+ return (*memCfg)->deviceCfg->eraseSize;
+}
+
+uint32_t qspi_get_mem_size(void)
+{
+ cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
+ return (*memCfg)->deviceCfg->memSize;
+}
+
+int32_t qspi_get_status(void)
+{
+ return qspiReservations;
+}
+
diff --git a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h b/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.h
similarity index 87%
copy from boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h
copy to boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.h
index 80e0d51..e8c4953 100644
--- a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.h
@@ -1,4 +1,4 @@
-/***************************************************************************//**
+/*******************************************************************************
* \file flash_qspi.h
* \version 1.0
*
@@ -44,27 +44,32 @@
* so agrees to indemnify Cypress against all liability.
*
******************************************************************************/
-#ifndef __FLASH_QSPI_H__
-#define __FLASH_QSPI_H__
+#ifndef FLASH_QSPI_H
+#define FLASH_QSPI_H
#include <stdint.h>
-#include "cy_pdl.h"
+#include "cy_sysint.h"
+#include "cy_smif.h"
+#include "cy_smif_memslot.h"
-/* make it exported if used in TOC (cy_serial_flash_prog.c) */
-/* cy_stc_smif_block_config_t smifBlockConfig_sfdp; */
+#define EXT_FLASH_DEV_DISABLED 0
+#define EXT_FLASH_DEV_FAILED -1
cy_en_smif_status_t qspi_init_sfdp(uint32_t smif_id);
cy_en_smif_status_t qspi_init(cy_stc_smif_block_config_t *blk_config);
cy_en_smif_status_t qspi_init_hardware(void);
+void qspi_deinit(uint32_t smif_id);
+
uint32_t qspi_get_prog_size(void);
uint32_t qspi_get_erase_size(void);
uint32_t qspi_get_mem_size(void);
+int32_t qspi_get_status(void);
+
+void qspi_enable(void);
+void qspi_disable(void);
SMIF_Type *qspi_get_device(void);
cy_stc_smif_context_t *qspi_get_context(void);
-cy_stc_smif_mem_config_t *qspi_get_memory_config(int index);
-void qspi_dump_device(cy_stc_smif_mem_device_cfg_t *dev);
+cy_stc_smif_mem_config_t *qspi_get_memory_config(uint8_t index);
-void qspi_deinit(uint32_t smif_id);
-
-#endif /* __FLASH_QSPI_H__ */
+#endif /* FLASH_QSPI_H */
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_multi2.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_multi2.json
new file mode 100644
index 0000000..8366917
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_multi2.json
@@ -0,0 +1,57 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60030000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60050000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_single.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_single.json
new file mode 100644
index 0000000..8c98f08
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_single.json
@@ -0,0 +1,39 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_multi2.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_multi2.json
new file mode 100644
index 0000000..8031750
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_multi2.json
@@ -0,0 +1,73 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x6007E000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x60060000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x14000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60030000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60050000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single.json
new file mode 100644
index 0000000..3fb2ac2
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single.json
@@ -0,0 +1,55 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x6007E000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x60060000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0xC000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json
new file mode 100644
index 0000000..b8f0835
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json
@@ -0,0 +1,83 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "service_app": {
+ "address": {
+ "description": "Address of the service application",
+ "value": "0x60070000"
+ },
+ "size": {
+ "description": "Size of the service application",
+ "value": "0x8000"
+ },
+ "params_address": {
+ "description": "Address of the service application input parameters",
+ "value": "0x60078000"
+ },
+ "params_size": {
+ "description": "Size of the service application input parameters",
+ "value": "0x400"
+ },
+ "desc_address": {
+ "description": "Address of the service application descriptor",
+ "value": "0x60078400"
+ },
+ "desc_size": {
+ "description": "Size of the service application descriptor",
+ "value": "0x20"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60030000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60050000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
new file mode 100644
index 0000000..d46066d
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
@@ -0,0 +1,65 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "service_app": {
+ "address": {
+ "description": "Address of the service application",
+ "value": "0x60070000"
+ },
+ "size": {
+ "description": "Size of the service application",
+ "value": "0x8000"
+ },
+ "params_address": {
+ "description": "Address of the service application input parameters",
+ "value": "0x60078000"
+ },
+ "params_size": {
+ "description": "Size of the service application input parameters",
+ "value": "0x400"
+ },
+ "desc_address": {
+ "description": "Address of the service application descriptor",
+ "value": "0x60078400"
+ },
+ "desc_size": {
+ "description": "Size of the service application descriptor",
+ "value": "0x20"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json
new file mode 100644
index 0000000..242f7cc
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json
@@ -0,0 +1,99 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x6007E000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x6005C000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x14000"
+ }
+ },
+ "service_app": {
+ "address": {
+ "description": "Address of the service application",
+ "value": "0x60070000"
+ },
+ "size": {
+ "description": "Size of the service application",
+ "value": "0x8000"
+ },
+ "params_address": {
+ "description": "Address of the service application input parameters",
+ "value": "0x60078000"
+ },
+ "params_size": {
+ "description": "Size of the service application input parameters",
+ "value": "0x400"
+ },
+ "desc_address": {
+ "description": "Address of the service application descriptor",
+ "value": "0x60078400"
+ },
+ "desc_size": {
+ "description": "Size of the service application descriptor",
+ "value": "0x20"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0xF000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x6003E000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0xF000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x6002F000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0xF000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x6004D000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0xF000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
new file mode 100644
index 0000000..addeee1
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
@@ -0,0 +1,81 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x6007E000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x60060000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0xC000"
+ }
+ },
+ "service_app": {
+ "address": {
+ "description": "Address of the service application",
+ "value": "0x60070000"
+ },
+ "size": {
+ "description": "Size of the service application",
+ "value": "0x8000"
+ },
+ "params_address": {
+ "description": "Address of the service application input parameters",
+ "value": "0x60078000"
+ },
+ "params_size": {
+ "description": "Size of the service application input parameters",
+ "value": "0x400"
+ },
+ "desc_address": {
+ "description": "Address of the service application descriptor",
+ "value": "0x60078400"
+ },
+ "desc_size": {
+ "description": "Size of the service application descriptor",
+ "value": "0x20"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h b/boot/cypress/cy_flash_pal/flash_cyw208xx/include/cy_smif_cyw20829.h
similarity index 85%
copy from boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h
copy to boot/cypress/cy_flash_pal/flash_cyw208xx/include/cy_smif_cyw20829.h
index fe1150d..42b0c1e 100644
--- a/boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/include/cy_smif_cyw20829.h
@@ -1,4 +1,4 @@
-/***************************************************************************//**
+/*******************************************************************************
* \file cy_smif_psoc6.h
* \version 1.0
*
@@ -45,20 +45,18 @@
*
******************************************************************************/
-#ifndef CY_SMIF_PSOC6_H_
-#define CY_SMIF_PSOC6_H_
+#ifndef CY_SMIF_CYW20829_H_
+#define CY_SMIF_CYW20829_H_
#include "stddef.h"
#include "stdbool.h"
#include "flash_qspi.h"
-#ifndef off_t
-typedef long int off_t;
-#endif
+typedef unsigned long offset_t;
-int psoc6_smif_read(const struct flash_area *fap, off_t addr, void *data, size_t len);
-int psoc6_smif_write(const struct flash_area *fap, off_t addr, const void *data, size_t len);
-int psoc6_smif_erase(off_t addr, size_t size);
+int cyw20829_smif_read(const struct flash_area *fap, offset_t addr, void *data, size_t len);
+int cyw20829_smif_write(const struct flash_area *fap, offset_t addr, const void *data, size_t len);
+int cyw20829_smif_erase(offset_t addr, size_t size);
-#endif /* CY_SMIF_PSOC6_H_ */
+#endif /* CY_SMIF_CYW20829_H_ */
diff --git a/boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h b/boot/cypress/cy_flash_pal/flash_cyw208xx/include/flash_map_backend/flash_map_backend.h
similarity index 81%
copy from boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h
copy to boot/cypress/cy_flash_pal/flash_cyw208xx/include/flash_map_backend/flash_map_backend.h
index 4b9409b..82c5578 100644
--- a/boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h
+++ b/boot/cypress/cy_flash_pal/flash_cyw208xx/include/flash_map_backend/flash_map_backend.h
@@ -14,7 +14,7 @@
* "License"); you may not use this file except in compliance
* with the License. You may obtain a copy of the License at
*
- * http://www.apache.org/licenses/LICENSE-2.0
+ * www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing,
* software distributed under the License is distributed on an
@@ -28,7 +28,6 @@
#ifndef FLASH_MAP_BACKEND_H
#define FLASH_MAP_BACKEND_H
-#include <mcuboot_config/mcuboot_config.h>
#include "cy_flash.h"
#define FLASH_DEVICE_INDEX_MASK (0x7Fu)
#define FLASH_DEVICE_GET_EXT_INDEX(n) ((n) & FLASH_DEVICE_INDEX_MASK)
@@ -39,7 +38,7 @@
#ifndef CY_BOOT_EXTERNAL_DEVICE_INDEX
/* assume first(one) SMIF device is used */
-#define CY_BOOT_EXTERNAL_DEVICE_INDEX (0)
+#define CY_BOOT_EXTERNAL_DEVICE_INDEX (0u)
#endif
/**
@@ -93,6 +92,26 @@
uint32_t fa_size;
};
+static inline uint8_t flash_area_get_id(const struct flash_area *fa)
+{
+ return fa->fa_id;
+}
+
+static inline uint8_t flash_area_get_device_id(const struct flash_area *fa)
+{
+ return fa->fa_device_id;
+}
+
+static inline uint32_t flash_area_get_off(const struct flash_area *fa)
+{
+ return fa->fa_off;
+}
+
+static inline uint32_t flash_area_get_size(const struct flash_area *fa)
+{
+ return fa->fa_size;
+}
+
/**
* @brief Structure describing a sector within a flash area.
*
@@ -112,6 +131,16 @@
uint32_t fs_size;
};
+static inline uint32_t flash_sector_get_off(const struct flash_sector *fs)
+{
+ return fs->fs_off;
+}
+
+static inline uint32_t flash_sector_get_size(const struct flash_sector *fs)
+{
+ return fs->fs_size;
+}
+
struct flash_map_entry {
uint32_t magic;
struct flash_area area;
@@ -128,7 +157,7 @@
/*< Opens the area for use. id is one of the `fa_id`s */
int flash_area_open(uint8_t id, const struct flash_area **fa);
-void flash_area_close(const struct flash_area *);
+void flash_area_close(const struct flash_area *fa);
/*< Reads `len` bytes of flash memory at `off` to the buffer at `dst` */
int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
uint32_t len);
@@ -137,8 +166,6 @@
const void *src, uint32_t len);
/*< Erases `len` bytes of flash memory at `off` */
int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len);
-/*< Erases aligned row of flash, where passed address resided */
-int flash_erase_row(uint32_t address);
/*< Returns this `flash_area`s alignment */
size_t flash_area_align(const struct flash_area *fa);
/*< Initializes an array of flash_area elements for the slot's sectors */
@@ -159,12 +186,16 @@
*/
uint8_t flash_area_erased_val(const struct flash_area *fa);
-/*
- * Reads len bytes from off, and checks if the read data is erased.
- *
- * Returns 1 if erased, 0 if non-erased, and -1 on failure.
- */
-int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off,
- void *dst, uint32_t len);
+// *****************************************************************************
+#ifdef MCUBOOT_ENC_IMAGES_XIP
+
+#include "bootutil/image.h"
+#include "bootutil/enc_key.h"
+
+int bootutil_img_encrypt(struct enc_key_data *enc_state, int image_index,
+ struct image_header *hdr, const struct flash_area *fap, uint32_t off, uint32_t sz,
+ uint32_t blk_off, uint8_t *buf);
+#endif /* MCUBOOT_ENC_IMAGES_XIP */
+
#endif /* FLASH_MAP_BACKEND_H */
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/cy_flash_map.c b/boot/cypress/cy_flash_pal/flash_psoc6/cy_flash_map.c
new file mode 100644
index 0000000..af17b0b
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/cy_flash_map.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2022 Infineon Technologies AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "mcuboot_config/mcuboot_config.h"
+#include "flash_map_backend/flash_map_backend.h"
+#include <sysflash/sysflash.h>
+
+#include "bootutil/bootutil_log.h"
+#include "bootutil/bootutil_public.h"
+#include "bootutil/fault_injection_hardening.h" /* for FIH_PANIC */
+
+#include "cy_flash.h"
+#include "cy_flash_map.h"
+
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+#include "cy_smif_psoc6.h"
+#endif
+
+#ifdef MCUBOOT_SWAP_USING_STATUS
+#include "swap_status.h"
+#endif
+
+#ifndef CY_BOOT_INTERNAL_FLASH_ERASE_VALUE
+/* This is the value of internal flash bytes after an erase */
+#define CY_BOOT_INTERNAL_FLASH_ERASE_VALUE (0x00u)
+#endif /* CY_BOOT_INTERNAL_FLASH_ERASE_VALUE */
+
+#ifndef CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE
+/* This is the value of external flash bytes after an erase */
+#define CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE (0xFFu)
+#endif /* CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE */
+
+/*
+ * Returns device flash start based on supported fd_id
+ */
+int flash_device_base(uint8_t fd_id, uintptr_t *ret)
+{
+ int rc = -1;
+
+ if (FLASH_DEVICE_INTERNAL_FLASH == fd_id) {
+ *ret = CY_FLASH_BASE;
+ rc = 0;
+ }
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ else if ((fd_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ *ret = CY_SMIF_BASE_MEM_OFFSET;
+ rc = 0;
+ }
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ else {
+ BOOT_LOG_ERR("invalid flash ID %u; expected %u or %u",
+ (unsigned)fd_id, FLASH_DEVICE_INTERNAL_FLASH,
+ FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX));
+ }
+
+ return rc;
+}
+
+/*
+ * Opens the area for use. id is one of the `fa_id`s
+ */
+int flash_area_open(uint8_t id, const struct flash_area **fa)
+{
+ int rc = -1;
+ uint32_t i = 0u;
+
+ while (NULL != boot_area_descs[i]) {
+
+ if (id == boot_area_descs[i]->fa_id) {
+ *fa = boot_area_descs[i];
+ rc = 0;
+ break;
+ }
+ i++;
+ }
+
+ return rc;
+}
+
+/*
+ * Clear pointer to flash area fa
+ */
+void flash_area_close(const struct flash_area *fa)
+{
+ (void)fa; /* Nothing to do there */
+}
+
+/*
+ * Reads `len` bytes of flash memory at `off` to the buffer at `dst`
+ */
+int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
+ uint32_t len)
+{
+ int rc = -1;
+ size_t addr = 0u;
+ uintptr_t flash_base = 0u;
+
+ if ((NULL != dst) && (NULL != fa)) {
+
+ if (off > fa->fa_size ||
+ len > fa->fa_size ||
+ off + len > fa->fa_size) {
+
+ return BOOT_EBADARGS;
+ }
+
+ rc = flash_device_base(fa->fa_device_id, &flash_base);
+
+ if (0 == rc) {
+
+ addr = flash_base + fa->fa_off + off;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ /* flash read by simple memory copying */
+ (void)memcpy((void *)dst, (const void *)((uint8_t *)addr), (size_t)len);
+ }
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ else {
+ rc = psoc6_smif_read(fa, addr, dst, len);
+ }
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ }
+ }
+
+ return rc;
+}
+
+/*
+ * Writes `len` bytes of flash memory at `off` from the buffer at `src`
+ */
+int flash_area_write(const struct flash_area *fa, uint32_t off,
+ const void *src, uint32_t len)
+{
+ int rc = BOOT_EFLASH;
+ size_t write_start_addr = 0u;
+ size_t write_end_addr = 0u;
+ const uint32_t * row_ptr = NULL;
+ uintptr_t flash_base = 0u;
+
+ if ( (NULL != src) && (NULL != fa) ) {
+
+ if (off > fa->fa_size ||
+ len > fa->fa_size ||
+ off + len > fa->fa_size) {
+
+ return BOOT_EBADARGS;
+ }
+
+ rc = flash_device_base(fa->fa_device_id, &flash_base);
+
+ if (0 == rc) {
+
+ write_start_addr = flash_base + fa->fa_off + off;
+ write_end_addr = flash_base + fa->fa_off + off + len;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+
+ uint32_t row_number = 0u;
+ uint32_t row_addr = 0u;
+
+ if (len % CY_FLASH_SIZEOF_ROW != 0u) {
+ return BOOT_EBADARGS;
+ }
+
+ if (write_start_addr % CY_FLASH_SIZEOF_ROW != 0u) {
+ return BOOT_EBADARGS;
+ }
+
+ row_number = (write_end_addr - write_start_addr) / CY_FLASH_SIZEOF_ROW;
+ row_addr = write_start_addr;
+
+ row_ptr = (const uint32_t *) src;
+
+ for (uint32_t i = 0; i < row_number; i++) {
+ if (Cy_Flash_WriteRow(row_addr, row_ptr) != CY_FLASH_DRV_SUCCESS) {
+ rc = BOOT_EFLASH;
+ break;
+ }
+
+ row_addr += (uint32_t) CY_FLASH_SIZEOF_ROW;
+ row_ptr = row_ptr + CY_FLASH_SIZEOF_ROW / 4U;
+ }
+ }
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) != 0u) {
+ rc = psoc6_smif_write(fa, write_start_addr, src, len);
+ }
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ else {
+ return BOOT_EFLASH;
+ }
+ }
+ }
+
+ return rc;
+}
+
+/*< Erases `len` bytes of flash memory at `off` */
+int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
+{
+ int rc = -1;
+ size_t erase_start_addr = 0u;
+ size_t erase_end_addr = 0u;
+ uintptr_t flash_base = 0u;
+
+ if (NULL != fa) {
+
+ if (off > fa->fa_size ||
+ len > fa->fa_size ||
+ off + len > fa->fa_size) {
+
+ return BOOT_EBADARGS;
+ }
+
+ rc = flash_device_base(fa->fa_device_id, &flash_base);
+
+ if (0 == rc) {
+
+ erase_start_addr = flash_base + fa->fa_off + off;
+ erase_end_addr = flash_base + fa->fa_off + off + len;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ uint32_t row_number = 0u;
+ uint32_t row_addr = 0u;
+ uint32_t row_start_addr = (erase_start_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;
+ uint32_t row_end_addr = (erase_end_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;
+
+ /* assume single row needs to be erased */
+ if (row_start_addr == row_end_addr) {
+ if (Cy_Flash_EraseRow(row_start_addr) != CY_FLASH_DRV_SUCCESS) {
+ rc = BOOT_EFLASH;
+ }
+ }
+ else {
+
+ row_number = (row_end_addr - row_start_addr) / CY_FLASH_SIZEOF_ROW;
+
+ while (0u != row_number) {
+ row_number--;
+ row_addr = row_start_addr + row_number * (uint32_t) CY_FLASH_SIZEOF_ROW;
+ if (Cy_Flash_EraseRow(row_addr) != CY_FLASH_DRV_SUCCESS) {
+ rc = BOOT_EFLASH;
+ break;
+ }
+ }
+ }
+ }
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ else {
+ rc = psoc6_smif_erase(erase_start_addr, len);
+ }
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ }
+ }
+
+ return rc;
+}
+
+/*< Returns this `flash_area`s alignment */
+size_t flash_area_align(const struct flash_area *fa)
+{
+ size_t rc = 0u; /* error code (alignment cannot be zero) */
+
+ if (NULL != fa) {
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ rc = CY_FLASH_ALIGN;
+ }
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ rc = qspi_get_prog_size();
+ }
+ else {
+ /* No action required */
+ }
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ }
+
+ return rc;
+}
+
+#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+/*< Initializes an array of flash_area elements for the slot's sectors */
+int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa)
+{
+ int rc = 0;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ (void)idx;
+ (void)cnt;
+ rc = 0;
+ }
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ (void)idx;
+ (void)cnt;
+ rc = 0;
+ }
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ else
+ {
+ /* incorrect/non-existing flash device id */
+ rc = -1;
+ }
+ return rc;
+}
+#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
+
+/*
+ * This depends on the mappings defined in sysflash.h.
+ * MCUBoot uses continuous numbering for the primary slot, the secondary slot,
+ * and the scratch while zephyr might number it differently.
+ */
+int flash_area_id_from_multi_image_slot(int image_index, int slot)
+{
+ int rc;
+ if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
+ return -1;
+ }
+
+ switch (slot) {
+ case 0:
+ rc = (int)FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index);
+ break;
+ case 1:
+ rc = (int)FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index);
+ break;
+ case 2:
+ rc = (int)FLASH_AREA_IMAGE_SCRATCH;
+ break;
+ default:
+ rc = -1; /* flash_area_open will fail on that */
+ break;
+ }
+ return rc;
+}
+
+int flash_area_id_from_image_slot(int slot)
+{
+ return flash_area_id_from_multi_image_slot(0, slot);
+}
+
+int flash_area_id_to_multi_image_slot(int image_index, int area_id)
+{
+ if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
+ return -1;
+ }
+
+ if (area_id == (int) FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index)) {
+ return 0;
+ }
+ if (area_id == (int) FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index)) {
+ return 1;
+ }
+
+ return -1;
+}
+
+int flash_area_id_to_image_slot(int area_id)
+{
+ return flash_area_id_to_multi_image_slot(0, area_id);
+}
+
+uint8_t flash_area_erased_val(const struct flash_area *fa)
+{
+ uint8_t ret = 0u;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ ret = (uint8_t) CY_BOOT_INTERNAL_FLASH_ERASE_VALUE;
+ }
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) != 0u) {
+ ret = (uint8_t) CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE;
+ }
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ else {
+ ret = 0u; /* The variable is reassigned to make the statement comply with the MISRA rule 15.7 */
+ FIH_PANIC; /* There is no appropriate error code */
+ }
+
+ return ret;
+}
+
+#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
+{
+ int rc = 0;
+ uint32_t i = 0u;
+ struct flash_area *fa = NULL;
+ size_t sectors_n = 0u;
+ uint32_t my_sector_addr = 0u;
+ uint32_t my_sector_size = 0u;
+
+ while (NULL != boot_area_descs[i]) {
+ if (idx == (int) boot_area_descs[i]->fa_id) {
+ fa = boot_area_descs[i];
+ break;
+ }
+ i++;
+ }
+
+ if ( (NULL != fa) && (NULL != cnt) && (NULL != ret) ) {
+ size_t sector_size = 0;
+ size_t area_size = fa->fa_size;
+
+ if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && defined(MCUBOOT_SWAP_USING_STATUS) && !defined(MCUBOOT_SWAP_USING_SCRATCH)
+ if (idx == (int) FLASH_AREA_IMAGE_SWAP_STATUS) {
+ sector_size = CY_FLASH_SIZEOF_ROW;
+ }
+ else {
+ sector_size = qspi_get_erase_size();
+#else
+ sector_size = CY_FLASH_SIZEOF_ROW;
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && defined(MCUBOOT_SWAP_USING_STATUS) && !defined(MCUBOOT_SWAP_USING_SCRATCH) */
+ }
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ /* implement for SMIF */
+ /* lets assume they are equal */
+#if defined(MCUBOOT_SWAP_USING_STATUS) || defined(USE_XIP)
+ sector_size = qspi_get_erase_size();
+#else
+ sector_size = CY_FLASH_SIZEOF_ROW;
+#endif /* MCUBOOT_SWAP_USING_STATUS */
+ }
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ else {
+ /* fa->fa_device_id = FLASH_DEVICE_UNDEFINED,
+ in this case the area should be empty with a very simple sector size of 1 byte */
+ area_size = 0u;
+ sector_size = 1u;
+ }
+
+ sectors_n = (area_size + (sector_size - 1U)) / sector_size;
+
+ if (sectors_n > (size_t)MCUBOOT_MAX_IMG_SECTORS) {
+ sector_size *= 2u;
+ }
+
+ sectors_n = 0;
+ my_sector_addr = fa->fa_off;
+ while (area_size > 0u) {
+ my_sector_size = sector_size;
+#ifdef MCUBOOT_SWAP_USING_SCRATCH
+ uint32_t my_sector_offs = my_sector_addr % my_sector_size;
+
+ if (my_sector_offs != 0u) {
+ my_sector_size = sector_size - my_sector_offs;
+ }
+
+ if (my_sector_size > area_size) {
+ my_sector_size = area_size;
+ }
+#endif /* MCUBOOT_SWAP_USING_SCRATCH */
+ ret[sectors_n].fs_size = my_sector_size;
+ ret[sectors_n].fs_off = my_sector_addr;
+
+ my_sector_addr += my_sector_size;
+ area_size -= my_sector_size;
+ sectors_n++;
+ }
+
+ if (sectors_n <= *cnt) {
+ *cnt = sectors_n;
+ }
+ else {
+ rc = -1;
+ }
+ }
+ else {
+ rc = -1;
+ }
+
+ return rc;
+}
+#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
diff --git a/boot/cypress/cy_flash_pal/cy_smif_psoc6.c b/boot/cypress/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c
similarity index 93%
rename from boot/cypress/cy_flash_pal/cy_smif_psoc6.c
rename to boot/cypress/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c
index c2dd5c3..d8f7a7e 100644
--- a/boot/cypress/cy_flash_pal/cy_smif_psoc6.c
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c
@@ -45,16 +45,12 @@
* so agrees to indemnify Cypress against all liability.
*
******************************************************************************/
+#ifndef CYW20829
+
#include "string.h"
#include "stdlib.h"
#include "stdbool.h"
-#ifdef MCUBOOT_HAVE_ASSERT_H
-#include "mcuboot_config/mcuboot_assert.h"
-#else
-#include <assert.h>
-#endif
-
#include "flash_map_backend/flash_map_backend.h"
#include <sysflash/sysflash.h>
@@ -72,7 +68,7 @@
#define PSOC6_FLASH_ERASE_BLOCK_SIZE CY_FLASH_SIZEOF_ROW /* PSoC6 Flash erases by Row */
int psoc6_smif_read(const struct flash_area *fap,
- off_t addr,
+ offset_t addr,
void *data,
size_t len)
{
@@ -93,7 +89,7 @@
}
int psoc6_smif_write(const struct flash_area *fap,
- off_t addr,
+ offset_t addr,
const void *data,
size_t len)
{
@@ -113,13 +109,13 @@
return rc;
}
-int psoc6_smif_erase(off_t addr, size_t size)
+int psoc6_smif_erase(offset_t addr, size_t size)
{
int rc = -1;
cy_en_smif_status_t st = CY_SMIF_SUCCESS;
uint32_t address;
- if (size > 0)
+ if (size > 0u)
{
/* It is erase sector-only
*
@@ -131,7 +127,7 @@
address = ((uint32_t)addr - CY_SMIF_BASE_MEM_OFFSET ) & ~((uint32_t)(memCfg->deviceCfg->eraseSize - 1u));
- while ((size > 0) && (CY_SMIF_SUCCESS == st))
+ while ((size > 0u) && (CY_SMIF_SUCCESS == st))
{
st = Cy_SMIF_MemEraseSector(qspi_get_device(),
memCfg,
@@ -150,3 +146,5 @@
return rc;
}
+
+#endif /* CY20829 */
diff --git a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.c b/boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
similarity index 83%
rename from boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.c
rename to boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
index 6ac5894..f62c3eb 100644
--- a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.c
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
@@ -95,7 +95,7 @@
struct qspi_ss_config
{
GPIO_PRT_Type* SS_Port;
- int SS_Pin;
+ uint32_t SS_Pin;
en_hsiom_sel_t SS_Mux;
};
@@ -104,55 +104,55 @@
defined(PSOC_062_2M) || \
defined(PSOC_062_1M))
#define CY_BOOTLOADER_SMIF_SS_CFG_NUM 4
-#elif defined(PSOC_064_512K) || defined(PSOC_062_512K)
+#elif defined(PSOC_064_512K) || defined(PSOC_062_512K) || defined(CYW20829)
#define CY_BOOTLOADER_SMIF_SS_CFG_NUM 3
#else
#error "Platform device name is unsupported."
#endif
-struct qspi_ss_config qspi_SS_Configuration[CY_BOOTLOADER_SMIF_SS_CFG_NUM] =
+static struct qspi_ss_config qspi_SS_Configuration[CY_BOOTLOADER_SMIF_SS_CFG_NUM] =
{
{
.SS_Port = GPIO_PRT11,
- .SS_Pin = 2,
+ .SS_Pin = 2u,
.SS_Mux = P11_2_SMIF_SPI_SELECT0
},
{
.SS_Port = GPIO_PRT11,
- .SS_Pin = 1,
+ .SS_Pin = 1u,
.SS_Mux = P11_1_SMIF_SPI_SELECT1
},
{
.SS_Port = GPIO_PRT11,
- .SS_Pin = 0,
+ .SS_Pin = 0u,
.SS_Mux = P11_0_SMIF_SPI_SELECT2
},
#if(CY_BOOTLOADER_SMIF_SS_CFG_NUM > 3)
{
.SS_Port = GPIO_PRT12,
- .SS_Pin = 4,
+ .SS_Pin = 4u,
.SS_Mux = P12_4_SMIF_SPI_SELECT3
}
#endif
};
static GPIO_PRT_Type *D3Port = GPIO_PRT11;
-static int D3Pin = 3;
+static uint32_t D3Pin = 3u;
static en_hsiom_sel_t D3MuxPort = P11_3_SMIF_SPI_DATA3;
static GPIO_PRT_Type *D2Port = GPIO_PRT11;
-static int D2Pin = 4;
+static uint32_t D2Pin = 4u;
static en_hsiom_sel_t D2MuxPort = P11_4_SMIF_SPI_DATA2;
static GPIO_PRT_Type *D1Port = GPIO_PRT11;
-static int D1Pin = 5;
+static uint32_t D1Pin = 5u;
static en_hsiom_sel_t D1MuxPort = P11_5_SMIF_SPI_DATA1;
static GPIO_PRT_Type *D0Port = GPIO_PRT11;
-static int D0Pin = 6;
+static uint32_t D0Pin = 6u;
static en_hsiom_sel_t D0MuxPort = P11_6_SMIF_SPI_DATA0;
static GPIO_PRT_Type *SCKPort = GPIO_PRT11;
-static int SCKPin = 7;
+static uint32_t SCKPin = 7u;
static en_hsiom_sel_t SCKMuxPort = P11_7_SMIF_SPI_CLK;
static SMIF_Type *QSPIPort = SMIF0;
@@ -196,23 +196,22 @@
{
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
- .baseAddress = 0x18000000U,
+ .baseAddress = CY_XIP_BASE,
/* The size allocated in the PSoC memory map, for the memory slave device.
The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-/* .memMappedSize = 0x4000000U, */
- .flags = CY_SMIF_FLAG_DETECT_SFDP,
+ .memMappedSize = CY_XIP_SIZE,
+ .flags = CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MEMORY_MAPPED,
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
.dataSelect = CY_SMIF_DATA_SEL0,
.deviceCfg = &dev_sfdp_0
};
+
static cy_stc_smif_mem_config_t *mems_sfdp[1] =
{
&mem_sfdp_0
};
-/* make it exported if used in TOC (cy_serial_flash_prog.c) */
-/* cy_stc_smif_block_config_t smifBlockConfig_sfdp = */
static cy_stc_smif_block_config_t smifBlockConfig_sfdp =
{
.memCount = 1,
@@ -223,7 +222,7 @@
static cy_stc_smif_context_t QSPI_context;
-cy_stc_smif_config_t const QSPI_config =
+static cy_stc_smif_config_t const QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = 1,
@@ -231,12 +230,14 @@
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR
};
-cy_stc_sysint_t smifIntConfig =
+#ifdef CM0P
+static cy_stc_sysint_t smifIntConfig =
{/* ATTENTION: make sure proper Interrupts configured for CM0p or M4 cores */
.intrSrc = NvicMux7_IRQn,
.cm0pSrc = smif_interrupt_IRQn,
.intrPriority = 1
};
+#endif
/* SMIF pinouts configurations */
static cy_stc_gpio_pin_config_t QSPI_SS_config =
@@ -255,7 +256,7 @@
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
+static const cy_stc_gpio_pin_config_t QSPI_DATA3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
@@ -271,7 +272,7 @@
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
+static const cy_stc_gpio_pin_config_t QSPI_DATA2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
@@ -287,7 +288,7 @@
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
+static const cy_stc_gpio_pin_config_t QSPI_DATA1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
@@ -303,7 +304,7 @@
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
+static const cy_stc_gpio_pin_config_t QSPI_DATA0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
@@ -319,7 +320,7 @@
.vrefSel = 0UL,
.vohSel = 0UL,
};
-const cy_stc_gpio_pin_config_t QSPI_SCK_config =
+static const cy_stc_gpio_pin_config_t QSPI_SCK_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
@@ -336,64 +337,71 @@
.vohSel = 0UL,
};
-void Isr_SMIF(void)
+#ifdef CM0P
+static void Isr_SMIF(void)
{
Cy_SMIF_Interrupt(QSPIPort, &QSPI_context);
}
+#endif
cy_en_smif_status_t qspi_init_hardware(void)
{
cy_en_smif_status_t st;
- Cy_GPIO_Pin_Init(D3Port, D3Pin, &QSPI_DATA3_config);
+ (void)Cy_GPIO_Pin_Init(D3Port, D3Pin, &QSPI_DATA3_config);
Cy_GPIO_SetHSIOM(D3Port, D3Pin, D3MuxPort);
- Cy_GPIO_Pin_Init(D2Port, D2Pin, &QSPI_DATA2_config);
+ (void)Cy_GPIO_Pin_Init(D2Port, D2Pin, &QSPI_DATA2_config);
Cy_GPIO_SetHSIOM(D2Port, D2Pin, D2MuxPort);
- Cy_GPIO_Pin_Init(D1Port, D1Pin, &QSPI_DATA1_config);
+ (void)Cy_GPIO_Pin_Init(D1Port, D1Pin, &QSPI_DATA1_config);
Cy_GPIO_SetHSIOM(D1Port, D1Pin, D1MuxPort);
- Cy_GPIO_Pin_Init(D0Port, D0Pin, &QSPI_DATA0_config);
+ (void)Cy_GPIO_Pin_Init(D0Port, D0Pin, &QSPI_DATA0_config);
Cy_GPIO_SetHSIOM(D0Port, D0Pin, D0MuxPort);
- Cy_GPIO_Pin_Init(SCKPort, SCKPin, &QSPI_SCK_config);
+ (void)Cy_GPIO_Pin_Init(SCKPort, SCKPin, &QSPI_SCK_config);
Cy_GPIO_SetHSIOM(SCKPort, SCKPin, SCKMuxPort);
- Cy_SysClk_ClkHfSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SYSCLK_CLKHF_IN_CLKPATH0);
- Cy_SysClk_ClkHfSetDivider(CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SMIF_SYSCLK_HFCLK_DIVIDER);
- Cy_SysClk_ClkHfEnable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
+ (void)Cy_SysClk_ClkHfSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+ (void)Cy_SysClk_ClkHfSetDivider(CY_SYSCLK_CLKHF_IN_CLKPATH2, CY_SMIF_SYSCLK_HFCLK_DIVIDER);
+ (void)Cy_SysClk_ClkHfEnable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
/*
* Setup the interrupt for the SMIF block. For the CM0 there
* is a two stage process to setup the interrupts.
*/
- Cy_SysInt_Init(&smifIntConfig, Isr_SMIF);
+#ifdef CM0P
+ (void)Cy_SysInt_Init(&smifIntConfig, Isr_SMIF);
+#endif
st = Cy_SMIF_Init(QSPIPort, &QSPI_config, 1000, &QSPI_context);
if (st != CY_SMIF_SUCCESS)
{
return st;
}
+
+#ifdef CM0P
NVIC_EnableIRQ(smifIntConfig.intrSrc); /* Finally, Enable the SMIF interrupt */
+#endif
Cy_SMIF_Enable(QSPIPort, &QSPI_context);
return CY_SMIF_SUCCESS;
}
-cy_stc_smif_mem_config_t *qspi_get_memory_config(int index)
+cy_stc_smif_mem_config_t *qspi_get_memory_config(uint8_t index)
{
return smif_blk_config->memConfig[index];
}
-SMIF_Type *qspi_get_device()
+SMIF_Type *qspi_get_device(void)
{
return QSPIPort;
}
-cy_stc_smif_context_t *qspi_get_context()
+cy_stc_smif_context_t *qspi_get_context(void)
{
return &QSPI_context;
}
@@ -418,7 +426,7 @@
cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
GPIO_PRT_Type *SS_Port;
- int SS_Pin;
+ uint32_t SS_Pin;
en_hsiom_sel_t SS_MuxPort;
switch(smif_id)
@@ -444,13 +452,13 @@
if(CY_SMIF_SUCCESS == stat)
{
- SS_Port = qspi_SS_Configuration[smif_id-1].SS_Port;
- SS_Pin = qspi_SS_Configuration[smif_id-1].SS_Pin;
- SS_MuxPort = qspi_SS_Configuration[smif_id-1].SS_Mux;
+ SS_Port = qspi_SS_Configuration[smif_id-1U].SS_Port;
+ SS_Pin = qspi_SS_Configuration[smif_id-1U].SS_Pin;
+ SS_MuxPort = qspi_SS_Configuration[smif_id-1U].SS_Mux;
QSPI_SS_config.hsiom = SS_MuxPort;
- Cy_GPIO_Pin_Init(SS_Port, SS_Pin, &QSPI_SS_config);
+ (void)Cy_GPIO_Pin_Init(SS_Port, SS_Pin, &QSPI_SS_config);
Cy_GPIO_SetHSIOM(SS_Port, SS_Pin, SS_MuxPort);
uint32_t try_count = CY_SMIF_INIT_TRY_COUNT;
@@ -491,15 +499,31 @@
Cy_SMIF_Disable(QSPIPort);
- Cy_SysClk_ClkHfDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
+ (void)Cy_SysClk_ClkHfDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
+#ifdef CM0P
NVIC_DisableIRQ(smifIntConfig.intrSrc);
Cy_SysInt_DisconnectInterruptSource(smifIntConfig.intrSrc, smifIntConfig.cm0pSrc);
+#endif
- Cy_GPIO_Port_Deinit(qspi_SS_Configuration[smif_id-1].SS_Port);
+ Cy_GPIO_Port_Deinit(qspi_SS_Configuration[smif_id-1U].SS_Port);
Cy_GPIO_Port_Deinit(SCKPort);
Cy_GPIO_Port_Deinit(D0Port);
Cy_GPIO_Port_Deinit(D1Port);
Cy_GPIO_Port_Deinit(D2Port);
Cy_GPIO_Port_Deinit(D3Port);
}
+
+void qspi_set_mode(cy_en_smif_mode_t mode)
+{
+ SMIF_Type* smif_mem = qspi_get_device();
+
+ Cy_SMIF_SetMode(smif_mem, mode);
+}
+
+cy_en_smif_mode_t qspi_get_mode(void)
+{
+ SMIF_Type* smif_mem = qspi_get_device();
+
+ return Cy_SMIF_GetMode(smif_mem);
+}
diff --git a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h b/boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
similarity index 89%
rename from boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h
rename to boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
index 80e0d51..1458091 100644
--- a/boot/cypress/cy_flash_pal/flash_qspi/flash_qspi.h
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
@@ -44,15 +44,12 @@
* so agrees to indemnify Cypress against all liability.
*
******************************************************************************/
-#ifndef __FLASH_QSPI_H__
-#define __FLASH_QSPI_H__
+#ifndef FLASH_QSPI_H
+#define FLASH_QSPI_H
#include <stdint.h>
#include "cy_pdl.h"
-/* make it exported if used in TOC (cy_serial_flash_prog.c) */
-/* cy_stc_smif_block_config_t smifBlockConfig_sfdp; */
-
cy_en_smif_status_t qspi_init_sfdp(uint32_t smif_id);
cy_en_smif_status_t qspi_init(cy_stc_smif_block_config_t *blk_config);
cy_en_smif_status_t qspi_init_hardware(void);
@@ -62,9 +59,12 @@
SMIF_Type *qspi_get_device(void);
cy_stc_smif_context_t *qspi_get_context(void);
-cy_stc_smif_mem_config_t *qspi_get_memory_config(int index);
-void qspi_dump_device(cy_stc_smif_mem_device_cfg_t *dev);
+cy_stc_smif_mem_config_t *qspi_get_memory_config(uint8_t index);
void qspi_deinit(uint32_t smif_id);
-#endif /* __FLASH_QSPI_H__ */
+void qspi_set_mode(cy_en_smif_mode_t mode);
+cy_en_smif_mode_t qspi_get_mode(void);
+
+
+#endif /* FLASH_QSPI_H */
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi.json
new file mode 100644
index 0000000..dea92e9
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi.json
@@ -0,0 +1,51 @@
+{
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x10028000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10038000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x10058000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi_smif.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi_smif.json
new file mode 100644
index 0000000..12fce09
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi_smif.json
@@ -0,0 +1,56 @@
+{
+ "external_flash": [
+ {
+ "model": "S25HS256T"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x40200"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18000000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x40200"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10058200"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x40200"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18240000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x40200"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single.json
new file mode 100644
index 0000000..b377c7a
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single.json
@@ -0,0 +1,33 @@
+{
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x10028000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single_smif.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single_smif.json
new file mode 100644
index 0000000..d3866d0
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single_smif.json
@@ -0,0 +1,38 @@
+{
+ "external_flash": [
+ {
+ "model": "S25HS256T"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x40200"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18000000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x40200"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi.json
new file mode 100644
index 0000000..67c0557
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi.json
@@ -0,0 +1,67 @@
+{
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x1007A800"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x10078000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x2800"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x10028000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10038000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x10058000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi_smif.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi_smif.json
new file mode 100644
index 0000000..cd80107
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi_smif.json
@@ -0,0 +1,72 @@
+{
+ "external_flash": [
+ {
+ "model": "S25HS256T"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x18440000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x80000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x10098400"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x3c00"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x40200"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18000000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x40200"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10058200"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x40200"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18240000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x40200"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_shared.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_shared.json
new file mode 100644
index 0000000..90853dc
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_shared.json
@@ -0,0 +1,74 @@
+{
+ "boot_and_upgrade": {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x1007A800"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x10078000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x2800"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "shared_slot": {
+ "description": "Using shared secondary slot",
+ "value": true
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x10038200"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ },
+ "application_2": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10028000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "shared_slot": {
+ "description": "Using shared secondary slot",
+ "value": true
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x10038400"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json
new file mode 100644
index 0000000..ca0f119
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json
@@ -0,0 +1,49 @@
+{
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x10040000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x2000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x10038000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x1800"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x10028000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single_smif.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single_smif.json
new file mode 100644
index 0000000..f921bba
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single_smif.json
@@ -0,0 +1,54 @@
+{
+ "external_flash": [
+ {
+ "model": "S25HS256T"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x18440000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x80000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x10058200"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x2400"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x40200"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18000000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x40200"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_overwrite.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_overwrite.json
new file mode 100644
index 0000000..92e26e2
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_overwrite.json
@@ -0,0 +1,39 @@
+{
+ "external_flash": [
+ {
+ "model": "S25HS256T",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x18000000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x80000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18080000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x80000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_swap.json b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_swap.json
new file mode 100644
index 0000000..e0a7267
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_swap.json
@@ -0,0 +1,55 @@
+{
+ "external_flash": [
+ {
+ "model": "S25HS256T",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x10000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x18000"
+ },
+ "scratch_address": {
+ "description": "Address of the scratch area",
+ "value": "0x18440000"
+ },
+ "scratch_size": {
+ "description": "Size of the scratch area",
+ "value": "0x80000"
+ },
+ "status_address": {
+ "description": "Address of the swap status partition",
+ "value": "0x10018000"
+ },
+ "status_size": {
+ "description": "Size of the swap status partition",
+ "value": "0x3c00"
+ }
+ },
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x18000000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x40200"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18080000"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x40200"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h b/boot/cypress/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h
similarity index 88%
rename from boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h
rename to boot/cypress/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h
index fe1150d..219f3c9 100644
--- a/boot/cypress/cy_flash_pal/include/cy_smif_psoc6.h
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h
@@ -48,17 +48,19 @@
#ifndef CY_SMIF_PSOC6_H_
#define CY_SMIF_PSOC6_H_
+#ifndef CYW20829
+
#include "stddef.h"
#include "stdbool.h"
#include "flash_qspi.h"
-#ifndef off_t
-typedef long int off_t;
-#endif
+typedef unsigned long offset_t;
-int psoc6_smif_read(const struct flash_area *fap, off_t addr, void *data, size_t len);
-int psoc6_smif_write(const struct flash_area *fap, off_t addr, const void *data, size_t len);
-int psoc6_smif_erase(off_t addr, size_t size);
+int psoc6_smif_read(const struct flash_area *fap, offset_t addr, void *data, size_t len);
+int psoc6_smif_write(const struct flash_area *fap, offset_t addr, const void *data, size_t len);
+int psoc6_smif_erase(offset_t addr, size_t size);
#endif /* CY_SMIF_PSOC6_H_ */
+
+#endif /* CYW20829 */
diff --git a/boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h b/boot/cypress/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h
similarity index 88%
rename from boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h
rename to boot/cypress/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h
index 4b9409b..194f798 100644
--- a/boot/cypress/cy_flash_pal/include/flash_map_backend/flash_map_backend.h
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h
@@ -39,7 +39,7 @@
#ifndef CY_BOOT_EXTERNAL_DEVICE_INDEX
/* assume first(one) SMIF device is used */
-#define CY_BOOT_EXTERNAL_DEVICE_INDEX (0)
+#define CY_BOOT_EXTERNAL_DEVICE_INDEX (0u)
#endif
/**
@@ -93,6 +93,26 @@
uint32_t fa_size;
};
+static inline uint8_t flash_area_get_id(const struct flash_area *fa)
+{
+ return fa->fa_id;
+}
+
+static inline uint8_t flash_area_get_device_id(const struct flash_area *fa)
+{
+ return fa->fa_device_id;
+}
+
+static inline uint32_t flash_area_get_off(const struct flash_area *fa)
+{
+ return fa->fa_off;
+}
+
+static inline uint32_t flash_area_get_size(const struct flash_area *fa)
+{
+ return fa->fa_size;
+}
+
/**
* @brief Structure describing a sector within a flash area.
*
@@ -112,6 +132,16 @@
uint32_t fs_size;
};
+static inline uint32_t flash_sector_get_off(const struct flash_sector *fs)
+{
+ return fs->fs_off;
+}
+
+static inline uint32_t flash_sector_get_size(const struct flash_sector *fs)
+{
+ return fs->fs_size;
+}
+
struct flash_map_entry {
uint32_t magic;
struct flash_area area;
@@ -128,7 +158,7 @@
/*< Opens the area for use. id is one of the `fa_id`s */
int flash_area_open(uint8_t id, const struct flash_area **fa);
-void flash_area_close(const struct flash_area *);
+void flash_area_close(const struct flash_area *fa);
/*< Reads `len` bytes of flash memory at `off` to the buffer at `dst` */
int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
uint32_t len);
@@ -137,8 +167,6 @@
const void *src, uint32_t len);
/*< Erases `len` bytes of flash memory at `off` */
int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len);
-/*< Erases aligned row of flash, where passed address resided */
-int flash_erase_row(uint32_t address);
/*< Returns this `flash_area`s alignment */
size_t flash_area_align(const struct flash_area *fa);
/*< Initializes an array of flash_area elements for the slot's sectors */
@@ -159,12 +187,4 @@
*/
uint8_t flash_area_erased_val(const struct flash_area *fa);
-/*
- * Reads len bytes from off, and checks if the read data is erased.
- *
- * Returns 1 if erased, 0 if non-erased, and -1 on failure.
- */
-int flash_area_read_is_empty(const struct flash_area *fa, uint32_t off,
- void *dst, uint32_t len);
-
#endif /* FLASH_MAP_BACKEND_H */
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c b/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
new file mode 100644
index 0000000..bcf6841
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
@@ -0,0 +1,474 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 3.0.0.5613
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+const cy_stc_smif_mem_cmd_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0_readCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0xECU,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_QUAD,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0x01U,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_QUAD,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 4U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_QUAD,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_PRESENT_1BYTE,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_cmd_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0_writeEnCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x06U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_cmd_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0_writeDisCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x04U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_cmd_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0_eraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0xDCU,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_cmd_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0_chipEraseCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x60U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_cmd_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0_programCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x34U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_QUAD,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_QUAD,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_cmd_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x35U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_cmd_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x05U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_cmd_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+{
+ /* The 8-bit command. 1 x I/O read command. */
+ .command = 0x01U,
+ /* The width of the command transfer. */
+ .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The width of the address transfer. */
+ .addrWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+ .mode = 0xFFFFFFFFU,
+ /* The width of the mode command transfer. */
+ .modeWidth = CY_SMIF_WIDTH_SINGLE,
+ /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+ .dummyCycles = 0U,
+ /* The width of the data transfer. */
+ .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /* The Data rate of data */
+ .dataRate = CY_SMIF_SDR,
+ /* This specifies the presence of the dummy field */
+ .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+ /* This specifies the presence of the mode field */
+ .modePresence = CY_SMIF_NOT_PRESENT,
+ /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+ .modeH = 0x00,
+ /* The Data rate of mode */
+ .modeRate = CY_SMIF_SDR,
+ /* The Data rate of address */
+ .addrRate = CY_SMIF_SDR,
+ /* This specifies the width of the command field */
+ .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+ /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+ .commandH = 0x00,
+ /* The Data rate of command */
+ .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_device_cfg_t __attribute__((section (".smif_struct")))
+deviceCfg_S25FL512S_SlaveSlot_0 =
+{
+ /* Specifies the number of address bytes used by the memory slave device. */
+ .numOfAddrBytes = 0x04U,
+ /* The size of the memory. */
+ .memSize = 0x04000000U,
+ /* Specifies the Read command. */
+ .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
+ /* Specifies the Write Enable command. */
+ .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
+ /* Specifies the Write Disable command. */
+ .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
+ /* Specifies the Erase command. */
+ .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
+ /* Specifies the sector size of each erase. */
+ .eraseSize = 0x00040000U,
+ /* Specifies the Chip Erase command. */
+ .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
+ /* Specifies the Program command. */
+ .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
+ /* Specifies the page size for programming. */
+ .programSize = 0x00000200U,
+ /* Specifies the command to read the QE-containing status register. */
+ .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+ /* Specifies the command to read the WIP-containing status register. */
+ .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+ /* Specifies the command to write into the QE-containing status register. */
+ .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+ /* The mask for the status register. */
+ .stsRegBusyMask = 0x01U,
+ /* The mask for the status register. */
+ .stsRegQuadEnableMask = 0x02U,
+ /* The max time for the erase type-1 cycle-time in ms. */
+ .eraseTime = 2600U,
+ /* The max time for the chip-erase cycle-time in ms. */
+ .chipEraseTime = 460000U,
+ /* The max time for the page-program cycle-time in us. */
+ .programTime = 1300U,
+#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
+ /* Points to NULL or to structure with info about sectors for hybrid memory. */
+ .hybridRegionCount = 0U,
+ .hybridRegionInfo = NULL
+#endif
+};
+
+const cy_stc_smif_mem_config_t __attribute__((section (".smif_struct")))
+S25FL512S_SlaveSlot_0 =
+{
+ /* Determines the slot number where the memory device is placed. */
+ .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+ /* Flags. */
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ .flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
+#else
+ .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
+#endif /* CY_IP_MXSMIF_VERSION */
+ /* The data-line selection options for a slave device. */
+ .dataSelect = CY_SMIF_DATA_SEL0,
+ /* The base address the memory slave is mapped to in the PSoC memory map.
+ Valid when the memory-mapped mode is enabled. */
+ .baseAddress = 0x18000000U,
+ /* The size allocated in the PSoC memory map, for the memory slave device.
+ The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+ .memMappedSize = 0x400000U,
+ /* If this memory device is one of the devices in the dual quad SPI configuration.
+ Valid when the memory mapped mode is enabled. */
+ .dualQuadSlots = 0,
+ /* The configuration of the device. */
+ .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0,
+#if (CY_IP_MXSMIF_VERSION >= 3)
+ /** Continous transfer merge timeout.
+ * After this period the memory device is deselected. A later transfer, even from a
+ * continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
+ * This configuration parameter is available for CAT1B devices. */
+ .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_config_t* const __attribute__((section (".smif_struct")))
+smifMemConfigs[CY_SMIF_DEVICE_NUM] = {
+ &S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t __attribute__((section (".smif_struct")))
+smifBlockConfig =
+{
+ /* The number of SMIF memories defined. */
+ .memCount = CY_SMIF_DEVICE_NUM,
+ /* The pointer to the array of memory config structures of size memCount. */
+ .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+ /* The version of the SMIF driver. */
+ .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+ /* The version of the SMIF driver. */
+ .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.h b/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.h
new file mode 100644
index 0000000..884be8f
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.h
@@ -0,0 +1,65 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 3.0.0.5613
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_CFG_TOOL_VERSION (300)
+
+/* Supported QSPI Driver version */
+#define CY_SMIF_DRV_VERSION_REQUIRED (100)
+
+#if !defined(CY_SMIF_DRV_VERSION)
+ #define CY_SMIF_DRV_VERSION (100)
+#endif
+
+/* Check the used Driver version */
+#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION)
+ #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
+#endif
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CYCFG_QSPI_MEMSLOT_H*/
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/qspi_config.cfg b/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/qspi_config.cfg
new file mode 100644
index 0000000..96ff76a
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/qspi_config.cfg
@@ -0,0 +1,28 @@
+################################################################################
+# File Name: qspi_config.cfg
+#
+# Description:
+# This file contains a SMIF Bank layout for use with OpenOCD.
+# This file was automatically generated and should not be modified.
+# QSPI Configurator: 3.0.0.5613
+#
+################################################################################
+# Copyright 2022 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+set SMIF_BANKS {
+ 0 {addr 0x18000000 size 0x400000 psize 0x00000200 esize 0x00040000}
+}
diff --git a/boot/cypress/cy_flash_pal/sysflash/sysflash.h b/boot/cypress/cy_flash_pal/sysflash/sysflash.h
new file mode 100644
index 0000000..dfe015f
--- /dev/null
+++ b/boot/cypress/cy_flash_pal/sysflash/sysflash.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2022 Infineon Technologies AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef SYSFLASH_H
+#define SYSFLASH_H
+
+#include <stdint.h>
+#include "cy_syslib.h"
+
+#ifndef MCUBOOT_IMAGE_NUMBER
+#ifdef MCUBootApp
+#warning Undefined MCUBOOT_IMAGE_NUMBER. Assuming 1 (single-image).
+#endif /* MCUBootApp */
+#define MCUBOOT_IMAGE_NUMBER 1
+#endif /* MCUBOOT_IMAGE_NUMBER */
+
+#if (MCUBOOT_IMAGE_NUMBER < 1 || MCUBOOT_IMAGE_NUMBER > 4)
+#error Unsupported MCUBOOT_IMAGE_NUMBER. Set it to between 1 and 4.
+#endif /* (MCUBOOT_IMAGE_NUMBER < 1 || MCUBOOT_IMAGE_NUMBER > 4) */
+
+#define FLASH_AREA_BOOTLOADER ( 0u)
+
+#define FLASH_AREA_IMG_1_PRIMARY ( 1u)
+#define FLASH_AREA_IMG_1_SECONDARY ( 2u)
+
+#define FLASH_AREA_IMAGE_SCRATCH ( 3u)
+
+#if MCUBOOT_IMAGE_NUMBER >= 2
+#define FLASH_AREA_IMG_2_PRIMARY ( 4u)
+#define FLASH_AREA_IMG_2_SECONDARY ( 5u)
+#endif /* MCUBOOT_IMAGE_NUMBER >= 2 */
+
+#define FLASH_AREA_IMAGE_SWAP_STATUS ( 7u)
+
+#if MCUBOOT_IMAGE_NUMBER >= 3
+#define FLASH_AREA_IMG_3_PRIMARY ( 8u)
+#define FLASH_AREA_IMG_3_SECONDARY ( 9u)
+#endif /* MCUBOOT_IMAGE_NUMBER >= 3 */
+
+#if MCUBOOT_IMAGE_NUMBER == 4
+#define FLASH_AREA_IMG_4_PRIMARY (10u)
+#define FLASH_AREA_IMG_4_SECONDARY (11u)
+#endif /* MCUBOOT_IMAGE_NUMBER == 4 */
+
+#define FLASH_AREA_ERROR 255u /* Invalid flash area */
+
+#ifdef PSOC6
+#define CY_SMIF_BASE_MEM_OFFSET 0x18000000u
+#endif /* PSOC6 */
+
+/* This defines if External Flash (SMIF) will be used for Upgrade Slots */
+#ifdef CYW20829
+#define CY_FLASH_BASE CY_XIP_BASE
+#define CY_SMIF_BASE_MEM_OFFSET CY_FLASH_BASE
+#define CY_FLASH_SIZEOF_ROW 4096u
+#endif /* CYW20829 */
+
+/* use PDL-defined offset or one from SMIF config */
+#define CY_SMIF_BASE (CY_XIP_BASE)
+
+#define CY_FLASH_ALIGN (CY_FLASH_SIZEOF_ROW)
+#define CY_FLASH_DEVICE_BASE (CY_FLASH_BASE)
+
+#define CY_IMG_HDR_SIZE 0x400
+#define BOOT_MAX_SWAP_STATUS_SECTORS (64)
+
+__STATIC_INLINE uint8_t FLASH_AREA_IMAGE_PRIMARY(uint32_t img_idx)
+{
+ uint8_t result = FLASH_AREA_ERROR;
+
+ if (img_idx < (uint32_t)MCUBOOT_IMAGE_NUMBER) {
+ static const uint8_t areas[] = {
+ FLASH_AREA_IMG_1_PRIMARY,
+#if MCUBOOT_IMAGE_NUMBER >= 2
+ FLASH_AREA_IMG_2_PRIMARY,
+#endif /* MCUBOOT_IMAGE_NUMBER >= 2 */
+#if MCUBOOT_IMAGE_NUMBER >= 3
+ FLASH_AREA_IMG_3_PRIMARY,
+#endif /* MCUBOOT_IMAGE_NUMBER >= 3 */
+#if MCUBOOT_IMAGE_NUMBER == 4
+ FLASH_AREA_IMG_4_PRIMARY
+#endif /* MCUBOOT_IMAGE_NUMBER == 4 */
+ };
+
+ result = areas[img_idx];
+ }
+
+ return result;
+}
+
+__STATIC_INLINE uint8_t FLASH_AREA_IMAGE_SECONDARY(uint32_t img_idx)
+{
+ uint8_t result = FLASH_AREA_ERROR;
+
+ if (img_idx < (uint32_t)MCUBOOT_IMAGE_NUMBER) {
+ static const uint8_t areas[] = {
+ FLASH_AREA_IMG_1_SECONDARY,
+#if MCUBOOT_IMAGE_NUMBER >= 2
+ FLASH_AREA_IMG_2_SECONDARY,
+#endif /* MCUBOOT_IMAGE_NUMBER >= 2 */
+#if MCUBOOT_IMAGE_NUMBER >= 3
+ FLASH_AREA_IMG_3_SECONDARY,
+#endif /* MCUBOOT_IMAGE_NUMBER >= 3 */
+#if MCUBOOT_IMAGE_NUMBER == 4
+ FLASH_AREA_IMG_4_SECONDARY
+#endif /* MCUBOOT_IMAGE_NUMBER == 4 */
+ };
+
+ result = areas[img_idx];
+ }
+
+ return result;
+}
+
+#endif /* SYSFLASH_H */
diff --git a/boot/cypress/host.mk b/boot/cypress/host.mk
index 6b6851e..a1f6ef8 100644
--- a/boot/cypress/host.mk
+++ b/boot/cypress/host.mk
@@ -46,3 +46,12 @@
endif
PRJ_DIR=$(call get_os_path, $(CURDIR))
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### host.mk ####)
+$(info CURDIR <-- $(CURDIR))
+$(info HOST_OS <-- $(HOST_OS))
+$(info UNAME_S <-> $(UNAME_S))
+endif
diff --git a/boot/cypress/libs/core-lib b/boot/cypress/libs/core-lib
index a0f53cd..7e6892e 160000
--- a/boot/cypress/libs/core-lib
+++ b/boot/cypress/libs/core-lib
@@ -1 +1 @@
-Subproject commit a0f53cdda39a373c45cdbf9f853c8018c1172461
+Subproject commit 7e6892ee1eeabc8f6c25fbf02cb00ff43bd3ac73
diff --git a/boot/cypress/libs/mtb-hal-cat1 b/boot/cypress/libs/mtb-hal-cat1
new file mode 160000
index 0000000..708a6b2
--- /dev/null
+++ b/boot/cypress/libs/mtb-hal-cat1
@@ -0,0 +1 @@
+Subproject commit 708a6b2542f0d8814c129a3141e78fd265826a0b
diff --git a/boot/cypress/libs/mtb-pdl-cat1 b/boot/cypress/libs/mtb-pdl-cat1
index 55b5a54..3c6aebd 160000
--- a/boot/cypress/libs/mtb-pdl-cat1
+++ b/boot/cypress/libs/mtb-pdl-cat1
@@ -1 +1 @@
-Subproject commit 55b5a5457195ad2a2a02e0a98ca72a9333e26397
+Subproject commit 3c6aebd2f3238b578329bfb8a6c5a0e138bd5c7b
diff --git a/boot/cypress/libs/pdl/psoc6pdl b/boot/cypress/libs/pdl/psoc6pdl
deleted file mode 160000
index 0e38b78..0000000
--- a/boot/cypress/libs/pdl/psoc6pdl
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0e38b78ef9ae3ce5db0563bdcde80a028c5fc38a
diff --git a/boot/cypress/libs/psoc6hal b/boot/cypress/libs/psoc6hal
deleted file mode 160000
index a0d6c08..0000000
--- a/boot/cypress/libs/psoc6hal
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit a0d6c08f1178750e29967999860485878fac09f9
diff --git a/boot/cypress/libs/retarget-io b/boot/cypress/libs/retarget-io
index bd88e66..a61cd7c 160000
--- a/boot/cypress/libs/retarget-io
+++ b/boot/cypress/libs/retarget-io
@@ -1 +1 @@
-Subproject commit bd88e66fc6976de49694382a5ce5dc7613f12ace
+Subproject commit a61cd7c5f4b2808c949248f05287c09e6578abfc
diff --git a/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c b/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c
index 0472f3e..2c02df8 100644
--- a/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c
+++ b/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c
@@ -36,15 +36,33 @@
/* Tracks the previous character sent to output stream */
#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-static char cy_retarget_io_stdout_prev_char = 0;
+static char cy_retarget_io_stdout_prev_char = '\0';
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
-cy_stc_scb_uart_context_t CYBSP_UART_context;
+static cy_stc_scb_uart_context_t CYBSP_UART_context;
static uint8_t cy_retarget_io_getchar(void);
static void cy_retarget_io_putchar(char c);
#if defined(__ARMCC_VERSION) /* ARM-MDK */
+
+int fputc(int ch, FILE *f);
+int fgetc(FILE *f);
+
+#elif defined (__ICCARM__) /* IAR */
+
+size_t __write(int handle, const unsigned char * buffer, size_t size);
+size_t __read(int handle, unsigned char * buffer, size_t size);
+
+#else /* (__GNUC__) GCC */
+
+int _write(int fd, const char *ptr, int len);
+int _read(int fd, char *ptr, int len);
+
+#endif /* defined(__ARMCC_VERSION) */
+
+
+#if defined(__ARMCC_VERSION) /* ARM-MDK */
/***************************************************************************
* Function Name: fputc
***************************************************************************/
@@ -96,13 +114,10 @@
return (nChars);
}
#else /* (__GNUC__) GCC */
- /* Add an explicit reference to the floating point printf library to allow
- the usage of floating point conversion specifier. */
- __asm (".global _printf_float");
/***************************************************************************
* Function Name: _write
***************************************************************************/
- __attribute__((weak)) int _write (int fd, const char *ptr, int len)
+ __attribute__((weak)) int _write(int fd, const char *ptr, int len)
{
int nChars = 0;
(void)fd;
@@ -118,13 +133,13 @@
cy_retarget_io_stdout_prev_char = *ptr;
#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
- cy_retarget_io_putchar((uint32_t)*ptr);
+ cy_retarget_io_putchar(*ptr);
++ptr;
}
}
return (nChars);
}
-#endif
+#endif /* defined(__ARMCC_VERSION) */
#if defined(__ARMCC_VERSION) /* ARM-MDK */
@@ -152,16 +167,13 @@
}
}
#else /* (__GNUC__) GCC */
- /* Add an explicit reference to the floating point scanf library to allow
- the usage of floating point conversion specifier. */
- __asm (".global _scanf_float");
- __attribute__((weak)) int _read (int fd, char *ptr, int len)
+ __attribute__((weak)) int _read(int fd, char *ptr, int len)
{
int nChars = 0;
(void)fd;
if (ptr != NULL)
{
- for(/* Empty */;nChars < len;++ptr)
+ while (nChars < len)
{
*ptr = (char)cy_retarget_io_getchar();
++nChars;
@@ -169,11 +181,12 @@
{
break;
}
+ ++ptr;
}
}
return (nChars);
}
-#endif
+#endif /* defined(__ARMCC_VERSION) */
static uint8_t cy_retarget_io_getchar(void)
{
@@ -188,10 +201,10 @@
static void cy_retarget_io_putchar(char c)
{
- uint32_t count = 0;
- while (count == 0)
+ uint32_t count = 0U;
+ while (count == 0U)
{
- count = Cy_SCB_UART_Put(CYBSP_UART_HW, c);
+ count = Cy_SCB_UART_Put(CYBSP_UART_HW, (uint8_t)c);
}
}
@@ -199,24 +212,24 @@
{
cy_rslt_t result = CY_RSLT_TYPE_ERROR;
- uint8_t oversample_value = 8u;
- uint8_t frac_bits = 0u;
+ uint8_t oversample_value = 8U;
+ uint8_t frac_bits = 0U;
uint32_t divider;
Cy_SCB_UART_Disable(base, NULL);
result = (cy_rslt_t) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0);
- divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + ((baudrate * oversample_value) / 2)) / (baudrate * oversample_value) - 1;
+ divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1UL << frac_bits)) + ((baudrate * oversample_value) / 2U)) / (baudrate * oversample_value) - 1U;
if (result == CY_RSLT_SUCCESS)
{
- result = (cy_rslt_t) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, divider);
+ result = (cy_rslt_t) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, divider);
}
if (result == CY_RSLT_SUCCESS)
{
- result = Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
+ result = Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
}
Cy_SCB_UART_Enable(base);
@@ -249,18 +262,18 @@
*/
void cy_retarget_io_wait_tx_complete(CySCB_Type *base, uint32_t tries_count)
{
- while(tries_count > 0)
+ while(tries_count > 0U)
{
if (!Cy_SCB_UART_IsTxComplete(base)) {
- Cy_SysLib_DelayCycles(10 * cy_delayFreqKhz);
- tries_count -= 1;
+ Cy_SysLib_DelayCycles(10U * cy_delayFreqKhz);
+ tries_count -= 1U;
} else {
return;
}
}
}
-void cy_retarget_io_pdl_deinit()
+void cy_retarget_io_pdl_deinit(void)
{
Cy_SCB_UART_DeInit(CYBSP_UART_HW);
}
diff --git a/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.h b/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.h
index f0c8733..4ebfdef 100644
--- a/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.h
+++ b/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.h
@@ -29,6 +29,8 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
+#ifndef CY_RETARGET_IO_PDL_H
+#define CY_RETARGET_IO_PDL_H
#pragma once
@@ -60,3 +62,4 @@
}
#endif
+#endif /* CY_RETARGET_IO_PDL_H */
diff --git a/boot/cypress/libs/watchdog/watchdog.c b/boot/cypress/libs/watchdog/watchdog.c
index 286e9c3..96200ab 100644
--- a/boot/cypress/libs/watchdog/watchdog.c
+++ b/boot/cypress/libs/watchdog/watchdog.c
@@ -28,6 +28,7 @@
#include <stdbool.h>
#include "watchdog.h"
+#include "cy_sysclk.h"
#include "cy_wdt.h"
#include "cy_utils.h"
@@ -36,31 +37,31 @@
#endif
#if defined(COMPONENT_PSOC6)
-#define _cy_wdg_lock() Cy_WDT_Lock()
-#define _cy_wdg_unlock() Cy_WDT_Unlock()
+#define cy_wdg_lock() Cy_WDT_Lock()
+#define cy_wdg_unlock() Cy_WDT_Unlock()
#else
-#define _cy_wdg_lock()
-#define _cy_wdg_unlock()
+#define cy_wdg_lock()
+#define cy_wdg_unlock()
#endif
// ((2^16 * 2) + (2^16 - 1)) * .030518 ms
/** Maximum WDT timeout in milliseconds */
-#define _cy_wdg_MAX_TIMEOUT_MS 6000
+#define cy_wdg_MAX_TIMEOUT_MS 6000U
/** Maximum number of ignore bits */
-#define _cy_wdg_MAX_IGNORE_BITS 12
+#define cy_wdg_MAX_IGNORE_BITS 12U
typedef struct {
uint16_t min_period_ms; // Minimum period in milliseconds that can be represented with this many ignored bits
uint16_t round_threshold_ms; // Timeout threshold in milliseconds from which to round up to the minimum period
-} _cy_wdg_ignore_bits_data_t;
+} cy_wdg_ignore_bits_data_t;
// ILO Frequency = 32768 Hz
// ILO Period = 1 / 32768 Hz = .030518 ms
// WDT Reset Period (timeout_ms) = .030518 ms * (2 * 2^(16 - ignore_bits) + match)
// ignore_bits range: 0 - 12
// match range: 0 - (2^(16 - ignore_bits) - 1)
-static const _cy_wdg_ignore_bits_data_t _cy_wdg_ignore_data[] = {
+static const cy_wdg_ignore_bits_data_t cy_wdg_ignore_data[] = {
{4001, 3001}, // 0 bits: min period: 4001ms, max period: 6000ms, round up from 3001+ms
{2001, 1500}, // 1 bit: min period: 2001ms, max period: 3000ms, round up from 1500+ms
{1001, 750}, // 2 bits: min period: 1001ms, max period: 1499ms, round up from 750+ms
@@ -76,106 +77,103 @@
{1, 1} // 12 bits: min period: 1ms, max period: 1ms
};
-static bool _cy_wdg_initialized = false;
-static bool _cy_wdg_pdl_initialized = false;
-static uint16_t _cy_wdg_initial_timeout_ms = 0;
-static uint8_t _cy_wdg_initial_ignore_bits = 0;
+static bool cy_wdg_initialized = false;
+static bool cy_wdg_pdl_initialized = false;
+static uint16_t cy_wdg_initial_timeout_ms = 0;
+static uint8_t cy_wdg_initial_ignore_bits = 0;
-static __INLINE uint32_t _cy_wdg_timeout_to_ignore_bits(uint32_t *timeout_ms) {
- for (uint32_t i = 0; i <= _cy_wdg_MAX_IGNORE_BITS; i++)
- {
- if (*timeout_ms >= _cy_wdg_ignore_data[i].round_threshold_ms)
- {
- if (*timeout_ms < _cy_wdg_ignore_data[i].min_period_ms)
- *timeout_ms = _cy_wdg_ignore_data[i].min_period_ms;
+static __INLINE uint8_t cy_wdg_timeout_to_ignore_bits(uint16_t *timeout_ms)
+{
+ for (uint8_t i = 0; i <= cy_wdg_MAX_IGNORE_BITS; i++) {
+ if (*timeout_ms >= cy_wdg_ignore_data[i].round_threshold_ms) {
+ if (*timeout_ms < cy_wdg_ignore_data[i].min_period_ms) {
+ *timeout_ms = cy_wdg_ignore_data[i].min_period_ms;
+ }
return i;
}
}
- return _cy_wdg_MAX_IGNORE_BITS; // Should never reach this
+ return cy_wdg_MAX_IGNORE_BITS; // Should never reach this
}
-static __INLINE uint16_t _cy_wdg_timeout_to_match(uint16_t timeout_ms, uint16_t ignore_bits)
+static __INLINE uint16_t cy_wdg_timeout_to_match(uint16_t timeout_ms, uint16_t ignore_bits)
{
- // match = (timeout_ms / .030518 ms) - (2 * 2^(16 - ignore_bits))
- return (uint16_t)(timeout_ms / .030518) - (1UL << (17 - ignore_bits)) + Cy_WDT_GetCount();
+ uint32_t timeout = (uint32_t)timeout_ms * CY_SYSCLK_ILO_FREQ / 1000U;
+ return (uint16_t)(timeout - (1UL << (17U - ignore_bits)) + Cy_WDT_GetCount());
}
/* Start API implementing */
-cy_rslt_t cy_wdg_init(uint32_t timeout_ms)
+cy_rslt_t cy_wdg_init(uint16_t timeout_ms)
{
- if (timeout_ms == 0 || timeout_ms > _cy_wdg_MAX_TIMEOUT_MS)
- {
- return -1;
+ if (timeout_ms == 0U || timeout_ms > cy_wdg_MAX_TIMEOUT_MS) {
+ return ~CY_RSLT_SUCCESS;
}
- if (_cy_wdg_initialized)
- {
- return -1;
+ if (cy_wdg_initialized) {
+ return ~CY_RSLT_SUCCESS;
}
- _cy_wdg_initialized = true;
+ cy_wdg_initialized = true;
- if (!_cy_wdg_pdl_initialized)
- {
+ if (!cy_wdg_pdl_initialized) {
Cy_WDT_Enable();
Cy_WDT_MaskInterrupt();
- _cy_wdg_pdl_initialized = true;
+ cy_wdg_pdl_initialized = true;
}
cy_wdg_stop();
- _cy_wdg_initial_timeout_ms = timeout_ms;
- uint8_t ignore_bits = _cy_wdg_timeout_to_ignore_bits(&timeout_ms);
- _cy_wdg_initial_ignore_bits = ignore_bits;
+ cy_wdg_initial_timeout_ms = timeout_ms;
+ uint8_t ignore_bits = cy_wdg_timeout_to_ignore_bits(&timeout_ms);
+ cy_wdg_initial_ignore_bits = ignore_bits;
Cy_WDT_SetIgnoreBits(ignore_bits);
- Cy_WDT_SetMatch(_cy_wdg_timeout_to_match(timeout_ms, ignore_bits));
+ Cy_WDT_SetMatch(cy_wdg_timeout_to_match(timeout_ms, ignore_bits));
cy_wdg_start();
return CY_RSLT_SUCCESS;
}
-void cy_wdg_free()
+void cy_wdg_free(void)
{
cy_wdg_stop();
- _cy_wdg_initialized = false;
+ cy_wdg_initialized = false;
}
-void cy_wdg_kick()
+void cy_wdg_kick(void)
{
/* Clear to prevent reset from WDT */
Cy_WDT_ClearWatchdog();
- _cy_wdg_unlock();
- Cy_WDT_SetMatch(_cy_wdg_timeout_to_match(_cy_wdg_initial_timeout_ms, _cy_wdg_initial_ignore_bits));
- _cy_wdg_lock();
+ cy_wdg_unlock();
+ Cy_WDT_SetMatch(cy_wdg_timeout_to_match(cy_wdg_initial_timeout_ms, cy_wdg_initial_ignore_bits));
+ cy_wdg_lock();
}
-void cy_wdg_start()
+void cy_wdg_start(void)
{
- _cy_wdg_unlock();
+ cy_wdg_unlock();
Cy_WDT_Enable();
- _cy_wdg_lock();
+ cy_wdg_lock();
}
-void cy_wdg_stop()
+void cy_wdg_stop(void)
{
- _cy_wdg_unlock();
+ cy_wdg_unlock();
Cy_WDT_Disable();
}
-uint32_t cy_wdg_get_timeout_ms()
+uint32_t cy_wdg_get_timeout_ms(void)
{
- return _cy_wdg_initial_timeout_ms;
+ return cy_wdg_initial_timeout_ms;
}
uint32_t cy_wdg_get_max_timeout_ms(void)
{
- return _cy_wdg_MAX_TIMEOUT_MS;
+ return cy_wdg_MAX_TIMEOUT_MS;
}
#if defined(__cplusplus)
diff --git a/boot/cypress/libs/watchdog/watchdog.h b/boot/cypress/libs/watchdog/watchdog.h
index 0d45f82..494326a 100644
--- a/boot/cypress/libs/watchdog/watchdog.h
+++ b/boot/cypress/libs/watchdog/watchdog.h
@@ -1,3 +1,5 @@
+#ifndef WATCHDOG_H
+#define WATCHDOG_H
/***************************************************************************//**
* \file cy_wdg.h
*
@@ -43,7 +45,7 @@
*
* Returns CY_RSLT_SUCCESS if the operation was successfull.
*/
-cy_rslt_t cy_wdg_init(uint32_t timeout_ms);
+cy_rslt_t cy_wdg_init(uint16_t timeout_ms);
/** Free the WDT
*
@@ -52,32 +54,32 @@
* cy_wdg_init().
*/
-void cy_wdg_free();
+void cy_wdg_free(void);
/** Resets the WDT
*
* This function should be called periodically to prevent the WDT from timing out and resetting the device.
*/
-void cy_wdg_kick();
+void cy_wdg_kick(void);
/** Start (enable) the WDT
*
* @return The status of the start request
*/
-void cy_wdg_start();
+void cy_wdg_start(void);
/** Stop (disable) the WDT
*
* @return The status of the stop request
*/
-void cy_wdg_stop();
+void cy_wdg_stop(void);
/** Get the WDT timeout
*
* Gets the time in milliseconds before the WDT times out.
* @return The time in milliseconds before the WDT times out
*/
-uint32_t cy_wdg_get_timeout_ms();
+uint32_t cy_wdg_get_timeout_ms(void);
/** Gets the maximum WDT timeout in milliseconds
*
@@ -88,3 +90,5 @@
#if defined(__cplusplus)
}
#endif
+
+#endif /* WATCHDOG_H */
diff --git a/boot/cypress/platforms.mk b/boot/cypress/platforms.mk
index 39fd34a..281c34c 100644
--- a/boot/cypress/platforms.mk
+++ b/boot/cypress/platforms.mk
@@ -25,54 +25,39 @@
include host.mk
-# Target platform is built for. PSOC_062_2M is set by default
-# Supported:
-# - PSOC_062_2M
-# - PSOC_062_1M
-# - PSOC_062_512K
-
-# default PLATFORM
-PLATFORM ?= PSOC_062_2M
-
# supported platforms
-PLATFORMS := PSOC_062_2M PSOC_062_1M PSOC_062_512K
+PLATFORMS := PSOC_062_2M PSOC_062_1M PSOC_062_512K CYW20829
ifneq ($(filter $(PLATFORM), $(PLATFORMS)),)
else
$(error Not supported platform: '$(PLATFORM)')
endif
-# For which core this application is built
-CORE ?= CM0P
-
-# MCU device selection, based on target device.
-# Default chips are used for supported platforms
-# This can be redefined in case of other chip usage
-ifeq ($(PLATFORM), PSOC_062_2M)
-# base kit CY8CPROTO-062-4343W
-DEVICE ?= CY8C624ABZI-D44
-PLATFORM_SUFFIX := 02
-else ifeq ($(PLATFORM), PSOC_062_1M)
-# base kit CY8CKIT-062-WIFI-BT
-DEVICE ?= CY8C6247BZI-D54
-PLATFORM_SUFFIX := 01
-else ifeq ($(PLATFORM), PSOC_062_512K)
-# base kit CY8CPROTO-062S3-4343W
-DEVICE ?= CY8C6245LQI-S3D72
-PLATFORM_SUFFIX := 03
+ifeq ($(PLATFORM), $(filter $(PLATFORM), PSOC_062_2M PSOC_062_1M PSOC_062_512K))
+FAMILY := PSOC6
+else ifeq ($(PLATFORM), CYW20829)
+FAMILY := CYW20829
endif
-# Add device name to defines
-DEFINES += $(DEVICE)
+# include family related makefile into build
+include platforms/$(FAMILY)/$(FAMILY).mk
+
DEFINES += $(PLATFORM)
+DEFINES += $(FAMILY)
# Convert defines to regular -DMY_NAME style
ifneq ($(DEFINES),)
- DEFINES_PLATFORM :=$(addprefix -D, $(subst -,_,$(DEFINES)))
+ PLATFORM_DEFINES := $(addprefix -D, $(subst -,_,$(DEFINES)))
endif
-ifeq ($(MAKEINFO) , 1)
-$(info $(PLATFORM_SUFFIX))
-$(info $(DEVICE))
-$(info $(DEFINES_PLATFORM))
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### platforms.mk ####)
+$(info DEFINES <-> $(DEFINES))
+$(info FAMILY <-> $(FAMILY))
+$(info PLATFORM <-- $(PLATFORM))
+$(info PLATFORMS <-> $(PLATFORMS))
+$(info PLATFORM_DEFINES <-> $(PLATFORM_DEFINES))
+$(info PLATFORM_SUFFIX <-- $(PLATFORM_SUFFIX))
endif
diff --git a/boot/cypress/platforms/CYW20829/CYW20829.md b/boot/cypress/platforms/CYW20829/CYW20829.md
new file mode 100644
index 0000000..4d591c6
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/CYW20829.md
@@ -0,0 +1,198 @@
+## CYW20829 platform description
+
+### Prerequisites
+
+#### Cysecuretools
+
+The CYW20829 chip has a set of security features. The special tool called `cysecuretools` is required to use most of them.
+
+Cysecuretools is a Python3 package, which can be installed using the conventional `python pip` packet manager:
+
+ python -m pip install cysecuretools
+
+Cysecuretools is used for reprovisioning of the chip, revocation of keys, security counter updates, image encryption and more. For more details on functionality, go to https://pypi.org/project/cysecuretools/
+
+Invocation of cysecuretools is build-in post build jobs for `MCUBootApp` and `BlinkyApp`, so the user gets ready to use images after build.
+
+### MCUBootApp specifics
+
+### Default memory map
+
+This repository provides a set of predefined memory maps in JSON files. They are located in `cy_flash_pal/flash_%platform_name%/flashmap`. One can use the predefined flash map or define its own using the predefined file as a template.
+
+### Encrypted image support
+
+CYW20829 does not have internal flash memory, so both primary and secondary images are located in external memory.
+
+To protect the firmware from read, place it in external memory in the encrypted form.
+
+CYW20829 can execute encrypted firmware directly using the onboard hardware interface (SMIF) with special mode XIP (eXecute-In-Place). In this mode all code is decrypted transparently by AES algorithm.
+
+MCUboot has its own Encrypted image mode to encrypt the firmware and transfer it with the AES session key included in the HKDF data block.
+
+**MCUboot image validation flow**
+
+- Decrypt the AES key / initial vector (IV) from HKDF
+- Set up AES IV + CTR nonce (Image addr = base_addr + header_size)
+- Read slot data by MMIO
+- Decrypt the image in the slot using MCUboot internal functionality
+- Calculate and verify hash from decrypted data
+- Validate the slot image by hash and sign it
+
+**MCUboot image upgrade flow**
+
+- Read slot 1 sector data using MMIO
+- Skip data decryption
+- Write data to the primary slot using MMIO
+
+**MCUboot Application Run**
+- Set up SMIF registers
+- Set the AES key
+- Set AES IV
+- Set SMIF mode to XIP
+- Go to the application entry point
+
+MCUBootApp and BlinkyApp can be built with an encrypted image plus encrypted XIP support using special build flags `ENC_IMG=1`. That flag will automatically enable XIP mode.
+
+Example build command for MCUBootApp:
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
+
+Example build command for BlinkyApp:
+
+ make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
+
+### Rollback protection Support
+
+The CYW20829 platform has a hardware-supported feature - a non-volatile counter (NV-counter). This feature is used by the MCUboot library to implement the rollback counter (security counter) protection. NV-counter on CYW20829 is implemented as an Efuse-type region that can only be incremented. This means, that each time a new counter value is updated - a corresponding number of Efuse is burned.
+
+The initial value of the rollback counter is programmed into the chip at the provisioning stage. The provisioning policy for Secure mode contains a corresponding field:
+
+
+ "reprovisioning":
+ {
+ "nv_counter": {
+ "description": "Anti-rollback counter (supports up to 32 updates)",
+ "value": 0
+ },
+
+If the `nv_counter` value is left untouched, any image with counters higher than 0 and less than (or equal to) 32 can be programmed into the chip.
+
+When preparing an image for MCUBootApp with the rollback counter support, sign it with `cysecuretools` using `policy/policy_reprovisioning_secure.json` supplied with it. The `nv_counter` value remains the same as one in the chip or set higher. When signing image `cysecuretools` places the `nv-counter` value and the reprovisioning packet in TLVs with tags 0x50 (plain value of counter) and 0x51 (reprovisioning packet). MCUBootApp then parses these tags and compares the value supplied with the image against the one stored in the Efuse counter.
+
+#### NV-counter update
+
+The CYW20829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of Efuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `cysecuretools` under `targets/cyw20829/packets/apps`. The `reprovisioning` application is used for NV-counter update.
+
+To enable the rollback counter feaure, one have to use a JSON flash map with the `"service_app"` section. Sample flash maps are located in `boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot`.
+
+The service application is supplied as a precompiled binary executed from RAM by BootROM. User should program either `cyapp_reprovisioning_signed.hex` (located at `./MCUBootApp/out/CYW20829/Debug/cyapp_reprovisioning_signed.hex`) or similar binary `./packets/apps/reprovisioning/cyapp_reprovisioning_signed.bin` (with the `"address"` specified in the `"service_app"` section of JSON flash map). Some other data is required for BootROM to execute the service app - this data is prepared by MCUBootApp.
+
+When MCUBootApp detects that the rollback counter must be updated on CYW20829, it executes the function, which prepares input data and service application descriptor data and places it in flash at addresses `"params_address"` and `"desc_address"`, respectively (see the `"service_app"` section in JSON flash map). Then, it sets the special flag in the service register, which signalizes BootROM to launch the service application and calls a system reset. BootROM is then detects the service app with its data, copies it to the corresponding addresses in RAM and executes it. Reprovisioning app then updates the `nv-counter` value in Efuse. An automatic reset can (and for convenience should) be initiated after that. To allow this value, `sys_reset_req` is set to `true` (`false` by default).
+
+ "sys_reset_req": {
+ "description": "Resets a device after RAM application finishes execution.",
+ "value": true
+ }
+
+For more details on BootROM service applications, refer to the CYW20829 documentation.
+
+#### Rollback counter behavior
+
+**Case 1**
+
+An image is singed using the `policy_reprovisioning_secure.json` policy with `nv-counter` field value set to 1; the current value of NV-counter in chip is `0` and programmed to the primary slot of MCUBootApp.
+
+MCUBootApp validates the image in the primary slot and initiates a rollback counter update. The image in the primary slot is started after that.
+
+**Case 2**
+
+An image is signed using the `policy_reprovisioning_secure.json` policy with `nv-counter`, the field value is set to 2; the current value of NV-counter in the chip is `1` and programmed into the secondary slot of MCUBootApp. The ugrade type is swap using the status partition.
+
+MCUBootApp validates the image in the secondary slot and initiates a firmware upgrade. After swapping the primary and
+secondary images, the firmware from the primary slot is executed immediately after upgrade.
+
+- If upgraded firmware operates correctly - starts its execution and sets the confirmation flag (read more in the design.md file), then, after a next reset, MCUBootApp updates the rollback counter value as in Case 1.
+
+- If upgraded firmware operates incorrectly - does not start or does not set the confirmation flag, the watchdog initiates a system reset and MCUBootApp performs the `revert` operation - copies back the previous firmware from the secondary to the primary slot, marks the image in the secondary slot as invalid and executes the original firmware from the primary slot. **The rollback counter is not updated in this case.**
+
+**Case 3**
+
+An image is signed with the `policy_reprovisioning_secure.json` policy with `nv-counter`, the field value is set to 3; the current value of NV-counter in chip is `4` and programmed to the secondary or primary slot of MCUBootApp. The upgrade type is swap using the status partition.
+
+MCUBootApp tries to validate the image, detects that the value of the rollback counter stored in the chip is greater than the one provided with the image, and rejects such an image. The firmware in the primary slot will not start and upgrade will not be initiated.
+
+When the reprovisioning packet TLV is absent in the primary or secondary image TLVs, MCUBootApp marks such an image as invalid.
+
+**Multi image case**
+
+Since there is only one physical security counter available on `CYW20829` in multi image use case, all images in system should have the same value of security counter.
+
+For example two images are programmed to their corresponding BOOT slots with security counter value of 2. Value of security counter stored in chip is also 2. In case one of images requires update and its value of security counter is increased to 3 - second image should also be updated with counter value of 3. This is required because `BootROM` will update security image counter stored in chip to 3 per first upgrade image. After that - second image would become invalid sice it still contains security counter of 2.
+
+An example of the build command for MCUBootApp with the rollback counter support:
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
+
+An example of the build command for BlinkyApp with TLVs containing rollback counter data:
+
+ make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
+
+### Build environment preparation
+
+For cysecuretools environment setup, the MCUboot `boot/cypress` folder is used.
+
+To create common CYW20829 configuration, use:
+
+ cysecuretools -t cyw20829 init
+
+To configure an OpenOCD package patch (via ModusToolbox™ by default):
+
+ cysecuretools set-ocd --name openocd --path C:/Users/%USERNAME%/ModusToolbox/tools_2.4/openocd
+
+This is enough for a NORMAL_NO_SECURE lifecycle. But for SECURE `LCS`, a few more steps are necessary.
+
+You will need to generate an RSA key pair (or copy it to keys folder, if it was generated previously), in order to provision a silicon in Secure mode:
+
+ cysecuretools -t cyw20829 -p policy/policy_secure.json create-key -k N
+
+where N is the key number, zero or one.
+
+To get access to the chip after provisioning, a debug certificate is required:
+
+ cysecuretools -t cyw20829 -p policy/policy_secure.json debug-certificate -t packets/debug_cert.json -o packets/debug_cert.bin -k N
+
+where N is the key number, zero or one.
+
+### CYW20829 provisioning
+
+For the first provision of CYW20829 chip, use:
+
+ cysecuretools -t cyw20829 -p policy/policy_%LCS%.json provision-device
+
+or
+
+ cysecuretools -t cyw20829 -p policy/policy_reprovisioning_%LCS%.json reprovision-device [--key-id N]
+
+for the following reprovision procedure.
+
+For more details on the CYW20829 environment setup and provisioning, go to the cysecuretools `README_CYW20829.md` file.
+
+### Programming applications
+
+#### Using OpenOCD from command line
+
+The following instruction assume the usage of one of Cypress KitProg3 devices and a development board.
+
+Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
+
+Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION` and `OPENOCD` variables:
+
+ export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
+
+ $OPENOCD_PATH/bin/openocd -s $OPENOCD_PATH/scripts -c "set ENABLE_ACQUIRE 0" -f $OPENOCD_PATH/scripts/interface/kitprog3.cfg -c "set SMIF_BANKS { 0 {addr 0x60000000 size 0x4000000 psize 0x1000 esize 0x40000} }" -f $OPENOCD_PATH/scripts/target/cyw20829.cfg -c "init; reset init; cmsis_flash init; flash write_image %PATH_TO_APPLICATION%/BlinkyApp.hex; shutdown"
+
+**Warning**
+
+The application slot is erased by `flash erase_address` before executing the `flash write_image` command.
+
diff --git a/boot/cypress/platforms/CYW20829/CYW20829.mk b/boot/cypress/platforms/CYW20829/CYW20829.mk
new file mode 100644
index 0000000..902ede3
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/CYW20829.mk
@@ -0,0 +1,329 @@
+################################################################################
+# \file CYW20829.mk
+# \version 1.0
+#
+# \brief
+# This file is dedicated for CYW20829 platform
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+include host.mk
+
+# Default core name of platform
+CORE := CM33
+CORE_SUFFIX := m33
+
+# PDL category suffix to resolve common path in pdl
+PDL_CAT_SUFFIX := 1B
+
+# MCU device selection, based on target device.
+# Default chips are used for supported platforms
+# This can be redefined in case of other chip usage
+DEVICE ?= CYW20829A0LKML
+# If PSVP build is required
+ifeq ($(CYW20829_PSVP), 1)
+DEVICE := CYW20829_PSVP
+SERVICE_APP_PLATFORM_SUFFIX := _psvp
+endif
+
+PLATFORM_SUFFIX ?= cyw20829
+
+# Add device name to defines
+DEFINES += $(DEVICE)
+
+# Default upgrade method
+PLATFORM_DEFAULT_USE_OVERWRITE ?= 0
+
+# Device flash start
+FLASH_START := 0x60000000
+FLASH_XIP_START := 0x08000000
+
+# Bootloader size
+PLATFORM_BOOTLOADER_SIZE ?= 0x20000
+
+###############################################################################
+# Application specific libraries
+###############################################################################
+# MCUBootApp
+###############################################################################
+THIS_APP_PATH = $(PRJ_DIR)/libs
+
+ifeq ($(APP_NAME), MCUBootApp)
+
+PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/cy_flash_pal
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/flash_qspi
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/include
+# INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/include/flash_map_backend)
+PLATFORM_SOURCES_FLASH := $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/*.c)
+PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/flash_qspi/*.c)
+
+# Platform dependend utils files
+PLATFORM_APP_SOURCES := $(PRJ_DIR)/platforms/$(FAMILY)/utils/cyw_20829_utils.c
+PLATFORM_INCLUDE_DIRS_UTILS := $(PRJ_DIR)/platforms/$(FAMILY)/utils
+
+# mbedTLS hardware acceleration settings
+ifeq ($(USE_CRYPTO_HW), 1)
+# cy-mbedtls-acceleration related include directories
+INCLUDE_DIRS_MBEDTLS_CRYPTOLITE := $(PRJ_DIR)/platforms/$(FAMILY)/mbedtls_Cryptolite
+# Collect source files for MbedTLS acceleration
+SOURCES_MBEDTLS_CRYPTOLITE := $(wildcard $(PRJ_DIR)/platforms/$(FAMILY)/mbedtls_Cryptolite/*.c)
+#
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS_CRYPTOLITE))
+# Collected source files for libraries
+SOURCES_LIBS += $(SOURCES_MBEDTLS_CRYPTOLITE)
+endif
+
+###############################################################################
+# Application dependent definitions
+# MCUBootApp
+# Default settings
+USE_EXTERNAL_FLASH := 1
+PROVISION_PATH ?= $(PRJ_DIR)
+LCS ?= NORMAL_NO_SECURE
+APPTYPE ?= flash
+SIGN_TYPE ?= bootrom_next_app
+SMIF_CRYPTO_CONFIG ?= NONE
+
+ifeq ($(LCS), NORMAL_NO_SECURE)
+APP_DEFAULT_POLICY ?= $(PRJ_DIR)/policy/policy_no_secure.json
+else
+APP_DEFAULT_POLICY ?= $(PRJ_DIR)/policy/policy_secure.json
+endif
+
+# Define MCUBootApp specific parameters
+PLATFORM_MAX_IMG_SECTORS = 32U
+
+###############################################################################
+# MCUBootApp flash map custom settings
+###############################################################################
+# Set this flag to 1 to enable custom settings in MCUBootApp
+USE_CUSTOM_MEMORY_MAP ?= 1
+
+PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE ?= 4096U
+PLATFORM_CHUNK_SIZE := 4096U
+###############################################################################
+
+###############################################################################
+# MCUBootApp service app definitions
+###############################################################################
+# Service app is only used in SECURE lifecycle
+ifeq ($(LCS), SECURE)
+# Service app path and file name
+SERVICE_APP_PATH := $(PRJ_DIR)/packets/apps/reprovisioning$(SERVICE_APP_PLATFORM_SUFFIX)
+SERVICE_APP_NAME := cyapp_reprovisioning_signed_icv0
+
+# Service app size is calculated here and converted to hex format
+PLATFORM_SERVICE_APP_SIZE ?= 0x$(shell printf "%x" `wc -c < $(SERVICE_APP_PATH)/$(SERVICE_APP_NAME).bin`)
+else
+ifeq ($(USE_HW_ROLLBACK_PROT), 1)
+$(warning Hardware rollback protection USE_HW_ROLLBACK_PROT=1 is only valid for LCS=SECURE mode)
+endif
+endif
+###############################################################################
+
+# Post build job to execute for platform
+post_build: $(OUT_CFG)/$(APP_NAME).elf
+ifeq ($(POST_BUILD_ENABLE), 1)
+ $(info [TOC2_Generate] - Execute toc2 generator script for $(APP_NAME))
+ @echo $(SHELL) $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(PLATFORM_BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM_SERVICE_APP_DESC_OFFSET)
+ $(shell $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(PLATFORM_BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM_SERVICE_APP_DESC_OFFSET))
+
+ # Convert binary to hex and rename
+ $(shell mv -f $(OUT_CFG)/$(APP_NAME).final.bin $(OUT_CFG)/$(APP_NAME).bin || rm -f $(OUT_CFG)/$(APP_NAME).bin)
+
+ $(GCC_PATH)/bin/arm-none-eabi-objcopy --change-address=$(FLASH_START) -I binary -O ihex $(OUT_CFG)/$(APP_NAME).bin $(OUT_CFG)/$(APP_NAME).hex
+ifeq ($(USE_HW_ROLLBACK_PROT), 1)
+ $(GCC_PATH)/bin/arm-none-eabi-objcopy --change-address=$$(($(FLASH_START)+$(PLATFORM_SERVICE_APP_OFFSET))) -I binary -O ihex $(SERVICE_APP_PATH)/$(SERVICE_APP_NAME).bin $(OUT_CFG)/$(SERVICE_APP_NAME).hex
+endif
+ $(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME).hex > $(OUT_CFG)/$(APP_NAME).objdump
+else
+ $(info Post build is disabled by POST_BUILD_ENABLE parameter)
+endif # POST_BUILD_ENABLE
+endif ## MCUBootApp
+
+###############################################################################
+# BlinkyApp
+###############################################################################
+ifeq ($(APP_NAME), BlinkyApp)
+
+# Basic settings
+LCS ?= NORMAL_NO_SECURE
+APPTYPE ?= flash
+SIGN_TYPE ?= mcuboot_user_app
+SMIF_CRYPTO_CONFIG ?= NONE
+
+ifeq ($(LCS), NORMAL_NO_SECURE)
+APP_DEFAULT_POLICY ?= $(PRJ_DIR)/policy/policy_no_secure.json
+else
+APP_DEFAULT_POLICY ?= $(PRJ_DIR)/policy/policy_secure.json
+endif
+
+PLATFORM_DEFAULT_ERASED_VALUE := 0xff
+
+# Define start of application
+PLATFORM_USER_APP_START ?= $(shell echo $$(($(PRIMARY_IMG_START)-$(FLASH_START)+$(FLASH_XIP_START))))
+# Define RAM start and size, slot size
+PLATFORM_DEFAULT_RAM_START ?= 0x2000C000
+PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
+
+PLATFORM_DEFINES_APP += -DUSER_APP_START_OFF=0x20000
+
+PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/cy_flash_pal
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/flash_qspi
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/include
+PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/flash_qspi/*.c)
+
+PLATFORM_DEFAULT_IMG_VER_ARG ?=
+
+PLATFORM_SIGN_ARGS := --image-format $(SIGN_TYPE) -i $(OUT_CFG)/$(APP_NAME).final.bin -o $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).bin --key-path $(PRJ_DIR)/keys/cypress-test-ec-p256.pem --update-key-path $(PRJ_DIR)/keys/priv_oem_0.pem --slot-size $(SLOT_SIZE) --align 1
+
+# Use encryption and random initial vector for image
+ifeq ($(ENC_IMG), 1)
+ PLATFORM_SIGN_ARGS += --encrypt --enckey ../../$(ENC_KEY_FILE).pem
+ PLATFORM_SIGN_ARGS += --app-addr=$(PLATFORM_USER_APP_START)
+endif
+
+post_build: $(OUT_CFG)/$(APP_NAME).bin
+ifeq ($(POST_BUILD_ENABLE), 1)
+ $(info [POST BUILD] - Executing post build script for $(APP_NAME))
+ $(info [TOC2_Generate] - Execute toc2 generator script for $(APP_NAME))
+ $(shell $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PRJ_DIR) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH))
+
+ $(shell cysecuretools -q -t cyw20829 -p $(APP_DEFAULT_POLICY) sign-image $(SIGN_ARGS))
+
+ $(GCC_PATH)/bin/arm-none-eabi-objcopy --change-address=$(HEADER_OFFSET) -I binary -O ihex $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).bin $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex
+ $(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex > $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).objdump
+else
+ $(info Post build is disabled by POST_BUILD_ENABLE parameter)
+endif # POST_BUILD_ENABLE
+endif ## BlinkyApp
+
+###############################################################################
+# Toolchain
+###############################################################################
+# Define build flags specific to a certain platform
+# Define build flags specific to a certain platform
+CFLAGS_PLATFORM := -c -mcpu=cortex-m33+nodsp --specs=nano.specs
+
+###############################################################################
+# Common libraries
+###############################################################################
+PLATFORM_SYSTEM_FILE_NAME := non-secure/ns_system_$(PLATFORM_SUFFIX).c
+PLATFORM_SOURCES_PDL_STARTUP := non-secure/ns_start_$(PLATFORM_SUFFIX).c
+PLATFORM_SOURCES_PDL_RUNTIME := non-secure/ns_runtime_$(PLATFORM_SUFFIX).c
+
+PLATFORM_SOURCES_RETARGET_IO := $(wildcard $(PRJ_DIR)/libs/retarget-io/*.c)
+
+PLATFORM_SOURCES_HAL := $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/pin_packages/cyhal_cyw20829_56_qfn.c
+PLATFORM_SOURCES_HAL += $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/triggers/cyhal_triggers_cyw20829.c
+PLATFORM_SOURCES_HAL += $(wildcard $(PRJ_DIR)/libs/mtb-hal-cat1/source/*.c)
+
+PLATFORM_INCLUDE_DIRS_PDL_STARTUP := $(PRJ_DIR)/libs/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/templates/COMPONENT_MTB/COMPONENT_$(CORE)/$(HEADER_FILES)
+
+PLATFORM_INCLUDE_DIRS_RETARGET_IO := $(PRJ_DIR)/libs/retarget-io
+
+PLATFORM_INCLUDE_DIRS_HAL := $(PRJ_DIR)/libs/mtb-hal-cat1/include
+PLATFORM_INCLUDE_DIRS_HAL += $(PRJ_DIR)/libs/mtb-hal-cat1/include_pvt
+PLATFORM_INCLUDE_DIRS_HAL += $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/
+PLATFORM_INCLUDE_DIRS_HAL += $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/pin_packages
+#PLATFORM_INCLUDE_DIRS_HAL += $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/triggers
+
+PLATFORM_DEFINES_LIBS := -DCY_USING_HAL
+PLATFORM_DEFINES_LIBS += -DCOMPONENT_CM33
+PLATFORM_DEFINES_LIBS += -DCOMPONENT_PSOC6HAL
+PLATFORM_DEFINES_LIBS += -DCOMPONENT_PSVP_CYW20829
+PLATFORM_DEFINES_LIBS += -DCOMPONENT_SOFTFP
+PLATFORM_DEFINES_LIBS += -DFLASH_BOOT
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### CYW20829.mk ####)
+$(info APPTYPE <-> $(APPTYPE))
+$(info APP_DEFAULT_POLICY <-> $(APP_DEFAULT_POLICY))
+$(info APP_NAME <-- $(APP_NAME))
+$(info CFLAGS_PLATFORM --> $(CFLAGS_PLATFORM))
+$(info CORE <-> $(CORE))
+$(info CORE_SUFFIX --> $(CORE_SUFFIX))
+$(info CYW20829_PSVP <-- $(CYW20829_PSVP))
+$(info DEFINES --> $(DEFINES))
+$(info DEVICE <-> $(DEVICE))
+$(info ENC_IMG <-- $(ENC_IMG))
+$(info ENC_KEY_FILE <-- $(ENC_KEY_FILE))
+$(info FAMILY <-- $(FAMILY))
+$(info FLASH_START <-> $(FLASH_START))
+$(info FLASH_XIP_START <-> $(FLASH_XIP_START))
+$(info GCC_PATH <-- $(GCC_PATH))
+$(info HEADER_FILES <-- $(HEADER_FILES))
+$(info HEADER_OFFSET <-- $(HEADER_OFFSET))
+$(info INCLUDE_DIRS_LIBS --> $(INCLUDE_DIRS_LIBS))
+$(info INCLUDE_DIRS_MBEDTLS_CRYPTOLITE <-> $(INCLUDE_DIRS_MBEDTLS_CRYPTOLITE))
+$(info LCS <-> $(LCS))
+$(info OUT_CFG <-- $(OUT_CFG))
+$(info PDL_CAT_SUFFIX <-> $(PDL_CAT_SUFFIX))
+$(info PLATFORM_APP_SOURCES --> $(PLATFORM_APP_SOURCES))
+$(info PLATFORM_BOOTLOADER_SIZE <-> $(PLATFORM_BOOTLOADER_SIZE))
+$(info PLATFORM_CHUNK_SIZE --> $(PLATFORM_CHUNK_SIZE))
+$(info PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE --> $(PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE))
+$(info PLATFORM_DEFAULT_ERASED_VALUE --> $(PLATFORM_DEFAULT_ERASED_VALUE))
+$(info PLATFORM_DEFAULT_IMG_VER_ARG --> $(PLATFORM_DEFAULT_IMG_VER_ARG))
+$(info PLATFORM_DEFAULT_RAM_SIZE --> $(PLATFORM_DEFAULT_RAM_SIZE))
+$(info PLATFORM_DEFAULT_RAM_START --> $(PLATFORM_DEFAULT_RAM_START))
+$(info PLATFORM_DEFAULT_USE_OVERWRITE --> $(PLATFORM_DEFAULT_USE_OVERWRITE))
+$(info PLATFORM_DEFINES_APP --> $(PLATFORM_DEFINES_APP))
+$(info PLATFORM_DEFINES_LIBS --> $(PLATFORM_DEFINES_LIBS))
+$(info PLATFORM_INCLUDE_DIRS_FLASH --> $(PLATFORM_INCLUDE_DIRS_FLASH))
+$(info PLATFORM_INCLUDE_DIRS_HAL --> $(PLATFORM_INCLUDE_DIRS_HAL))
+$(info PLATFORM_INCLUDE_DIRS_PDL_STARTUP --> $(PLATFORM_INCLUDE_DIRS_PDL_STARTUP))
+$(info PLATFORM_INCLUDE_DIRS_RETARGET_IO --> $(PLATFORM_INCLUDE_DIRS_RETARGET_IO))
+$(info PLATFORM_INCLUDE_DIRS_UTILS --> $(PLATFORM_INCLUDE_DIRS_UTILS))
+$(info PLATFORM_SERVICE_APP_DESC_OFFSET <-- $(PLATFORM_SERVICE_APP_DESC_OFFSET))
+$(info PLATFORM_SERVICE_APP_OFFSET <-- $(PLATFORM_SERVICE_APP_OFFSET))
+$(info PLATFORM_SERVICE_APP_SIZE --> $(PLATFORM_SERVICE_APP_SIZE))
+$(info PLATFORM_SIGN_ARGS --> $(PLATFORM_SIGN_ARGS))
+$(info PLATFORM_SOURCES_FLASH --> $(PLATFORM_SOURCES_FLASH))
+$(info PLATFORM_SOURCES_HAL --> $(PLATFORM_SOURCES_HAL))
+$(info PLATFORM_SOURCES_PDL_RUNTIME --> $(PLATFORM_SOURCES_PDL_RUNTIME))
+$(info PLATFORM_SOURCES_PDL_STARTUP --> $(PLATFORM_SOURCES_PDL_STARTUP))
+$(info PLATFORM_SOURCES_RETARGET_IO --> $(PLATFORM_SOURCES_RETARGET_IO))
+$(info PLATFORM_SUFFIX <-> $(PLATFORM_SUFFIX))
+$(info PLATFORM_SYSTEM_FILE_NAME --> $(PLATFORM_SYSTEM_FILE_NAME))
+$(info PLATFORM_USER_APP_START <-> $(PLATFORM_USER_APP_START))
+$(info POST_BUILD_ENABLE <-- $(POST_BUILD_ENABLE))
+$(info PRIMARY_IMG_START <-- $(PRIMARY_IMG_START))
+$(info PRJ_DIR <-- $(PRJ_DIR))
+$(info PROVISION_PATH <-> $(PROVISION_PATH))
+$(info SERVICE_APP_NAME <-> $(SERVICE_APP_NAME))
+$(info SERVICE_APP_OFFSET <-- $(SERVICE_APP_OFFSET))
+$(info SERVICE_APP_PATH <-> $(SERVICE_APP_PATH))
+$(info SERVICE_APP_PLATFORM_SUFFIX <-> $(SERVICE_APP_PLATFORM_SUFFIX))
+$(info SHELL <-- $(SHELL))
+$(info SIGN_ARGS <-- $(SIGN_ARGS))
+$(info SIGN_TYPE <-> $(SIGN_TYPE))
+$(info SLOT_SIZE <-- $(SLOT_SIZE))
+$(info SMIF_CRYPTO_CONFIG <-> $(SMIF_CRYPTO_CONFIG))
+$(info SOURCES_LIBS --> $(SOURCES_LIBS))
+$(info SOURCES_MBEDTLS_CRYPTOLITE <-> $(SOURCES_MBEDTLS_CRYPTOLITE))
+$(info TOOLCHAIN_PATH <-- $(TOOLCHAIN_PATH))
+$(info UPGRADE_SUFFIX <-- $(UPGRADE_SUFFIX))
+$(info USE_CRYPTO_HW <-- $(USE_CRYPTO_HW))
+$(info USE_CUSTOM_MEMORY_MAP --> $(USE_CUSTOM_MEMORY_MAP))
+$(info USE_EXTERNAL_FLASH --> $(USE_EXTERNAL_FLASH))
+$(info USE_HW_ROLLBACK_PROT <-- $(USE_HW_ROLLBACK_PROT))
+endif
diff --git a/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.c b/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.c
new file mode 100644
index 0000000..6adee83
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.c
@@ -0,0 +1,281 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ * Copyright (c) 2021 Infineon Technologies AG
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(MBEDTLS_CONFIG_FILE)
+#include MBEDTLS_CONFIG_FILE
+#else
+#include "config.h"
+#endif
+
+#if defined(MBEDTLS_SHA256_C)
+
+#include "mbedtls/sha256.h"
+#include "mbedtls/platform_util.h"
+
+#if defined(MBEDTLS_SHA256_ALT)
+
+/* Uncomment for distinct error codes */
+/* #define MAP_SPECIFIC_ERROR_CODES */
+
+/* Cy_Cryptolite_Sha256_Update() fails with CY_CRYPTOLITE_BUS_ERROR for data
+ * from Flash, if length is 64 bytes or more.
+ */
+#define CYW20829_SHA256_FLASH_WORKAROUND
+
+/* Parameter validation macros based on platform_util.h */
+#define SHA256_VALIDATE_RET(cond) \
+ MBEDTLS_INTERNAL_VALIDATE_RET((cond), MBEDTLS_ERR_SHA256_BAD_INPUT_DATA)
+
+#define SHA256_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE(cond)
+
+#ifdef CYW20829_SHA256_FLASH_WORKAROUND
+
+#ifndef CYW20829
+#error Workaround is only for CYW20829!
+#endif /* CYW20829 */
+
+#include "cyw20829_partition.h"
+
+/* Largest safe length for Cy_Cryptolite_Sha256_Update() */
+#define CYW20829_SHA256_SAFE_CHUNK_SIZE 63u
+
+#endif /* CYW20829_SHA256_FLASH_WORKAROUND */
+
+/**
+ * \brief Map Cryptolite status to mbed TLS error code.
+ *
+ * \param status The \c CY_CRYPTOLITE_??? function status.
+ * \return \c 0 on success.
+ * \return A negative error code on failure.
+ */
+static
+#ifndef MAP_SPECIFIC_ERROR_CODES
+inline __attribute__((always_inline))
+#endif /* MAP_SPECIFIC_ERROR_CODES */
+int cryptolite_to_mbedtls(cy_en_cryptolite_status_t status)
+{
+ int rc = -1;
+
+ switch (status) {
+ case CY_CRYPTOLITE_SUCCESS:
+ rc = 0;
+ break;
+
+#ifdef MAP_SPECIFIC_ERROR_CODES
+ case CY_CRYPTOLITE_BAD_PARAMS:
+ rc = MBEDTLS_ERR_SHA256_BAD_INPUT_DATA;
+ break;
+
+ case CY_CRYPTOLITE_HW_BUSY:
+ case CY_CRYPTOLITE_BUS_ERROR:
+ rc = MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED;
+ break;
+#endif /* MAP_SPECIFIC_ERROR_CODES */
+
+ default:
+ break;
+ }
+
+ return rc;
+}
+
+/**
+ * \brief Zeroize memory block. There is no Cy_Crypto_Core_MemSet() in
+ * Cryptolite, and no memset_s() in newlib-nano.
+ *
+ * \param buf The buffer to zeroize.
+ * \param len The length of the buffer in Bytes.
+ */
+static inline __attribute__((always_inline))
+void zeroize(void *buf, size_t len)
+{
+ volatile uint8_t *p = (volatile uint8_t *)buf;
+
+ while (len > 0u) {
+ *p++ = 0u;
+ len--;
+ }
+}
+
+/**
+ * \brief This function initializes a SHA-256 context.
+ *
+ * \param ctx The SHA-256 context to initialize. This must not be \c NULL.
+ */
+void mbedtls_sha256_init(mbedtls_sha256_context *ctx)
+{
+ cy_en_cryptolite_status_t status;
+
+ SHA256_VALIDATE(ctx != NULL);
+ zeroize(ctx, sizeof(*ctx));
+
+ /* There is some chance crypto HW might be busy here */
+ do {
+ status = Cy_Cryptolite_Sha256_Init(CRYPTO, ctx);
+ } while (CY_CRYPTOLITE_HW_BUSY == status);
+
+ SHA256_VALIDATE(CY_CRYPTOLITE_SUCCESS == status);
+}
+
+/**
+ * \brief This function clears a SHA-256 context.
+ *
+ * \param ctx The SHA-256 context to clear. This may be \c NULL, in which
+ * case this function returns immediately. If it is not \c NULL,
+ * it must point to an initialized SHA-256 context.
+ */
+void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
+{
+ if (ctx != NULL) {
+ (void)Cy_Cryptolite_Sha256_Free(CRYPTO, ctx);
+ zeroize(ctx, sizeof(*ctx));
+ }
+}
+
+/**
+ * \brief This function clones the state of a SHA-256 context.
+ *
+ * \param dst The destination context. This must be initialized.
+ * \param src The context to clone. This must be initialized.
+ */
+void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
+ const mbedtls_sha256_context *src)
+{
+ SHA256_VALIDATE(dst != NULL);
+ SHA256_VALIDATE(src != NULL);
+
+ *dst = *src;
+}
+
+/**
+ * \brief This function starts a SHA-224 or SHA-256 checksum
+ * calculation.
+ * WARNING: SHA-224 is NOT supported by Cryptolite!
+ *
+ * \param ctx The context to use. This must be initialized.
+ * \param is224 This determines which function to use. This must be
+ * either \c 0 for SHA-256, or \c 1 for SHA-224.
+ *
+ * \return \c 0 on success.
+ * \return A negative error code on failure.
+ */
+int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224)
+{
+ SHA256_VALIDATE_RET(ctx != NULL);
+ SHA256_VALIDATE_RET(0u == is224);
+
+ (void)is224;
+
+ return cryptolite_to_mbedtls(
+ Cy_Cryptolite_Sha256_Start(CRYPTO, ctx));
+}
+
+/**
+ * \brief This function feeds an input buffer into an ongoing
+ * SHA-256 checksum calculation.
+ *
+ * \param ctx The SHA-256 context. This must be initialized
+ * and have a hash operation started.
+ * \param input The buffer holding the data. This must be a readable
+ * buffer of length \p ilen Bytes.
+ * \param ilen The length of the input data in Bytes.
+ *
+ * \return \c 0 on success.
+ * \return A negative error code on failure.
+ */
+int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx,
+ const unsigned char *input,
+ size_t ilen)
+{
+ size_t offs = 0;
+ SHA256_VALIDATE_RET(ctx != NULL);
+ SHA256_VALIDATE_RET(0u == ilen || input != NULL);
+
+#ifdef CYW20829_SHA256_FLASH_WORKAROUND
+ /* Apply workaround only for data from Flash */
+ if ((uintptr_t)input >= XIP_NS_CBUS &&
+ (uintptr_t)(input + ilen) <= XIP_NS_CBUS + XIP_SIZE) {
+
+ while (ilen > CYW20829_SHA256_SAFE_CHUNK_SIZE) {
+ cy_en_cryptolite_status_t status =
+ Cy_Cryptolite_Sha256_Update(CRYPTO,
+ (uint8_t const *)input + offs,
+ CYW20829_SHA256_SAFE_CHUNK_SIZE,
+ ctx);
+
+ if (CY_CRYPTOLITE_SUCCESS != status) {
+ return cryptolite_to_mbedtls(status);
+ }
+
+ offs += CYW20829_SHA256_SAFE_CHUNK_SIZE;
+ ilen -= CYW20829_SHA256_SAFE_CHUNK_SIZE;
+ }
+ }
+#endif /* CYW20829_SHA256_FLASH_WORKAROUND */
+
+ return cryptolite_to_mbedtls(
+ Cy_Cryptolite_Sha256_Update(CRYPTO, (uint8_t const *)input + offs,
+ (uint32_t)ilen, ctx));
+}
+
+/**
+ * \brief This function finishes the SHA-256 operation, and writes
+ * the result to the output buffer.
+ *
+ * \param ctx The SHA-256 context. This must be initialized
+ * and have a hash operation started.
+ * \param output The SHA-224 or SHA-256 checksum result.
+ * This must be a writable buffer of length \c 32 Bytes.
+ *
+ * \return \c 0 on success.
+ * \return A negative error code on failure.
+ */
+int mbedtls_sha256_finish_ret(mbedtls_sha256_context *ctx,
+ unsigned char output[32])
+{
+ SHA256_VALIDATE_RET(ctx != NULL);
+ SHA256_VALIDATE_RET((unsigned char *)output != NULL);
+
+ return cryptolite_to_mbedtls(
+ Cy_Cryptolite_Sha256_Finish(CRYPTO, (uint8_t *)output, ctx));
+}
+
+/**
+ * \brief This function processes a single data block within
+ * the ongoing SHA-256 computation. This function is for
+ * internal use only.
+ *
+ * \param ctx The SHA-256 context. This must be initialized.
+ * \param data The buffer holding one block of data. This must
+ * be a readable buffer of length \c 64 Bytes.
+ *
+ * \return \c 0 on success.
+ * \return A negative error code on failure.
+ */
+int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx,
+ const unsigned char data[64])
+{
+ return mbedtls_sha256_update_ret(ctx,
+ data,
+ CY_CRYPTOLITE_SHA256_BLOCK_SIZE);
+}
+
+#endif /* MBEDTLS_SHA256_ALT */
+
+#endif /* MBEDTLS_SHA256_C */
diff --git a/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.h b/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.h
new file mode 100644
index 0000000..f919246
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.h
@@ -0,0 +1,37 @@
+/*
+ * mbed Microcontroller Library
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ * Copyright (c) 2021 Infineon Technologies AG
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if !defined(SHA256_ALT_H)
+#define SHA256_ALT_H
+
+#if defined(MBEDTLS_CONFIG_FILE)
+#include MBEDTLS_CONFIG_FILE
+#else
+#include "config.h"
+#endif
+
+#if defined(MBEDTLS_SHA256_ALT)
+
+#include "cy_cryptolite.h"
+
+typedef cy_stc_cryptolite_context_sha_t mbedtls_sha256_context;
+
+#endif /* MBEDTLS_SHA256_ALT */
+
+#endif /* (SHA256_ALT_H) */
diff --git a/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.c b/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.c
new file mode 100644
index 0000000..cd39f2d
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2021 Infineon Technologies AG
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdint.h>
+
+#include "sysflash/sysflash.h"
+#include "cy_efuse.h"
+
+#include "cy_security_cnt_platform.h"
+#include "cy_service_app.h"
+
+#if defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT
+
+#define TEST_BIT(var, pos) (0U != ((var) & (1UL << (pos))))
+
+#define NV_COUNTER_EFUSE_OFFSET 0x60
+
+/**
+ * Efuse stores nv counter value as a consequent bits. This means
+ * NV counter set to 5 in policy would be written as 0x1F. This function
+ * converts efuse value to integer value.
+ *
+ * @param val Value of security counter from which came from efuse
+ * which needs to converted in a number
+ *
+ * @return Security counter value in number form encoded in complex type on success;
+ * FIH_FAILURE on failure.
+ */
+static fih_uint convert_efuse_val(fih_uint val)
+{
+ uint32_t i = 0U;
+ uint32_t j = MAX_SEC_COUNTER_VAL - 1U;
+
+ while (TEST_BIT(fih_uint_decode(val), i++)) {
+ j--;
+ }
+
+ if ((MAX_SEC_COUNTER_VAL - j) == i) {
+ return fih_uint_encode(i - 1U);
+ }
+ else {
+ return (fih_uint)FIH_FAILURE;
+ }
+}
+
+/**
+ * Reads a data corresponding to security counter which is stored in
+ * efuses of chip and converts it actual value of security counter
+ *
+ * @param security_cnt Pointer to a variable, where security counter value would be stored
+ *
+ * @return FIH_SUCESS on success; FIH_FAILURE on failure.
+ */
+fih_int platform_security_counter_get(fih_uint *security_cnt) {
+
+ fih_int fih_ret = FIH_FAILURE;
+ cy_en_efuse_status_t efuse_stat = CY_EFUSE_ERR_UNC;
+ uint32_t nv_counter = 0;
+ fih_uint nv_counter_secure = (fih_uint)FIH_FAILURE;
+
+ /* Init also enables Efuse block */
+ efuse_stat = Cy_EFUSE_Init(EFUSE);
+
+ if (efuse_stat == CY_EFUSE_SUCCESS) {
+
+ efuse_stat = Cy_EFUSE_ReadWord(EFUSE, &nv_counter, NV_COUNTER_EFUSE_OFFSET);
+
+ if (efuse_stat == CY_EFUSE_SUCCESS){
+ /* Read value of counter from efuse twice to ensure value is not compromised */
+ nv_counter_secure = fih_uint_encode(nv_counter);
+ nv_counter = 0U;
+ efuse_stat = Cy_EFUSE_ReadWord(EFUSE, &nv_counter, NV_COUNTER_EFUSE_OFFSET);
+ }
+ if (efuse_stat == CY_EFUSE_SUCCESS){
+
+ if (fih_uint_eq(nv_counter_secure, fih_uint_encode(nv_counter))) {
+
+ *security_cnt = convert_efuse_val(nv_counter);
+ fih_ret = FIH_SUCCESS;
+
+ }
+ }
+
+ Cy_EFUSE_Disable(EFUSE);
+ Cy_EFUSE_DeInit(EFUSE);
+ }
+
+ FIH_RET(fih_ret);
+}
+
+/**
+ * Updates the stored value of a given image's security counter with a new
+ * security counter value if the new one is greater.
+ *
+ * @param reprov_packet Pointer to a reprovisioning packet containing NV counter.
+ * @param packet_len Length of a packet
+ * @param img_security_cnt Security counter value of image
+ *
+ * @return 0 on success; nonzero on failure.
+ */
+int32_t platform_security_counter_update(uint32_t img_security_cnt, uint8_t * reprov_packet)
+{
+ int32_t rc = -1;
+ fih_uint security_cnt = (fih_uint) FIH_FAILURE;
+ fih_int fih_rc = FIH_FAILURE;
+
+ /* Read value of security counter stored in chips efuses.
+ * Only one security counter is available in system. Maximum value is 32.
+ */
+ FIH_CALL(platform_security_counter_get, fih_rc, &security_cnt);
+
+ if (true == fih_eq(fih_rc, FIH_SUCCESS)) {
+
+ /* Compare the new image's security counter value against the
+ * stored security counter value.
+ */
+ if ( (img_security_cnt > fih_uint_decode(security_cnt)) &&
+ (img_security_cnt <= MAX_SEC_COUNTER_VAL) ) {
+
+ /* Attention: This function initiates system reset */
+ call_service_app(reprov_packet);
+ /* Runtime should never get here. Panic statement added to secure
+ * sutiation when hacker initiates skip of call_service_app function.
+ */
+ FIH_PANIC;
+ }
+ else {
+ rc = 0;
+ }
+ }
+
+return rc;
+}
+
+#endif /* defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.h b/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.h
new file mode 100644
index 0000000..d2e0e3c
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2021 Infineon Technologies AG
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef CY_SECURITY_CNT_PLATFORM_H
+#define CY_SECURITY_CNT_PLATFORM_H
+
+#ifdef CYW20829
+
+#include "bootutil/fault_injection_hardening.h"
+
+#define MAX_SEC_COUNTER_VAL (32U)
+
+/**
+ * Reads a data corresponding to security counter which is stored in
+ * efuses of chip and converts it actual value of security conter
+ *
+ * @param security_cnt Pointer to a variable, where security conter value would be stored
+ *
+ * @return FIH_SUCESS on success; FIH_FAILURE on failure.
+ */
+fih_int platform_security_counter_get(fih_uint *security_cnt);
+
+/**
+ * Updates the stored value of a given image's security counter with a new
+ * security counter value if the new one is greater.
+ *
+ * @param reprov_packet Pointer to a reprovisioning packet containing NV counter.
+ * @param packet_len Length of a packet
+ * @param img_security_cnt Security conter value of image
+ *
+ * @return 0 on success; nonzero on failure.
+ */
+int32_t platform_security_counter_update(uint32_t img_security_cnt, uint8_t * reprov_packet);
+#endif /* CYW20829 */
+
+#endif /* CY_SECURITY_CNT_PLATFORM_H */
diff --git a/boot/cypress/platforms/CYW20829/cy_service_app.c b/boot/cypress/platforms/CYW20829/cy_service_app.c
new file mode 100644
index 0000000..2d2f2fb
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cy_service_app.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2021 Infineon Technologies AG
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "bootutil/image.h"
+#include "bootutil_priv.h"
+#include "sysflash/sysflash.h"
+
+#include "flash_qspi.h"
+#include "cy_smif_cyw20829.h"
+
+#include "cy_service_app.h"
+
+#if defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT
+
+#ifndef CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE
+/* This is the value of external flash bytes after an erase */
+#define CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE (0xFFu)
+#endif /* CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE */
+
+/* Status code for the successful completion of the service application. */
+#define CYAPP_SUCCESS (0xF2A00001U)
+
+/*
+* Function is used to write data to external flash. Input address can be unaligned
+*/
+static int flash_write_packet(uint32_t address, uint8_t * data, uint32_t len)
+{
+ uint32_t row_addr = 0;
+
+ int32_t rc = -1;
+ cy_en_smif_status_t st = CY_SMIF_BAD_PARAM;
+ cy_stc_smif_mem_config_t *cfg = NULL;
+ SMIF_Type * smif_device = NULL;
+ uint32_t erase_size = 0U;
+ cy_stc_smif_context_t * smif_context = NULL;
+ uint8_t row_buff[CY_MAX_EXT_FLASH_ERASE_SIZE];
+
+ cfg = qspi_get_memory_config(0);
+ smif_device = qspi_get_device();
+ erase_size = qspi_get_erase_size();
+ smif_context = qspi_get_context();
+
+ if ( (erase_size > CY_MAX_EXT_FLASH_ERASE_SIZE) ||
+ (((address % erase_size) + len) > erase_size) ) {
+
+ return rc;
+ }
+
+ if ( (NULL != cfg) && (NULL != smif_device) && (NULL != smif_context) ) {
+ uint32_t row_mask = erase_size /* is a power of 2 */ - 1U;
+
+ /* Accepting an arbitrary address */
+ row_addr = (address - CY_XIP_BASE) & ~row_mask;
+
+ /* Preserving the block */
+ st = Cy_SMIF_MemRead(smif_device, cfg, row_addr, row_buff, erase_size, smif_context);
+
+ if (CY_SMIF_SUCCESS == st) {
+ /* Modifying target bytes */
+ (void)memcpy(row_buff + (address & row_mask), data, len);
+
+ /* Programming the updated block back */
+ st = Cy_SMIF_MemEraseSector(smif_device, cfg, row_addr, erase_size, smif_context);
+
+ if (CY_SMIF_SUCCESS == st) {
+ st = Cy_SMIF_MemWrite(smif_device, cfg, row_addr, row_buff, erase_size, smif_context);
+
+ if (CY_SMIF_SUCCESS == st) {
+ rc = 0;
+ }
+ }
+ }
+ }
+
+ return rc;
+}
+
+/*
+* Reads data from the external flash by arbitrary address.
+*/
+static int32_t flash_read(uint32_t address, uint8_t * data, uint32_t len)
+{
+ int32_t rc = -1;
+ cy_en_smif_status_t st = CY_SMIF_BAD_PARAM;
+ cy_stc_smif_mem_config_t *cfg = NULL;
+ SMIF_Type * smif_device = NULL;
+ cy_stc_smif_context_t * smif_context = NULL;
+
+ cfg = qspi_get_memory_config(0);
+ smif_device = qspi_get_device();
+ smif_context = qspi_get_context();
+
+ if ( (NULL != cfg) && (NULL != smif_device) && (NULL != smif_context) && (NULL != data) &&
+ (address >= CY_XIP_BASE) ) {
+ st = Cy_SMIF_MemRead(smif_device, cfg, (address - CY_XIP_BASE), data, len, smif_context);
+
+ if (CY_SMIF_SUCCESS == st) {
+ rc = 0;
+ }
+ }
+
+ return rc;
+}
+
+/*
+* In CYW20829 security counter can only be updated using special service application,
+* which is executed by BootROM. Function initializes suplement data for service app and
+* triggers system reset. BootROM is then runs service app, which performs actual update
+* of security counter value in chips efuse.
+*/
+void call_service_app(uint8_t * reprov_packet)
+{
+ int32_t rc = -1;
+ service_app_desc_type reprov_app_desc;
+
+ /* Initialize service app descriptor */
+ reprov_app_desc.service_app_descr_size = SERVICE_APP_DESC_SIZE;
+ reprov_app_desc.service_app_addr = SERVICE_APP_OFFSET;
+ reprov_app_desc.service_app_size = SERVICE_APP_SIZE;
+ reprov_app_desc.input_param_addr = SERVICE_APP_INPUT_PARAMS_OFFSET;
+ reprov_app_desc.input_param_size = REPROV_PACK_SIZE;
+
+ /* Put service app suplement data in flash */
+ if (NULL != reprov_packet)
+ {
+ /* Write input params */
+ rc = flash_write_packet((CY_XIP_BASE + SERVICE_APP_INPUT_PARAMS_OFFSET),
+ reprov_packet, REPROV_PACK_SIZE);
+ if (0 == rc) {
+ /* Write application descriptor. The address of the application
+ * descriptor is already present in the TOC2 (offset 0x8). */
+ rc = flash_write_packet((CY_XIP_BASE + SERVICE_APP_DESC_OFFSET),
+ (uint8_t *)&reprov_app_desc, sizeof(reprov_app_desc));
+ if (0 == rc) {
+ /* Set code to tell BootROM to launch a service app downloaded to RAM from an external memory */
+ SRSS->TST_DEBUG_CTL = CYBOOT_REQUEST_EXT_APP;
+ /* Trigger device reset */
+ __NVIC_SystemReset();
+ }
+ }
+ }
+}
+
+/*
+* Checks the service application completion status.
+*
+* Reads the service app descriptor from the flash. If it is populated, erases the service app
+* descriptor and verifies that the application status in the TST_DEBUG_STATUS register
+* contains the CYAPP_SUCCESS value.
+* Function limitations:
+* - assumes that the service app descriptor is located in external flash;
+* - erases the entire sector where the service app descriptor is located.
+*
+* Returns 0 if the service app descriptor is empty or TST_DEBUG_STATUS register
+* contains the CYAPP_SUCCESS value. Otherwise it returns -1.
+*/
+int32_t check_service_app_status(void)
+{
+ int32_t rc = -1;
+ uint8_t reprov_app_desc[sizeof(service_app_desc_type)] = {0};
+
+ rc = flash_read((CY_XIP_BASE + SERVICE_APP_DESC_OFFSET),
+ reprov_app_desc, sizeof(reprov_app_desc));
+ if (0 == rc) {
+ if (bootutil_buffer_is_filled(reprov_app_desc, CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE, sizeof(reprov_app_desc))) {
+ rc = 0;
+ }
+ else {
+ rc = cyw20829_smif_erase((CY_XIP_BASE + SERVICE_APP_DESC_OFFSET), qspi_get_erase_size());
+ if (0 == rc) {
+ if (CYAPP_SUCCESS == SRSS->TST_DEBUG_STATUS) {
+ rc = 0;
+ }
+ else {
+ rc = -1;
+ }
+ }
+ }
+ }
+
+ return rc;
+}
+
+#endif /* MCUBootApp && MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/CYW20829/cy_service_app.h b/boot/cypress/platforms/CYW20829/cy_service_app.h
new file mode 100644
index 0000000..c306bfa
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cy_service_app.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2021 Infineon Technologies AG
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if !defined(CY_SERVICE_APP)
+#define CY_SERVICE_APP
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if defined(MCUBootApp) && defined(MCUBOOT_HW_ROLLBACK_PROT)
+
+#include <stdint.h>
+
+#ifndef SERVICE_APP_DESC_SIZE
+#define SERVICE_APP_DESC_SIZE 0x14
+#endif /* SERVICE_APP_DESC_SIZE */
+
+#ifndef SERVICE_APP_SIZE
+#error "Size of service application is undefined!"
+#endif /* SERVICE_APP_SIZE */
+
+#define CYBOOT_REQUEST_EXT_APP (3UL)
+
+/*
+ * Service application regions in external flash
+ *
+0x60070000 -------------------------
+ | |
+ | |
+ | Service App Binary |
+ | |
+ | |
+ | |
+ | |
+0x60078000 -------------------------
+ | |
+ | Service App Input |
+ | Params |
+ | |
+0x60078400 -------------------------
+ | |
+ | Service App |
+ | Descriptor Addr |
+ | |
+0x60078420 -------------------------
+*/
+
+#ifndef SERVICE_APP_OFFSET
+#error "Service application offset is undefined!"
+#endif
+
+#ifndef SERVICE_APP_INPUT_PARAMS_OFFSET
+#error "Service application input parameters offset is undefined!"
+#endif
+
+#ifndef SERVICE_APP_DESC_OFFSET
+#error "Service application descriptor offset is undefined!"
+#endif
+
+/*
+ * 0x00 SERVICE_APP_DESCR_SIZE Service application descriptor object size,
+ * includes size entry (hardcoded value 20 bytes).
+ * 0x04 SERVICE_APP_ADDR Start address of service application in the external memory (offset).
+ * 0x08 SERVICE_APP_SIZE Service application image size.
+ * 0x0C INPUT_PARAM_ADDR Address of input parameters for service application in the
+ * external memory (offset).
+ * 0x10 INPUT_PARAM_SIZE Input parameters size.
+*/
+typedef struct
+{
+ uint32_t service_app_descr_size;
+ uint32_t service_app_addr;
+ uint32_t service_app_size;
+ uint32_t input_param_addr;
+ uint32_t input_param_size;
+} service_app_desc_type;
+
+/*
+* Function initilizes data required for service app execution and triggers system reset
+* to initiate service app execution
+*/
+void call_service_app(uint8_t * reprov_packet);
+
+/*
+* Returns completion status of the service application
+*/
+int32_t check_service_app_status(void);
+
+#endif /* MCUBootApp */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_SERVICE_APP && MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/CYW20829/cybsp.c b/boot/cypress/platforms/CYW20829/cybsp.c
new file mode 100644
index 0000000..e8407b7
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cybsp.c
@@ -0,0 +1,151 @@
+/***************************************************************************//**
+* \file cybsp.c
+*
+* Description:
+* Provides initialization code for starting up the hardware contained on the
+* Cypress board.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdlib.h>
+#include "cy_syspm.h"
+#include "cy_sysclk.h"
+#include "cybsp.h"
+#if defined(CY_USING_HAL)
+#include "cyhal_hwmgr.h"
+#include "cyhal_syspm.h"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// The sysclk deep sleep callback is recommended to be the last callback that is executed before
+// entry into deep sleep mode and the first one upon exit the deep sleep mode.
+// Doing so minimizes the time spent on low power mode entry and exit.
+#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
+ #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
+#endif
+
+#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
+static cyhal_sdio_t sdio_obj;
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_get_wifi_sdio_obj
+//--------------------------------------------------------------------------------------------------
+cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
+{
+ return &sdio_obj;
+}
+
+
+#endif // if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_register_sysclk_pm_callback
+//
+// Registers a power management callback that prepares the clock system for entering deep sleep mode
+// and restore the clocks upon wakeup from deep sleep.
+// NOTE: This is called automatically as part of \ref cybsp_init
+//--------------------------------------------------------------------------------------------------
+static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
+{
+ cy_rslt_t result = CY_RSLT_SUCCESS;
+ static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
+ static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback =
+ {
+ .callback = &Cy_SysClk_DeepSleepCallback,
+ .type = CY_SYSPM_DEEPSLEEP,
+ .callbackParams = &cybsp_sysclk_pm_callback_param,
+ .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
+ };
+
+ if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
+ {
+ result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
+ }
+ return result;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_init
+//--------------------------------------------------------------------------------------------------
+cy_rslt_t cybsp_init(void)
+{
+ // Setup hardware manager to track resource usage then initialize all system (clock/power) board
+ // configuration
+ #if defined(CY_USING_HAL)
+ cy_rslt_t result = cyhal_hwmgr_init();
+
+ if (CY_RSLT_SUCCESS == result)
+ {
+ result = cyhal_syspm_init();
+ }
+
+ #ifdef CY_CFG_PWR_VDDA_MV
+ if (CY_RSLT_SUCCESS == result)
+ {
+ cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
+ }
+ #endif
+
+ #else // if defined(CY_USING_HAL)
+ cy_rslt_t result = CY_RSLT_SUCCESS;
+ #endif // if defined(CY_USING_HAL)
+
+ #if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
+ init_cycfg_all();
+ #endif
+
+ if (CY_RSLT_SUCCESS == result)
+ {
+ result = cybsp_register_sysclk_pm_callback();
+ }
+
+ #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
+ // Initialize SDIO interface. This must be done before other HAL API calls as some SDIO
+ // implementations require specific peripheral instances.
+ // NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary().
+ // This is typically done when starting up WiFi.
+ if (CY_RSLT_SUCCESS == result)
+ {
+ // Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2,
+ // CYBSP_WIFI_SDIO_D3, CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
+ result = cyhal_sdio_init(
+ &sdio_obj,
+ CYBSP_WIFI_SDIO_CMD,
+ CYBSP_WIFI_SDIO_CLK,
+ CYBSP_WIFI_SDIO_D0,
+ CYBSP_WIFI_SDIO_D1,
+ CYBSP_WIFI_SDIO_D2,
+ CYBSP_WIFI_SDIO_D3);
+ }
+ #endif // defined(CYBSP_WIFI_CAPABLE)
+
+ // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was
+ // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP
+ // reservation list (cyreservedresources.list) to make sure no resources are reserved by both.
+ return result;
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/CYW20829/cybsp.h b/boot/cypress/platforms/CYW20829/cybsp.h
new file mode 100644
index 0000000..6d5d663
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cybsp.h
@@ -0,0 +1,83 @@
+#ifndef CYBSP_H
+#define CYBSP_H
+/***********************************************************************************************//**
+ * \file cybsp.h
+ *
+ * \brief
+ * Basic API for setting up boards containing a Cypress MCU.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2021 Cypress Semiconductor Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
+#include "cyhal_sdio.h"
+#endif
+#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE)
+#include "cybsp_bt_config.h"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \addtogroup group_bsp_errors Error Codes
+ * \{
+ * Error codes specific to the board.
+ */
+
+/** Failed to configure sysclk power management callback */
+#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK \
+ (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
+
+/** \} group_bsp_errors */
+
+/**
+ * \addtogroup group_bsp_functions Functions
+ * \{
+ * All functions exposed by the board.
+ */
+
+/**
+ * \brief Initialize all hardware on the board
+ * \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is
+ * a problem initializing any hardware it returns an error code specific
+ * to the hardware module that had a problem.
+ */
+cy_rslt_t cybsp_init(void);
+
+#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
+/**
+ * \brief Get the initialized sdio object used for communicating with the WiFi Chip.
+ * \note This function should only be called after cybsp_init();
+ * \returns The initialized sdio object.
+ */
+cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
+#endif // defined(CYBSP_WIFI_CAPABLE)
+
+/** \} group_bsp_functions */
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif /* CYBSP_H */
diff --git a/boot/cypress/platforms/CYW20829/cybsp_doc.h b/boot/cypress/platforms/CYW20829/cybsp_doc.h
new file mode 100644
index 0000000..dec68e1
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cybsp_doc.h
@@ -0,0 +1,842 @@
+#ifndef CYBSP_DOC_H
+#define CYBSP_DOC_H
+/***********************************************************************************************//**
+ * \copyright
+ * Copyright 2018-2021 Cypress Semiconductor Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#if defined(CY_USING_HAL)
+#include "cyhal_pin_package.h"
+#endif
+#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
+#include "cycfg.h"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \addtogroup group_bsp_pins Pin Mappings
+ * \{
+ * Macro definitions for common peripheral pins on the board.
+ */
+
+#if defined(CYBSP_USER_LED)
+/**
+ * \addtogroup group_bsp_pins_led LED Pins
+ * \{
+ * Pins connected to user LEDs on the board.
+ */
+
+#ifdef CYBSP_LED_RGB_RED
+/** RGB LED - Red \def CYBSP_LED_RGB_RED
+ */
+#endif
+#ifdef CYBSP_LED_RGB_GREEN
+/** RGB LED - Green \def CYBSP_LED_RGB_GREEN
+ */
+#endif
+#ifdef CYBSP_LED_RGB_BLUE
+/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE
+ */
+#endif
+#ifdef CYBSP_USER_LED
+/** User LED \def CYBSP_USER_LED
+ */
+#endif
+#ifdef CYBSP_USER_LED1
+/** User LED1 \def CYBSP_USER_LED1
+ */
+#endif
+#ifdef CYBSP_USER_LED2
+/** User LED2 \def CYBSP_USER_LED2
+ */
+#endif
+#ifdef CYBSP_USER_LED3
+/** User LED3 \def CYBSP_USER_LED3
+ */
+#endif
+#ifdef CYBSP_USER_LED4
+/** User LED 4 \def CYBSP_USER_LED4
+ */
+#endif
+#ifdef CYBSP_USER_LED5
+/** User LED 5 \def CYBSP_USER_LED5
+ */
+#endif
+#ifdef CYBSP_USER_LED6
+/** User LED 6 \def CYBSP_USER_LED6
+ */
+#endif
+#ifdef CYBSP_USER_LED7
+/** User LED 7 \def CYBSP_USER_LED7
+ */
+#endif
+#ifdef CYBSP_USER_LED8
+/** User LED 8 \def CYBSP_USER_LED8
+ */
+#endif
+#ifdef CYBSP_USER_LED9
+/** User LED 9 \def CYBSP_USER_LED9
+ */
+#endif
+#ifdef CYBSP_USER_LED10
+/** User LED 10 \def CYBSP_USER_LED10
+ */
+#endif
+#ifdef CYBSP_LED1
+/** LED 1 \def CYBSP_LED1
+ */
+#endif
+#ifdef CYBSP_LED2
+/** LED 2 \def CYBSP_LED2
+ */
+#endif
+#ifdef CYBSP_LED3
+/** LED 3 \def CYBSP_LED3
+ */
+#endif
+#ifdef CYBSP_LED3_RGB_RED
+/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED
+ */
+#endif
+#ifdef CYBSP_LED3_RGB_GREEN
+/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN
+ */
+#endif
+#ifdef CYBSP_LED3_RGB_BLUE
+/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE
+ */
+#endif
+#ifdef CYBSP_LED4
+/** LED 4 \def CYBSP_LED4
+ */
+#endif
+#ifdef CYBSP_LED5
+/** LED 5 \def CYBSP_LED5
+ */
+#endif
+#ifdef CYBSP_LED6
+/** LED 6 \def CYBSP_LED6
+ */
+#endif
+#ifdef CYBSP_LED7
+/** LED 7 \def CYBSP_LED7
+ */
+#endif
+#ifdef CYBSP_LED8
+/** LED 8 \def CYBSP_LED8
+ */
+#endif
+#ifdef CYBSP_LED9
+/** LED 9 \def CYBSP_LED9
+ */
+#endif
+#ifdef CYBSP_LED10
+/** LED 10 \def CYBSP_LED10
+ */
+#endif
+#ifdef CYBSP_LED11
+/** LED 11 \def CYBSP_LED11
+ */
+#endif
+#ifdef CYBSP_LED12
+/** LED 12 \def CYBSP_LED12
+ */
+#endif
+#ifdef CYBSP_LED13
+/** LED 13 \def CYBSP_LED13
+ */
+#endif
+#ifdef CYBSP_LED_SLD0
+/** Slider LED 0 \def CYBSP_LED_SLD0
+ */
+#endif
+#ifdef CYBSP_LED_SLD1
+/** Slider LED 1 \def CYBSP_LED_SLD1
+ */
+#endif
+#ifdef CYBSP_LED_SLD2
+/** Slider LED 2 \def CYBSP_LED_SLD2
+ */
+#endif
+#ifdef CYBSP_LED_SLD3
+/** Slider LED 3 \def CYBSP_LED_SLD3
+ */
+#endif
+#ifdef CYBSP_LED_SLD4
+/** Slider LED 4 \def CYBSP_LED_SLD4
+ */
+#endif
+#ifdef CYBSP_LED_SLD5
+/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5
+ */
+#endif
+#ifdef CYBSP_LED_BTN0
+/** Button LED 0 \def CYBSP_LED_BTN0
+ */
+#endif
+#ifdef CYBSP_LED_BTN1
+/** Button LED 1 \def CYBSP_LED_BTN1
+ */
+#endif
+#ifdef CYBSP_LED_BTN2
+/** Button LED 2 \def CYBSP_LED_BTN2
+ */
+#endif
+
+/** \} group_bsp_pins_led */
+#endif // defined(CYBSP_USER_LED)
+
+#if defined(CYBSP_USER_BTN)
+/**
+ * \addtogroup group_bsp_pins_btn Button Pins
+ * \{
+ * Pins connected to user buttons on the board.
+ */
+
+#ifdef CYBSP_SW1
+/** Switch 1 \def CYBSP_SW1
+ */
+#endif
+#ifdef CYBSP_SW2
+/** Switch 2 \def CYBSP_SW2
+ */
+#endif
+#ifdef CYBSP_SW3
+/** Switch 3 \def CYBSP_SW3
+ */
+#endif
+#ifdef CYBSP_SW4
+/** Switch 4 \def CYBSP_SW4
+ */
+#endif
+#ifdef CYBSP_USER_BTN
+/** User Button 1 \def CYBSP_USER_BTN
+ */
+#endif
+#ifdef CYBSP_USER_BTN1
+/** User Button 1 \def CYBSP_USER_BTN1
+ */
+#endif
+#ifdef CYBSP_USER_BTN2
+/** User Button 2 \def CYBSP_USER_BTN2
+ */
+#endif
+#ifdef CYBSP_POTENTIOMETER_INPUT
+/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT
+ */
+#endif
+
+/** \} group_bsp_pins_btn */
+#endif // defined(CYBSP_USER_BTN)
+
+#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
+/**
+ * \addtogroup group_bsp_pins_comm Communication Pins
+ * \{
+ * Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...)
+ */
+
+#ifdef CYBSP_DEBUG_UART_RX
+/** Pin: UART RX \def CYBSP_DEBUG_UART_RX
+ */
+#endif
+#ifdef CYBSP_DEBUG_UART_TX
+/** Pin: UART TX \def CYBSP_DEBUG_UART_TX
+ */
+#endif
+#ifdef CYBSP_I2C_SCL
+/** Pin: I2C SCL \def CYBSP_I2C_SCL
+ */
+#endif
+#ifdef CYBSP_I2C_SDA
+/** Pin: I2C SDA \def CYBSP_I2C_SDA
+ */
+#endif
+#ifdef CYBSP_SWDIO
+/** Pin: SWDIO \def CYBSP_SWDIO
+ */
+#endif
+#ifdef CYBSP_SWDCK
+/** Pin: SWDCK \def CYBSP_SWDCK
+ */
+#endif
+#ifdef CYBSP_SPI_MOSI
+/** Pin: SPI MOSI \def CYBSP_SPI_MOSI
+ */
+#endif
+#ifdef CYBSP_SPI_MISO
+/** Pin: SPI MISO \def CYBSP_SPI_MISO
+ */
+#endif
+#ifdef CYBSP_SPI_CLK
+/** Pin: SPI CLK \def CYBSP_SPI_CLK
+ */
+#endif
+#ifdef CYBSP_SPI_CS
+/** Pin: SPI CS \def CYBSP_SPI_CS
+ */
+#endif
+#ifdef CYBSP_SWO
+/** Pin: SWO \def CYBSP_SWO
+ */
+#endif
+#ifdef CYBSP_QSPI_SS
+/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS
+ */
+#endif
+#ifdef CYBSP_QSPI_D3
+/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3
+ */
+#endif
+#ifdef CYBSP_QSPI_D2
+/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2
+ */
+#endif
+#ifdef CYBSP_QSPI_D1
+/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1
+ */
+#endif
+#ifdef CYBSP_QSPI_D0
+/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0
+ */
+#endif
+#ifdef CYBSP_QSPI_SCK
+/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D0
+/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D1
+/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D2
+/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D3
+/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_CMD
+/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_CLK
+/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK
+ */
+#endif
+#ifdef CYBSP_WIFI_WL_REG_ON
+/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON
+ */
+#endif
+#ifdef CYBSP_WIFI_HOST_WAKE
+/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE
+ */
+
+/** WiFi host-wake GPIO drive mode */
+#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
+/** WiFi host-wake IRQ event */
+#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
+#endif
+#ifdef CYBSP_BT_UART_RX
+/** Pin: BT UART RX \def CYBSP_BT_UART_RX
+ */
+#endif
+#ifdef CYBSP_BT_UART_TX
+/** Pin: BT UART TX \def CYBSP_BT_UART_TX
+ */
+#endif
+#ifdef CYBSP_BT_UART_RTS
+/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS
+ */
+#endif
+#ifdef CYBSP_BT_UART_CTS
+/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS
+ */
+#endif
+#ifdef CYBSP_BT_POWER
+/** Pin: BT Power \def CYBSP_BT_POWER
+ */
+#endif
+#ifdef CYBSP_BT_HOST_WAKE
+/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE
+ */
+/** BT host-wake GPIO drive mode */
+#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE)
+/** BT host wake IRQ event */
+#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL)
+#endif
+#ifdef CYBSP_BT_DEVICE_WAKE
+/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE
+ */
+/** BT device wakeup GPIO drive mode */
+#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG)
+/** BT device wakeup polarity */
+#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u)
+#endif
+#ifdef CYBSP_PDM_CLK
+/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK
+ */
+#endif
+#ifdef CYBSP_PDM_DATA
+/** Pin PDM PCM DATA \def CYBSP_PDM_DATA
+ */
+#endif
+#ifdef CYBSP_I2S_MCLK
+/** Pin: I2S MCLK \def CYBSP_I2S_MCLK
+ */
+#endif
+#ifdef CYBSP_I2S_TX_SCK
+/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK
+ */
+#endif
+#ifdef CYBSP_I2S_TX_WS
+/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS
+ */
+#endif
+#ifdef CYBSP_I2S_TX_DATA
+/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA
+ */
+#endif
+#ifdef CYBSP_I2S_RX_SCK
+/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK
+ */
+#endif
+#ifdef CYBSP_I2S_RX_WS
+/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS
+ */
+#endif
+#ifdef CYBSP_I2S_RX_DATA
+/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA
+ */
+#endif
+#ifdef CYBSP_DEBUG_UART_RTS
+/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS
+ */
+#endif
+#ifdef CYBSP_DEBUG_UART_CTS
+/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS
+ */
+#endif
+#ifdef CYBSP_UART_RX
+/** Pin: UART RX \def CYBSP_UART_RX
+ */
+#endif
+#ifdef CYBSP_UART_TX
+/** Pin: UART TX \def CYBSP_UART_TX
+ */
+#endif
+#ifdef CYBSP_TDO_SWO
+/** Pin: \def CYBSP_TDO_SWO
+ */
+#endif
+#ifdef CYBSP_TMS_SWDIO
+/** Pin: \def CYBSP_TMS_SWDIO
+ */
+#endif
+#ifdef CYBSP_SWCLK
+/** Pin: \def CYBSP_SWCLK
+ */
+#endif
+
+/** \} group_bsp_pins_comm */
+#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
+
+#if defined(CYBSP_A0)
+/**
+ * \addtogroup group_bsp_pins_arduino Arduino Header Pins
+ * \{
+ * Pins mapped to the Arduino header on the board.
+ */
+
+#ifdef CYBSP_A0
+/** Arduino A0 \def CYBSP_A0
+ */
+#endif
+#ifdef CYBSP_A1
+/** Arduino A1 \def CYBSP_A1
+ */
+#endif
+#ifdef CYBSP_A2
+/** Arduino A2 \def CYBSP_A2
+ */
+#endif
+#ifdef CYBSP_A3
+/** Arduino A3 \def CYBSP_A3
+ */
+#endif
+#ifdef CYBSP_A4
+/** Arduino A4 \def CYBSP_A4
+ */
+#endif
+#ifdef CYBSP_A5
+/** Arduino A5 \def CYBSP_A5
+ */
+#endif
+#ifdef CYBSP_D0
+/** Arduino D0 \def CYBSP_D0
+ */
+#endif
+#ifdef CYBSP_D1
+/** Arduino D1 \def CYBSP_D1
+ */
+#endif
+#ifdef CYBSP_D2
+/** Arduino D2 \def CYBSP_D2
+ */
+#endif
+#ifdef CYBSP_D3
+/** Arduino D3 \def CYBSP_D3
+ */
+#endif
+#ifdef CYBSP_D4
+/** Arduino D4 \def CYBSP_D4
+ */
+#endif
+#ifdef CYBSP_D5
+/** Arduino D5 \def CYBSP_D5
+ */
+#endif
+#ifdef CYBSP_D6
+/** Arduino D6 \def CYBSP_D6
+ */
+#endif
+#ifdef CYBSP_D7
+/** Arduino D7 \def CYBSP_D7
+ */
+#endif
+#ifdef CYBSP_D8
+/** Arduino D8 \def CYBSP_D8
+ */
+#endif
+#ifdef CYBSP_D9
+/** Arduino D9 \def CYBSP_D9
+ */
+#endif
+#ifdef CYBSP_D10
+/** Arduino D10 \def CYBSP_D10
+ */
+#endif
+#ifdef CYBSP_D11
+/** Arduino D11 \def CYBSP_D11
+ */
+#endif
+#ifdef CYBSP_D12
+/** Arduino D12 \def CYBSP_D12
+ */
+#endif
+#ifdef CYBSP_D13
+/** Arduino D13 \def CYBSP_D13
+ */
+#endif
+#ifdef CYBSP_D14
+/** Arduino D14 \def CYBSP_D14
+ */
+#endif
+#ifdef CYBSP_D15
+/** Arduino D15 \def CYBSP_D15
+ */
+#endif
+
+/** \} group_bsp_pins_arduino */
+#endif // defined(CYBSP_A0)
+
+#if defined(CYBSP_J2_1)
+/**
+ * \addtogroup group_bsp_pins_j2 J2 Header Pins
+ * \{
+ * Pins mapped to the J2 header on the board.
+ */
+
+#ifdef CYBSP_J2_1
+/** Cypress J2 Header pin 1 \def CYBSP_J2_1
+ */
+#endif
+#ifdef CYBSP_J2_2
+/** Cypress J2 Header pin 2 \def CYBSP_J2_2
+ */
+#endif
+#ifdef CYBSP_J2_3
+/** Cypress J2 Header pin 3 \def CYBSP_J2_3
+ */
+#endif
+#ifdef CYBSP_J2_4
+/** Cypress J2 Header pin 4 \def CYBSP_J2_4
+ */
+#endif
+#ifdef CYBSP_J2_5
+/** Cypress J2 Header pin 5 \def CYBSP_J2_5
+ */
+#endif
+#ifdef CYBSP_J2_7
+/** Cypress J2 Header pin 7 \def CYBSP_J2_7
+ */
+#endif
+#ifdef CYBSP_J2_8
+/** Cypress J2 Header pin 8 \def CYBSP_J2_8
+ */
+#endif
+#ifdef CYBSP_J2_9
+/** Cypress J2 Header pin 9 \def CYBSP_J2_9
+ */
+#endif
+#ifdef CYBSP_J2_10
+/** Cypress J2 Header pin 10 \def CYBSP_J2_10
+ */
+#endif
+#ifdef CYBSP_J2_11
+/** Cypress J2 Header pin 11 \def CYBSP_J2_11
+ */
+#endif
+#ifdef CYBSP_J2_12
+/** Cypress J2 Header pin 12 \def CYBSP_J2_12
+ */
+#endif
+#ifdef CYBSP_J2_13
+/** Cypress J2 Header pin 13 \def CYBSP_J2_13
+ */
+#endif
+#ifdef CYBSP_J2_15
+/** Cypress J2 Header pin 15 \def CYBSP_J2_15
+ */
+#endif
+#ifdef CYBSP_J2_16
+/** Cypress J2 Header pin 16 \def CYBSP_J2_16
+ */
+#endif
+#ifdef CYBSP_J2_16
+/** Cypress J2 Header pin 16 \def CYBSP_J2_16
+ */
+#endif
+#ifdef CYBSP_J2_6
+/** Cypress J2 Header pin 6 \def CYBSP_J2_6
+ */
+#endif
+#ifdef CYBSP_J2_17
+/** Cypress J2 Header pin 17 \def CYBSP_J2_17
+ */
+#endif
+#ifdef CYBSP_J2_18
+/** Cypress J2 Header pin 18 \def CYBSP_J2_18
+ */
+#endif
+#ifdef CYBSP_J2_19
+/** Cypress J2 Header pin 19 \def CYBSP_J2_19
+ */
+#endif
+#ifdef CYBSP_J2_20
+/** Cypress J2 Header pin 20 \def CYBSP_J2_20
+ */
+#endif
+#ifdef CYBSP_J2_14
+/** Cypress J2 Header pin 14 \def CYBSP_J2_14
+ */
+#endif
+
+/** \} group_bsp_pins_j2 */
+#endif // defined(CYBSP_J2_1)
+
+#if defined(CYBSP_J6_1)
+/**
+ * \addtogroup group_bsp_pins_j6 J6 Header Pins
+ * \{
+ * Pins mapped to the J6 header on the board.
+ */
+
+#ifdef CYBSP_J6_1
+/** Cypress J6 Header pin 1 \def CYBSP_J6_1
+ */
+#endif
+#ifdef CYBSP_J6_2
+/** Cypress J6 Header pin 2 \def CYBSP_J6_2
+ */
+#endif
+#ifdef CYBSP_J6_3
+/** Cypress J6 Header pin 3 \def CYBSP_J6_3
+ */
+#endif
+#ifdef CYBSP_J6_4
+/** Cypress J6 Header pin 4 \def CYBSP_J6_4
+ */
+#endif
+#ifdef CYBSP_J6_5
+/** Cypress J6 Header pin 5 \def CYBSP_J6_5
+ */
+#endif
+#ifdef CYBSP_J6_6
+/** Cypress J6 Header pin 6 \def CYBSP_J6_6
+ */
+#endif
+#ifdef CYBSP_J6_7
+/** Cypress J6 Header pin 7 \def CYBSP_J6_7
+ */
+#endif
+#ifdef CYBSP_J6_8
+/** Cypress J6 Header pin 8 \def CYBSP_J6_8
+ */
+#endif
+#ifdef CYBSP_J6_9
+/** Cypress J6 Header pin 9 \def CYBSP_J6_9
+ */
+#endif
+#ifdef CYBSP_J6_10
+/** Cypress J6 Header pin 10 \def CYBSP_J6_10
+ */
+#endif
+#ifdef CYBSP_J6_11
+/** Cypress J6 Header pin 11 \def CYBSP_J6_11
+ */
+#endif
+#ifdef CYBSP_J6_12
+/** Cypress J6 Header pin 12 \def CYBSP_J6_12
+ */
+#endif
+#ifdef CYBSP_J6_13
+/** Cypress J6 Header pin 13 \def CYBSP_J6_13
+ */
+#endif
+#ifdef CYBSP_J6_14
+/** Cypress J6 Header pin 14 \def CYBSP_J6_14
+ */
+#endif
+#ifdef CYBSP_J6_15
+/** Cypress J6 Header pin 15 \def CYBSP_J6_15
+ */
+#endif
+#ifdef CYBSP_J6_16
+/** Cypress J6 Header pin 16 \def CYBSP_J6_16
+ */
+#endif
+
+/** \} group_bsp_pins_j6 */
+#endif // defined(CYBSP_J6_1)
+
+#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
+/**
+ * \addtogroup group_bsp_pins_capsense Capsense
+ * \{
+ * Pins connected to CapSense sensors on the board.
+ */
+
+#ifdef CYBSP_CSD_TX
+/** Pin: CapSesnse TX \def CYBSP_CSD_TX
+ */
+#endif
+#ifdef CYBSP_CINA
+/** Pin: CapSesnse CINA \def CYBSP_CINA
+ */
+#endif
+#ifdef CYBSP_CINTA
+/** Pin: CapSesnse CINTA \def CYBSP_CINTA
+ */
+#endif
+#ifdef CYBSP_CINB
+/** Pin: CapSesnse CINB \def CYBSP_CINB
+ */
+#endif
+#ifdef CYBSP_CINTB
+/** Pin: CapSesnse CINTB \def CYBSP_CINTB
+ */
+#endif
+#ifdef CYBSP_CMOD
+/** Pin: CapSesnse CMOD \def CYBSP_CMOD
+ */
+#endif
+#ifdef CYBSP_CSD_BTN0
+/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0
+ */
+#endif
+#ifdef CYBSP_CSD_BTN1
+/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1
+ */
+#endif
+#ifdef CYBSP_CSD_SLD0
+/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0
+ */
+#endif
+#ifdef CYBSP_CSD_SLD1
+/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1
+ */
+#endif
+#ifdef CYBSP_CSD_SLD2
+/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2
+ */
+#endif
+#ifdef CYBSP_CSD_SLD3
+/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3
+ */
+#endif
+#ifdef CYBSP_CSD_SLD4
+/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4
+ */
+#endif
+#ifdef CYBSP_CSD_SLD5
+/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5
+ */
+#endif
+#ifdef CYBSP_CSX_BTN_TX
+/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX
+ */
+#endif
+#ifdef CYBSP_CSX_BTN0
+/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0
+ */
+#endif
+#ifdef CYBSP_CSX_BTN1
+/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1
+ */
+#endif
+#ifdef CYBSP_CSX_BTN2
+/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2
+ */
+#endif
+
+/** \} group_bsp_pins_capsense */
+#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
+
+#if defined(CYBSP_WCO_IN)
+/**
+ * \addtogroup group_bsp_pins_wco WCO
+ * \{
+ * Pins connected to the WCO on the board.
+ */
+#ifdef CYBSP_WCO_IN
+/** Pin: WCO input \def CYBSP_WCO_IN
+ */
+#endif
+#ifdef CYBSP_WCO_OUT
+/** Pin: WCO output \def CYBSP_WCO_OUT
+ */
+#endif
+
+/** \} group_bsp_pins_wco */
+#endif // defined(CYBSP_WCO_IN)
+
+/** \} group_bsp_pins */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CYBSP_DOC */
diff --git a/boot/cypress/platforms/CYW20829/cybsp_types.h b/boot/cypress/platforms/CYW20829/cybsp_types.h
new file mode 100644
index 0000000..eded7dd
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cybsp_types.h
@@ -0,0 +1,56 @@
+#ifndef CYBSP_TYPES_H
+#define CYBSP_TYPES_H
+/***********************************************************************************************//**
+ * \copyright
+ * Copyright 2018-2021 Cypress Semiconductor Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#include "cybsp_doc.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \addtogroup group_bsp_pin_state Pin States
+ * \{
+ * Macros to abstract out whether the LEDs & Buttons are wired high or active low.
+ */
+/** Pin state for the LED on. */
+#ifndef CYBSP_LED_STATE_ON
+#define CYBSP_LED_STATE_ON (0U)
+#endif
+/** Pin state for the LED off. */
+#ifndef CYBSP_LED_STATE_OFF
+#define CYBSP_LED_STATE_OFF (1U)
+#endif
+/** Pin state for when a button is pressed. */
+#ifndef CYBSP_BTN_PRESSED
+#define CYBSP_BTN_PRESSED (0U)
+#endif
+/** Pin state for when a button is released. */
+#ifndef CYBSP_BTN_OFF
+#define CYBSP_BTN_OFF (1U)
+#endif
+/** \} group_bsp_pin_state */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CYBSP_TYPES_H */
diff --git a/boot/cypress/platforms/cycfg_routing.h b/boot/cypress/platforms/CYW20829/cycfg.c
similarity index 60%
copy from boot/cypress/platforms/cycfg_routing.h
copy to boot/cypress/platforms/CYW20829/cycfg.c
index bfb2998..d668910 100644
--- a/boot/cypress/platforms/cycfg_routing.h
+++ b/boot/cypress/platforms/CYW20829/cycfg.c
@@ -1,14 +1,16 @@
/*******************************************************************************
-* File Name: cycfg_routing.h
+* File Name: cycfg.c
*
* Description:
-* Establishes all necessary connections between hardware elements.
+* Wrapper function to initialize all generated code.
* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.0.1889
+* Tools Package 2.2.1.3040
+* integration_mxs40sv2-LATEST 3.0.0.5994
+* personalities 3.0.0.0
+* udd 3.0.0.775
*
********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -24,23 +26,9 @@
* limitations under the License.
********************************************************************************/
-#if !defined(CYCFG_ROUTING_H)
-#define CYCFG_ROUTING_H
+#include "cycfg.h"
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-void init_cycfg_routing(void);
-
-#define init_cycfg_connectivity() init_cycfg_routing()
-
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
-
-#if defined(__cplusplus)
+void init_cycfg_all(void)
+{
+ init_cycfg_system();
}
-#endif
-
-
-#endif /* CYCFG_ROUTING_H */
diff --git a/boot/cypress/platforms/cycfg_routing.h b/boot/cypress/platforms/CYW20829/cycfg.h
similarity index 65%
copy from boot/cypress/platforms/cycfg_routing.h
copy to boot/cypress/platforms/CYW20829/cycfg.h
index bfb2998..a8ed6ad 100644
--- a/boot/cypress/platforms/cycfg_routing.h
+++ b/boot/cypress/platforms/CYW20829/cycfg.h
@@ -1,14 +1,16 @@
/*******************************************************************************
-* File Name: cycfg_routing.h
+* File Name: cycfg.h
*
* Description:
-* Establishes all necessary connections between hardware elements.
+* Simple wrapper header containing all generated files.
* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.0.1889
+* Tools Package 2.2.1.3040
+* integration_mxs40sv2-LATEST 3.0.0.5994
+* personalities 3.0.0.0
+* udd 3.0.0.775
*
********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -24,23 +26,23 @@
* limitations under the License.
********************************************************************************/
-#if !defined(CYCFG_ROUTING_H)
-#define CYCFG_ROUTING_H
+#if !defined(CYCFG_H)
+#define CYCFG_H
#if defined(__cplusplus)
extern "C" {
#endif
-void init_cycfg_routing(void);
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_pins.h"
-#define init_cycfg_connectivity() init_cycfg_routing()
+void init_cycfg_all(void);
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#if defined(__cplusplus)
}
#endif
-#endif /* CYCFG_ROUTING_H */
+#endif /* CYCFG_H */
diff --git a/boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.c b/boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.c
new file mode 100644
index 0000000..954b06f
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.c
@@ -0,0 +1,30 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.c
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.2.0.2790
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_connectivity_bt.h"
+
diff --git a/boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.h b/boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.h
new file mode 100644
index 0000000..545ebcc
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.h
@@ -0,0 +1,54 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.h
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.2.0.2790
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CONNECTIVITY_BT_H)
+#define CYCFG_CONNECTIVITY_BT_H
+
+#include "cycfg_notices.h"
+#include "cycfg_pins.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define bt_0_power_0_ENABLED 1U
+#define CYCFG_BT_LP_ENABLED (1u)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
+#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE
+#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW
+#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE
+#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CONNECTIVITY_BT_H */
diff --git a/boot/cypress/platforms/cycfg_routing.h b/boot/cypress/platforms/CYW20829/cycfg_notices.h
similarity index 60%
copy from boot/cypress/platforms/cycfg_routing.h
copy to boot/cypress/platforms/CYW20829/cycfg_notices.h
index bfb2998..bcaadf2 100644
--- a/boot/cypress/platforms/cycfg_routing.h
+++ b/boot/cypress/platforms/CYW20829/cycfg_notices.h
@@ -1,14 +1,17 @@
/*******************************************************************************
-* File Name: cycfg_routing.h
+* File Name: cycfg_notices.h
*
* Description:
-* Establishes all necessary connections between hardware elements.
+* Contains warnings and errors that occurred while generating code for the
+* design.
* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.0.1889
+* Tools Package 2.2.1.3040
+* integration_mxs40sv2-LATEST 3.0.0.5994
+* personalities 3.0.0.0
+* udd 3.0.0.775
*
********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -24,23 +27,8 @@
* limitations under the License.
********************************************************************************/
-#if !defined(CYCFG_ROUTING_H)
-#define CYCFG_ROUTING_H
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-void init_cycfg_routing(void);
-
-#define init_cycfg_connectivity() init_cycfg_routing()
-
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
-
-#if defined(__cplusplus)
-}
-#endif
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
-#endif /* CYCFG_ROUTING_H */
+#endif /* CYCFG_NOTICES_H */
diff --git a/boot/cypress/platforms/CYW20829/cycfg_pins.c b/boot/cypress/platforms/CYW20829/cycfg_pins.c
new file mode 100644
index 0000000..2042372
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cycfg_pins.c
@@ -0,0 +1,30 @@
+/*******************************************************************************
+* File Name: cycfg_pins.c
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.2.1.3040
+* integration_mxs40sv2-LATEST 3.0.0.5994
+* personalities 3.0.0.0
+* udd 3.0.0.775
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_pins.h"
+
diff --git a/boot/cypress/platforms/CYW20829/cycfg_pins.h b/boot/cypress/platforms/CYW20829/cycfg_pins.h
new file mode 100644
index 0000000..71f7e79
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cycfg_pins.h
@@ -0,0 +1,67 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.2.1.3040
+* integration_mxs40sv2-LATEST 3.0.0.5994
+* personalities 3.0.0.0
+* udd 3.0.0.775
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if defined (CY_USING_HAL)
+ #define CYBSP_USER_LED1 (P0_0)
+ #define CYBSP_USER_LED CYBSP_USER_LED1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_USER_BTN1 (P0_1)
+ #define CYBSP_USER_BTN CYBSP_USER_BTN1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_SWO (P1_0)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_SWDIO (P1_2)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_SWDCK (P1_3)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_DEBUG_UART_RX (P3_2)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_DEBUG_UART_TX (P3_3)
+#endif //defined (CY_USING_HAL)
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/boot/cypress/platforms/CYW20829/cycfg_routing.c b/boot/cypress/platforms/CYW20829/cycfg_routing.c
new file mode 100644
index 0000000..0b66046
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cycfg_routing.c
@@ -0,0 +1,43 @@
+/*******************************************************************************
+* File Name: cycfg_routing.c
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.2.0.2790
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_routing.h"
+
+#include "cy_device_headers.h"
+
+void init_cycfg_routing(void)
+{
+ HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+ HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+ HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+}
diff --git a/boot/cypress/platforms/CYW20829/cycfg_routing.h b/boot/cypress/platforms/CYW20829/cycfg_routing.h
new file mode 100644
index 0000000..ea1de77
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cycfg_routing.h
@@ -0,0 +1,61 @@
+/*******************************************************************************
+* File Name: cycfg_routing.h
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.2.0.2790
+* latest-v2.X 2.0.0.6211
+* personalities 3.0.0.0
+* udd 3.0.0.562
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_ROUTING_H)
+#define CYCFG_ROUTING_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+void init_cycfg_routing(void);
+#define init_cycfg_connectivity() init_cycfg_routing()
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
+#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
+#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_ROUTING_H */
diff --git a/boot/cypress/platforms/CYW20829/cycfg_system.c b/boot/cypress/platforms/CYW20829/cycfg_system.c
new file mode 100644
index 0000000..c388dc9
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cycfg_system.c
@@ -0,0 +1,376 @@
+/*******************************************************************************
+* File Name: cycfg_system.c
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.2.1.3040
+* integration_mxs40sv2-LATEST 3.0.0.5994
+* personalities 3.0.0.0
+* udd 3.0.0.775
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_system.h"
+
+#define CY_CFG_SYSCLK_ECO_ERROR 1
+#define CY_CFG_SYSCLK_ALTHF_ERROR 2
+#define CY_CFG_SYSCLK_FLL_ERROR 4
+#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_MULT 504U
+#define CY_CFG_SYSCLK_FLL_REFDIV 42U
+#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE2
+#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true
+#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U
+#define CY_CFG_SYSCLK_FLL_IGAIN 8U
+#define CY_CFG_SYSCLK_FLL_PGAIN 7U
+#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U
+#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
+#define CY_CFG_SYSCLK_FLL_CCO_FREQ 198U
+#define CY_CFG_SYSCLK_FLL_OUT_FREQ 48000000
+#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 48UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF1_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 8UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
+#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
+#define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO
+#define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U
+
+void cycfg_ClockStartupError(uint32_t error);
+
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 0U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 1U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 2U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 3U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+
+__WEAK void cycfg_ClockStartupError(uint32_t error)
+{
+ (void)error; /* Suppress the compiler warning */
+ while (true) {}
+}
+__STATIC_INLINE void Cy_SysClk_FllInit(void)
+{
+ Cy_SysClk_FllOutputDividerEnable(false);
+
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(0UL))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ }
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf0Init(void)
+{
+ (void)Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+ (void)Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf1Init(void)
+{
+ (void)Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
+ (void)Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ (void)Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath0Init(void)
+{
+ (void)Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath1Init(void)
+{
+ (void)Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath2Init(void)
+{
+ (void)Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath3Init(void)
+{
+ (void)Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
+}
+
+
+void init_cycfg_system(void)
+{
+
+ /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
+ Cy_SysLib_SetWaitStates(false, 150UL);
+ #ifdef CY_CFG_PWR_ENABLED
+ #ifdef CY_CFG_PWR_INIT
+ init_cycfg_power();
+ #else
+ #warning Power system will not be configured. Update power personality to v1.20 or later.
+ #endif /* CY_CFG_PWR_INIT */
+ #endif /* CY_CFG_PWR_ENABLED */
+
+ /* Reset the core clock path to default and disable all the FLLs*/
+ (void)Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ (void)Cy_SysClk_ClkPathSetSource((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
+
+ if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
+ (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0)))
+ {
+ (void)Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ }
+
+ (void)Cy_SysClk_FllDisable();
+ (void)Cy_SysClk_ClkPathSetSource((uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
+ (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+ #ifdef CY_IP_MXBLESS
+ (void)Cy_BLE_EcoReset();
+ #endif
+
+
+ /* Enable all source clocks */
+ #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+ Cy_SysClk_PiloInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+ Cy_SysClk_WcoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+ Cy_SysClk_ClkLfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+ Cy_SysClk_AltHfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+ Cy_SysClk_EcoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+ Cy_SysClk_ExtClkInit();
+ #endif
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
+ /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
+ (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
+ (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ #else
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #endif
+
+ /* Configure Path Clocks */
+ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+ Cy_SysClk_ClkPath0Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+ Cy_SysClk_ClkPath2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+ Cy_SysClk_ClkPath3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+ Cy_SysClk_ClkPath4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+ Cy_SysClk_ClkPath5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+ Cy_SysClk_ClkPath6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+ Cy_SysClk_ClkPath7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+ Cy_SysClk_ClkPath8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+ Cy_SysClk_ClkPath9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+ Cy_SysClk_ClkPath10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+ Cy_SysClk_ClkPath11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+ Cy_SysClk_ClkPath12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+ Cy_SysClk_ClkPath13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+ Cy_SysClk_ClkPath14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+ Cy_SysClk_ClkPath15Init();
+ #endif
+
+ /* Configure and enable FLL */
+ #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+ Cy_SysClk_FllInit();
+ #endif
+
+ Cy_SysClk_ClkHf0Init();
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ /* Apply the ClkPath1 user setting */
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #endif
+
+ /* Configure HF clocks */
+ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+ Cy_SysClk_ClkHf1Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+ Cy_SysClk_ClkHf2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+ Cy_SysClk_ClkHf3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+ Cy_SysClk_ClkHf4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+ Cy_SysClk_ClkHf5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+ Cy_SysClk_ClkHf6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+ Cy_SysClk_ClkHf7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+ Cy_SysClk_ClkHf8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+ Cy_SysClk_ClkHf9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+ Cy_SysClk_ClkHf10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+ Cy_SysClk_ClkHf11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+ Cy_SysClk_ClkHf12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+ Cy_SysClk_ClkHf13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+ Cy_SysClk_ClkHf14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+ Cy_SysClk_ClkHf15Init();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+ Cy_SysClk_ClkAltSysTickInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+ Cy_SysClk_ClkPumpInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+ Cy_SysClk_ClkBakInit();
+ #endif
+
+ /* Configure default enabled clocks */
+ #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+ Cy_SysClk_IloInit();
+ #endif
+
+ #ifndef CY_CFG_SYSCLK_IMO_ENABLED
+ #error the IMO must be enabled for proper chip operation
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+ Cy_SysClk_MfoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+ Cy_SysClk_ClkMfInit();
+ #endif
+
+ /* Set accurate flash wait states */
+ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
+ Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+ #endif
+
+ /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+ SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+ (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+ (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+ (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+ (void)cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/CYW20829/cycfg_system.h b/boot/cypress/platforms/CYW20829/cycfg_system.h
new file mode 100644
index 0000000..34b2a67
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/cycfg_system.h
@@ -0,0 +1,80 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.2.1.3040
+* integration_mxs40sv2-LATEST 3.0.0.5994
+* personalities 3.0.0.0
+* udd 3.0.0.775
+*
+********************************************************************************
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_pra.h"
+#include "cy_pra_cfg.h"
+#if defined (CY_USING_HAL)
+ #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
+#define srss_0_clock_0_hfclk_1_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF1 1UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH_NUM 1UL
+#define srss_0_clock_0_iho_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */
diff --git a/boot/cypress/platforms/CYW20829/img_confirm/set_img_ok.c b/boot/cypress/platforms/CYW20829/img_confirm/set_img_ok.c
new file mode 100644
index 0000000..89bdd89
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/img_confirm/set_img_ok.c
@@ -0,0 +1,121 @@
+/********************************************************************************
+* Copyright 2021 Infineon Technologies AG
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
+
+#include "set_img_ok.h"
+
+static uint8_t row_buff[FLASH_ROW_BUF_SZ];
+
+/**
+ * @brief Function reads value of img_ok flag from address.
+ *
+ * @param address - address of img_ok flag in primary img trailer
+ * @return int - value at address
+ */
+static int read_img_ok_value(uint32_t address)
+{
+ uint32_t row_mask = qspi_get_erase_size() /* is a power of 2 */ - 1u;
+ uint32_t row_addr = (address - CY_XIP_BASE) & ~row_mask;
+
+ cy_stc_smif_mem_config_t *cfg = qspi_get_memory_config(0);
+ cy_en_smif_status_t st = Cy_SMIF_MemRead(qspi_get_device(), cfg,
+ row_addr, row_buff, qspi_get_erase_size(),
+ qspi_get_context());
+ if (CY_SMIF_SUCCESS == st) {
+ return row_buff[address & row_mask];
+ }
+
+ return -1;
+}
+
+/**
+ * @brief Function sets img_ok flag value to primary image trailer.
+ *
+ * @param address - address of img_ok flag in primary img trailer
+ * @param value - value corresponding to img_ok set
+ *
+ * @return - operation status. 0 - set succesfully, -1 - failed to set.
+ */
+static int write_img_ok_value(uint32_t address, uint8_t src)
+{
+ int rc = -1;
+ uint32_t row_addr = 0;
+
+ cy_stc_smif_mem_config_t *cfg = qspi_get_memory_config(0);
+ uint32_t row_mask = qspi_get_erase_size() /* is a power of 2 */ - 1u;
+ cy_en_smif_status_t st;
+
+ /* Accepting an arbitrary address */
+ row_addr = (address - CY_XIP_BASE) & ~row_mask;
+
+ /* Preserving the block */
+ st = Cy_SMIF_MemRead(qspi_get_device(), cfg,
+ row_addr, row_buff, qspi_get_erase_size(),
+ qspi_get_context());
+
+ if (CY_SMIF_SUCCESS == st) {
+ /* Modifying the target byte */
+ row_buff[address & row_mask] = src;
+
+ /* Programming the updated block back */
+ st = Cy_SMIF_MemEraseSector(qspi_get_device(), cfg,
+ row_addr, qspi_get_erase_size(),
+ qspi_get_context());
+
+ if (CY_SMIF_SUCCESS == st) {
+ st = Cy_SMIF_MemWrite(qspi_get_device(), cfg,
+ row_addr, row_buff, qspi_get_erase_size(),
+ qspi_get_context());
+ }
+ }
+
+ if (CY_SMIF_SUCCESS == st) {
+ rc = 0;
+ }
+
+ return rc;
+}
+
+/**
+ * @brief Public function to confirm that upgraded application is operable
+ * after swap. Should be called from main code of user application.
+ * It sets mcuboot flag img_ok in primary (boot) image trailer.
+ * MCUBootApp checks img_ok flag at first reset after upgrade and
+ * validates successful swap.
+ *
+ * @param address - address of img_ok flag in primary img trailer
+ * @param value - value corresponding to img_ok set
+ *
+ * @return - operation status. 1 - already set, 0 - set succesfully,
+ * -1 - failed to set.
+ */
+int set_img_ok(uint32_t address, uint8_t value)
+{
+ int32_t rc = -1;
+
+ if (read_img_ok_value(address) != value) {
+ rc = write_img_ok_value(address, value);
+ }
+ else {
+ rc = IMG_OK_ALREADY_SET;
+ }
+
+ return rc;
+}
+
+#endif /* !(SWAP_DISABLED) && defined(UPGRADE_IMAGE) */
diff --git a/boot/cypress/platforms/CYW20829/qspi_config.cfg b/boot/cypress/platforms/CYW20829/qspi_config.cfg
new file mode 100644
index 0000000..8858f3f
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/qspi_config.cfg
@@ -0,0 +1,29 @@
+################################################################################
+# File Name: qspi_config.cfg
+#
+# Description:
+# This file contains a SMIF Bank layout for use with OpenOCD.
+# This file was automatically generated and should not be modified.
+# QSPI Configurator: 2.30.0.4366
+#
+################################################################################
+# Copyright 2021 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+set SMIF_BANKS {
+ 0 {addr 0x60000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+
diff --git a/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.c b/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.c
new file mode 100644
index 0000000..5778fc1
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.c
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2021 Infineon Technologies AG
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "cyw_20829_utils.h"
+
+/* Cypress pdl headers */
+#include "cy_pdl.h"
+
+#include "bootutil/bootutil.h"
+#include "bootutil/bootutil_log.h"
+#include "flash_map_backend/flash_map_backend.h"
+
+#include <string.h>
+
+#include "flash_qspi.h"
+
+#ifdef CYW20829
+
+#define CY_GET_XIP_REMAP_ADDR(addr) ((addr) - CY_XIP_BASE + CY_XIP_REMAP_OFFSET)
+#define CY_GET_XIP_REMAP_ADDR_FIH(addr) fih_uint_encode(fih_uint_decode((addr)) - CY_XIP_BASE + CY_XIP_REMAP_OFFSET)
+
+#define CY_GET_SRAM0_REMAP_ADDR(addr) ((addr) - CY_SRAM0_BASE + CY_SRAM0_REMAP_OFFSET)
+
+/* TOC2 */
+#define TOC2_SIZE 16u
+#define TOC2_SIZE_IDX 0u
+/* is followed by L1 Application Descriptor */
+#define L1_APP_DESCR_SIZE 28u
+#define L1_APP_DESCR_SIZE_IDX 0u
+#define BOOTSTRAP_SRC_ADDR_IDX 1u /* points to Non-Secure Vector Table */
+#define BOOTSTRAP_DST_ADDR_IDX 2u
+#define BOOTSTRAP_SIZE_IDX 3u
+
+/* Non-Secure Vector Table */
+#define NS_VECTOR_TABLE_SIZE 340u
+#define NS_VECTOR_TABLE_ALIGNMENT 0x200u /* NS_VECTOR_TABLE_SIZE rounded up to the power of 2 */
+#define L1_APP_STACK_POINTER_IDX 0u
+#define L1_APP_RESET_HANDLER_IDX 1u
+
+/* Valid memory address range 0x2000_4000 - 0x2002_0000 */
+#define BOOTSTRAP_PROHIBITED 0x4000u
+#define BOOTSTRAP_SRAM0_ADDR (CY_SRAM0_BASE + BOOTSTRAP_PROHIBITED)
+#define BOOTSTRAP_SRAM0_SIZE (CY_SRAM0_SIZE - BOOTSTRAP_PROHIBITED)
+
+#define Q(x) #x
+#define QUOTE(x) Q(x)
+
+/*
+ * Check whether data fits into the specified memory area.
+ */
+static inline __attribute__((always_inline))
+bool fits_into(uintptr_t data, size_t data_size,
+ uintptr_t area, size_t area_size)
+{
+ uintptr_t end = data + data_size;
+ return data >= area &&
+ data_size <= area_size &&
+ end <= area + area_size &&
+ end >= data; /* overflow check */
+}
+
+/*
+ * Check whether pointer is aligned to the specified power of 2 boundary.
+ */
+static inline __attribute__((always_inline))
+bool is_aligned(uintptr_t ptr, uint32_t align)
+{
+ if ((align == 0u) || ((align & (align - 1u)) != 0u)) {
+ return false;
+ }
+ else {
+ return (ptr & (align - 1u)) == 0u;
+ }
+}
+
+/*
+ * Get an indexed word from the fih_uint-pointed array.
+ */
+static inline __attribute__((always_inline))
+uint32_t fih_ptr_word(fih_uint fih_ptr, uint32_t index)
+{
+ return ((const uint32_t *)fih_uint_decode(fih_ptr))[index];
+}
+
+#ifdef MCUBOOT_ENC_IMAGES_XIP
+/*
+ * AES-CTR buffer encryption/decryption for SMIF XIP mode
+ */
+static int mbedtls_aes_crypt_ctr_xip(mbedtls_aes_context *ctx,
+ size_t length,
+ uint32_t *nc_off,
+ uint8_t nonce_counter[BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE],
+ uint8_t stream_block[BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE],
+ const uint8_t *input,
+ uint8_t *output)
+{
+ int rc = 0;
+ uint32_t xip_addr = 0;
+ uint32_t i;
+
+ if (length % BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE != 0u) {
+ return BOOT_EBADARGS;
+ }
+
+ (void)nc_off;
+
+ while (length > 0u) {
+ rc = mbedtls_aes_crypt_ecb(ctx, MBEDTLS_AES_ENCRYPT, nonce_counter, stream_block);
+
+ if (rc != 0) {
+ break;
+ }
+
+ (void)memcpy((uint8_t*)&xip_addr, nonce_counter, sizeof(xip_addr));
+ xip_addr += BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE;
+ (void)memcpy(nonce_counter, (uint8_t*)&xip_addr, sizeof(xip_addr));
+
+ for (i = 0; i < BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE; i++) {
+ uint8_t c = *input++;
+ *output++ = c ^ stream_block[i];
+ }
+
+ length -= BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE;
+ }
+
+ return rc;
+}
+
+int
+bootutil_img_encrypt(struct enc_key_data *enc_state, int image_index,
+ struct image_header *hdr, const struct flash_area *fap, uint32_t off, uint32_t sz,
+ uint32_t blk_off, uint8_t *buf)
+{
+ struct enc_key_data *enc;
+ uint8_t nonce[BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE];
+ uint8_t stream_block[BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE];
+ int slot = 0;
+ int rc = -1;
+ uint32_t fa_addr = 0u;
+ uintptr_t flash_base = 0u;
+
+ rc = flash_device_base(fap->fa_device_id, &flash_base);
+
+ if (0 == rc) {
+
+ fa_addr = flash_base + fap->fa_off;
+
+ (void)hdr;
+
+ /* boot_copy_region will call boot_encrypt with sz = 0 when skipping over
+ the TLVs. */
+ if (sz > 0u) {
+
+ slot = flash_area_id_to_multi_image_slot(image_index, (int)fap->fa_id);
+
+ if (slot > 0) {
+ uint8_t id_pri = FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index);
+ const struct flash_area *fa_pri = NULL;
+
+ if (flash_area_open(id_pri, &fa_pri) < 0) {
+ return BOOT_EFLASH;
+ }
+ else {
+ fa_addr = flash_base + fa_pri->fa_off;
+ flash_area_close(fa_pri);
+ }
+ }
+ else if (slot < 0) {
+ return -1;
+ }
+ else {
+ /* No action required */
+ }
+
+ enc = &enc_state[slot];
+ if (enc->valid == 1u) {
+
+ off += CY_GET_XIP_REMAP_ADDR(fa_addr);
+
+ (void)memcpy(nonce, (uint8_t*)&off, sizeof(off));
+ (void)memcpy(nonce + 4u, enc->aes_iv, BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE - 4u);
+
+ rc = mbedtls_aes_crypt_ctr_xip(&enc->aes_ctr, sz, &blk_off, nonce, stream_block, buf, buf);
+ }
+ }
+ }
+
+ return rc;
+}
+#endif
+
+static __NO_RETURN void hang(void)
+{
+ FIH_PANIC;
+}
+
+/* End of cyw20829_RunAppFinish() */
+extern uint8_t hsiniFppAnuR_92802wyc[];
+
+CY_RAMFUNC_BEGIN
+static __NO_RETURN __attribute__((naked))
+void cyw20829_RunAppFinish(uintptr_t bootstrap_dst,
+ uintptr_t bootstrap_src,
+ uint32_t bootstrap_size)
+{
+ /* MCUBoot is over! The code below depends on the linker script. Assuming
+ * stack is located at the very beginning, followed by code and data, and
+ * heap is located at the end. cyw20829_RunAppFinish is located as low as
+ * possible, ideally following the MCUBoot's Vector Table in RAM, to save
+ * max space for the application (the goal is to fit below 0x20004000).
+ * First we wipe SRAM from the end of cyw20829_RunAppFinish to the end of
+ * heap. Then bootstrap is copied to its place. Then, after the necessary
+ * setup, we wipe SRAM from the stack limit to the wiping loop itself. So
+ * only 6 launcher's instructions are left. Note that the app's bootstrap
+ * is copied to the area cleaned at the start, so self-destruction cannot
+ * affect it. Also, we have to remap code addresses from C-bus to S-AHB.
+ */
+ asm volatile(
+ " cpsid i\n" /* Disable interrupts */
+ /* Wipe MCUBoot's RAM to prevent information leakage (Pt. 1) */
+ " mov r0, #0\n"
+ " ldr r1, =(hsiniFppAnuR_92802wyc-" /* Should be remapped from */
+ QUOTE(CY_SRAM0_REMAP_OFFSET)"+" /* C-bus to S-AHB! */
+ QUOTE(CY_SRAM0_BASE)")\n" /* Avoid self-destruction */
+ " ldr r2, =__HeapLimit\n"
+ "1: str r0, [r1]\n"
+ " add r1, #4\n"
+ " cmp r1, r2\n"
+ " blo 1b\n"
+ /* Copy most of bootstrap by doublewords */
+ " mov r2, %0\n"
+ "2: cmp %2, #8\n"
+ " blo 3f\n" /* Note: bootstrap_size cannot be 0 */
+ " ldmia %1!, {r0, r1}\n"
+ " stmia r2!, {r0, r1}\n"
+ " subs %2, #8\n"
+ " beq 4f\n" /* The whole bootstrap is copied */
+ " b 2b\n"
+ /* Copy rest of bootstrap by bytes (if any) */
+ "3: ldrb r0, [%1]\n"
+ " add %1, #1\n"
+ " strb r0, [r2]\n"
+ " add r2, #1\n"
+ " subs %2, #1\n"
+ " bne 3b\n"
+ "4: dmb sy\n"
+ /* Relocate Vector Table */
+ " str %0, [%3]\n" /* Bootstrap starts with Vector Table */
+ " str %0, [%4]\n" /* (%0 points to it) */
+ /* Prepare stack */
+ " ldr r0, ="QUOTE(CY_SRAM0_BASE)"\n"
+ " msr msplim, r0\n"
+ " ldr r0, [%0]\n"
+ " msr msp, r0\n"
+ /* Reset handler */
+ " ldr lr, [%0, #4]\n"
+ /* Wipe MCUBoot's RAM to prevent information leakage (Pt. 2) */
+ " mov r0, #0\n"
+ " ldr r1, =__StackLimit\n"
+ " ldr r2, =(5f-" /* Should be remapped from C-bus to S-AHB! */
+ QUOTE(CY_SRAM0_REMAP_OFFSET)"+"
+ QUOTE(CY_SRAM0_BASE)")\n" /* Final self-destruction */
+ " b 5f\n" /* Skip the constant pool */
+ /* Put the constant pool here (to avoid premature self-destruction) */
+ " .ltorg\n"
+ "5: str r0, [r1]\n"
+ " add r1, #4\n"
+ " cmp r1, r2\n"
+ " blo 5b\n"
+ /* Wipe general-purpose registers just in case */
+ " Ldmdb r1, {r1-r12}\n" /* Load GPRs from the zeroed memory */
+ /* Launch bootstrap */
+ " bx lr\n"
+ "hsiniFppAnuR_92802wyc:\n" /* End of function code */
+ : /* no output */
+ : /* input %0 */ "r" (bootstrap_dst),
+ /* input %1 */ "r" (bootstrap_src),
+ /* input %2 */ "r" (bootstrap_size),
+ /* input %3 */ "r" (&MXCM33->CM33_NS_VECTOR_TABLE_BASE),
+ /* input %4 */ "r" (&SCB->VTOR)
+ : /* clobbered */ "cc", "r0", "r1", "r2");
+}
+CY_RAMFUNC_END
+
+CY_RAMFUNC_BEGIN
+__NO_RETURN void cyw20829_RunApp(fih_uint toc2_addr, uint32_t *key, uint32_t *iv)
+{
+ fih_uint l1_app_descr_addr = (fih_uint)FIH_FAILURE;
+ fih_uint ns_vect_tbl_addr = (fih_uint)FIH_FAILURE;
+
+ uint32_t bootstrap_src_addr = 0u;
+ uint32_t bootstrap_dst_addr = 0u;
+ uint32_t bootstrap_size = 0u;
+
+ uint32_t stack_pointer = 0u;
+ uint32_t reset_handler = (uint32_t)&hang;
+
+#ifdef MCUBOOT_ENC_IMAGES_XIP
+ if (key != NULL && iv != NULL) {
+ SMIF_Type *smif_device = qspi_get_device();
+
+ Cy_SMIF_SetCryptoKey(smif_device, key);
+ Cy_SMIF_SetCryptoIV(smif_device, iv);
+
+ // TODO: Check for other Slave select ID
+ if (Cy_SMIF_SetCryptoEnable(smif_device, CY_SMIF_SLAVE_SELECT_0) != CY_SMIF_SUCCESS) {
+ FIH_PANIC;
+ }
+
+ Cy_SMIF_SetMode(smif_device, CY_SMIF_MEMORY);
+
+ /* Clean up key and IV */
+ (void)memset(key, 0, BOOTUTIL_CRYPTO_AES_CTR_KEY_SIZE);
+ (void)memset(iv, 0, BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE);
+ }
+#else
+ (void)key;
+ (void)iv;
+#endif /* MCUBOOT_ENC_IMAGES_XIP */
+
+ /* Validate TOC2 in external memory (non-remapped) */
+ if (!is_aligned((uintptr_t)fih_uint_decode(toc2_addr), 4u) ||
+ !fits_into((uintptr_t)fih_uint_decode(toc2_addr), TOC2_SIZE,
+ (uintptr_t)CY_XIP_BASE, CY_XIP_SIZE) ||
+ fih_ptr_word(CY_GET_XIP_REMAP_ADDR_FIH(fih_uint_decode(toc2_addr)), TOC2_SIZE_IDX) != TOC2_SIZE) {
+
+ FIH_PANIC;
+ }
+
+ /* TOC2 is followed by L1 Application Descriptor */
+ l1_app_descr_addr = CY_GET_XIP_REMAP_ADDR_FIH(fih_uint_decode(toc2_addr) + TOC2_SIZE);
+
+ /* Validate L1 Application Descriptor in external memory */
+ if (!is_aligned((uintptr_t)fih_uint_decode(l1_app_descr_addr), 4u) ||
+ !fits_into((uintptr_t)fih_uint_decode(l1_app_descr_addr), L1_APP_DESCR_SIZE,
+ (uintptr_t)CY_XIP_REMAP_OFFSET, CY_XIP_SIZE) ||
+ fih_ptr_word(l1_app_descr_addr, L1_APP_DESCR_SIZE_IDX) != L1_APP_DESCR_SIZE) {
+
+ FIH_PANIC;
+ }
+
+ /* Extract L1 Application Descriptor fields */
+ bootstrap_src_addr = fih_ptr_word(l1_app_descr_addr, BOOTSTRAP_SRC_ADDR_IDX);
+ bootstrap_dst_addr = fih_ptr_word(l1_app_descr_addr, BOOTSTRAP_DST_ADDR_IDX);
+ bootstrap_size = fih_ptr_word(l1_app_descr_addr, BOOTSTRAP_SIZE_IDX);
+
+#ifndef NDEBUG
+ /* Make sure bootstrap and launcher do not overlap. Checks the validity of
+ * the linker script, the runtime check is below (BOOTSTRAP_SRAM0_ADDR).
+ */
+ if (fits_into((uintptr_t)bootstrap_dst_addr, 0,
+ (uintptr_t)cyw20829_RunAppFinish,
+ (uintptr_t)hsiniFppAnuR_92802wyc - (uintptr_t)cyw20829_RunAppFinish) ||
+ fits_into((uintptr_t)bootstrap_dst_addr + bootstrap_size, 0,
+ (uintptr_t)cyw20829_RunAppFinish,
+ (uintptr_t)hsiniFppAnuR_92802wyc - (uintptr_t)cyw20829_RunAppFinish)) {
+
+ FIH_PANIC;
+ }
+#endif /* !NDEBUG */
+
+ /* Validate bootstrap destination in SRAM (starts with the NS Vector Table) */
+ if (bootstrap_size < NS_VECTOR_TABLE_SIZE ||
+ !is_aligned((uintptr_t)bootstrap_dst_addr, NS_VECTOR_TABLE_ALIGNMENT) ||
+ !fits_into((uintptr_t)bootstrap_dst_addr, bootstrap_size,
+ (uintptr_t)BOOTSTRAP_SRAM0_ADDR, BOOTSTRAP_SRAM0_SIZE)) {
+
+ FIH_PANIC;
+ }
+
+ /* Bootstrap source in external memory starts with the image of NS Vector Table) */
+ ns_vect_tbl_addr = CY_GET_XIP_REMAP_ADDR_FIH(fih_uint_decode(toc2_addr) + bootstrap_src_addr);
+
+ /* Validate bootstrap source image in external memory */
+ if (!is_aligned((uintptr_t)fih_uint_decode(ns_vect_tbl_addr), 4u) ||
+ !fits_into((uintptr_t)fih_uint_decode(ns_vect_tbl_addr), bootstrap_size,
+ (uintptr_t)CY_XIP_REMAP_OFFSET, CY_XIP_SIZE)) {
+
+ FIH_PANIC;
+ }
+
+ /* Extract app's Stack Pointer from the image of NS Vector Table and validate it */
+ stack_pointer = fih_ptr_word(ns_vect_tbl_addr, L1_APP_STACK_POINTER_IDX);
+
+ if (!is_aligned((uintptr_t)stack_pointer, 8u) ||
+ !fits_into((uintptr_t)stack_pointer, 0u,
+ (uintptr_t)CY_SRAM0_BASE, CY_SRAM0_SIZE)) {
+
+ FIH_PANIC;
+ }
+
+ /* Extract app's Reset Handler from the image of NS Vector Table and validate it */
+ reset_handler = fih_ptr_word(ns_vect_tbl_addr, L1_APP_RESET_HANDLER_IDX);
+
+ if ((reset_handler & 1u) != 1u /* i.e., thumb function */ ||
+ !fits_into((uintptr_t)(reset_handler & ~1u), 2u, /* should lay in the remapped SRAM */
+ (uintptr_t)CY_GET_SRAM0_REMAP_ADDR(bootstrap_dst_addr), bootstrap_size)) {
+
+ FIH_PANIC;
+ }
+
+ /* MCUBoot is over */
+ cyw20829_RunAppFinish((uintptr_t)bootstrap_dst_addr,
+ (uintptr_t)fih_uint_decode(ns_vect_tbl_addr),
+ bootstrap_size);
+}
+CY_RAMFUNC_END
+
+#endif /* CYW20829 */
diff --git a/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.h b/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.h
new file mode 100644
index 0000000..ecaf9d1
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2021 Infineon Technologies AG
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef CYW_20829_UTILS_H
+#define CYW_20829_UTILS_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include "sysflash/sysflash.h"
+
+#include "bootutil/image.h"
+#include "bootutil/enc_key.h"
+#include "bootutil/fault_injection_hardening.h"
+
+#ifdef CYW20829
+
+extern const volatile uint32_t __data_start__[];
+extern const volatile uint32_t __data_end__[];
+
+extern const volatile uint32_t __bss_start__[];
+extern const volatile uint32_t __bss_end__[];
+
+extern const volatile uint32_t __HeapBase[];
+extern const volatile uint32_t __HeapLimit[];
+
+extern const volatile uint32_t __StackLimit[];
+extern const volatile uint32_t __StackTop[];
+
+__NO_RETURN void cyw20829_RunApp(fih_uint toc2_addr, uint32_t *key, uint32_t *iv);
+#endif
+
+#endif /* CYW_20829_UTILS_H */
+
diff --git a/boot/cypress/platforms/PSOC6/PSOC6.md b/boot/cypress/platforms/PSOC6/PSOC6.md
new file mode 100644
index 0000000..8cbe47f
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/PSOC6.md
@@ -0,0 +1,98 @@
+## PSoC™ 6 platform description
+
+### MCUBootApp specifics
+
+### Default memory map
+
+This repository provides a set of predefined memory maps in JSON files. They are located in `cy_flash_pal/flash_psoc6/flashmap`. One can use the predefined flash map or define its own using the predefined file as a template.
+
+### JSON flash map
+As absolute addresses are used in JSON flash maps, the placement of flash area in internal or external memory is derived from its address. For instance:
+```
+ "application_1": {
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ "upgrade_address": {
+ "description": "Address of the application secondary slot",
+ "value": "0x18030200"
+ },
+ "upgrade_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x10000"
+ }
+ }
+```
+declares primary slot in the internal Flash, and secondary slot in the external Flash.
+
+##### Shared secondary slot
+Some Flash ICs have large erase block. For SEMPER™ Secure NOR Flash it is 256 kilobytes, so placing each image trailer in a separate erase block seems a waste.
+
+Specific technique is needed to place all trailers of the shared secondary slot in the single erase block. Since the whole erase block with trailer is occasionally cleared by MCUBoot, image padding is required to place trailers at different addresses and to avoid unintended erasing of image bytes.
+```
+ /| |-----------| |
+ / | | | |
+ / |-----------| | |
+ / | | | |
+ / | | Image 2 |-----------|
+ / | Image 1 | | |
+ / : : : Image 3 :
+ / | | | |
+ / |-----------|-----------|-----------|
+ Shared | Trailer | Padding | |\
+Secondary |0x200 bytes|0x200 bytes| Padding | \
+ Slot |-----------|-----------| | \
+ \ | | Trailer |0x400 bytes| \
+ \ | |0x200 bytes| | Erase
+ \ | |-----------|-----------| block
+ \ | | | Trailer | 256 K
+ \ | | |0x200 bytes| /
+ \ | | |-----------| /
+ \ : : : : /
+ \ | | | |/
+ \|-----------|-----------|-----------|
+```
+The pre-build script issues messages, such as
+```
+Note: application_2 (secondary slot) requires 512 padding bytes before trailer
+```
+to remind about the necessary padding.
+
+### Encrypted Image Support
+
+To protect the user's image from unwanted read, Upgrade Image Encryption can be applied. The ECDH/HKDF with the EC256 scheme is used in a given solution as well as mbedTLS as a crypto provider.
+
+To enable the image encryption support, use the `ENC_IMG=1` build flag (BlinkyApp should also be built with this flash set 1).
+
+The user is also responsible for providing corresponding binary key data in `enc_priv_key[]` (file `\MCUBootApp\keys.c`). The public part will be used by `imgtool` when signing and encrypting upgrade image. Signing image with encryption is described in [BlinkyApp.md](../../BlinkyApp/BlinkyApp.md).
+
+After MCUBootApp is built with these settings, unencrypted and encrypted images will be accepted in the secondary (upgrade) slot.
+
+An example of the command:
+
+ make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json ENC_IMG=1
+
+NOTE: Debug configuration of MCUBootApp with Multi-image encrypted upgrades in external flash (built with flags `BUILDCFG=Debug` `MCUBOOT_IMG_NUMBER=2 USE_EXTERNAL_FLASH=1 ENC_IMG=1`) is set to use optimization level `-O2 -g3` to fit into `0x18000` allocated for `MCUBootApp`.
+
+### Programming applications
+
+#### Using OpenOCD from command line
+
+The following instructions assume the usage of one of Cypress development kits `CY8CPROTO_062_4343W`.
+
+Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
+
+Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION.hex` and `OPENOCD` paths:
+
+ export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
+
+ ${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
+ -f ${OPENOCD}/scripts/interface/kitprog3.cfg \
+ -f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
+ -c "init; reset init; program PATH_TO_APPLICATION.hex" \
+ -c "resume; reset; exit"
diff --git a/boot/cypress/platforms/PSOC6/PSOC6.mk b/boot/cypress/platforms/PSOC6/PSOC6.mk
new file mode 100644
index 0000000..b4b0c20
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/PSOC6.mk
@@ -0,0 +1,300 @@
+################################################################################
+# \file PSOC6.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe supported boards and platforms for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+include host.mk
+
+# PDL category suffix to resolve common path in pdl
+PDL_CAT_SUFFIX := 1A
+
+# MCU device selection, based on target device.
+# Default chips are used for supported platforms
+# This can be redefined in case of other chip usage
+ifeq ($(PLATFORM), PSOC_062_2M)
+# base kit CY8CPROTO-062-4343W
+DEVICE ?= CY8C624ABZI_S2D44
+PLATFORM_SUFFIX := 02
+else ifeq ($(PLATFORM), PSOC_062_1M)
+# base kit CY8CKIT-062-WIFI-BT
+DEVICE ?= CY8C6247BZI-D54
+PLATFORM_SUFFIX := 01
+else ifeq ($(PLATFORM), PSOC_062_512K)
+# base kit CY8CPROTO-062S3-4343W
+DEVICE ?= CY8C6245LQI-S3D72
+PLATFORM_SUFFIX := 03
+endif
+
+# Add device name to defines
+DEFINES += $(DEVICE)
+
+# Default upgrade method
+PLATFORM_DEFAULT_USE_OVERWRITE ?= 0
+
+###############################################################################
+# Application specific libraries
+###############################################################################
+# MCUBootApp
+###############################################################################
+THIS_APP_PATH = $(PRJ_DIR)/libs
+
+ifeq ($(APP_NAME), MCUBootApp)
+
+CORE := CM0P
+CORE_SUFFIX = m0plus
+
+# Add retartget IO implementation using pdl
+PLATFORM_SOURCES_RETARGET_IO_PDL := $(wildcard $(THIS_APP_PATH)/retarget_io_pdl/*.c)
+
+# Collect dirrectories containing headers for PLATFORM
+PLATFORM_INCLUDE_RETARGET_IO_PDL := $(THIS_APP_PATH)/retarget_io_pdl
+
+# PSOC6HAL source files
+PLATFORM_SOURCES_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_crypto_common.c
+PLATFORM_SOURCES_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_hwmgr.c
+
+# needed for Crypto HW Acceleration and headers inclusion, do not use for peripherals
+# peripherals should be accessed
+PLATFORM_INCLUDE_DIRS_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include
+PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include
+PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include_pvt
+PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages
+
+# mbedTLS hardware acceleration settings
+ifeq ($(USE_CRYPTO_HW), 1)
+# cy-mbedtls-acceleration related include directories
+INCLUDE_DIRS_MBEDTLS_MXCRYPTO := $(THIS_APP_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO
+# Collect source files for MbedTLS acceleration
+SOURCES_MBEDTLS_MXCRYPTO := $(wildcard $(THIS_APP_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO/*.c)
+#
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS_MXCRYPTO))
+# Collected source files for libraries
+SOURCES_LIBS += $(SOURCES_MBEDTLS_MXCRYPTO)
+endif
+
+###############################################################################
+# Application dependent definitions
+# MCUBootApp default settings
+# 0 by default until mbedtls.3.0 support
+USE_CRYPTO_HW ?= 0
+
+# Bootloader size
+PLATFORM_BOOTLOADER_SIZE ?= 0x18000
+###############################################################################
+
+PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/cy_flash_pal
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/flash_qspi
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/include
+# INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/cy_flash_pal/flash_psoc/include/flash_map_backend)
+PLATFORM_SOURCES_FLASH := $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_psoc6/*.c)
+PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_psoc6/flash_qspi/*.c)
+
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+ifeq ($(BUILDCFG), Debug)
+# Include files with statically defined SMIF configuration to enable
+# OpenOCD debugging of external memory
+PLATFORM_SOURCES_FLASH += cy_serial_flash_prog.c
+PLATFORM_SOURCES_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/smif_cfg_dbg
+endif
+endif
+
+# Post build job to execute for platform
+post_build: $(OUT_CFG)/$(APP_NAME)_unsigned.hex
+ifeq ($(POST_BUILD_ENABLE), 1)
+ $(info [POST BUILD] - Executing post build script for $(APP_NAME))
+ $(shell cp -f $(OUT_CFG)/$(APP_NAME)_unsigned.hex $(OUT_CFG)/$(APP_NAME).hex)
+ $(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME).hex > $(OUT_CFG)/$(APP_NAME).objdump
+else
+ $(info Post build is disabled by POST_BUILD_ENABLE parameter)
+endif # POST_BUILD_ENABLE
+endif ## MCUBootApp
+
+###############################################################################
+# BlinkyApp
+###############################################################################
+ifeq ($(APP_NAME), BlinkyApp)
+
+CORE := CM4
+CORE_SUFFIX = m4
+
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+PLATFORM_DEFAULT_ERASED_VALUE := 0xff
+else
+PLATFORM_DEFAULT_ERASED_VALUE := 0
+endif
+
+# Define start of application, RAM start and size, slot size
+ifeq ($(PLATFORM), PSOC_062_2M)
+ifeq ($(USE_XIP), 1)
+ PLATFORM_DEFAULT_RAM_START ?= 0x08020000
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0xE0000
+else
+ PLATFORM_DEFAULT_RAM_START ?= 0x08040000
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
+endif
+else ifeq ($(PLATFORM), PSOC_062_1M)
+ifeq ($(USE_XIP), 1)
+ PLATFORM_DEFAULT_RAM_START ?= 0x08000800
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x47800
+else
+ PLATFORM_DEFAULT_RAM_START ?= 0x08020000
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
+endif
+else ifeq ($(PLATFORM), PSOC_062_512K)
+ifeq ($(USE_XIP), 1)
+ PLATFORM_DEFAULT_RAM_START ?= 0x08000800
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x3F800
+else
+ PLATFORM_DEFAULT_RAM_START ?= 0x08020000
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
+endif
+endif
+# Default start address of application (boot)
+PLATFORM_USER_APP_START ?= $(PRIMARY_IMG_START)
+# For PSOC6 platform PRIMARY_IMG_START start is the same as USER_APP_START
+# This parameter can be different in cases when code is resided in
+# flash mapped to one address range, but executed using different bus
+# for access with another address range. For example, execution of code
+# from external memory in XIP mode.
+PLATFORM_DEFAULT_PRIMARY_IMG_START ?= $(PLATFORM_DEFAULT_USER_APP_START)
+
+PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/cy_flash_pal
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/flash_qspi
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/include
+PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_psoc6/flash_qspi/*.c)
+
+# We still need this for MCUBoot apps signing
+IMGTOOL_PATH ?= ../../scripts/imgtool.py
+
+PLATFORM_DEFAULT_IMG_VER_ARG ?= -v "1.0.0"
+
+PLATFORM_SIGN_ARGS := sign --header-size 1024 --pad-header --align 8 -M 512
+
+# Set parameters needed for signing
+ifeq ($(IMG_TYPE), UPGRADE)
+ # Use encryption and random initial vector for image
+ ifeq ($(ENC_IMG), 1)
+ PLATFORM_SIGN_ARGS += --encrypt ../../$(ENC_KEY_FILE).pem
+ PLATFORM_SIGN_ARGS += --use-random-iv
+ endif
+endif
+
+# Post build action to execute after main build job
+post_build: $(OUT_CFG)/$(APP_NAME).bin
+ifeq ($(POST_BUILD_ENABLE), 1)
+ $(info [POST BUILD] - Executing post build script for $(APP_NAME))
+ $(shell mv -f $(OUT_CFG)/$(APP_NAME).bin $(OUT_CFG)/$(APP_NAME)_unsigned.bin)
+ $(PYTHON_PATH) $(IMGTOOL_PATH) $(SIGN_ARGS) -S $(SLOT_SIZE) -R $(ERASED_VALUE) $(UPGRADE_TYPE) -k keys/$(SIGN_KEY_FILE).pem $(OUT_CFG)/$(APP_NAME)_unsigned.bin $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex --hex-addr=$(HEADER_OFFSET)
+ $(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex > $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).objdump
+else
+ $(info Post build is disabled by POST_BUILD_ENABLE parameter)
+endif # POST_BUILD_ENABLE
+endif ## BlinkyApp
+
+
+###############################################################################
+# Toolchain
+###############################################################################
+# Define build flags specific to a certain platform
+CFLAGS_PLATFORM := -mcpu=cortex-$(CORE_SUFFIX) -mfloat-abi=soft -fno-stack-protector -fstrict-aliasing
+
+###############################################################################
+# Common libraries
+###############################################################################
+PLATFORM_SYSTEM_FILE_NAME := system_psoc6_c$(CORE_SUFFIX).c
+PLATFORM_STARTUP_FILE := $(PRJ_DIR)/libs/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/startup_psoc6_$(PLATFORM_SUFFIX)_c$(CORE_SUFFIX).S
+
+PLATFORM_INCLUDE_DIRS_PDL_STARTUP := $(PRJ_DIR)/libs/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/templates/COMPONENT_MTB
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### PSOC6.mk ####)
+$(info APP_NAME <-- $(APP_NAME))
+$(info CFLAGS_PLATFORM <-> $(CFLAGS_PLATFORM))
+$(info COMPILER <-- $(COMPILER))
+$(info CORE <-> $(CORE))
+$(info CORE_SUFFIX <-- $(CORE_SUFFIX))
+$(info DEFINES <-> $(DEFINES))
+$(info DEVICE <-> $(DEVICE))
+$(info ENC_IMG <-- $(ENC_IMG))
+$(info ENC_KEY_FILE <-- $(ENC_KEY_FILE))
+$(info ERASED_VALUE <-- $(ERASED_VALUE))
+$(info FAMILY <-- $(FAMILY))
+$(info GCC_PATH <-- $(GCC_PATH))
+$(info HEADER_OFFSET <-- $(HEADER_OFFSET))
+$(info IMGTOOL_PATH <-> $(IMGTOOL_PATH))
+$(info IMG_TYPE <-- $(IMG_TYPE))
+$(info INCLUDE_DIRS_LIBS <-> $(INCLUDE_DIRS_LIBS))
+$(info INCLUDE_DIRS_MBEDTLS_MXCRYPTO <-> $(INCLUDE_DIRS_MBEDTLS_MXCRYPTO))
+$(info MCUBOOT_IMAGE_NUMBER <-- $(MCUBOOT_IMAGE_NUMBER))
+$(info OUT_CFG <-- $(OUT_CFG))
+$(info PDL_CAT_SUFFIX <-> $(PDL_CAT_SUFFIX))
+$(info PLATFORM <-- $(PLATFORM))
+$(info PLATFORM_APP_SOURCES <-> $(PLATFORM_APP_SOURCES))
+$(info PLATFORM_BOOTLOADER_SIZE <-> $(PLATFORM_BOOTLOADER_SIZE))
+$(info PLATFORM_DEFAULT_ERASED_VALUE <-> $(PLATFORM_DEFAULT_ERASED_VALUE))
+$(info PLATFORM_DEFAULT_RAM_SIZE <-> $(PLATFORM_DEFAULT_RAM_SIZE))
+$(info PLATFORM_DEFAULT_RAM_START <-> $(PLATFORM_DEFAULT_RAM_START))
+$(info PLATFORM_DEFAULT_SLOT_SIZE <-> $(PLATFORM_DEFAULT_SLOT_SIZE))
+$(info PLATFORM_DEFAULT_USER_APP_START <-> $(PLATFORM_DEFAULT_USER_APP_START))
+$(info PLATFORM_DEFAULT_PRIMARY_IMG_START <-> $(PLATFORM_DEFAULT_PRIMARY_IMG_START))
+$(info PLATFORM_DEFAULT_USE_OVERWRITE <-> $(PLATFORM_DEFAULT_USE_OVERWRITE))
+$(info PLATFORM_DEFINES <-- $(PLATFORM_DEFINES))
+$(info PLATFORM_EXTERNAL_FLASH_SCRATCH_OFFSET <-> $(PLATFORM_EXTERNAL_FLASH_SCRATCH_OFFSET))
+$(info PLATFORM_EXTERNAL_FLASH_SECONDARY_1_OFFSET <-> $(PLATFORM_EXTERNAL_FLASH_SECONDARY_1_OFFSET))
+$(info PLATFORM_EXTERNAL_FLASH_SECONDARY_2_OFFSET <-> $(PLATFORM_EXTERNAL_FLASH_SECONDARY_2_OFFSET))
+$(info PLATFORM_IMAGE_1_SLOT_SIZE <-> $(PLATFORM_IMAGE_1_SLOT_SIZE))
+$(info PLATFORM_IMAGE_2_SLOT_SIZE <-> $(PLATFORM_IMAGE_2_SLOT_SIZE))
+$(info PLATFORM_INCLUDE_DIRS_FLASH <-> $(PLATFORM_INCLUDE_DIRS_FLASH))
+$(info PLATFORM_INCLUDE_DIRS_HAL_MCUB <-> $(PLATFORM_INCLUDE_DIRS_HAL_MCUB))
+$(info PLATFORM_INCLUDE_DIRS_PDL_STARTUP <-> $(PLATFORM_INCLUDE_DIRS_PDL_STARTUP))
+$(info PLATFORM_INCLUDE_RETARGET_IO_PDL <-> $(PLATFORM_INCLUDE_RETARGET_IO_PDL))
+$(info PLATFORM_SCRATCH_SIZE <-> $(PLATFORM_SCRATCH_SIZE))
+$(info PLATFORM_DEFAULT_IMG_VER_ARG <-> $(PLATFORM_DEFAULT_IMG_VER_ARG))
+$(info PLATFORM_SIGN_ARGS <-> $(PLATFORM_SIGN_ARGS))
+$(info PLATFORM_SOURCES_FLASH <-> $(PLATFORM_SOURCES_FLASH))
+$(info PLATFORM_SOURCES_HAL_MCUB <-> $(PLATFORM_SOURCES_HAL_MCUB))
+$(info PLATFORM_SOURCES_RETARGET_IO_PDL <-> $(PLATFORM_SOURCES_RETARGET_IO_PDL))
+$(info PLATFORM_STARTUP_FILE <-> $(PLATFORM_STARTUP_FILE))
+$(info PLATFORM_SUFFIX <-> $(PLATFORM_SUFFIX))
+$(info PLATFORM_SYSTEM_FILE_NAME <-> $(PLATFORM_SYSTEM_FILE_NAME))
+$(info POST_BUILD_ENABLE <-- $(POST_BUILD_ENABLE))
+$(info PRJ_DIR <-- $(PRJ_DIR))
+$(info PYTHON_PATH <-- $(PYTHON_PATH))
+$(info SIGN_ARGS <-- $(SIGN_ARGS))
+$(info SIGN_KEY_FILE <-- $(SIGN_KEY_FILE))
+$(info SLOT_SIZE <-- $(SLOT_SIZE))
+$(info SOURCES_LIBS <-> $(SOURCES_LIBS))
+$(info SOURCES_MBEDTLS_MXCRYPTO <-> $(SOURCES_MBEDTLS_MXCRYPTO))
+$(info THIS_APP_PATH <-- $(THIS_APP_PATH))
+$(info UPGRADE_SUFFIX <-- $(UPGRADE_SUFFIX))
+$(info UPGRADE_TYPE <-- $(UPGRADE_TYPE))
+$(info USER_APP_START <-- $(USER_APP_START))
+$(info USE_CRYPTO_HW <-> $(USE_CRYPTO_HW))
+$(info USE_CUSTOM_MEMORY_MAP <-> $(USE_CUSTOM_MEMORY_MAP))
+$(info USE_EXTERNAL_FLASH <-> $(USE_EXTERNAL_FLASH))
+$(info USE_OVERWRITE <-- $(USE_OVERWRITE))
+$(info USE_XIP <-- $(USE_XIP))
+endif
diff --git a/boot/cypress/platforms/PSOC6/bsp.h b/boot/cypress/platforms/PSOC6/bsp.h
new file mode 100644
index 0000000..078594f
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/bsp.h
@@ -0,0 +1,79 @@
+/*
+********************************************************************************
+* Copyright 2021 Infineon Technologies AG
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(BSP_H)
+#define BSP_H
+
+#include "custom_debug_uart_cfg.h"
+
+/*https://wiki.sei.cmu.edu/confluence/display/c/PRE05-C.+Understand+macro+replacement+when+concatenating+tokens+or+performing+stringification*/
+#define JOIN(x, y) JOIN_AGAIN(x, y)
+#define JOIN_AGAIN(x, y) x ## y
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/* If this flash is set use user defined HW */
+#if defined(USE_CUSTOM_DEBUG_UART)
+
+#ifndef CUSTOM_UART_HW
+#error "Option USE_CUSTOM_DEBUG_UART turned on, but CUSTOM_UART_HW is undefined \r\n";
+#else
+#define BSP_UART_HW CUSTOM_UART_HW
+#endif /* CUSTOM_UART_HW */
+
+#ifndef CUSTOM_UART_SCB_NUMBER
+#error "Option USE_CUSTOM_DEBUG_UART turned on, but CUSTOM_UART_SCB_NUMBER is undefined \r\n";
+#else
+#define BSP_UART_SCB_NUMBER CUSTOM_UART_SCB_NUMBER
+#endif /* CUSTOM_UART_SCB_NUMBER */
+
+#ifndef CUSTOM_UART_PORT
+#error "Option USE_CUSTOM_DEBUG_UART turned on, but CUSTOM_UART_PORT is undefined \r\n";
+#else
+#define BSP_UART_PORT CUSTOM_UART_PORT
+#endif /* CUSTOM_UART_PORT */
+
+#ifndef CUSTOM_UART_RX_PIN
+#error "Option USE_CUSTOM_DEBUG_UART turned on, but CUSTOM_UART_RX_PIN is undefined \r\n";
+#else
+#define BSP_UART_RX_PIN CUSTOM_UART_RX_PIN
+#endif /* CUSTOM_UART_RX_PIN */
+
+#ifndef CUSTOM_UART_TX_PIN
+#error "Option USE_CUSTOM_DEBUG_UART turned on, but CUSTOM_UART_TX_PIN is undefined \r\n";
+#else
+#define BSP_UART_TX_PIN CUSTOM_UART_TX_PIN
+#endif /* CUSTOM_UART_TX_PIN */
+
+/* Use default HW, which is commonly used on Infineon kits */
+#else
+
+#define BSP_UART_HW SCB5
+#define BSP_UART_SCB_NUMBER 5
+#define BSP_UART_PORT 5
+#define BSP_UART_RX_PIN 0
+#define BSP_UART_TX_PIN 1
+
+#endif /* USE_CUSTOM_DEBUG_UART */
+
+#if defined(__cplusplus)
+}
+#endif
+#endif /* BSP_H */
diff --git a/boot/cypress/platforms/cycfg.c b/boot/cypress/platforms/PSOC6/cycfg.c
similarity index 100%
rename from boot/cypress/platforms/cycfg.c
rename to boot/cypress/platforms/PSOC6/cycfg.c
diff --git a/boot/cypress/platforms/cycfg.h b/boot/cypress/platforms/PSOC6/cycfg.h
similarity index 100%
rename from boot/cypress/platforms/cycfg.h
rename to boot/cypress/platforms/PSOC6/cycfg.h
diff --git a/boot/cypress/platforms/cycfg_clocks.c b/boot/cypress/platforms/PSOC6/cycfg_clocks.c
similarity index 74%
rename from boot/cypress/platforms/cycfg_clocks.c
rename to boot/cypress/platforms/PSOC6/cycfg_clocks.c
index 7f720f7..48c1497 100644
--- a/boot/cypress/platforms/cycfg_clocks.c
+++ b/boot/cypress/platforms/PSOC6/cycfg_clocks.c
@@ -27,21 +27,21 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
- {
- .type = CYHAL_RSC_CLOCK,
- .block_num = CYBSP_CSD_CLK_DIV_HW,
- .channel_num = CYBSP_CSD_CLK_DIV_NUM,
- };
+ const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
+ {
+ .type = CYHAL_RSC_CLOCK,
+ .block_num = CYBSP_CSD_CLK_DIV_HW,
+ .channel_num = CYBSP_CSD_CLK_DIV_NUM,
+ };
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
- Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
- Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
- Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+ (void)Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+ (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+ (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+ cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
}
diff --git a/boot/cypress/platforms/cycfg_clocks.h b/boot/cypress/platforms/PSOC6/cycfg_clocks.h
similarity index 100%
rename from boot/cypress/platforms/cycfg_clocks.h
rename to boot/cypress/platforms/PSOC6/cycfg_clocks.h
diff --git a/boot/cypress/platforms/PSOC6/cycfg_peripherals.c b/boot/cypress/platforms/PSOC6/cycfg_peripherals.c
new file mode 100644
index 0000000..2e423ef
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/cycfg_peripherals.c
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.3.1.1499
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
+const cy_stc_scb_uart_config_t CYBSP_UART_config =
+{
+ .uartMode = CY_SCB_UART_STANDARD,
+ .enableMutliProcessorMode = false,
+ .smartCardRetryOnNack = false,
+ .irdaInvertRx = false,
+ .irdaEnableLowPowerReceiver = false,
+ .oversample = 8,
+ .enableMsbFirst = false,
+ .dataWidth = 8UL,
+ .parity = CY_SCB_UART_PARITY_NONE,
+ .stopBits = CY_SCB_UART_STOP_BITS_1,
+ .enableInputFilter = false,
+ .breakWidth = 11UL,
+ .dropOnFrameError = false,
+ .dropOnParityError = false,
+ .receiverAddress = 0x0UL,
+ .receiverAddressMask = 0x0UL,
+ .acceptAddrInFifo = false,
+ .enableCts = false,
+ .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rtsRxFifoLevel = 0UL,
+ .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+ .rxFifoTriggerLevel = 0UL,
+ .rxFifoIntEnableMask = 0UL,
+ .txFifoTriggerLevel = 63UL,
+ .txFifoIntEnableMask = 0UL,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_UART_obj =
+ {
+ .type = CYHAL_RSC_SCB,
+ .block_num = 5U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_peripherals(void)
+{
+ (void)Cy_SysClk_PeriphAssignDivider(PCLK_SCBx_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&CYBSP_UART_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/cycfg_peripherals.h b/boot/cypress/platforms/PSOC6/cycfg_peripherals.h
similarity index 82%
rename from boot/cypress/platforms/cycfg_peripherals.h
rename to boot/cypress/platforms/PSOC6/cycfg_peripherals.h
index 41a0383..09aabfb 100644
--- a/boot/cypress/platforms/cycfg_peripherals.h
+++ b/boot/cypress/platforms/PSOC6/cycfg_peripherals.h
@@ -31,20 +31,23 @@
#include "cy_scb_uart.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
- #include "cyhal_hwmgr.h"
+ #include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
+#include "bsp.h"
+
#if defined(__cplusplus)
extern "C" {
#endif
-#define CYBSP_UART_ENABLED 1U
-#define CYBSP_UART_HW SCB5
-#define CYBSP_UART_IRQ scb_5_interrupt_IRQn
+#define CYBSP_UART_ENABLED 1U
+#define CYBSP_UART_HW BSP_UART_HW
+#define CYBSP_UART_IRQ JOIN(JOIN(scb_, USE_UART_SCB_NUMBER), _interrupt_IRQn)
+#define PCLK_SCBx_CLOCK JOIN(JOIN(PCLK_SCB, BSP_UART_SCB_NUMBER), _CLOCK)
extern const cy_stc_scb_uart_config_t CYBSP_UART_config;
#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t CYBSP_UART_obj;
+ extern const cyhal_resource_inst_t CYBSP_UART_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);
diff --git a/boot/cypress/platforms/PSOC6/cycfg_pins.c b/boot/cypress/platforms/PSOC6/cycfg_pins.c
new file mode 100644
index 0000000..e29a86c
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/cycfg_pins.c
@@ -0,0 +1,89 @@
+/*******************************************************************************
+* File Name: cycfg_pins.c
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.3.1.1499
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_pins.h"
+
+const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_HIGHZ,
+ .hsiom = CYBSP_UART_RX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_UART_RX_obj =
+ {
+ .type = CYHAL_RSC_GPIO,
+ .block_num = CYBSP_UART_RX_PORT_NUM,
+ .channel_num = CYBSP_UART_RX_PIN,
+ };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = CYBSP_UART_TX_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t CYBSP_UART_TX_obj =
+ {
+ .type = CYHAL_RSC_GPIO,
+ .block_num = CYBSP_UART_TX_PORT_NUM,
+ .channel_num = CYBSP_UART_TX_PIN,
+ };
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void)
+{
+ (void)Cy_GPIO_Pin_Init(CYBSP_UART_RX_PORT, CYBSP_UART_RX_PIN, &CYBSP_UART_RX_config);
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&CYBSP_UART_RX_obj);
+#endif //defined (CY_USING_HAL)
+
+ (void)Cy_GPIO_Pin_Init(CYBSP_UART_TX_PORT, CYBSP_UART_TX_PIN, &CYBSP_UART_TX_config);
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&CYBSP_UART_TX_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/PSOC6/cycfg_pins.h b/boot/cypress/platforms/PSOC6/cycfg_pins.h
new file mode 100644
index 0000000..e844400
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/cycfg_pins.h
@@ -0,0 +1,116 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../psoc6pdl): 1.3.1.1499
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+ #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#include "bsp.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_UART_RX_ENABLED 1U
+#define CYBSP_UART_RX_PORT JOIN(GPIO_PRT, BSP_UART_PORT)
+#define CYBSP_UART_RX_PORT_NUM BSP_UART_PORT
+#define CYBSP_UART_RX_PIN BSP_UART_RX_PIN
+#define CYBSP_UART_RX_NUM BSP_UART_RX_PIN
+#define CYBSP_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_UART_RX_INIT_DRIVESTATE 1U
+/*#ifndef ioss_0_port_10_pin_0_HSIOM
+ #define ioss_0_port_10_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif*/
+
+#define CYBSP_UART_RX_HSIOM ioss_port_pin_rx_HSIOM
+#define CYBSP_UART_RX_IRQ JOIN(JOIN(ioss_interrupts_gpio_, BSP_UART_PORT), _IRQn)
+
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_RX_HAL_PORT_PIN JOIN(JOIN(JOIN(P, BSP_UART_PORT), _), BSP_UART_RX_PIN)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_UART_TX_ENABLED 1U
+#define CYBSP_UART_TX_PORT JOIN(GPIO_PRT, BSP_UART_PORT)
+#define CYBSP_UART_TX_PORT_NUM BSP_UART_PORT
+#define CYBSP_UART_TX_PIN BSP_UART_TX_PIN
+#define CYBSP_UART_TX_NUM BSP_UART_TX_PIN
+#define CYBSP_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_UART_TX_INIT_DRIVESTATE 1
+/*#ifndef ioss_0_port_10_pin_1_HSIOM
+ #define ioss_0_port_10_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif*/
+#define CYBSP_UART_TX_HSIOM ioss_port_pin_tx_HSIOM
+#define CYBSP_UART_TX_IRQ JOIN(JOIN(ioss_interrupts_gpio_, BSP_UART_PORT), _IRQn)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_TX_HAL_PORT_PIN JOIN(JOIN(JOIN(P, BSP_UART_PORT), _), BSP_UART_TX_PIN)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ #define CYBSP_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config;
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_UART_RX_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config;
+#if defined (CY_USING_HAL)
+ extern const cyhal_resource_inst_t CYBSP_UART_TX_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/boot/cypress/platforms/cycfg_routing.c b/boot/cypress/platforms/PSOC6/cycfg_routing.c
similarity index 100%
rename from boot/cypress/platforms/cycfg_routing.c
rename to boot/cypress/platforms/PSOC6/cycfg_routing.c
diff --git a/boot/cypress/platforms/cycfg_routing.h b/boot/cypress/platforms/PSOC6/cycfg_routing.h
similarity index 82%
rename from boot/cypress/platforms/cycfg_routing.h
rename to boot/cypress/platforms/PSOC6/cycfg_routing.h
index bfb2998..41c6c60 100644
--- a/boot/cypress/platforms/cycfg_routing.h
+++ b/boot/cypress/platforms/PSOC6/cycfg_routing.h
@@ -27,6 +27,8 @@
#if !defined(CYCFG_ROUTING_H)
#define CYCFG_ROUTING_H
+#include "bsp.h"
+
#if defined(__cplusplus)
extern "C" {
#endif
@@ -35,8 +37,8 @@
#define init_cycfg_connectivity() init_cycfg_routing()
-#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
-#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
+#define ioss_port_pin_rx_HSIOM JOIN(JOIN(JOIN(JOIN(JOIN(JOIN(P, BSP_UART_PORT), _), BSP_UART_RX_PIN), _SCB), BSP_UART_SCB_NUMBER), _UART_RX)
+#define ioss_port_pin_tx_HSIOM JOIN(JOIN(JOIN(JOIN(JOIN(JOIN(P, BSP_UART_PORT), _), BSP_UART_TX_PIN), _SCB), BSP_UART_SCB_NUMBER), _UART_TX)
#if defined(__cplusplus)
}
diff --git a/boot/cypress/platforms/PSOC6/cycfg_system.c b/boot/cypress/platforms/PSOC6/cycfg_system.c
new file mode 100644
index 0000000..cf3f4e7
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/cycfg_system.c
@@ -0,0 +1,540 @@
+/*******************************************************************************
+* File Name: cycfg_system.c
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Device Configurator: 2.0.0.1483
+* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
+*
+********************************************************************************
+* Copyright 2017-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_system.h"
+
+#define CY_CFG_SYSCLK_ECO_ERROR 1
+#define CY_CFG_SYSCLK_ALTHF_ERROR 2
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+#define CY_CFG_SYSCLK_FLL_ERROR 4
+#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_ILO_ENABLED 1
+#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_ENABLED 1
+#define CY_CFG_SYSCLK_PLL1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
+#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
+#define CY_CFG_SYSCLK_WCO_ENABLED 1
+
+void cycfg_ClockStartupError(uint32_t error);
+
+static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
+{
+ .fllMult = 500U,
+ .refDiv = 20U,
+ .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
+ .enableOutputDiv = true,
+ .lockTolerance = 10U,
+ .igain = 9U,
+ .pgain = 5U,
+ .settlingCount = 8U,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+ .cco_Freq = 355U,
+};
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 0U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 1U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+ const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
+ {
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 2U,
+ .channel_num = 0U,
+ };
+#endif //defined (CY_USING_HAL)
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
+{
+ .feedbackDiv = 36,
+ .referenceDiv = 1,
+ .outputDiv = 2,
+ .lfMode = false,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
+{
+ .feedbackDiv = 30,
+ .referenceDiv = 1,
+ .outputDiv = 5,
+ .lfMode = false,
+ .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+};
+
+__WEAK void cycfg_ClockStartupError(uint32_t error)
+{
+ (void)error; /* Suppress the compiler warning */
+ while (true) {}
+}
+__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit(void)
+{
+ Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
+}
+__STATIC_INLINE void Cy_SysClk_ClkBakInit(void)
+{
+ Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+}
+__STATIC_INLINE void Cy_SysClk_ClkFastInit(void)
+{
+ Cy_SysClk_ClkFastSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_FllInit(void)
+{
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+ }
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf0Init(void)
+{
+ (void)Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+ (void)Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf2Init(void)
+{
+ (void)Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+ (void)Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+ (void)Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf3Init(void)
+{
+ (void)Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+ (void)Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ (void)Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf4Init(void)
+{
+ (void)Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
+ (void)Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ (void)Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
+}
+__STATIC_INLINE void Cy_SysClk_IloInit(void)
+{
+ /* The WDT is unlocked in the default startup code */
+ Cy_SysClk_IloEnable();
+ Cy_SysClk_IloHibernateOn(true);
+}
+__STATIC_INLINE void Cy_SysClk_ClkLfInit(void)
+{
+ /* The WDT is unlocked in the default startup code */
+ Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath0Init(void)
+{
+ (void)Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath1Init(void)
+{
+ (void)Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath2Init(void)
+{
+ (void)Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPeriInit(void)
+{
+ Cy_SysClk_ClkPeriSetDivider(1U);
+}
+__STATIC_INLINE void Cy_SysClk_Pll0Init(void)
+{
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+}
+__STATIC_INLINE void Cy_SysClk_Pll1Init(void)
+{
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+ }
+}
+__STATIC_INLINE void Cy_SysClk_ClkSlowInit(void)
+{
+ Cy_SysClk_ClkSlowSetDivider(0U);
+}
+__STATIC_INLINE void Cy_SysClk_ClkTimerInit(void)
+{
+ Cy_SysClk_ClkTimerDisable();
+ Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
+ Cy_SysClk_ClkTimerSetDivider(0U);
+ Cy_SysClk_ClkTimerEnable();
+}
+__STATIC_INLINE void Cy_SysClk_WcoInit(void)
+{
+ (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+ (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+ if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
+ {
+ cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
+ }
+}
+
+
+void init_cycfg_system(void)
+{
+ /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
+ Cy_SysLib_SetWaitStates(false, 150UL);
+ #ifdef CY_CFG_PWR_ENABLED
+ #ifdef CY_CFG_PWR_INIT
+ init_cycfg_power();
+ #else
+ #warning Power system will not be configured. Update power personality to v1.20 or later.
+ #endif /* CY_CFG_PWR_INIT */
+ #endif /* CY_CFG_PWR_ENABLED */
+
+ /* Reset the core clock path to default and disable all the FLLs/PLLs */
+ (void)Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkFastSetDivider(0U);
+ Cy_SysClk_ClkPeriSetDivider(1U);
+ Cy_SysClk_ClkSlowSetDivider(0U);
+ for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+ {
+ (void)Cy_SysClk_PllDisable(pll);
+ }
+ (void)Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
+
+ if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
+ (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
+ {
+ (void)Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ }
+
+ (void)Cy_SysClk_FllDisable();
+ (void)Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
+ (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+ #ifdef CY_IP_MXBLESS
+ (void)Cy_BLE_EcoReset();
+ #endif
+
+
+ /* Enable all source clocks */
+ #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+ Cy_SysClk_PiloInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+ Cy_SysClk_WcoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+ Cy_SysClk_ClkLfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+ Cy_SysClk_AltHfInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+ Cy_SysClk_EcoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+ Cy_SysClk_ExtClkInit();
+ #endif
+
+ /* Configure CPU clock dividers */
+ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+ Cy_SysClk_ClkFastInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+ Cy_SysClk_ClkPeriInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+ Cy_SysClk_ClkSlowInit();
+ #endif
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+ /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
+ (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
+ (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ #else
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #endif
+
+ /* Configure Path Clocks */
+ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+ Cy_SysClk_ClkPath0Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+ Cy_SysClk_ClkPath2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+ Cy_SysClk_ClkPath3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+ Cy_SysClk_ClkPath4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+ Cy_SysClk_ClkPath5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+ Cy_SysClk_ClkPath6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+ Cy_SysClk_ClkPath7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+ Cy_SysClk_ClkPath8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+ Cy_SysClk_ClkPath9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+ Cy_SysClk_ClkPath10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+ Cy_SysClk_ClkPath11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+ Cy_SysClk_ClkPath12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+ Cy_SysClk_ClkPath13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+ Cy_SysClk_ClkPath14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+ Cy_SysClk_ClkPath15Init();
+ #endif
+
+ /* Configure and enable FLL */
+ #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+ Cy_SysClk_FllInit();
+ #endif
+
+ Cy_SysClk_ClkHf0Init();
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ /* Apply the ClkPath1 user setting */
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #endif
+
+
+ /* Configure and enable PLLs */
+ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+ Cy_SysClk_Pll0Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+ Cy_SysClk_Pll1Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
+ Cy_SysClk_Pll2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
+ Cy_SysClk_Pll3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
+ Cy_SysClk_Pll4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
+ Cy_SysClk_Pll5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
+ Cy_SysClk_Pll6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
+ Cy_SysClk_Pll7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
+ Cy_SysClk_Pll8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
+ Cy_SysClk_Pll9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
+ Cy_SysClk_Pll10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
+ Cy_SysClk_Pll11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
+ Cy_SysClk_Pll12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
+ Cy_SysClk_Pll13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
+ Cy_SysClk_Pll14Init();
+ #endif
+
+ /* Configure HF clocks */
+ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+ Cy_SysClk_ClkHf1Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+ Cy_SysClk_ClkHf2Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+ Cy_SysClk_ClkHf3Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+ Cy_SysClk_ClkHf4Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+ Cy_SysClk_ClkHf5Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+ Cy_SysClk_ClkHf6Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+ Cy_SysClk_ClkHf7Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+ Cy_SysClk_ClkHf8Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+ Cy_SysClk_ClkHf9Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+ Cy_SysClk_ClkHf10Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+ Cy_SysClk_ClkHf11Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+ Cy_SysClk_ClkHf12Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+ Cy_SysClk_ClkHf13Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+ Cy_SysClk_ClkHf14Init();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+ Cy_SysClk_ClkHf15Init();
+ #endif
+
+ /* Configure miscellaneous clocks */
+ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+ Cy_SysClk_ClkTimerInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+ Cy_SysClk_ClkAltSysTickInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+ Cy_SysClk_ClkPumpInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+ Cy_SysClk_ClkBakInit();
+ #endif
+
+ /* Configure default enabled clocks */
+ #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+ Cy_SysClk_IloInit();
+ #else
+ Cy_SysClk_IloDisable();
+ #endif
+
+ #ifndef CY_CFG_SYSCLK_IMO_ENABLED
+ #error the IMO must be enabled for proper chip operation
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+ Cy_SysClk_MfoInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+ Cy_SysClk_ClkMfInit();
+ #endif
+
+ /* Set accurate flash wait states */
+ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
+ Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+ #endif
+
+ /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+ SystemCoreClockUpdate();
+
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/cycfg_system.h b/boot/cypress/platforms/PSOC6/cycfg_system.h
similarity index 100%
rename from boot/cypress/platforms/cycfg_system.h
rename to boot/cypress/platforms/PSOC6/cycfg_system.h
diff --git a/boot/cypress/platforms/PSOC6/img_confirm/set_img_ok.c b/boot/cypress/platforms/PSOC6/img_confirm/set_img_ok.c
new file mode 100644
index 0000000..220f86c
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/img_confirm/set_img_ok.c
@@ -0,0 +1,239 @@
+/********************************************************************************
+* Copyright 2021 Infineon Technologies AG
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
+
+#include "set_img_ok.h"
+
+static uint8_t row_buff[FLASH_ROW_BUF_SZ];
+
+#ifndef USE_XIP
+
+/**
+ * @brief Function reads value of img_ok flag from address.
+ *
+ * @param address - address of img_ok flag in primary img trailer
+ * @return int - value at address
+ */
+static int read_img_ok_value(uint32_t address)
+{
+ return *(volatile uint8_t *)address;
+}
+
+/**
+ * @brief Function sets img_ok flag value to primary image trailer.
+ *
+ * @param address - address of img_ok flag in primary img trailer
+ * @param value - value corresponding to img_ok set
+ *
+ * @return - operation status. 0 - set succesfully, -1 - failed to set.
+ */
+static int write_img_ok_value(uint32_t address, uint8_t value)
+{
+ int rc = -1;
+ uint32_t row_addr = 0;
+
+ uint32_t row_mask = CY_FLASH_SIZEOF_ROW /* is a power of 2 */ - 1u;
+ cy_en_flashdrv_status_t st;
+
+ /* Accepting an arbitrary address */
+ row_addr = address & ~row_mask;
+
+ /* Preserving the row */
+ (void)memcpy(row_buff, (void *)row_addr, sizeof(row_buff));
+
+ /* Modifying the target byte */
+ row_buff[address & row_mask] = value;
+
+ /* Programming the updated row back */
+ st = Cy_Flash_WriteRow(row_addr, (const uint32_t *)row_buff);
+
+ if (CY_FLASH_DRV_SUCCESS == st) {
+ rc = 0;
+ }
+
+ return rc;
+}
+
+#else
+
+extern cy_stc_smif_block_config_t smifBlockConfig_sfdp;
+extern cy_stc_smif_mem_config_t *mems_sfdp[1];
+extern cy_stc_smif_mem_config_t mem_sfdp_0;
+extern cy_stc_smif_mem_device_cfg_t dev_sfdp_0;
+
+/**
+ * @brief Function sets img_ok value to primary slot trailer
+ * when application is executed from external memory
+ * in XIP mode. This function is executed from RAM since
+ * it reconfigures SMIF block from XIP to MMIO mode, then
+ * writes img_ok set value and switches back to XIP mode.
+ *
+ * @param address - address of img_ok flag in primary img trailer
+ * @param value - value corresponding to img_ok set
+ *
+ * @return - operation status. 1 - already set, 0 - set succesfully,
+ * -1 - failed to set.
+ */
+CY_RAMFUNC_BEGIN
+static int set_img_ok_ram(uint32_t address, uint8_t value)
+{
+ int32_t rc = IMG_OK_SET_FAILED;
+ uint32_t try_count = 10U;
+
+ cy_en_smif_status_t stat = CY_SMIF_BUSY;
+ SMIF_Type *QSPIPort = SMIF0;
+ cy_stc_smif_context_t QSPI_context;
+ cy_en_smif_mode_t mode = CY_SMIF_NORMAL;
+
+ Cy_SMIF_SetMode(SMIF0, CY_SMIF_NORMAL);
+ mode = Cy_SMIF_GetMode(QSPIPort);
+
+ if (mode != CY_SMIF_NORMAL) {
+ CY_HALT();
+ }
+
+ for (try_count = 0U; try_count < 10U; try_count++) {
+
+ stat = Cy_SMIF_MemInit(QSPIPort, &smifBlockConfig_sfdp, &QSPI_context);
+
+ if (CY_SMIF_SUCCESS == stat) {
+ break;
+ }
+
+ Cy_SysLib_Delay(500U);
+ }
+
+ if (stat == CY_SMIF_SUCCESS) {
+
+ cy_stc_smif_mem_config_t *cfg = smifBlockConfig_sfdp.memConfig[0];
+ /* Determine row start address, where image trailer is allocated */
+ uint32_t erase_len = cfg->deviceCfg->eraseSize;
+ uint32_t row_mask = erase_len /* is a power of two */ - 1u;
+ uint32_t row_addr = (address - CY_XIP_BASE) & ~row_mask;
+ /* Determine start address of image trailer
+ * The minimum erase size area is allocated
+ * for trailer, but reading the whole area is
+ * not nessesary since data is only located at
+ * first 0x200 bytes. Trailer size is taken as 0x200
+ * to keep consistency with internal memory
+ * implementation, where min_erase_size is 0x200
+ */
+ uint32_t img_trailer_addr = address - CY_XIP_BASE + USER_SWAP_IMAGE_OK_OFFS - IMG_TRAILER_SZ;
+ uint32_t img_ok_mask = FLASH_ROW_BUF_SZ /* is a power of 2 */ - 1u;
+
+ cy_en_smif_status_t st = Cy_SMIF_MemRead(QSPIPort, cfg,
+ img_trailer_addr, row_buff, FLASH_ROW_BUF_SZ,
+ &QSPI_context);
+
+ if (CY_SMIF_SUCCESS == st) {
+
+ if (row_buff[address & img_ok_mask] != value) {
+
+ row_buff[address & img_ok_mask] = value;
+
+ /* Programming the updated block back */
+ st = Cy_SMIF_MemEraseSector(QSPIPort, cfg,
+ row_addr, erase_len,
+ &QSPI_context);
+
+ if (CY_SMIF_SUCCESS == st) {
+ st = Cy_SMIF_MemWrite(QSPIPort, cfg,
+ img_trailer_addr, row_buff, FLASH_ROW_BUF_SZ,
+ &QSPI_context);
+ if (CY_SMIF_SUCCESS == st) {
+ rc = IMG_OK_SET_SUCCESS;
+ }
+ }
+ else {
+ rc = IMG_OK_SET_FAILED;
+ }
+ }
+ else {
+ rc = IMG_OK_ALREADY_SET;
+ }
+ }
+ else {
+ rc = IMG_OK_SET_FAILED;
+ }
+
+ stat = Cy_SMIF_CacheEnable(QSPIPort, CY_SMIF_CACHE_FAST);
+
+ if (CY_SMIF_SUCCESS == stat) {
+ Cy_SMIF_SetMode(QSPIPort, CY_SMIF_MEMORY);
+ mode = Cy_SMIF_GetMode(QSPIPort);
+
+ if (mode != CY_SMIF_MEMORY) {
+ CY_HALT();
+ }
+ }
+ }
+ else {
+ /* do nothing */
+ }
+
+ return rc;
+}
+CY_RAMFUNC_END
+
+#endif /* USE_XIP */
+
+/**
+ * @brief Public function to confirm that upgraded application is operable
+ * after swap. Should be called from main code of user application.
+ * It sets mcuboot flag img_ok in primary (boot) image trailer.
+ * MCUBootApp checks img_ok flag at first reset after upgrade and
+ * validates successful swap.
+ *
+ * @param address - address of img_ok flag in primary img trailer
+ * @param value - value corresponding to img_ok set
+ *
+ * @return - operation status. 1 - already set, 0 - set succesfully,
+ * -1 - failed to set.
+ */
+int set_img_ok(uint32_t address, uint8_t value)
+{
+ int32_t rc = -1;
+
+ /* Write Image OK flag to the slot trailer, so MCUBoot-loader
+ * will not revert new image
+ */
+#ifdef USE_XIP
+ /*
+ * When switching from XIP execution mode to RAM function
+ * it is required to clear and disable SMIF cache. set_img_ok_ram
+ * is then turns cache on before return. If it is not done - return
+ * to execution from RAM to XIP hangs indefinitely.
+ */
+ Cy_SMIF_CacheDisable(SMIF0, CY_SMIF_CACHE_FAST);
+ Cy_SMIF_CacheInvalidate(SMIF0, CY_SMIF_CACHE_FAST);
+ rc = set_img_ok_ram(address, value);
+
+#else
+
+ if (read_img_ok_value(address) != value) {
+ rc = write_img_ok_value(address, value);
+ }
+ else {
+ rc = IMG_OK_ALREADY_SET;
+ }
+#endif /* USE_XIP */
+
+ return rc;
+}
+
+#endif /* !(SWAP_DISABLED) && defined(UPGRADE_IMAGE) */
diff --git a/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.c b/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.c
new file mode 100644
index 0000000..c918656
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2021 Infineon Technologies AG
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdint.h>
+
+#include "sysflash/sysflash.h"
+#include "bootutil/bootutil_log.h"
+
+#include "cy_security_cnt_platform.h"
+
+#if defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT
+
+/*
+ * Reads a data corresponding to security counter which is stored in
+ * efuses of chip and converts it actual value of security conter
+ *
+ * @param security_cnt Pointer to a variable, where security conter value would be stored
+ *
+ * @return FIH_SUCESS on success; FIH_FAILURE on failure.
+ */
+fih_int platform_security_counter_get(fih_uint *security_cnt) {
+
+ (void)security_cnt;
+
+ BOOT_LOG_ERR("Hardware security conter is not supported on PSOC6 platform.");
+
+ FIH_RET(FIH_FAILURE);
+}
+
+/**
+ * Updates the stored value of a given image's security counter with a new
+ * security counter value if the new one is greater.
+ *
+ * @param reprov_packet Pointer to a reprovisioning packet containing NV counter.
+ * @param packet_len Length of a packet
+ * @param img_security_cnt Security conter value of image
+ *
+ * @return 0 on success; nonzero on failure.
+ */
+int32_t platform_security_counter_update(uint32_t img_security_cnt, void * custom_data)
+{
+ (void)img_security_cnt;
+ (void)custom_data;
+
+ BOOT_LOG_ERR("Hardware security conter is not supported on PSOC6 platform.");
+
+ return -1;
+}
+
+#endif /* defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.h b/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.h
new file mode 100644
index 0000000..b7cca56
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2020 Arm Limited.
+ * Copyright (c) 2021 Infineon Technologies AG
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef CY_SECURITY_CNT_PLATFORM_H
+#define CY_SECURITY_CNT_PLATFORM_H
+
+#ifdef PSOC6
+
+#include "bootutil/fault_injection_hardening.h"
+
+/**
+ * Reads a data corresponding to security counter which is stored in
+ * efuses of chip and converts it actual value of security conter
+ *
+ * @param security_cnt Pointer to a variable, where security conter value would be stored
+ *
+ * @return FIH_SUCESS on success; FIH_FAILURE on failure.
+ */
+fih_int platform_security_counter_get(fih_uint *security_cnt);
+
+/**
+ * Updates the stored value of a given image's security counter with a new
+ * security counter value if the new one is greater.
+ *
+ * @param reprov_packet Pointer to a reprovisioning packet containing NV counter.
+ * @param packet_len Length of a packet
+ * @param img_security_cnt Security conter value of image
+ *
+ * @return 0 on success; nonzero on failure.
+ */
+int32_t platform_security_counter_update(uint32_t img_security_cnt, void * custom_data);
+#endif /* PSOC6 */
+
+#endif /* CY_SECURITY_CNT_PLATFORM_H */
\ No newline at end of file
diff --git a/boot/cypress/platforms/cycfg_peripherals.c b/boot/cypress/platforms/cycfg_peripherals.c
deleted file mode 100644
index 1c55938..0000000
--- a/boot/cypress/platforms/cycfg_peripherals.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_peripherals.c
-*
-* Description:
-* Peripheral Hardware Block configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.3.1.1499
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_peripherals.h"
-
-const cy_stc_scb_uart_config_t CYBSP_UART_config =
-{
- .uartMode = CY_SCB_UART_STANDARD,
- .enableMutliProcessorMode = false,
- .smartCardRetryOnNack = false,
- .irdaInvertRx = false,
- .irdaEnableLowPowerReceiver = false,
- .oversample = 8,
- .enableMsbFirst = false,
- .dataWidth = 8UL,
- .parity = CY_SCB_UART_PARITY_NONE,
- .stopBits = CY_SCB_UART_STOP_BITS_1,
- .enableInputFilter = false,
- .breakWidth = 11UL,
- .dropOnFrameError = false,
- .dropOnParityError = false,
- .receiverAddress = 0x0UL,
- .receiverAddressMask = 0x0UL,
- .acceptAddrInFifo = false,
- .enableCts = false,
- .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
- .rtsRxFifoLevel = 0UL,
- .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
- .rxFifoTriggerLevel = 0UL,
- .rxFifoIntEnableMask = 0UL,
- .txFifoTriggerLevel = 63UL,
- .txFifoIntEnableMask = 0UL,
-};
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t CYBSP_UART_obj =
- {
- .type = CYHAL_RSC_SCB,
- .block_num = 5U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
-
-
-void init_cycfg_peripherals(void)
-{
- Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
-#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&CYBSP_UART_obj);
-#endif //defined (CY_USING_HAL)
-}
diff --git a/boot/cypress/platforms/cycfg_pins.c b/boot/cypress/platforms/cycfg_pins.c
deleted file mode 100644
index 771d772..0000000
--- a/boot/cypress/platforms/cycfg_pins.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.c
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.3.1.1499
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_pins.h"
-
-const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_HIGHZ,
- .hsiom = CYBSP_UART_RX_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_1_2,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t CYBSP_UART_RX_obj =
- {
- .type = CYHAL_RSC_GPIO,
- .block_num = CYBSP_UART_RX_PORT_NUM,
- .channel_num = CYBSP_UART_RX_PIN,
- };
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = CYBSP_UART_TX_HSIOM,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_1_2,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t CYBSP_UART_TX_obj =
- {
- .type = CYHAL_RSC_GPIO,
- .block_num = CYBSP_UART_TX_PORT_NUM,
- .channel_num = CYBSP_UART_TX_PIN,
- };
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_pins(void)
-{
- Cy_GPIO_Pin_Init(CYBSP_UART_RX_PORT, CYBSP_UART_RX_PIN, &CYBSP_UART_RX_config);
-#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&CYBSP_UART_RX_obj);
-#endif //defined (CY_USING_HAL)
-
- Cy_GPIO_Pin_Init(CYBSP_UART_TX_PORT, CYBSP_UART_TX_PIN, &CYBSP_UART_TX_config);
-#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&CYBSP_UART_TX_obj);
-#endif //defined (CY_USING_HAL)
-}
diff --git a/boot/cypress/platforms/cycfg_pins.h b/boot/cypress/platforms/cycfg_pins.h
deleted file mode 100644
index c214826..0000000
--- a/boot/cypress/platforms/cycfg_pins.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.3.1.1499
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cy_gpio.h"
-#if defined (CY_USING_HAL)
- #include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_UART_RX_ENABLED 1U
-#define CYBSP_UART_RX_PORT GPIO_PRT5
-#define CYBSP_UART_RX_PORT_NUM 5U
-#define CYBSP_UART_RX_PIN 0U
-#define CYBSP_UART_RX_NUM 0U
-#define CYBSP_UART_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
-#define CYBSP_UART_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_0_HSIOM
- #define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_UART_RX_HSIOM ioss_0_port_5_pin_0_HSIOM
-#define CYBSP_UART_RX_IRQ ioss_interrupts_gpio_5_IRQn
-#if defined (CY_USING_HAL)
- #define CYBSP_UART_RX_HAL_PORT_PIN P5_0
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_UART_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_UART_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_UART_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_NONE
-#endif //defined (CY_USING_HAL)
-#define CYBSP_UART_TX_ENABLED 1U
-#define CYBSP_UART_TX_PORT GPIO_PRT5
-#define CYBSP_UART_TX_PORT_NUM 5U
-#define CYBSP_UART_TX_PIN 1U
-#define CYBSP_UART_TX_NUM 1U
-#define CYBSP_UART_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_UART_TX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_5_pin_1_HSIOM
- #define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_UART_TX_HSIOM ioss_0_port_5_pin_1_HSIOM
-#define CYBSP_UART_TX_IRQ ioss_interrupts_gpio_5_IRQn
-#if defined (CY_USING_HAL)
- #define CYBSP_UART_TX_HAL_PORT_PIN P5_1
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_UART_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_UART_TX_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- #define CYBSP_UART_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
-#endif //defined (CY_USING_HAL)
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_UART_RX_config;
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t CYBSP_UART_RX_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_UART_TX_config;
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t CYBSP_UART_TX_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */
diff --git a/boot/cypress/platforms/cycfg_system.c b/boot/cypress/platforms/cycfg_system.c
deleted file mode 100644
index 57ab013..0000000
--- a/boot/cypress/platforms/cycfg_system.c
+++ /dev/null
@@ -1,537 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_system.c
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_system.h"
-
-#define CY_CFG_SYSCLK_ECO_ERROR 1
-#define CY_CFG_SYSCLK_ALTHF_ERROR 2
-#define CY_CFG_SYSCLK_PLL_ERROR 3
-#define CY_CFG_SYSCLK_FLL_ERROR 4
-#define CY_CFG_SYSCLK_WCO_ERROR 5
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
-#define CY_CFG_SYSCLK_FLL_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
-#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_ILO_ENABLED 1
-#define CY_CFG_SYSCLK_IMO_ENABLED 1
-#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
-#define CY_CFG_SYSCLK_PLL0_ENABLED 1
-#define CY_CFG_SYSCLK_PLL1_ENABLED 1
-#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
-#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
-#define CY_CFG_SYSCLK_WCO_ENABLED 1
-
-static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
-{
- .fllMult = 500U,
- .refDiv = 20U,
- .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
- .enableOutputDiv = true,
- .lockTolerance = 10U,
- .igain = 9U,
- .pgain = 5U,
- .settlingCount = 8U,
- .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
- .cco_Freq = 355U,
-};
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 0U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 1U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 2U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
-{
- .feedbackDiv = 36,
- .referenceDiv = 1,
- .outputDiv = 2,
- .lfMode = false,
- .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-};
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
-{
- .feedbackDiv = 30,
- .referenceDiv = 1,
- .outputDiv = 5,
- .lfMode = false,
- .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-};
-
-__WEAK void cycfg_ClockStartupError(uint32_t error)
-{
- (void)error; /* Suppress the compiler warning */
- while(1);
-}
-__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
-{
- Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
-}
-__STATIC_INLINE void Cy_SysClk_ClkBakInit()
-{
- Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
-}
-__STATIC_INLINE void Cy_SysClk_ClkFastInit()
-{
- Cy_SysClk_ClkFastSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_FllInit()
-{
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
- {
- cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
- }
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
- {
- cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
- }
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
-{
- Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
-{
- Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
- Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
-{
- Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
- Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
-{
- Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
- Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
- Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
-}
-__STATIC_INLINE void Cy_SysClk_IloInit()
-{
- /* The WDT is unlocked in the default startup code */
- Cy_SysClk_IloEnable();
- Cy_SysClk_IloHibernateOn(true);
-}
-__STATIC_INLINE void Cy_SysClk_ClkLfInit()
-{
- /* The WDT is unlocked in the default startup code */
- Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
-{
- Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
-{
- Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
-{
- Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
-{
- Cy_SysClk_ClkPeriSetDivider(1U);
-}
-__STATIC_INLINE void Cy_SysClk_Pll0Init()
-{
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
- {
- cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
- }
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
- {
- cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
- }
-}
-__STATIC_INLINE void Cy_SysClk_Pll1Init()
-{
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
- {
- cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
- }
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
- {
- cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
- }
-}
-__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
-{
- Cy_SysClk_ClkSlowSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
-{
- Cy_SysClk_ClkTimerDisable();
- Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
- Cy_SysClk_ClkTimerSetDivider(0U);
- Cy_SysClk_ClkTimerEnable();
-}
-__STATIC_INLINE void Cy_SysClk_WcoInit()
-{
- (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
- (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
- {
- cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
- }
-}
-
-
-void init_cycfg_system(void)
-{
- /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
- Cy_SysLib_SetWaitStates(false, 150UL);
- #ifdef CY_CFG_PWR_ENABLED
- #ifdef CY_CFG_PWR_INIT
- init_cycfg_power();
- #else
- #warning Power system will not be configured. Update power personality to v1.20 or later.
- #endif /* CY_CFG_PWR_INIT */
- #endif /* CY_CFG_PWR_ENABLED */
-
- /* Reset the core clock path to default and disable all the FLLs/PLLs */
- Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
- Cy_SysClk_ClkFastSetDivider(0U);
- Cy_SysClk_ClkPeriSetDivider(1U);
- Cy_SysClk_ClkSlowSetDivider(0U);
- for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
- {
- (void)Cy_SysClk_PllDisable(pll);
- }
- Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
-
- if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
- (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
- {
- Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
- }
-
- Cy_SysClk_FllDisable();
- Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
- Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
- #ifdef CY_IP_MXBLESS
- (void)Cy_BLE_EcoReset();
- #endif
-
-
- /* Enable all source clocks */
- #ifdef CY_CFG_SYSCLK_PILO_ENABLED
- Cy_SysClk_PiloInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_WCO_ENABLED
- Cy_SysClk_WcoInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
- Cy_SysClk_ClkLfInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
- Cy_SysClk_AltHfInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_ECO_ENABLED
- Cy_SysClk_EcoInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
- Cy_SysClk_ExtClkInit();
- #endif
-
- /* Configure CPU clock dividers */
- #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
- Cy_SysClk_ClkFastInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
- Cy_SysClk_ClkPeriInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
- Cy_SysClk_ClkSlowInit();
- #endif
-
- #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
- /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
- Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
- Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
- #else
- #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
- Cy_SysClk_ClkPath1Init();
- #endif
- #endif
-
- /* Configure Path Clocks */
- #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
- Cy_SysClk_ClkPath0Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
- Cy_SysClk_ClkPath2Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
- Cy_SysClk_ClkPath3Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
- Cy_SysClk_ClkPath4Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
- Cy_SysClk_ClkPath5Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
- Cy_SysClk_ClkPath6Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
- Cy_SysClk_ClkPath7Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
- Cy_SysClk_ClkPath8Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
- Cy_SysClk_ClkPath9Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
- Cy_SysClk_ClkPath10Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
- Cy_SysClk_ClkPath11Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
- Cy_SysClk_ClkPath12Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
- Cy_SysClk_ClkPath13Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
- Cy_SysClk_ClkPath14Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
- Cy_SysClk_ClkPath15Init();
- #endif
-
- /* Configure and enable FLL */
- #ifdef CY_CFG_SYSCLK_FLL_ENABLED
- Cy_SysClk_FllInit();
- #endif
-
- Cy_SysClk_ClkHf0Init();
-
- #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
- #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
- /* Apply the ClkPath1 user setting */
- Cy_SysClk_ClkPath1Init();
- #endif
- #endif
-
- /* Configure and enable PLLs */
- #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
- Cy_SysClk_Pll0Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
- Cy_SysClk_Pll1Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
- Cy_SysClk_Pll2Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
- Cy_SysClk_Pll3Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
- Cy_SysClk_Pll4Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
- Cy_SysClk_Pll5Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
- Cy_SysClk_Pll6Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
- Cy_SysClk_Pll7Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
- Cy_SysClk_Pll8Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
- Cy_SysClk_Pll9Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
- Cy_SysClk_Pll10Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
- Cy_SysClk_Pll11Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
- Cy_SysClk_Pll12Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
- Cy_SysClk_Pll13Init();
- #endif
- #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
- Cy_SysClk_Pll14Init();
- #endif
-
- /* Configure HF clocks */
- #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
- Cy_SysClk_ClkHf1Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
- Cy_SysClk_ClkHf2Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
- Cy_SysClk_ClkHf3Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
- Cy_SysClk_ClkHf4Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
- Cy_SysClk_ClkHf5Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
- Cy_SysClk_ClkHf6Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
- Cy_SysClk_ClkHf7Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
- Cy_SysClk_ClkHf8Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
- Cy_SysClk_ClkHf9Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
- Cy_SysClk_ClkHf10Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
- Cy_SysClk_ClkHf11Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
- Cy_SysClk_ClkHf12Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
- Cy_SysClk_ClkHf13Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
- Cy_SysClk_ClkHf14Init();
- #endif
- #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
- Cy_SysClk_ClkHf15Init();
- #endif
-
- /* Configure miscellaneous clocks */
- #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
- Cy_SysClk_ClkTimerInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
- Cy_SysClk_ClkAltSysTickInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
- Cy_SysClk_ClkPumpInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
- Cy_SysClk_ClkBakInit();
- #endif
-
- /* Configure default enabled clocks */
- #ifdef CY_CFG_SYSCLK_ILO_ENABLED
- Cy_SysClk_IloInit();
- #else
- Cy_SysClk_IloDisable();
- #endif
-
- #ifndef CY_CFG_SYSCLK_IMO_ENABLED
- #error the IMO must be enabled for proper chip operation
- #endif
-
- #ifdef CY_CFG_SYSCLK_MFO_ENABLED
- Cy_SysClk_MfoInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
- Cy_SysClk_ClkMfInit();
- #endif
-
- /* Set accurate flash wait states */
- #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
- Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
- #endif
-
- /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
- SystemCoreClockUpdate();
-
-#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
-#endif //defined (CY_USING_HAL)
-}
diff --git a/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.c b/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.c
deleted file mode 100644
index 0472f3e..0000000
--- a/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/***************************************************************************//**
-* \file cy_retarget_io.c
-*
-* \brief
-* Provides APIs for retargeting stdio to UART hardware contained on the Cypress
-* kits.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include "cy_retarget_io_pdl.h"
-
-#include "cycfg_peripherals.h"
-
-#include "cy_sysint.h"
-#include "cy_scb_uart.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/* Tracks the previous character sent to output stream */
-#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-static char cy_retarget_io_stdout_prev_char = 0;
-#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
-
-cy_stc_scb_uart_context_t CYBSP_UART_context;
-
-static uint8_t cy_retarget_io_getchar(void);
-static void cy_retarget_io_putchar(char c);
-
-#if defined(__ARMCC_VERSION) /* ARM-MDK */
- /***************************************************************************
- * Function Name: fputc
- ***************************************************************************/
- __attribute__((weak)) int fputc(int ch, FILE *f)
- {
- (void)f;
- #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- if ((char)ch == '\n' && cy_retarget_io_stdout_prev_char != '\r')
- {
- cy_retarget_io_putchar('\r');
- }
-
- cy_retarget_io_stdout_prev_char = (char)ch;
- #endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
- cy_retarget_io_putchar(ch);
- return (ch);
- }
-#elif defined (__ICCARM__) /* IAR */
- #include <yfuns.h>
-
- /***************************************************************************
- * Function Name: __write
- ***************************************************************************/
- __weak size_t __write(int handle, const unsigned char * buffer, size_t size)
- {
- size_t nChars = 0;
- /* This template only writes to "standard out", for all other file
- * handles it returns failure. */
- if (handle != _LLIO_STDOUT)
- {
- return (_LLIO_ERROR);
- }
- if (buffer != NULL)
- {
- for (/* Empty */; nChars < size; ++nChars)
- {
- #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- if (*buffer == '\n' && cy_retarget_io_stdout_prev_char != '\r')
- {
- cy_retarget_io_putchar('\r');
- }
-
- cy_retarget_io_stdout_prev_char = *buffer;
- #endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
- cy_retarget_io_putchar(*buffer);
- ++buffer;
- }
- }
- return (nChars);
- }
-#else /* (__GNUC__) GCC */
- /* Add an explicit reference to the floating point printf library to allow
- the usage of floating point conversion specifier. */
- __asm (".global _printf_float");
- /***************************************************************************
- * Function Name: _write
- ***************************************************************************/
- __attribute__((weak)) int _write (int fd, const char *ptr, int len)
- {
- int nChars = 0;
- (void)fd;
- if (ptr != NULL)
- {
- for (/* Empty */; nChars < len; ++nChars)
- {
- #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
- if (*ptr == '\n' && cy_retarget_io_stdout_prev_char != '\r')
- {
- cy_retarget_io_putchar('\r');
- }
-
- cy_retarget_io_stdout_prev_char = *ptr;
- #endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
- cy_retarget_io_putchar((uint32_t)*ptr);
- ++ptr;
- }
- }
- return (nChars);
- }
-#endif
-
-
-#if defined(__ARMCC_VERSION) /* ARM-MDK */
- /***************************************************************************
- * Function Name: fgetc
- ***************************************************************************/
- __attribute__((weak)) int fgetc(FILE *f)
- {
- (void)f;
- return (cy_retarget_io_getchar());
- }
-#elif defined (__ICCARM__) /* IAR */
- __weak size_t __read(int handle, unsigned char * buffer, size_t size)
- {
- /* This template only reads from "standard in", for all other file
- handles it returns failure. */
- if ((handle != _LLIO_STDIN) || (buffer == NULL))
- {
- return (_LLIO_ERROR);
- }
- else
- {
- *buffer = cy_retarget_io_getchar();
- return (1);
- }
- }
-#else /* (__GNUC__) GCC */
- /* Add an explicit reference to the floating point scanf library to allow
- the usage of floating point conversion specifier. */
- __asm (".global _scanf_float");
- __attribute__((weak)) int _read (int fd, char *ptr, int len)
- {
- int nChars = 0;
- (void)fd;
- if (ptr != NULL)
- {
- for(/* Empty */;nChars < len;++ptr)
- {
- *ptr = (char)cy_retarget_io_getchar();
- ++nChars;
- if((*ptr == '\n') || (*ptr == '\r'))
- {
- break;
- }
- }
- }
- return (nChars);
- }
-#endif
-
-static uint8_t cy_retarget_io_getchar(void)
-{
- uint32_t read_value = Cy_SCB_UART_Get(CYBSP_UART_HW);
- while (read_value == CY_SCB_UART_RX_NO_DATA)
- {
- read_value = Cy_SCB_UART_Get(CYBSP_UART_HW);
- }
-
- return (uint8_t)read_value;
-}
-
-static void cy_retarget_io_putchar(char c)
-{
- uint32_t count = 0;
- while (count == 0)
- {
- count = Cy_SCB_UART_Put(CYBSP_UART_HW, c);
- }
-}
-
-static cy_rslt_t cy_retarget_io_pdl_setbaud(CySCB_Type *base, uint32_t baudrate)
-{
- cy_rslt_t result = CY_RSLT_TYPE_ERROR;
-
- uint8_t oversample_value = 8u;
- uint8_t frac_bits = 0u;
- uint32_t divider;
-
- Cy_SCB_UART_Disable(base, NULL);
-
- result = (cy_rslt_t) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0);
-
- divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + ((baudrate * oversample_value) / 2)) / (baudrate * oversample_value) - 1;
-
- if (result == CY_RSLT_SUCCESS)
- {
- result = (cy_rslt_t) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0u, divider);
- }
-
- if (result == CY_RSLT_SUCCESS)
- {
- result = Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0u);
- }
-
- Cy_SCB_UART_Enable(base);
-
- return result;
-}
-
-cy_rslt_t cy_retarget_io_pdl_init(uint32_t baudrate)
-{
- cy_rslt_t result = CY_RSLT_TYPE_ERROR;
-
- result = (cy_rslt_t)Cy_SCB_UART_Init(CYBSP_UART_HW, &CYBSP_UART_config, &CYBSP_UART_context);
-
- if (result == CY_RSLT_SUCCESS)
- {
- result = cy_retarget_io_pdl_setbaud(CYBSP_UART_HW, baudrate);
- }
-
- if (result == CY_RSLT_SUCCESS)
- {
- Cy_SCB_UART_Enable(CYBSP_UART_HW);
- }
-
- return result;
-}
-
-/**
- * @brief Wait while UART completes transfer. Try for tries_count times -
- * once each 10 millisecons.
- */
-void cy_retarget_io_wait_tx_complete(CySCB_Type *base, uint32_t tries_count)
-{
- while(tries_count > 0)
- {
- if (!Cy_SCB_UART_IsTxComplete(base)) {
- Cy_SysLib_DelayCycles(10 * cy_delayFreqKhz);
- tries_count -= 1;
- } else {
- return;
- }
- }
-}
-
-void cy_retarget_io_pdl_deinit()
-{
- Cy_SCB_UART_DeInit(CYBSP_UART_HW);
-}
-
-#if defined(__cplusplus)
-}
-#endif
diff --git a/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.h b/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.h
deleted file mode 100644
index f0c8733..0000000
--- a/boot/cypress/platforms/retarget_io_pdl/cy_retarget_io_pdl.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/***************************************************************************//**
-* \file cy_retarget_io.h
-*
-* \brief
-* Provides APIs for transmitting messages to or from the board via standard
-* printf/scanf functions. Messages are transmitted over a UART connection which
-* is generally connected to a host machine. Transmission is done at 115200 baud
-* using the tx and rx pins provided by the user of this library. The UART
-* instance is made available via cy_retarget_io_uart_obj in case any changes
-* to the default configuration are desired.
-* NOTE: If the application is built using newlib-nano, by default, floating
-* point format strings (%f) are not supported. To enable this support you must
-* add '-u _printf_float' to the linker command line.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#pragma once
-
-#include <stdio.h>
-#include "cy_result.h"
-#include "cy_pdl.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/** UART baud rate */
-#define CY_RETARGET_IO_BAUDRATE (115200)
-
-/** Defining this macro enables conversion of line feed (LF) into carriage
- * return followed by line feed (CR & LF) on the output direction (STDOUT). You
- * can define this macro through the DEFINES variable in the application
- * Makefile.
- */
-#define CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-
-cy_rslt_t cy_retarget_io_pdl_init(uint32_t baudrate);
-
-void cy_retarget_io_wait_tx_complete(CySCB_Type *base, uint32_t tries_count);
-
-void cy_retarget_io_pdl_deinit(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
diff --git a/boot/cypress/run_toc2_generator.sh b/boot/cypress/run_toc2_generator.sh
new file mode 100755
index 0000000..4b47cba
--- /dev/null
+++ b/boot/cypress/run_toc2_generator.sh
@@ -0,0 +1,364 @@
+#!/bin/bash
+(set -o igncr) 2>/dev/null && set -o igncr; #keep this comment
+
+echo_run() { echo "\$ ${@/eval/}" ; "$@" ; }
+
+# set -vx
+
+# parameters
+# 1. secure/non-secure
+# 2. path to app
+# 3. app name
+# 4. app type
+# 5. path to keys
+# 6. smif config file
+
+# additional mcuboot makefile param
+# 7. gcc toolchain path
+# 8. path to policy
+# 9. default application slot size
+# 10. enable encryption
+# 11. service application descriptor address
+
+# Combined image configuration
+LCS=$1
+: ${LCS:="NORMAL_NO_SECURE"}
+
+# Path to the image and image name for programming (the extension must be bin)
+L1_USER_APP_BIN="$2/$3.bin"
+: ${L1_USER_APP_BIN:="blinky.bin"}
+
+if [ "$LCS" == "SECURE" ]; then
+L1_USER_APP_BIN_SIGN="$2/$3.signed.bin"
+: ${L1_USER_APP_BIN_SIGN:="blinky.signed.bin"}
+fi
+
+L1_USER_APP_ELF="$2/$3.elf"
+: ${L1_USER_APP_ELF:="blinky.elf"}
+
+FINAL_BIN_FILE="$2/$3.final.bin"
+: ${FINAL_BIN_FILE:="blinky.final.bin"}
+
+COMBINED_BIN_FILE="$2/$3.combined.bin"
+: ${L1_USER_APP_BIN:="blinky.combined.bin"}
+
+FINAL_HEX_FILE="$2/$3.final.hex"
+: ${FINAL_HEX_FILE:="blinky.final.hex"}
+
+AES_CTR_NONCE_FILE="$2/$3.signed_nonce.bin"
+
+ENCRYPTED_MCUBOOT_BIN_FILE="$2/$3.signed_encrypted.bin"
+
+TOC2_FILE="$2/toc2.bin"
+
+L1_DESC_TEMP="$2/l1_app_desc_temp.bin"
+
+L1_DESC_FILE="$2/l1_app_desc.bin"
+
+L1_USER_APP_HEADER_FILE="$2/l1_user_app_header.bin"
+
+APP_TYPE=$4
+: ${APP_TYPE:="l1ram"}
+
+PROVISION_PATH=$5
+: ${PROVISION_PATH:="."}
+
+# Path to the smif_crypto_cfg and its name for programming (the extension
+# must be bin)
+SMIF_CRYPTO_CFG=$6
+: ${SMIF_CRYPTO_CFG:="NONE"}
+
+# Full path to the default toolchain
+if [ "$7" == "" ];then
+ NM_TOOL=arm-none-eabi-nm
+else
+ NM_TOOL="$7"/bin/arm-none-eabi-nm
+fi
+
+POLICY_PATH=$8
+: ${POLICY_PATH:="$PROVISION_PATH/policy/policy_secure.json"}
+
+SLOT_SIZE=$9
+
+if [ "${10}" == "1" ];then
+ ENC_OPTION="--encrypt"
+else
+ ENC_OPTION=""
+fi
+
+SERVICE_APP_DESCR_ADDR=${11}
+: ${SERVICE_APP_DESCR_ADDR:=0x0}
+
+######################## Validate Input Args #################################
+if ! [ -f $L1_USER_APP_BIN ]; then
+ echo "ERROR: $L1_USER_APP_BIN not found"
+ exit 1
+fi
+
+if ! [ -f $L1_USER_APP_ELF ]; then
+ echo "ERROR: $L1_USER_APP_ELF not found"
+ exit 1
+fi
+
+if ! [ -d $PROVISION_PATH ]; then
+ echo "ERROR: $PROVISION_PATH not found"
+ exit 1
+fi
+
+if [ "$TOOLCHAIN" != "ARM" ]; then
+if ! [ -x $NM_TOOL ]; then
+ echo "ERROR: $NM_TOOL not found"
+ exit 1
+fi
+fi
+
+if ! [ -x "$(command -v awk)" ]; then
+ echo "ERROR: awk not found"
+ exit 1
+fi
+
+# if ! [ -x "$(command -v print)" ]; then
+# echo "ERROR: print not found"
+# exit 1
+# fi
+
+if [ "$LCS" == "SECURE" ]; then
+ if ! [ -x "$(command -v cysecuretools)" ]; then
+ echo "ERROR: cysecuretools not found"
+ exit 1
+ fi
+fi
+######################### Generate TOC2 ########################################
+
+# Hardcoded value bytes
+TOC2_SIZE=16
+
+# Hardcoded address in external memory
+TOC2_ADDR=0x0
+
+# TOC2 entries in hexadecimal
+L1_APP_DESCR_ADDR=0x10
+DEBUG_CERT_ADDR=0x0
+
+# Convert to hex string (without 0x prefix)
+TOC2_SIZE_HEX=$(printf "%08x" $TOC2_SIZE)
+L1_APP_DESCR_ADDR_HEX=$(printf "%08x" $(expr $L1_APP_DESCR_ADDR))
+SERVICE_APP_DESCR_ADDR_HEX=$(printf "%08x" $(expr $SERVICE_APP_DESCR_ADDR))
+DEBUG_CERT_ADDR_HEX=$(printf "%08x" $(expr $DEBUG_CERT_ADDR))
+
+# Write 4 bytes from hex string, LSB first
+printf "\x"${TOC2_SIZE_HEX:6:2} > $TOC2_FILE
+printf "\x"${TOC2_SIZE_HEX:4:2} >> $TOC2_FILE
+printf "\x"${TOC2_SIZE_HEX:2:2} >> $TOC2_FILE
+printf "\x"${TOC2_SIZE_HEX:0:2} >> $TOC2_FILE
+
+printf "\x"${L1_APP_DESCR_ADDR_HEX:6:2} >> $TOC2_FILE
+printf "\x"${L1_APP_DESCR_ADDR_HEX:4:2} >> $TOC2_FILE
+printf "\x"${L1_APP_DESCR_ADDR_HEX:2:2} >> $TOC2_FILE
+printf "\x"${L1_APP_DESCR_ADDR_HEX:0:2} >> $TOC2_FILE
+
+printf "\x"${SERVICE_APP_DESCR_ADDR_HEX:6:2} >> $TOC2_FILE
+printf "\x"${SERVICE_APP_DESCR_ADDR_HEX:4:2} >> $TOC2_FILE
+printf "\x"${SERVICE_APP_DESCR_ADDR_HEX:2:2} >> $TOC2_FILE
+printf "\x"${SERVICE_APP_DESCR_ADDR_HEX:0:2} >> $TOC2_FILE
+
+printf "\x"${DEBUG_CERT_ADDR_HEX:6:2} >> $TOC2_FILE
+printf "\x"${DEBUG_CERT_ADDR_HEX:4:2} >> $TOC2_FILE
+printf "\x"${DEBUG_CERT_ADDR_HEX:2:2} >> $TOC2_FILE
+printf "\x"${DEBUG_CERT_ADDR_HEX:0:2} >> $TOC2_FILE
+
+if [ ! -f "$TOC2_FILE" ]; then
+ echo "Error: $TOC2_FILE does not exist." > /dev/tty
+ exit -1
+fi
+######################### Generate L1_APP_DESCR ################################
+
+# Hardcoded value bytes
+L1_APP_DESCR_SIZE=28
+
+# Placed after the TOC2
+L1_APP_DESCR_ADDR=$(printf "0x%x" `expr $TOC2_SIZE`)
+BOOT_STRAP_DST_ADDR=0x20004000
+# L1_APP_DESCR entries in hexadecimal
+if [ "$LCS" == "NORMAL_NO_SECURE" ]; then
+ BOOT_STRAP_ADDR=0x50 # Fix address for un-signed image
+else
+ BOOT_STRAP_ADDR=0x30 # Fix address for signed image
+fi
+
+if [ "$APP_TYPE" == "l1ram" ]; then
+ BOOT_STRAP_SIZE=`wc -c ${L1_USER_APP_BIN} | awk '{print $1}'`
+ BOOT_STRAP_DST_ADDR_ELF=`${NM_TOOL} ${L1_USER_APP_ELF} | grep "__bootstrap_start_addr__" | awk '{print $1}'`
+ BOOT_STRAP_DST_ADDR=$(printf "%d" $((16#$BOOT_STRAP_DST_ADDR_ELF)))
+
+ if [ ! -f "$L1_USER_APP_BIN" ]; then
+ echo "Error: $L1_USER_APP_BIN does not exist." > /dev/tty
+ exit -1
+ fi
+else
+ BOOT_STRAP_SIZE_ELF=`${NM_TOOL} ${L1_USER_APP_ELF} | grep "__bootstrap_size__" | awk '{print $1}'`
+ BOOT_STRAP_SIZE=$(printf "%d" $((16#$BOOT_STRAP_SIZE_ELF)))
+ BOOT_STRAP_DST_ADDR_ELF=`${NM_TOOL} ${L1_USER_APP_ELF} | grep "__bootstrap_start_addr__" | awk '{print $1}'`
+ BOOT_STRAP_DST_ADDR=$(printf "%d" $((16#$BOOT_STRAP_DST_ADDR_ELF)))
+if [ "$TOOLCHAIN" == "ARM" ]; then
+# Reserving 0x3000 for bootstrap. This needs to be calculated based on the actual size
+ BOOT_STRAP_SIZE=12288
+fi
+fi
+
+# Convert to hex string (without 0x prefix)
+L1_APP_DESCR_SIZE_HEX=$(printf "%08x" $L1_APP_DESCR_SIZE)
+BOOT_STRAP_ADDR_HEX=$(printf "%08x" $BOOT_STRAP_ADDR)
+BOOT_STRAP_DST_ADDR_HEX=$(printf "%08x" $BOOT_STRAP_DST_ADDR)
+BOOT_STRAP_SIZE_HEX=$(printf "%08x" $BOOT_STRAP_SIZE)
+
+if [ $BOOT_STRAP_SIZE_HEX == 00000000 ]; then
+ echo "ERROR: in calculating bootstrap size"
+ exit 1
+fi
+
+# Write 4 bytes from hex string, LSB first
+printf "\x"${L1_APP_DESCR_SIZE_HEX:6:2} > $L1_DESC_TEMP
+printf "\x"${L1_APP_DESCR_SIZE_HEX:4:2} >> $L1_DESC_TEMP
+printf "\x"${L1_APP_DESCR_SIZE_HEX:2:2} >> $L1_DESC_TEMP
+printf "\x"${L1_APP_DESCR_SIZE_HEX:0:2} >> $L1_DESC_TEMP
+
+printf "\x"${BOOT_STRAP_ADDR_HEX:6:2} >> $L1_DESC_TEMP
+printf "\x"${BOOT_STRAP_ADDR_HEX:4:2} >> $L1_DESC_TEMP
+printf "\x"${BOOT_STRAP_ADDR_HEX:2:2} >> $L1_DESC_TEMP
+printf "\x"${BOOT_STRAP_ADDR_HEX:0:2} >> $L1_DESC_TEMP
+
+printf "\x"${BOOT_STRAP_DST_ADDR_HEX:6:2} >> $L1_DESC_TEMP
+printf "\x"${BOOT_STRAP_DST_ADDR_HEX:4:2} >> $L1_DESC_TEMP
+printf "\x"${BOOT_STRAP_DST_ADDR_HEX:2:2} >> $L1_DESC_TEMP
+printf "\x"${BOOT_STRAP_DST_ADDR_HEX:0:2} >> $L1_DESC_TEMP
+
+printf "\x"${BOOT_STRAP_SIZE_HEX:6:2} >> $L1_DESC_TEMP
+printf "\x"${BOOT_STRAP_SIZE_HEX:4:2} >> $L1_DESC_TEMP
+printf "\x"${BOOT_STRAP_SIZE_HEX:2:2} >> $L1_DESC_TEMP
+printf "\x"${BOOT_STRAP_SIZE_HEX:0:2} >> $L1_DESC_TEMP
+
+if [ ! -f "$L1_DESC_TEMP" ]; then
+ echo "Error: $L1_DESC_TEMP does not exist." > /dev/tty
+ exit -1
+fi
+
+if [ "$SMIF_CRYPTO_CFG" == "NONE" ]; then
+ for var in 0 1 2
+ do
+ SMIF_CRYPTO_CFG_HEX=00000000
+ printf "\x"${SMIF_CRYPTO_CFG_HEX:6:2} >> $L1_DESC_TEMP
+ printf "\x"${SMIF_CRYPTO_CFG_HEX:4:2} >> $L1_DESC_TEMP
+ printf "\x"${SMIF_CRYPTO_CFG_HEX:2:2} >> $L1_DESC_TEMP
+ printf "\x"${SMIF_CRYPTO_CFG_HEX:0:2} >> $L1_DESC_TEMP
+ done
+
+ `mv $L1_DESC_TEMP $L1_DESC_FILE`
+
+ if [ ! -f "$L1_DESC_FILE" ]; then
+ echo "Error: $L1_DESC_FILE does not exist." > /dev/tty
+ exit -1
+ fi
+else
+ if [ ! -f "$L1_DESC_TEMP.bin" ]; then
+ echo "Error: $L1_DESC_TEMP.bin does not exist." > /dev/tty
+ exit -1
+ fi
+ if [ ! -f "$SMIF_CRYPTO_CFG.bin" ]; then
+ echo "Error: $SMIF_CRYPTO_CFG.bin does not exist." > /dev/tty
+ exit -1
+ fi
+
+ `cat $L1_DESC_TEMP $SMIF_CRYPTO_CFG.bin > $L1_DESC_FILE
+ rm -f $L1_DESC_TEMP`
+
+ if [ ! -f "$L1_DESC_FILE" ]; then
+ echo "Error: $L1_DESC_FILE does not exist." > /dev/tty
+ exit -1
+ fi
+ if [ -f "$L1_DESC_TEMP" ]; then
+ echo "Error: $L1_DESC_TEMP has not been removed." > /dev/tty
+ exit -1
+ fi
+fi
+
+if [ ! -f "$TOC2_FILE" ]; then
+ echo "Error: $TOC2_FILE does not exist." > /dev/tty
+ exit -1
+fi
+if [ ! -f "$L1_DESC_FILE" ]; then
+ echo "Error: $L1_DESC_FILE does not exist." > /dev/tty
+ exit -1
+fi
+
+# 4 bytes of padding (encrypted data should be aligned to 0x10 boundary)
+echo -en "\0\0\0\0" >> $L1_DESC_FILE
+
+if [ "$LCS" == "NORMAL_NO_SECURE" ]; then
+
+ number=0
+
+ L1_USER_APP_HEADER_HEX=00000000
+ # create 32 byte null header for bootstrap
+ printf "\x"${L1_USER_APP_HEADER_HEX:6:2} > $L1_USER_APP_HEADER_FILE
+ printf "\x"${L1_USER_APP_HEADER_HEX:4:2} >> $L1_USER_APP_HEADER_FILE
+ printf "\x"${L1_USER_APP_HEADER_HEX:2:2} >> $L1_USER_APP_HEADER_FILE
+ printf "\x"${L1_USER_APP_HEADER_HEX:0:2} >> $L1_USER_APP_HEADER_FILE
+
+ if [ ! -f "$L1_USER_APP_HEADER_FILE" ]; then
+ echo "Error: $L1_USER_APP_HEADER_FILE does not exist." > /dev/tty
+ exit -1
+ fi
+
+ while [ $number -lt 7 ]
+ do
+ printf "\x"${L1_USER_APP_HEADER_HEX:6:2} >> $L1_USER_APP_HEADER_FILE
+ printf "\x"${L1_USER_APP_HEADER_HEX:4:2} >> $L1_USER_APP_HEADER_FILE
+ printf "\x"${L1_USER_APP_HEADER_HEX:2:2} >> $L1_USER_APP_HEADER_FILE
+ printf "\x"${L1_USER_APP_HEADER_HEX:0:2} >> $L1_USER_APP_HEADER_FILE
+
+ number=`expr $number + 1`
+ done
+
+ if [ ! -f "$L1_USER_APP_HEADER_FILE" ]; then
+ echo "Error: $L1_USER_APP_HEADER_FILE does not exist." > /dev/tty
+ exit -1
+ fi
+ if [ ! -f "$L1_USER_APP_BIN" ]; then
+ echo "Error: $L1_USER_APP_BIN does not exist." > /dev/tty
+ exit -1
+ fi
+
+ # Combining all images (toc2+l1_app_desc+l1_user_app_header+l1_user_app) to Final binary file
+ `cat $TOC2_FILE $L1_DESC_FILE $L1_USER_APP_HEADER_FILE $L1_USER_APP_BIN > $FINAL_BIN_FILE`
+elif [ "$LCS" == "SECURE" ]; then
+ if [ ! -f "$L1_USER_APP_BIN" ]; then
+ echo "Error: $L1_USER_APP_BIN does not exist." > /dev/tty
+ exit -1
+ fi
+
+ # Sign l1 user app L1_USER_APP_BIN_SIGN
+ cysecuretools -q -t cyw20829 -p $POLICY_PATH sign-image --image-format bootrom_next_app -i $L1_USER_APP_BIN -k 0 -o $L1_USER_APP_BIN_SIGN --slot-size $SLOT_SIZE --app-addr 0x08000030 $ENC_OPTION
+
+ if [ ! -f "$L1_USER_APP_BIN_SIGN" ]; then
+ echo "Error: $L1_USER_APP_BIN_SIGN has not been created." > /dev/tty
+ exit -1
+ fi
+
+ # Combining all images (toc2+l1_app_desc+l1_user_app) to Final binary file of MCUBootApp
+ if [ -z $ENC_OPTION ]; then
+ cat $TOC2_FILE $L1_DESC_FILE $L1_USER_APP_BIN_SIGN > $FINAL_BIN_FILE
+ else
+ # Patching L1 app descriptor with AES-CTR Nonce
+ dd seek=16 bs=1 count=12 conv=notrunc if=$AES_CTR_NONCE_FILE of=$L1_DESC_FILE >& /dev/null && \
+ cat $TOC2_FILE $L1_DESC_FILE ${ENCRYPTED_MCUBOOT_BIN_FILE} > $FINAL_BIN_FILE
+ fi
+else
+ echo "ERROR: Invalid LCS ($LCS) value"
+ exit 1
+fi
+
+if [ ! -f "$FINAL_BIN_FILE" ]; then
+ echo "Error: $FINAL_BIN_FILE does not exist." > /dev/tty
+ exit -1
+fi
diff --git a/boot/cypress/scripts/bin2c.py b/boot/cypress/scripts/bin2c.py
new file mode 100644
index 0000000..04bc67a
--- /dev/null
+++ b/boot/cypress/scripts/bin2c.py
@@ -0,0 +1,95 @@
+#!/usr/bin/env python
+
+import os
+import sys
+import argparse
+import binascii
+
+number_of_columns = 16
+
+copyright = """/***************************************************************************//**
+* \\file {}
+*
+* \\brief
+* Cortex-M0+ prebuilt application image.
+*
+********************************************************************************
+* \\copyright
+* Copyright (c) 2018-2019 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: LicenseRef-PBL
+*
+* Licensed under the Permissive Binary License
+*******************************************************************************/
+
+"""
+
+header = """
+#if defined(__APPLE__) && defined(__clang__)
+__attribute__ ((__section__("__CY_M0P_IMAGE,__cy_m0p_image"), used))
+#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cy_m0p_image"), used))
+#elif defined(__ICCARM__)
+#pragma location=".cy_m0p_image"
+#else
+#error "An unsupported toolchain"
+#endif
+const uint8_t cy_m0p_image[] = {
+"""
+
+c_list = []
+
+
+# Get component name from the command line
+parser = argparse.ArgumentParser()
+parser.add_argument("bin_path", help="Specify path the input binary file to be converted to a C array.")
+parser.add_argument("c_path", help="Specify path the output C file with the C array.")
+parser.add_argument("c_macro", help="Specify the C preprocessor macro to wrap the variable.")
+args = parser.parse_args()
+bin_path = args.bin_path
+c_path = args.c_path
+c_macro = args.c_macro
+
+c_file=os.path.basename(c_path)
+
+f = open(bin_path, "rb")
+data = list(f.read())
+
+with open(c_path, "w") as c_fd:
+
+ # Clear content of the file
+ c_fd.seek(0)
+ c_fd.truncate()
+
+ # Write copyright
+ c_fd.write(copyright.format(c_file))
+
+ # Include headers
+ c_fd.write("#include <stdint.h>\n")
+ c_fd.write("#include \"cy_device_headers.h\"\n")
+ c_fd.write("\n")
+
+ # Open conditional block
+ if c_macro:
+ c_fd.write("#if defined(" + c_macro + ")\n")
+
+ # Write template
+ c_fd.write(header)
+
+ # Generate list of the data bytes
+ for n in data:
+ c_list.append(format(n, '#04x'))
+
+ for i in range(int(len(c_list) / number_of_columns) + 1):
+ line_list = c_list[i * number_of_columns: (i + 1) * number_of_columns]
+ c_fd.write(" ")
+ for item in line_list:
+ c_fd.write(" %su," % item)
+ c_fd.write("\n")
+
+ c_fd.write("};\n")
+
+ # Close conditional block
+ if c_macro:
+ c_fd.write("#endif /* defined(" + c_macro + ") */")
+ c_fd.write("\n")
+f.close()
diff --git a/boot/cypress/scripts/cppcheck.sh b/boot/cypress/scripts/cppcheck.sh
new file mode 100644
index 0000000..862b926
--- /dev/null
+++ b/boot/cypress/scripts/cppcheck.sh
@@ -0,0 +1,145 @@
+#!/bin/bash
+#
+# this must be the first non-commented line in this script. It ensures
+# bash doesn't choke on \r on Windows
+(set -o igncr) 2>/dev/null && set -o igncr; # this comment is needed
+
+#
+# This script does static code analysis using Cppcheck tool
+# Copyright (c) 2019 Cypress Semiconductor.
+#
+
+# It performs Cppcheck code analysis with following inputs
+# 1. CypressBootloader/sources - Code analysis is done on all the sources of CypressBootloader.
+# 2. Additional source files to be analyzed are grabbed from config file that is provided as a first argument to the script.
+# 3. Files to be ignored are grabbed from config file that is provided as a first argument to the script.
+# 4. To ignore a file its name need to be added to the config file with word "ignore" as perfix
+# 5. To add any additional files, apart the files from CypressBootloader/sources, those names need
+# to be added in a config file.
+# Example
+# A). add below entries in cpp_check.dat file
+# ignore cy_bootloader_hw.c
+# file1.c
+# file2.c
+# ignore cy_bootloader_services.c
+# B). invoke cpp_check shell script
+# cpp_check.sh cpp_check.dat
+#
+# Above example performs Cppcheck analysis on CypressBootloader/sources, ignore cy_bootloader_hw.c, file1.c, file2.c and ignores cy_bootloader_services.c
+
+
+app_name="$1"
+platform="$2"
+app_defines="$3"
+app_includes="$4"
+CPP_CHECK_FILES="$5"
+scope="$6"
+buildcfg="$7"
+
+if [[ ${scope} != "" ]]; then
+ SCOPE="--enable=${scope}"
+else
+ SCOPE=""
+fi
+
+#Retrieve list of files need to be ignored
+while IFS= read -r line
+do
+ CPP_CHECK_IGNORE_FILES="$CPP_CHECK_IGNORE_FILES -i $line"
+done < "${app_name}/cppcheck/ignore_files.list"
+
+#Retrieve list of cppcheck directives
+while IFS= read -r line
+do
+ CPP_CHECK_SUPPRESS="$CPP_CHECK_SUPPRESS --suppress=$line"
+done < "${app_name}/cppcheck/suppress_types.list"
+
+echo "-------------------------------------------"
+echo "Suppress options:" "$CPP_CHECK_SUPPRESS"
+echo "-------------------------------------------"
+echo "Additional files:" "$CPP_CHECK_FILES"
+echo "-------------------------------------------"
+echo "Ignoring files:" "$CPP_CHECK_IGNORE_FILES"
+echo "-------------------------------------------"
+echo "CppCheck scope of messages defined with option " ${SCOPE}
+echo "-------------------------------------------"
+echo "Run CppCheck for platform" ${platform}
+echo "-------------------------------------------"
+echo "Defines passed to CppCheck:"
+echo ${app_defines}
+echo "-------------------------------------------"
+echo "Include dirs passed to CppCheck:"
+echo ${app_includes}
+echo "-------------------------------------------"
+
+mkdir -p ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_html
+
+dos2unix ${app_name}/cppcheck/suppress_messages.list
+
+#Generate xml file
+cppcheck ${SCOPE} ${CPP_CHECK_SUPPRESS} -D__GNUC__ -D${platform} ${app_defines} ${app_includes} ${CPP_CHECK_FILES} ${CPP_CHECK_IGNORE_FILES} \
+ --xml 2> ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.xml
+
+#Generate html file
+python scripts/cppcheck-htmlreport.py --file=${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.xml --report-dir=${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_html --title=${app_name}
+
+cppcheck ${SCOPE} ${CPP_CHECK_SUPPRESS} -D__GNUC__ -D${platform} ${app_defines} ${app_includes} ${CPP_CHECK_FILES} ${CPP_CHECK_IGNORE_FILES} \
+ --template="{severity}\n{id}\n{message}\n{file}\n{line}:{column}\n{code}\n" 2> ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full
+
+#Generate csv file
+echo "severity@id@message@file@line" > ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.csv
+while IFS= read -r line
+do
+ read -r line2
+ read -r line3
+ read -r line4
+ read -r line5
+ line4=$(echo $line4 | sed 's/.*\\cy_mcuboot\\//' | tr '\\' '/')
+ if grep -xq "${line}@${line2}@${line3}@${line4}@${line5}" ${app_name}/cppcheck/suppress_messages.list
+ then
+ :;#suppress current warning
+ else
+ echo ${line}@${line2}@${line3}@${line4}@${line5}
+ fi
+ read -r line
+ read -r line
+ read -r line
+done \
+< ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full \
+>>${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.csv
+
+#Generate log file
+while IFS= read -r line
+do
+ read -r line2
+ read -r line3
+ read -r line4
+ read -r line5
+ line4=$(echo $line4 | sed 's/.*\\cy_mcuboot\\//' | tr '\\' '/')
+ if grep -xq "${line}@${line2}@${line3}@${line4}@${line5}" ${app_name}/cppcheck/suppress_messages.list
+ then
+ read -r line
+ read -r line
+ read -r line
+ else
+ echo ${line} : ${line2}
+ echo ${line3}
+ echo "${line4} (${line5})"
+ read -r line
+ echo ${line}
+ read -r line
+ echo ${line}
+ read -r line
+ echo "-------------------------------------------"
+ fi
+done \
+< ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full \
+> ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.log
+
+rm ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full
+cat ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.log
+
+RC=$(( $(wc -l ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.csv | cut -d' ' -f1) -1 ))
+echo "${app_name} CPPCHECK FOR ${platform} KIT FOUND $RC ERRORS"
+
+exit $RC
\ No newline at end of file
diff --git a/boot/cypress/scripts/find_cysectools.py b/boot/cypress/scripts/find_cysectools.py
new file mode 100644
index 0000000..7bea0fc
--- /dev/null
+++ b/boot/cypress/scripts/find_cysectools.py
@@ -0,0 +1,58 @@
+"""
+Copyright (c) 2019 Cypress Semiconductor Corporation
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import subprocess
+import sys
+
+package = 'cysecuretools'
+
+def find_cysectools(package_name):
+
+ """
+ Check if package exist in system and return its location if it does
+ """
+
+ pip_show = subprocess.Popen([sys.executable, '-m', 'pip', 'show', package],
+ stdout=subprocess.PIPE, stderr=subprocess.PIPE)
+
+ stdout = pip_show.communicate()[0]
+ rc = pip_show.wait()
+
+ if (rc != 0):
+ print("No package with name " + package + " found")
+ exit(1)
+ else:
+ pip_show_info = stdout.decode("utf-8").splitlines()
+
+ for line in pip_show_info:
+ if 'Location:' in line:
+ location = line.replace('Location: ', '')
+
+ if sys.platform == 'win32':
+ return location.replace('\\','/')
+ else:
+ return location
+
+def main():
+ """
+ Call function and print output
+ """
+ cysecuretools_path = find_cysectools(package)
+
+ print(cysecuretools_path)
+
+if __name__ == "__main__":
+ main()
\ No newline at end of file
diff --git a/boot/cypress/scripts/flashmap.py b/boot/cypress/scripts/flashmap.py
new file mode 100644
index 0000000..339e4c5
--- /dev/null
+++ b/boot/cypress/scripts/flashmap.py
@@ -0,0 +1,710 @@
+"""MCUBoot Flash Map Converter (JSON to .h)
+Copyright (c) 2022 Infineon Technologies AG
+"""
+
+import sys
+import getopt
+import json
+
+# Supported Platforms
+platDict = {
+ 'PSOC_062_2M': {
+ 'flashAddr': 0x10000000,
+ 'flashSize': 0x200000, # 2 MBytes
+ 'eraseSize': 0x200, # 512 bytes
+ 'smifAddr': 0x18000000,
+ 'smifSize': 0x8000000 # i.e., window size
+ },
+ 'PSOC_062_1M': {
+ 'flashAddr': 0x10000000,
+ 'flashSize': 0x100000, # 1 MByte
+ 'eraseSize': 0x200, # 512 bytes
+ 'smifAddr': 0x18000000,
+ 'smifSize': 0x8000000 # i.e., window size
+ },
+ 'PSOC_062_512K': {
+ 'flashAddr': 0x10000000,
+ 'flashSize': 0x80000, # 512 KBytes
+ 'eraseSize': 0x200, # 512 bytes
+ 'smifAddr': 0x18000000,
+ 'smifSize': 0x8000000 # i.e., window size
+ },
+ 'CYW20829': {
+ 'flashSize': 0, # n/a
+ 'smifAddr': 0x60000000,
+ 'smifSize': 0x8000000 # i.e., window size
+ }
+}
+
+# Supported SPI Flash ICs
+flashDict = {
+ # Fudan
+ 'FM25Q04': {
+ 'flashSize': 0x80000, # 4 Mbits
+ 'eraseSize': 0x1000, # 128 uniform sectors with 4K-byte each
+ },
+ 'FM25W04': {
+ 'flashSize': 0x80000, # 4 Mbits
+ 'eraseSize': 0x1000, # 128 uniform sectors with 4K-byte each
+ },
+ 'FM25Q08': {
+ 'flashSize': 0x100000, # 8 Mbits
+ 'eraseSize': 0x1000, # 256 uniform sectors with 4K-byte each
+ },
+ 'FM25W08': {
+ 'flashSize': 0x100000, # 8 Mbits
+ 'eraseSize': 0x1000, # 256 uniform sectors with 4K-byte each
+ },
+ # Puya
+ 'P25Q05H': {
+ 'flashSize': 0x10000, # 512 Kbits
+ 'eraseSize': 0x1000, # Uniform 4K-byte Sector Erase
+ },
+ 'P25Q10H': {
+ 'flashSize': 0x20000, # 1 Mbit
+ 'eraseSize': 0x1000, # Uniform 4K-byte Sector Erase
+ },
+ 'P25Q20H': {
+ 'flashSize': 0x40000, # 2 Mbits
+ 'eraseSize': 0x1000, # Uniform 4K-byte Sector Erase
+ },
+ 'P25Q40H': {
+ 'flashSize': 0x80000, # 4 Mbits
+ 'eraseSize': 0x1000, # Uniform 4K-byte Sector Erase
+ },
+ # Infineon
+ 'S25HS256T': {
+ 'flashSize': 0x2000000, # 256 Mbits
+ 'eraseSize': 0x40000, # Uniform Sector Architecture
+ },
+ 'S25HS512T': {
+ 'flashSize': 0x4000000, # 512 Mbits
+ 'eraseSize': 0x40000, # Uniform Sector Architecture
+ },
+ 'S25HS01GT': {
+ 'flashSize': 0x8000000, # 1 Gbit
+ 'eraseSize': 0x40000, # Uniform Sector Architecture
+ }
+}
+
+
+def is_overlap(fa1off, fa1size, fa2off, fa2size, align):
+ """Check if two flash areas on the same device overlap"""
+ mask = align - 1
+ assert align > 0 and (align & mask) == 0 # ensure align is a power of 2
+ fa1end = (fa1off + fa1size + mask) & ~mask
+ fa2end = (fa2off + fa2size + mask) & ~mask
+ fa1off = fa1off & ~mask
+ fa2off = fa2off & ~mask
+ return fa1off < fa2end and fa2off < fa1end
+
+
+def is_same_mem(fa1addr, fa2addr):
+ """Check if two addresses belong to the same memory"""
+ if fa1addr is None or fa2addr is None:
+ return False
+ mask = 0xFF000000
+ return (fa1addr & mask) == (fa2addr & mask)
+
+
+class CmdLineParams:
+ """Command line parameters"""
+
+ def __init__(self):
+ self.plat_id = ''
+ self.in_file = ''
+ self.out_file = ''
+ self.img_id = None
+
+ usage = 'USAGE:\n' + sys.argv[0] + \
+ ''' -p <platform> -i <flash_map.json> -o <flash_map.h> -d <img_id>
+
+OPTIONS:
+-h --help Display the usage information
+-p --platform= Target (e.g., PSOC_062_512K)
+-i --ifile= JSON flash map file
+-o --ofile= C header file to be generated
+-d --img_id ID of application to build'''
+
+ try:
+ opts, unused = getopt.getopt(
+ sys.argv[1:], 'hi:o:p:d:',
+ ['help', 'platform=', 'ifile=', 'ofile=', 'img_id='])
+ if len(unused) > 0:
+ print(usage, file=sys.stderr)
+ sys.exit(1)
+ except getopt.GetoptError:
+ print(usage, file=sys.stderr)
+ sys.exit(1)
+
+ for opt, arg in opts:
+ if opt in ('-h', '--help'):
+ print(usage, file=sys.stderr)
+ sys.exit()
+ elif opt in ('-p', '--platform'):
+ self.plat_id = arg
+ elif opt in ('-i', '--ifile'):
+ self.in_file = arg
+ elif opt in ('-o', '--ofile'):
+ self.out_file = arg
+ elif opt in ('-d', '--img_id'):
+ self.img_id = arg
+
+ if len(self.in_file) == 0 or len(self.out_file) == 0:
+ print(usage, file=sys.stderr)
+ sys.exit(1)
+
+
+class AreaList:
+ """List of flash areas"""
+
+ def __init__(self, plat, flash, use_overwrite):
+ self.plat = plat
+ self.flash = flash
+ self.use_overwrite = use_overwrite
+ self.areas = []
+ self.peers = {}
+ self.trailers = {}
+ self.internal_flash = False
+ self.external_flash = False
+ self.external_flash_xip = False
+
+ def get_min_erase_size(self):
+ """Calculate minimum erase block size for int./ext. Flash """
+ return self.plat['eraseSize'] if self.plat['flashSize'] > 0 \
+ else self.flash['eraseSize']
+
+ def get_img_trailer_size(self):
+ """Calculate image trailer size"""
+ return self.get_min_erase_size()
+
+ def process_int_area(self, title, fa_addr, fa_size,
+ img_trailer_size, shared_slot):
+ """Process internal flash area"""
+ fa_device_id = 'FLASH_DEVICE_INTERNAL_FLASH'
+ fa_off = fa_addr - self.plat['flashAddr']
+ if img_trailer_size is not None:
+ if self.use_overwrite:
+ if shared_slot:
+ print('Shared slot', title,
+ 'is not supported in OVERWRITE mode',
+ file=sys.stderr)
+ sys.exit(7)
+ else:
+ # Check trailer alignment (start at the sector boundary)
+ align = (fa_off + fa_size - img_trailer_size) % \
+ self.plat['eraseSize']
+ if align != 0:
+ fa_addr += self.plat['eraseSize'] - align
+ if fa_addr + fa_size <= \
+ self.plat['flashAddr'] + self.plat['flashSize']:
+ print('Misaligned', title,
+ '- suggested address', hex(fa_addr),
+ file=sys.stderr)
+ else:
+ print('Misaligned', title, file=sys.stderr)
+ sys.exit(7)
+ else:
+ # Check alignment (flash area should start at the sector boundary)
+ if fa_off % self.plat['eraseSize'] != 0:
+ print('Misaligned', title, file=sys.stderr)
+ sys.exit(7)
+ slot_sectors = int((fa_off % self.plat['eraseSize'] +
+ fa_size + self.plat['eraseSize'] - 1) //
+ self.plat['eraseSize'])
+ return fa_device_id, fa_off, slot_sectors
+
+ def process_ext_area(self, title, fa_addr, fa_size,
+ img_trailer_size, shared_slot):
+ """Process external flash area"""
+ if self.flash is None:
+ print('Unspecified SPI Flash IC',
+ file=sys.stderr)
+ sys.exit(3)
+ if fa_addr + fa_size <= \
+ self.plat['smifAddr'] + self.flash['flashSize']:
+ flash_idx = 'CY_BOOT_EXTERNAL_DEVICE_INDEX'
+ fa_device_id = f'FLASH_DEVICE_EXTERNAL_FLASH({flash_idx})'
+ fa_off = fa_addr - self.plat['smifAddr']
+ else:
+ print('Misfitting', title, file=sys.stderr)
+ sys.exit(7)
+ if img_trailer_size is not None:
+ if self.use_overwrite:
+ if shared_slot:
+ print('Shared slot', title,
+ 'is not supported in OVERWRITE mode',
+ file=sys.stderr)
+ sys.exit(7)
+ else:
+ # Check trailer alignment (start at the sector boundary)
+ align = (fa_off + fa_size - img_trailer_size) % \
+ self.flash['eraseSize']
+ if align != 0:
+ peer_addr = self.peers.get(fa_addr)
+ if shared_slot:
+ # Special case when using both int. and ext. memory
+ if self.plat['flashSize'] > 0 and \
+ align % self.plat['eraseSize'] == 0:
+ print('Note:', title, 'requires', align,
+ 'padding bytes before trailer',
+ file=sys.stderr)
+ else:
+ print('Misaligned', title, file=sys.stderr)
+ sys.exit(7)
+ elif is_same_mem(fa_addr, peer_addr) and \
+ fa_addr % self.flash['eraseSize'] == \
+ peer_addr % self.flash['eraseSize']:
+ pass # postpone checking
+ else:
+ fa_addr += self.flash['eraseSize'] - align
+ if fa_addr + fa_size <= \
+ self.plat['smifAddr'] + self.flash['flashSize']:
+ print('Misaligned', title,
+ '- suggested address', hex(fa_addr),
+ file=sys.stderr)
+ else:
+ print('Misaligned', title, file=sys.stderr)
+ sys.exit(7)
+ else:
+ # Check alignment (flash area should start at the sector boundary)
+ if fa_off % self.flash['eraseSize'] != 0:
+ print('Misaligned', title, file=sys.stderr)
+ sys.exit(7)
+ slot_sectors = int((fa_off % self.flash['eraseSize'] +
+ fa_size + self.flash['eraseSize'] - 1) //
+ self.flash['eraseSize'])
+ self.external_flash = True
+ if self.flash['XIP']:
+ self.external_flash_xip = True
+ return fa_device_id, fa_off, slot_sectors
+
+ def chk_area(self, fa_addr, fa_size, peer_addr=None):
+ """Check area location (internal/external flash)"""
+ if peer_addr is not None:
+ self.peers[peer_addr] = fa_addr
+ fa_limit = fa_addr + fa_size
+ if self.plat['flashSize'] and \
+ fa_addr >= self.plat['flashAddr'] and \
+ fa_limit <= self.plat['flashAddr'] + self.plat['flashSize']:
+ # Internal flash
+ self.internal_flash = True
+
+ def add_area(self, title,
+ fa_id, fa_addr, fa_size,
+ img_trailer_size=None, shared_slot=False):
+ """Add flash area to AreaList.
+ Internal/external flash is detected by address.
+ Returns number of sectors in a slot"""
+ if fa_size == 0:
+ print('Empty', title, file=sys.stderr)
+ sys.exit(7)
+
+ fa_limit = fa_addr + fa_size
+ if self.plat['flashSize'] and \
+ fa_addr >= self.plat['flashAddr'] and \
+ fa_limit <= self.plat['flashAddr'] + self.plat['flashSize']:
+ # Internal flash
+ fa_device_id, fa_off, slot_sectors = self.process_int_area(
+ title, fa_addr, fa_size, img_trailer_size, shared_slot)
+ align = self.plat['eraseSize']
+ elif self.plat['smifSize'] and \
+ fa_addr >= self.plat['smifAddr'] and \
+ fa_limit <= self.plat['smifAddr'] + self.plat['smifSize']:
+ # External flash
+ fa_device_id, fa_off, slot_sectors = self.process_ext_area(
+ title, fa_addr, fa_size, img_trailer_size, shared_slot)
+ align = self.flash['eraseSize']
+ else:
+ print('Invalid', title, file=sys.stderr)
+ sys.exit(7)
+
+ if shared_slot:
+ assert img_trailer_size is not None
+ tr_addr = fa_addr + fa_size - img_trailer_size
+ tr_name = self.trailers.get(tr_addr)
+ if tr_name is not None:
+ print('Same trailer address for', title, 'and', tr_name,
+ file=sys.stderr)
+ sys.exit(7)
+ self.trailers[tr_addr] = title
+
+ # Ensure no flash areas on this device will overlap, except the
+ # shared slot
+ for area in self.areas:
+ if fa_device_id == area['fa_device_id']:
+ over = is_overlap(fa_off, fa_size,
+ area['fa_off'], area['fa_size'],
+ align)
+ if shared_slot and area['shared_slot']:
+ if not over: # images in shared slot should overlap
+ print(title, 'is not shared with', area['title'],
+ file=sys.stderr)
+ sys.exit(7)
+ elif over:
+ print(title, 'overlaps with', area['title'],
+ file=sys.stderr)
+ sys.exit(7)
+
+ self.areas.append({'title': title,
+ 'shared_slot': shared_slot,
+ 'fa_id': fa_id,
+ 'fa_device_id': fa_device_id,
+ 'fa_off': fa_off,
+ 'fa_size': fa_size})
+ return slot_sectors
+
+ def generate_c_source(self, params):
+ """Generate C source"""
+ c_array = 'flash_areas'
+
+ try:
+ with open(params.out_file, "w", encoding='UTF-8') as out_f:
+ out_f.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
+ ' ALL CHANGES WILL BE LOST! */\n')
+ out_f.write(f'/* Platform: {params.plat_id} */\n')
+ out_f.write(f'\nstatic struct flash_area {c_array}[] = {{\n')
+ comma = len(self.areas)
+ area_count = 0
+ for area in self.areas:
+ comma -= 1
+ if area['fa_id'] is not None:
+ sss = ' /* Shared secondary slot */' \
+ if area['shared_slot'] else ''
+ out_f.writelines('\n'.join([
+ ' {' + sss,
+ f" .fa_id = {area['fa_id']},",
+ f" .fa_device_id = {area['fa_device_id']},",
+ f" .fa_off = {hex(area['fa_off'])}U,",
+ f" .fa_size = {hex(area['fa_size'])}U",
+ ' },' if comma else ' }', '']))
+ area_count += 1
+ out_f.write('};\n\n'
+ 'struct flash_area *boot_area_descs[] = {\n')
+ for area_index in range(area_count):
+ out_f.write(f' &{c_array}[{area_index}U],\n')
+ out_f.write(' NULL\n};\n')
+ except (FileNotFoundError, OSError):
+ print('Cannot create', params.out_file, file=sys.stderr)
+ sys.exit(4)
+
+
+def cvt_dec_or_hex(val, desc):
+ """Convert (hexa)decimal string to number"""
+ try:
+ return int(val, 0)
+ except ValueError:
+ print('Invalid value', val, 'for', desc, file=sys.stderr)
+ sys.exit(6)
+
+
+def get_val(obj, attr):
+ """Get JSON 'value'"""
+ obj = obj[attr]
+ try:
+ return cvt_dec_or_hex(obj['value'], obj['description'])
+ except KeyError as key:
+ print('Malformed JSON:', key,
+ 'is missing in', "'" + attr + "'",
+ file=sys.stderr)
+ sys.exit(5)
+
+
+def get_bool(obj, attr, def_val=False):
+ """Get JSON boolean value (returns def_val if it missing)"""
+ ret_val = def_val
+ obj = obj.get(attr)
+ if obj is not None:
+ try:
+ val = str(obj['value']).lower()
+ desc = obj['description']
+ if val == 'true':
+ ret_val = True
+ elif val == 'false':
+ ret_val = False
+ else:
+ print('Invalid value', val, 'for', desc, file=sys.stderr)
+ sys.exit(6)
+ except KeyError as key:
+ print('Malformed JSON:', key,
+ 'is missing in', "'" + attr + "'",
+ file=sys.stderr)
+ sys.exit(5)
+ return ret_val
+
+
+class AddrSize:
+ """Bootloader area"""
+
+ def __init__(self, bootloader, addr_name, size_name):
+ self.fa_addr = get_val(bootloader, addr_name)
+ self.fa_size = get_val(bootloader, size_name)
+
+
+def calc_status_size(boot_swap_status_row_sz, max_img_sectors,
+ img_number, scratch_flag=True):
+ """Estimate status size, see swap_status.h"""
+ boot_swap_status_cnt_sz = 4
+ boot_swap_status_crc_sz = 4
+ boot_swap_status_mgcrec_sz = 4
+ boot_swap_status_trailer_size = 64
+ boot_swap_status_payld_sz = \
+ boot_swap_status_row_sz - boot_swap_status_mgcrec_sz - \
+ boot_swap_status_cnt_sz - boot_swap_status_crc_sz
+ boot_swap_status_sect_rows_num = \
+ int((max_img_sectors - 1) //
+ boot_swap_status_payld_sz) + 1
+ boot_swap_status_trail_rows_num = \
+ int((boot_swap_status_trailer_size - 1) //
+ boot_swap_status_payld_sz) + 1
+ boot_swap_status_d_size = \
+ boot_swap_status_row_sz * \
+ (boot_swap_status_sect_rows_num + boot_swap_status_trail_rows_num)
+ boot_swap_status_mult = 2
+ boot_swap_status_size = boot_swap_status_mult * boot_swap_status_d_size
+ status_zone_cnt = 2 * img_number
+ if scratch_flag:
+ status_zone_cnt += 1
+ return boot_swap_status_size * status_zone_cnt
+
+
+def process_json(in_file):
+ """Process JSON"""
+ try:
+ with open(in_file, encoding='UTF-8') as in_f:
+ try:
+ flash_map = json.load(in_f)
+ except ValueError:
+ print('Cannot parse', in_file, file=sys.stderr)
+ sys.exit(4)
+ except (FileNotFoundError, OSError):
+ print('Cannot open', in_file, file=sys.stderr)
+ sys.exit(4)
+ flash = flash_map.get('external_flash')
+ if flash is not None:
+ flash = flash[0]
+ model = flash.get('model')
+ mode = flash.get('mode')
+ if model is not None:
+ try:
+ flash = flashDict[model]
+ except KeyError:
+ print('Supported SPI Flash ICs are:',
+ ', '.join(flashDict.keys()),
+ file=sys.stderr)
+ sys.exit(3)
+ else:
+ try:
+ flash = {'flashSize': cvt_dec_or_hex(flash['flash-size'],
+ 'flash-size'),
+ 'eraseSize': cvt_dec_or_hex(flash['erase-size'],
+ 'erase-size')}
+ except KeyError as key:
+ print('Malformed JSON:', key,
+ "is missing in 'external_flash'",
+ file=sys.stderr)
+ sys.exit(3)
+ flash.update({'XIP': str(mode).upper() == 'XIP'})
+ return flash_map['boot_and_upgrade'], flash
+
+
+def process_images(area_list, boot_and_upgrade):
+ """Process images"""
+ app_count = 0
+ slot_sectors_max = 0
+ all_shared = get_bool(boot_and_upgrade['bootloader'], 'shared_slot')
+ any_shared = all_shared
+
+ apps_flash_map = [None, ]
+
+ for stage in range(2):
+ for app_index in range(1, 5):
+
+ app_flash_map = {}
+
+ try:
+ app_ident = f'application_{app_index}'
+ application = boot_and_upgrade[app_ident]
+ try:
+ primary_addr = get_val(application, 'address')
+ primary_size = get_val(application, 'size')
+ secondary_addr = get_val(application, 'upgrade_address')
+ secondary_size = get_val(application, 'upgrade_size')
+ except KeyError as key:
+ print('Malformed JSON:', key, 'is missing',
+ file=sys.stderr)
+ sys.exit(5)
+ if stage == 0:
+ if primary_size != secondary_size:
+ print('Primary and secondary slot sizes'
+ ' are different for', app_ident,
+ file=sys.stderr)
+ sys.exit(6)
+ area_list.chk_area(primary_addr, primary_size)
+ area_list.chk_area(secondary_addr, secondary_size,
+ primary_addr)
+ else:
+ slot_sectors_max = max(
+ slot_sectors_max,
+ area_list.add_area(
+ f'{app_ident} (primary slot)',
+ f'FLASH_AREA_IMG_{app_index}_PRIMARY',
+ primary_addr, primary_size,
+ area_list.get_img_trailer_size()))
+ shared_slot = get_bool(application, 'shared_slot', all_shared)
+ any_shared = any_shared or shared_slot
+ slot_sectors_max = max(
+ slot_sectors_max,
+ area_list.add_area(
+ f'{app_ident} (secondary slot)',
+ f'FLASH_AREA_IMG_{app_index}_SECONDARY',
+ secondary_addr, secondary_size,
+ area_list.get_img_trailer_size(),
+ shared_slot))
+
+ app_slot_prim = {"address": hex(primary_addr), "size": hex(primary_size)}
+ app_slot_sec = {"address": hex(secondary_addr), "size": hex(secondary_size)}
+
+ app_flash_map.update({"primary": app_slot_prim, "secondary": app_slot_sec})
+ apps_flash_map.append(app_flash_map)
+
+ app_count = app_index
+
+ except KeyError:
+ break
+ if app_count == 0:
+ print('Malformed JSON: no application(s) found',
+ file=sys.stderr)
+ sys.exit(5)
+
+ return app_count, slot_sectors_max, apps_flash_map, any_shared
+
+
+def main():
+ """Flash map converter"""
+ params = CmdLineParams()
+
+ try:
+ plat = platDict[params.plat_id]
+ except KeyError:
+ print('Supported platforms are:', ', '.join(platDict.keys()),
+ file=sys.stderr)
+ sys.exit(2)
+
+ try:
+ boot_and_upgrade, flash = process_json(params.in_file)
+ bootloader = boot_and_upgrade['bootloader']
+ boot = AddrSize(bootloader, 'address', 'size')
+ except KeyError as key:
+ print('Malformed JSON:', key, 'is missing',
+ file=sys.stderr)
+ sys.exit(5)
+
+ try:
+ scratch = AddrSize(bootloader, 'scratch_address', 'scratch_size')
+ except KeyError:
+ scratch = None
+
+ try:
+ swap_status = AddrSize(bootloader, 'status_address', 'status_size')
+ except KeyError:
+ swap_status = None
+
+ # Create flash areas
+ area_list = AreaList(plat, flash, scratch is None and swap_status is None)
+ area_list.add_area('bootloader', 'FLASH_AREA_BOOTLOADER',
+ boot.fa_addr, boot.fa_size)
+
+ # Service RAM app (optional)
+ service_app = boot_and_upgrade.get('service_app')
+ app_binary = None
+ input_params = None
+ app_desc = None
+ if service_app is not None:
+ if plat['flashSize'] > 0:
+ print('service_app is unsupported on this platform',
+ file=sys.stderr)
+ sys.exit(7)
+ try:
+ app_binary = AddrSize(service_app, 'address', 'size')
+ input_params = AddrSize(service_app, 'params_address', 'params_size')
+ app_desc = AddrSize(service_app, 'desc_address', 'desc_size')
+ if input_params.fa_addr != app_binary.fa_addr + app_binary.fa_size or \
+ app_desc.fa_addr != input_params.fa_addr + input_params.fa_size or \
+ app_desc.fa_size != 0x20:
+ print('Malformed service_app definition', file=sys.stderr)
+ sys.exit(7)
+ area_list.add_area('service_app', None, app_binary.fa_addr,
+ app_binary.fa_size + input_params.fa_size + app_desc.fa_size)
+ except KeyError as key:
+ print('Malformed JSON:', key, 'is missing',
+ file=sys.stderr)
+ sys.exit(5)
+
+ # Fill flash areas
+ app_count, slot_sectors_max, apps_flash_map, shared_slot = \
+ process_images(area_list, boot_and_upgrade)
+
+ slot_sectors_max = max(slot_sectors_max, 32)
+
+ if swap_status is not None:
+ status_size_min = calc_status_size(area_list.get_min_erase_size(),
+ slot_sectors_max,
+ app_count,
+ scratch is not None)
+
+ if swap_status.fa_size < status_size_min:
+ print('Insufficient swap status area - suggested size',
+ hex(status_size_min),
+ file=sys.stderr)
+ sys.exit(7)
+ area_list.add_area('swap status partition',
+ 'FLASH_AREA_IMAGE_SWAP_STATUS',
+ swap_status.fa_addr, swap_status.fa_size)
+
+ if scratch is not None:
+ area_list.add_area('scratch area',
+ 'FLASH_AREA_IMAGE_SCRATCH',
+ scratch.fa_addr, scratch.fa_size)
+
+ # Image id parameter is not used for MCUBootApp
+ if params.img_id is None:
+ area_list.generate_c_source(params)
+
+ # Report necessary values back to make
+ print('# AUTO-GENERATED FILE, DO NOT EDIT. ALL CHANGES WILL BE LOST!')
+
+ if params.img_id is not None:
+ primary_img_start = (apps_flash_map[int(params.img_id)].get("primary")).get("address")
+ secondary_img_start = (apps_flash_map[int(params.img_id)].get("secondary")).get("address")
+ bootloader_size = (bootloader.get("size")).get("value")
+ slot_size = (apps_flash_map[int(params.img_id)].get("primary")).get("size")
+
+ print('PRIMARY_IMG_START := ' + primary_img_start)
+ print('SECONDARY_IMG_START := ' + secondary_img_start)
+ print('SLOT_SIZE := ' + slot_size)
+ print('BOOTLOADER_SIZE := ' + bootloader_size)
+ else:
+ print('MCUBOOT_IMAGE_NUMBER :=', app_count)
+ print('MAX_IMG_SECTORS :=', slot_sectors_max)
+
+ if area_list.use_overwrite:
+ print('USE_OVERWRITE := 1')
+ if area_list.external_flash:
+ print('USE_EXTERNAL_FLASH := 1')
+ if area_list.external_flash_xip:
+ print('USE_XIP := 1')
+ if shared_slot:
+ print('USE_SHARED_SLOT := 1')
+ if service_app is not None:
+ print('PLATFORM_SERVICE_APP_OFFSET :=',
+ hex(app_binary.fa_addr - plat['smifAddr']))
+ print('PLATFORM_SERVICE_APP_INPUT_PARAMS_OFFSET :=',
+ hex(input_params.fa_addr - plat['smifAddr']))
+ print('PLATFORM_SERVICE_APP_DESC_OFFSET :=',
+ hex(app_desc.fa_addr - plat['smifAddr']))
+ print('USE_HW_ROLLBACK_PROT := 1')
+
+
+if __name__ == '__main__':
+ main()
diff --git a/boot/cypress/scripts/verbose_make.py b/boot/cypress/scripts/verbose_make.py
new file mode 100644
index 0000000..c9cc037
--- /dev/null
+++ b/boot/cypress/scripts/verbose_make.py
@@ -0,0 +1,49 @@
+"""VERBOSE Makefile Generator
+Copyright (c) 2022 Infineon Technologies AG
+"""
+
+import os
+import re
+import sys
+
+
+def main():
+ """VERBOSE Makefile Generator"""
+ if len(sys.argv) != 2:
+ print(f'Usage: {sys.argv[0]} <makefile>\n', file=sys.stderr)
+ sys.exit(1)
+
+ with open(sys.argv[1], 'r', encoding='UTF-8') as mk_file:
+ mk_vars = {}
+
+ for line in mk_file:
+ line = line.strip()
+
+ if re.search(r'\s*#', line): # skip comments
+ continue
+
+ match = re.search(r'^\t*([A-Za-z_]\w+)\s*[+:?]=', line)
+ if match: # set variable
+ var = match.group(1)
+ mk_vars[var] = 1 | mk_vars.get(var, 0)
+
+ match = re.findall(r'\$\(([A-Za-z_]\w+)\)', line)
+ for var in match: # get variable(s)
+ mk_vars[var] = 2 | mk_vars.get(var, 0)
+
+ if mk_vars.get('VERBOSE'):
+ del mk_vars['VERBOSE']
+
+ print('''\
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)''')
+ print(f'$(info #### {os.path.basename(sys.argv[1])} ####)')
+ dirs = (None, '-->', '<--', '<->')
+ for var in sorted(mk_vars.keys()):
+ print(f'$(info {var} {dirs[mk_vars[var]]} $({var}))')
+ print('endif')
+
+
+if __name__ == '__main__':
+ main()
diff --git a/boot/cypress/toolchains.mk b/boot/cypress/toolchains.mk
index 970f325..2e20404 100644
--- a/boot/cypress/toolchains.mk
+++ b/boot/cypress/toolchains.mk
@@ -23,7 +23,7 @@
# limitations under the License.
################################################################################
-include common_libs.mk
+include host.mk
# Compilers
GCC_ARM := 1
@@ -31,27 +31,16 @@
ARM := 3
OTHER := 4
-ifeq ($(MAKEINFO), 1)
+ifeq ($(VERBOSE), 1)
$(info $(COMPILER))
endif
-# Detect host OS to make resolving compiler pathes easier
-UNAME_S := $(shell uname -s)
-ifeq ($(UNAME_S), Darwin)
- HOST_OS = osx
-else
- ifeq ($(UNAME_S), Linux)
- HOST_OS = linux
- else
- HOST_OS = win
- endif
-endif
# Path to the compiler installation
# NOTE: Absolute pathes for now for the sake of development
ifeq ($(HOST_OS), win)
ifeq ($(COMPILER), GCC_ARM)
- TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/ModusToolbox/tools_2.2/gcc
- MY_TOOLCHAIN_PATH:=$(subst \,/,$(TOOLCHAIN_PATH))
+ TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/ModusToolbox/tools_2.3/gcc
+ MY_TOOLCHAIN_PATH := $(call get_os_path, $(TOOLCHAIN_PATH))
TOOLCHAIN_PATH := $(MY_TOOLCHAIN_PATH)
GCC_PATH := $(TOOLCHAIN_PATH)
# executables
@@ -82,23 +71,31 @@
# Set flags for toolchain executables
ifeq ($(COMPILER), GCC_ARM)
# set build-in compiler flags
- CFLAGS_COMMON := -mcpu=cortex-$(CORE_SIFFX) -mthumb -mfloat-abi=soft -fno-stack-protector -ffunction-sections -fdata-sections -ffat-lto-objects -fstrict-aliasing -g -Wall -Wextra
- # preset default level of optimization - can be changed in application.mk
+ CFLAGS_COMMON := -mthumb -ffunction-sections -fdata-sections -g -Wall -Wextra
ifeq ($(BUILDCFG), Debug)
- CFLAGS_OPTIMIZATION ?= -Og -g3
+ CFLAGS_SPECIAL ?= -Og -g3
+ CFLAGS_COMMON += $(CFLAGS_SPECIAL)
else ifeq ($(BUILDCFG), Release)
- CFLAGS_OPTIMIZATION ?= -Os -g
+ CFLAGS_COMMON += -Os -g -DNDEBUG
else
$(error BUILDCFG : '$(BUILDCFG)' is not supported)
endif
- # add defines and includes
- CFLAGS := $(CFLAGS_COMMON) $(INCLUDES)
+
+ # ifeq ($(CORE), CM33)
+ # CFLAGS_PLATFORM := -c -mcpu=cortex-m33+nodsp --specs=nano.specs
+ # else
+ # CFLAGS_PLATFORM := -mcpu=cortex-$(CORE_SUFFIX) -mfloat-abi=soft -fno-stack-protector -fstrict-aliasing
+ # endif
+
+ # $CFLAGS_PLATFORM is defined in plaform specific mk file
+ CFLAGS := $(CFLAGS_COMMON) $(CFLAGS_PLATFORM) $(INCLUDES)
+
CC_DEPEND = -MD -MP -MF
- LDFLAGS_COMMON := -mcpu=cortex-$(CORE_SIFFX) -mthumb -specs=nano.specs -ffunction-sections -fdata-sections -Wl,--gc-sections -L "$(GCC_PATH)/lib/gcc/arm-none-eabi/7.2.1/thumb/v6-m" -ffat-lto-objects -g --enable-objc-gc
+ LDFLAGS_COMMON := -mcpu=cortex-$(CORE_SUFFIX) -mthumb -specs=nano.specs -ffunction-sections -fdata-sections -Wl,--gc-sections -ffat-lto-objects -g --enable-objc-gc
ifeq ($(BUILDCFG), Debug)
- # preset default level of optimization - can be changed in application.mk
- LDFLAGS_OPTIMIZATION ?= -Og
+ LDFLAGS_SPECIAL ?= -Og
+ LDFLAGS_COMMON += $(LDFLAGS_SPECIAL)
else ifeq ($(BUILDCFG), Release)
LDFLAGS_OPTIMIZATION ?= -Os
else
@@ -107,3 +104,36 @@
LDFLAGS_NANO := -L "$(GCC_PATH)/arm-none-eabi/lib/thumb/v6-m"
LDFLAGS := $(LDFLAGS_COMMON) $(LDFLAGS_NANO)
endif
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### toolchains.mk ####)
+$(info ARM --> $(ARM))
+$(info BUILDCFG <-- $(BUILDCFG))
+$(info CC <-> $(CC))
+$(info CFLAGS --> $(CFLAGS))
+$(info CFLAGS_COMMON <-> $(CFLAGS_COMMON))
+$(info CFLAGS_PLATFORM <-- $(CFLAGS_PLATFORM))
+$(info CFLAGS_SPECIAL <-> $(CFLAGS_SPECIAL))
+$(info COMPILER <-- $(COMPILER))
+$(info CORE_SUFFIX <-- $(CORE_SUFFIX))
+$(info GCC_ARM --> $(GCC_ARM))
+$(info GCC_PATH <-> $(GCC_PATH))
+$(info HOST_OS <-- $(HOST_OS))
+$(info IAR --> $(IAR))
+$(info INCLUDES <-- $(INCLUDES))
+$(info LD --> $(LD))
+$(info LDFLAGS --> $(LDFLAGS))
+$(info LDFLAGS_COMMON <-> $(LDFLAGS_COMMON))
+$(info LDFLAGS_NANO <-> $(LDFLAGS_NANO))
+$(info LDFLAGS_OPTIMIZATION --> $(LDFLAGS_OPTIMIZATION))
+$(info LDFLAGS_SPECIAL <-> $(LDFLAGS_SPECIAL))
+$(info MY_TOOLCHAIN_PATH <-> $(MY_TOOLCHAIN_PATH))
+$(info OBJCOPY --> $(OBJCOPY))
+$(info OBJDUMP --> $(OBJDUMP))
+$(info OTHER --> $(OTHER))
+$(info PDL_ELFTOOL --> $(PDL_ELFTOOL))
+$(info TOOLCHAIN_PATH <-> $(TOOLCHAIN_PATH))
+$(info USERNAME <-- $(USERNAME))
+endif