commit c8d67f10b114b06e35af13278f314a8fed3b57f3
author Fabio Utzig <utzig@apache.org> Fri Dec 14 06:45:23 2018 -0200
committer Fabio Utzig <utzig@utzig.org> Mon Dec 17 14:41:02 2018 -0200
tree 08dcd5aca400e51fd0f24315906cbd679860cfe2
parent 04fd63e6bac91b011c1276f6289b66bf9524ce95

Add TLV gen for RSA sig+enc

Signed-off-by: Fabio Utzig <utzig@apache.org>

sim/src/lib.rs

diff --git a/sim/src/lib.rs b/sim/src/lib.rs
index 47d20eb..72d0636 100644
--- a/sim/src/lib.rs
+++ b/sim/src/lib.rs
@@ -1139,6 +1139,7 @@
 
 // The TLV in use depends on what kind of signature we are verifying.
 #[cfg(feature = "sig-rsa")]
+#[cfg(not(feature = "enc-rsa"))]
 fn make_tlv() -> TlvGen {
     TlvGen::new_rsa_pss()
 }
@@ -1148,11 +1149,18 @@
     TlvGen::new_ecdsa()
 }
 
+#[cfg(not(feature = "sig-rsa"))]
 #[cfg(feature = "enc-rsa")]
 fn make_tlv() -> TlvGen {
     TlvGen::new_enc_rsa()
 }
 
+#[cfg(feature = "sig-rsa")]
+#[cfg(feature = "enc-rsa")]
+fn make_tlv() -> TlvGen {
+    TlvGen::new_sig_enc_rsa()
+}
+
 #[cfg(feature = "enc-kw")]
 fn make_tlv() -> TlvGen {
     TlvGen::new_enc_kw()