diff --git a/boot/espressif/hal/CMakeLists.txt b/boot/espressif/hal/CMakeLists.txt
index 03d6e0d..db82d83 100644
--- a/boot/espressif/hal/CMakeLists.txt
+++ b/boot/espressif/hal/CMakeLists.txt
@@ -7,11 +7,13 @@
 set(SRC_DIR ${CMAKE_CURRENT_LIST_DIR}/src)
 set(INCLUDE_DIRS
     ${CMAKE_CURRENT_LIST_DIR}/include
-    ${CMAKE_CURRENT_LIST_DIR}/include/${MCUBOOT_TARGET})
+    ${CMAKE_CURRENT_LIST_DIR}/include/${MCUBOOT_TARGET}
+    )
 
 list(APPEND INCLUDE_DIRS
     ${esp_idf_dir}/components/esp_common/include
     ${esp_idf_dir}/components/esp_rom/include
+    ${esp_idf_dir}/components/esp_rom/include/${MCUBOOT_TARGET}
     ${esp_idf_dir}/components/xtensa/${MCUBOOT_TARGET}/include
     ${esp_idf_dir}/components/spi_flash/include
     ${esp_idf_dir}/components/spi_flash/private_include
@@ -21,6 +23,7 @@
     ${esp_idf_dir}/components/soc/include
     ${esp_idf_dir}/components/esp_hw_support/include
     ${esp_idf_dir}/components/hal/${MCUBOOT_TARGET}/include
+    ${esp_idf_dir}/components/hal/${MCUBOOT_TARGET}/include/hal
     ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}
     ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/private_include
     ${esp_idf_dir}/components/bootloader_support/include
@@ -30,8 +33,8 @@
     ${esp_idf_dir}/components/efuse/${MCUBOOT_TARGET}/include
     )
 set(hal_srcs
-    ${SRC_DIR}/bootloader_init.c
     ${SRC_DIR}/bootloader_wdt.c
+    ${SRC_DIR}/${MCUBOOT_TARGET}/bootloader_init.c
     ${esp_idf_dir}/components/hal/mpu_hal.c
     ${esp_idf_dir}/components/bootloader_support/src/bootloader_flash.c
     ${esp_idf_dir}/components/bootloader_support/src/bootloader_flash_config_${MCUBOOT_TARGET}.c
@@ -50,6 +53,12 @@
     ${esp_idf_dir}/components/${MCUBOOT_TARGET}/clk.c
     )
 
+if ("${MCUBOOT_TARGET}" STREQUAL "esp32s2")
+    list(APPEND hal_srcs
+        ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/regi2c_ctrl.c
+    )
+endif()
+
 set(CFLAGS
     "-nostdlib"
     "-mlongcalls"
@@ -97,6 +106,7 @@
 set_source_files_properties(
     ${esp_idf_dir}/components/bootloader_support/src/bootloader_flash.c
     ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/rtc_clk_init.c
+    ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/rtc_init.c
     ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/rtc_clk.c
     ${esp_idf_dir}/components/esp_hw_support/port/${MCUBOOT_TARGET}/rtc_time.c
     PROPERTIES COMPILE_FLAGS
@@ -114,13 +124,23 @@
     ${CFLAGS}
     )
 
-target_link_libraries(
-    hal
-    PUBLIC
-    ${LDFLAGS}
+set(LINKER_SCRIPTS
     -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.ld
     -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.libgcc.ld
     -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.api.ld
     -T${esp_idf_dir}/components/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.peripherals.ld
     -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.newlib-funcs.ld
     )
+
+if ("${MCUBOOT_TARGET}" STREQUAL "esp32s2")
+    list(APPEND LINKER_SCRIPTS
+        -T${esp_idf_dir}/components/esp_rom/${MCUBOOT_TARGET}/ld/${MCUBOOT_TARGET}.rom.spiflash.ld
+    )
+endif()
+
+target_link_libraries(
+    hal
+    PUBLIC
+    ${LDFLAGS}
+    ${LINKER_SCRIPTS}
+    )
diff --git a/boot/espressif/hal/include/esp32s2/sdkconfig.h b/boot/espressif/hal/include/esp32s2/sdkconfig.h
new file mode 100644
index 0000000..b4114f3
--- /dev/null
+++ b/boot/espressif/hal/include/esp32s2/sdkconfig.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define BOOTLOADER_BUILD 1
+#define CONFIG_IDF_TARGET_ESP32S2 1
+#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
+#define CONFIG_ESP32S2_XTAL_FREQ 40
+#define CONFIG_MCUBOOT 1
+#define NDEBUG 1
+#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000
+#define CONFIG_ESP_CONSOLE_UART_BAUDRATE 115200
+#define CONFIG_BOOTLOADER_OFFSET_IN_FLASH 0x1000
diff --git a/boot/espressif/hal/include/mcuboot_config/mcuboot_logging.h b/boot/espressif/hal/include/mcuboot_config/mcuboot_logging.h
index 1968cec..2c69a14 100644
--- a/boot/espressif/hal/include/mcuboot_config/mcuboot_logging.h
+++ b/boot/espressif/hal/include/mcuboot_config/mcuboot_logging.h
@@ -6,6 +6,8 @@
 
 #pragma once
 
+#include "sdkconfig.h"
+
 extern int ets_printf(const char *fmt, ...);
 
 #define MCUBOOT_LOG_LEVEL_OFF      0
@@ -14,8 +16,10 @@
 #define MCUBOOT_LOG_LEVEL_INFO     3
 #define MCUBOOT_LOG_LEVEL_DEBUG    4
 
-#if (MCUBOOT_TARGET == esp32)
+#if CONFIG_IDF_TARGET_ESP32
 #define TARGET "[esp32]"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#define TARGET "[esp32s2]"
 #else
 #error "Selected target not supported."
 #endif
diff --git a/boot/espressif/hal/src/bootloader_init.c b/boot/espressif/hal/src/esp32/bootloader_init.c
similarity index 97%
rename from boot/espressif/hal/src/bootloader_init.c
rename to boot/espressif/hal/src/esp32/bootloader_init.c
index 8ffe15c..0e77ecb 100644
--- a/boot/espressif/hal/src/bootloader_init.c
+++ b/boot/espressif/hal/src/esp32/bootloader_init.c
@@ -23,10 +23,10 @@
 
 #include "hal/wdt_hal.h"
 
-#include "esp32/rom/cache.h"
-#include "esp32/rom/ets_sys.h"
-#include "esp32/rom/spi_flash.h"
-#include "esp32/rom/uart.h"
+#include "rom/cache.h"
+#include "rom/ets_sys.h"
+#include "rom/spi_flash.h"
+#include "rom/uart.h"
 
 esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
 
diff --git a/boot/espressif/hal/src/bootloader_init.c b/boot/espressif/hal/src/esp32s2/bootloader_init.c
similarity index 66%
copy from boot/espressif/hal/src/bootloader_init.c
copy to boot/espressif/hal/src/esp32s2/bootloader_init.c
index 8ffe15c..8bc91ba 100644
--- a/boot/espressif/hal/src/bootloader_init.c
+++ b/boot/espressif/hal/src/esp32s2/bootloader_init.c
@@ -10,6 +10,9 @@
 #include "esp_attr.h"
 #include "esp_image_format.h"
 
+#include "esp_rom_efuse.h"
+#include "esp_rom_gpio.h"
+
 #include "bootloader_init.h"
 #include "bootloader_mem.h"
 #include "bootloader_clock.h"
@@ -20,13 +23,15 @@
 #include "soc/dport_reg.h"
 #include "soc/efuse_reg.h"
 #include "soc/rtc.h"
+#include "soc/extmem_reg.h"
+#include "soc/io_mux_reg.h"
 
 #include "hal/wdt_hal.h"
 
-#include "esp32/rom/cache.h"
-#include "esp32/rom/ets_sys.h"
-#include "esp32/rom/spi_flash.h"
-#include "esp32/rom/uart.h"
+#include "rom/cache.h"
+#include "rom/ets_sys.h"
+#include "rom/spi_flash.h"
+#include "rom/uart.h"
 
 esp_image_header_t WORD_ALIGNED_ATTR bootloader_image_hdr;
 
@@ -35,54 +40,15 @@
     memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
 }
 
-static void bootloader_common_vddsdio_configure(void)
-{
-    rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
-    if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) {    /* VDDSDIO regulator is enabled @ 1.8V */
-        cfg.drefh = 3;
-        cfg.drefm = 3;
-        cfg.drefl = 3;
-        cfg.force = 1;
-        rtc_vddsdio_set_config(cfg);
-        ets_delay_us(10); /* wait for regulator to become stable */
-    }
-}
-
 static void bootloader_reset_mmu(void)
 {
-    /* completely reset MMU in case serial bootloader was running */
-    Cache_Read_Disable(0);
-#if !CONFIG_FREERTOS_UNICORE
-    Cache_Read_Disable(1);
-#endif
-    Cache_Flush(0);
-#if !CONFIG_FREERTOS_UNICORE
-    Cache_Flush(1);
-#endif
-    mmu_init(0);
-#if !CONFIG_FREERTOS_UNICORE
-    /* The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
-        necessary to work around a hardware bug. */
-    DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
-    mmu_init(1);
-    DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
-#endif
+    Cache_Suspend_ICache();
+    Cache_Invalidate_ICache_All();
+    Cache_MMU_Init();
 
     /* normal ROM boot exits with DROM0 cache unmasked,
-        but serial bootloader exits with it masked. */
-    DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
-#if !CONFIG_FREERTOS_UNICORE
-    DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
-#endif
-}
-
-static esp_err_t bootloader_check_rated_cpu_clock(void)
-{
-    int rated_freq = bootloader_clock_get_rated_freq_mhz();
-    if (rated_freq < 80) {
-        return ESP_FAIL;
-    }
-    return ESP_OK;
+    but serial bootloader exits with it masked. */
+    REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_DROM0);
 }
 
 esp_err_t bootloader_read_bootloader_header(void)
@@ -115,18 +81,44 @@
     default:
         size = 2;
     }
-    Cache_Read_Disable(0);
-    /* Set flash chip size */
+    uint32_t autoload = Cache_Suspend_ICache();
+    // Set flash chip size
     esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
-    /* TODO: set mode */
-    /* TODO: set frequency */
-    Cache_Flush(0);
-    Cache_Read_Enable(0);
+    Cache_Resume_ICache(autoload);
+}
+
+void IRAM_ATTR bootloader_configure_spi_pins(int drv)
+{
+    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
+    uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
+    if (spiconfig != 0) {
+        clk_gpio_num = spiconfig         & 0x3f;
+        q_gpio_num = (spiconfig >> 6)    & 0x3f;
+        d_gpio_num = (spiconfig >> 12)   & 0x3f;
+        cs0_gpio_num = (spiconfig >> 18) & 0x3f;
+        hd_gpio_num = (spiconfig >> 24)  & 0x3f;
+        wp_gpio_num = wp_pin;
+    }
+    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
+    if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
+        esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
+    }
+    if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
+        esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
+    }
 }
 
 static void IRAM_ATTR bootloader_init_flash_configure(void)
 {
-    bootloader_flash_gpio_config(&bootloader_image_hdr);
     bootloader_flash_dummy_config(&bootloader_image_hdr);
     bootloader_flash_cs_timing_config();
 }
@@ -166,7 +158,7 @@
 {
     const int uart_num = 0;
 
-    uartAttach();
+    uartAttach(NULL);
     ets_install_uart_printf();
     uart_tx_wait_idle(0);
 
@@ -174,10 +166,15 @@
     uart_div_modify(uart_num, (rtc_clk_apb_freq_get() << 4) / uart_baud);
 }
 
+static void bootloader_super_wdt_auto_feed(void)
+{
+    REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
+}
 
 esp_err_t bootloader_init(void)
 {
     esp_err_t ret = ESP_OK;
+    bootloader_super_wdt_auto_feed();
 
     bootloader_init_mem();
 
@@ -186,20 +183,12 @@
     {
         assert(&_bss_start <= &_bss_end);
         assert(&_data_start <= &_data_end);
-        assert(sp < &_bss_start);
-        assert(sp < &_data_start);
     }
 #endif
     /* clear bss section */
     bootloader_clear_bss_section();
-    /* bootst up vddsdio */
-    bootloader_common_vddsdio_configure();
     /* reset MMU */
     bootloader_reset_mmu();
-    /* check rated CPU clock */
-    if ((ret = bootloader_check_rated_cpu_clock()) != ESP_OK) {
-        goto err;
-    }
     /* config clock */
     bootloader_clock_configure();
     /* initialize uart console, from now on, we can use ets_printf */