diff --git a/boot/cypress/.gitignore b/boot/cypress/.gitignore
index 5c96f68..1579283 100644
--- a/boot/cypress/.gitignore
+++ b/boot/cypress/.gitignore
@@ -27,9 +27,9 @@
 /scripts/*.egg
 
 # Pre_build autogenerated files
-MCUBootApp/flashmap.mk
-BlinkyApp/flashmap.mk
-platforms/cy_flash_pal/cy_flash_map.h
+MCUBootApp/memorymap.mk
+BlinkyApp/memorymap.mk
+platforms/memory/memorymap.h
 
 # Build dirs
 *out/*/*
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.md b/boot/cypress/BlinkyApp/BlinkyApp.md
index 4586a2c..dc29c4c 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.md
+++ b/boot/cypress/BlinkyApp/BlinkyApp.md
@@ -28,7 +28,7 @@
 
 `FLASH_MAP` `make` parameter is used to provide an input file for pre-build action. Refer to `MCUBootApp.md` for details.
 
-The result of the pre-build script is an auto-generated `flashmap.mk` file with a set of makefile flags:
+The result of the pre-build script is an auto-generated `memorymap.mk` file with a set of makefile flags:
 
 `PRIMARY_IMG_START` - start address of the primary image in flash, this value is defined in the JSON flash map as the `"value"` field of the address section for `"application_#"`.
 
@@ -57,7 +57,9 @@
 
 Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE 3.0**:
 
-    make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/$(USERNAME)/ModusToolbox/tools_3.0/gcc
+    make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.0/gcc
+
+    make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 APP_CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1 TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.0/gcc
 
 The supported platforms:
 
@@ -66,6 +68,8 @@
 * PSOC_062_512K
 * PSOC_063_1M
 * CYW20829
+* XMC7200
+* XMC7100
 
 The root directory is boot/cypress.
 Since BlinkyApp built for BOOT or UPGRADE slot has its own folder BlinkyApp/out/boot or BlinkyApp/out/upgrade consider using following jobs to clear build folder before build.
@@ -75,7 +79,7 @@
  - **clean_boot** - to clean the BOOT image directory
  - **clean_upgrade** - to clean the UPGRADE image directory.   
  
-These jobs also remove auto-generated files 'flashmap.mk' and 'cy_flash_map.h', which is required to eliminate possible errors.   
+These jobs also remove auto-generated files 'memorymap.mk' and 'memory.h', which is required to eliminate possible errors.   
 
 **Upgrade mode dependency**
 
@@ -83,21 +87,25 @@
 To build `BlinkyApp` for different upgrade modes choose flash map JSON file with the corresponding suffix - either `_swap_` or `_overwrite_`.  
 But hold in the mind, that `MCUBootApp` and `BlinkyApp` should use the same flash map file!  
 For example: to building `MCUBootApp` and `BlinkyApp` in the 'single overwride' mode use the flash map file:   
-`FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json`  
+`FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_single.json`  
 
 **Single-image**
 
 The following command will build BlinkyApp as a regular HEX file for the primary (BOOT) slot to be used in a single image case with `swap` upgrade type of Bootloader:
 
-    make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json IMG_ID=1
+    make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json IMG_ID=1
+
+    make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 APP_CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1
 
 To build an image for the secondary (UPGRADE) slot to be used in a single image case with `swap` upgrade type of Bootloader:
 
-    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json IMG_ID=1
+    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json IMG_ID=1
+
+    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 APP_CORE=CM7 CORE_ID=0 IMG_TYPE=UPGRADE IMG_ID=1
 
 To build an image for the secondary (UPGRADE) slot to be used in a single image case with `overwrite` upgrade type of Bootloader:
 
-    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json IMG_ID=1
+    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_single.json IMG_ID=1
 
 **Multi-image**
 
@@ -109,7 +117,7 @@
 
 `IMG_ID` flag value should correspond to the `application_#` number of JSON flash map file used for the build. For example, to build `BlinkyApp` for the UPGRADE slot of the second image following command is used:
 
-    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json IMG_ID=2
+    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_single.json IMG_ID=2
 
 When this option is omitted, `IMG_ID=1` is assumed.    
 
@@ -120,13 +128,13 @@
 
 To build a `BlinkyApp` upgrade image for external memory to be used in a single image configuration with overwrite upgrade mode, use the command:
 
-    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single_smif.json IMG_ID=1
+    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_single_smif.json IMG_ID=1
 
 `ERASED_VALUE` defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S. For `CYW20289` default value is `0xff` since it only uses an external flash.
 
 In the multi-image configuration, an upgrade image for the second application is built using the command:
 
-    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi_smif.json IMG_ID=2
+    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_multi_smif.json IMG_ID=2
 
 **Encrypted upgrade image**
 
@@ -134,7 +142,7 @@
 
 To obtain an encrypted upgrade image of BlinkyApp, pass extra flag `ENC_IMG=1` in the command line, for example:
 
-    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json IMG_ID=1 ENC_IMG=1
+    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_single.json IMG_ID=1 ENC_IMG=1
 
 This also suggests that the user has already placed a corresponding *.pem key in the \keys folder. The key variables are defined in the root Makefile as SIGN_KEY_FILE and ENC_KEY_FILE
 
@@ -152,6 +160,8 @@
     - `PSOC_062_1M`
     - `PSOC_062_512K`
     - `CYW20289`
+    - `XMC7200`
+    - `XMC7100`
 - `SLOT_SIZE` - The size of the primary/secondary slot of MCUBootApp. This app will be used with
     - 0x%VALUE%
 - `IMG_TYPE` - The slot of MCUBootApp, for which the image is being built.
@@ -164,7 +174,7 @@
     - Example: TOOLCHAIN_PATH=/home/user/ModusToolbox/tools_2.4/gcc
     - Example: TOOLCHAIN_PATH=C:/ModusToolbox/tools_2.4/gcc
 
-Flags are set by pre-build action. Result of pre-build can be found in autogenerated file `BlinkyApp/flashmap.mk`.   
+Flags are set by pre-build action. Result of pre-build can be found in autogenerated file `BlinkyApp/memorymap.mk`.   
 
 - `USE_OVERWRITE` - Define the Upgrade mode type of `MCUBootApp` to use with this app.
     - `1` - For Overwrite mode.
@@ -178,7 +188,7 @@
 
 ### Post-build
 
-The post-build action is executed at the compile time for `BlinkyApp`. For the `PSOC_062_2M`, `PSOC_062_1M`, `PSOC_062_512K` platforms, it calls `imgtool` from `MCUboot` scripts and adds a signature to the compiled image.
+The post-build action is executed at the compile time for `BlinkyApp`. For the `XMC7200` `XMC7100` `PSOC_062_2M`, `PSOC_062_1M`, `PSOC_062_512K` platforms, it calls `imgtool` from `MCUboot` scripts and adds a signature to the compiled image.
 
 Flags passed to `imgtool` for a signature are defined in the `SIGN_ARGS` variable in BlinkyApp.mk.
 
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.mk b/boot/cypress/BlinkyApp/BlinkyApp.mk
index d7769cf..905ef47 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.mk
+++ b/boot/cypress/BlinkyApp/BlinkyApp.mk
@@ -33,24 +33,14 @@
 COMPILER ?= GCC_ARM
 IMG_TYPE ?= BOOT
 IMG_ID ?= 1
+USE_HW_KEY ?= 0
 
 # image type can be BOOT or UPGRADE
 IMG_TYPES = BOOT UPGRADE
 
 CUR_APP_PATH = $(PRJ_DIR)/$(APP_NAME)
 
-ifneq ($(FLASH_MAP), )
-#to compare NV-counters for each images with number of images on CYW20829
-ifeq ($(PLATFORM), CYW20829)
-$(CUR_APP_PATH)/flashmap.mk:
-	$(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/cy_flash_pal/cy_flash_map.h -d $(IMG_ID) -c $(PRJ_DIR)/policy/policy_reprovisioning_secure.json > $(CUR_APP_PATH)/flashmap.mk
-else
-$(CUR_APP_PATH)/flashmap.mk:
-	$(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/cy_flash_pal/cy_flash_map.h -d $(IMG_ID) > $(CUR_APP_PATH)/flashmap.mk
-endif
-include $(CUR_APP_PATH)/flashmap.mk
-DEFINES_APP := -DCY_FLASH_MAP_JSON
-endif
+-include $(CUR_APP_PATH)/memorymap.mk
 
 # TODO: optimize here and in MCUBootApp.mk
 # Output folder
@@ -78,7 +68,32 @@
 endif
 
 include $(PRJ_DIR)/platforms.mk
+
+ifneq ($(FLASH_MAP), )
+ifeq ($(FAMILY), CYW20829)
+$(CUR_APP_PATH)/memorymap.mk:
+	$(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -c $(PRJ_DIR)/policy/policy_secure.json -d $(IMG_ID) -c $(PRJ_DIR)/policy/policy_reprovisioning_secure.json > $(CUR_APP_PATH)/memorymap.mk
+else ifeq ($(FAMILY), XMC7000)
+$(CUR_APP_PATH)/memorymap.mk:
+	$(PYTHON_PATH) scripts/memorymap_rework.py run -p $(PLATFORM_CONFIG) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory -n memorymap -d $(IMG_ID) > $(CUR_APP_PATH)/memorymap.mk
+else
+$(CUR_APP_PATH)/memorymap.mk:
+	$(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -d $(IMG_ID) > $(CUR_APP_PATH)/memorymap.mk
+endif
+DEFINES_APP += -DCY_FLASH_MAP_JSON
+endif
+
 include $(PRJ_DIR)/common_libs.mk
+
+#Blinky Release XIP mode workaround
+ifneq ($(PLATFORM), CYW20829)
+ifeq ($(BUILDCFG), Release)
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+CFLAGS_OPTIMIZATION := -Og -g3
+endif
+endif
+endif
+
 include $(PRJ_DIR)/toolchains.mk
 
 # use USE_OVERWRITE = 1 for overwrite only mode
@@ -116,13 +131,18 @@
 USER_APP_RAM_SIZE ?= $(PLATFORM_DEFAULT_RAM_SIZE)
 endif
 
+DEFINES_APP += -DMCUBOOT_IMAGE_NUMBER=$(MCUBOOT_IMAGE_NUMBER)
 DEFINES_APP += -DUSER_APP_RAM_START=$(USER_APP_RAM_START)
 DEFINES_APP += -DUSER_APP_RAM_SIZE=$(USER_APP_RAM_SIZE)
 DEFINES_APP += -DUSER_APP_START=$(USER_APP_START)
 DEFINES_APP += -DPRIMARY_IMG_START=$(PRIMARY_IMG_START)
 DEFINES_APP += -DUSER_APP_SIZE=$(SLOT_SIZE)
 DEFINES_APP += -DAPP_$(APP_CORE)
+DEFINES_APP += -DBOOT_$(APP_CORE)
+DEFINES_APP += -DAPP_CORE_ID=$(APP_CORE_ID)
 DEFINES_APP += $(PLATFORM_DEFINES_APP)
+DEFINES_APP += -DMEMORY_ALIGN=$(PLATFORM_MEMORY_ALIGN)
+DEFINES_APP += -DPLATFORM_MAX_TRAILER_PAGE_SIZE=$(PLATFORM_MAX_TRAILER_PAGE_SIZE)
 
 #Use default led if no command line parameter added
 ifeq ($(LED_PORT), )
@@ -150,11 +170,13 @@
 DEFINES_APP += -DCY_DEBUG_UART_RX=$(UART_RX)
 endif
 
+ifeq ($(USE_EXTERNAL_FLASH), 1)
 ifeq ($(USE_XIP), 1)
 DEFINES_APP += -DUSE_XIP
-DEFINES_APP += -DCY_BOOT_USE_EXTERNAL_FLASH
 LD_SUFFIX = _xip
 endif
+DEFINES_APP += -DCY_BOOT_USE_EXTERNAL_FLASH
+endif
 
 # Add version metadata to image
 ifneq ($(IMG_VER), )
@@ -175,6 +197,7 @@
 
 # Collect Test Application sources
 SOURCES_APP_SRC := $(wildcard $(CUR_APP_PATH)/*.c)
+SOURCES_APP_SRC += $(PLATFORM_APP_SOURCES)
 
 # Set offset for secondary image
 ifeq ($(IMG_TYPE), UPGRADE)
@@ -191,6 +214,7 @@
 INCLUDE_DIRS_APP := $(addprefix -I, $(CURDIR))
 INCLUDE_DIRS_APP += $(addprefix -I, $(CUR_APP_PATH))
 INCLUDE_DIRS_APP += $(addprefix -I, $(PLATFORM_INCLUDE_DIRS_FLASH))
+INCLUDE_DIRS_APP += $(addprefix -I, $(PLATFORM_INCLUDE_DIRS_UTILS))
 
 # ++++
 INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/MCUBootApp/config)
@@ -221,6 +245,7 @@
 # add flag to imgtool if not using swap for upgrade
 ifeq ($(USE_OVERWRITE), 1)
 UPGRADE_TYPE := --overwrite-only
+DEFINES_APP += -DMCUBOOT_OVERWRITE_ONLY
 endif
 
 ifeq ($(BOOT_RECORD_SW_TYPE), )
@@ -236,6 +261,11 @@
 
 SIGN_ARGS := $(PLATFORM_SIGN_ARGS) $(IMG_VER_ARG) $(IMG_DEPS_ARG)
 
+# Include full public key to signed image TLV insted of its hash
+ifeq ($(USE_HW_KEY), 1)
+SIGN_ARGS += --public-key-format
+endif
+
 # Set parameters needed for signing
 ifeq ($(IMG_TYPE), UPGRADE)
 	# Set img_ok flag to trigger swap type permanent
diff --git a/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_boot_2M.launch b/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_boot_2M.launch
new file mode 100644
index 0000000..ea1d541
--- /dev/null
+++ b/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_boot_2M.launch
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="run"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set remotetimeout 15"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${cy_tools_path:openocd}/bin/openocd"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s &quot;${openocd_path}/../scripts&quot;&#13;&#10;-s &quot;${cy_prj_path}/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg&quot;&#13;&#10;-c &quot;source [find interface/kitprog3.cfg]&quot;&#13;&#10;-c &quot;puts stderr {Started by GNU MCU Eclipse}&quot;&#13;&#10;-c &quot;source [find target/psoc6_2m.cfg]&quot;&#13;&#10;-c &quot;psoc6.cpu.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1&quot;&#13;&#10;-c &quot;gdb_port 3332&quot;&#13;&#10;-c &quot;psoc6 sflash_restrictions 1&quot;&#13;&#10;-c &quot;init; reset init&quot;"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="run"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="/Users/rnok/repos/cy_mcuboot_project/cy_mcuboot/boot/cypress/BlinkyApp/out/boot/CY8CKIT-064S2-4343W/Debug/BlinkyApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="${cy_prj_path}/boot/cypress/BlinkyApp/out/PSOC_062_2M/Debug/boot/BlinkyApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_tools_path:CY_TOOL_arm-none-eabi-gdb_EXE}"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${cy_prj_path}/boot/cypress/BlinkyApp/out/PSOC_062_2M/Debug/boot/BlinkyApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="cy_mcuboot"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.1249144476"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/cy_mcuboot"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;&gt;&#10;    &lt;memoryBlockExpression address=&quot;268566528&quot; label=&quot;0x10020000&quot;/&gt;&#10;    &lt;memoryBlockExpression address=&quot;268632064&quot; label=&quot;0x10030000&quot;/&gt;&#10;    &lt;memoryBlockExpression address=&quot;268534743&quot; label=&quot;0x100183d7&quot;/&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
+    <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_upgrade_2M.launch b/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_upgrade_2M.launch
new file mode 100644
index 0000000..cc4a413
--- /dev/null
+++ b/boot/cypress/BlinkyApp/BlinkyApp_CM4_Debug_upgrade_2M.launch
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="run"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set remotetimeout 15"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${cy_tools_path:openocd}/bin/openocd"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s &quot;${openocd_path}/../scripts&quot;&#13;&#10;-s &quot;${cy_prj_path}/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg&quot;&#13;&#10;-c &quot;source [find interface/kitprog3.cfg]&quot;&#13;&#10;-c &quot;puts stderr {Started by GNU MCU Eclipse}&quot;&#13;&#10;-c &quot;source [find target/psoc6_2m.cfg]&quot;&#13;&#10;-c &quot;psoc6.cpu.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1&quot;&#13;&#10;-c &quot;gdb_port 3332&quot;&#13;&#10;-c &quot;psoc6 sflash_restrictions 1&quot;&#13;&#10;-c &quot;init; reset init&quot;"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="run"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="/Users/rnok/repos/cy_mcuboot_project/cy_mcuboot/boot/cypress/BlinkyApp/out/boot/CY8CKIT-064S2-4343W/Debug/BlinkyApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="${cy_prj_path}/boot/cypress/BlinkyApp/out/PSOC_062_2M/Debug/upgrade/BlinkyApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_tools_path:CY_TOOL_arm-none-eabi-gdb_EXE}"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="${cy_prj_path}/boot/cypress/BlinkyApp/out/PSOC_062_2M/Debug/upgrade/BlinkyApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="cy_mcuboot"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.1249144476"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/cy_mcuboot"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;&gt;&#10;    &lt;memoryBlockExpression address=&quot;268566528&quot; label=&quot;0x10020000&quot;/&gt;&#10;    &lt;memoryBlockExpression address=&quot;268632064&quot; label=&quot;0x10030000&quot;/&gt;&#10;    &lt;memoryBlockExpression address=&quot;268534743&quot; label=&quot;0x100183d7&quot;/&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
+    <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/boot/cypress/BlinkyApp/Readme.md b/boot/cypress/BlinkyApp/Readme.md
new file mode 100644
index 0000000..ba5340e
--- /dev/null
+++ b/boot/cypress/BlinkyApp/Readme.md
@@ -0,0 +1,165 @@
+### Blinking LED test application for MCUboot bootloader
+
+### Description
+
+Implements simple Blinky LED CM4 application to demonstrate MCUboot Application operation in terms of BOOT and UPGRADE process.
+
+It is started by MCUboot Application which is running on CM0p.
+
+Functionality:
+
+* Blinks RED led with 2 different rates, depending on type of image - BOOT or UPGRADE.
+* Prints debug info and version of itself to terminal at 115200 baud.
+* Can be built for BOOT slot or UPGRADE slot of bootloader.
+
+Currently supported platforms
+
+* PSOC_062_2M
+* PSOC_062_1M
+* PSOC_062_512K
+
+### Hardware limitations
+
+Since this application is created to demonstrate MCUboot library features and not as reference examples some considerations are taken.
+
+1. Port/pin `P5_0` and `P5_1` used to configure serial port for debug prints. These pins are the most commonly used for serial port connection among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definitions of `CY_DEBUG_UART_TX` and `CY_DEBUG_UART_RX` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
+2. Port `GPIO_PRT13` pin `7U` used to define user connection LED. This pin is the most commonly used for USER_LED connection among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definitions of `LED_PORT` and `LED_PIN` in `main.c` of BlinkyApp to port/pin pairs corresponding to your design.
+
+### Pre-build action
+
+Pre-build action is implemented for defining start address and size of flash, as well as RAM start address and size for BlinkyApp.
+These values are set by specifing following macros: `-DUSER_APP_SIZE`, `-DUSER_APP_START`, `-DRAM_SIZE`, `-DRAM_START` in makefile.
+
+Pre-build action calls GCC preprocessor which intantiates defines for particular values in `BlinkyApp_template.ld`.
+
+Default values set for currently supported targets:
+* `BlinkyApp.mk` to `-DUSER_APP_START=0x10018000`
+
+**Important**: make sure RAM areas of CM4-based BlinkyApp and CM0p-based MCUBootApp bootloader do not overlap.
+Memory (stack) corruption of CM0p application can cause failure if SystemCall-served operations invoked from CM4.
+
+### Building an application
+
+Root directory for build is **boot/cypress.**
+
+The following command will build regular HEX file of a BlinkyApp for BOOT slot. Substitute `PLATFORM=` to a paltform name you use in all following commands.
+
+    make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
+
+This have following defaults suggested:
+
+    BUILDCFG=Debug
+    IMG_TYPE=BOOT
+
+To build UPGRADE image use following command:
+
+    make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x10000
+
+    Note: HEADER_OFFSET=%SLOT_SIZE%
+
+Example command-line for single-image:
+
+    make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
+
+**Building Multi-Image**
+
+`BlinkyApp` can be built to use in multi-image bootloader configuration.
+
+To get appropriate artifacts to use with multi image MCUBootApp, makefile flag `HEADER_OFFSET=` can be used.
+
+Example usage:
+
+Considering default config:
+
+* first image BOOT (PRIMARY) slot start `0x10018000`
+* slot size `0x10000`
+* second image BOOT (PRIMARY) slot start `0x10038000`
+
+To get appropriate artifact for second image PRIMARY slot run this command:
+
+    make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT HEADER_OFFSET=0x20000
+
+*Note:* only 2 images are supported at the moment.
+
+**How to build upgrade image for external memory:**
+
+To prepare MCUBootApp for work with external memory please refer to `MCUBootApp/ExternalMemory.md`.
+
+For build BlinkyApp upgrade image for external memory use command:
+
+    make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x7FE8000 ERASED_VALUE=0xff
+
+`HEADER_OFFSET` defines the offset from original boot image address. This one in line above suggests secondary slot will start from `0x18000000`.
+
+`ERASED_VALUE` defines the memory cell contents in erased state. It is `0x00` for PSoC6's internal Flash and `0xff` for S25FL512S.
+
+In case of using muti-image configuration, upgrade image for second application can be built using next command:
+
+    make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x8028000 ERASED_VALUE=0xff
+
+    Note: for S25FL512S block address shuld be mutiple by 0x40000
+
+**How to build encrypted upgrade image :**
+
+To prepare MCUBootApp for work with encrypted upgrade image please refer to `MCUBootApp/Readme.md`.
+
+To obtain encrypted upgrade image of BlinkyApp extra flag `ENC_IMG=1` should be passed in command line, for example:
+
+    make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x20000 ENC_IMG=1
+
+This also suggests user already placed corresponing `*.pem` key in `\keys` folder. The key variables are defined in root `Makefile` as `SIGN_KEY_FILE` and `ENC_KEY_FILE`
+
+### Post-build
+
+Post build action is executed at compile time for `BlinkyApp`. In case of build for `PSOC_062_2M` platform it calls `imgtool` from `MCUboot` scripts and adds signature to compiled image.
+
+Flags passed to `imgtool` for signature are defined in `SIGN_ARGS` variable in BlinkyApp.mk.
+
+### How to program an application
+
+Use any preferred tool for programming hex files.
+
+Hex file names to use for programming:
+
+`BlinkyApp` always produce build artifacts in 2 separate folders - `boot` and `upgrade`.
+
+`BlinkyApp` built to run with `MCUBootApp` produces files with name BlinkyApp.hex in `boot` directory and `BlinkyApp_upgrade.hex` in `upgrade` folder. These files are ready to be flashed to the board.
+
+`BlinkyApp_unsigned.hex` hex file is also preserved in both cases for possible troubleshooting.
+
+Files to use for programming are:
+
+`BOOT` - boot/BlinkyApp.hex
+`UPGRADE` - upgrade/BlinkyApp_upgrade.hex
+
+**Flags:**
+- `BUILDCFG` - configuration **Release** or **Debug**
+- `MAKEINFO` - 0 (default) - less build info, 1 - verbose output of compilation.
+- `HEADER_OFFSET` - 0 (default) - no offset of output hex file, 0x%VALUE% - offset for output hex file. Value 0x10000 is slot size MCUboot Bootloader in this example.
+- `IMG_TYPE` - `BOOT` (default) - build image for BOOT slot of MCUboot Bootloader, `UPGRADE` - build image for UPGRADE slot of MCUboot Bootloader.
+- `ENC_IMG` - 0 (default) - build regular upgrade image, `1` - build encrypted upgrade image (MCUBootApp should also be built with this flash set 1)
+
+**NOTE**: In case of `UPGRADE` image `HEADER_OFFSET` should be set to MCUboot Bootloader slot size.
+
+### Example terminal output
+
+When user application programmed in BOOT slot:
+
+    ===========================
+    [BlinkyApp] BlinkyApp v1.0 [CM4]
+    ===========================
+    [BlinkyApp] GPIO initialized
+    [BlinkyApp] UART initialized
+    [BlinkyApp] Retarget I/O set to 115200 baudrate
+    [BlinkyApp] Red led blinks with 1 sec period
+
+When user application programmed in UPRADE slot and upgrade procedure was successful:
+
+    ===========================
+    [BlinkyApp] BlinkyApp v2.0 [+]
+    ===========================
+
+    [BlinkyApp] GPIO initialized
+    [BlinkyApp] UART initialized
+    [BlinkyApp] Retarget I/O set to 115200 baudrate
+    [BlinkyApp] Red led blinks with 0.25 sec period
diff --git a/boot/cypress/BlinkyApp/libs.mk b/boot/cypress/BlinkyApp/libs.mk
index ff8637b..bd5caef 100644
--- a/boot/cypress/BlinkyApp/libs.mk
+++ b/boot/cypress/BlinkyApp/libs.mk
@@ -30,60 +30,19 @@
 #
 CUR_LIBS_PATH = $(PRJ_DIR)/libs
 
-# Collect source files for Retarget-io
-ifneq ($(PLATFORM), CYW20829)
-ifeq ($(APP_CORE), CM0P)
-SOURCES_RETARGET_IO := $(wildcard $(THIS_APP_PATH)/retarget_io_pdl/*.c)
-endif
-ifneq ($(APP_CORE), CM0P)
-SOURCES_RETARGET_IO := $(wildcard $(CUR_LIBS_PATH)/retarget-io/*.c)
-endif
-endif
 SOURCES_WATCHDOG := $(wildcard $(CUR_LIBS_PATH)/watchdog/*.c)
 
-# Collect source files for HAL
-ifneq ($(PLATFORM), CYW20829)
-ifneq ($(APP_CORE), CM0P)
-SOURCES_HAL_BLINKY := $(wildcard $(CUR_LIBS_PATH)/mtb-hal-cat1/source/*.c)
-SOURCES_HAL_BLINKY += $(wildcard $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/*.c)
-SOURCES_HAL_BLINKY += $(wildcard $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/*.c)
-endif
-endif
-
-# Retarget-io related include directories
-ifeq ($(APP_CORE), CM0P)
-INCLUDE_DIRS_RETARGET_IO := $(THIS_APP_PATH)/retarget_io_pdl
-endif
-ifneq ($(APP_CORE), CM0P)
-INCLUDE_DIRS_RETARGET_IO := $(CUR_LIBS_PATH)/retarget-io
-endif
 INCLUDE_DIRS_WATCHDOG := $(CUR_LIBS_PATH)/watchdog
 
-# Collect dirrectories containing headers for PSOC6 HAL
-ifneq ($(PLATFORM), CYW20829)
-ifneq ($(APP_CORE), CM0P)
-INCLUDE_DIRS_HAL_BLINKY := $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A
-INCLUDE_DIRS_HAL_BLINKY := $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include
-INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/include
-INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/include_pvt
-INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages
-INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/triggers
-endif
-endif
-
 # Collected source files for libraries
 SOURCES_LIBS += $(SOURCES_WATCHDOG)
-ifneq ($(PLATFORM), CYW20829)
-SOURCES_LIBS += $(SOURCES_RETARGET_IO)
-SOURCES_LIBS += $(SOURCES_HAL_BLINKY)
-endif
+SOURCES_LIBS += $(SOURCES_FIH)
+
 
 # Collected include directories for libraries
 INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_WATCHDOG))
-ifneq ($(PLATFORM), CYW20829)
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_RETARGET_IO))
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL_BLINKY))
-endif
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_FIH))
+
 
 ###############################################################################
 # Print debug information about all settings used and/or set in this file
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld
index 3a2a33c..dea9ce6 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld
@@ -133,7 +133,7 @@
 
         EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o
                 *cy_sysclk.o *cy_smif_hybrid_sect.o *flash_qspi.o
-                *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm0plus.o) *(.text)
+                *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm0plus.o, *libgcc.a) *(.text)
 
         KEEP(*(.init))
         KEEP(*(.fini))
@@ -252,6 +252,7 @@
         KEEP(*(.cy_ramfunc*))
         . = ALIGN(4);
 
+        *libgcc.a(.text*)
         *cy_smif.o(.text*)
         *cy_smif_memslot.o(.text*)
         *cy_smif_sfdp.o(.text*)
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
index 3e84aa3..c99131c 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
@@ -132,7 +132,7 @@
 
         EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o
                 *cy_sysclk.o *cy_smif_hybrid_sect.o *flash_qspi.o
-                *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm4.o) *(.text)
+                *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm4.o *libgcc.a) *(.text)
 
         KEEP(*(.init))
         KEEP(*(.fini))
@@ -251,6 +251,7 @@
         KEEP(*(.cy_ramfunc*))
         . = ALIGN(4);
 
+        *libgcc.a(.text*)
         *cy_smif.o(.text*)
         *cy_smif_memslot.o(.text*)
         *cy_smif_sfdp.o(.text*)
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld
new file mode 100644
index 0000000..3767ba8
--- /dev/null
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld
@@ -0,0 +1,435 @@
+/***************************************************************************//**
+* \file xmc7200d_x8384_cm7.ld
+* \version 1.0.0
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+GROUP(-lgcc -lc -lnosys )
+SEARCH_DIR(.)
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+ENTRY(Reset_Handler)
+
+/* The size of the MCU boot header area at the start of FLASH */
+BOOT_HEADER_SIZE = 0x400;
+
+/* The size of the stack section at the end of CM7 SRAM */
+STACK_SIZE = 0x1000;
+RAMVECTORS_ALIGNMENT                = 128;
+
+sram_start_reserve                  = 0;
+
+sram_total_size                     = 0x00100000; /* SRAM0 + SRAM1 */
+sram_private_for_srom               = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
+sram_used_by_boot                   = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
+
+cm0plus_sram_reserve                = 0x00020000; /* cm0 sram size */
+cm7_0_sram_reserve                  = 0x00060000; /* cm7_0 sram size */
+
+code_flash_total_size               = 0x00830000;
+cm0plus_code_flash_reserve          = 0x00080000;
+cm7_0_code_flash_reserve            = 0x00200000;
+
+code_flash_base_address             = 0x10000000;
+sram_base_address                   = 0x28000000;
+
+/* SRAM reservations */
+_base_SRAM_CM7_0                    = sram_base_address + cm0plus_sram_reserve;
+_size_SRAM_CM7_0                    = cm7_0_sram_reserve;
+/* In case of single CM7 device CM7_1 values should not be used */
+_base_SRAM_CM7_1                    = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
+_size_SRAM_CM7_1                    = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve;
+
+/* Code flash reservations */
+_base_CODE_FLASH_CM0P               = code_flash_base_address;
+_size_CODE_FLASH_CM0P               = cm0plus_code_flash_reserve;
+_base_CODE_FLASH_CM7_0              = code_flash_base_address + cm0plus_code_flash_reserve;
+_size_CODE_FLASH_CM7_0              = cm7_0_code_flash_reserve;
+_base_CODE_FLASH_CM7_1              = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
+_size_CODE_FLASH_CM7_1              = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
+
+/* Fixed Addresses */
+_base_WORK_FLASH                    = 0x14000000;
+_size_WORK_FLASH                    = 0x00040000;   /* 256K Work flash */
+_base_CM7_0_ITCM                    = 0xA0000000;
+_size_CM7_0_ITCM                    = 0x00004000;
+_base_CM7_0_DTCM                    = 0xA0010000;
+_size_CM7_0_DTCM                    = 0x00004000;
+_base_CM7_1_ITCM                    = 0xA0100000;
+_size_CM7_1_ITCM                    = 0x00004000;
+_base_CM7_1_DTCM                    = 0xA0110000;
+_size_CM7_1_DTCM                    = 0x00004000;
+
+/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */
+_base_SRAM                          = DEFINED(_CORE_CM7_1_) ? _base_SRAM_CM7_1 : DEFINED(_CORE_CM7_0_) ? _base_SRAM_CM7_0 : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_SRAM                          = DEFINED(_CORE_CM7_1_) ? _size_SRAM_CM7_1 : DEFINED(_CORE_CM7_0_) ? _size_SRAM_CM7_0 : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_base_CODE_FLASH                    = DEFINED(_CORE_CM7_1_) ? _base_CODE_FLASH_CM7_1 : DEFINED(_CORE_CM7_0_) ? _base_CODE_FLASH_CM7_0  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_CODE_FLASH                    = DEFINED(_CORE_CM7_1_) ? _size_CODE_FLASH_CM7_1 : DEFINED(_CORE_CM7_0_) ? _size_CODE_FLASH_CM7_0  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_base_SFLASH_USER_DATA              = 0x17000800;
+_size_SFLASH_USER_DATA              = 0x00000800;
+_base_SFLASH_NAR                    = 0x17001A00;
+_size_SFLASH_NAR                    = 0x00000200;
+_base_SFLASH_PUB_KEY                = 0x17006400;
+_size_SFLASH_PUB_KEY                = 0x00000C00;
+_base_SFLASH_APP_PROT               = 0x17007600;
+_size_SFLASH_APP_PROT               = 0x00000200;
+_base_SFLASH_TOC2                   = 0x17007C00;
+_size_SFLASH_TOC2                   = 0x00000200;
+_base_XIP                           = 0x60000000;
+_size_XIP                           = 0x08000000;
+_base_EFUSE                         = 0x90700000;
+_size_EFUSE                         = 0x00100000;
+_base_ITCM                          = DEFINED(_CORE_CM7_1_) ? _base_CM7_1_ITCM : DEFINED(_CORE_CM7_0_) ? _base_CM7_0_ITCM  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_ITCM                          = DEFINED(_CORE_CM7_1_) ? _size_CM7_1_ITCM : DEFINED(_CORE_CM7_0_) ? _size_CM7_0_ITCM  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_base_DTCM                          = DEFINED(_CORE_CM7_1_) ? _base_CM7_1_DTCM : DEFINED(_CORE_CM7_0_) ? _base_CM7_0_DTCM  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_DTCM                          = DEFINED(_CORE_CM7_1_) ? _size_CM7_1_DTCM : DEFINED(_CORE_CM7_0_) ? _size_CM7_0_DTCM  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+    /* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
+    ram                 (rxw)       : ORIGIN = USER_APP_RAM_START,                  LENGTH = USER_APP_RAM_SIZE         /* SRAM */
+    flash_cm0p          (rx)        : ORIGIN = _base_CODE_FLASH_CM0P,               LENGTH = _size_CODE_FLASH_CM0P      /* CODE flash CM0+ */
+    flash               (rx)        : ORIGIN = USER_APP_START,                      LENGTH = USER_APP_SIZE              /* CODE flash CM7_0/1 */
+
+    /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+     * You can assign sections to this memory region for only one of the cores.
+     */
+    em_eeprom           (rw)        : ORIGIN = _base_WORK_FLASH,            LENGTH = _size_WORK_FLASH           /* WORK flash */
+
+    /* The following regions define device specific memory regions and must not be changed. */
+    sflash_user_data    (rx)        : ORIGIN = _base_SFLASH_USER_DATA,      LENGTH = _size_SFLASH_USER_DATA     /* Supervisory flash: User data */
+    sflash_nar          (rx)        : ORIGIN = _base_SFLASH_NAR,            LENGTH = _size_SFLASH_NAR            /* Supervisory flash: Normal Access Restrictions (NAR) */
+    sflash_public_key   (rx)        : ORIGIN = _base_SFLASH_PUB_KEY,        LENGTH = _size_SFLASH_PUB_KEY       /* Supervisory flash: Public Key */
+    sflash_app_prot     (rx)        : ORIGIN = _base_SFLASH_APP_PROT,       LENGTH = _size_SFLASH_APP_PROT
+    sflash_toc_2        (rx)        : ORIGIN = _base_SFLASH_TOC2,           LENGTH = _size_SFLASH_TOC2          /* Supervisory flash: Table of Content # 2 */
+    xip                 (rx)        : ORIGIN = _base_XIP,                   LENGTH = _size_XIP                  /* XIP: 128 MB */
+    efuse               (rx)        : ORIGIN = _base_EFUSE,                 LENGTH = _size_EFUSE                /* 1MB */
+    itcm                (rx)        : ORIGIN = _base_ITCM,                  LENGTH = _size_ITCM                 /* ITCM */
+    dtcm                (rx)        : ORIGIN = _base_DTCM,                  LENGTH = _base_DTCM                 /* DTCM */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+SECTIONS
+{
+    /* Cortex-M0+ application flash image area. Comment this section if you don't want to include CM0+ image */
+    /* .cy_cm0p_image  ORIGIN(flash_cm0p):
+    {
+        . = ALIGN(4);
+        __cy_m0p_code_start = . ;
+        KEEP(*(.cy_m0p_image))
+        __cy_m0p_code_end = . ;
+    } > flash_cm0p */
+
+    /* Check if .cy_m0p_image size exceeds cm0plus_code_flash_reserve */
+    /* ASSERT(__cy_m0p_code_end < ORIGIN(flash), "CM0+ flash image overflows with CM7, increase CM7 base address ") */
+
+    /* Cortex-M7 application flash area */
+    .text ORIGIN(flash) + BOOT_HEADER_SIZE :
+    {
+        /* Cortex-M7 flash vector table */
+        . = ALIGN(4);
+        __Vectors = . ;
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        . = ALIGN(4);
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* Read-only code (constants). */
+        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+        KEEP(*(.eh_frame*))
+    } > flash
+
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > flash
+
+    __exidx_start = .;
+
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > flash
+    __exidx_end = .;
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+
+        /* Copy data section to RAM */
+        LONG (__etext)                                      /* From */
+        LONG (__data_start__)                               /* To   */
+        LONG ((__data_end__ - __data_start__)/4)            /* Size */
+
+        __copy_table_end__ = .;
+    } > flash
+
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG ((__bss_end__ - __bss_start__)/4)
+        __zero_table_end__ = .;
+    } > flash
+
+    __etext =  . ;
+
+
+    .ramVectors (NOLOAD) :
+    {
+        . = ALIGN(RAMVECTORS_ALIGNMENT);
+        __ram_vectors_start__ = .;
+        KEEP(*(.ram_vectors))
+        __ram_vectors_end__   = .;
+    } > ram
+
+
+    .data __ram_vectors_end__ :
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+
+        KEEP(*(.cy_ramfunc*))
+        . = ALIGN(32);
+
+        KEEP(*(cy_sharedmem*))
+        . = ALIGN(4);
+
+        __data_end__ = .;
+
+    } > ram AT>flash
+
+
+    /* Place variables in the section that should not be initialized during the
+    *  device startup.
+    */
+    .noinit (NOLOAD) : ALIGN(8)
+    {
+      KEEP(*(.noinit))
+    } > ram
+
+
+    /* The uninitialized global or static variables are placed in this section.
+    *
+    * The NOLOAD attribute tells linker that .bss section does not consume
+    * any space in the image. The NOLOAD attribute changes the .bss type to
+    * NOBITS, and that  makes linker to A) not allocate section in memory, and
+    * A) put information to clear the section with all zeros during application
+    * loading.
+    *
+    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+    * This  makes linker to A) allocate zeroed section in memory, and B) copy
+    * this section to RAM during application loading.
+    */
+    .bss (NOLOAD):
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram
+
+
+    .heap (NOLOAD):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+        __HeapLimit = .;
+    } > ram
+
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        KEEP(*(.stack*))
+    } > ram
+
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(ram) + LENGTH(ram);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+    /* Emulated EEPROM Flash area */
+    .cy_em_eeprom :
+    {
+        KEEP(*(.cy_em_eeprom))
+    } > em_eeprom
+
+
+    /* Supervisory Flash: User data */
+    .cy_sflash_user_data :
+    {
+        KEEP(*(.cy_sflash_user_data))
+    } > sflash_user_data
+
+
+    /* Supervisory Flash: Normal Access Restrictions (NAR) */
+    .cy_sflash_nar :
+    {
+        KEEP(*(.cy_sflash_nar))
+    } > sflash_nar
+
+
+    /* Supervisory Flash: Public Key */
+    .cy_sflash_public_key :
+    {
+        KEEP(*(.cy_sflash_public_key))
+    } > sflash_public_key
+
+
+    /* Supervisory Flash: Table of Content # 2 */
+    .cy_toc_part2 :
+    {
+        KEEP(*(.cy_toc_part2))
+    } > sflash_toc_2
+
+    /* Places the code in the Execute in Place (XIP) section. See the smif driver
+    *  documentation for details.
+    */
+    cy_xip :
+    {
+        __cy_xip_start = .;
+        KEEP(*(.cy_xip))
+        __cy_xip_end = .;
+    } > xip
+
+
+    /* eFuse */
+    .cy_efuse :
+    {
+        KEEP(*(.cy_efuse))
+    } > efuse
+
+    /* itcm */
+    .cy_itcm :
+    {
+        KEEP(*(.cy_itcm))
+    } > itcm
+
+    /* dtcm */
+    .cy_dtcm :
+    {
+        KEEP(*(.cy_dtcm))
+    } > dtcm
+}
+
+
+/*============================================================
+ * Symbols for use by application
+ *============================================================
+ */
+
+__ecc_init_sram_start_address = ORIGIN(ram);
+__ecc_init_sram_end_address   = ORIGIN(ram) + LENGTH(ram);
+
+/* EOF */
diff --git a/boot/cypress/BlinkyApp/main.c b/boot/cypress/BlinkyApp/main.c
index 900c870..5bc5a59 100644
--- a/boot/cypress/BlinkyApp/main.c
+++ b/boot/cypress/BlinkyApp/main.c
@@ -57,6 +57,11 @@
 
     printf("[BlinkyApp] Image type: " IMAGE_TYPE " on %s core\r\n", detect_core_message);
 
+    /* Disable watchdog timer to mark successful start up of application. */
+    cyhal_wdt_free(NULL);
+
+    printf(WATCHDOG_FREE_MESSAGE);
+
     for (;;) {
         /* Toggle the user LED periodically */
         Cy_SysLib_Delay(BLINK_PERIOD / 2);
diff --git a/boot/cypress/BlinkyApp/platform.h b/boot/cypress/BlinkyApp/platform.h
index a34650a..f7e8122 100644
--- a/boot/cypress/BlinkyApp/platform.h
+++ b/boot/cypress/BlinkyApp/platform.h
@@ -1,55 +1,42 @@
 #ifndef PLATFORM_H
 #define PLATFORM_H
 
-#ifdef CYW20829
 #include <inttypes.h>
-
-#include "cybsp.h"
-#include "cycfg_pins.h"
-#include "cyhal_wdt.h"
-#else
-#include "system_psoc6.h"
-#endif /* CYW20829 */
-
 #include <stdio.h>
 
 #include "cy_pdl.h"
-#ifdef APP_CM0P
-#include "cycfg_peripherals.h"
-#include "cycfg_pins.h"
-#include "cy_retarget_io_pdl.h"
-#else
-#include "cyhal.h"
 #include "cy_retarget_io.h"
-
-#endif /* APP_CM0P */
-#include "watchdog.h"
+#include "cybsp.h"
+#include "cycfg.h"
+#include "cyhal.h"
+#include "cyhal_wdt.h"
 
 #if defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829)
 #include "flash_qspi.h"
 #endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829) */
 
 #ifdef BOOT_IMAGE
-#define IMAGE_TYPE             "BOOT"
-#define BLINK_PERIOD           (1000u)
-#define GREETING_MESSAGE_INFO  "[BlinkyApp] Red led blinks with 1 sec period\r\n"
+#define IMAGE_TYPE "BOOT"
+#define BLINK_PERIOD (1000u)
+#define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 1 sec period\r\n"
 #elif defined(UPGRADE_IMAGE)
-#define IMAGE_TYPE             "UPGRADE"
-#define BLINK_PERIOD           (250u)
-#define GREETING_MESSAGE_INFO  "[BlinkyApp] Red led blinks with 0.25 sec period\r\n"
+#define IMAGE_TYPE "UPGRADE"
+#define BLINK_PERIOD (250u)
+#define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 0.25 sec period\r\n"
 #else
-#error                         "[BlinkyApp] Please specify type of image: -DBOOT_IMAGE or -DUPGRADE_IMAGE\r\n"
+#error "[BlinkyApp] Please specify type of image: -DBOOT_IMAGE or -DUPGRADE_IMAGE\r\n"
 #endif /* BOOT_IMAGE */
 
-#define GREETING_MESSAGE_VER   "[BlinkyApp] Version:"
+#define GREETING_MESSAGE_VER "[BlinkyApp] Version:"
 
-#define WATCHDOG_FREE_MESSAGE  "[BlinkyApp] Turn off watchdog timer\r\n"
+#define WATCHDOG_FREE_MESSAGE "[BlinkyApp] Turn off watchdog timer\r\n"
 
 #define SMIF_ID (1U) /* Assume SlaveSelect_0 is used for External Memory */
 
-static const char* core33_message ="CM33";
-static const char* core0p_message ="CM0P";
-static const char* core4_message  ="CM4";
+static const char* core33_message = "CM33";
+static const char* core0p_message = "CM0P";
+static const char* core4_message = "CM4";
+static const char* core7_message = "CM7";
 
 #if defined(__cplusplus)
 extern "C" {
@@ -58,9 +45,10 @@
 static inline const char* test_app_init_hardware(void)
 {
     const char* detect_core_message = NULL;
-    (void) core33_message;
-    (void) core0p_message;
-    (void) core4_message;
+    (void)core33_message;
+    (void)core0p_message;
+    (void)core4_message;
+    (void)core7_message;
     cy_rslt_t res = CY_RSLT_TYPE_ERROR;
 
     const cy_stc_gpio_pin_config_t LED_config = {
@@ -79,25 +67,14 @@
         .vohSel = 0UL,
     };
 
-#ifdef CYW20829
     cybsp_init();
-#elif defined APP_CM0P
-    init_cycfg_peripherals();
-    init_cycfg_pins();
-#endif /* CYW20829 */
-
     /* enable interrupts */
     __enable_irq();
 
     /* Initialize led port */
     Cy_GPIO_Pin_Init(LED_PORT, LED_PIN, &LED_config);
 
-    /* Initialize retarget-io to use the debug UART port */
-#ifdef APP_CM0P
-    res = cy_retarget_io_pdl_init(CY_RETARGET_IO_BAUDRATE);
-#else
     res = cy_retarget_io_init(CY_DEBUG_UART_TX, CY_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);
-#endif /* APP_CM0P */
 
     if (res != CY_RSLT_SUCCESS) {
         CY_ASSERT(0);
@@ -115,7 +92,6 @@
     printf("===========================\r\n");
 
     cy_en_smif_status_t rc = CY_SMIF_CMD_NOT_FOUND;
-    cyhal_wdt_t *cyw20829_wdt = NULL;
 
     rc = qspi_init_sfdp(SMIF_ID);
     if (CY_SMIF_SUCCESS == rc) {
@@ -124,39 +100,39 @@
         printf("[BlinkyApp] External Memory initialization w/ SFDP FAILED: 0x%" PRIx32 " \r\n", (uint32_t)rc);
     }
 
-    /* Disable watchdog timer to mark successful start up of application. */
-    cyhal_wdt_free(cyw20829_wdt);
-
 #else
     /* Determine on which core this app is running by polling CPUSS_IDENTITY register.
      * This register contains bits field [8:11]. This field specifies the bus master
      * identifier of the transfer that reads the register.
      */
-#ifdef APP_CM0P
 
+#ifdef APP_CM0P
     en_prot_master_t core = _FLD2VAL(CPUSS_IDENTITY_MS, CPUSS->IDENTITY);
 
     if (CPUSS_MS_ID_CM4 == core) {
         printf("\n[BlinkyApp] is compiled for CM0P core, started on CM4 instead. Execution Halted.\n");
         CY_ASSERT(0);
-    }
-    else if (CPUSS_MS_ID_CM0 == core) {
+    } else if (CPUSS_MS_ID_CM0 == core) {
         detect_core_message = core0p_message;
-    }
-    else
+    } else
 #endif /* APP_CM0P */
     {
         detect_core_message = core4_message;
     }
+#ifdef APP_CM7
+    if (CPUSS_MS_ID_CM7_0 == _FLD2VAL(CPUSS_IDENTITY_MS, CPUSS->IDENTITY)) {
+        detect_core_message = core7_message;
+    }
+#endif
+
     printf("===========================\r\n");
-    cy_wdg_free();
 #endif /* CYW20829 */
     printf("[BlinkyApp] GPIO initialized \r\n");
     printf("[BlinkyApp] UART initialized \r\n");
     printf("[BlinkyApp] Retarget I/O set to 115200 baudrate \r\n");
-    printf(WATCHDOG_FREE_MESSAGE);
+    cyhal_wdt_kick(NULL);
 
-    return(detect_core_message);
+    return (detect_core_message);
 }
 
 #if defined(__cplusplus)
diff --git a/boot/cypress/MCUBootApp/ExternalMemory.md b/boot/cypress/MCUBootApp/ExternalMemory.md
index bfc8162..9a339b3 100644
--- a/boot/cypress/MCUBootApp/ExternalMemory.md
+++ b/boot/cypress/MCUBootApp/ExternalMemory.md
@@ -70,23 +70,23 @@
 
 On CYW20829 platform XIP mode is always used due to absence of internal memory.
 
-This is optional for PSoC™ 6 devices. The JSON flash map should contain `"mode": "XIP"` in the `"external_flash" section`. `USE_XIP` flag is added to auto-generated `flashmap.mk` on pre-build action.
+This is optional for PSoC™ 6 devices. The JSON flash map should contain `"mode": "XIP"` in the `"external_flash" section`. `USE_XIP` flag is added to auto-generated `memorymap.mk` on pre-build action.
 
 When XIP mode is used primary slot of an image can be placed in external memory.
 
-This repository provides default flash map files with suffix _xip_ to be used for XIP mode in `platforms/cy_flash_pal/flash_%platform_name%/flashmap`.
+This repository provides default flash map files with suffix _xip_ to be used for XIP mode in `platforms/memory/flash_%platform_name%/flashmap`.
 
 #### How to enable external memory support
 
-External memory is enabled when `make` flag `USE_EXTERNAL_FLASH` is set to `1`. Value of this flag is set in auto-generated `flashmap.mk` files when field `"external_flash"` is present in JSON file. 
+External memory is enabled when `make` flag `USE_EXTERNAL_FLASH` is set to `1`. Value of this flag is set in auto-generated `memorymap.mk` files when field `"external_flash"` is present in JSON file. 
 
-Default flash maps with suffix _smif_ are provided in `platforms/cy_flash_pal/flash_psoc6/flashmap` folder for PSoC™ 6 devices, where presense of external memory in system is optional.
+Default flash maps with suffix _smif_ are provided in `platforms/memory/PSOC6/flashmap` folder for PSoC™ 6 devices, where presense of external memory in system is optional.
 
 Build MCUBootApp as described in the [MCUBootApp.md](MCUBootApp.md) file.
 
 **Building an upgrade image for external memory:**
 
-    make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE ERASED_VALUE=0xff FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json IMG_ID=1
+    make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE ERASED_VALUE=0xff FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single_smif.json IMG_ID=1
 
 `ERASED_VALUE` - Defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S.
 
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.md b/boot/cypress/MCUBootApp/MCUBootApp.md
index c07cb9e..3422afb 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.md
+++ b/boot/cypress/MCUBootApp/MCUBootApp.md
@@ -20,6 +20,7 @@
 * `CYBLE-416045-EVAL`
 * `CY8CPROTO-063-BLE`
 * `CY8CKIT-062-BLE`
+* `KIT_XMC72_EVK`
 
 ### Platfrom specifics
 
@@ -31,7 +32,7 @@
 
 The flash map of the bootloader is defined at compile-time and cannot be changed dynamically. Flash map is prepared in the industry-accepted JSON (JavaScript Object Notation) format. It should follow the rules described in section **How to modify the flash map**.
 
-`MCUBootApp` contains JSON templates for flash maps with commonly used configurations. They can be found in `platforms/cy_flash_pal/flash_%platform_name%/flashmap` The slots' sizes are defined per platform to be compatible with all supported device families.
+`MCUBootApp` contains JSON templates for flash maps with commonly used configurations. They can be found in `platforms/memory/flash_%platform_name%/flashmap` The slots' sizes are defined per platform to be compatible with all supported device families.
 
 The actual addresses are provided in corresponding platform doc files:
 
@@ -101,12 +102,6 @@
 
 There also should be a mandatory `"bootloader"` section, describing the location and size of `MCUBootApp` in the `"address"` and `"size"` parameters, respectively.
 
-Under some circumstances (e.g., PSoC™ 62 with application slots in both internal and external flash memories), the slot address must be properly aligned, as the image trailer should start exactly at the erase block boundary. When an improper address is specified, `make` will fail with a message like:
-```
-Misaligned application_1 (secondary slot) - suggested address 0x18030200
-```
-This gives the nearest larger address that satisfies the slot location requirements. Other errors, such as overlapping flash areas, are also checked and reported.
-
 ###### Scratch area
 The scratch area location and size are given in the `"scratch_address"` and `"scratch_size"` parameters of the `"bootloader"` subsection.
 For example:
@@ -264,8 +259,6 @@
 ```
 The purpose of such a layout is to allow MCUBoot to understand what image is placed in the shared secondary slot. While secondary images now can (and should) overlap, their trailers must under no circumstances share the same address!
 
-Normally image trailer occupies the whole erase block (e.g. 512 bytes for PSoC™ 62 internal Flash, or 256 kilobytes for SEMPER™ Secure NOR Flash). There is a specific case when images are placed in both memory types, refer to the [PSOC6.md](../platforms/PSOC6.md) file.
-
 One can declare all secondary slots as shared using the following JSON syntax:
 
 ```
@@ -395,11 +388,11 @@
 ```
 
 ###### Flash map internals
-When the `FLASH_MAP=` option is supplied to `make`, it involves the Python script `boot/cypress/scripts/flashmap.py`. It takes the JSON file and converts flash map into the C header file `boot/cypress/platforms/cy_flash_pal/cy_flash_map.h`.
+When the `FLASH_MAP=` option is supplied to `make`, it involves the Python script `boot/cypress/scripts/memorymap.py`. It takes the JSON file and converts flash map into the C header file `boot/cypress/platforms/memory/memory.h`.
 
-At the same time it creates the `boot/cypress/MCUBootApp/flashmap.mk`, which is conditionally included from the `boot/cypress/MCUBootApp/MCUBootApp.mk`. The generated file contains various definitions derived from the flash map, such as `MCUBOOT_IMAGE_NUMBER`, `MAX_IMG_SECTORS`, `USE_EXTERNAL_FLASH`, and `USE_XIP`. So, there is no need to specify these and similar parameters manually.
+At the same time it creates the `boot/cypress/MCUBootApp/memorymap.mk`, which is conditionally included from the `boot/cypress/MCUBootApp/MCUBootApp.mk`. The generated file contains various definitions derived from the flash map, such as `MCUBOOT_IMAGE_NUMBER`, `MAX_IMG_SECTORS`, `USE_EXTERNAL_FLASH`, and `USE_XIP`. So, there is no need to specify these and similar parameters manually.
 
-Do not edit either `sysflash/cy_flash_map.h` or `flashmap.mk`, as both files are overwritten on every build.
+Do not edit either `sysflash/memory.h` or `memorymap.mk`, as both files are overwritten on every build.
 
 #### External flash
 
@@ -436,7 +429,7 @@
 
 Multi-image operation considers upgrading and verification of more than one image on a device.
 
-Single or multi-image mode is dictated by the `MCUBOOT_IMAGE_NUMBER` `make` flag. This flag's value is set in an auto-generated `flashmap.mk` file per flash map used. There is no need to pass it manually.
+Single or multi-image mode is dictated by the `MCUBOOT_IMAGE_NUMBER` `make` flag. This flag's value is set in an auto-generated `memorymap.mk` file per flash map used. There is no need to pass it manually.
 
 In Multi-image operation, up to four images are supported. 
 
@@ -464,7 +457,7 @@
 
 `#define MCUBOOT_OVERWRITE_ONLY 1`
 
-This flag's value is set in an auto-generated `flashmap.mk` file per flash map used. There is no need to pass it manually.
+This flag's value is set in an auto-generated `memorymap.mk` file per flash map used. There is no need to pass it manually.
 
 In Overwrite-only mode, MCUBootApp first checks if any upgrade image is present in the secondary slot(s), then validates the digital signature of the upgrade image in the secondary slot(s). If validation is successful, MCUBootApp starts copying the secondary slot content to the primary slot. After the copy is done, MCUBootApp starts the upgrade image execution from the primary slot.
 
@@ -579,6 +572,16 @@
 
 If there is a need to wipe out the product and flash new firmware directly to the primary (BOOT) slot, the device is transferred to the `Empty` or `Ready` state and then walks through all the states again.
 
+### Software limitation
+For both internal and external flash memories, the slot address must be properly aligned, as the image trailer should occupy a separate sector.
+
+Normally image trailer occupies the whole erase block (e.g. 512 bytes for PSoC™ 62 internal Flash, or 256 kilobytes for SEMPER™ Secure NOR Flash). There is a specific case when images are placed in both memory types, refer to the [PSOC6.md](../platforms/PSOC6.md) file.
+
+When an improper address is specified, `make` will fail with a message like:
+```
+Misaligned application_1 (secondary slot) - suggested address 0x18030200
+```
+This gives the nearest larger address that satisfies the slot location requirements. Other errors, such as overlapping flash areas, are also checked and reported.
 ### Hardware limitations
 
 This application is created to demonstrate the MCUboot library features and not as a reference example. So, some considerations are taken.
@@ -616,12 +619,12 @@
 
 1. Choose Upgrade mode and number of images.
 
-`platforms/cy_flash_pal/flash_%platform_name%/flashmap` folder contains a set of predefined flash map JSON files with suffixes _overwrite_ or _swap_ for upgrade methods and _single_ or _multi_ for images number in its names. Depending on the file chosen upgrade method and images number are configured:
+`platforms/memory/flash_%platform_name%/flashmap` folder contains a set of predefined flash map JSON files with suffixes _overwrite_ or _swap_ for upgrade methods and _single_ or _multi_ for images number in its names. Depending on the file chosen upgrade method and images number are configured:
 
 `USE_OVERWRITE` `make` flag is set to 1 or 0 for `overwrite` or `swap` mode;
 `MCUBOOT_IMAGE_NUMBER` flag is set to a number of corresponding `application_#` sections in the flash map file.
 
-These flag values are set in an auto-generated `flashmap.mk` file per flash map used. There is no need to pass them manually.
+These flag values are set in an auto-generated `memorymap.mk` file per flash map used. There is no need to pass them manually.
 
 __NOTE__: Do not use flash map JSON files with suffixes xip or smif for `PSoC™ 063` kits.
 
@@ -629,9 +632,9 @@
 
 Pass `USE_CRYPTO_HW=1` to the `make` command. This option is temporarily disabled by default - see paragraph **Hardware cryptography acceleration**.
 
-Additionally, users can configure hardware rollback protection on the supported platforms. To do this flash map file from `platforms/cy_flash_pal/flash_%platform_name%/flashmap/hw_rollback_prot` folder should be used.
+Additionally, users can configure hardware rollback protection on the supported platforms. To do this flash map file from `platforms/memory/flash_%platform_name%/flashmap/hw_rollback_prot` folder should be used.
 
-`USE_HW_ROLLBACK_PROT` `make` flag is set to 1 in auto-generated `flashmap.mk`. 
+`USE_HW_ROLLBACK_PROT` `make` flag is set to 1 in auto-generated `memorymap.mk`. 
 
 The rollback protection feature is currently supported on CYW20829 devices in Secure mode only.
 
@@ -641,49 +644,58 @@
 
 Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE 3.0**:
 
-    make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/$(USERNAME)/ModusToolbox/tools_3.0/gcc
+    make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.0/gcc
 
 * Build MCUBootApp in the `Debug` configuration for Single-image mode with swap upgrade.
 
     `PSoC™ 062`
 
-        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json
+        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json
 
     `PSoC™ 063`
 
-        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_063_1M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json
+        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_063_1M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json
+
+    `XMC7200`
+
+        make clean app APP_NAME=MCUBootApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_swap_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM0P APP_CORE=CM7 APP_CORE_ID=0
+
+    `XMC7100`
+
+        make clean app APP_NAME=MCUBootApp PLATFORM=XMC7100 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_swap_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7100_platform.json CORE=CM0P APP_CORE=CM7 APP_CORE_ID=0
 
 * Build MCUBootApp in `Release` configuration for Multi-image mode with overwriting update.
 
     `PSoC™ 062`
 
-        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi.json
+        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_multi.json
 
     `PSoC™ 063`
 
-        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_063_1M BUILDCFG=Release FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi.json
+        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_063_1M BUILDCFG=Release FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_multi.json
+
 
 * Build MCUBootApp in `Debug` configuration for Single-image mode with swap upgrade and in `smif` mode.
 
     `PSoC™ 062`
 
-        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json
+        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single_smif.json
 
     `PSoC™ 063`
 
         Supported only for `PLATFORM=PSOC_063_1M DEVICE=CY8C6347BZI-BLD53`
-        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_1M DEVICE=CY8C6347BZI-BLD53 BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json
+        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_1M DEVICE=CY8C6347BZI-BLD53 BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single_smif.json
         `NOTE:` PSOC_062_1M platform is used here since kit, where particular MPN is installed is called CY8CKIT-062-BLE
 
 * Build MCUBootApp in `Debug` configuration for Single-image mode with swap upgrade and in `xip` mode.
 
     `PSoC™ 062`
 
-        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_swap.json
+        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_xip_swap.json
 
     `PSoC™ 063`
 
-        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_1M DEVICE=CY8C6347BZI-BLD53 BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_swap.json
+        make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_1M DEVICE=CY8C6347BZI-BLD53 BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_xip_swap.json
     `NOTE:` PSOC_062_1M platform is used here since kit, where particular MPN is installed is called CY8CKIT-062-BLE
 
 The root directory for the build is `boot/cypress`.
@@ -716,13 +728,13 @@
 `DEVICE` - is used to set a particular MPN for a platform since multiple MPNs are associated with one platform, for example:   
 `PLATFORM=PSOC_062_1M DEVICE=CY8C6347BZI-BLD53`   
 
-The next flags will be set by script in auto-generated makefile 'flashmap.mk':   
+The next flags will be set by script in auto-generated makefile 'memorymap.mk':   
 `MCUBOOT_IMAGE_NUMBER` - The number of images to be supported by the current build of MCUBootApp.    
 `USE_OVERWRITE` - `0` - Use swap with Scratch upgrade mode, `1` - use Overwrite only upgrade.   
 `USE_EXTERNAL_FLASH` - When set to `1`, it enables the external memory support on the PSoC™ 6 platform. This value is always set to `1` on CYW20829.   
 `USE_HW_ROLLBACK_PROT` - When set to `1`, it enables the hardware rollback protection on the CYW20829 platform with Secure mode enabled.   
 
-Adding `clean` to `make` will clean the build folder, and files boot/cypress/MCUBootApp/flashmap.mk and boot/cypress/platforms/cy_flash_pal/cy_flash_map.h  will be removed and re-generated.   
+Adding `clean` to `make` will clean the build folder, and files boot/cypress/MCUBootApp/memorymap.mk and boot/cypress/platforms/memory/memorymap.h will be removed and re-generated.   
 
 ### Programming solution
 
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.mk b/boot/cypress/MCUBootApp/MCUBootApp.mk
index a90e488..dfac125 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.mk
+++ b/boot/cypress/MCUBootApp/MCUBootApp.mk
@@ -33,29 +33,31 @@
 
 CUR_APP_PATH = $(PRJ_DIR)/$(APP_NAME)
 
-ifneq ($(FLASH_MAP), )
-#to 'Bit_per_cnt' generation for CYW20829
-ifeq ($(PLATFORM), CYW20829)
-$(CUR_APP_PATH)/flashmap.mk:
-	$(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/cy_flash_pal/cy_flash_map.h -c $(PRJ_DIR)/policy/policy_secure.json > $(CUR_APP_PATH)/flashmap.mk
-else
-$(CUR_APP_PATH)/flashmap.mk:
-	$(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/cy_flash_pal/cy_flash_map.h > $(CUR_APP_PATH)/flashmap.mk
-endif
-include $(CUR_APP_PATH)/flashmap.mk
-DEFINES_APP := -DCY_FLASH_MAP_JSON
-endif
+-include $(CUR_APP_PATH)/memorymap.mk
 
 MCUBOOT_IMAGE_NUMBER ?= 1
 ENC_IMG ?= 0
+USE_HW_KEY ?= 0
 USE_BOOTSTRAP ?= 1
 MCUBOOT_LOG_LEVEL ?= MCUBOOT_LOG_LEVEL_DEBUG
 USE_SHARED_SLOT ?= 0
+FIH_PROFILE_LEVEL_LIST := OFF LOW MEDIUM HIGH
+FIH_PROFILE_LEVEL ?= MEDIUM
 
 ifneq ($(COMPILER), GCC_ARM)
 $(error Only GCC ARM is supported at this moment)
 endif
 
+# Check FIH profile param
+ifneq ($(filter $(FIH_PROFILE_LEVEL), $(FIH_PROFILE_LEVEL_LIST)),)
+ifneq ($(FIH_PROFILE_LEVEL), OFF) 
+DEFINES_APP += -DMCUBOOT_FIH_PROFILE_ON
+DEFINES_APP += -DMCUBOOT_FIH_PROFILE_$(FIH_PROFILE_LEVEL)
+endif
+else
+$(error Wrong FIH_PROFILE_LEVEL param)
+endif
+
 # Output folder
 OUT := $(APP_NAME)/out
 # Output folder to contain build artifacts
@@ -64,6 +66,21 @@
 OUT_CFG := $(OUT_TARGET)/$(BUILDCFG)
 
 include $(PRJ_DIR)/platforms.mk
+
+ifneq ($(FLASH_MAP), )
+ifeq ($(FAMILY), CYW20829)
+$(CUR_APP_PATH)/memorymap.mk:
+	$(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -c $(PRJ_DIR)/policy/policy_secure.json > $(CUR_APP_PATH)/memorymap.mk
+else ifeq ($(FAMILY), XMC7000)
+$(CUR_APP_PATH)/memorymap.mk:
+	$(PYTHON_PATH) scripts/memorymap_rework.py run -p $(PLATFORM_CONFIG) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory -n memorymap > $(CUR_APP_PATH)/memorymap.mk
+else
+$(CUR_APP_PATH)/memorymap.mk:
+	$(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h > $(CUR_APP_PATH)/memorymap.mk
+endif
+DEFINES_APP += -DCY_FLASH_MAP_JSON
+endif
+
 include $(PRJ_DIR)/common_libs.mk
 include $(PRJ_DIR)/toolchains.mk
 
@@ -74,10 +91,14 @@
 # Application-specific DEFINES
 DEFINES_APP += -DMBEDTLS_CONFIG_FILE="\"mcuboot_crypto_config.h\""
 DEFINES_APP += -DECC256_KEY_FILE="\"keys/$(SIGN_KEY_FILE).pub\""
-DEFINES_APP += -D$(CORE)
+DEFINES_APP += -DBOOT_$(CORE)
 DEFINES_APP += -DAPP_$(APP_CORE)
+DEFINES_APP += -DAPP_CORE_ID=$(APP_CORE_ID)
 DEFINES_APP += -DMCUBOOT_IMAGE_NUMBER=$(MCUBOOT_IMAGE_NUMBER)
 DEFINES_APP += -DUSE_SHARED_SLOT=$(USE_SHARED_SLOT)
+DEFINES_APP += -DMCUBOOT_PLATFORM_CHUNK_SIZE=$(PLATFORM_CHUNK_SIZE)
+DEFINES_APP += -DMEMORY_ALIGN=$(PLATFORM_MEMORY_ALIGN)
+DEFINES_APP += -DPLATFORM_MAX_TRAILER_PAGE_SIZE=$(PLATFORM_MAX_TRAILER_PAGE_SIZE)
 
 # Define MCUboot size and pass it to linker script
 LDFLAGS_DEFSYM  += -Wl,--defsym,BOOTLOADER_SIZE=$(BOOTLOADER_SIZE)
@@ -137,6 +158,12 @@
 SOURCES_LIBS += $(SOURCES_MBEDTLS_MXCRYPTO)
 endif
 
+# Use key provisioned in device to verify images
+ifeq ($(USE_HW_KEY), 1)
+DEFINES_APP=-DMCUBOOT_HW_KEY
+
+endif
+
 # Compile with user redefined values for UART HW, port, pins
 ifeq ($(USE_CUSTOM_DEBUG_UART), 1)
 DEFINES_APP += -DUSE_CUSTOM_DEBUG_UART=1
@@ -186,6 +213,7 @@
 
 # Collect MCUBoot sourses
 SOURCES_MCUBOOT := $(wildcard $(PRJ_DIR)/../bootutil/src/*.c)
+
 # Collect MCUBoot Application sources
 SOURCES_APP_SRC := main.c keys.c
 ifeq ($(USE_EXEC_TIME_CHECK), 1)
@@ -193,18 +221,16 @@
 SOURCES_APP_SRC += misc/timebase_us.c
 endif
 
-# Collect Flash Layer sources and header files dirs
-INCLUDE_DIRS_FLASH := $(PLATFORM_INCLUDE_DIRS_FLASH)
 INCLUDE_DIRS_UTILS := $(PLATFORM_INCLUDE_DIRS_UTILS)
-SOURCES_FLASH := $(PLATFORM_SOURCES_FLASH)
 
 # Collect all the sources
 SOURCES_APP := $(SOURCES_MCUBOOT)
-SOURCES_APP += $(SOURCES_FLASH)
 SOURCES_APP += $(addprefix $(CUR_APP_PATH)/, $(SOURCES_APP_SRC))
 SOURCES_APP += $(PLATFORM_APP_SOURCES)
 
 INCLUDE_DIRS_MCUBOOT := $(addprefix -I, $(PRJ_DIR)/../bootutil/include)
+INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(PRJ_DIR)/../bootutil/include/bootutil)
+INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(PRJ_DIR)/../bootutil/include/bootutil/crypto)
 INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(PRJ_DIR)/../bootutil/src)
 INCLUDE_DIRS_MCUBOOT += $(addprefix -I, $(PRJ_DIR)/..)
 
@@ -222,6 +248,9 @@
 ifeq ($(COMPILER), GCC_ARM)
 LDFLAGS += $(LDFLAGS_DEFSYM)
 LINKER_SCRIPT := $(CUR_APP_PATH)/$(APP_NAME)_$(CORE).ld
+ifeq ($(FAMILY), XMC7000)
+LINKER_SCRIPT := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/linker.ld
+endif
 else
 $(error Only GCC ARM is supported at this moment)
 endif
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
index d721274..c6e3361 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
@@ -64,8 +64,8 @@
      * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
      */
     ram               (rwx)   : ORIGIN = 0x08000A00, LENGTH = 0x1F600
-    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x17E90
-    smif_struct       (rx)    : ORIGIN = 0x10017E90, LENGTH = 0x170
+    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x27E90
+    smif_struct		  (rx)    : ORIGIN = 0x10027E90, LENGTH = 0x170
 
     /* This is an unprotected public RAM region, with the placed .cy_sharedmem.
      * This region is used to place objects that require full access from both cores.
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch b/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch
new file mode 100644
index 0000000..cde42b8
--- /dev/null
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM0P_Debug.launch
@@ -0,0 +1,62 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set remotetimeout 15"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${cy_tools_path:openocd}/bin/openocd"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s &quot;${openocd_path}/../scripts&quot;&#13;&#10;-c &quot;set QSPI_FLASHLOADER bsps/TARGET_APP_KIT_XMC72_EVK/config/GeneratedSource/CAT1C_SMIF.FLM&quot;&#13;&#10;-c &quot;source [find interface/kitprog3.cfg]&quot;&#13;&#10;-c &quot;transport select swd&quot;&#13;&#10;-c &quot;puts stderr {Started by GNU MCU Eclipse}&quot;&#13;&#10;-c &quot;source [find target/cat1c.cfg]&quot;&#13;&#10;-c &quot;gdb_port 3333&quot;&#13;&#10;-c &quot;cat1c sflash_restrictions 1&quot;&#13;&#10;-c &quot;init; reset init&quot;"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="mon reset run&#13;&#10;mon cat1c reset_halt sysresetreq&#13;&#10;flushregs&#13;&#10;mon gdb_sync&#13;&#10;stepi"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="init"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="./out/PSOC_062_2M/Debug/MCUBootApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_tools_path:CY_TOOL_arm-none-eabi-gdb_EXE}"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="/Users/rnok/repos/xmc7200/cy_mcuboot/boot/cypress/MCUBootApp/out/XMC7200/Debug/MCUBootApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="cy_mcuboot"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/cy_mcuboot"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;&gt;&#10;    &lt;memoryBlockExpression address=&quot;268828484&quot; label=&quot;0x1005ff44&quot;/&gt;&#10;    &lt;memoryBlockExpression address=&quot;268697600&quot; label=&quot;0x10040000&quot;/&gt;&#10;&lt;/memoryBlockExpressionList&gt;&#10;"/>
+    <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld
index db3671f..83be8e4 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld
@@ -186,6 +186,7 @@
         *cy_smif_sfdp.o(.text*)
         *cy_gpio.o(.text*)
         *cy_smif_hybrid_sect.o(.text*)
+        *fault_injection_hardening.o(.text*)
 
         . = ALIGN(4);
         __app_text_ram_end__ = .;
@@ -319,6 +320,7 @@
         *cy_smif_sfdp.o(.text*)
         *cy_gpio.o(.text*)
         *cyhal_system.o(.text*)
+        *fault_injection_hardening.o(.text*)
         *lib_a-memset.o(.text*)
         *lib_a-memcpy-stub.o(.text*)
 
@@ -368,6 +370,7 @@
         *cy_gpio.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
         *cycfg_qspi_memslot.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
         *cyhal_system.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+        *fault_injection_hardening.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
         *lib_a-memset.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
         *lib_a-memcpy-stub.o(.data* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
 
@@ -402,6 +405,7 @@
         *cy_smif_memslot.o(.bss* COMMON)
         *cy_smif_sfdp.o(.bss* COMMON)
         *cy_gpio.o(.bss* COMMON)
+        *fault_injection_hardening.o(.bss* COMMON)
         *lib_a-memset.o(.bss* COMMON)
         *lib_a-memcpy-stub.o(.bss* COMMON)
         KEEP(*(.cy_l1bss*))
@@ -423,7 +427,7 @@
         . = ALIGN(4);
         __text_begin = .;
 
-        *(EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o *cy_gpio.o *cy_smif_hybrid_sect.o) .text*)
+        *(EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o *cy_gpio.o *cy_smif_hybrid_sect.o *fault_injection_hardening.o) .text*)
 
         KEEP(*(.init))
         KEEP(*(.fini))
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld
index 95b4b19..06a074b 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld
@@ -317,14 +317,6 @@
     ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
 
 
-    /* Used for the digital signature of the secure application and the Bootloader SDK application.
-    * The size of the section depends on the required data size. */
-    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
-    {
-        KEEP(*(.cy_app_signature))
-    } > flash
-
-
     /* Emulated EEPROM Flash area */
     .cy_em_eeprom :
     {
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM7.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM7.ld
new file mode 100644
index 0000000..6b6de37
--- /dev/null
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM7.ld
@@ -0,0 +1,432 @@
+/***************************************************************************//**
+* \file xmc7200d_x8384_cm7.ld
+* \version 1.0.0
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+GROUP(-lgcc -lc -lnosys )
+SEARCH_DIR(.)
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM7 SRAM */
+STACK_SIZE = 0x1000;
+RAMVECTORS_ALIGNMENT                = 128;
+
+sram_start_reserve                  = 0;
+
+sram_total_size                     = 0x00100000; /* SRAM0 + SRAM1 */
+sram_private_for_srom               = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
+sram_used_by_boot                   = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
+
+cm0plus_sram_reserve                = 0x00020000; /* cm0 sram size */
+cm7_0_sram_reserve                  = 0x00030000; /* cm7_0 sram size */
+
+code_flash_total_size               = 0x00830000;
+cm0plus_code_flash_reserve          = 0x00080000;
+cm7_0_code_flash_reserve            = 0x00200000;
+
+code_flash_base_address             = 0x10000000;
+sram_base_address                   = 0x28000000;
+
+/* SRAM reservations */
+_base_SRAM_CM7_0                    = sram_base_address + cm0plus_sram_reserve;
+_size_SRAM_CM7_0                    = cm7_0_sram_reserve;
+/* In case of single CM7 device CM7_1 values should not be used */
+_base_SRAM_CM7_1                    = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
+_size_SRAM_CM7_1                    = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve;
+
+/* Code flash reservations */
+_base_CODE_FLASH_CM0P               = code_flash_base_address;
+_size_CODE_FLASH_CM0P               = cm0plus_code_flash_reserve;
+_base_CODE_FLASH_CM7_0              = code_flash_base_address + cm0plus_code_flash_reserve;
+_size_CODE_FLASH_CM7_0              = cm7_0_code_flash_reserve;
+_base_CODE_FLASH_CM7_1              = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
+_size_CODE_FLASH_CM7_1              = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
+
+/* Fixed Addresses */
+_base_WORK_FLASH                    = 0x14000000;
+_size_WORK_FLASH                    = 0x00040000;   /* 256K Work flash */
+_base_CM7_0_ITCM                    = 0xA0000000;
+_size_CM7_0_ITCM                    = 0x00004000;
+_base_CM7_0_DTCM                    = 0xA0010000;
+_size_CM7_0_DTCM                    = 0x00004000;
+_base_CM7_1_ITCM                    = 0xA0100000;
+_size_CM7_1_ITCM                    = 0x00004000;
+_base_CM7_1_DTCM                    = 0xA0110000;
+_size_CM7_1_DTCM                    = 0x00004000;
+
+/* For the non-dual cm7 device, _CORE_CM7_0_ should be defined and _CORE_CM7_1_ should not be defined */
+_base_SRAM                          = DEFINED(_CORE_CM7_1_) ? _base_SRAM_CM7_1 : DEFINED(_CORE_CM7_0_) ? _base_SRAM_CM7_0 : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_SRAM                          = DEFINED(_CORE_CM7_1_) ? _size_SRAM_CM7_1 : DEFINED(_CORE_CM7_0_) ? _size_SRAM_CM7_0 : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_base_CODE_FLASH                    = DEFINED(_CORE_CM7_1_) ? _base_CODE_FLASH_CM7_1 : DEFINED(_CORE_CM7_0_) ? _base_CODE_FLASH_CM7_0  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_CODE_FLASH                    = DEFINED(_CORE_CM7_1_) ? _size_CODE_FLASH_CM7_1 : DEFINED(_CORE_CM7_0_) ? _size_CODE_FLASH_CM7_0  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_base_SFLASH_USER_DATA              = 0x17000800;
+_size_SFLASH_USER_DATA              = 0x00000800;
+_base_SFLASH_NAR                    = 0x17001A00;
+_size_SFLASH_NAR                    = 0x00000200;
+_base_SFLASH_PUB_KEY                = 0x17006400;
+_size_SFLASH_PUB_KEY                = 0x00000C00;
+_base_SFLASH_APP_PROT               = 0x17007600;
+_size_SFLASH_APP_PROT               = 0x00000200;
+_base_SFLASH_TOC2                   = 0x17007C00;
+_size_SFLASH_TOC2                   = 0x00000200;
+_base_XIP                           = 0x60000000;
+_size_XIP                           = 0x08000000;
+_base_EFUSE                         = 0x90700000;
+_size_EFUSE                         = 0x00100000;
+_base_ITCM                          = DEFINED(_CORE_CM7_1_) ? _base_CM7_1_ITCM : DEFINED(_CORE_CM7_0_) ? _base_CM7_0_ITCM  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_ITCM                          = DEFINED(_CORE_CM7_1_) ? _size_CM7_1_ITCM : DEFINED(_CORE_CM7_0_) ? _size_CM7_0_ITCM  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_base_DTCM                          = DEFINED(_CORE_CM7_1_) ? _base_CM7_1_DTCM : DEFINED(_CORE_CM7_0_) ? _base_CM7_0_DTCM  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+_size_DTCM                          = DEFINED(_CORE_CM7_1_) ? _size_CM7_1_DTCM : DEFINED(_CORE_CM7_0_) ? _size_CM7_0_DTCM  : ASSERT(1<1, "Error: Either_CORE_CM7_0_ or _CORE_CM7_1_ not defined");
+
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+    /* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
+    ram                 (rxw)       : ORIGIN = _base_SRAM_CM7_0,            LENGTH = _size_SRAM_CM7_0 - 0x10000 /* SRAM */
+    flash_cm0p          (rx)        : ORIGIN = _base_CODE_FLASH_CM0P,       LENGTH = _size_CODE_FLASH_CM0P      /* CODE flash CM0+ */
+    flash               (rx)        : ORIGIN = _base_CODE_FLASH_CM7_0,      LENGTH = 0x20000                    /* CODE flash CM7_0/1 */
+
+    /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+     * You can assign sections to this memory region for only one of the cores.
+     */
+    em_eeprom           (rw)        : ORIGIN = _base_WORK_FLASH,            LENGTH = _size_WORK_FLASH           /* WORK flash */
+
+    /* The following regions define device specific memory regions and must not be changed. */
+    sflash_user_data    (rx)        : ORIGIN = _base_SFLASH_USER_DATA,      LENGTH = _size_SFLASH_USER_DATA     /* Supervisory flash: User data */
+    sflash_nar          (rx)        : ORIGIN = _base_SFLASH_NAR,            LENGTH = _size_SFLASH_NAR            /* Supervisory flash: Normal Access Restrictions (NAR) */
+    sflash_public_key   (rx)        : ORIGIN = _base_SFLASH_PUB_KEY,        LENGTH = _size_SFLASH_PUB_KEY       /* Supervisory flash: Public Key */
+    sflash_app_prot     (rx)        : ORIGIN = _base_SFLASH_APP_PROT,       LENGTH = _size_SFLASH_APP_PROT
+    sflash_toc_2        (rx)        : ORIGIN = _base_SFLASH_TOC2,           LENGTH = _size_SFLASH_TOC2          /* Supervisory flash: Table of Content # 2 */
+    xip                 (rx)        : ORIGIN = _base_XIP,                   LENGTH = _size_XIP                  /* XIP: 128 MB */
+    efuse               (rx)        : ORIGIN = _base_EFUSE,                 LENGTH = _size_EFUSE                /* 1MB */
+    itcm                (rx)        : ORIGIN = _base_ITCM,                  LENGTH = _size_ITCM                 /* ITCM */
+    dtcm                (rx)        : ORIGIN = _base_DTCM,                  LENGTH = _base_DTCM                 /* DTCM */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+SECTIONS
+{
+    /* Cortex-M0+ application flash image area. Comment this section if you don't want to include CM0+ image */
+    .cy_cm0p_image  ORIGIN(flash_cm0p):
+    {
+        . = ALIGN(4);
+        __cy_m0p_code_start = . ;
+        KEEP(*(.cy_m0p_image))
+        __cy_m0p_code_end = . ;
+    } > flash_cm0p
+
+    /* Check if .cy_m0p_image size exceeds cm0plus_code_flash_reserve */
+    ASSERT(__cy_m0p_code_end < ORIGIN(flash), "CM0+ flash image overflows with CM7, increase CM7 base address ")
+
+    /* Cortex-M7 application flash area */
+    .text ORIGIN(flash) :
+    {
+        /* Cortex-M7 flash vector table */
+        . = ALIGN(4);
+        __Vectors = . ;
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        . = ALIGN(4);
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* Read-only code (constants). */
+        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+        KEEP(*(.eh_frame*))
+    } > flash
+
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > flash
+
+    __exidx_start = .;
+
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > flash
+    __exidx_end = .;
+
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+
+        /* Copy data section to RAM */
+        LONG (__etext)                                      /* From */
+        LONG (__data_start__)                               /* To   */
+        LONG ((__data_end__ - __data_start__)/4)            /* Size */
+
+        __copy_table_end__ = .;
+    } > flash
+
+
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG ((__bss_end__ - __bss_start__)/4)
+        __zero_table_end__ = .;
+    } > flash
+
+    __etext =  . ;
+
+
+    .ramVectors (NOLOAD) :
+    {
+        . = ALIGN(RAMVECTORS_ALIGNMENT);
+        __ram_vectors_start__ = .;
+        KEEP(*(.ram_vectors))
+        __ram_vectors_end__   = .;
+    } > ram
+
+
+    .data __ram_vectors_end__ :
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+
+        KEEP(*(.cy_ramfunc*))
+        . = ALIGN(32);
+
+        KEEP(*(cy_sharedmem*))
+        . = ALIGN(4);
+
+        __data_end__ = .;
+
+    } > ram AT>flash
+
+
+    /* Place variables in the section that should not be initialized during the
+    *  device startup.
+    */
+    .noinit (NOLOAD) : ALIGN(8)
+    {
+      KEEP(*(.noinit))
+    } > ram
+
+
+    /* The uninitialized global or static variables are placed in this section.
+    *
+    * The NOLOAD attribute tells linker that .bss section does not consume
+    * any space in the image. The NOLOAD attribute changes the .bss type to
+    * NOBITS, and that  makes linker to A) not allocate section in memory, and
+    * A) put information to clear the section with all zeros during application
+    * loading.
+    *
+    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+    * This  makes linker to A) allocate zeroed section in memory, and B) copy
+    * this section to RAM during application loading.
+    */
+    .bss (NOLOAD):
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram
+
+
+    .heap (NOLOAD):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+        __HeapLimit = .;
+    } > ram
+
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        KEEP(*(.stack*))
+    } > ram
+
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(ram) + LENGTH(ram);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+    /* Emulated EEPROM Flash area */
+    .cy_em_eeprom :
+    {
+        KEEP(*(.cy_em_eeprom))
+    } > em_eeprom
+
+
+    /* Supervisory Flash: User data */
+    .cy_sflash_user_data :
+    {
+        KEEP(*(.cy_sflash_user_data))
+    } > sflash_user_data
+
+
+    /* Supervisory Flash: Normal Access Restrictions (NAR) */
+    .cy_sflash_nar :
+    {
+        KEEP(*(.cy_sflash_nar))
+    } > sflash_nar
+
+
+    /* Supervisory Flash: Public Key */
+    .cy_sflash_public_key :
+    {
+        KEEP(*(.cy_sflash_public_key))
+    } > sflash_public_key
+
+
+    /* Supervisory Flash: Table of Content # 2 */
+    .cy_toc_part2 :
+    {
+        KEEP(*(.cy_toc_part2))
+    } > sflash_toc_2
+
+    /* Places the code in the Execute in Place (XIP) section. See the smif driver
+    *  documentation for details.
+    */
+    cy_xip :
+    {
+        __cy_xip_start = .;
+        KEEP(*(.cy_xip))
+        __cy_xip_end = .;
+    } > xip
+
+
+    /* eFuse */
+    .cy_efuse :
+    {
+        KEEP(*(.cy_efuse))
+    } > efuse
+
+    /* itcm */
+    .cy_itcm :
+    {
+        KEEP(*(.cy_itcm))
+    } > itcm
+
+    /* dtcm */
+    .cy_dtcm :
+    {
+        KEEP(*(.cy_dtcm))
+    } > dtcm
+}
+
+
+/*============================================================
+ * Symbols for use by application
+ *============================================================
+ */
+
+__ecc_init_sram_start_address = ORIGIN(ram);
+__ecc_init_sram_end_address   = ORIGIN(ram) + LENGTH(ram);
+
+/* EOF */
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CYW20829_Debug.launch b/boot/cypress/MCUBootApp/MCUBootApp_CYW20829_Debug.launch
new file mode 100644
index 0000000..3b3300a
--- /dev/null
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CYW20829_Debug.launch
@@ -0,0 +1,59 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+    <stringAttribute key="com.cypress.studio.launch.mode" value="debug"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+    <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="/Users/rnok/Downloads/ASSETS/cyopenocd/openocd_4.3_1445/bin/openocd"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s &quot;/Users/rnok/Downloads/ASSETS/cyopenocd/openocd_4.3_1445/scripts&quot;&#13;&#10;-s &quot;./libs/TARGET_PSVP-CYW20829/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource&quot;&#13;&#10;-c &quot;set SMIF_LOADER /Users/rnok/repos/cyw20829/AnyCloud_CYW20829_Blinky_App/./libs/TARGET_PSVP-CYW20829/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/CYW208xx_SMIF.FLM&quot;&#13;&#10;-c &quot;source [find interface/kitprog3.cfg]&quot;&#13;&#10;-c &quot;puts stderr {Started by GNU MCU Eclipse}&quot;&#13;&#10;-c &quot;source [find target/cyw208xx.cfg]&quot;&#13;&#10;-c &quot;cyw208xx.cm33 configure -rtos auto -rtos-wipe-on-reset-halt 1&quot;&#13;&#10;-c &quot;gdb_breakpoint_override hard&quot;&#13;&#10;-c &quot;init; reset init&quot;"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
+    <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="flushregs"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="init"/>
+    <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${cy_prj_path}/build/PSVP-CYW20829/Debug/mtb-example-anycloud-blinky.bin"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="/Users/rnok/repos/cyw20829/cy_mcuboot/boot/cypress/MCUBootApp/out/CYW20829/Debug/MCUBootApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_tools_path:CY_TOOL_arm-none-eabi-gdb_EXE}"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="/Users/rnok/repos/cyw20829/cy_mcuboot/boot/cypress/MCUBootApp/out/CYW20829/Debug/MCUBootApp.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="MCUBootApp_CYW20829_Debug"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+    <listAttribute key="org.eclipse.debug.ui.favoriteGroups">
+        <listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#10;"/>
+    <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>
diff --git a/boot/cypress/MCUBootApp/README.md b/boot/cypress/MCUBootApp/README.md
new file mode 100644
index 0000000..bb53301
--- /dev/null
+++ b/boot/cypress/MCUBootApp/README.md
@@ -0,0 +1,221 @@
+### Port of MCUboot library to be used with Cypress targets
+
+**Solution Description**
+
+Given solution demonstrates operation of MCUboot on Cypress' PSoC6 device.
+
+There are two applications implemented:
+* MCUBootApp - PSoC6 MCUboot-based bootloading application;
+* BlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE;
+
+Cypress boards, that can be used with this evaluation example:
+- CY8CPROTO-062-4343W - PSoC 6 2M on board
+- CY8CKIT-062-WIFI-BT - PSoC 6 1M on board
+- CY8CPROTO-062S3-4343W - PSoC 6 512K on board
+The default flash map implemented is the following:
+
+Single-image mode.
+
+`[0x10000000, 0x10018000]` - MCUBootApp (bootloader) area;
+
+`[0x10018000, 0x10028000]` - primary slot for BlinkyApp;
+
+`[0x10028000, 0x10038000]` - secondary slot for BlinkyApp;
+
+`[0x10038000, 0x10039000]` - scratch area (not used);
+
+Size of slots `0x10000` - 64kb
+
+MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses completely SW implementation of cryptographic functions based on Mbed TLS Library.
+
+**Important**: make sure primary, secondary slot and bootloader app sizes are appropriate and correspond to flash area size defined in Applications' linker files.
+
+**Important**: make sure RAM areas of CM0p-based MCUBootApp bootloader and CM4-based BlinkyApp do not overlap.
+Memory (stack) corruption of CM0p application can cause failure if SystemCall-served operations invoked from CM4.
+
+### Hardware cryptography acceleration
+
+Cypress PSOC6 MCU family supports hardware acceleration of cryptography based on Mbed TLS Library via shim layer. Implementation of this layer is supplied as separate submodule `cy-mbedtls-acceleration`. HW acceleration of cryptography shortens boot time more then 4 times, comparing to software implementation (observation results).
+
+To enable hardware acceleration in `MCUBootApp` pass flag `USE_CRYPTO_HW=1` to `make` while build.
+
+Hardware acceleration of cryptography is enabled for PSOC6 devices by default.
+
+### How to modify memory map
+
+__Option 1.__
+
+Navigate to `sysflash.h` and modify the flash area(s) / slots sizes to meet your needs.
+
+__Option 2.__
+
+Navigate to `sysflash.h`, uncomment `memory_EXT_DESC` definition.
+Now define and initialize `struct flash_area *boot_area_descs[]` with flash memory addresses and sizes you need at the beginning of application, so flash APIs from `memory.c` will use it.
+
+__Note:__ for both options make sure you have updated `MCUBOOT_MAX_IMG_SECTORS` appropriatery with sector size assumed to be 512.
+
+**How to override the flash map values during build process:**
+
+Navigate to MCUBootApp.mk, find section `DEFINES_APP +=`
+Update this line and or add similar for flash map parameters to override.
+
+The possible list could be:
+
+* MCUBOOT_MAX_IMG_SECTORS
+* memory_EXT_DESC
+* CY_BOOT_SCRATCH_SIZE
+* CY_BOOT_BOOTLOADER_SIZE
+* CY_BOOT_PRIMARY_1_SIZE
+* CY_BOOT_SECONDARY_1_SIZE
+* CY_BOOT_PRIMARY_2_SIZE
+* CY_BOOT_SECONDARY_2_SIZE
+
+As an example in a makefile it should look like following:
+
+`DEFINES_APP +=-Dmemory_EXT_DESC`
+
+`DEFINES_APP +=-DMCUBOOT_MAX_IMG_SECTORS=512`
+
+`DEFINES_APP +=-DCY_BOOT_PRIMARY_1_SIZE=0x15000`
+
+**Multi-Image Operation**
+
+Multi-image operation considers upgrading and verification of more then one image on the device.
+
+To enable multi-image operation define `MCUBOOT_IMAGE_NUMBER` in `MCUBootApp/config/mcuboot_config.h` file should be set to 2 (only dual-image is supported at the moment). This could also be done on build time by passing `MCUBOOT_IMAGE_NUMBER=2` as parameter to `make`.
+
+Default value of `MCUBOOT_IMAGE_NUMBER` is 1, which corresponds to single image configuratios.
+
+In multi-image operation (two images are considered for simplicity) MCUboot Bootloader application operates as following:
+
+* Verifies Primary_1 and Primary_2 images;
+* Verifies Secondary_1 and Secondary_2 images;
+* Upgrades Secondary to Primary if valid images found;
+* Boots image from Primary_1 slot only;
+* Boots Primary_1 only if both - Primary_1 and Primary_2 are present and valid;
+
+This ensures two dependent applications can be accepted by device only in case both images are valid.
+
+**Default Flash map for Multi-Image operation:**
+
+`0x10000000 - 0x10018000` - MCUboot Bootloader
+
+`0x10018000 - 0x10028000` - Primary_1 (BOOT) slot of Bootloader
+
+`0x10028000 - 0x10038000` - Secondary_1 (UPGRADE) slot of Bootloader
+
+`0x10038000 - 0x10048000` - Primary_2 (BOOT) slot of Bootloader
+
+`0x10048000 - 0x10058000` - Secondary_2 (UPGRADE) slot of Bootloader
+
+`0x10058000 - 0x10059000` - Scratch of Bootloader
+
+Size of slots `0x10000` - 64kb
+
+__Note:__ It is also possible to place secondary (upgrade) slots in external memory module so resulting image size can be doubled.
+For more details about External Memory usage, please refer to separate guiding document `ExternalMemory.md`.
+
+### Hardware limitations
+
+Since this application is created to demonstrate MCUboot library features and not as reference examples some considerations are taken.
+
+1. `SCB5` used to configure serial port for debug prints. This is the most commonly used Serial Communication Block number among available Cypress PSoC 6 kits. If you try to use custom hardware with this application - change definition of `CYBSP_UART_HW` in `main.c` of MCUBootApp to SCB* that correspond to your design.
+
+2. `CY_SMIF_SLAVE_SELECT_0` is used as definition SMIF driver API. This configuration is used on evaluation kit for this example CY8CPROTO-062-4343W, CY8PROTO-062S3-4343W, CY8CKIT-062-4343W. If you try to use custom hardware with this application - change value of `smif_id` in `main.c` of MCUBootApp to value that corresponds to your design.
+
+
+### Downloading solution's assets
+
+There is a set assets required:
+
+* MCUBooot Library (root repository)
+* PSoC6 HAL Library
+* PSoC6 Peripheral Drivers Library (PDL)
+* Mbed TLS Cryptographic Library
+
+To get submodules - run the following command:
+
+    git submodule update --init --recursive
+
+### Building solution
+
+This folder contains make files infrastructure for building MCUBoot Bootloader. Same approach used in sample BlinkyLedApp application. Example command are provided below for couple different build configurations.
+
+* Build MCUBootApp in `Debug` for signle image use case.
+
+        make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug MCUBOOT_IMAGE_NUMBER=1
+
+* Build MCUBootApp in `Release` for multi image use case.
+
+        make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release MCUBOOT_IMAGE_NUMBER=2
+
+* To Build MCUBootApp with external memory support - pass `USE_EXTERNAL_FLASH=1` flag to `make` command in examples above. In this case UPGRADE image will be located in external memory. Refer to ExternalMemory.md for additional details.
+
+Root directory for build is **boot/cypress.**
+
+**Encrypted Image Support**
+
+To protect user image from unwanted read - Upgrade Image Encryption can be applied. The ECDH/HKDF with EC256 scheme is used in a given solution as well as Mbed TLS as a crypto provider.
+
+To enable image encryption support use `ENC_IMG=1` build flag (BlinkyApp should also be built with this flash set 1).
+
+User is also responsible for providing corresponding binary key data in `enc_priv_key[]` (file `\MCUBootApp\keys.c`). The public part will be used by imgtool when signing and encrypting upgrade image. Signing image with encryption is described in `\BlinkyApp\Readme.md`.
+
+After MCUBootApp is built with these settings unencrypted and encrypted images will be accepted in secondary (upgrade) slot.
+
+Example command:
+
+        make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug MCUBOOT_IMAGE_NUMBER=1 ENC_IMG=1
+
+**Programming solution**
+
+There are couple ways of programming hex of MCUBootApp and BlinkyApp. Following instructions assume one of Cypress development kits, for example `CY8CPROTO_062_4343W`.
+
+1. Direct usage of OpenOCD.
+OpenOCD package is supplied with ModuToolbox IDE and can be found in installation folder under `./tools_2.1/openocd`.
+Open terminal application -  and execute following command after substitution `PATH_TO_APPLICATION.hex` and `OPENOCD` paths.
+
+Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines.
+
+        export OPENOCD=/Applications/ModusToolbox/tools_2.1/openocd 
+
+        ${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
+                            -f ${OPENOCD}/scripts/interface/kitprog3.cfg \
+                            -f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
+                            -c "init; reset init; program PATH_TO_APPLICATION.hex" \
+                            -c "resume; reset; exit" 
+
+2. Using GUI tool `Cypress Programmer` - follow [link](https://www.cypress.com/products/psoc-programming-solutions) to download.
+   Connect board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines. Open `Cypress Programmer` and click `Connect`, then choose hex file: `MCUBootApp.hex` or `BlinkyApp.hex` and click `Program`.  Check log to ensure programming success. Reset board.
+
+3. Using `DAPLINK`.
+   Connect board to your computer. Switch embeded  Kitprog3 to `DAPLINK` mode by pressing `SW3 MODE` button until `LED2 STATUS` blinks fast and mass storage device appeared in OS. Drag and drop `hex` files you wish to program to `DAPLINK` drive in your OS.
+
+
+
+**Currently supported platforms:**
+
+* PSOC_062_2M
+* PSOC_062_1M
+* PSOC_062_512K
+
+**Build environment troubleshooting:**
+
+Regular shell/terminal combination on Linux and MacOS.
+
+On Windows:
+
+* Cygwin
+* Msys2
+
+Also IDE may be used:
+* Eclipse / ModusToolbox ("makefile project from existing source")
+
+*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
+
+*Python/Python3* - make sure you have correct path referenced in `PATH`;
+
+*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
+
+This will iherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.
+
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
index c2b2348..a1e36ba 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
@@ -65,7 +65,7 @@
  * to erase size of target hardware.
  */
 #ifndef MCUBOOT_PLATFORM_CHUNK_SIZE
-#define MCUBOOT_PLATFORM_CHUNK_SIZE 4096U
+#define MCUBOOT_PLATFORM_CHUNK_SIZE 0x200U
 #endif
 
 /*
diff --git a/boot/cypress/MCUBootApp/cy_serial_flash_prog.c b/boot/cypress/MCUBootApp/cy_serial_flash_prog.c
index 8bf7d8e..84197e1 100644
--- a/boot/cypress/MCUBootApp/cy_serial_flash_prog.c
+++ b/boot/cypress/MCUBootApp/cy_serial_flash_prog.c
@@ -1,4 +1,4 @@
-/***************************************************************************//**
+/*******************************************************************************
 * \file cy_serial_flash_prog.c
 *
 * \brief
diff --git a/boot/cypress/MCUBootApp/libs.mk b/boot/cypress/MCUBootApp/libs.mk
index 24bd642..c21c9cd 100644
--- a/boot/cypress/MCUBootApp/libs.mk
+++ b/boot/cypress/MCUBootApp/libs.mk
@@ -32,14 +32,12 @@
 THIS_APP_PATH = $(PRJ_DIR)/libs
 MBEDTLS_PATH = $(PRJ_DIR)/../../ext
 
+ifneq ($(FAMILY), XMC7000)
 # Add watchdog folder to build
 SOURCES_WATCHDOG := $(wildcard $(THIS_APP_PATH)/watchdog/*.c)
-
-# Add retartget IO implementation using pdl
-SOURCES_RETARGET_IO_PDL := $(PLATFORM_SOURCES_RETARGET_IO_PDL)
-
-# Collect dirrectories containing headers for PLATFORM
-INCLUDE_RETARGET_IO_PDL := $(PLATFORM_INCLUDE_RETARGET_IO_PDL)
+# Watchdog related includes
+INCLUDE_DIRS_WATCHDOG := $(THIS_APP_PATH)/watchdog
+endif
 
 # PSOC6HAL source files
 SOURCES_HAL_MCUB := $(PLATFORM_SOURCES_HAL_MCUB)
@@ -53,13 +51,10 @@
 # Collected source files for libraries
 SOURCES_LIBS += $(SOURCES_MBEDTLS)
 SOURCES_LIBS += $(SOURCES_WATCHDOG)
+SOURCES_LIBS += $(SOURCES_FIH)
 
 # Collect source files for platform dependent libraries
 SOURCES_LIBS += $(SOURCES_HAL_MCUB)
-SOURCES_LIBS += $(SOURCES_RETARGET_IO_PDL)
-
-# Watchdog related includes
-INCLUDE_DIRS_WATCHDOG := $(THIS_APP_PATH)/watchdog
 
 # MbedTLS related include directories
 ifeq ($(USE_CRYPTO_HW), 1)
@@ -76,31 +71,29 @@
 # Collected include directories for libraries
 INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_WATCHDOG))
 INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_FIH))
 
 # Collect platform dependent include dirs
 INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL_MCUB))
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_RETARGET_IO_PDL))
 
 ###############################################################################
 # Print debug information about all settings used and/or set in this file
 ifeq ($(VERBOSE), 1)
 $(info #### libs.mk ####)
+$(info INCLUDE_DIRS_FIH <-> $(INCLUDE_DIRS_FIH))
 $(info INCLUDE_DIRS_HAL_MCUB <-> $(INCLUDE_DIRS_HAL_MCUB))
-$(info INCLUDE_DIRS_LIBS --> $(INCLUDE_DIRS_LIBS))
+$(info INCLUDE_DIRS_LIBS <-> $(INCLUDE_DIRS_LIBS))
 $(info INCLUDE_DIRS_MBEDTLS <-> $(INCLUDE_DIRS_MBEDTLS))
 $(info INCLUDE_DIRS_WATCHDOG <-> $(INCLUDE_DIRS_WATCHDOG))
-$(info INCLUDE_RETARGET_IO_PDL <-> $(INCLUDE_RETARGET_IO_PDL))
 $(info MBEDTLS_PATH <-- $(MBEDTLS_PATH))
 $(info PLATFORM <-- $(PLATFORM))
 $(info PLATFORM_INCLUDE_DIRS_HAL_MCUB <-- $(PLATFORM_INCLUDE_DIRS_HAL_MCUB))
-$(info PLATFORM_INCLUDE_RETARGET_IO_PDL <-- $(PLATFORM_INCLUDE_RETARGET_IO_PDL))
 $(info PLATFORM_SOURCES_HAL_MCUB <-- $(PLATFORM_SOURCES_HAL_MCUB))
-$(info PLATFORM_SOURCES_RETARGET_IO_PDL <-- $(PLATFORM_SOURCES_RETARGET_IO_PDL))
 $(info PRJ_DIR <-- $(PRJ_DIR))
+$(info SOURCES_FIH <-> $(SOURCES_FIH))
 $(info SOURCES_HAL_MCUB <-> $(SOURCES_HAL_MCUB))
-$(info SOURCES_LIBS --> $(SOURCES_LIBS))
+$(info SOURCES_LIBS <-> $(SOURCES_LIBS))
 $(info SOURCES_MBEDTLS <-> $(SOURCES_MBEDTLS))
-$(info SOURCES_RETARGET_IO_PDL <-> $(SOURCES_RETARGET_IO_PDL))
 $(info SOURCES_WATCHDOG <-> $(SOURCES_WATCHDOG))
 $(info THIS_APP_PATH <-- $(THIS_APP_PATH))
 $(info USE_CRYPTO_HW <-- $(USE_CRYPTO_HW))
diff --git a/boot/cypress/MCUBootApp/main.c b/boot/cypress/MCUBootApp/main.c
index 8a78193..926e36d 100644
--- a/boot/cypress/MCUBootApp/main.c
+++ b/boot/cypress/MCUBootApp/main.c
@@ -22,21 +22,16 @@
 
 /* Cypress pdl headers */
 #include "cy_pdl.h"
-
-#ifdef CYW20829
-#include "cy_retarget_io.h"
-#include "cybsp.h"
+#include "cyhal.h"
 #include "cyhal_wdt.h"
-#include "cyw_platform_utils.h"
+
+#if defined CYW20829
 #include "cy_service_app.h"
-#else
-#include "cy_retarget_io_pdl.h"
-#include "cycfg_clocks.h"
-#include "cycfg_peripherals.h"
-#if defined APP_CM0P || defined CM4
+#endif
+
+#include "cybsp.h"
+#include "cy_retarget_io.h"
 #include "cyw_platform_utils.h"
-#endif /* defined APP_CM0P || defined CM4  */
-#endif /* defined CYW20829 */
 
 #if defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829)
 #include "flash_qspi.h"
@@ -55,8 +50,6 @@
 
 #include "bootutil/fault_injection_hardening.h"
 
-#include "watchdog.h"
-
 #ifdef USE_EXEC_TIME_CHECK
 #include "misc/timebase_us.h"
 #include "misc/exec_time_check.h"
@@ -85,7 +78,7 @@
 #define SMIF_ID         (1U) /* Assume SlaveSelect_0 is used for External Memory */
 #endif /* CY_BOOT_USE_EXTERNAL_FLASH */
 
-#define BOOT_MSG_FINISH "MCUBoot Bootloader finished.\n" \
+#define BOOT_MSG_FINISH "MCUBoot Bootloader finished.\r\n" \
                         "Deinitializing hardware..."
 
 static void hw_deinit(void);
@@ -98,7 +91,7 @@
                            rsp->br_hdr->ih_hdr_size);
 }
 
-#ifdef CYW20829
+#if defined CYW20829
 
 #if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
 CY_RAMFUNC_BEGIN /* SMIF will be deinitialized in this case! */
@@ -117,18 +110,18 @@
 CY_RAMFUNC_END /* SMIF will be deinitialized in this case! */
 #endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
 
-#endif /* CYW20829 */
+#endif /* defined CYW20829 */
 
 static bool do_boot(struct boot_rsp *rsp)
 {
     uintptr_t flash_base = 0;
 
-#ifdef CYW20829
+#if defined CYW20829
     uint32_t *key = NULL;
     uint32_t *iv = NULL;
-#endif /* CYW20829 */
+#endif /* defined CYW20829 */
 
-    if (rsp != NULL) {
+    if ((rsp != NULL) && (rsp->br_hdr != NULL)) {
         int rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
 
         if (0 == rc) {
@@ -141,11 +134,12 @@
             BOOT_LOG_INF("Start slot Address: 0x%08" PRIx32, (uint32_t)fih_uint_decode(app_addr));
 
             rc = flash_device_base(rsp->br_flash_dev_id, &flash_base);
-            if ((rc != 0) || fih_uint_not_eq(calc_app_addr(flash_base, rsp), app_addr)) {
+            if (rc != 0 || fih_uint_eq(calc_app_addr(flash_base, rsp), app_addr) != FIH_TRUE) {
                 return false;
             }
 
-#ifdef CYW20829
+#if defined CYW20829
+
 #ifdef MCUBOOT_ENC_IMAGES_XIP
             if (IS_ENCRYPTED(rsp->br_hdr)) {
                 key = rsp->xip_key;
@@ -179,15 +173,15 @@
             BOOT_LOG_INF("Launching app on CM4 core");
             BOOT_LOG_INF(BOOT_MSG_FINISH);
             hw_deinit();
-#ifdef CM0P
+#ifdef BOOT_CM0P
             Cy_SysEnableCM4(fih_uint_decode(app_addr));
             return true;
 #else
             psoc6_launch_cm4_app(app_addr);
-#endif /* CM0P */
+#endif /* BOOT_CM0P */
 
 #elif defined APP_CM0P
-#ifdef CM0P
+#ifdef BOOT_CM0P
             /* This function does not return */
             BOOT_LOG_INF("Launching app on CM0P core");
             BOOT_LOG_INF(BOOT_MSG_FINISH);
@@ -195,8 +189,15 @@
             psoc6_launch_cm0p_app(app_addr);
 #else
 #error "Application should run on Cortex-M4"
-#endif /* CM0P */
+#endif /* BOOT_CM0P */
 
+#elif defined APP_CM7
+            /* This function does not return */
+            BOOT_LOG_INF("Launching app on CM7 core");
+            BOOT_LOG_INF(BOOT_MSG_FINISH);
+            hw_deinit();
+            xmc7000_launch_cm7_app(app_addr);
+            return true;
 #else
 #error "Application should run on either Cortex-M0+ or Cortex-M4"
 #endif /* APP_CM4 */
@@ -213,13 +214,12 @@
 
 int main(void)
 {
-    struct boot_rsp rsp;
-    cy_rslt_t rc = MCUBOOTAPP_RSLT_ERR;
+    struct boot_rsp rsp = {};
     bool boot_succeeded = false;
     fih_int fih_rc = FIH_FAILURE;
+    cy_rslt_t rc = cybsp_init();
 
-#ifdef CYW20829
-    rc = cybsp_init();
+
     if (rc != CY_RSLT_SUCCESS) {
         CY_ASSERT((bool)0);
         /* Loop forever... */
@@ -227,11 +227,6 @@
             __WFI();
         }
     }
-#else
-    SystemInit();
-    init_cycfg_peripherals();
-    init_cycfg_pins();
-#endif /* CYW20829 */
 
 #ifdef USE_EXEC_TIME_CHECK
     timebase_us_init();
@@ -251,20 +246,16 @@
      * to keep CM4 disabled. Note that debugging of CM4 is not supported when it
      * is disabled.
      */
-#if !defined CYW20829
-#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CM4)
+#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(BOOT_CM4)
     if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()) {
         Cy_SysDisableCM4();
     }
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CM4) */
-    /* Initialize retarget-io to use the debug UART port (CYBSP_UART_HW) */
-    rc = cy_retarget_io_pdl_init(CY_RETARGET_IO_BAUDRATE);
-#else
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(BOOT_CM4) */
     /* Initialize retarget-io to use the debug UART port */
     rc = cy_retarget_io_init(CYBSP_DEBUG_UART_TX,
                              CYBSP_DEBUG_UART_RX,
                              CY_RETARGET_IO_BAUDRATE);
-#endif /* CYW20829 */
+
     if (rc != CY_RSLT_SUCCESS) {
         CY_ASSERT((bool)0);
         /* Loop forever... */
@@ -303,7 +294,6 @@
         }
 #endif /* CYW20829 && MCUBOOT_HW_ROLLBACK_PROT */
 
-        (void)memset(&rsp, 0, sizeof(rsp));
 #ifdef USE_EXEC_TIME_CHECK
         {
             uint32_t exec_time;
@@ -315,20 +305,17 @@
             BOOT_LOG_INF("Exec time: %" PRIu32 " [ms]", exec_time / 1000U);
         }
 #endif /* USE_EXEC_TIME_CHECK */
-        if (true == fih_eq(fih_rc, FIH_SUCCESS)) {
+        if (FIH_TRUE == fih_eq(fih_rc, FIH_SUCCESS)) {
             BOOT_LOG_INF("User Application validated successfully");
             /* initialize watchdog timer. it should be updated from user app
             * to mark successful start up of this app. if the watchdog is not updated,
             * reset will be initiated by watchdog timer and swap revert operation started
             * to roll back to operable image.
             */
-#ifdef CYW20829
-            cyhal_wdt_t *cyw20829_wdt = NULL;
+            cyhal_wdt_t *wdt = NULL;
 
-            rc = cyhal_wdt_init(cyw20829_wdt, WDT_TIME_OUT_MS);
-#else
-            rc = cy_wdg_init(WDT_TIME_OUT_MS);
-#endif /* CYW20829 */
+            rc = cyhal_wdt_init(wdt, WDT_TIME_OUT_MS);
+
             if (CY_RSLT_SUCCESS == rc) {
 
                 boot_succeeded = do_boot(&rsp);
@@ -355,23 +342,13 @@
 
 static void hw_deinit(void)
 {
-#ifdef CYW20829
-    /* Flush the TX buffer, need to be fixed in retarget_io */
-    Cy_SysLib_Delay(50);
-
-    cy_retarget_io_deinit();
-    cy_wdg_stop();
-    cy_wdg_free();
-    /* Note: qspi_deinit() is called (if needed) in cyw20829_launch_app() above */
-#else
-    cy_retarget_io_wait_tx_complete(CYBSP_UART_HW, 10);
-    cy_retarget_io_pdl_deinit();
-    Cy_GPIO_Port_Deinit(CYBSP_UART_RX_PORT);
-    Cy_GPIO_Port_Deinit(CYBSP_UART_TX_PORT);
 #if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) && !defined(USE_XIP)
     qspi_deinit(SMIF_ID);
 #endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
-#endif /* CYW20829 */
+
+    /* Flush the TX buffer, need to be fixed in retarget_io */
+    while(cy_retarget_io_is_tx_active()){}
+    cy_retarget_io_deinit();
 
 #ifdef USE_EXEC_TIME_CHECK
     timebase_us_deinit();
diff --git a/boot/cypress/Makefile b/boot/cypress/Makefile
index 0f0a378..a444c04 100644
--- a/boot/cypress/Makefile
+++ b/boot/cypress/Makefile
@@ -46,6 +46,8 @@
 THREADS_NUM ?= 8
 
 SIGN_KEY_FILE ?= cypress-test-ec-p256
+SECURE_MODE_KEY_NAME ?= cypress-test-rsa2k
+SECURE_MODE_KEY_TYPE ?= RSA2048
 ENC_KEY_FILE ?= enc-ec256-pub
 ENC_IMG ?= 0
 
@@ -109,10 +111,6 @@
 # updating CFLAGS at this point as DEFINES are completed
 CFLAGS += $(DEFINES) $(CFLAGS_OPTIMIZATION)
 
-ifeq ($(WARN_AS_ERR), 1)
-CC_WARN_IN_ERR_FLAGS := -Werror
-endif
-
 VPATH = $(dir $(C_FILES) $(ASM_FILES) $(C_LIBS))
 
 LDFLAGS += $(LDFLAGS_OPTIMIZATION)
@@ -181,9 +179,9 @@
 	@echo "CC $<"
 ifeq ($(VERBOSE), 1)
 	@echo
-	@echo $(CC) $(CFLAGS) $(CC_WARN_IN_ERR_FLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
+	@echo $(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
 endif
-	@$(CC) $(CFLAGS) $(CC_WARN_IN_ERR_FLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
+	@$(CC) $(CFLAGS) $(INCLUDE_DIRS) $(CC_DEPEND) $(@:.o=.d) -c $< -o $@
 
 $(OUT_OBJ)/%.o: %.S
 	@echo "AS $<"
@@ -208,17 +206,17 @@
 
 clean:
 	@echo "Cleanup out directory..."
-	rm -f ./$(APP_NAME)/flashmap.mk ./platforms/cy_flash_pal/cy_flash_map.h
+	rm -f ./$(APP_NAME)/memorymap.mk ./platforms/memory/cy_flash_map.h ./platforms/memory/memorymap.h ./platforms/memory/memorymap.c
 	rm -rf $(OUT_TARGET)/$(BUILDCFG)
 
 clean_boot:
 	@echo "Cleanup out BOOT directory of $(APP_NAME)..."
-	rm -f ./$(APP_NAME)/flashmap.mk
+	rm -f ./$(APP_NAME)/memorymap.mk
 	rm -rf $(OUT_TARGET)/$(BUILDCFG)/boot
 
 clean_upgrade:
 	@echo "Cleanup out UPGRADE directory of $(APP_NAME)..."
-	rm -f ./$(APP_NAME)/flashmap.mk
+	rm -f ./$(APP_NAME)/memorymap.mk
 	rm -rf $(OUT_TARGET)/$(BUILDCFG)/upgrade
 
 run_cppcheck:
@@ -230,6 +228,15 @@
 	../../scripts/imgtool.py keygen -k keys/$(SIGN_KEY_FILE).pem -t ecdsa-p256
 	../../scripts/imgtool.py getpub -k keys/$(SIGN_KEY_FILE).pem > keys/$(SIGN_KEY_FILE).pub
 
+gen_secure_cfgs:
+ifeq ($(SECURE_MODE_KEY_NAME), cypress-test-rsa2k)
+	@echo "Generating public $(SECURE_MODE_KEY_TYPE) keys"
+	cysecuretools -t $(PLATFORM) create-key --key-type $(SECURE_MODE_KEY_TYPE) -o ./keys/$(SECURE_MODE_KEY_NAME).pem ./keys/$(SECURE_MODE_KEY_NAME).pub --format PEM
+endif
+	@echo "Generating secure mode key config"
+	cysecuretools convert-key -k ./keys/$(SECURE_MODE_KEY_NAME).pub -o ./platforms/utils/$(FAMILY)/cy_si_key.c --fmt secure_boot --endian little
+
+
 ###############################################################################
 # Print debug information about all settings used and/or set in this file
 ifeq ($(VERBOSE), 1)
@@ -244,7 +251,6 @@
 $(info BUILDCFG <-> $(BUILDCFG))
 $(info CC <-- $(CC))
 $(info CC_DEPEND <-- $(CC_DEPEND))
-$(info CC_WARN_IN_ERR_FLAGS <-> $(CC_WARN_IN_ERR_FLAGS))
 $(info CFLAGS <-> $(CFLAGS))
 $(info CFLAGS_OPTIMIZATION <-- $(CFLAGS_OPTIMIZATION))
 $(info COMPILER <-- $(COMPILER))
diff --git a/boot/cypress/README.md b/boot/cypress/README.md
index fb9d8ee..cca2c2f 100644
--- a/boot/cypress/README.md
+++ b/boot/cypress/README.md
@@ -1,56 +1,47 @@
-## Port of MCUboot library for evaluation with Cypress PSoC™ 6 and CYW20829 chips
+### Port of MCUBoot library for evaluation with Cypress PSoC 6 chips
 
 ### Disclaimer
 
-This solution is included in the `MCUboot` repository in order to demonstrate the basic concepts and features of the MCUboot library on PSoC™ 6 and CYW20829 devices. Applications are created per MCUboot library maintainers requirements. The implementation differs from conventional and recommended by Cypress Semiconductors development flow for PSoC™ 6 and CYW20829 devices. These applications are not recommended as a starting point for development because they are not supported examples.
+Given solution is included in `MCUboot` repository with purpose to demonstrate basic consepts and features of MCUboot library on Cypress PSoC 6 device. Applications are created per MCUboot library maintainers requirements. Implemetation differs from conventional and recomended by Cypress Semiconductors development flow for PSoC 6 devices. These applications are not recomended as a starting point for development and should not be considered as supported examples for PSoC 6 devices.
 
-Examples provided to use with **ModusToolbox™ Software Environment** are a recommended reference point to start development of MCUboot based bootloaders for PSoC™ 6 and CYW20829 devices.
+Examples provided to use with **ModusToolbox® Software Environment** are a recommended reference point to start development of MCUboot based bootloaders for PSoC 6 devices.
 
-For examples, refer to the **Infineon Technologies AG** [github](https://github.com/Infineon/Code-Examples-for-ModusToolbox-Software) page.
+Refer to **Cypress Semiconductors** [github](https://github.com/cypresssemiconductorco) page to find examples.
 
-1. MCUboot-based basic bootloader [mtb-example-psoc6-mcuboot-basic](https://github.com/Infineon/mtb-example-psoc6-mcuboot-basic)
-2. MCUboot-based bootloader with rollback to factory app in external flash [mtb-example-anycloud-mcuboot-rollback](https://github.com/Infineon/mtb-example-anycloud-mcuboot-rollback)
+1. MCUboot-Based Basic Bootloader [mtb-example-psoc6-mcuboot-basic](https://github.com/cypresssemiconductorco/mtb-example-psoc6-mcuboot-basic)
+2. MCUboot-Based Bootloader with Rollback to Factory App in External Flash [mtb-example-anycloud-mcuboot-rollback](https://github.com/cypresssemiconductorco/mtb-example-anycloud-mcuboot-rollback)
 
 ### Solution description
 
-The two applications implemented:
-* MCUBootApp - PSoC™ 6 and CYW20829 MCUboot-based bootloading application
-* BlinkyApp - a simple PSoC™ 6 and CYW20829 blinking LED application, which is a target of BOOT/UPGRADE
+There are two applications implemented:
+* MCUBootApp - PSoC6 MCUboot-based bootloading application;
+* BlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE;
 
-#### MCUBootApp
+The default flash map for MCUBootApp implemented is next:
 
-* The two types of upgrade operation supported:
-  * **Overwrite only** - The secondary image is only copied to the primary slot after validation.
-  * **Swap** - The secondary and primary slots images are swapped during the upgrade process. Upgrade operation can be reverted if the secondary image is bad. "Bad image" does not set the imageOK flag in the image trailer. If imageOK is not set, MCUBootApp does not turn off WatchDog Timer and WDT resets the device to start the REVERT procedure.
+* [0x10000000, 0x10018000] - MCUBootApp (bootloader) area;
+* [0x10018000, 0x10028000] - primary slot for BlinkyApp;
+* [0x10028000, 0x10038000] - secondary slot for BlinkyApp;
+* [0x10038000, 0x10039000] - scratch area;
 
-* The two types of operation modes supported:
-  * Single image
-  * Multi image
+The flash map is defined through sysflash.h and memory.c.
 
-* Some or all partitions (slots) can be placed in external memory. For more details about external memory usage, refer to [ExternalMemory.md](MCUBootApp/ExternalMemory.md).
+It is also possible to place secondary (upgrade) slots in external memory module. In this case primary slot can be doubled in size.
+For more details about External Memory usage, please refer to separate guiding document `MCUBootApp/ExternalMemory.md`.
 
-* MCUBootApp checks the image integrity with SHA256, image authenticity with EC256 digital signature verification.
-* Cryptographic functions can be based on completely software implementation or be hardware accelerated on some platforms. The mbedTLS library is used in both cases.
-
-For more details on **MCUBootApp**, refer to [MCUBootApp.md](MCUBootApp/MCUBootApp.md).
-
-#### BlinkyApp
-* Can be built to use either primary or secondary image for both internal and external flash memory.
-* Primary and secondary images differ in text printed to the serial terminal and LED-blinking frequency.
-* The watchdog timer functionality is supported to confirm successful start/upgrade of the application.
-* The user-application side of MCUboot swap operation is demonstrated by two kinds of user images, compiled for the primary and secondary slot.
-
-For more details on **BlinkyApp**, refer to [BlinkyApp.md](BlinkyApp/BlinkyApp.md).
+MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses either completely software implementation of cryptographic functions or accelerated by hardware - both based on Mbed TLS Library.
 
 ### Downloading solution's assets
 
-The set of required libraries represented as submodules:
+There is a set assets required:
 
-* MCUBooot library (root repository)
-* Peripheral Drivers library (PDL)
-* mbedTLS Cryptographic library
+* MCUBooot Library (root repository)
+* PSoC6 Peripheral Drivers Library (PDL)
+* Mbed TLS Cryptographic Library
 
-To retrieve source code with subsequent submodules, pull:
+Those are represented as submodules.
+
+To retrieve source code with subsequent submodules pull:
 
     git clone --recursive https://github.com/mcu-tools/mcuboot.git
 
@@ -59,15 +50,17 @@
     cd mcuboot
     git submodule update --init --recursive
 
+
+
 ### Building solution
 
-The root directory for build is `boot/cypress`.
+Root directory for build is **boot/cypress.**
 
-The root folder contains a make-files infrastructure for building both MCUBootApp bootloading-application and BlinkyApp user-application.
+This folder contains make files infrastructure for building both MCUboot Bootloader and sample BlinkyApp application used for Bootloader demo functionality.
 
-For instructions on how to build and upload MCUBootApp bootloading-application and sample user-application, refer to the [MCUBootApp.md](MCUBootApp/MCUBootApp.md) and [BlinkyApp.md](BlinkyApp/BlinkyApp.md) files in corresponding folders.
+Instructions on how to build and upload MCUBootApp bootloader application and sample user applocation are located in `Readme.md` files in corresponding folders.
 
-**Toolchain**
+Supported platforms for `MCUboot`, `BlinkyApp`:
 
 **GCC_ARM** is only supported (built and verified on GCC 9.3.1).
 
@@ -79,18 +72,21 @@
 
 Below is an example on how to set toolchin path to the latest include with **ModusToolbox™ IDE 3.0**:
 
-    make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/$(USERNAME)/ModusToolbox/tools_3.0/gcc
+    make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.0/gcc
 
 ### Build environment troubleshooting
 
-The following CLI/IDE are supported for project build:
+Following CLI / IDE are supported for project build:
 
 * Cygwin on Windows systems
 * unix style shells on *nix systems
-* Eclipse / ModusToolbox™ ("makefile project from existing source")
+* Eclipse / ModusToolbox ("makefile project from existing source")
 
-*Make* - Ensure that it is added to the system's `PATH` variable and the correct path is the first on the list.
+*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
 
-*Python/Python3* - Ensure that you have the correct path referenced in `PATH`.
+*Python/Python3* - make sure you have correct path referenced in `PATH`;
 
-*Msys2* - To use the system's path, navigate to the msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart the MSYS2 shell. This will inherit the system's path and find `python` installed in a regular way as well as `imgtool` and its dependencies.
+*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
+
+This will inherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.
+
diff --git a/boot/cypress/common_libs.mk b/boot/cypress/common_libs.mk
index 954d385..52aaf49 100644
--- a/boot/cypress/common_libs.mk
+++ b/boot/cypress/common_libs.mk
@@ -42,22 +42,39 @@
 SOURCES_PDL_STARTUP := $(COMPONENT_CORE_PATH)/$(PLATFORM_SOURCES_PDL_STARTUP)
 
 # Collect source files for Retarget-io
-SOURCES_RETARGET_IO := $(PLATFORM_SOURCES_RETARGET_IO)
+SOURCES_RETARGET_IO := $(wildcard $(PRJ_DIR)/libs/retarget-io/*.c)
 
 # HAL source files
-SOURCES_HAL := $(PLATFORM_SOURCES_HAL)
+SOURCES_HAL := $(wildcard $(PRJ_DIR)/libs/mtb-hal-cat1/source/*.c)
+SOURCES_HAL += $(wildcard $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/pin_packages/*.c)
+SOURCES_HAL += $(wildcard $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/triggers/*.c)
 
 # Add platform folder to build
 SOURCES_PLATFORM := $(wildcard $(PRJ_DIR)/platforms/BSP/$(FAMILY)/*.c)
 SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/security_counter/*.c)
 SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/security_counter/$(FAMILY)/*.c)
+SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/memory/*.c)
+SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/memory/$(FAMILY)/*.c)
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/memory/external_memory/*.c)
+SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/memory/$(FAMILY)/flash_qspi/*.c)
+endif
+SOURCES_PLATFORM += $(PLATFORM_SOURCES_FLASH)
 
 # PDL related include directories
 INCLUDE_DIRS_PDL := $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/include
+INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/third_party/ethernet/include
 INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/ip
 INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include
 INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/templates/COMPONENT_MTB
 
+# HAL related include directories
+INCLUDE_DIRS_HAL := $(CY_LIBS_PATH)/mtb-hal-cat1/include
+INCLUDE_DIRS_HAL += $(CY_LIBS_PATH)/mtb-hal-cat1/include_pvt
+INCLUDE_DIRS_HAL += $(CY_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/
+INCLUDE_DIRS_HAL += $(CY_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/pin_packages
+INCLUDE_DIRS_HAL += $(CY_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/triggers
+
 INCLUDE_DIRS_CMSIS += $(CY_LIBS_PATH)/cmsis/Core/Include
 
 # core-libs related include directories
@@ -67,15 +84,21 @@
 INCLUDE_DIRS_PDL_STARTUP += $(COMPONENT_CORE_PATH)/HEADER_FILES
 
 # Retarget-io related include directories
-INCLUDE_DIRS_RETARGET_IO := $(PLATFORM_INCLUDE_DIRS_RETARGET_IO)
-
-# HAL include directories files
-INCLUDE_DIRS_HAL := $(PLATFORM_INCLUDE_DIRS_HAL)
+INCLUDE_DIRS_RETARGET_IO := $(THIS_APP_PATH)/retarget-io
 
 # Include platforms folder
-INCLUDE_DIRS_PLATFORM := $(PRJ_DIR)/platforms//BSP/$(FAMILY)
+INCLUDE_DIRS_PLATFORM := $(PRJ_DIR)/platforms/BSP/$(FAMILY)
 INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/security_counter/$(FAMILY)
 INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/security_counter
+INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/memory
+INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/memory/flash_map_backend
+INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/memory/$(FAMILY)
+INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/memory/$(FAMILY)/include
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/memory/external_memory
+INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/memory/$(FAMILY)/flash_qspi
+endif
+INCLUDE_DIRS_PLATFORM += $(PLATFORM_INCLUDE_DIRS_FLASH)
 INCLUDE_DIRS_PLATFORM += $(PLATFORM_INCLUDE_DIRS_PDL_STARTUP)
 
 # Assembler startup file for platform
@@ -83,14 +106,15 @@
 
 # Collected source files for libraries
 SOURCES_LIBS := $(SOURCES_PDL)
+SOURCES_LIBS += $(SOURCES_HAL)
 SOURCES_LIBS += $(SOURCES_PDL_SYSTEM)
 SOURCES_LIBS += $(SOURCES_PDL_STARTUP)
 SOURCES_LIBS += $(SOURCES_PDL_RUNTIME)
-SOURCES_LIBS += $(SOURCES_HAL)
 SOURCES_LIBS += $(SOURCES_RETARGET_IO)
 
 # Collected include directories for libraries
 INCLUDE_DIRS_LIBS := $(addprefix -I,$(INCLUDE_DIRS_PDL))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL))
 INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_CMSIS))
 INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_PDL_STARTUP))
 INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_CORE_LIB))
diff --git a/boot/cypress/libs/cy-mbedtls-acceleration b/boot/cypress/libs/cy-mbedtls-acceleration
index a9a4aef..b61f07e 160000
--- a/boot/cypress/libs/cy-mbedtls-acceleration
+++ b/boot/cypress/libs/cy-mbedtls-acceleration
@@ -1 +1 @@
-Subproject commit a9a4aef9153e4890379690d8d695e96a9d864762
+Subproject commit b61f07e62037c00eabf60afbf048ee254bc99a1e
diff --git a/boot/cypress/libs/mtb-hal-cat1 b/boot/cypress/libs/mtb-hal-cat1
index 282ef6e..b62baf5 160000
--- a/boot/cypress/libs/mtb-hal-cat1
+++ b/boot/cypress/libs/mtb-hal-cat1
@@ -1 +1 @@
-Subproject commit 282ef6e565290f097e02a7afbe6dcde30c0f4028
+Subproject commit b62baf5e65de50af87dce5b76f3d5ccf0e93132b
diff --git a/boot/cypress/libs/mtb-pdl-cat1 b/boot/cypress/libs/mtb-pdl-cat1
index 8ed7d45..e851dc2 160000
--- a/boot/cypress/libs/mtb-pdl-cat1
+++ b/boot/cypress/libs/mtb-pdl-cat1
@@ -1 +1 @@
-Subproject commit 8ed7d4526dcc8d1c2efb96f7f56da8d5dc043227
+Subproject commit e851dc2c1a9f7acaf29aad83c7e65ccd48cec453
diff --git a/boot/cypress/libs/retarget-io b/boot/cypress/libs/retarget-io
deleted file mode 160000
index 3072757..0000000
--- a/boot/cypress/libs/retarget-io
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 30727575b7bdd69df69d47c74e4fb56ced3633c4
diff --git a/boot/cypress/libs/retarget-io/cy_retarget_io.c b/boot/cypress/libs/retarget-io/cy_retarget_io.c
new file mode 100644
index 0000000..c508666
--- /dev/null
+++ b/boot/cypress/libs/retarget-io/cy_retarget_io.c
@@ -0,0 +1,609 @@
+/***************************************************************************//**
+* \file cy_retarget_io.c
+*
+* \brief
+* Provides APIs for retargeting stdio to UART hardware contained on the Cypress
+* kits.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_retarget_io.h"
+#include "cyhal_hw_types.h"
+#include "cyhal_uart.h"
+#include "cy_utils.h"
+#include "cyhal_system.h"
+#include <stdbool.h>
+#include <stdlib.h>
+
+#if (defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)) && defined(__GNUC__) && \
+    !defined(__ARMCC_VERSION) && !defined(__clang__)
+
+// The cyhal_uart driver is not necessarily thread-safe. To avoid concurrent
+// access, the ARM and IAR libraries use mutexes to control access to stdio
+// streams. For Newlib, the mutex must be implemented in _write(). For all
+// libraries, the program must start the RTOS kernel before calling any stdio
+// functions.
+
+#include "cyabs_rtos.h"
+
+static cy_mutex_t cy_retarget_io_mutex;
+static bool       cy_retarget_io_mutex_initialized = false;
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_mutex_init
+//--------------------------------------------------------------------------------------------------
+static cy_rslt_t cy_retarget_io_mutex_init(void)
+{
+    cy_rslt_t rslt;
+    if (cy_retarget_io_mutex_initialized)
+    {
+        rslt = CY_RSLT_SUCCESS;
+    }
+    else if (CY_RSLT_SUCCESS == (rslt = cy_rtos_init_mutex(&cy_retarget_io_mutex)))
+    {
+        cy_retarget_io_mutex_initialized = true;
+    }
+    return rslt;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_mutex_acquire
+//--------------------------------------------------------------------------------------------------
+static void cy_retarget_io_mutex_acquire(void)
+{
+    CY_ASSERT(cy_retarget_io_mutex_initialized);
+    cy_rslt_t rslt = cy_rtos_get_mutex(&cy_retarget_io_mutex, CY_RTOS_NEVER_TIMEOUT);
+    if (rslt != CY_RSLT_SUCCESS)
+    {
+        abort();
+    }
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_mutex_release
+//--------------------------------------------------------------------------------------------------
+static void cy_retarget_io_mutex_release(void)
+{
+    CY_ASSERT(cy_retarget_io_mutex_initialized);
+    cy_rslt_t rslt = cy_rtos_set_mutex(&cy_retarget_io_mutex);
+    if (rslt != CY_RSLT_SUCCESS)
+    {
+        abort();
+    }
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_mutex_deinit
+//--------------------------------------------------------------------------------------------------
+static void cy_retarget_io_mutex_deinit(void)
+{
+    CY_ASSERT(cy_retarget_io_mutex_initialized);
+    cy_rslt_t rslt = cy_rtos_deinit_mutex(&cy_retarget_io_mutex);
+    if (rslt != CY_RSLT_SUCCESS)
+    {
+        abort();
+    }
+    cy_retarget_io_mutex_initialized = false;
+}
+
+
+#else // if (defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)) && defined(__GNUC__) &&
+// !defined(__ARMCC_VERSION) && !defined(__clang__)
+#ifdef __ICCARM__
+// Ignore unused functions
+#pragma diag_suppress=Pe177
+#endif
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_mutex_init
+//--------------------------------------------------------------------------------------------------
+static inline cy_rslt_t cy_retarget_io_mutex_init(void)
+{
+    return CY_RSLT_SUCCESS;
+}
+
+
+#if defined(__ARMCC_VERSION) // ARM-MDK
+__attribute__((unused))
+#endif
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_mutex_acquire
+//--------------------------------------------------------------------------------------------------
+static inline void cy_retarget_io_mutex_acquire(void)
+{
+}
+
+
+#if defined(__ARMCC_VERSION) // ARM-MDK
+__attribute__((unused))
+#endif
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_mutex_release
+//--------------------------------------------------------------------------------------------------
+static inline void cy_retarget_io_mutex_release(void)
+{
+}
+
+
+#if defined(__ARMCC_VERSION) // ARM-MDK
+__attribute__((unused))
+#endif
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_mutex_deinit
+//--------------------------------------------------------------------------------------------------
+static inline void cy_retarget_io_mutex_deinit(void)
+{
+}
+
+
+#endif // if (defined(CY_RTOS_AWARE) || defined(COMPONENT_RTOS_AWARE)) && defined(__GNUC__) &&
+// !defined(__ARMCC_VERSION) && !defined(__clang__)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// UART HAL object used by BSP for Debug UART port
+cyhal_uart_t cy_retarget_io_uart_obj;
+
+// Tracks the previous character sent to output stream
+#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+static char cy_retarget_io_stdout_prev_char = 0;
+#endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_getchar
+//--------------------------------------------------------------------------------------------------
+static inline cy_rslt_t cy_retarget_io_getchar(char* c)
+{
+    return cyhal_uart_getc(&cy_retarget_io_uart_obj, (uint8_t*)c, 0);
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_putchar
+//--------------------------------------------------------------------------------------------------
+static inline cy_rslt_t cy_retarget_io_putchar(char c)
+{
+    return cyhal_uart_putc(&cy_retarget_io_uart_obj, (uint8_t)c);
+}
+
+
+#if defined(__ARMCC_VERSION) // ARM-MDK
+//--------------------------------------------------------------------------------------------------
+// fputc
+//--------------------------------------------------------------------------------------------------
+__attribute__((weak)) int fputc(int ch, FILE* f)
+{
+    (void)f;
+    cy_rslt_t rslt = CY_RSLT_SUCCESS;
+    #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+    if (((char)ch == '\n') && (cy_retarget_io_stdout_prev_char != '\r'))
+    {
+        rslt = cy_retarget_io_putchar('\r');
+    }
+    #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+
+    if (CY_RSLT_SUCCESS == rslt)
+    {
+        rslt = cy_retarget_io_putchar(ch);
+    }
+
+    #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+    if (CY_RSLT_SUCCESS == rslt)
+    {
+        cy_retarget_io_stdout_prev_char = (char)ch;
+    }
+    #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+
+    return (CY_RSLT_SUCCESS == rslt) ? ch : EOF;
+}
+
+
+#elif defined (__ICCARM__) // IAR
+    #include <yfuns.h>
+
+//--------------------------------------------------------------------------------------------------
+// __write
+//--------------------------------------------------------------------------------------------------
+__weak size_t __write(int handle, const unsigned char* buffer, size_t size)
+{
+    size_t nChars = 0;
+    // This template only writes to "standard out", for all other file handles it returns failure.
+    if (handle != _LLIO_STDOUT)
+    {
+        return (_LLIO_ERROR);
+    }
+    if (buffer != NULL)
+    {
+        cy_rslt_t rslt = CY_RSLT_SUCCESS;
+        for (; nChars < size; ++nChars)
+        {
+            #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+            if ((*buffer == '\n') && (cy_retarget_io_stdout_prev_char != '\r'))
+            {
+                rslt = cy_retarget_io_putchar('\r');
+            }
+            #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+
+            if (rslt == CY_RSLT_SUCCESS)
+            {
+                rslt = cy_retarget_io_putchar(*buffer);
+            }
+
+            if (rslt != CY_RSLT_SUCCESS)
+            {
+                break;
+            }
+
+            #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+            cy_retarget_io_stdout_prev_char = *buffer;
+            #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+            ++buffer;
+        }
+    }
+    return (nChars);
+}
+
+
+#else // (__GNUC__)  GCC
+// Add an explicit reference to the floating point printf library to allow the usage of floating
+// point conversion specifier.
+//__asm(".global _printf_float");
+//--------------------------------------------------------------------------------------------------
+// _write
+//--------------------------------------------------------------------------------------------------
+__attribute__((weak)) int _write(int fd, const char* ptr, int len)
+{
+    int nChars = 0;
+    (void)fd;
+    if (ptr != NULL)
+    {
+        cy_rslt_t rslt = CY_RSLT_SUCCESS;
+        cy_retarget_io_mutex_acquire();
+        for (; nChars < len; ++nChars)
+        {
+            #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+            if ((*ptr == '\n') && (cy_retarget_io_stdout_prev_char != '\r'))
+            {
+                rslt = cy_retarget_io_putchar('\r');
+            }
+            #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+
+            if (CY_RSLT_SUCCESS == rslt)
+            {
+                rslt = cy_retarget_io_putchar((uint32_t)*ptr);
+            }
+
+            if (CY_RSLT_SUCCESS != rslt)
+            {
+                break;
+            }
+
+            #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+            cy_retarget_io_stdout_prev_char = *ptr;
+            #endif // CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+            ++ptr;
+        }
+        cy_retarget_io_mutex_release();
+    }
+    return (nChars);
+}
+
+
+#endif // if defined(__ARMCC_VERSION)
+
+
+#if defined(__ARMCC_VERSION) // ARM-MDK
+//--------------------------------------------------------------------------------------------------
+// fgetc
+//--------------------------------------------------------------------------------------------------
+__attribute__((weak)) int fgetc(FILE* f)
+{
+    (void)f;
+    char c;
+    cy_rslt_t rslt = cy_retarget_io_getchar(&c);
+    return (CY_RSLT_SUCCESS == rslt) ? c : EOF;
+}
+
+
+#elif defined (__ICCARM__) // IAR
+//--------------------------------------------------------------------------------------------------
+// __read
+//--------------------------------------------------------------------------------------------------
+__weak size_t __read(int handle, unsigned char* buffer, size_t size)
+{
+    // This template only reads from "standard in", for all other file handles it returns failure.
+    if ((handle != _LLIO_STDIN) || (buffer == NULL))
+    {
+        return (_LLIO_ERROR);
+    }
+    else
+    {
+        cy_rslt_t rslt = cy_retarget_io_getchar((char*)buffer);
+        return (CY_RSLT_SUCCESS == rslt) ? 1 : 0;
+    }
+}
+
+
+#else // (__GNUC__)  GCC
+// Add an explicit reference to the floating point scanf library to allow the usage of floating
+// point conversion specifier.
+//__asm(".global _scanf_float");
+//--------------------------------------------------------------------------------------------------
+// _read
+//--------------------------------------------------------------------------------------------------
+__attribute__((weak)) int _read(int fd, char* ptr, int len)
+{
+    (void)fd;
+
+    int nChars = 0;
+    if (ptr != NULL)
+    {
+        cy_rslt_t rslt;
+        do
+        {
+            rslt = cy_retarget_io_getchar(ptr);
+            if (rslt == CY_RSLT_SUCCESS)
+            {
+                ++nChars;
+                if ((*ptr == '\n') || (*ptr == '\r'))
+                {
+                    break;
+                }
+                ptr++;
+            }
+        } while ((rslt == CY_RSLT_SUCCESS) && (nChars < len));
+    }
+
+    return (nChars);
+}
+
+
+#endif // if defined(__ARMCC_VERSION)
+
+#if defined(__ARMCC_VERSION) // ARM-MDK
+// Include _sys_* prototypes provided by ARM Compiler runtime library
+    #include <rt_sys.h>
+
+// Prevent linkage of library functions that use semihosting calls
+__asm(".global __use_no_semihosting\n\t");
+
+// Enable the linker to select an optimized library that does not include code to handle input
+// arguments to main()
+__asm(".global __ARM_use_no_argv\n\t");
+
+//--------------------------------------------------------------------------------------------------
+// _sys_open
+//
+// Open a file: dummy implementation.
+// Everything goes to the same output, no need to translate the file names
+// (__stdin_name/__stdout_name/__stderr_name) to descriptor numbers
+//--------------------------------------------------------------------------------------------------
+FILEHANDLE __attribute__((weak)) _sys_open(const char* name, int openmode)
+{
+    (void)name;
+    (void)openmode;
+    return 1;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// _sys_close
+//
+// Close a file: dummy implementation.
+//--------------------------------------------------------------------------------------------------
+int __attribute__((weak)) _sys_close(FILEHANDLE fh)
+{
+    (void)fh;
+    return 0;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// _sys_write
+//
+// Write to a file: dummy implementation.
+// The low-level function fputc retargets output to use UART TX
+//--------------------------------------------------------------------------------------------------
+int __attribute__((weak)) _sys_write(FILEHANDLE fh, const unsigned char* buf, unsigned len,
+                                     int mode)
+{
+    (void)fh;
+    (void)buf;
+    (void)len;
+    (void)mode;
+    return 0;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// _sys_read
+//
+// Read from a file: dummy implementation.
+// The low-level function fputc retargets input to use UART RX
+//--------------------------------------------------------------------------------------------------
+int __attribute__((weak)) _sys_read(FILEHANDLE fh, unsigned char* buf, unsigned len, int mode)
+{
+    (void)fh;
+    (void)buf;
+    (void)len;
+    (void)mode;
+    return -1;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// _ttywrch
+//
+// Write a character to the output channel: dummy implementation.
+//--------------------------------------------------------------------------------------------------
+void __attribute__((weak)) _ttywrch(int ch)
+{
+    (void)ch;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// _sys_istty
+//
+// Check if the file is connected to a terminal: dummy implementation
+//--------------------------------------------------------------------------------------------------
+int __attribute__((weak)) _sys_istty(FILEHANDLE fh)
+{
+    (void)fh;
+    return 0;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// _sys_seek
+//
+// Move the file position to a given offset: dummy implementation
+//--------------------------------------------------------------------------------------------------
+int __attribute__((weak)) _sys_seek(FILEHANDLE fh, long pos)
+{
+    (void)fh;
+    (void)pos;
+    return -1;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// _sys_flen
+// Return the current length of a file: dummy implementation
+//--------------------------------------------------------------------------------------------------
+long __attribute__((weak)) _sys_flen(FILEHANDLE fh)
+{
+    (void)fh;
+    return 0;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// _sys_exit
+//
+// Terminate the program: dummy implementation
+//--------------------------------------------------------------------------------------------------
+void __attribute__((weak)) _sys_exit(int returncode)
+{
+    (void)returncode;
+    for (;;)
+    {
+        // Halt here forever
+    }
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// _sys_command_string
+//
+// Return a pointer to the command line: dummy implementation
+//--------------------------------------------------------------------------------------------------
+char __attribute__((weak)) *_sys_command_string(char* cmd, int len)
+{
+    (void)cmd;
+    (void)len;
+    return NULL;
+}
+
+
+#endif // ARM-MDK
+
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_init_fc
+//
+// Enables user to provide flow control pins during initialization
+//--------------------------------------------------------------------------------------------------
+cy_rslt_t cy_retarget_io_init_fc(cyhal_gpio_t tx, cyhal_gpio_t rx, cyhal_gpio_t cts,
+                                 cyhal_gpio_t rts, uint32_t baudrate)
+{
+    const cyhal_uart_cfg_t uart_config =
+    {
+        .data_bits          = 8,
+        .stop_bits          = 1,
+        .parity             = CYHAL_UART_PARITY_NONE,
+        .rx_buffer          = NULL,
+        .rx_buffer_size     = 0
+    };
+
+    #if (CYHAL_API_VERSION >= 2)
+    cy_rslt_t result = cyhal_uart_init(&cy_retarget_io_uart_obj, tx, rx, cts, rts, NULL,
+                                       &uart_config);
+    #else // HAL API before version 2
+    cy_rslt_t result = cyhal_uart_init(&cy_retarget_io_uart_obj, tx, rx, NULL, &uart_config);
+    if (result == CY_RSLT_SUCCESS)
+    {
+        result = cyhal_uart_set_flow_control(&cy_retarget_io_uart_obj, cts, rts);
+    }
+    #endif
+
+    if (result == CY_RSLT_SUCCESS)
+    {
+        result = cyhal_uart_set_baud(&cy_retarget_io_uart_obj, baudrate, NULL);
+    }
+
+    if (result == CY_RSLT_SUCCESS)
+    {
+        result = cy_retarget_io_mutex_init();
+    }
+
+    return result;
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_is_tx_active
+//--------------------------------------------------------------------------------------------------
+bool cy_retarget_io_is_tx_active(void)
+{
+    return cyhal_uart_is_tx_active(&cy_retarget_io_uart_obj);
+}
+
+
+//--------------------------------------------------------------------------------------------------
+// cy_retarget_io_deinit
+//--------------------------------------------------------------------------------------------------
+void cy_retarget_io_deinit(void)
+{
+    // Since the largest hardware buffer would be 256 bytes
+    // it takes about 500 ms to transmit the 256 bytes at 9600 baud.
+    // Thus 1000 ms gives roughly 50% padding to this time.
+    int timeout_remaining_ms = 1000;
+    while (timeout_remaining_ms > 0)
+    {
+        if (!cy_retarget_io_is_tx_active())
+        {
+            break;
+        }
+        cyhal_system_delay_ms(1);
+        timeout_remaining_ms--;
+    }
+    CY_ASSERT(timeout_remaining_ms != 0);
+    cyhal_uart_free(&cy_retarget_io_uart_obj);
+    cy_retarget_io_mutex_deinit();
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/libs/retarget-io/cy_retarget_io.h b/boot/cypress/libs/retarget-io/cy_retarget_io.h
new file mode 100644
index 0000000..fe2330d
--- /dev/null
+++ b/boot/cypress/libs/retarget-io/cy_retarget_io.h
@@ -0,0 +1,118 @@
+/***********************************************************************************************//**
+ * \file cy_retarget_io.h
+ *
+ * \brief
+ * Provides APIs for transmitting messages to or from the board via standard
+ * printf/scanf functions. Messages are transmitted over a UART connection which
+ * is generally connected to a host machine. Transmission is done at 115200 baud
+ * using the tx and rx pins provided by the user of this library. The UART
+ * instance is made available via cy_retarget_io_uart_obj in case any changes
+ * to the default configuration are desired.
+ * NOTE: If the application is built using newlib-nano, by default, floating
+ * point format strings (%f) are not supported. To enable this support you must
+ * add '-u _printf_float' to the linker command line.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+/**
+ * \addtogroup group_board_libs Retarget IO
+ * \{
+ */
+
+#pragma once
+
+#include <stdio.h>
+#include "cy_result.h"
+#include "cyhal_hw_types.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/** UART HAL object used by this library */
+extern cyhal_uart_t cy_retarget_io_uart_obj;
+
+/** UART baud rate */
+#define CY_RETARGET_IO_BAUDRATE             (115200)
+
+/**
+ * \brief Initialization function for redirecting low level IO commands to allow
+ * sending messages over a UART interface. This will setup the communication
+ * interface to allow using printf and related functions.
+ *
+ * In an RTOS environment, this function must be called after the RTOS has been
+ * initialized.
+ *
+ * \param tx UART TX pin, if no TX pin use NC
+ * \param rx UART RX pin, if no RX pin use NC
+ * \param baudrate UART baudrate
+ * \returns CY_RSLT_SUCCESS if successfully initialized, else an error about
+ * what went wrong
+ */
+#define cy_retarget_io_init(tx, rx, baudrate) cy_retarget_io_init_fc(tx, rx, NC, NC, baudrate)
+
+#ifdef DOXYGEN
+
+/** Defining this macro enables conversion of line feed (LF) into carriage
+ * return followed by line feed (CR & LF) on the output direction (STDOUT). You
+ * can define this macro through the DEFINES variable in the application
+ * Makefile.
+ */
+#define CY_RETARGET_IO_CONVERT_LF_TO_CRLF
+
+#endif // DOXYGEN
+
+/**
+ * \brief Initialization function for redirecting low level IO commands to allow
+ * sending messages over a UART interface with flow control. This will setup the
+ * communication interface to allow using printf and related functions.
+ *
+ * In an RTOS environment, this function must be called after the RTOS has been
+ * initialized.
+ *
+ * \param tx UART TX pin, if no TX pin use NC
+ * \param rx UART RX pin, if no RX pin use NC
+ * \param cts UART CTS pin, if no CTS pin use NC
+ * \param rts UART RTS pin, if no RTS pin use NC
+ * \param baudrate UART baudrate
+ * \returns CY_RSLT_SUCCESS if successfully initialized, else an error about
+ * what went wrong
+ */
+cy_rslt_t cy_retarget_io_init_fc(cyhal_gpio_t tx, cyhal_gpio_t rx, cyhal_gpio_t cts,
+                                 cyhal_gpio_t rts, uint32_t baudrate);
+
+/**
+ * \brief Checks whether there is data waiting to be written to the serial console.
+ * \returns true if there are pending TX transactions, otherwise false
+ */
+bool cy_retarget_io_is_tx_active(void);
+
+/**
+ * \brief Releases the UART interface allowing it to be used for other purposes.
+ * After calling this, printf and related functions will no longer work.
+ */
+void cy_retarget_io_deinit(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** \} group_board_libs */
diff --git a/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c b/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c
deleted file mode 100644
index 2c02df8..0000000
--- a/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/***************************************************************************//**
-* \file cy_retarget_io.c
-*
-* \brief
-* Provides APIs for retargeting stdio to UART hardware contained on the Cypress
-* kits.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include "cy_retarget_io_pdl.h"
-
-#include "cycfg_peripherals.h"
-
-#include "cy_sysint.h"
-#include "cy_scb_uart.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/* Tracks the previous character sent to output stream */
-#ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-static char cy_retarget_io_stdout_prev_char = '\0';
-#endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
-
-static cy_stc_scb_uart_context_t CYBSP_UART_context;
-
-static uint8_t cy_retarget_io_getchar(void);
-static void cy_retarget_io_putchar(char c);
-
-#if defined(__ARMCC_VERSION) /* ARM-MDK */
-
-int fputc(int ch, FILE *f);
-int fgetc(FILE *f);
-
-#elif defined (__ICCARM__) /* IAR */
-
-size_t __write(int handle, const unsigned char * buffer, size_t size);
-size_t __read(int handle, unsigned char * buffer, size_t size);
-
-#else /* (__GNUC__)  GCC */
-
-int _write(int fd, const char *ptr, int len);
-int _read(int fd, char *ptr, int len);
-
-#endif /* defined(__ARMCC_VERSION) */
-
-
-#if defined(__ARMCC_VERSION) /* ARM-MDK */
-    /***************************************************************************
-    * Function Name: fputc
-    ***************************************************************************/
-    __attribute__((weak)) int fputc(int ch, FILE *f)
-    {
-        (void)f;
-    #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-        if ((char)ch == '\n' && cy_retarget_io_stdout_prev_char != '\r')
-        {
-            cy_retarget_io_putchar('\r');
-        }
-
-        cy_retarget_io_stdout_prev_char = (char)ch;
-    #endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
-        cy_retarget_io_putchar(ch);
-        return (ch);
-    }
-#elif defined (__ICCARM__) /* IAR */
-    #include <yfuns.h>
-
-    /***************************************************************************
-    * Function Name: __write
-    ***************************************************************************/
-    __weak size_t __write(int handle, const unsigned char * buffer, size_t size)
-    {
-        size_t nChars = 0;
-        /* This template only writes to "standard out", for all other file
-        * handles it returns failure. */
-        if (handle != _LLIO_STDOUT)
-        {
-            return (_LLIO_ERROR);
-        }
-        if (buffer != NULL)
-        {
-            for (/* Empty */; nChars < size; ++nChars)
-            {
-            #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-                if (*buffer == '\n' && cy_retarget_io_stdout_prev_char != '\r')
-                {
-                    cy_retarget_io_putchar('\r');
-                }
-
-                cy_retarget_io_stdout_prev_char = *buffer;
-            #endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
-                cy_retarget_io_putchar(*buffer);
-                ++buffer;
-            }
-        }
-        return (nChars);
-    }
-#else /* (__GNUC__)  GCC */
-    /***************************************************************************
-    * Function Name: _write
-    ***************************************************************************/
-    __attribute__((weak)) int _write(int fd, const char *ptr, int len)
-    {
-        int nChars = 0;
-        (void)fd;
-        if (ptr != NULL)
-        {
-            for (/* Empty */; nChars < len; ++nChars)
-            {
-            #ifdef CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-                if (*ptr == '\n' && cy_retarget_io_stdout_prev_char != '\r')
-                {
-                    cy_retarget_io_putchar('\r');
-                }
-
-                cy_retarget_io_stdout_prev_char = *ptr;
-            #endif /* CY_RETARGET_IO_CONVERT_LF_TO_CRLF */
-                cy_retarget_io_putchar(*ptr);
-                ++ptr;
-            }
-        }
-        return (nChars);
-    }
-#endif /* defined(__ARMCC_VERSION) */
-
-
-#if defined(__ARMCC_VERSION) /* ARM-MDK */
-    /***************************************************************************
-    * Function Name: fgetc
-    ***************************************************************************/
-    __attribute__((weak)) int fgetc(FILE *f)
-    {
-        (void)f;
-        return (cy_retarget_io_getchar());
-    }
-#elif defined (__ICCARM__) /* IAR */
-    __weak size_t __read(int handle, unsigned char * buffer, size_t size)
-    {
-        /* This template only reads from "standard in", for all other file
-        handles it returns failure. */
-        if ((handle != _LLIO_STDIN) || (buffer == NULL))
-        {
-            return (_LLIO_ERROR);
-        }
-        else
-        {
-            *buffer = cy_retarget_io_getchar();
-            return (1);
-        }
-    }
-#else /* (__GNUC__)  GCC */
-    __attribute__((weak)) int _read(int fd, char *ptr, int len)
-    {
-        int nChars = 0;
-        (void)fd;
-        if (ptr != NULL)
-        {
-            while (nChars < len)
-            {
-                *ptr = (char)cy_retarget_io_getchar();
-                ++nChars;
-                if((*ptr == '\n') || (*ptr == '\r'))
-                {
-                    break;
-                }
-                ++ptr;
-            }
-        }
-        return (nChars);
-    }
-#endif /* defined(__ARMCC_VERSION) */
-
-static uint8_t cy_retarget_io_getchar(void)
-{
-    uint32_t read_value = Cy_SCB_UART_Get(CYBSP_UART_HW);
-    while (read_value == CY_SCB_UART_RX_NO_DATA)
-    {
-        read_value = Cy_SCB_UART_Get(CYBSP_UART_HW);
-    }
-
-    return (uint8_t)read_value;
-}
-
-static void cy_retarget_io_putchar(char c)
-{
-    uint32_t count = 0U;
-    while (count == 0U)
-    {
-        count = Cy_SCB_UART_Put(CYBSP_UART_HW, (uint8_t)c);
-    }
-}
-
-static cy_rslt_t cy_retarget_io_pdl_setbaud(CySCB_Type *base, uint32_t baudrate)
-{
-    cy_rslt_t result = CY_RSLT_TYPE_ERROR;
-
-    uint8_t oversample_value = 8U;
-    uint8_t frac_bits = 0U;
-    uint32_t divider;
-
-    Cy_SCB_UART_Disable(base, NULL);
-
-    result = (cy_rslt_t) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0);
-
-    divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1UL << frac_bits)) + ((baudrate * oversample_value) / 2U)) / (baudrate * oversample_value) - 1U;
-
-    if (result == CY_RSLT_SUCCESS)
-    {
-        result = (cy_rslt_t) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, divider);
-    }
-    
-    if (result == CY_RSLT_SUCCESS)
-    {
-        result = Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
-    }
-
-    Cy_SCB_UART_Enable(base);
-
-    return result;
-}
-
-cy_rslt_t cy_retarget_io_pdl_init(uint32_t baudrate)
-{
-    cy_rslt_t result = CY_RSLT_TYPE_ERROR;
-
-    result = (cy_rslt_t)Cy_SCB_UART_Init(CYBSP_UART_HW, &CYBSP_UART_config, &CYBSP_UART_context);
-
-    if (result == CY_RSLT_SUCCESS)
-    {
-        result = cy_retarget_io_pdl_setbaud(CYBSP_UART_HW, baudrate);
-    }
-
-    if (result == CY_RSLT_SUCCESS)
-    {
-        Cy_SCB_UART_Enable(CYBSP_UART_HW);
-    }
-
-    return result;
-}
-
-/**
- * @brief Wait while UART completes transfer. Try for tries_count times -
- *        once each 10 millisecons.
- */
-void cy_retarget_io_wait_tx_complete(CySCB_Type *base, uint32_t tries_count)
-{
-    while(tries_count > 0U)
-    {
-        if (!Cy_SCB_UART_IsTxComplete(base)) {
-            Cy_SysLib_DelayCycles(10U * cy_delayFreqKhz);
-            tries_count -= 1U;
-        } else {
-            return;
-        }
-    }
-}
-
-void cy_retarget_io_pdl_deinit(void)
-{
-    Cy_SCB_UART_DeInit(CYBSP_UART_HW);
-}
-
-#if defined(__cplusplus)
-}
-#endif
diff --git a/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.h b/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.h
deleted file mode 100644
index 4ebfdef..0000000
--- a/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/***************************************************************************//**
-* \file cy_retarget_io.h
-*
-* \brief
-* Provides APIs for transmitting messages to or from the board via standard
-* printf/scanf functions. Messages are transmitted over a UART connection which
-* is generally connected to a host machine. Transmission is done at 115200 baud
-* using the tx and rx pins provided by the user of this library. The UART
-* instance is made available via cy_retarget_io_uart_obj in case any changes
-* to the default configuration are desired.
-* NOTE: If the application is built using newlib-nano, by default, floating
-* point format strings (%f) are not supported. To enable this support you must
-* add '-u _printf_float' to the linker command line.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-#ifndef CY_RETARGET_IO_PDL_H
-#define CY_RETARGET_IO_PDL_H
-
-#pragma once
-
-#include <stdio.h>
-#include "cy_result.h"
-#include "cy_pdl.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/** UART baud rate */
-#define CY_RETARGET_IO_BAUDRATE             (115200)
-
-/** Defining this macro enables conversion of line feed (LF) into carriage
- * return followed by line feed (CR & LF) on the output direction (STDOUT). You
- * can define this macro through the DEFINES variable in the application
- * Makefile.
- */
-#define CY_RETARGET_IO_CONVERT_LF_TO_CRLF
-
-cy_rslt_t cy_retarget_io_pdl_init(uint32_t baudrate);
-
-void cy_retarget_io_wait_tx_complete(CySCB_Type *base, uint32_t tries_count);
-
-void cy_retarget_io_pdl_deinit(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* CY_RETARGET_IO_PDL_H */
diff --git a/boot/cypress/libs/watchdog/watchdog.c b/boot/cypress/libs/watchdog/watchdog.c
deleted file mode 100644
index 96200ab..0000000
--- a/boot/cypress/libs/watchdog/watchdog.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/***************************************************************************//**
-* \file cy_wdg.c
-*
-* \brief
-* Provides a high level interface for interacting with the Cypress Watchdog Timer.
-* This interface abstracts out the chip specific details. If any chip specific
-* functionality is necessary, or performance is critical the low level functions
-* can be used directly.
-*
-*
-********************************************************************************
-* \copyright
-* Copyright 2019-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include <stdbool.h>
-#include "watchdog.h"
-#include "cy_sysclk.h"
-#include "cy_wdt.h"
-#include "cy_utils.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#if defined(COMPONENT_PSOC6)
-#define cy_wdg_lock()   Cy_WDT_Lock()
-#define cy_wdg_unlock() Cy_WDT_Unlock()
-#else
-#define cy_wdg_lock()
-#define cy_wdg_unlock()
-#endif
-
-// ((2^16 * 2) + (2^16 - 1)) * .030518 ms
-/** Maximum WDT timeout in milliseconds */
-#define cy_wdg_MAX_TIMEOUT_MS 6000U
-
-/** Maximum number of ignore bits */
-#define cy_wdg_MAX_IGNORE_BITS 12U
-
-typedef struct {
-    uint16_t min_period_ms; // Minimum period in milliseconds that can be represented with this many ignored bits
-    uint16_t round_threshold_ms; // Timeout threshold in milliseconds from which to round up to the minimum period
-} cy_wdg_ignore_bits_data_t;
-
-// ILO Frequency = 32768 Hz
-// ILO Period = 1 / 32768 Hz = .030518 ms
-// WDT Reset Period (timeout_ms) = .030518 ms * (2 * 2^(16 - ignore_bits) + match)
-// ignore_bits range: 0 - 12
-// match range: 0 - (2^(16 - ignore_bits) - 1)
-static const cy_wdg_ignore_bits_data_t cy_wdg_ignore_data[] = {
-    {4001, 3001}, // 0 bits:  min period: 4001ms, max period: 6000ms, round up from 3001+ms
-    {2001, 1500}, // 1 bit:   min period: 2001ms, max period: 3000ms, round up from 1500+ms
-    {1001, 750},  // 2 bits:  min period: 1001ms, max period: 1499ms, round up from 750+ms
-    {501,  375},  // 3 bits:  min period: 501ms,  max period: 749ms,  round up from 375+ms
-    {251,  188},  // 4 bits:  min period: 251ms,  max period: 374ms,  round up from 188+ms
-    {126,  94},   // 5 bits:  min period: 126ms,  max period: 187ms,  round up from 94+ms
-    {63,   47},   // 6 bits:  min period: 63ms,   max period: 93ms,   round up from 47+ms
-    {32,   24},   // 7 bits:  min period: 32ms,   max period: 46ms,   round up from 24+ms
-    {16,   12},   // 8 bits:  min period: 16ms,   max period: 23ms,   round up from 12+ms
-    {8,    6},    // 9 bits:  min period: 8ms,    max period: 11ms,   round up from 6+ms
-    {4,    3},    // 10 bits: min period: 4ms,    max period: 5ms,    round up from 3+ms
-    {2,    2},    // 11 bits: min period: 2ms,    max period: 2ms
-    {1,    1}     // 12 bits: min period: 1ms,    max period: 1ms
-};
-
-static bool cy_wdg_initialized = false;
-static bool cy_wdg_pdl_initialized = false;
-static uint16_t cy_wdg_initial_timeout_ms = 0;
-static uint8_t cy_wdg_initial_ignore_bits = 0;
-
-static __INLINE uint8_t cy_wdg_timeout_to_ignore_bits(uint16_t *timeout_ms)
-{
-    for (uint8_t i = 0; i <= cy_wdg_MAX_IGNORE_BITS; i++) {
-        if (*timeout_ms >= cy_wdg_ignore_data[i].round_threshold_ms) {
-            if (*timeout_ms < cy_wdg_ignore_data[i].min_period_ms) {
-                *timeout_ms = cy_wdg_ignore_data[i].min_period_ms;
-            }
-            return i;
-        }
-    }
-    return cy_wdg_MAX_IGNORE_BITS; // Should never reach this
-}
-
-static __INLINE uint16_t cy_wdg_timeout_to_match(uint16_t timeout_ms, uint16_t ignore_bits)
-{
-    uint32_t timeout = (uint32_t)timeout_ms * CY_SYSCLK_ILO_FREQ / 1000U;
-    return (uint16_t)(timeout - (1UL << (17U - ignore_bits)) + Cy_WDT_GetCount());
-}
-
-/* Start API implementing */
-
-cy_rslt_t cy_wdg_init(uint16_t timeout_ms)
-{
-    if (timeout_ms == 0U || timeout_ms > cy_wdg_MAX_TIMEOUT_MS) {
-        return ~CY_RSLT_SUCCESS;
-    }
-
-    if (cy_wdg_initialized) {
-        return ~CY_RSLT_SUCCESS;
-    }
-
-    cy_wdg_initialized = true;
-
-    if (!cy_wdg_pdl_initialized) {
-        Cy_WDT_Enable();
-        Cy_WDT_MaskInterrupt();
-        cy_wdg_pdl_initialized = true;
-    }
-
-    cy_wdg_stop();
-
-    cy_wdg_initial_timeout_ms = timeout_ms;
-    uint8_t ignore_bits = cy_wdg_timeout_to_ignore_bits(&timeout_ms);
-    cy_wdg_initial_ignore_bits = ignore_bits;
-
-    Cy_WDT_SetIgnoreBits(ignore_bits);
-
-    Cy_WDT_SetMatch(cy_wdg_timeout_to_match(timeout_ms, ignore_bits));
-
-    cy_wdg_start();
-
-    return CY_RSLT_SUCCESS;
-}
-
-void cy_wdg_free(void)
-{
-    cy_wdg_stop();
-
-    cy_wdg_initialized = false;
-}
-
-void cy_wdg_kick(void)
-{
-    /* Clear to prevent reset from WDT */
-    Cy_WDT_ClearWatchdog();
-
-    cy_wdg_unlock();
-    Cy_WDT_SetMatch(cy_wdg_timeout_to_match(cy_wdg_initial_timeout_ms, cy_wdg_initial_ignore_bits));
-    cy_wdg_lock();
-}
-
-void cy_wdg_start(void)
-{
-    cy_wdg_unlock();
-    Cy_WDT_Enable();
-    cy_wdg_lock();
-}
-
-void cy_wdg_stop(void)
-{
-    cy_wdg_unlock();
-    Cy_WDT_Disable();
-}
-
-uint32_t cy_wdg_get_timeout_ms(void)
-{
-    return cy_wdg_initial_timeout_ms;
-}
-
-uint32_t cy_wdg_get_max_timeout_ms(void)
-{
-    return cy_wdg_MAX_TIMEOUT_MS;
-}
-
-#if defined(__cplusplus)
-}
-#endif
diff --git a/boot/cypress/libs/watchdog/watchdog.h b/boot/cypress/libs/watchdog/watchdog.h
deleted file mode 100644
index 494326a..0000000
--- a/boot/cypress/libs/watchdog/watchdog.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef WATCHDOG_H
-#define WATCHDOG_H
-/***************************************************************************//**
-* \file cy_wdg.h
-*
-* \brief
-* Provides a high level interface for interacting with the Watchdog Timer.
-* This interface abstracts out the chip specific details. If any chip specific
-* functionality is necessary, or performance is critical the low level functions
-* can be used directly.
-*
-********************************************************************************
-* \copyright
-* Copyright 2019-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#pragma once
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "cy_result.h"
-
-/** Initialize and start the WDT
-*
-* The specified timeout must be at least 1ms and at most the WDT's maximum timeout (see cy_wdg_get_max_timeout_ms()).
-* @param[inout] timeout_ms The time in milliseconds before the WDT times out (1ms - max) (see cy_wdg_get_max_timeout_ms())
-* @return The status of the init request
-*
-* Returns CY_RSLT_SUCCESS if the operation was successfull.
-*/
-cy_rslt_t cy_wdg_init(uint16_t timeout_ms);
-
-/** Free the WDT
-*
-* Powers down the WDT.
-* After calling this function no other WDT functions should be called except
-* cy_wdg_init().
-*/
-
-void cy_wdg_free(void);
-
-/** Resets the WDT
-*
-* This function should be called periodically to prevent the WDT from timing out and resetting the device.
-*/
-void cy_wdg_kick(void);
-
-/** Start (enable) the WDT
-*
-* @return The status of the start request
-*/
-void cy_wdg_start(void);
-
-/** Stop (disable) the WDT
-*
-* @return The status of the stop request
-*/
-void cy_wdg_stop(void);
-
-/** Get the WDT timeout
-*
-* Gets the time in milliseconds before the WDT times out.
-* @return The time in milliseconds before the WDT times out
-*/
-uint32_t cy_wdg_get_timeout_ms(void);
-
-/** Gets the maximum WDT timeout in milliseconds
-*
-* @return The maximum timeout for the WDT
-*/
-uint32_t cy_wdg_get_max_timeout_ms(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-#endif /* WATCHDOG_H */
diff --git a/boot/cypress/manifests/custom-ce-manifest.xml b/boot/cypress/manifests/custom-ce-manifest.xml
new file mode 100644
index 0000000..576d5c4
--- /dev/null
+++ b/boot/cypress/manifests/custom-ce-manifest.xml
@@ -0,0 +1,16 @@
+<apps version="2.0">
+    <app keywords="psoc6,mcuboot,bootloader,mtb-flow, cyw20829" req_capabilities_v2="[cy8cproto_062_4343w, cy8cproto_062s3_4343w, cyw20829, psvp-cyw20829]">
+        <name>Bootloader Solution</name>
+        <id>mtb-example-bootloader-solution</id>
+        <category>Bootloaders</category>
+        <uri>https://gitlab.intra.infineon.com/wpp/ce/mtb/mtb-example-bootloader-solution/</uri>
+        <description><![CDATA[This code example demonstrates building a simple bootloader application.]]></description>
+        <req_capabilities></req_capabilities>
+        <versions>
+            <version flow_version="2.0" tools_min_version="3.0.0">
+                <num>Latest 1.X</num>
+            <commit>develop</commit>
+            </version>
+        </versions>
+    </app>
+</apps>
diff --git a/boot/cypress/manifests/mtb-super-manifest-fv2-test-ce-mcuboot.xml b/boot/cypress/manifests/mtb-super-manifest-fv2-test-ce-mcuboot.xml
new file mode 100644
index 0000000..9e1eaa3
--- /dev/null
+++ b/boot/cypress/manifests/mtb-super-manifest-fv2-test-ce-mcuboot.xml
@@ -0,0 +1,56 @@
+<super-manifest version="2.0">
+  <board-manifest-list>
+    <board-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-bsp-manifest/raw/v2.X/mtb-bsp-manifest.xml</uri>
+    </board-manifest>
+    <board-manifest dependency-url="https://gitlab.intra.infineon.com/repo-staging/mtb-bsp-manifest/raw/v2.X/mtb-bsp-dependencies-manifest.xml">
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-bsp-manifest/raw/v2.X/mtb-bsp-manifest-fv2.xml</uri>
+    </board-manifest>
+    <board-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-bt-bsp-manifest/raw/v2.X/mtb-bt-bsp-manifest.xml</uri>
+    </board-manifest>
+    <board-manifest dependency-url="https://gitlab.intra.infineon.com/repo-staging/mtb-bt-bsp-manifest/raw/v2.X/mtb-bt-bsp-dependencies-manifest.xml">
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-bt-bsp-manifest/raw/v2.X/mtb-bt-bsp-manifest-fv2.xml</uri>
+    </board-manifest>
+  </board-manifest-list>
+  <app-manifest-list>
+    <app-manifest>
+      <uri>custom-ce-manifest.xml</uri>
+    </app-manifest>
+    <app-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-ce-manifest/raw/v2.X/mtb-ce-manifest.xml</uri>
+    </app-manifest>
+    <app-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-ce-manifest/raw/v2.X/mtb-ce-manifest-fv2.xml</uri>
+    </app-manifest>
+    <app-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-bt-app-manifest/raw/v2.X/mtb-bt-app-manifest.xml</uri>
+    </app-manifest>
+    <app-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-bt-app-manifest/raw/v2.X/mtb-bt-app-manifest-fv2.xml</uri>
+    </app-manifest>
+    <app-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/cce-app-manifest/raw/v2.X/cce-app-manifest-fv2.xml</uri>
+    </app-manifest>
+  </app-manifest-list>
+  <middleware-manifest-list>
+    <middleware-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-mw-manifest/raw/v2.X/mtb-mw-manifest.xml</uri>
+    </middleware-manifest>
+    <middleware-manifest dependency-url="https://gitlab.intra.infineon.com/repo-staging/mtb-mw-manifest/raw/v2.X/mtb-mw-dependencies-manifest.xml">
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-mw-manifest/raw/v2.X/mtb-mw-manifest-fv2.xml</uri>
+    </middleware-manifest>
+    <middleware-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-bt-mw-manifest/raw/v2.X/mtb-bt-mw-manifest.xml</uri>
+    </middleware-manifest>
+    <middleware-manifest dependency-url="https://gitlab.intra.infineon.com/repo-staging/mtb-bt-mw-manifest/raw/v2.X/mtb-bt-mw-dependencies-manifest.xml">
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-bt-mw-manifest/raw/v2.X/mtb-bt-mw-manifest-fv2.xml</uri>
+    </middleware-manifest>
+    <middleware-manifest>
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-wifi-mw-manifest/raw/v2.X/mtb-wifi-mw-manifest.xml</uri>
+    </middleware-manifest>
+    <middleware-manifest dependency-url="https://gitlab.intra.infineon.com/repo-staging/mtb-wifi-mw-manifest/raw/v2.X/mtb-wifi-mw-dependencies-manifest.xml">
+      <uri>https://gitlab.intra.infineon.com/repo-staging/mtb-wifi-mw-manifest/raw/v2.X/mtb-wifi-mw-manifest-fv2.xml</uri>
+    </middleware-manifest>
+  </middleware-manifest-list>
+</super-manifest>
\ No newline at end of file
diff --git a/boot/cypress/platforms.mk b/boot/cypress/platforms.mk
index 8122d94..56421c2 100644
--- a/boot/cypress/platforms.mk
+++ b/boot/cypress/platforms.mk
@@ -27,7 +27,8 @@
 
 # supported platforms
 PSOC_06X := PSOC_061_2M PSOC_061_1M PSOC_061_512K PSOC_062_2M PSOC_062_1M PSOC_062_512K PSOC_063_1M
-PLATFORMS := $(PSOC_06X) CYW20829
+XMC7000 := XMC7200 XMC7100
+PLATFORMS := $(PSOC_06X) CYW20829 $(XMC7000)
 
 ifneq ($(filter $(PLATFORM), $(PLATFORMS)),)
 else
@@ -38,6 +39,8 @@
 FAMILY := PSOC6
 else ifeq ($(PLATFORM), CYW20829)
 FAMILY := CYW20829
+else ifeq ($(PLATFORM), $(filter $(PLATFORM), $(XMC7000)))
+FAMILY := XMC7000
 endif
 
 # include family related makefile into build
diff --git a/boot/cypress/platforms/BSP/CYW20829/cyw20829_psvp.h b/boot/cypress/platforms/BSP/CYW20829/cyw20829_psvp.h
new file mode 100644
index 0000000..65868c0
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/cyw20829_psvp.h
@@ -0,0 +1,916 @@
+/***************************************************************************//**
+* \file cyw20829_psvp.h
+*
+* \brief
+* CYW20829_PSVP device header
+*
+********************************************************************************
+* \copyright
+* (c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _CYW20829_PSVP_H_
+#define _CYW20829_PSVP_H_
+
+/**
+* \addtogroup group_device CYW20829_PSVP
+* \{
+*/
+
+/**
+* \addtogroup Configuration_of_CMSIS
+* \{
+*/
+
+/*******************************************************************************
+*                         Interrupt Number Definition
+*******************************************************************************/
+
+typedef enum {
+  /* ARM Cortex-M33 Core Interrupt Numbers */
+  Reset_IRQn                        = -15,      /*!< -15 Reset Vector, invoked on Power up and warm reset */
+  NonMaskableInt_IRQn               = -14,      /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
+  HardFault_IRQn                    = -13,      /*!< -13 Hard Fault, all classes of Fault */
+  MemoryManagement_IRQn             = -12,      /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
+  BusFault_IRQn                     = -11,      /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
+  UsageFault_IRQn                   = -10,      /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
+  SecureFault_IRQn                  =  -9,      /*!<  -9 Secure Fault Interrupt */
+  SVCall_IRQn                       =  -5,      /*!<  -5 System Service Call via SVC instruction */
+  DebugMonitor_IRQn                 =  -4,      /*!<  -4 Debug Monitor */
+  PendSV_IRQn                       =  -2,      /*!<  -2 Pendable request for system service */
+  SysTick_IRQn                      =  -1,      /*!<  -1 System Tick Timer */
+  /* CYW20829_PSVP Peripheral Interrupt Numbers */
+  ioss_interrupts_gpio_0_IRQn       =   0,      /*!<   0 [DeepSleep] GPIO Port Interrupt #0 */
+  ioss_interrupts_gpio_1_IRQn       =   1,      /*!<   1 [DeepSleep] GPIO Port Interrupt #1 */
+  ioss_interrupts_gpio_2_IRQn       =   2,      /*!<   2 [DeepSleep] GPIO Port Interrupt #2 */
+  ioss_interrupts_gpio_3_IRQn       =   3,      /*!<   3 [DeepSleep] GPIO Port Interrupt #3 */
+  ioss_interrupts_gpio_4_IRQn       =   4,      /*!<   4 [DeepSleep] GPIO Port Interrupt #4 */
+  ioss_interrupts_gpio_5_IRQn       =   5,      /*!<   5 [DeepSleep] GPIO Port Interrupt #5 */
+  ioss_interrupt_vdd_IRQn           =   6,      /*!<   6 [DeepSleep] GPIO Supply Detect Interrupt */
+  ioss_interrupt_gpio_IRQn          =   7,      /*!<   7 [DeepSleep] GPIO All Ports */
+  scb_0_interrupt_IRQn              =   8,      /*!<   8 [DeepSleep] Serial Communication Block #0 (DeepSleep capable) */
+  srss_interrupt_mcwdt_0_IRQn       =   9,      /*!<   9 [DeepSleep] Multi Counter Watchdog Timer interrupt */
+  srss_interrupt_backup_IRQn        =  10,      /*!<  10 [DeepSleep] Backup domain interrupt */
+  srss_interrupt_IRQn               =  11,      /*!<  11 [DeepSleep] Other combined Interrupts for srss (LVD and CLKCAL, CLKCAL only supported in Active mode) */
+  cpuss_interrupts_ipc_dpslp_0_IRQn =  12,      /*!<  12 [DeepSleep] cpuss Inter Process Communication Interrupt #0 */
+  cpuss_interrupts_ipc_dpslp_1_IRQn =  13,      /*!<  13 [DeepSleep] cpuss Inter Process Communication Interrupt #1 */
+  keyscan_interrupt_IRQn            =  14,      /*!<  14 [DeepSleep] mxkeyscan interrupt for keyscan edge or fifo thresh to WIC in M33 */
+  srss_interrupt_wdt_IRQn           =  15,      /*!<  15 [DeepSleep] Interrupt from WDT */
+  btss_interrupt_btss_ipc_IRQn      =  16,      /*!<  16 [DeepSleep] interrupt from BTSS IPC */
+  scb_1_interrupt_IRQn              =  17,      /*!<  17 [Active] Serial Communication Block #1 */
+  scb_2_interrupt_IRQn              =  18,      /*!<  18 [Active] Serial Communication Block #2 */
+  cpuss_interrupts_dw0_0_IRQn       =  19,      /*!<  19 [Active] cpuss DataWire #0, Channel #0 */
+  cpuss_interrupts_dw0_1_IRQn       =  20,      /*!<  20 [Active] cpuss DataWire #0, Channel #1 */
+  cpuss_interrupts_dw0_2_IRQn       =  21,      /*!<  21 [Active] cpuss DataWire #0, Channel #2 */
+  cpuss_interrupts_dw0_3_IRQn       =  22,      /*!<  22 [Active] cpuss DataWire #0, Channel #3 */
+  cpuss_interrupts_dw0_4_IRQn       =  23,      /*!<  23 [Active] cpuss DataWire #0, Channel #4 */
+  cpuss_interrupts_dw0_5_IRQn       =  24,      /*!<  24 [Active] cpuss DataWire #0, Channel #5 */
+  cpuss_interrupts_dw0_6_IRQn       =  25,      /*!<  25 [Active] cpuss DataWire #0, Channel #6 */
+  cpuss_interrupts_dw0_7_IRQn       =  26,      /*!<  26 [Active] cpuss DataWire #0, Channel #7 */
+  cpuss_interrupts_dw0_8_IRQn       =  27,      /*!<  27 [Active] cpuss DataWire #0, Channel #8 */
+  cpuss_interrupts_dw0_9_IRQn       =  28,      /*!<  28 [Active] cpuss DataWire #0, Channel #9 */
+  cpuss_interrupts_dw0_10_IRQn      =  29,      /*!<  29 [Active] cpuss DataWire #0, Channel #10 */
+  cpuss_interrupts_dw0_11_IRQn      =  30,      /*!<  30 [Active] cpuss DataWire #0, Channel #11 */
+  cpuss_interrupts_dw0_12_IRQn      =  31,      /*!<  31 [Active] cpuss DataWire #0, Channel #12 */
+  cpuss_interrupts_dw0_13_IRQn      =  32,      /*!<  32 [Active] cpuss DataWire #0, Channel #13 */
+  cpuss_interrupts_dw0_14_IRQn      =  33,      /*!<  33 [Active] cpuss DataWire #0, Channel #14 */
+  cpuss_interrupts_dw0_15_IRQn      =  34,      /*!<  34 [Active] cpuss DataWire #0, Channel #15 */
+  cpuss_interrupt_mpc_promc_IRQn    =  35,      /*!<  35 [Active] PROMC Int */
+  cpuss_interrupt_ppu_sramc0_IRQn   =  36,      /*!<  36 [Active] PPU SRAM0 */
+  cpuss_interrupt_mpc_sramc0_IRQn   =  37,      /*!<  37 [Active] MPC SRAM0 */
+  cpuss_interrupt_cm33_0_fp_IRQn    =  38,      /*!<  38 [Active] CM33 0 Floating Point Interrupt */
+  cpuss_interrupts_cm33_0_cti_0_IRQn =  39,     /*!<  39 [Active] CM33-0 CTI interrupt outputs */
+  cpuss_interrupts_cm33_0_cti_1_IRQn =  40,     /*!<  40 [Active] CM33-1 CTI interrupt outputs */
+  cpuss_interrupt_exp_br_ahb_error_IRQn =  41,  /*!<  41 [Active] EXPANSION BRIDGE AHB Error interrupt */
+  tcpwm_0_interrupts_0_IRQn         =  42,      /*!<  42 [Active] TCPWM #0, Counter #0 */
+  tcpwm_0_interrupts_1_IRQn         =  43,      /*!<  43 [Active] TCPWM #0, Counter #1 */
+  tcpwm_0_interrupts_256_IRQn       =  44,      /*!<  44 [Active] TCPWM #0, Counter #256 */
+  tcpwm_0_interrupts_257_IRQn       =  45,      /*!<  45 [Active] TCPWM #0, Counter #257 */
+  tcpwm_0_interrupts_258_IRQn       =  46,      /*!<  46 [Active] TCPWM #0, Counter #258 */
+  tcpwm_0_interrupts_259_IRQn       =  47,      /*!<  47 [Active] TCPWM #0, Counter #259 */
+  tcpwm_0_interrupts_260_IRQn       =  48,      /*!<  48 [Active] TCPWM #0, Counter #260 */
+  tcpwm_0_interrupts_261_IRQn       =  49,      /*!<  49 [Active] TCPWM #0, Counter #261 */
+  tcpwm_0_interrupts_262_IRQn       =  50,      /*!<  50 [Active] TCPWM #0, Counter #262 */
+  smif_interrupt_normal_IRQn        =  51,      /*!<  51 [Active] Serial Memory Interface interrupt */
+  smif_interrupt_mpc_IRQn           =  52,      /*!<  52 [Active] Serial Memory Interface interrupt */
+  tdm_0_interrupts_rx_0_IRQn        =  53,      /*!<  53 [Active] TDM0 Audio interrupt RX */
+  tdm_0_interrupts_tx_0_IRQn        =  54,      /*!<  54 [Active] TDM0 Audio interrupt TX */
+  pdm_0_interrupts_0_IRQn           =  55,      /*!<  55 [Active] PDM0/PCM0 Audio interrupt */
+  pdm_0_interrupts_1_IRQn           =  56,      /*!<  56 [Active] PDM0/PCM0 Audio interrupt */
+  srss_interrupt_main_ppu_IRQn      =  57,      /*!<  57 [Active] SRSS Main PPU Interrupt */
+  peri_interrupt_ppc_IRQn           =  58,      /*!<  58 [Active] PERI PPC Interrupt */
+  peri_interrupt_ahb_error_IRQn     =  59,      /*!<  59 [Active] PERI AHB Interrupt */
+  lin_0_interrupts_0_IRQn           =  60,      /*!<  60 [Active] LIN Interrupt, Channel #0 */
+  lin_0_interrupts_1_IRQn           =  61,      /*!<  61 [Active] LIN Interrupt, Channel #1 */
+  crypto_interrupt_error_IRQn       =  62,      /*!<  62 [Active] Crypto Interrupt */
+  cpuss_interrupt_ppu_cpuss_IRQn    =  63,      /*!<  63 [Active] CPUSS PPU Interrupt */
+  canfd_0_interrupts0_0_IRQn        =  64,      /*!<  64 [Active] CAN #0, Interrupt #0, Channel #0 */
+  canfd_0_interrupts1_0_IRQn        =  65,      /*!<  65 [Active] CAN #0, Interrupt #1, Channel #0 */
+  canfd_0_interrupt0_IRQn           =  66,      /*!<  66 [Active] Can #0, Consolidated interrupt #0 */
+  adcmic_interrupt_adcmic_IRQn      =  67,      /*!<  67 [Active] ADCMIC interrupt */
+  btss_interrupt_btss_exception_IRQn =  68,     /*!<  68 [Active] interrupt indicating BTSS has encountered exception */
+  unconnected_IRQn                  = 240       /*!< 240 Unconnected */
+} IRQn_Type;
+
+
+/*******************************************************************************
+*                    Processor and Core Peripheral Section
+*******************************************************************************/
+
+/* Configuration of the ARM Cortex-M33 Processor and Core Peripherals */
+#define __CM33_REV                      0x0001U /*!< CM33 Core Revision */
+#define __NVIC_PRIO_BITS                3       /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig          0       /*!< Set to 1 if different SysTick Config is used */
+#define __VTOR_PRESENT                  1       /*!< Set to 1 if CPU supports Vector Table Offset Register */
+#define __MPU_PRESENT                   1       /*!< MPU present or not */
+#define __FPU_PRESENT                   1       /*!< FPU present or not */
+#define __CM0P_PRESENT                  0       /*!< CM0P present or not */
+#define __DTCM_PRESENT                  0       /*!< DTCM present or not */
+#define __ICACHE_PRESENT                0       /*!< ICACHE present or not */
+#define __DCACHE_PRESENT                0       /*!< DCACHE present or not */
+
+/** \} Configuration_of_CMSIS */
+
+#include "core_cm33.h"                          /*!< ARM Cortex-M33 processor and core peripherals */
+
+
+/* Memory Blocks */
+#define CY_ROM_BASE                     0x00000000UL
+#define CY_ROM_SIZE                     0x00010000UL
+#define CY_ROM_SECURE_OFFSET            0x10000000UL
+#define CY_ROM_REMAP_OFFSET             0x00000000UL
+#define CY_ROM_REMAP_SECURE_OFFSET      0x10000000UL
+#define CY_CAN0MRAM_BASE                0x40450000UL
+#define CY_CAN0MRAM_SIZE                0x00010000UL
+#define CY_EFUSE_BASE                   0x40810800UL
+#define CY_EFUSE_SIZE                   0x00000200UL
+#define CY_XIP_BASE                     0x60000000UL
+#define CY_XIP_SIZE                     0x08000000UL
+#define CY_XIP_SECURE_OFFSET            0x70000000UL
+#define CY_XIP_REMAP_OFFSET             0x08000000UL
+#define CY_XIP_REMAP_SECURE_OFFSET      0x18000000UL
+#define CY_SRAM0_BASE                   0x20000000UL
+#define CY_SRAM0_SIZE                   0x00020000UL
+#define CY_SRAM0_SECURE_OFFSET          0x30000000UL
+#define CY_SRAM0_REMAP_OFFSET           0x04000000UL
+#define CY_SRAM0_REMAP_SECURE_OFFSET    0x14000000UL
+
+#include "system_cat1b.h"                       /*!< Category 1B System */
+
+/* IP List */
+#define CY_IP_MXS40ADCMIC               1u
+#define CY_IP_MXS40ADCMIC_INSTANCES     1u
+#define CY_IP_MXS40ADCMIC_VERSION       1u
+#define CY_IP_MXS40BLE52SS              1u
+#define CY_IP_MXS40BLE52SS_INSTANCES    1u
+#define CY_IP_MXS40BLE52SS_VERSION      1u
+#define CY_IP_MXTTCANFD                 1u
+#define CY_IP_MXTTCANFD_INSTANCES       1u
+#define CY_IP_MXTTCANFD_VERSION         1u
+#define CY_IP_M33SYSCPUSS               1u
+#define CY_IP_M33SYSCPUSS_INSTANCES     1u
+#define CY_IP_M33SYSCPUSS_VERSION       1u
+#define CY_IP_MXCRYPTOLITE              1u
+#define CY_IP_MXCRYPTOLITE_INSTANCES    1u
+#define CY_IP_MXCRYPTOLITE_VERSION      1u
+#define CY_IP_MXDFT                     1u
+#define CY_IP_MXDFT_INSTANCES           1u
+#define CY_IP_MXDFT_VERSION             2u
+#define CY_IP_MXEFUSE                   1u
+#define CY_IP_MXEFUSE_INSTANCES         1u
+#define CY_IP_MXEFUSE_VERSION           3u
+#define CY_IP_MXS40SIOSS                1u
+#define CY_IP_MXS40SIOSS_INSTANCES      1u
+#define CY_IP_MXS40SIOSS_VERSION        1u
+#define CY_IP_MXKEYSCAN                 1u
+#define CY_IP_MXKEYSCAN_INSTANCES       1u
+#define CY_IP_MXKEYSCAN_VERSION         1u
+#define CY_IP_MXLIN                     1u
+#define CY_IP_MXLIN_INSTANCES           1u
+#define CY_IP_MXLIN_VERSION             1u
+#define CY_IP_MXCM33                    1u
+#define CY_IP_MXCM33_INSTANCES          1u
+#define CY_IP_MXCM33_VERSION            1u
+#define CY_IP_MXDW                      1u
+#define CY_IP_MXDW_INSTANCES            1u
+#define CY_IP_MXDW_VERSION              1u
+#define CY_IP_MXIPC                     1u
+#define CY_IP_MXIPC_INSTANCES           1u
+#define CY_IP_MXIPC_VERSION             1u
+#define CY_IP_MXPROMC                   1u
+#define CY_IP_MXPROMC_INSTANCES         1u
+#define CY_IP_MXPROMC_VERSION           1u
+#define CY_IP_MXSRAMC                   1u
+#define CY_IP_MXSRAMC_INSTANCES         1u
+#define CY_IP_MXSRAMC_VERSION           1u
+#define CY_IP_MXPDM                     1u
+#define CY_IP_MXPDM_INSTANCES           1u
+#define CY_IP_MXPDM_VERSION             1u
+#define CY_IP_MXSPERI                   1u
+#define CY_IP_MXSPERI_INSTANCES         1u
+#define CY_IP_MXSPERI_VERSION           1u
+#define CY_IP_MXSPERI_TR                1u
+#define CY_IP_MXSPERI_TR_INSTANCES      1u
+#define CY_IP_MXSPERI_TR_VERSION        1u
+#define CY_IP_MXSCB                     1u
+#define CY_IP_MXSCB_INSTANCES           3u
+#define CY_IP_MXSCB_VERSION             4u
+#define CY_IP_MXSMIF                    1u
+#define CY_IP_MXSMIF_INSTANCES          1u
+#define CY_IP_MXSMIF_VERSION            3u
+#define CY_IP_MXS40SSRSS                1u
+#define CY_IP_MXS40SSRSS_INSTANCES      1u
+#define CY_IP_MXS40SSRSS_VERSION        1u
+#define CY_IP_MXTCPWM                   1u
+#define CY_IP_MXTCPWM_INSTANCES         1u
+#define CY_IP_MXTCPWM_VERSION           2u
+#define CY_IP_MXTDM                     1u
+#define CY_IP_MXTDM_INSTANCES           1u
+#define CY_IP_MXTDM_VERSION             1u
+
+#include "cyw20829_config.h"
+#include "gpio_cyw20829_56_qfn.h"
+
+#define CY_DEVICE_CYW20829
+#define CY_SILICON_ID                   0xFFFFFFFFUL
+#define CY_HF_CLK_MAX_FREQ              150000000UL
+
+
+/*******************************************************************************
+*                                     PERI
+*******************************************************************************/
+
+#define PERI_BASE                               0x40000000UL
+#define PERI                                    ((PERI_Type*) PERI_BASE)                                          /* 0x40000000 */
+#define PERI_GR0                                ((PERI_GR_Type*) &PERI->GR[0])                                    /* 0x40004000 */
+#define PERI_GR1                                ((PERI_GR_Type*) &PERI->GR[1])                                    /* 0x40004040 */
+#define PERI_GR2                                ((PERI_GR_Type*) &PERI->GR[2])                                    /* 0x40004080 */
+#define PERI_GR3                                ((PERI_GR_Type*) &PERI->GR[3])                                    /* 0x400040C0 */
+#define PERI_TR_GR0                             ((PERI_TR_GR_Type*) &PERI->TR_GR[0])                              /* 0x40008000 */
+#define PERI_TR_GR1                             ((PERI_TR_GR_Type*) &PERI->TR_GR[1])                              /* 0x40008400 */
+#define PERI_TR_GR2                             ((PERI_TR_GR_Type*) &PERI->TR_GR[2])                              /* 0x40008800 */
+#define PERI_TR_GR3                             ((PERI_TR_GR_Type*) &PERI->TR_GR[3])                              /* 0x40008C00 */
+#define PERI_TR_GR4                             ((PERI_TR_GR_Type*) &PERI->TR_GR[4])                              /* 0x40009000 */
+#define PERI_TR_GR5                             ((PERI_TR_GR_Type*) &PERI->TR_GR[5])                              /* 0x40009400 */
+#define PERI_TR_GR6                             ((PERI_TR_GR_Type*) &PERI->TR_GR[6])                              /* 0x40009800 */
+#define PERI_TR_GR7                             ((PERI_TR_GR_Type*) &PERI->TR_GR[7])                              /* 0x40009C00 */
+#define PERI_TR_GR8                             ((PERI_TR_GR_Type*) &PERI->TR_GR[8])                              /* 0x4000A000 */
+#define PERI_TR_GR9                             ((PERI_TR_GR_Type*) &PERI->TR_GR[9])                              /* 0x4000A400 */
+#define PERI_TR_1TO1_GR0                        ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0])                    /* 0x4000C000 */
+#define PERI_TR_1TO1_GR1                        ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1])                    /* 0x4000C400 */
+#define PERI_TR_1TO1_GR2                        ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2])                    /* 0x4000C800 */
+#define PERI_TR_1TO1_GR3                        ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3])                    /* 0x4000CC00 */
+#define PERI_TR_1TO1_GR4                        ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4])                    /* 0x4000D000 */
+
+/*******************************************************************************
+*                                     PPC
+*******************************************************************************/
+
+#define PPC_BASE                                0x40020000UL
+#define PPC                                     ((PPC_Type*) PPC_BASE)                                            /* 0x40020000 */
+#define PPC_R_ADDR0                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[0])                              /* 0x40025000 */
+#define PPC_R_ADDR1                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[1])                              /* 0x40025004 */
+#define PPC_R_ADDR2                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[2])                              /* 0x40025008 */
+#define PPC_R_ADDR3                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[3])                              /* 0x4002500C */
+#define PPC_R_ADDR4                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[4])                              /* 0x40025010 */
+#define PPC_R_ADDR5                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[5])                              /* 0x40025014 */
+#define PPC_R_ADDR6                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[6])                              /* 0x40025018 */
+#define PPC_R_ADDR7                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[7])                              /* 0x4002501C */
+#define PPC_R_ADDR8                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[8])                              /* 0x40025020 */
+#define PPC_R_ADDR9                             ((PPC_R_ADDR_Type*) &PPC->R_ADDR[9])                              /* 0x40025024 */
+#define PPC_R_ADDR10                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[10])                             /* 0x40025028 */
+#define PPC_R_ADDR11                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[11])                             /* 0x4002502C */
+#define PPC_R_ADDR12                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[12])                             /* 0x40025030 */
+#define PPC_R_ADDR13                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[13])                             /* 0x40025034 */
+#define PPC_R_ADDR14                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[14])                             /* 0x40025038 */
+#define PPC_R_ADDR15                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[15])                             /* 0x4002503C */
+#define PPC_R_ADDR16                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[16])                             /* 0x40025040 */
+#define PPC_R_ADDR17                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[17])                             /* 0x40025044 */
+#define PPC_R_ADDR18                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[18])                             /* 0x40025048 */
+#define PPC_R_ADDR19                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[19])                             /* 0x4002504C */
+#define PPC_R_ADDR20                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[20])                             /* 0x40025050 */
+#define PPC_R_ADDR21                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[21])                             /* 0x40025054 */
+#define PPC_R_ADDR22                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[22])                             /* 0x40025058 */
+#define PPC_R_ADDR23                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[23])                             /* 0x4002505C */
+#define PPC_R_ADDR24                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[24])                             /* 0x40025060 */
+#define PPC_R_ADDR25                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[25])                             /* 0x40025064 */
+#define PPC_R_ADDR26                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[26])                             /* 0x40025068 */
+#define PPC_R_ADDR27                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[27])                             /* 0x4002506C */
+#define PPC_R_ADDR28                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[28])                             /* 0x40025070 */
+#define PPC_R_ADDR29                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[29])                             /* 0x40025074 */
+#define PPC_R_ADDR30                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[30])                             /* 0x40025078 */
+#define PPC_R_ADDR31                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[31])                             /* 0x4002507C */
+#define PPC_R_ADDR32                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[32])                             /* 0x40025080 */
+#define PPC_R_ADDR33                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[33])                             /* 0x40025084 */
+#define PPC_R_ADDR34                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[34])                             /* 0x40025088 */
+#define PPC_R_ADDR35                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[35])                             /* 0x4002508C */
+#define PPC_R_ADDR36                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[36])                             /* 0x40025090 */
+#define PPC_R_ADDR37                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[37])                             /* 0x40025094 */
+#define PPC_R_ADDR38                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[38])                             /* 0x40025098 */
+#define PPC_R_ADDR39                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[39])                             /* 0x4002509C */
+#define PPC_R_ADDR40                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[40])                             /* 0x400250A0 */
+#define PPC_R_ADDR41                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[41])                             /* 0x400250A4 */
+#define PPC_R_ADDR42                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[42])                             /* 0x400250A8 */
+#define PPC_R_ADDR43                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[43])                             /* 0x400250AC */
+#define PPC_R_ADDR44                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[44])                             /* 0x400250B0 */
+#define PPC_R_ADDR45                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[45])                             /* 0x400250B4 */
+#define PPC_R_ADDR46                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[46])                             /* 0x400250B8 */
+#define PPC_R_ADDR47                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[47])                             /* 0x400250BC */
+#define PPC_R_ADDR48                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[48])                             /* 0x400250C0 */
+#define PPC_R_ADDR49                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[49])                             /* 0x400250C4 */
+#define PPC_R_ADDR50                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[50])                             /* 0x400250C8 */
+#define PPC_R_ADDR51                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[51])                             /* 0x400250CC */
+#define PPC_R_ADDR52                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[52])                             /* 0x400250D0 */
+#define PPC_R_ADDR53                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[53])                             /* 0x400250D4 */
+#define PPC_R_ADDR54                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[54])                             /* 0x400250D8 */
+#define PPC_R_ADDR55                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[55])                             /* 0x400250DC */
+#define PPC_R_ADDR56                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[56])                             /* 0x400250E0 */
+#define PPC_R_ADDR57                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[57])                             /* 0x400250E4 */
+#define PPC_R_ADDR58                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[58])                             /* 0x400250E8 */
+#define PPC_R_ADDR59                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[59])                             /* 0x400250EC */
+#define PPC_R_ADDR60                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[60])                             /* 0x400250F0 */
+#define PPC_R_ADDR61                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[61])                             /* 0x400250F4 */
+#define PPC_R_ADDR62                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[62])                             /* 0x400250F8 */
+#define PPC_R_ADDR63                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[63])                             /* 0x400250FC */
+#define PPC_R_ADDR64                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[64])                             /* 0x40025100 */
+#define PPC_R_ADDR65                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[65])                             /* 0x40025104 */
+#define PPC_R_ADDR66                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[66])                             /* 0x40025108 */
+#define PPC_R_ADDR67                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[67])                             /* 0x4002510C */
+#define PPC_R_ADDR68                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[68])                             /* 0x40025110 */
+#define PPC_R_ADDR69                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[69])                             /* 0x40025114 */
+#define PPC_R_ADDR70                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[70])                             /* 0x40025118 */
+#define PPC_R_ADDR71                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[71])                             /* 0x4002511C */
+#define PPC_R_ADDR72                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[72])                             /* 0x40025120 */
+#define PPC_R_ADDR73                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[73])                             /* 0x40025124 */
+#define PPC_R_ADDR74                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[74])                             /* 0x40025128 */
+#define PPC_R_ADDR75                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[75])                             /* 0x4002512C */
+#define PPC_R_ADDR76                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[76])                             /* 0x40025130 */
+#define PPC_R_ADDR77                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[77])                             /* 0x40025134 */
+#define PPC_R_ADDR78                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[78])                             /* 0x40025138 */
+#define PPC_R_ADDR79                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[79])                             /* 0x4002513C */
+#define PPC_R_ADDR80                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[80])                             /* 0x40025140 */
+#define PPC_R_ADDR81                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[81])                             /* 0x40025144 */
+#define PPC_R_ADDR82                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[82])                             /* 0x40025148 */
+#define PPC_R_ADDR83                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[83])                             /* 0x4002514C */
+#define PPC_R_ADDR84                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[84])                             /* 0x40025150 */
+#define PPC_R_ADDR85                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[85])                             /* 0x40025154 */
+#define PPC_R_ADDR86                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[86])                             /* 0x40025158 */
+#define PPC_R_ADDR87                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[87])                             /* 0x4002515C */
+#define PPC_R_ADDR88                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[88])                             /* 0x40025160 */
+#define PPC_R_ADDR89                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[89])                             /* 0x40025164 */
+#define PPC_R_ADDR90                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[90])                             /* 0x40025168 */
+#define PPC_R_ADDR91                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[91])                             /* 0x4002516C */
+#define PPC_R_ADDR92                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[92])                             /* 0x40025170 */
+#define PPC_R_ADDR93                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[93])                             /* 0x40025174 */
+#define PPC_R_ADDR94                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[94])                             /* 0x40025178 */
+#define PPC_R_ADDR95                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[95])                             /* 0x4002517C */
+#define PPC_R_ADDR96                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[96])                             /* 0x40025180 */
+#define PPC_R_ADDR97                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[97])                             /* 0x40025184 */
+#define PPC_R_ADDR98                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[98])                             /* 0x40025188 */
+#define PPC_R_ADDR99                            ((PPC_R_ADDR_Type*) &PPC->R_ADDR[99])                             /* 0x4002518C */
+#define PPC_R_ADDR100                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[100])                            /* 0x40025190 */
+#define PPC_R_ADDR101                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[101])                            /* 0x40025194 */
+#define PPC_R_ADDR102                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[102])                            /* 0x40025198 */
+#define PPC_R_ADDR103                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[103])                            /* 0x4002519C */
+#define PPC_R_ADDR104                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[104])                            /* 0x400251A0 */
+#define PPC_R_ADDR105                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[105])                            /* 0x400251A4 */
+#define PPC_R_ADDR106                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[106])                            /* 0x400251A8 */
+#define PPC_R_ADDR107                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[107])                            /* 0x400251AC */
+#define PPC_R_ADDR108                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[108])                            /* 0x400251B0 */
+#define PPC_R_ADDR109                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[109])                            /* 0x400251B4 */
+#define PPC_R_ADDR110                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[110])                            /* 0x400251B8 */
+#define PPC_R_ADDR111                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[111])                            /* 0x400251BC */
+#define PPC_R_ADDR112                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[112])                            /* 0x400251C0 */
+#define PPC_R_ADDR113                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[113])                            /* 0x400251C4 */
+#define PPC_R_ADDR114                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[114])                            /* 0x400251C8 */
+#define PPC_R_ADDR115                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[115])                            /* 0x400251CC */
+#define PPC_R_ADDR116                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[116])                            /* 0x400251D0 */
+#define PPC_R_ADDR117                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[117])                            /* 0x400251D4 */
+#define PPC_R_ADDR118                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[118])                            /* 0x400251D8 */
+#define PPC_R_ADDR119                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[119])                            /* 0x400251DC */
+#define PPC_R_ADDR120                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[120])                            /* 0x400251E0 */
+#define PPC_R_ADDR121                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[121])                            /* 0x400251E4 */
+#define PPC_R_ADDR122                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[122])                            /* 0x400251E8 */
+#define PPC_R_ADDR123                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[123])                            /* 0x400251EC */
+#define PPC_R_ADDR124                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[124])                            /* 0x400251F0 */
+#define PPC_R_ADDR125                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[125])                            /* 0x400251F4 */
+#define PPC_R_ADDR126                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[126])                            /* 0x400251F8 */
+#define PPC_R_ADDR127                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[127])                            /* 0x400251FC */
+#define PPC_R_ADDR128                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[128])                            /* 0x40025200 */
+#define PPC_R_ADDR129                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[129])                            /* 0x40025204 */
+#define PPC_R_ADDR130                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[130])                            /* 0x40025208 */
+#define PPC_R_ADDR131                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[131])                            /* 0x4002520C */
+#define PPC_R_ADDR132                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[132])                            /* 0x40025210 */
+#define PPC_R_ADDR133                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[133])                            /* 0x40025214 */
+#define PPC_R_ADDR134                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[134])                            /* 0x40025218 */
+#define PPC_R_ADDR135                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[135])                            /* 0x4002521C */
+#define PPC_R_ADDR136                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[136])                            /* 0x40025220 */
+#define PPC_R_ADDR137                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[137])                            /* 0x40025224 */
+#define PPC_R_ADDR138                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[138])                            /* 0x40025228 */
+#define PPC_R_ADDR139                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[139])                            /* 0x4002522C */
+#define PPC_R_ADDR140                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[140])                            /* 0x40025230 */
+#define PPC_R_ADDR141                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[141])                            /* 0x40025234 */
+#define PPC_R_ADDR142                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[142])                            /* 0x40025238 */
+#define PPC_R_ADDR143                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[143])                            /* 0x4002523C */
+#define PPC_R_ADDR144                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[144])                            /* 0x40025240 */
+#define PPC_R_ADDR145                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[145])                            /* 0x40025244 */
+#define PPC_R_ADDR146                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[146])                            /* 0x40025248 */
+#define PPC_R_ADDR147                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[147])                            /* 0x4002524C */
+#define PPC_R_ADDR148                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[148])                            /* 0x40025250 */
+#define PPC_R_ADDR149                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[149])                            /* 0x40025254 */
+#define PPC_R_ADDR150                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[150])                            /* 0x40025258 */
+#define PPC_R_ADDR151                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[151])                            /* 0x4002525C */
+#define PPC_R_ADDR152                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[152])                            /* 0x40025260 */
+#define PPC_R_ADDR153                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[153])                            /* 0x40025264 */
+#define PPC_R_ADDR154                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[154])                            /* 0x40025268 */
+#define PPC_R_ADDR155                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[155])                            /* 0x4002526C */
+#define PPC_R_ADDR156                           ((PPC_R_ADDR_Type*) &PPC->R_ADDR[156])                            /* 0x40025270 */
+#define PPC_R_ATT0                              ((PPC_R_ATT_Type*) &PPC->R_ATT[0])                                /* 0x40026000 */
+#define PPC_R_ATT1                              ((PPC_R_ATT_Type*) &PPC->R_ATT[1])                                /* 0x40026004 */
+#define PPC_R_ATT2                              ((PPC_R_ATT_Type*) &PPC->R_ATT[2])                                /* 0x40026008 */
+#define PPC_R_ATT3                              ((PPC_R_ATT_Type*) &PPC->R_ATT[3])                                /* 0x4002600C */
+#define PPC_R_ATT4                              ((PPC_R_ATT_Type*) &PPC->R_ATT[4])                                /* 0x40026010 */
+#define PPC_R_ATT5                              ((PPC_R_ATT_Type*) &PPC->R_ATT[5])                                /* 0x40026014 */
+#define PPC_R_ATT6                              ((PPC_R_ATT_Type*) &PPC->R_ATT[6])                                /* 0x40026018 */
+#define PPC_R_ATT7                              ((PPC_R_ATT_Type*) &PPC->R_ATT[7])                                /* 0x4002601C */
+#define PPC_R_ATT8                              ((PPC_R_ATT_Type*) &PPC->R_ATT[8])                                /* 0x40026020 */
+#define PPC_R_ATT9                              ((PPC_R_ATT_Type*) &PPC->R_ATT[9])                                /* 0x40026024 */
+#define PPC_R_ATT10                             ((PPC_R_ATT_Type*) &PPC->R_ATT[10])                               /* 0x40026028 */
+#define PPC_R_ATT11                             ((PPC_R_ATT_Type*) &PPC->R_ATT[11])                               /* 0x4002602C */
+#define PPC_R_ATT12                             ((PPC_R_ATT_Type*) &PPC->R_ATT[12])                               /* 0x40026030 */
+#define PPC_R_ATT13                             ((PPC_R_ATT_Type*) &PPC->R_ATT[13])                               /* 0x40026034 */
+#define PPC_R_ATT14                             ((PPC_R_ATT_Type*) &PPC->R_ATT[14])                               /* 0x40026038 */
+#define PPC_R_ATT15                             ((PPC_R_ATT_Type*) &PPC->R_ATT[15])                               /* 0x4002603C */
+#define PPC_R_ATT16                             ((PPC_R_ATT_Type*) &PPC->R_ATT[16])                               /* 0x40026040 */
+#define PPC_R_ATT17                             ((PPC_R_ATT_Type*) &PPC->R_ATT[17])                               /* 0x40026044 */
+#define PPC_R_ATT18                             ((PPC_R_ATT_Type*) &PPC->R_ATT[18])                               /* 0x40026048 */
+#define PPC_R_ATT19                             ((PPC_R_ATT_Type*) &PPC->R_ATT[19])                               /* 0x4002604C */
+#define PPC_R_ATT20                             ((PPC_R_ATT_Type*) &PPC->R_ATT[20])                               /* 0x40026050 */
+#define PPC_R_ATT21                             ((PPC_R_ATT_Type*) &PPC->R_ATT[21])                               /* 0x40026054 */
+#define PPC_R_ATT22                             ((PPC_R_ATT_Type*) &PPC->R_ATT[22])                               /* 0x40026058 */
+#define PPC_R_ATT23                             ((PPC_R_ATT_Type*) &PPC->R_ATT[23])                               /* 0x4002605C */
+#define PPC_R_ATT24                             ((PPC_R_ATT_Type*) &PPC->R_ATT[24])                               /* 0x40026060 */
+#define PPC_R_ATT25                             ((PPC_R_ATT_Type*) &PPC->R_ATT[25])                               /* 0x40026064 */
+#define PPC_R_ATT26                             ((PPC_R_ATT_Type*) &PPC->R_ATT[26])                               /* 0x40026068 */
+#define PPC_R_ATT27                             ((PPC_R_ATT_Type*) &PPC->R_ATT[27])                               /* 0x4002606C */
+#define PPC_R_ATT28                             ((PPC_R_ATT_Type*) &PPC->R_ATT[28])                               /* 0x40026070 */
+#define PPC_R_ATT29                             ((PPC_R_ATT_Type*) &PPC->R_ATT[29])                               /* 0x40026074 */
+#define PPC_R_ATT30                             ((PPC_R_ATT_Type*) &PPC->R_ATT[30])                               /* 0x40026078 */
+#define PPC_R_ATT31                             ((PPC_R_ATT_Type*) &PPC->R_ATT[31])                               /* 0x4002607C */
+#define PPC_R_ATT32                             ((PPC_R_ATT_Type*) &PPC->R_ATT[32])                               /* 0x40026080 */
+#define PPC_R_ATT33                             ((PPC_R_ATT_Type*) &PPC->R_ATT[33])                               /* 0x40026084 */
+#define PPC_R_ATT34                             ((PPC_R_ATT_Type*) &PPC->R_ATT[34])                               /* 0x40026088 */
+#define PPC_R_ATT35                             ((PPC_R_ATT_Type*) &PPC->R_ATT[35])                               /* 0x4002608C */
+#define PPC_R_ATT36                             ((PPC_R_ATT_Type*) &PPC->R_ATT[36])                               /* 0x40026090 */
+#define PPC_R_ATT37                             ((PPC_R_ATT_Type*) &PPC->R_ATT[37])                               /* 0x40026094 */
+#define PPC_R_ATT38                             ((PPC_R_ATT_Type*) &PPC->R_ATT[38])                               /* 0x40026098 */
+#define PPC_R_ATT39                             ((PPC_R_ATT_Type*) &PPC->R_ATT[39])                               /* 0x4002609C */
+#define PPC_R_ATT40                             ((PPC_R_ATT_Type*) &PPC->R_ATT[40])                               /* 0x400260A0 */
+#define PPC_R_ATT41                             ((PPC_R_ATT_Type*) &PPC->R_ATT[41])                               /* 0x400260A4 */
+#define PPC_R_ATT42                             ((PPC_R_ATT_Type*) &PPC->R_ATT[42])                               /* 0x400260A8 */
+#define PPC_R_ATT43                             ((PPC_R_ATT_Type*) &PPC->R_ATT[43])                               /* 0x400260AC */
+#define PPC_R_ATT44                             ((PPC_R_ATT_Type*) &PPC->R_ATT[44])                               /* 0x400260B0 */
+#define PPC_R_ATT45                             ((PPC_R_ATT_Type*) &PPC->R_ATT[45])                               /* 0x400260B4 */
+#define PPC_R_ATT46                             ((PPC_R_ATT_Type*) &PPC->R_ATT[46])                               /* 0x400260B8 */
+#define PPC_R_ATT47                             ((PPC_R_ATT_Type*) &PPC->R_ATT[47])                               /* 0x400260BC */
+#define PPC_R_ATT48                             ((PPC_R_ATT_Type*) &PPC->R_ATT[48])                               /* 0x400260C0 */
+#define PPC_R_ATT49                             ((PPC_R_ATT_Type*) &PPC->R_ATT[49])                               /* 0x400260C4 */
+#define PPC_R_ATT50                             ((PPC_R_ATT_Type*) &PPC->R_ATT[50])                               /* 0x400260C8 */
+#define PPC_R_ATT51                             ((PPC_R_ATT_Type*) &PPC->R_ATT[51])                               /* 0x400260CC */
+#define PPC_R_ATT52                             ((PPC_R_ATT_Type*) &PPC->R_ATT[52])                               /* 0x400260D0 */
+#define PPC_R_ATT53                             ((PPC_R_ATT_Type*) &PPC->R_ATT[53])                               /* 0x400260D4 */
+#define PPC_R_ATT54                             ((PPC_R_ATT_Type*) &PPC->R_ATT[54])                               /* 0x400260D8 */
+#define PPC_R_ATT55                             ((PPC_R_ATT_Type*) &PPC->R_ATT[55])                               /* 0x400260DC */
+#define PPC_R_ATT56                             ((PPC_R_ATT_Type*) &PPC->R_ATT[56])                               /* 0x400260E0 */
+#define PPC_R_ATT57                             ((PPC_R_ATT_Type*) &PPC->R_ATT[57])                               /* 0x400260E4 */
+#define PPC_R_ATT58                             ((PPC_R_ATT_Type*) &PPC->R_ATT[58])                               /* 0x400260E8 */
+#define PPC_R_ATT59                             ((PPC_R_ATT_Type*) &PPC->R_ATT[59])                               /* 0x400260EC */
+#define PPC_R_ATT60                             ((PPC_R_ATT_Type*) &PPC->R_ATT[60])                               /* 0x400260F0 */
+#define PPC_R_ATT61                             ((PPC_R_ATT_Type*) &PPC->R_ATT[61])                               /* 0x400260F4 */
+#define PPC_R_ATT62                             ((PPC_R_ATT_Type*) &PPC->R_ATT[62])                               /* 0x400260F8 */
+#define PPC_R_ATT63                             ((PPC_R_ATT_Type*) &PPC->R_ATT[63])                               /* 0x400260FC */
+#define PPC_R_ATT64                             ((PPC_R_ATT_Type*) &PPC->R_ATT[64])                               /* 0x40026100 */
+#define PPC_R_ATT65                             ((PPC_R_ATT_Type*) &PPC->R_ATT[65])                               /* 0x40026104 */
+#define PPC_R_ATT66                             ((PPC_R_ATT_Type*) &PPC->R_ATT[66])                               /* 0x40026108 */
+#define PPC_R_ATT67                             ((PPC_R_ATT_Type*) &PPC->R_ATT[67])                               /* 0x4002610C */
+#define PPC_R_ATT68                             ((PPC_R_ATT_Type*) &PPC->R_ATT[68])                               /* 0x40026110 */
+#define PPC_R_ATT69                             ((PPC_R_ATT_Type*) &PPC->R_ATT[69])                               /* 0x40026114 */
+#define PPC_R_ATT70                             ((PPC_R_ATT_Type*) &PPC->R_ATT[70])                               /* 0x40026118 */
+#define PPC_R_ATT71                             ((PPC_R_ATT_Type*) &PPC->R_ATT[71])                               /* 0x4002611C */
+#define PPC_R_ATT72                             ((PPC_R_ATT_Type*) &PPC->R_ATT[72])                               /* 0x40026120 */
+#define PPC_R_ATT73                             ((PPC_R_ATT_Type*) &PPC->R_ATT[73])                               /* 0x40026124 */
+#define PPC_R_ATT74                             ((PPC_R_ATT_Type*) &PPC->R_ATT[74])                               /* 0x40026128 */
+#define PPC_R_ATT75                             ((PPC_R_ATT_Type*) &PPC->R_ATT[75])                               /* 0x4002612C */
+#define PPC_R_ATT76                             ((PPC_R_ATT_Type*) &PPC->R_ATT[76])                               /* 0x40026130 */
+#define PPC_R_ATT77                             ((PPC_R_ATT_Type*) &PPC->R_ATT[77])                               /* 0x40026134 */
+#define PPC_R_ATT78                             ((PPC_R_ATT_Type*) &PPC->R_ATT[78])                               /* 0x40026138 */
+#define PPC_R_ATT79                             ((PPC_R_ATT_Type*) &PPC->R_ATT[79])                               /* 0x4002613C */
+#define PPC_R_ATT80                             ((PPC_R_ATT_Type*) &PPC->R_ATT[80])                               /* 0x40026140 */
+#define PPC_R_ATT81                             ((PPC_R_ATT_Type*) &PPC->R_ATT[81])                               /* 0x40026144 */
+#define PPC_R_ATT82                             ((PPC_R_ATT_Type*) &PPC->R_ATT[82])                               /* 0x40026148 */
+#define PPC_R_ATT83                             ((PPC_R_ATT_Type*) &PPC->R_ATT[83])                               /* 0x4002614C */
+#define PPC_R_ATT84                             ((PPC_R_ATT_Type*) &PPC->R_ATT[84])                               /* 0x40026150 */
+#define PPC_R_ATT85                             ((PPC_R_ATT_Type*) &PPC->R_ATT[85])                               /* 0x40026154 */
+#define PPC_R_ATT86                             ((PPC_R_ATT_Type*) &PPC->R_ATT[86])                               /* 0x40026158 */
+#define PPC_R_ATT87                             ((PPC_R_ATT_Type*) &PPC->R_ATT[87])                               /* 0x4002615C */
+#define PPC_R_ATT88                             ((PPC_R_ATT_Type*) &PPC->R_ATT[88])                               /* 0x40026160 */
+#define PPC_R_ATT89                             ((PPC_R_ATT_Type*) &PPC->R_ATT[89])                               /* 0x40026164 */
+#define PPC_R_ATT90                             ((PPC_R_ATT_Type*) &PPC->R_ATT[90])                               /* 0x40026168 */
+#define PPC_R_ATT91                             ((PPC_R_ATT_Type*) &PPC->R_ATT[91])                               /* 0x4002616C */
+#define PPC_R_ATT92                             ((PPC_R_ATT_Type*) &PPC->R_ATT[92])                               /* 0x40026170 */
+#define PPC_R_ATT93                             ((PPC_R_ATT_Type*) &PPC->R_ATT[93])                               /* 0x40026174 */
+#define PPC_R_ATT94                             ((PPC_R_ATT_Type*) &PPC->R_ATT[94])                               /* 0x40026178 */
+#define PPC_R_ATT95                             ((PPC_R_ATT_Type*) &PPC->R_ATT[95])                               /* 0x4002617C */
+#define PPC_R_ATT96                             ((PPC_R_ATT_Type*) &PPC->R_ATT[96])                               /* 0x40026180 */
+#define PPC_R_ATT97                             ((PPC_R_ATT_Type*) &PPC->R_ATT[97])                               /* 0x40026184 */
+#define PPC_R_ATT98                             ((PPC_R_ATT_Type*) &PPC->R_ATT[98])                               /* 0x40026188 */
+#define PPC_R_ATT99                             ((PPC_R_ATT_Type*) &PPC->R_ATT[99])                               /* 0x4002618C */
+#define PPC_R_ATT100                            ((PPC_R_ATT_Type*) &PPC->R_ATT[100])                              /* 0x40026190 */
+#define PPC_R_ATT101                            ((PPC_R_ATT_Type*) &PPC->R_ATT[101])                              /* 0x40026194 */
+#define PPC_R_ATT102                            ((PPC_R_ATT_Type*) &PPC->R_ATT[102])                              /* 0x40026198 */
+#define PPC_R_ATT103                            ((PPC_R_ATT_Type*) &PPC->R_ATT[103])                              /* 0x4002619C */
+#define PPC_R_ATT104                            ((PPC_R_ATT_Type*) &PPC->R_ATT[104])                              /* 0x400261A0 */
+#define PPC_R_ATT105                            ((PPC_R_ATT_Type*) &PPC->R_ATT[105])                              /* 0x400261A4 */
+#define PPC_R_ATT106                            ((PPC_R_ATT_Type*) &PPC->R_ATT[106])                              /* 0x400261A8 */
+#define PPC_R_ATT107                            ((PPC_R_ATT_Type*) &PPC->R_ATT[107])                              /* 0x400261AC */
+#define PPC_R_ATT108                            ((PPC_R_ATT_Type*) &PPC->R_ATT[108])                              /* 0x400261B0 */
+#define PPC_R_ATT109                            ((PPC_R_ATT_Type*) &PPC->R_ATT[109])                              /* 0x400261B4 */
+#define PPC_R_ATT110                            ((PPC_R_ATT_Type*) &PPC->R_ATT[110])                              /* 0x400261B8 */
+#define PPC_R_ATT111                            ((PPC_R_ATT_Type*) &PPC->R_ATT[111])                              /* 0x400261BC */
+#define PPC_R_ATT112                            ((PPC_R_ATT_Type*) &PPC->R_ATT[112])                              /* 0x400261C0 */
+#define PPC_R_ATT113                            ((PPC_R_ATT_Type*) &PPC->R_ATT[113])                              /* 0x400261C4 */
+#define PPC_R_ATT114                            ((PPC_R_ATT_Type*) &PPC->R_ATT[114])                              /* 0x400261C8 */
+#define PPC_R_ATT115                            ((PPC_R_ATT_Type*) &PPC->R_ATT[115])                              /* 0x400261CC */
+#define PPC_R_ATT116                            ((PPC_R_ATT_Type*) &PPC->R_ATT[116])                              /* 0x400261D0 */
+#define PPC_R_ATT117                            ((PPC_R_ATT_Type*) &PPC->R_ATT[117])                              /* 0x400261D4 */
+#define PPC_R_ATT118                            ((PPC_R_ATT_Type*) &PPC->R_ATT[118])                              /* 0x400261D8 */
+#define PPC_R_ATT119                            ((PPC_R_ATT_Type*) &PPC->R_ATT[119])                              /* 0x400261DC */
+#define PPC_R_ATT120                            ((PPC_R_ATT_Type*) &PPC->R_ATT[120])                              /* 0x400261E0 */
+#define PPC_R_ATT121                            ((PPC_R_ATT_Type*) &PPC->R_ATT[121])                              /* 0x400261E4 */
+#define PPC_R_ATT122                            ((PPC_R_ATT_Type*) &PPC->R_ATT[122])                              /* 0x400261E8 */
+#define PPC_R_ATT123                            ((PPC_R_ATT_Type*) &PPC->R_ATT[123])                              /* 0x400261EC */
+#define PPC_R_ATT124                            ((PPC_R_ATT_Type*) &PPC->R_ATT[124])                              /* 0x400261F0 */
+#define PPC_R_ATT125                            ((PPC_R_ATT_Type*) &PPC->R_ATT[125])                              /* 0x400261F4 */
+#define PPC_R_ATT126                            ((PPC_R_ATT_Type*) &PPC->R_ATT[126])                              /* 0x400261F8 */
+#define PPC_R_ATT127                            ((PPC_R_ATT_Type*) &PPC->R_ATT[127])                              /* 0x400261FC */
+#define PPC_R_ATT128                            ((PPC_R_ATT_Type*) &PPC->R_ATT[128])                              /* 0x40026200 */
+#define PPC_R_ATT129                            ((PPC_R_ATT_Type*) &PPC->R_ATT[129])                              /* 0x40026204 */
+#define PPC_R_ATT130                            ((PPC_R_ATT_Type*) &PPC->R_ATT[130])                              /* 0x40026208 */
+#define PPC_R_ATT131                            ((PPC_R_ATT_Type*) &PPC->R_ATT[131])                              /* 0x4002620C */
+#define PPC_R_ATT132                            ((PPC_R_ATT_Type*) &PPC->R_ATT[132])                              /* 0x40026210 */
+#define PPC_R_ATT133                            ((PPC_R_ATT_Type*) &PPC->R_ATT[133])                              /* 0x40026214 */
+#define PPC_R_ATT134                            ((PPC_R_ATT_Type*) &PPC->R_ATT[134])                              /* 0x40026218 */
+#define PPC_R_ATT135                            ((PPC_R_ATT_Type*) &PPC->R_ATT[135])                              /* 0x4002621C */
+#define PPC_R_ATT136                            ((PPC_R_ATT_Type*) &PPC->R_ATT[136])                              /* 0x40026220 */
+#define PPC_R_ATT137                            ((PPC_R_ATT_Type*) &PPC->R_ATT[137])                              /* 0x40026224 */
+#define PPC_R_ATT138                            ((PPC_R_ATT_Type*) &PPC->R_ATT[138])                              /* 0x40026228 */
+#define PPC_R_ATT139                            ((PPC_R_ATT_Type*) &PPC->R_ATT[139])                              /* 0x4002622C */
+#define PPC_R_ATT140                            ((PPC_R_ATT_Type*) &PPC->R_ATT[140])                              /* 0x40026230 */
+#define PPC_R_ATT141                            ((PPC_R_ATT_Type*) &PPC->R_ATT[141])                              /* 0x40026234 */
+#define PPC_R_ATT142                            ((PPC_R_ATT_Type*) &PPC->R_ATT[142])                              /* 0x40026238 */
+#define PPC_R_ATT143                            ((PPC_R_ATT_Type*) &PPC->R_ATT[143])                              /* 0x4002623C */
+#define PPC_R_ATT144                            ((PPC_R_ATT_Type*) &PPC->R_ATT[144])                              /* 0x40026240 */
+#define PPC_R_ATT145                            ((PPC_R_ATT_Type*) &PPC->R_ATT[145])                              /* 0x40026244 */
+#define PPC_R_ATT146                            ((PPC_R_ATT_Type*) &PPC->R_ATT[146])                              /* 0x40026248 */
+#define PPC_R_ATT147                            ((PPC_R_ATT_Type*) &PPC->R_ATT[147])                              /* 0x4002624C */
+#define PPC_R_ATT148                            ((PPC_R_ATT_Type*) &PPC->R_ATT[148])                              /* 0x40026250 */
+#define PPC_R_ATT149                            ((PPC_R_ATT_Type*) &PPC->R_ATT[149])                              /* 0x40026254 */
+#define PPC_R_ATT150                            ((PPC_R_ATT_Type*) &PPC->R_ATT[150])                              /* 0x40026258 */
+#define PPC_R_ATT151                            ((PPC_R_ATT_Type*) &PPC->R_ATT[151])                              /* 0x4002625C */
+#define PPC_R_ATT152                            ((PPC_R_ATT_Type*) &PPC->R_ATT[152])                              /* 0x40026260 */
+#define PPC_R_ATT153                            ((PPC_R_ATT_Type*) &PPC->R_ATT[153])                              /* 0x40026264 */
+#define PPC_R_ATT154                            ((PPC_R_ATT_Type*) &PPC->R_ATT[154])                              /* 0x40026268 */
+#define PPC_R_ATT155                            ((PPC_R_ATT_Type*) &PPC->R_ATT[155])                              /* 0x4002626C */
+#define PPC_R_ATT156                            ((PPC_R_ATT_Type*) &PPC->R_ATT[156])                              /* 0x40026270 */
+
+/*******************************************************************************
+*                                  PERI_PCLK
+*******************************************************************************/
+
+#define PERI_PCLK_BASE                          0x40040000UL
+#define PERI_PCLK                               ((PERI_PCLK_Type*) PERI_PCLK_BASE)                                /* 0x40040000 */
+#define PERI_PCLK_GR0                           ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[0])                          /* 0x40040000 */
+#define PERI_PCLK_GR1                           ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[1])                          /* 0x40042000 */
+#define PERI_PCLK_GR2                           ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[2])                          /* 0x40044000 */
+#define PERI_PCLK_GR3                           ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[3])                          /* 0x40046000 */
+#define PERI_PCLK_GR4                           ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[4])                          /* 0x40048000 */
+#define PERI_PCLK_GR5                           ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[5])                          /* 0x4004A000 */
+#define PERI_PCLK_GR6                           ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[6])                          /* 0x4004C000 */
+
+/*******************************************************************************
+*                                   RAMC_PPU
+*******************************************************************************/
+
+#define RAMC_PPU0_BASE                          0x40100000UL
+#define RAMC_PPU1_BASE                          0x40101000UL
+#define RAMC_PPU2_BASE                          0x40102000UL
+#define RAMC_PPU0                               ((RAMC_PPU_Type*) RAMC_PPU0_BASE)                                 /* 0x40100000 */
+#define RAMC_PPU1                               ((RAMC_PPU_Type*) RAMC_PPU1_BASE)                                 /* 0x40101000 */
+#define RAMC_PPU2                               ((RAMC_PPU_Type*) RAMC_PPU2_BASE)                                 /* 0x40102000 */
+
+/*******************************************************************************
+*                                    ICACHE
+*******************************************************************************/
+
+#define ICACHE0_BASE                            0x40103000UL
+#define ICACHE1_BASE                            0x40104000UL
+#define ICACHE0                                 ((ICACHE_Type*) ICACHE0_BASE)                                     /* 0x40103000 */
+#define ICACHE1                                 ((ICACHE_Type*) ICACHE1_BASE)                                     /* 0x40104000 */
+
+/*******************************************************************************
+*                                  CPUSS_PPU
+*******************************************************************************/
+
+#define CPUSS_PPU_BASE                          0x40105000UL
+#define CPUSS_PPU                               ((CPUSS_PPU_Type*) CPUSS_PPU_BASE)                                /* 0x40105000 */
+
+/*******************************************************************************
+*                                     RAMC
+*******************************************************************************/
+
+#define RAMC0_BASE                              0x40110000UL
+#define RAMC0                                   ((RAMC_Type*) RAMC0_BASE)                                         /* 0x40110000 */
+#define RAMC0_MPC0                              ((RAMC_MPC_Type*) &RAMC0->MPC[0])                                 /* 0x40114000 */
+
+/*******************************************************************************
+*                                    PROMC
+*******************************************************************************/
+
+#define PROMC_BASE                              0x40140000UL
+#define PROMC                                   ((PROMC_Type*) PROMC_BASE)                                        /* 0x40140000 */
+#define PROMC_MPC0                              ((PROMC_MPC_Type*) &PROMC->MPC[0])                                /* 0x40141000 */
+
+/*******************************************************************************
+*                                    MXCM33
+*******************************************************************************/
+
+#define MXCM33_BASE                             0x40160000UL
+#define MXCM33                                  ((MXCM33_Type*) MXCM33_BASE)                                      /* 0x40160000 */
+
+/*******************************************************************************
+*                                      DW
+*******************************************************************************/
+
+#define DW0_BASE                                0x40180000UL
+#define DW0                                     ((DW_Type*) DW0_BASE)                                             /* 0x40180000 */
+#define DW0_CH_STRUCT0                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0])                         /* 0x40188000 */
+#define DW0_CH_STRUCT1                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1])                         /* 0x40188040 */
+#define DW0_CH_STRUCT2                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2])                         /* 0x40188080 */
+#define DW0_CH_STRUCT3                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3])                         /* 0x401880C0 */
+#define DW0_CH_STRUCT4                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4])                         /* 0x40188100 */
+#define DW0_CH_STRUCT5                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5])                         /* 0x40188140 */
+#define DW0_CH_STRUCT6                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6])                         /* 0x40188180 */
+#define DW0_CH_STRUCT7                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7])                         /* 0x401881C0 */
+#define DW0_CH_STRUCT8                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8])                         /* 0x40188200 */
+#define DW0_CH_STRUCT9                          ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9])                         /* 0x40188240 */
+#define DW0_CH_STRUCT10                         ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10])                        /* 0x40188280 */
+#define DW0_CH_STRUCT11                         ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11])                        /* 0x401882C0 */
+#define DW0_CH_STRUCT12                         ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12])                        /* 0x40188300 */
+#define DW0_CH_STRUCT13                         ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13])                        /* 0x40188340 */
+#define DW0_CH_STRUCT14                         ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14])                        /* 0x40188380 */
+#define DW0_CH_STRUCT15                         ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15])                        /* 0x401883C0 */
+
+/*******************************************************************************
+*                                    CPUSS
+*******************************************************************************/
+
+#define CPUSS_BASE                              0x401C0000UL
+#define CPUSS                                   ((CPUSS_Type*) CPUSS_BASE)                                        /* 0x401C0000 */
+
+/*******************************************************************************
+*                                  MS_CTL_1_2
+*******************************************************************************/
+
+#define MS_CTL_1_2_BASE                         0x401C4000UL
+#define MS_CTL_1_2                              ((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)                              /* 0x401C4000 */
+#define MS5                                     ((MS_Type*) &MS_CTL_1_2->MS[5])                                   /* 0x401C4050 */
+#define MS_PC5                                  ((MS_PC_Type*) &MS_CTL_1_2->MS_PC[5])                             /* 0x401C5050 */
+
+/*******************************************************************************
+*                                 CPUSS_SL_CTL
+*******************************************************************************/
+
+#define CPUSS_SL_CTL_BASE                       0x401C8000UL
+#define CPUSS_SL_CTL                            ((CPUSS_SL_CTL_Type*) CPUSS_SL_CTL_BASE)                          /* 0x401C8000 */
+
+/*******************************************************************************
+*                                     IPC
+*******************************************************************************/
+
+#define IPC_BASE                                0x401D0000UL
+#define IPC                                     ((IPC_Type*) IPC_BASE)                                            /* 0x401D0000 */
+#define IPC_STRUCT0                             ((IPC_STRUCT_Type*) &IPC->STRUCT[0])                              /* 0x401D0000 */
+#define IPC_STRUCT1                             ((IPC_STRUCT_Type*) &IPC->STRUCT[1])                              /* 0x401D0020 */
+#define IPC_STRUCT2                             ((IPC_STRUCT_Type*) &IPC->STRUCT[2])                              /* 0x401D0040 */
+#define IPC_STRUCT3                             ((IPC_STRUCT_Type*) &IPC->STRUCT[3])                              /* 0x401D0060 */
+#define IPC_INTR_STRUCT0                        ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0])                    /* 0x401D1000 */
+#define IPC_INTR_STRUCT1                        ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1])                    /* 0x401D1020 */
+
+/*******************************************************************************
+*                                     SRSS
+*******************************************************************************/
+
+#define SRSS_BASE                               0x40200000UL
+#define SRSS                                    ((SRSS_Type*) SRSS_BASE)                                          /* 0x40200000 */
+#define MCWDT_STRUCT0                           ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0])                     /* 0x4020D000 */
+
+/*******************************************************************************
+*                                   PWRMODE
+*******************************************************************************/
+
+#define PWRMODE_BASE                            0x40210000UL
+#define PWRMODE                                 ((PWRMODE_Type*) PWRMODE_BASE)                                    /* 0x40210000 */
+#define PWRMODE_PD0                             ((PWRMODE_PD_Type*) &PWRMODE->PD[0])                              /* 0x40210000 */
+#define PWRMODE_PD1                             ((PWRMODE_PD_Type*) &PWRMODE->PD[1])                              /* 0x40210010 */
+#define PWRMODE_PD2                             ((PWRMODE_PD_Type*) &PWRMODE->PD[2])                              /* 0x40210020 */
+#define PWRMODE_PD3                             ((PWRMODE_PD_Type*) &PWRMODE->PD[3])                              /* 0x40210030 */
+#define PWRMODE_PD4                             ((PWRMODE_PD_Type*) &PWRMODE->PD[4])                              /* 0x40210040 */
+#define PWRMODE_PD5                             ((PWRMODE_PD_Type*) &PWRMODE->PD[5])                              /* 0x40210050 */
+#define PWRMODE_PD6                             ((PWRMODE_PD_Type*) &PWRMODE->PD[6])                              /* 0x40210060 */
+#define PWRMODE_PD7                             ((PWRMODE_PD_Type*) &PWRMODE->PD[7])                              /* 0x40210070 */
+#define PWRMODE_PD8                             ((PWRMODE_PD_Type*) &PWRMODE->PD[8])                              /* 0x40210080 */
+#define PWRMODE_PD9                             ((PWRMODE_PD_Type*) &PWRMODE->PD[9])                              /* 0x40210090 */
+#define PWRMODE_PD10                            ((PWRMODE_PD_Type*) &PWRMODE->PD[10])                             /* 0x402100A0 */
+#define PWRMODE_PD11                            ((PWRMODE_PD_Type*) &PWRMODE->PD[11])                             /* 0x402100B0 */
+#define PWRMODE_PD12                            ((PWRMODE_PD_Type*) &PWRMODE->PD[12])                             /* 0x402100C0 */
+#define PWRMODE_PD13                            ((PWRMODE_PD_Type*) &PWRMODE->PD[13])                             /* 0x402100D0 */
+#define PWRMODE_PD14                            ((PWRMODE_PD_Type*) &PWRMODE->PD[14])                             /* 0x402100E0 */
+#define PWRMODE_PD15                            ((PWRMODE_PD_Type*) &PWRMODE->PD[15])                             /* 0x402100F0 */
+#define PWRMODE_PPU_MAIN                        ((PWRMODE_PPU_MAIN_Type*) &PWRMODE->PPU_MAIN)                     /* 0x40211000 */
+#define PWRMODE_PPU_MAIN_PPU_MAIN               ((PWRMODE_PPU_MAIN_PPU_MAIN_Type*) &PWRMODE->PPU_MAIN.PPU_MAIN)   /* 0x40211000 */
+
+/*******************************************************************************
+*                                    BACKUP
+*******************************************************************************/
+
+#define BACKUP_BASE                             0x40220000UL
+#define BACKUP                                  ((BACKUP_Type*) BACKUP_BASE)                                      /* 0x40220000 */
+
+/*******************************************************************************
+*                                    CRYPTO
+*******************************************************************************/
+
+#define CRYPTO_BASE                             0x40230000UL
+#define CRYPTO                                  ((CRYPTO_Type*) CRYPTO_BASE)                                      /* 0x40230000 */
+
+/*******************************************************************************
+*                                    HSIOM
+*******************************************************************************/
+
+#define HSIOM_BASE                              0x40400000UL
+#define HSIOM                                   ((HSIOM_Type*) HSIOM_BASE)                                        /* 0x40400000 */
+#define HSIOM_PRT0                              ((HSIOM_PRT_Type*) &HSIOM->PRT[0])                                /* 0x40400000 */
+#define HSIOM_PRT1                              ((HSIOM_PRT_Type*) &HSIOM->PRT[1])                                /* 0x40400010 */
+#define HSIOM_PRT2                              ((HSIOM_PRT_Type*) &HSIOM->PRT[2])                                /* 0x40400020 */
+#define HSIOM_PRT3                              ((HSIOM_PRT_Type*) &HSIOM->PRT[3])                                /* 0x40400030 */
+#define HSIOM_PRT4                              ((HSIOM_PRT_Type*) &HSIOM->PRT[4])                                /* 0x40400040 */
+#define HSIOM_PRT5                              ((HSIOM_PRT_Type*) &HSIOM->PRT[5])                                /* 0x40400050 */
+
+/*******************************************************************************
+*                                     GPIO
+*******************************************************************************/
+
+#define GPIO_BASE                               0x40410000UL
+#define GPIO                                    ((GPIO_Type*) GPIO_BASE)                                          /* 0x40410000 */
+#define GPIO_PRT0                               ((GPIO_PRT_Type*) &GPIO->PRT[0])                                  /* 0x40410000 */
+#define GPIO_PRT1                               ((GPIO_PRT_Type*) &GPIO->PRT[1])                                  /* 0x40410080 */
+#define GPIO_PRT2                               ((GPIO_PRT_Type*) &GPIO->PRT[2])                                  /* 0x40410100 */
+#define GPIO_PRT3                               ((GPIO_PRT_Type*) &GPIO->PRT[3])                                  /* 0x40410180 */
+#define GPIO_PRT4                               ((GPIO_PRT_Type*) &GPIO->PRT[4])                                  /* 0x40410200 */
+#define GPIO_PRT5                               ((GPIO_PRT_Type*) &GPIO->PRT[5])                                  /* 0x40410280 */
+
+/*******************************************************************************
+*                                   SMARTIO
+*******************************************************************************/
+
+#define SMARTIO_BASE                            0x40420000UL
+#define SMARTIO                                 ((SMARTIO_Type*) SMARTIO_BASE)                                    /* 0x40420000 */
+#define SMARTIO_PRT3                            ((SMARTIO_PRT_Type*) &SMARTIO->PRT[3])                            /* 0x40420300 */
+
+/*******************************************************************************
+*                                     LIN
+*******************************************************************************/
+
+#define LIN0_BASE                               0x40430000UL
+#define LIN0                                    ((LIN_Type*) LIN0_BASE)                                           /* 0x40430000 */
+#define LIN0_CH0                                ((LIN_CH_Type*) &LIN0->CH[0])                                     /* 0x40438000 */
+#define LIN0_CH1                                ((LIN_CH_Type*) &LIN0->CH[1])                                     /* 0x40438100 */
+
+/*******************************************************************************
+*                                    CANFD
+*******************************************************************************/
+
+#define CANFD0_BASE                             0x40440000UL
+#define CANFD0                                  ((CANFD_Type*) CANFD0_BASE)                                       /* 0x40440000 */
+#define CANFD0_CH0                              ((CANFD_CH_Type*) &CANFD0->CH[0])                                 /* 0x40440000 */
+#define CANFD0_CH0_M_TTCAN                      ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN)                 /* 0x40440000 */
+
+/*******************************************************************************
+*                                    TCPWM
+*******************************************************************************/
+
+#define TCPWM0_BASE                             0x404A0000UL
+#define TCPWM0                                  ((TCPWM_Type*) TCPWM0_BASE)                                       /* 0x404A0000 */
+#define TCPWM0_GRP0                             ((TCPWM_GRP_Type*) &TCPWM0->GRP[0])                               /* 0x404A0000 */
+#define TCPWM0_GRP1                             ((TCPWM_GRP_Type*) &TCPWM0->GRP[1])                               /* 0x404A8000 */
+#define TCPWM0_GRP0_CNT0                        ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0])                    /* 0x404A0000 */
+#define TCPWM0_GRP0_CNT1                        ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1])                    /* 0x404A0080 */
+#define TCPWM0_GRP1_CNT0                        ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0])                    /* 0x404A8000 */
+#define TCPWM0_GRP1_CNT1                        ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1])                    /* 0x404A8080 */
+#define TCPWM0_GRP1_CNT2                        ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2])                    /* 0x404A8100 */
+#define TCPWM0_GRP1_CNT3                        ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3])                    /* 0x404A8180 */
+#define TCPWM0_GRP1_CNT4                        ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4])                    /* 0x404A8200 */
+#define TCPWM0_GRP1_CNT5                        ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5])                    /* 0x404A8280 */
+#define TCPWM0_GRP1_CNT6                        ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6])                    /* 0x404A8300 */
+
+/*******************************************************************************
+*                                 MXS40ADCMIC
+*******************************************************************************/
+
+#define MXS40ADCMIC0_BASE                       0x40520000UL
+#define MXS40ADCMIC0                            ((MXS40ADCMIC_Type*) MXS40ADCMIC0_BASE)                           /* 0x40520000 */
+
+/*******************************************************************************
+*                                     SCB
+*******************************************************************************/
+
+#define SCB0_BASE                               0x40590000UL
+#define SCB1_BASE                               0x405A0000UL
+#define SCB2_BASE                               0x405B0000UL
+#define SCB0                                    ((CySCB_Type*) SCB0_BASE)                                         /* 0x40590000 */
+#define SCB1                                    ((CySCB_Type*) SCB1_BASE)                                         /* 0x405A0000 */
+#define SCB2                                    ((CySCB_Type*) SCB2_BASE)                                         /* 0x405B0000 */
+
+/*******************************************************************************
+*                                    EFUSE
+*******************************************************************************/
+
+#define EFUSE_BASE                              0x40810000UL
+#define EFUSE                                   ((EFUSE_Type*) EFUSE_BASE)                                        /* 0x40810000 */
+
+/*******************************************************************************
+*                                     SMIF
+*******************************************************************************/
+
+#define SMIF0_BASE                              0x40890000UL
+#define SMIF0                                   ((SMIF_Type*) SMIF0_BASE)                                         /* 0x40890000 */
+#define SMIF0_SMIF_CRYPTO0                      ((SMIF_SMIF_CRYPTO_Type*) &SMIF0->SMIF_CRYPTO_BLOCK[0])           /* 0x40890200 */
+#define SMIF0_DEVICE0                           ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0])                           /* 0x40890800 */
+#define SMIF0_DEVICE1                           ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1])                           /* 0x40890880 */
+#define SMIF0_MPC0                              ((SMIF_MPC_Type*) &SMIF0->MPC[0])                                 /* 0x40891000 */
+
+/*******************************************************************************
+*                                     TDM
+*******************************************************************************/
+
+#define TDM0_BASE                               0x408C0000UL
+#define TDM0                                    ((TDM_Type*) TDM0_BASE)                                           /* 0x408C0000 */
+#define TDM0_TDM_STRUCT0                        ((TDM_TDM_STRUCT_Type*) &TDM0->TDM_STRUCT[0])                     /* 0x408C8000 */
+#define TDM0_TDM_STRUCT0_TDM_TX_STRUCT          ((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type*) &TDM0->TDM_STRUCT[0].TDM_TX_STRUCT) /* 0x408C8000 */
+#define TDM0_TDM_STRUCT0_TDM_RX_STRUCT          ((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type*) &TDM0->TDM_STRUCT[0].TDM_RX_STRUCT) /* 0x408C8100 */
+
+/*******************************************************************************
+*                                     PDM
+*******************************************************************************/
+
+#define PDM0_BASE                               0x408D0000UL
+#define PDM0                                    ((PDM_Type*) PDM0_BASE)                                           /* 0x408D0000 */
+#define PDM0_CH0                                ((PDM_CH_Type*) &PDM0->CH[0])                                     /* 0x408D8000 */
+#define PDM0_CH1                                ((PDM_CH_Type*) &PDM0->CH[1])                                     /* 0x408D8100 */
+
+/*******************************************************************************
+*                                  MXKEYSCAN
+*******************************************************************************/
+
+#define MXKEYSCAN_BASE                          0x40920000UL
+#define MXKEYSCAN                               ((MXKEYSCAN_Type*) MXKEYSCAN_BASE)                                /* 0x40920000 */
+
+/*******************************************************************************
+*                                     BTSS
+*******************************************************************************/
+
+#define BTSS_BASE                               0x42000000UL
+#define BTSS                                    ((BTSS_Type*) BTSS_BASE)                                          /* 0x42000000 */
+#define BTSS_DATA_RAM_IPC                       ((BTSS_DATA_RAM_IPC_Type*) &BTSS->DATA_RAM_IPC)                   /* 0x42600000 */
+
+/** \} CYW20829_PSVP */
+
+#endif /* _CYW20829_PSVP_H_ */
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp.c b/boot/cypress/platforms/BSP/PSOC6/cybsp.c
new file mode 100644
index 0000000..d20fa97
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp.c
@@ -0,0 +1,157 @@
+/***************************************************************************//**
+* \file cybsp.c
+*
+* Description:
+* Provides initialization code for starting up the hardware contained on the
+* Infineon board.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdlib.h>
+#include "cy_syspm.h"
+#include "cy_sysclk.h"
+#include "cybsp.h"
+#if defined(CY_USING_HAL)
+#include "cyhal_hwmgr.h"
+#include "cyhal_syspm.h"
+
+#if defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
+#include "SDIO_HOST.h"
+#endif
+#endif // defined(CY_USING_HAL)
+
+#if defined(COMPONENT_MW_CAT1CM0P)
+    #include "mtb_cat1cm0p.h"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// The sysclk deep sleep callback is recommended to be the last callback that is executed before
+// entry into deep sleep mode and the first one upon exit the deep sleep mode.
+// Doing so minimizes the time spent on low power mode entry and exit.
+#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
+    #define CYBSP_SYSCLK_PM_CALLBACK_ORDER  (255u)
+#endif
+
+#if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+//--------------------------------------------------------------------------------------------------
+// cybsp_register_sysclk_pm_callback
+//
+// Registers a power management callback that prepares the clock system for entering deep sleep mode
+// and restore the clocks upon wakeup from deep sleep.
+// NOTE: This is called automatically as part of \ref cybsp_init
+//--------------------------------------------------------------------------------------------------
+static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
+{
+    cy_rslt_t                             result                         = CY_RSLT_SUCCESS;
+    static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
+    static cy_stc_syspm_callback_t        cybsp_sysclk_pm_callback       =
+    {
+        .callback       = &Cy_SysClk_DeepSleepCallback,
+        .type           = CY_SYSPM_DEEPSLEEP,
+        .callbackParams = &cybsp_sysclk_pm_callback_param,
+        .order          = CYBSP_SYSCLK_PM_CALLBACK_ORDER
+    };
+
+    if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
+    {
+        result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
+    }
+    return result;
+}
+
+
+#endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_init
+//--------------------------------------------------------------------------------------------------
+cy_rslt_t cybsp_init(void)
+{
+    // Setup hardware manager to track resource usage then initialize all system (clock/power) board
+    // configuration
+    #if defined(CY_USING_HAL)
+    cy_rslt_t result = cyhal_hwmgr_init();
+
+    if (CY_RSLT_SUCCESS == result)
+    {
+        result = cyhal_syspm_init();
+    }
+
+    #ifdef CY_CFG_PWR_VDDA_MV
+    if (CY_RSLT_SUCCESS == result)
+    {
+        cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
+    }
+    #endif
+
+    #else // if defined(CY_USING_HAL)
+    cy_rslt_t result = CY_RSLT_SUCCESS;
+    #endif // if defined(CY_USING_HAL)
+
+    // By default, the peripheral configuration will be done on the first core running user code.
+    // This is the CM0+ if it is available and not running a pre-built image, and the CM4 otherwise.
+    // This is done to ensure configuration is available for all cores that might need to use it.
+    // In the case of a dual core project, this can be changed below to perform initialization on
+    // the CM4 if necessary.
+    #if defined(CORE_NAME_CM0P_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM4_0) && \
+    defined(CY_USING_PREBUILT_CM0P_IMAGE))
+    //cycfg_config_init();
+    #endif
+
+    // Do any additional configuration reservations that are needed on all cores.
+    //cycfg_config_reservations();
+
+    if (CY_RSLT_SUCCESS == result)
+    {
+        #if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+        result = cybsp_register_custom_sysclk_pm_callback();
+        #else
+        result = cybsp_register_sysclk_pm_callback();
+        #endif
+    }
+
+    #if defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
+
+    // Reserve resources for the UDB SDIO interface that might want to be used by others. This
+    // includes specific clock and DMA instances. This must be done before other HAL API calls as
+    // specific peripheral instances are needed
+    // NOTE: The full SDIO/WiFi interface still needs to be initialized via
+    // cybsp_wifi_init_primary(). This is typically done when starting up WiFi.
+    if (CY_RSLT_SUCCESS == result)
+    {
+        result = SDIO_ReserveResources();
+    }
+    #endif // defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
+
+    // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was
+    // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP
+    // reservation list (cyreservedresources.list) to make sure no resources are reserved by both.
+    return result;
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp.h b/boot/cypress/platforms/BSP/PSOC6/cybsp.h
new file mode 100644
index 0000000..cd27cf6
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp.h
@@ -0,0 +1,83 @@
+/***********************************************************************************************//**
+ * \file cybsp.h
+ *
+ * \brief
+ * Basic API for setting up boards containing a Cypress MCU.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+#include "cybsp_hw_config.h"
+#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE)
+#include "cybsp_bt_config.h"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \addtogroup group_bsp_errors Error Codes
+ * \{
+ * Error codes specific to the board.
+ */
+
+/** Failed to configure sysclk power management callback */
+#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK  \
+    (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
+
+/** \} group_bsp_errors */
+
+/**
+ * \addtogroup group_bsp_functions Functions
+ * \{
+ * All functions exposed by the board.
+ */
+
+/**
+ * \brief Initialize all hardware on the board
+ * \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is
+ *          a problem initializing any hardware it returns an error code specific
+ *          to the hardware module that had a problem.
+ */
+cy_rslt_t cybsp_init(void);
+
+#if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+//--------------------------------------------------------------------------------------------------
+// cybsp_register_custom_sysclk_pm_callback
+//
+// Registers a power management callback that prepares the clock system for entering deep sleep mode
+// and restore the clocks upon wakeup from deep sleep. The application should implement this
+// function and define `CYBSP_CUSTOM_SYSCLK_PM_CALLBACK` if it needs to replace the default SysClk
+// DeepSleep callback behavior with application specific logic.
+// NOTE: This is called automatically as part of \ref cybsp_init
+//--------------------------------------------------------------------------------------------------
+cy_rslt_t cybsp_register_custom_sysclk_pm_callback(void);
+#endif // defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+
+/** \} group_bsp_functions */
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp_doc.h b/boot/cypress/platforms/BSP/PSOC6/cybsp_doc.h
new file mode 100644
index 0000000..1f9f0d6
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp_doc.h
@@ -0,0 +1,843 @@
+/***********************************************************************************************//**
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#if defined(CY_USING_HAL)
+#include "cyhal_pin_package.h"
+#endif
+/* CAT4 and CAT5 do not have configurators so the BSP defines pins in a non-generated header */
+#if defined(COMPONENT_CAT4) || defined(COMPONENT_CAT5)
+#include "cybsp_pins.h"
+#else
+#include "cycfg.h"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \addtogroup group_bsp_pins Pin Mappings
+ * \{
+ * Macro definitions for common peripheral pins on the board.
+ */
+
+#if defined(CYBSP_USER_LED)
+/**
+ * \addtogroup group_bsp_pins_led LED Pins
+ * \{
+ * Pins connected to user LEDs on the board.
+ */
+
+#ifdef CYBSP_LED_RGB_RED
+/** RGB LED - Red \def CYBSP_LED_RGB_RED
+ */
+#endif
+#ifdef CYBSP_LED_RGB_GREEN
+/** RGB LED - Green \def CYBSP_LED_RGB_GREEN
+ */
+#endif
+#ifdef CYBSP_LED_RGB_BLUE
+/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE
+ */
+#endif
+#ifdef CYBSP_USER_LED
+/** User LED \def CYBSP_USER_LED
+ */
+#endif
+#ifdef CYBSP_USER_LED1
+/** User LED1 \def CYBSP_USER_LED1
+ */
+#endif
+#ifdef CYBSP_USER_LED2
+/** User LED2 \def CYBSP_USER_LED2
+ */
+#endif
+#ifdef CYBSP_USER_LED3
+/** User LED3 \def CYBSP_USER_LED3
+ */
+#endif
+#ifdef CYBSP_USER_LED4
+/** User LED 4 \def CYBSP_USER_LED4
+ */
+#endif
+#ifdef CYBSP_USER_LED5
+/** User LED 5 \def CYBSP_USER_LED5
+ */
+#endif
+#ifdef CYBSP_USER_LED6
+/** User LED 6 \def CYBSP_USER_LED6
+ */
+#endif
+#ifdef CYBSP_USER_LED7
+/** User LED 7 \def CYBSP_USER_LED7
+ */
+#endif
+#ifdef CYBSP_USER_LED8
+/** User LED 8 \def CYBSP_USER_LED8
+ */
+#endif
+#ifdef CYBSP_USER_LED9
+/** User LED 9 \def CYBSP_USER_LED9
+ */
+#endif
+#ifdef CYBSP_USER_LED10
+/** User LED 10 \def CYBSP_USER_LED10
+ */
+#endif
+#ifdef CYBSP_LED1
+/** LED 1 \def CYBSP_LED1
+ */
+#endif
+#ifdef CYBSP_LED2
+/** LED 2 \def CYBSP_LED2
+ */
+#endif
+#ifdef CYBSP_LED3
+/** LED 3 \def CYBSP_LED3
+ */
+#endif
+#ifdef CYBSP_LED3_RGB_RED
+/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED
+ */
+#endif
+#ifdef CYBSP_LED3_RGB_GREEN
+/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN
+ */
+#endif
+#ifdef CYBSP_LED3_RGB_BLUE
+/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE
+ */
+#endif
+#ifdef CYBSP_LED4
+/** LED 4 \def CYBSP_LED4
+ */
+#endif
+#ifdef CYBSP_LED5
+/** LED 5 \def CYBSP_LED5
+ */
+#endif
+#ifdef CYBSP_LED6
+/** LED 6 \def CYBSP_LED6
+ */
+#endif
+#ifdef CYBSP_LED7
+/** LED 7 \def CYBSP_LED7
+ */
+#endif
+#ifdef CYBSP_LED8
+/** LED 8 \def CYBSP_LED8
+ */
+#endif
+#ifdef CYBSP_LED9
+/** LED 9 \def CYBSP_LED9
+ */
+#endif
+#ifdef CYBSP_LED10
+/** LED 10 \def CYBSP_LED10
+ */
+#endif
+#ifdef CYBSP_LED11
+/** LED 11 \def CYBSP_LED11
+ */
+#endif
+#ifdef CYBSP_LED12
+/** LED 12 \def CYBSP_LED12
+ */
+#endif
+#ifdef CYBSP_LED13
+/** LED 13 \def CYBSP_LED13
+ */
+#endif
+#ifdef CYBSP_LED_SLD0
+/** Slider LED 0 \def CYBSP_LED_SLD0
+ */
+#endif
+#ifdef CYBSP_LED_SLD1
+/** Slider LED 1 \def CYBSP_LED_SLD1
+ */
+#endif
+#ifdef CYBSP_LED_SLD2
+/** Slider LED 2 \def CYBSP_LED_SLD2
+ */
+#endif
+#ifdef CYBSP_LED_SLD3
+/** Slider LED 3 \def CYBSP_LED_SLD3
+ */
+#endif
+#ifdef CYBSP_LED_SLD4
+/** Slider LED 4 \def CYBSP_LED_SLD4
+ */
+#endif
+#ifdef CYBSP_LED_SLD5
+/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5
+ */
+#endif
+#ifdef CYBSP_LED_BTN0
+/** Button LED 0 \def CYBSP_LED_BTN0
+ */
+#endif
+#ifdef CYBSP_LED_BTN1
+/** Button LED 1 \def CYBSP_LED_BTN1
+ */
+#endif
+#ifdef CYBSP_LED_BTN2
+/** Button LED 2 \def CYBSP_LED_BTN2
+ */
+#endif
+
+/** \} group_bsp_pins_led */
+#endif // defined(CYBSP_USER_LED)
+
+#if defined(CYBSP_USER_BTN)
+/**
+ * \addtogroup group_bsp_pins_btn Button Pins
+ * \{
+ * Pins connected to user buttons on the board.
+ */
+
+#ifdef CYBSP_SW1
+/** Switch 1 \def CYBSP_SW1
+ */
+#endif
+#ifdef CYBSP_SW2
+/** Switch 2 \def CYBSP_SW2
+ */
+#endif
+#ifdef CYBSP_SW3
+/** Switch 3 \def CYBSP_SW3
+ */
+#endif
+#ifdef CYBSP_SW4
+/** Switch 4 \def CYBSP_SW4
+ */
+#endif
+#ifdef CYBSP_USER_BTN
+/** User Button 1 \def CYBSP_USER_BTN
+ */
+#endif
+#ifdef CYBSP_USER_BTN1
+/** User Button 1 \def CYBSP_USER_BTN1
+ */
+#endif
+#ifdef CYBSP_USER_BTN2
+/** User Button 2 \def CYBSP_USER_BTN2
+ */
+#endif
+#ifdef CYBSP_POTENTIOMETER_INPUT
+/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT
+ */
+#endif
+
+/** \} group_bsp_pins_btn */
+#endif // defined(CYBSP_USER_BTN)
+
+#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
+/**
+ * \addtogroup group_bsp_pins_comm Communication Pins
+ * \{
+ * Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...)
+ */
+
+#ifdef CYBSP_DEBUG_UART_RX
+/** Pin: UART RX \def CYBSP_DEBUG_UART_RX
+ */
+#endif
+#ifdef CYBSP_DEBUG_UART_TX
+/** Pin: UART TX \def CYBSP_DEBUG_UART_TX
+ */
+#endif
+#ifdef CYBSP_I2C_SCL
+/** Pin: I2C SCL \def CYBSP_I2C_SCL
+ */
+#endif
+#ifdef CYBSP_I2C_SDA
+/** Pin: I2C SDA \def CYBSP_I2C_SDA
+ */
+#endif
+#ifdef CYBSP_SWDIO
+/** Pin: SWDIO \def CYBSP_SWDIO
+ */
+#endif
+#ifdef CYBSP_SWDCK
+/** Pin: SWDCK \def CYBSP_SWDCK
+ */
+#endif
+#ifdef CYBSP_SPI_MOSI
+/** Pin: SPI MOSI \def CYBSP_SPI_MOSI
+ */
+#endif
+#ifdef CYBSP_SPI_MISO
+/** Pin: SPI MISO \def CYBSP_SPI_MISO
+ */
+#endif
+#ifdef CYBSP_SPI_CLK
+/** Pin: SPI CLK \def CYBSP_SPI_CLK
+ */
+#endif
+#ifdef CYBSP_SPI_CS
+/** Pin: SPI CS \def CYBSP_SPI_CS
+ */
+#endif
+#ifdef CYBSP_SWO
+/** Pin: SWO \def CYBSP_SWO
+ */
+#endif
+#ifdef CYBSP_QSPI_SS
+/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS
+ */
+#endif
+#ifdef CYBSP_QSPI_D3
+/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3
+ */
+#endif
+#ifdef CYBSP_QSPI_D2
+/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2
+ */
+#endif
+#ifdef CYBSP_QSPI_D1
+/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1
+ */
+#endif
+#ifdef CYBSP_QSPI_D0
+/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0
+ */
+#endif
+#ifdef CYBSP_QSPI_SCK
+/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D0
+/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D1
+/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D2
+/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D3
+/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_CMD
+/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_CLK
+/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK
+ */
+#endif
+#ifdef CYBSP_WIFI_WL_REG_ON
+/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON
+ */
+#endif
+#ifdef CYBSP_WIFI_HOST_WAKE
+/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE
+ */
+
+/** WiFi host-wake GPIO drive mode */
+#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
+/** WiFi host-wake IRQ event */
+#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
+#endif
+#ifdef CYBSP_BT_UART_RX
+/** Pin: BT UART RX \def CYBSP_BT_UART_RX
+ */
+#endif
+#ifdef CYBSP_BT_UART_TX
+/** Pin: BT UART TX \def CYBSP_BT_UART_TX
+ */
+#endif
+#ifdef CYBSP_BT_UART_RTS
+/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS
+ */
+#endif
+#ifdef CYBSP_BT_UART_CTS
+/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS
+ */
+#endif
+#ifdef CYBSP_BT_POWER
+/** Pin: BT Power \def CYBSP_BT_POWER
+ */
+#endif
+#ifdef CYBSP_BT_HOST_WAKE
+/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE
+ */
+/** BT host-wake GPIO drive mode */
+#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE)
+/** BT host wake IRQ event */
+#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL)
+#endif
+#ifdef CYBSP_BT_DEVICE_WAKE
+/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE
+ */
+/** BT device wakeup GPIO drive mode */
+#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG)
+/** BT device wakeup polarity */
+#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u)
+#endif
+#ifdef CYBSP_PDM_CLK
+/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK
+ */
+#endif
+#ifdef CYBSP_PDM_DATA
+/** Pin PDM PCM DATA \def CYBSP_PDM_DATA
+ */
+#endif
+#ifdef CYBSP_I2S_MCLK
+/** Pin: I2S MCLK \def CYBSP_I2S_MCLK
+ */
+#endif
+#ifdef CYBSP_I2S_TX_SCK
+/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK
+ */
+#endif
+#ifdef CYBSP_I2S_TX_WS
+/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS
+ */
+#endif
+#ifdef CYBSP_I2S_TX_DATA
+/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA
+ */
+#endif
+#ifdef CYBSP_I2S_RX_SCK
+/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK
+ */
+#endif
+#ifdef CYBSP_I2S_RX_WS
+/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS
+ */
+#endif
+#ifdef CYBSP_I2S_RX_DATA
+/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA
+ */
+#endif
+#ifdef CYBSP_DEBUG_UART_RTS
+/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS
+ */
+#endif
+#ifdef CYBSP_DEBUG_UART_CTS
+/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS
+ */
+#endif
+#ifdef CYBSP_UART_RX
+/** Pin: UART RX \def CYBSP_UART_RX
+ */
+#endif
+#ifdef CYBSP_UART_TX
+/** Pin: UART TX \def CYBSP_UART_TX
+ */
+#endif
+#ifdef CYBSP_TDO_SWO
+/** Pin: \def CYBSP_TDO_SWO
+ */
+#endif
+#ifdef CYBSP_TMS_SWDIO
+/** Pin: \def CYBSP_TMS_SWDIO
+ */
+#endif
+#ifdef CYBSP_SWCLK
+/** Pin: \def CYBSP_SWCLK
+ */
+#endif
+
+/** \} group_bsp_pins_comm */
+#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
+
+#if defined(CYBSP_A0)
+/**
+ * \addtogroup group_bsp_pins_arduino Arduino Header Pins
+ * \{
+ * Pins mapped to the Arduino header on the board.
+ */
+
+#ifdef CYBSP_A0
+/** Arduino A0 \def CYBSP_A0
+ */
+#endif
+#ifdef CYBSP_A1
+/** Arduino A1 \def CYBSP_A1
+ */
+#endif
+#ifdef CYBSP_A2
+/** Arduino A2 \def CYBSP_A2
+ */
+#endif
+#ifdef CYBSP_A3
+/** Arduino A3 \def CYBSP_A3
+ */
+#endif
+#ifdef CYBSP_A4
+/** Arduino A4 \def CYBSP_A4
+ */
+#endif
+#ifdef CYBSP_A5
+/** Arduino A5 \def CYBSP_A5
+ */
+#endif
+#ifdef CYBSP_D0
+/** Arduino D0 \def CYBSP_D0
+ */
+#endif
+#ifdef CYBSP_D1
+/** Arduino D1 \def CYBSP_D1
+ */
+#endif
+#ifdef CYBSP_D2
+/** Arduino D2 \def CYBSP_D2
+ */
+#endif
+#ifdef CYBSP_D3
+/** Arduino D3 \def CYBSP_D3
+ */
+#endif
+#ifdef CYBSP_D4
+/** Arduino D4 \def CYBSP_D4
+ */
+#endif
+#ifdef CYBSP_D5
+/** Arduino D5 \def CYBSP_D5
+ */
+#endif
+#ifdef CYBSP_D6
+/** Arduino D6 \def CYBSP_D6
+ */
+#endif
+#ifdef CYBSP_D7
+/** Arduino D7 \def CYBSP_D7
+ */
+#endif
+#ifdef CYBSP_D8
+/** Arduino D8 \def CYBSP_D8
+ */
+#endif
+#ifdef CYBSP_D9
+/** Arduino D9 \def CYBSP_D9
+ */
+#endif
+#ifdef CYBSP_D10
+/** Arduino D10 \def CYBSP_D10
+ */
+#endif
+#ifdef CYBSP_D11
+/** Arduino D11 \def CYBSP_D11
+ */
+#endif
+#ifdef CYBSP_D12
+/** Arduino D12 \def CYBSP_D12
+ */
+#endif
+#ifdef CYBSP_D13
+/** Arduino D13 \def CYBSP_D13
+ */
+#endif
+#ifdef CYBSP_D14
+/** Arduino D14 \def CYBSP_D14
+ */
+#endif
+#ifdef CYBSP_D15
+/** Arduino D15 \def CYBSP_D15
+ */
+#endif
+
+/** \} group_bsp_pins_arduino */
+#endif // defined(CYBSP_A0)
+
+#if defined(CYBSP_J2_1)
+/**
+ * \addtogroup group_bsp_pins_j2 J2 Header Pins
+ * \{
+ * Pins mapped to the J2 header on the board.
+ */
+
+#ifdef CYBSP_J2_1
+/** Infineon J2 Header pin 1 \def CYBSP_J2_1
+ */
+#endif
+#ifdef CYBSP_J2_2
+/** Infineon J2 Header pin 2 \def CYBSP_J2_2
+ */
+#endif
+#ifdef CYBSP_J2_3
+/** Infineon J2 Header pin 3 \def CYBSP_J2_3
+ */
+#endif
+#ifdef CYBSP_J2_4
+/** Infineon J2 Header pin 4 \def CYBSP_J2_4
+ */
+#endif
+#ifdef CYBSP_J2_5
+/** Infineon J2 Header pin 5 \def CYBSP_J2_5
+ */
+#endif
+#ifdef CYBSP_J2_7
+/** Infineon J2 Header pin 7 \def CYBSP_J2_7
+ */
+#endif
+#ifdef CYBSP_J2_8
+/** Infineon J2 Header pin 8 \def CYBSP_J2_8
+ */
+#endif
+#ifdef CYBSP_J2_9
+/** Infineon J2 Header pin 9 \def CYBSP_J2_9
+ */
+#endif
+#ifdef CYBSP_J2_10
+/** Infineon J2 Header pin 10 \def CYBSP_J2_10
+ */
+#endif
+#ifdef CYBSP_J2_11
+/** Infineon J2 Header pin 11 \def CYBSP_J2_11
+ */
+#endif
+#ifdef CYBSP_J2_12
+/** Infineon J2 Header pin 12 \def CYBSP_J2_12
+ */
+#endif
+#ifdef CYBSP_J2_13
+/** Infineon J2 Header pin 13 \def CYBSP_J2_13
+ */
+#endif
+#ifdef CYBSP_J2_15
+/** Infineon J2 Header pin 15 \def CYBSP_J2_15
+ */
+#endif
+#ifdef CYBSP_J2_16
+/** Infineon J2 Header pin 16 \def CYBSP_J2_16
+ */
+#endif
+#ifdef CYBSP_J2_16
+/** Infineon J2 Header pin 16 \def CYBSP_J2_16
+ */
+#endif
+#ifdef CYBSP_J2_6
+/** Infineon J2 Header pin 6 \def CYBSP_J2_6
+ */
+#endif
+#ifdef CYBSP_J2_17
+/** Infineon J2 Header pin 17 \def CYBSP_J2_17
+ */
+#endif
+#ifdef CYBSP_J2_18
+/** Infineon J2 Header pin 18 \def CYBSP_J2_18
+ */
+#endif
+#ifdef CYBSP_J2_19
+/** Infineon J2 Header pin 19 \def CYBSP_J2_19
+ */
+#endif
+#ifdef CYBSP_J2_20
+/** Infineon J2 Header pin 20 \def CYBSP_J2_20
+ */
+#endif
+#ifdef CYBSP_J2_14
+/** Infineon J2 Header pin 14 \def CYBSP_J2_14
+ */
+#endif
+
+/** \} group_bsp_pins_j2 */
+#endif // defined(CYBSP_J2_1)
+
+#if defined(CYBSP_J6_1)
+/**
+ * \addtogroup group_bsp_pins_j6 J6 Header Pins
+ * \{
+ * Pins mapped to the J6 header on the board.
+ */
+
+#ifdef CYBSP_J6_1
+/** Infineon J6 Header pin 1 \def CYBSP_J6_1
+ */
+#endif
+#ifdef CYBSP_J6_2
+/** Infineon J6 Header pin 2 \def CYBSP_J6_2
+ */
+#endif
+#ifdef CYBSP_J6_3
+/** Infineon J6 Header pin 3 \def CYBSP_J6_3
+ */
+#endif
+#ifdef CYBSP_J6_4
+/** Infineon J6 Header pin 4 \def CYBSP_J6_4
+ */
+#endif
+#ifdef CYBSP_J6_5
+/** Infineon J6 Header pin 5 \def CYBSP_J6_5
+ */
+#endif
+#ifdef CYBSP_J6_6
+/** Infineon J6 Header pin 6 \def CYBSP_J6_6
+ */
+#endif
+#ifdef CYBSP_J6_7
+/** Infineon J6 Header pin 7 \def CYBSP_J6_7
+ */
+#endif
+#ifdef CYBSP_J6_8
+/** Infineon J6 Header pin 8 \def CYBSP_J6_8
+ */
+#endif
+#ifdef CYBSP_J6_9
+/** Infineon J6 Header pin 9 \def CYBSP_J6_9
+ */
+#endif
+#ifdef CYBSP_J6_10
+/** Infineon J6 Header pin 10 \def CYBSP_J6_10
+ */
+#endif
+#ifdef CYBSP_J6_11
+/** Infineon J6 Header pin 11 \def CYBSP_J6_11
+ */
+#endif
+#ifdef CYBSP_J6_12
+/** Infineon J6 Header pin 12 \def CYBSP_J6_12
+ */
+#endif
+#ifdef CYBSP_J6_13
+/** Infineon J6 Header pin 13 \def CYBSP_J6_13
+ */
+#endif
+#ifdef CYBSP_J6_14
+/** Infineon J6 Header pin 14 \def CYBSP_J6_14
+ */
+#endif
+#ifdef CYBSP_J6_15
+/** Infineon J6 Header pin 15 \def CYBSP_J6_15
+ */
+#endif
+#ifdef CYBSP_J6_16
+/** Infineon J6 Header pin 16 \def CYBSP_J6_16
+ */
+#endif
+
+/** \} group_bsp_pins_j6 */
+#endif // defined(CYBSP_J6_1)
+
+#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
+/**
+ * \addtogroup group_bsp_pins_capsense Capsense
+ * \{
+ * Pins connected to CAPSENSE™ sensors on the board.
+ */
+
+#ifdef CYBSP_CSD_TX
+/** Pin: CapSesnse TX \def CYBSP_CSD_TX
+ */
+#endif
+#ifdef CYBSP_CINA
+/** Pin: CapSesnse CINA \def CYBSP_CINA
+ */
+#endif
+#ifdef CYBSP_CINTA
+/** Pin: CapSesnse CINTA \def CYBSP_CINTA
+ */
+#endif
+#ifdef CYBSP_CINB
+/** Pin: CapSesnse CINB \def CYBSP_CINB
+ */
+#endif
+#ifdef CYBSP_CINTB
+/** Pin: CapSesnse CINTB \def CYBSP_CINTB
+ */
+#endif
+#ifdef CYBSP_CMOD
+/** Pin: CapSesnse CMOD \def CYBSP_CMOD
+ */
+#endif
+#ifdef CYBSP_CSD_BTN0
+/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0
+ */
+#endif
+#ifdef CYBSP_CSD_BTN1
+/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1
+ */
+#endif
+#ifdef CYBSP_CSD_SLD0
+/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0
+ */
+#endif
+#ifdef CYBSP_CSD_SLD1
+/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1
+ */
+#endif
+#ifdef CYBSP_CSD_SLD2
+/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2
+ */
+#endif
+#ifdef CYBSP_CSD_SLD3
+/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3
+ */
+#endif
+#ifdef CYBSP_CSD_SLD4
+/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4
+ */
+#endif
+#ifdef CYBSP_CSD_SLD5
+/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5
+ */
+#endif
+#ifdef CYBSP_CSX_BTN_TX
+/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX
+ */
+#endif
+#ifdef CYBSP_CSX_BTN0
+/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0
+ */
+#endif
+#ifdef CYBSP_CSX_BTN1
+/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1
+ */
+#endif
+#ifdef CYBSP_CSX_BTN2
+/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2
+ */
+#endif
+
+/** \} group_bsp_pins_capsense */
+#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
+
+#if defined(CYBSP_WCO_IN)
+/**
+ * \addtogroup group_bsp_pins_wco WCO
+ * \{
+ * Pins connected to the WCO on the board.
+ */
+#ifdef CYBSP_WCO_IN
+/** Pin: WCO input \def CYBSP_WCO_IN
+ */
+#endif
+#ifdef CYBSP_WCO_OUT
+/** Pin: WCO output \def CYBSP_WCO_OUT
+ */
+#endif
+
+/** \} group_bsp_pins_wco */
+#endif // defined(CYBSP_WCO_IN)
+
+/** \} group_bsp_pins */
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp_hw_config.h b/boot/cypress/platforms/BSP/PSOC6/cybsp_hw_config.h
new file mode 100644
index 0000000..580d49c
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp_hw_config.h
@@ -0,0 +1,42 @@
+/***********************************************************************************************//**
+ * \file cybsp_hw_config.h
+ *
+ * \brief
+ * Basic API for handling defaults for hardware so code examples behave the same across different
+ * devices.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+#pragma once
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#ifndef CYBSP_USER_BTN_DRIVE
+#define CYBSP_USER_BTN_DRIVE          (CYHAL_GPIO_DRIVE_PULLUP)
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp_types.h b/boot/cypress/platforms/BSP/PSOC6/cybsp_types.h
new file mode 100644
index 0000000..aeb7023
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp_types.h
@@ -0,0 +1,73 @@
+/***********************************************************************************************//**
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#include "cybsp_doc.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \cond INTERNAL
+ */
+/* WIFI interface types */
+#define CYBSP_SDIO_INTERFACE             (0)
+#define CYBSP_SPI_INTERFACE              (1)
+#define CYBSP_M2M_INTERFACE              (2)
+
+/* Map from the new components to the old interface names for
+ * compatibility with code that still depends on those defines */
+#if defined(COMPONENT_WIFI_INTERFACE_SDIO)
+#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SDIO_INTERFACE)
+#elif defined(COMPONENT_WIFI_INTERFACE_SPI)
+#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SPI_INTERFACE)
+#elif defined(COMPONENT_WIFI_INTERFACE_M2M)
+#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_M2M_INTERFACE)
+#endif
+/** \endcond */
+
+/**
+ * \addtogroup group_bsp_pin_state Pin States
+ * \{
+ * Macros to abstract out whether the LEDs & Buttons are wired high or active low.
+ */
+/** Pin state for the LED on. */
+#ifndef CYBSP_LED_STATE_ON
+#define CYBSP_LED_STATE_ON          (0U)
+#endif
+/** Pin state for the LED off. */
+#ifndef CYBSP_LED_STATE_OFF
+#define CYBSP_LED_STATE_OFF         (1U)
+#endif
+/** Pin state for when a button is pressed. */
+#ifndef CYBSP_BTN_PRESSED
+#define CYBSP_BTN_PRESSED           (0U)
+#endif
+/** Pin state for when a button is released. */
+#ifndef CYBSP_BTN_OFF
+#define CYBSP_BTN_OFF               (1U)
+#endif
+/** \} group_bsp_pin_state */
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/XMC7000/CAT1C_SMIF.FLM b/boot/cypress/platforms/BSP/XMC7000/CAT1C_SMIF.FLM
new file mode 100644
index 0000000..1153f5d
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/CAT1C_SMIF.FLM
Binary files differ
diff --git a/boot/cypress/platforms/BSP/XMC7000/FlashCAT1C_SMIF.out b/boot/cypress/platforms/BSP/XMC7000/FlashCAT1C_SMIF.out
new file mode 100644
index 0000000..c16bb08
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/FlashCAT1C_SMIF.out
Binary files differ
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp.c b/boot/cypress/platforms/BSP/XMC7000/cybsp.c
new file mode 100644
index 0000000..00c25fd
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp.c
@@ -0,0 +1,138 @@
+/***************************************************************************//**
+* \file cybsp.c
+*
+* Description:
+* Provides initialization code for starting up the hardware contained on the
+* Infineon board.
+*
+********************************************************************************
+* \copyright
+* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdlib.h>
+#include "cy_syspm.h"
+#include "cy_sysclk.h"
+#include "cybsp.h"
+#if defined(CY_USING_HAL)
+#include "cyhal_hwmgr.h"
+#include "cyhal_syspm.h"
+#endif
+#if defined(COMPONENT_MW_CAT1CM0P)
+    #include "mtb_cat1cm0p.h"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// The sysclk deep sleep callback is recommended to be the last callback that is executed before
+// entry into deep sleep mode and the first one upon exit the deep sleep mode.
+// Doing so minimizes the time spent on low power mode entry and exit.
+#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
+    #define CYBSP_SYSCLK_PM_CALLBACK_ORDER  (255u)
+#endif
+
+#if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+//--------------------------------------------------------------------------------------------------
+// cybsp_register_sysclk_pm_callback
+//
+// Registers a power management callback that prepares the clock system for entering deep sleep mode
+// and restore the clocks upon wakeup from deep sleep.
+// NOTE: This is called automatically as part of \ref cybsp_init
+//--------------------------------------------------------------------------------------------------
+static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
+{
+    cy_rslt_t                             result                         = CY_RSLT_SUCCESS;
+    static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL };
+    static cy_stc_syspm_callback_t        cybsp_sysclk_pm_callback       =
+    {
+        .callback       = &Cy_SysClk_DeepSleepCallback,
+        .type           = CY_SYSPM_DEEPSLEEP,
+        .callbackParams = &cybsp_sysclk_pm_callback_param,
+        .order          = CYBSP_SYSCLK_PM_CALLBACK_ORDER
+    };
+
+    if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
+    {
+        result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
+    }
+    return result;
+}
+
+
+#endif // if !defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+
+
+//--------------------------------------------------------------------------------------------------
+// cybsp_init
+//--------------------------------------------------------------------------------------------------
+cy_rslt_t cybsp_init(void)
+{
+    // Setup hardware manager to track resource usage then initialize all system (clock/power) board
+    // configuration
+    #if defined(CY_USING_HAL)
+    cy_rslt_t result = cyhal_hwmgr_init();
+
+    if (CY_RSLT_SUCCESS == result)
+    {
+        result = cyhal_syspm_init();
+    }
+
+    #ifdef CY_CFG_PWR_VDDA_MV
+    if (CY_RSLT_SUCCESS == result)
+    {
+        cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
+    }
+    #endif
+
+    #else // if defined(CY_USING_HAL)
+    cy_rslt_t result = CY_RSLT_SUCCESS;
+    #endif // if defined(CY_USING_HAL)
+
+    // By default, the peripheral configuration will be done on the first core running user code.
+    // This is the CM0+ if it is available and not running a pre-built image, and the CM7 otherwise.
+    // This is done to ensure configuration is available for all cores that might need to use it.
+    // In the case of a dual core project, this can be changed below to perform initialization on
+    // the CM7 if necessary.
+    #if defined(CORE_NAME_CM0P_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM7_0) && \
+    defined(CY_USING_PREBUILT_CM0P_IMAGE))
+    cycfg_config_init();
+    #endif
+
+    cycfg_config_reservations();
+
+    if (CY_RSLT_SUCCESS == result)
+    {
+        #if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+        result = cybsp_register_custom_sysclk_pm_callback();
+        #else
+        result = cybsp_register_sysclk_pm_callback();
+        #endif
+    }
+
+    // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was
+    // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP
+    // reservation list (cyreservedresources.list) to make sure no resources are reserved by both.
+    return result;
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp.h b/boot/cypress/platforms/BSP/XMC7000/cybsp.h
new file mode 100644
index 0000000..cd27cf6
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp.h
@@ -0,0 +1,83 @@
+/***********************************************************************************************//**
+ * \file cybsp.h
+ *
+ * \brief
+ * Basic API for setting up boards containing a Cypress MCU.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+#include "cybsp_hw_config.h"
+#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE)
+#include "cybsp_bt_config.h"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \addtogroup group_bsp_errors Error Codes
+ * \{
+ * Error codes specific to the board.
+ */
+
+/** Failed to configure sysclk power management callback */
+#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK  \
+    (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
+
+/** \} group_bsp_errors */
+
+/**
+ * \addtogroup group_bsp_functions Functions
+ * \{
+ * All functions exposed by the board.
+ */
+
+/**
+ * \brief Initialize all hardware on the board
+ * \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is
+ *          a problem initializing any hardware it returns an error code specific
+ *          to the hardware module that had a problem.
+ */
+cy_rslt_t cybsp_init(void);
+
+#if defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+//--------------------------------------------------------------------------------------------------
+// cybsp_register_custom_sysclk_pm_callback
+//
+// Registers a power management callback that prepares the clock system for entering deep sleep mode
+// and restore the clocks upon wakeup from deep sleep. The application should implement this
+// function and define `CYBSP_CUSTOM_SYSCLK_PM_CALLBACK` if it needs to replace the default SysClk
+// DeepSleep callback behavior with application specific logic.
+// NOTE: This is called automatically as part of \ref cybsp_init
+//--------------------------------------------------------------------------------------------------
+cy_rslt_t cybsp_register_custom_sysclk_pm_callback(void);
+#endif // defined(CYBSP_CUSTOM_SYSCLK_PM_CALLBACK)
+
+/** \} group_bsp_functions */
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h b/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
new file mode 100644
index 0000000..1f9f0d6
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
@@ -0,0 +1,843 @@
+/***********************************************************************************************//**
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#if defined(CY_USING_HAL)
+#include "cyhal_pin_package.h"
+#endif
+/* CAT4 and CAT5 do not have configurators so the BSP defines pins in a non-generated header */
+#if defined(COMPONENT_CAT4) || defined(COMPONENT_CAT5)
+#include "cybsp_pins.h"
+#else
+#include "cycfg.h"
+#endif
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \addtogroup group_bsp_pins Pin Mappings
+ * \{
+ * Macro definitions for common peripheral pins on the board.
+ */
+
+#if defined(CYBSP_USER_LED)
+/**
+ * \addtogroup group_bsp_pins_led LED Pins
+ * \{
+ * Pins connected to user LEDs on the board.
+ */
+
+#ifdef CYBSP_LED_RGB_RED
+/** RGB LED - Red \def CYBSP_LED_RGB_RED
+ */
+#endif
+#ifdef CYBSP_LED_RGB_GREEN
+/** RGB LED - Green \def CYBSP_LED_RGB_GREEN
+ */
+#endif
+#ifdef CYBSP_LED_RGB_BLUE
+/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE
+ */
+#endif
+#ifdef CYBSP_USER_LED
+/** User LED \def CYBSP_USER_LED
+ */
+#endif
+#ifdef CYBSP_USER_LED1
+/** User LED1 \def CYBSP_USER_LED1
+ */
+#endif
+#ifdef CYBSP_USER_LED2
+/** User LED2 \def CYBSP_USER_LED2
+ */
+#endif
+#ifdef CYBSP_USER_LED3
+/** User LED3 \def CYBSP_USER_LED3
+ */
+#endif
+#ifdef CYBSP_USER_LED4
+/** User LED 4 \def CYBSP_USER_LED4
+ */
+#endif
+#ifdef CYBSP_USER_LED5
+/** User LED 5 \def CYBSP_USER_LED5
+ */
+#endif
+#ifdef CYBSP_USER_LED6
+/** User LED 6 \def CYBSP_USER_LED6
+ */
+#endif
+#ifdef CYBSP_USER_LED7
+/** User LED 7 \def CYBSP_USER_LED7
+ */
+#endif
+#ifdef CYBSP_USER_LED8
+/** User LED 8 \def CYBSP_USER_LED8
+ */
+#endif
+#ifdef CYBSP_USER_LED9
+/** User LED 9 \def CYBSP_USER_LED9
+ */
+#endif
+#ifdef CYBSP_USER_LED10
+/** User LED 10 \def CYBSP_USER_LED10
+ */
+#endif
+#ifdef CYBSP_LED1
+/** LED 1 \def CYBSP_LED1
+ */
+#endif
+#ifdef CYBSP_LED2
+/** LED 2 \def CYBSP_LED2
+ */
+#endif
+#ifdef CYBSP_LED3
+/** LED 3 \def CYBSP_LED3
+ */
+#endif
+#ifdef CYBSP_LED3_RGB_RED
+/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED
+ */
+#endif
+#ifdef CYBSP_LED3_RGB_GREEN
+/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN
+ */
+#endif
+#ifdef CYBSP_LED3_RGB_BLUE
+/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE
+ */
+#endif
+#ifdef CYBSP_LED4
+/** LED 4 \def CYBSP_LED4
+ */
+#endif
+#ifdef CYBSP_LED5
+/** LED 5 \def CYBSP_LED5
+ */
+#endif
+#ifdef CYBSP_LED6
+/** LED 6 \def CYBSP_LED6
+ */
+#endif
+#ifdef CYBSP_LED7
+/** LED 7 \def CYBSP_LED7
+ */
+#endif
+#ifdef CYBSP_LED8
+/** LED 8 \def CYBSP_LED8
+ */
+#endif
+#ifdef CYBSP_LED9
+/** LED 9 \def CYBSP_LED9
+ */
+#endif
+#ifdef CYBSP_LED10
+/** LED 10 \def CYBSP_LED10
+ */
+#endif
+#ifdef CYBSP_LED11
+/** LED 11 \def CYBSP_LED11
+ */
+#endif
+#ifdef CYBSP_LED12
+/** LED 12 \def CYBSP_LED12
+ */
+#endif
+#ifdef CYBSP_LED13
+/** LED 13 \def CYBSP_LED13
+ */
+#endif
+#ifdef CYBSP_LED_SLD0
+/** Slider LED 0 \def CYBSP_LED_SLD0
+ */
+#endif
+#ifdef CYBSP_LED_SLD1
+/** Slider LED 1 \def CYBSP_LED_SLD1
+ */
+#endif
+#ifdef CYBSP_LED_SLD2
+/** Slider LED 2 \def CYBSP_LED_SLD2
+ */
+#endif
+#ifdef CYBSP_LED_SLD3
+/** Slider LED 3 \def CYBSP_LED_SLD3
+ */
+#endif
+#ifdef CYBSP_LED_SLD4
+/** Slider LED 4 \def CYBSP_LED_SLD4
+ */
+#endif
+#ifdef CYBSP_LED_SLD5
+/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5
+ */
+#endif
+#ifdef CYBSP_LED_BTN0
+/** Button LED 0 \def CYBSP_LED_BTN0
+ */
+#endif
+#ifdef CYBSP_LED_BTN1
+/** Button LED 1 \def CYBSP_LED_BTN1
+ */
+#endif
+#ifdef CYBSP_LED_BTN2
+/** Button LED 2 \def CYBSP_LED_BTN2
+ */
+#endif
+
+/** \} group_bsp_pins_led */
+#endif // defined(CYBSP_USER_LED)
+
+#if defined(CYBSP_USER_BTN)
+/**
+ * \addtogroup group_bsp_pins_btn Button Pins
+ * \{
+ * Pins connected to user buttons on the board.
+ */
+
+#ifdef CYBSP_SW1
+/** Switch 1 \def CYBSP_SW1
+ */
+#endif
+#ifdef CYBSP_SW2
+/** Switch 2 \def CYBSP_SW2
+ */
+#endif
+#ifdef CYBSP_SW3
+/** Switch 3 \def CYBSP_SW3
+ */
+#endif
+#ifdef CYBSP_SW4
+/** Switch 4 \def CYBSP_SW4
+ */
+#endif
+#ifdef CYBSP_USER_BTN
+/** User Button 1 \def CYBSP_USER_BTN
+ */
+#endif
+#ifdef CYBSP_USER_BTN1
+/** User Button 1 \def CYBSP_USER_BTN1
+ */
+#endif
+#ifdef CYBSP_USER_BTN2
+/** User Button 2 \def CYBSP_USER_BTN2
+ */
+#endif
+#ifdef CYBSP_POTENTIOMETER_INPUT
+/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT
+ */
+#endif
+
+/** \} group_bsp_pins_btn */
+#endif // defined(CYBSP_USER_BTN)
+
+#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
+/**
+ * \addtogroup group_bsp_pins_comm Communication Pins
+ * \{
+ * Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...)
+ */
+
+#ifdef CYBSP_DEBUG_UART_RX
+/** Pin: UART RX \def CYBSP_DEBUG_UART_RX
+ */
+#endif
+#ifdef CYBSP_DEBUG_UART_TX
+/** Pin: UART TX \def CYBSP_DEBUG_UART_TX
+ */
+#endif
+#ifdef CYBSP_I2C_SCL
+/** Pin: I2C SCL \def CYBSP_I2C_SCL
+ */
+#endif
+#ifdef CYBSP_I2C_SDA
+/** Pin: I2C SDA \def CYBSP_I2C_SDA
+ */
+#endif
+#ifdef CYBSP_SWDIO
+/** Pin: SWDIO \def CYBSP_SWDIO
+ */
+#endif
+#ifdef CYBSP_SWDCK
+/** Pin: SWDCK \def CYBSP_SWDCK
+ */
+#endif
+#ifdef CYBSP_SPI_MOSI
+/** Pin: SPI MOSI \def CYBSP_SPI_MOSI
+ */
+#endif
+#ifdef CYBSP_SPI_MISO
+/** Pin: SPI MISO \def CYBSP_SPI_MISO
+ */
+#endif
+#ifdef CYBSP_SPI_CLK
+/** Pin: SPI CLK \def CYBSP_SPI_CLK
+ */
+#endif
+#ifdef CYBSP_SPI_CS
+/** Pin: SPI CS \def CYBSP_SPI_CS
+ */
+#endif
+#ifdef CYBSP_SWO
+/** Pin: SWO \def CYBSP_SWO
+ */
+#endif
+#ifdef CYBSP_QSPI_SS
+/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS
+ */
+#endif
+#ifdef CYBSP_QSPI_D3
+/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3
+ */
+#endif
+#ifdef CYBSP_QSPI_D2
+/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2
+ */
+#endif
+#ifdef CYBSP_QSPI_D1
+/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1
+ */
+#endif
+#ifdef CYBSP_QSPI_D0
+/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0
+ */
+#endif
+#ifdef CYBSP_QSPI_SCK
+/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D0
+/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D1
+/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D2
+/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_D3
+/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_CMD
+/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD
+ */
+#endif
+#ifdef CYBSP_WIFI_SDIO_CLK
+/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK
+ */
+#endif
+#ifdef CYBSP_WIFI_WL_REG_ON
+/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON
+ */
+#endif
+#ifdef CYBSP_WIFI_HOST_WAKE
+/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE
+ */
+
+/** WiFi host-wake GPIO drive mode */
+#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
+/** WiFi host-wake IRQ event */
+#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
+#endif
+#ifdef CYBSP_BT_UART_RX
+/** Pin: BT UART RX \def CYBSP_BT_UART_RX
+ */
+#endif
+#ifdef CYBSP_BT_UART_TX
+/** Pin: BT UART TX \def CYBSP_BT_UART_TX
+ */
+#endif
+#ifdef CYBSP_BT_UART_RTS
+/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS
+ */
+#endif
+#ifdef CYBSP_BT_UART_CTS
+/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS
+ */
+#endif
+#ifdef CYBSP_BT_POWER
+/** Pin: BT Power \def CYBSP_BT_POWER
+ */
+#endif
+#ifdef CYBSP_BT_HOST_WAKE
+/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE
+ */
+/** BT host-wake GPIO drive mode */
+#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE)
+/** BT host wake IRQ event */
+#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL)
+#endif
+#ifdef CYBSP_BT_DEVICE_WAKE
+/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE
+ */
+/** BT device wakeup GPIO drive mode */
+#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG)
+/** BT device wakeup polarity */
+#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u)
+#endif
+#ifdef CYBSP_PDM_CLK
+/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK
+ */
+#endif
+#ifdef CYBSP_PDM_DATA
+/** Pin PDM PCM DATA \def CYBSP_PDM_DATA
+ */
+#endif
+#ifdef CYBSP_I2S_MCLK
+/** Pin: I2S MCLK \def CYBSP_I2S_MCLK
+ */
+#endif
+#ifdef CYBSP_I2S_TX_SCK
+/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK
+ */
+#endif
+#ifdef CYBSP_I2S_TX_WS
+/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS
+ */
+#endif
+#ifdef CYBSP_I2S_TX_DATA
+/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA
+ */
+#endif
+#ifdef CYBSP_I2S_RX_SCK
+/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK
+ */
+#endif
+#ifdef CYBSP_I2S_RX_WS
+/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS
+ */
+#endif
+#ifdef CYBSP_I2S_RX_DATA
+/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA
+ */
+#endif
+#ifdef CYBSP_DEBUG_UART_RTS
+/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS
+ */
+#endif
+#ifdef CYBSP_DEBUG_UART_CTS
+/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS
+ */
+#endif
+#ifdef CYBSP_UART_RX
+/** Pin: UART RX \def CYBSP_UART_RX
+ */
+#endif
+#ifdef CYBSP_UART_TX
+/** Pin: UART TX \def CYBSP_UART_TX
+ */
+#endif
+#ifdef CYBSP_TDO_SWO
+/** Pin: \def CYBSP_TDO_SWO
+ */
+#endif
+#ifdef CYBSP_TMS_SWDIO
+/** Pin: \def CYBSP_TMS_SWDIO
+ */
+#endif
+#ifdef CYBSP_SWCLK
+/** Pin: \def CYBSP_SWCLK
+ */
+#endif
+
+/** \} group_bsp_pins_comm */
+#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO)
+
+#if defined(CYBSP_A0)
+/**
+ * \addtogroup group_bsp_pins_arduino Arduino Header Pins
+ * \{
+ * Pins mapped to the Arduino header on the board.
+ */
+
+#ifdef CYBSP_A0
+/** Arduino A0 \def CYBSP_A0
+ */
+#endif
+#ifdef CYBSP_A1
+/** Arduino A1 \def CYBSP_A1
+ */
+#endif
+#ifdef CYBSP_A2
+/** Arduino A2 \def CYBSP_A2
+ */
+#endif
+#ifdef CYBSP_A3
+/** Arduino A3 \def CYBSP_A3
+ */
+#endif
+#ifdef CYBSP_A4
+/** Arduino A4 \def CYBSP_A4
+ */
+#endif
+#ifdef CYBSP_A5
+/** Arduino A5 \def CYBSP_A5
+ */
+#endif
+#ifdef CYBSP_D0
+/** Arduino D0 \def CYBSP_D0
+ */
+#endif
+#ifdef CYBSP_D1
+/** Arduino D1 \def CYBSP_D1
+ */
+#endif
+#ifdef CYBSP_D2
+/** Arduino D2 \def CYBSP_D2
+ */
+#endif
+#ifdef CYBSP_D3
+/** Arduino D3 \def CYBSP_D3
+ */
+#endif
+#ifdef CYBSP_D4
+/** Arduino D4 \def CYBSP_D4
+ */
+#endif
+#ifdef CYBSP_D5
+/** Arduino D5 \def CYBSP_D5
+ */
+#endif
+#ifdef CYBSP_D6
+/** Arduino D6 \def CYBSP_D6
+ */
+#endif
+#ifdef CYBSP_D7
+/** Arduino D7 \def CYBSP_D7
+ */
+#endif
+#ifdef CYBSP_D8
+/** Arduino D8 \def CYBSP_D8
+ */
+#endif
+#ifdef CYBSP_D9
+/** Arduino D9 \def CYBSP_D9
+ */
+#endif
+#ifdef CYBSP_D10
+/** Arduino D10 \def CYBSP_D10
+ */
+#endif
+#ifdef CYBSP_D11
+/** Arduino D11 \def CYBSP_D11
+ */
+#endif
+#ifdef CYBSP_D12
+/** Arduino D12 \def CYBSP_D12
+ */
+#endif
+#ifdef CYBSP_D13
+/** Arduino D13 \def CYBSP_D13
+ */
+#endif
+#ifdef CYBSP_D14
+/** Arduino D14 \def CYBSP_D14
+ */
+#endif
+#ifdef CYBSP_D15
+/** Arduino D15 \def CYBSP_D15
+ */
+#endif
+
+/** \} group_bsp_pins_arduino */
+#endif // defined(CYBSP_A0)
+
+#if defined(CYBSP_J2_1)
+/**
+ * \addtogroup group_bsp_pins_j2 J2 Header Pins
+ * \{
+ * Pins mapped to the J2 header on the board.
+ */
+
+#ifdef CYBSP_J2_1
+/** Infineon J2 Header pin 1 \def CYBSP_J2_1
+ */
+#endif
+#ifdef CYBSP_J2_2
+/** Infineon J2 Header pin 2 \def CYBSP_J2_2
+ */
+#endif
+#ifdef CYBSP_J2_3
+/** Infineon J2 Header pin 3 \def CYBSP_J2_3
+ */
+#endif
+#ifdef CYBSP_J2_4
+/** Infineon J2 Header pin 4 \def CYBSP_J2_4
+ */
+#endif
+#ifdef CYBSP_J2_5
+/** Infineon J2 Header pin 5 \def CYBSP_J2_5
+ */
+#endif
+#ifdef CYBSP_J2_7
+/** Infineon J2 Header pin 7 \def CYBSP_J2_7
+ */
+#endif
+#ifdef CYBSP_J2_8
+/** Infineon J2 Header pin 8 \def CYBSP_J2_8
+ */
+#endif
+#ifdef CYBSP_J2_9
+/** Infineon J2 Header pin 9 \def CYBSP_J2_9
+ */
+#endif
+#ifdef CYBSP_J2_10
+/** Infineon J2 Header pin 10 \def CYBSP_J2_10
+ */
+#endif
+#ifdef CYBSP_J2_11
+/** Infineon J2 Header pin 11 \def CYBSP_J2_11
+ */
+#endif
+#ifdef CYBSP_J2_12
+/** Infineon J2 Header pin 12 \def CYBSP_J2_12
+ */
+#endif
+#ifdef CYBSP_J2_13
+/** Infineon J2 Header pin 13 \def CYBSP_J2_13
+ */
+#endif
+#ifdef CYBSP_J2_15
+/** Infineon J2 Header pin 15 \def CYBSP_J2_15
+ */
+#endif
+#ifdef CYBSP_J2_16
+/** Infineon J2 Header pin 16 \def CYBSP_J2_16
+ */
+#endif
+#ifdef CYBSP_J2_16
+/** Infineon J2 Header pin 16 \def CYBSP_J2_16
+ */
+#endif
+#ifdef CYBSP_J2_6
+/** Infineon J2 Header pin 6 \def CYBSP_J2_6
+ */
+#endif
+#ifdef CYBSP_J2_17
+/** Infineon J2 Header pin 17 \def CYBSP_J2_17
+ */
+#endif
+#ifdef CYBSP_J2_18
+/** Infineon J2 Header pin 18 \def CYBSP_J2_18
+ */
+#endif
+#ifdef CYBSP_J2_19
+/** Infineon J2 Header pin 19 \def CYBSP_J2_19
+ */
+#endif
+#ifdef CYBSP_J2_20
+/** Infineon J2 Header pin 20 \def CYBSP_J2_20
+ */
+#endif
+#ifdef CYBSP_J2_14
+/** Infineon J2 Header pin 14 \def CYBSP_J2_14
+ */
+#endif
+
+/** \} group_bsp_pins_j2 */
+#endif // defined(CYBSP_J2_1)
+
+#if defined(CYBSP_J6_1)
+/**
+ * \addtogroup group_bsp_pins_j6 J6 Header Pins
+ * \{
+ * Pins mapped to the J6 header on the board.
+ */
+
+#ifdef CYBSP_J6_1
+/** Infineon J6 Header pin 1 \def CYBSP_J6_1
+ */
+#endif
+#ifdef CYBSP_J6_2
+/** Infineon J6 Header pin 2 \def CYBSP_J6_2
+ */
+#endif
+#ifdef CYBSP_J6_3
+/** Infineon J6 Header pin 3 \def CYBSP_J6_3
+ */
+#endif
+#ifdef CYBSP_J6_4
+/** Infineon J6 Header pin 4 \def CYBSP_J6_4
+ */
+#endif
+#ifdef CYBSP_J6_5
+/** Infineon J6 Header pin 5 \def CYBSP_J6_5
+ */
+#endif
+#ifdef CYBSP_J6_6
+/** Infineon J6 Header pin 6 \def CYBSP_J6_6
+ */
+#endif
+#ifdef CYBSP_J6_7
+/** Infineon J6 Header pin 7 \def CYBSP_J6_7
+ */
+#endif
+#ifdef CYBSP_J6_8
+/** Infineon J6 Header pin 8 \def CYBSP_J6_8
+ */
+#endif
+#ifdef CYBSP_J6_9
+/** Infineon J6 Header pin 9 \def CYBSP_J6_9
+ */
+#endif
+#ifdef CYBSP_J6_10
+/** Infineon J6 Header pin 10 \def CYBSP_J6_10
+ */
+#endif
+#ifdef CYBSP_J6_11
+/** Infineon J6 Header pin 11 \def CYBSP_J6_11
+ */
+#endif
+#ifdef CYBSP_J6_12
+/** Infineon J6 Header pin 12 \def CYBSP_J6_12
+ */
+#endif
+#ifdef CYBSP_J6_13
+/** Infineon J6 Header pin 13 \def CYBSP_J6_13
+ */
+#endif
+#ifdef CYBSP_J6_14
+/** Infineon J6 Header pin 14 \def CYBSP_J6_14
+ */
+#endif
+#ifdef CYBSP_J6_15
+/** Infineon J6 Header pin 15 \def CYBSP_J6_15
+ */
+#endif
+#ifdef CYBSP_J6_16
+/** Infineon J6 Header pin 16 \def CYBSP_J6_16
+ */
+#endif
+
+/** \} group_bsp_pins_j6 */
+#endif // defined(CYBSP_J6_1)
+
+#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
+/**
+ * \addtogroup group_bsp_pins_capsense Capsense
+ * \{
+ * Pins connected to CAPSENSE™ sensors on the board.
+ */
+
+#ifdef CYBSP_CSD_TX
+/** Pin: CapSesnse TX \def CYBSP_CSD_TX
+ */
+#endif
+#ifdef CYBSP_CINA
+/** Pin: CapSesnse CINA \def CYBSP_CINA
+ */
+#endif
+#ifdef CYBSP_CINTA
+/** Pin: CapSesnse CINTA \def CYBSP_CINTA
+ */
+#endif
+#ifdef CYBSP_CINB
+/** Pin: CapSesnse CINB \def CYBSP_CINB
+ */
+#endif
+#ifdef CYBSP_CINTB
+/** Pin: CapSesnse CINTB \def CYBSP_CINTB
+ */
+#endif
+#ifdef CYBSP_CMOD
+/** Pin: CapSesnse CMOD \def CYBSP_CMOD
+ */
+#endif
+#ifdef CYBSP_CSD_BTN0
+/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0
+ */
+#endif
+#ifdef CYBSP_CSD_BTN1
+/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1
+ */
+#endif
+#ifdef CYBSP_CSD_SLD0
+/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0
+ */
+#endif
+#ifdef CYBSP_CSD_SLD1
+/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1
+ */
+#endif
+#ifdef CYBSP_CSD_SLD2
+/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2
+ */
+#endif
+#ifdef CYBSP_CSD_SLD3
+/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3
+ */
+#endif
+#ifdef CYBSP_CSD_SLD4
+/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4
+ */
+#endif
+#ifdef CYBSP_CSD_SLD5
+/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5
+ */
+#endif
+#ifdef CYBSP_CSX_BTN_TX
+/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX
+ */
+#endif
+#ifdef CYBSP_CSX_BTN0
+/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0
+ */
+#endif
+#ifdef CYBSP_CSX_BTN1
+/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1
+ */
+#endif
+#ifdef CYBSP_CSX_BTN2
+/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2
+ */
+#endif
+
+/** \} group_bsp_pins_capsense */
+#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA)
+
+#if defined(CYBSP_WCO_IN)
+/**
+ * \addtogroup group_bsp_pins_wco WCO
+ * \{
+ * Pins connected to the WCO on the board.
+ */
+#ifdef CYBSP_WCO_IN
+/** Pin: WCO input \def CYBSP_WCO_IN
+ */
+#endif
+#ifdef CYBSP_WCO_OUT
+/** Pin: WCO output \def CYBSP_WCO_OUT
+ */
+#endif
+
+/** \} group_bsp_pins_wco */
+#endif // defined(CYBSP_WCO_IN)
+
+/** \} group_bsp_pins */
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h b/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
new file mode 100644
index 0000000..580d49c
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
@@ -0,0 +1,42 @@
+/***********************************************************************************************//**
+ * \file cybsp_hw_config.h
+ *
+ * \brief
+ * Basic API for handling defaults for hardware so code examples behave the same across different
+ * devices.
+ *
+ ***************************************************************************************************
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+#pragma once
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#ifndef CYBSP_USER_BTN_DRIVE
+#define CYBSP_USER_BTN_DRIVE          (CYHAL_GPIO_DRIVE_PULLUP)
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_types.h b/boot/cypress/platforms/BSP/XMC7000/cybsp_types.h
new file mode 100644
index 0000000..aeb7023
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp_types.h
@@ -0,0 +1,73 @@
+/***********************************************************************************************//**
+ * \copyright
+ * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **************************************************************************************************/
+
+#pragma once
+
+#include "cybsp_doc.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * \cond INTERNAL
+ */
+/* WIFI interface types */
+#define CYBSP_SDIO_INTERFACE             (0)
+#define CYBSP_SPI_INTERFACE              (1)
+#define CYBSP_M2M_INTERFACE              (2)
+
+/* Map from the new components to the old interface names for
+ * compatibility with code that still depends on those defines */
+#if defined(COMPONENT_WIFI_INTERFACE_SDIO)
+#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SDIO_INTERFACE)
+#elif defined(COMPONENT_WIFI_INTERFACE_SPI)
+#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_SPI_INTERFACE)
+#elif defined(COMPONENT_WIFI_INTERFACE_M2M)
+#define CYBSP_WIFI_INTERFACE_TYPE (CYBSP_M2M_INTERFACE)
+#endif
+/** \endcond */
+
+/**
+ * \addtogroup group_bsp_pin_state Pin States
+ * \{
+ * Macros to abstract out whether the LEDs & Buttons are wired high or active low.
+ */
+/** Pin state for the LED on. */
+#ifndef CYBSP_LED_STATE_ON
+#define CYBSP_LED_STATE_ON          (0U)
+#endif
+/** Pin state for the LED off. */
+#ifndef CYBSP_LED_STATE_OFF
+#define CYBSP_LED_STATE_OFF         (1U)
+#endif
+/** Pin state for when a button is pressed. */
+#ifndef CYBSP_BTN_PRESSED
+#define CYBSP_BTN_PRESSED           (0U)
+#endif
+/** Pin state for when a button is released. */
+#ifndef CYBSP_BTN_OFF
+#define CYBSP_BTN_OFF               (1U)
+#endif
+/** \} group_bsp_pin_state */
+
+#if defined(__cplusplus)
+}
+#endif
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.c b/boot/cypress/platforms/BSP/XMC7000/cycfg.c
new file mode 100644
index 0000000..f61f95b
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.c
@@ -0,0 +1,49 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+/* This function is provided for compatibility with older 2.X style projects. */
+void init_cycfg_all(void)
+{
+    cycfg_config_init();
+    cycfg_config_reservations();
+}
+void cycfg_config_init(void)
+{
+    init_cycfg_system();
+    init_cycfg_clocks();
+    init_cycfg_routing();
+    init_cycfg_pins();
+}
+void cycfg_config_reservations(void)
+{
+    reserve_cycfg_system();
+    reserve_cycfg_clocks();
+    reserve_cycfg_pins();
+}
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.h b/boot/cypress/platforms/BSP/XMC7000/cycfg.h
new file mode 100644
index 0000000..c650151
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.h
@@ -0,0 +1,53 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+
+void init_cycfg_all(void);
+void cycfg_config_init(void);
+void cycfg_config_reservations(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp b/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp
new file mode 100644
index 0000000..a2dfeb7
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.timestamp
@@ -0,0 +1,28 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
new file mode 100644
index 0000000..8d36f4e
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
@@ -0,0 +1,73 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t peri_0_group_0_div_16_0_obj = 
+    {
+        .type = CYHAL_RSC_CLOCK,
+        .block_num = peri_0_group_0_div_16_0_HW,
+        .channel_num = peri_0_group_0_div_16_0_NUM,
+    };
+    const cyhal_resource_inst_t peri_0_group_0_div_8_2_obj = 
+    {
+        .type = CYHAL_RSC_CLOCK,
+        .block_num = peri_0_group_0_div_8_2_HW,
+        .channel_num = peri_0_group_0_div_8_2_NUM,
+    };
+    const cyhal_resource_inst_t peri_0_group_1_div_24_5_0_obj = 
+    {
+        .type = CYHAL_RSC_CLOCK,
+        .block_num = peri_0_group_1_div_24_5_0_HW,
+        .channel_num = peri_0_group_1_div_24_5_0_NUM,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_16_0_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U);
+    Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_16_0_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U, 0U);
+    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_16_0_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U);
+    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U);
+    Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U, 0U);
+    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_0_DIV_8_2_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 2U);
+    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_24_5_0_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U);
+    Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_24_5_0_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U, 105U, 11U);
+    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_1_DIV_24_5_0_GRP_NUM, CY_SYSCLK_DIV_24_5_BIT, 0U);
+}
+
+void reserve_cycfg_clocks(void)
+{
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&peri_0_group_0_div_16_0_obj);
+    cyhal_hwmgr_reserve(&peri_0_group_0_div_8_2_obj);
+    cyhal_hwmgr_reserve(&peri_0_group_1_div_24_5_0_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
new file mode 100644
index 0000000..a066ddc
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
@@ -0,0 +1,84 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define peri_0_group_0_div_16_0_ENABLED 1U
+#if defined (CY_USING_HAL)
+    #define peri_0_group_0_div_16_0_HW CYHAL_CLOCK_BLOCK_PERIPHERAL0_16BIT
+#endif //defined (CY_USING_HAL)
+#if !defined (CY_USING_HAL)
+    #define peri_0_group_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
+#endif //!defined (CY_USING_HAL)
+#define peri_0_group_0_div_16_0_NUM 0U
+#define PERI_0_GROUP_0_DIV_16_0_GRP_NUM (0U << PERI_PCLK_GR_NUM_Pos)
+#define peri_0_group_0_div_8_2_ENABLED 1U
+#if defined (CY_USING_HAL)
+    #define peri_0_group_0_div_8_2_HW CYHAL_CLOCK_BLOCK_PERIPHERAL0_8BIT
+#endif //defined (CY_USING_HAL)
+#if !defined (CY_USING_HAL)
+    #define peri_0_group_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
+#endif //!defined (CY_USING_HAL)
+#define peri_0_group_0_div_8_2_NUM 2U
+#define PERI_0_GROUP_0_DIV_8_2_GRP_NUM (0U << PERI_PCLK_GR_NUM_Pos)
+#define peri_0_group_1_div_24_5_0_ENABLED 1U
+#if defined (CY_USING_HAL)
+    #define peri_0_group_1_div_24_5_0_HW CYHAL_CLOCK_BLOCK_PERIPHERAL1_24_5BIT
+#endif //defined (CY_USING_HAL)
+#if !defined (CY_USING_HAL)
+    #define peri_0_group_1_div_24_5_0_HW CY_SYSCLK_DIV_24_5_BIT
+#endif //!defined (CY_USING_HAL)
+#define peri_0_group_1_div_24_5_0_NUM 0U
+#define PERI_0_GROUP_1_DIV_24_5_0_GRP_NUM (1U << PERI_PCLK_GR_NUM_Pos)
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t peri_0_group_0_div_16_0_obj;
+    extern const cyhal_resource_inst_t peri_0_group_0_div_8_2_obj;
+    extern const cyhal_resource_inst_t peri_0_group_1_div_24_5_0_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_clocks(void);
+void reserve_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
new file mode 100644
index 0000000..7499cf0
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
@@ -0,0 +1,46 @@
+/*******************************************************************************
+* File Name: cycfg_notices.h
+*
+* Description:
+* Contains warnings and errors that occurred while generating code for the
+* design.
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
+
+#ifdef CY_SUPPORTS_DEVICE_VALIDATION
+#ifndef XMC7100D_E272K4160
+    #error "Unexpected MPN; expected DEVICE:=XMC7100D-E272K4160. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif
+#endif
+
+#ifdef CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION
+#ifndef XMC7100D_E272K4160
+    #error "Unexpected MPN; expected DEVICE:=XMC7100D-E272K4160. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif
+#endif
+
+
+#endif /* CYCFG_NOTICES_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
new file mode 100644
index 0000000..3e65c19
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
@@ -0,0 +1,30 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_peripherals.h"
+
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
new file mode 100644
index 0000000..2eec711
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
@@ -0,0 +1,43 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.h
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PERIPHERALS_H)
+#define CYCFG_PERIPHERALS_H
+
+#include "cycfg_notices.h"
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PERIPHERALS_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
new file mode 100644
index 0000000..d4ad893
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
@@ -0,0 +1,221 @@
+/*******************************************************************************
+* File Name: cycfg_pins.c
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_pins.h"
+
+const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_WCO_IN_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_WCO_IN_PORT_NUM,
+        .channel_num = CYBSP_WCO_IN_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_WCO_OUT_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_WCO_OUT_PORT_NUM,
+        .channel_num = CYBSP_WCO_OUT_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_ECO_IN_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_ECO_IN_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_ECO_IN_PORT_NUM,
+        .channel_num = CYBSP_ECO_IN_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_ECO_OUT_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_ECO_OUT_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_ECO_OUT_PORT_NUM,
+        .channel_num = CYBSP_ECO_OUT_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+    .hsiom = CYBSP_SWO_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWO_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWO_PORT_NUM,
+        .channel_num = CYBSP_SWO_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_PULLDOWN,
+    .hsiom = CYBSP_SWDCK_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWDCK_PORT_NUM,
+        .channel_num = CYBSP_SWDCK_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_PULLUP,
+    .hsiom = CYBSP_SWDIO_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWDIO_PORT_NUM,
+        .channel_num = CYBSP_SWDIO_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_pins(void)
+{
+    Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config);
+    Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config);
+    Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+    Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+    Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+}
+
+void reserve_cycfg_pins(void)
+{
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+    cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+    cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj);
+    cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj);
+    cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+    cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+    cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
new file mode 100644
index 0000000..2acf412
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
@@ -0,0 +1,296 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#include "cycfg_routing.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if defined (CY_USING_HAL)
+    #define CYBSP_CAN_TX (P0_2)
+    #define CYBSP_CAN_RX (P0_3)
+    #define CYBSP_SPI_MISO (P10_0)
+    #define CYBSP_D12 CYBSP_SPI_MISO
+    #define CYBSP_SPI_MOSI (P10_1)
+    #define CYBSP_D11 CYBSP_SPI_MOSI
+    #define CYBSP_SPI_CLK (P10_2)
+    #define CYBSP_D13 CYBSP_SPI_CLK
+    #define CYBSP_SPI_CS (P10_3)
+    #define CYBSP_D10 CYBSP_SPI_CS
+    #define CYBSP_D9 (P10_4)
+    #define CYBSP_D8 (P10_5)
+    #define CYBSP_A8 (P12_0)
+    #define CYBSP_A9 (P12_1)
+    #define CYBSP_A10 (P12_2)
+    #define CYBSP_A11 (P12_3)
+    #define CYBSP_A12 (P12_4)
+    #define CYBSP_A13 (P12_5)
+    #define CYBSP_A14 (P12_6)
+    #define CYBSP_A15 (P12_7)
+    #define CYBSP_DEBUG_UART_RX (P13_0)
+    #define CYBSP_D0 CYBSP_DEBUG_UART_RX
+    #define CYBSP_DEBUG_UART_TX (P13_1)
+    #define CYBSP_D1 CYBSP_DEBUG_UART_TX
+    #define CYBSP_DEBUG_UART_RTS (P13_2)
+    #define CYBSP_D2 CYBSP_DEBUG_UART_RTS
+    #define CYBSP_DEBUG_UART_CTS (P13_3)
+    #define CYBSP_D3 CYBSP_DEBUG_UART_CTS
+    #define CYBSP_D4 (P13_4)
+    #define CYBSP_D5 (P13_5)
+    #define CYBSP_D6 (P13_6)
+    #define CYBSP_D7 (P13_7)
+    #define CYBSP_A0 (P14_0)
+    #define CYBSP_A1 (P14_1)
+    #define CYBSP_A2 (P14_2)
+    #define CYBSP_A3 (P14_3)
+    #define CYBSP_A4 (P14_4)
+    #define CYBSP_A5 (P14_5)
+    #define CYBSP_A6 (P14_6)
+    #define CYBSP_A7 (P14_7)
+    #define CYBSP_I2C_SDA (P15_1)
+    #define CYBSP_I2C_SCL (P15_2)
+    #define CYBSP_USER_LED (P16_1)
+    #define CYBSP_USER_LED1 CYBSP_USER_LED
+    #define LED1 CYBSP_USER_LED
+    #define CYBSP_USER_LED2 (P16_2)
+    #define LED2 CYBSP_USER_LED2
+    #define CYBSP_USER_LED3 (P16_3)
+    #define LED3 CYBSP_USER_LED3
+    #define CYBSP_USER_BTN2 (P17_3)
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT21
+#define CYBSP_WCO_IN_PORT_NUM 21U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_21_pin_0_HSIOM
+    #define ioss_0_port_21_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_21_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_21_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN_HAL_PORT_PIN P21_0
+    #define CYBSP_WCO_IN P21_0
+    #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+    #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT21
+#define CYBSP_WCO_OUT_PORT_NUM 21U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_21_pin_1_HSIOM
+    #define ioss_0_port_21_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_21_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_21_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT_HAL_PORT_PIN P21_1
+    #define CYBSP_WCO_OUT P21_1
+    #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+    #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_ECO_IN_ENABLED 1U
+#define CYBSP_ECO_IN_PORT GPIO_PRT21
+#define CYBSP_ECO_IN_PORT_NUM 21U
+#define CYBSP_ECO_IN_PIN 2U
+#define CYBSP_ECO_IN_NUM 2U
+#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_ECO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_21_pin_2_HSIOM
+    #define ioss_0_port_21_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_ECO_IN_HSIOM ioss_0_port_21_pin_2_HSIOM
+#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_21_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_ECO_IN_HAL_PORT_PIN P21_2
+    #define CYBSP_ECO_IN P21_2
+    #define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+    #define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_ECO_OUT_ENABLED 1U
+#define CYBSP_ECO_OUT_PORT GPIO_PRT21
+#define CYBSP_ECO_OUT_PORT_NUM 21U
+#define CYBSP_ECO_OUT_PIN 3U
+#define CYBSP_ECO_OUT_NUM 3U
+#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_21_pin_3_HSIOM
+    #define ioss_0_port_21_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_ECO_OUT_HSIOM ioss_0_port_21_pin_3_HSIOM
+#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_21_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_ECO_OUT_HAL_PORT_PIN P21_3
+    #define CYBSP_ECO_OUT P21_3
+    #define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+    #define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_USER_BTN1 (P21_4)
+    #define CYBSP_USER_BTN CYBSP_USER_BTN1
+    #define CYBSP_TRACE_DATA0 (P21_5)
+    #define CYBSP_TRACE_DATA1 (P22_1)
+    #define CYBSP_TRACE_DATA2 (P22_2)
+    #define CYBSP_TRACE_DATA3 (P22_3)
+    #define CYBSP_TRACE_CLK (P22_4)
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT23
+#define CYBSP_SWO_PORT_NUM 23U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_23_pin_4_HSIOM
+    #define ioss_0_port_23_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_23_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_23_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWO_HAL_PORT_PIN P23_4
+    #define CYBSP_SWO P23_4
+    #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
+    #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT23
+#define CYBSP_SWDCK_PORT_NUM 23U
+#define CYBSP_SWDCK_PIN 5U
+#define CYBSP_SWDCK_NUM 5U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_23_pin_5_HSIOM
+    #define ioss_0_port_23_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_23_pin_5_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_23_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK_HAL_PORT_PIN P23_5
+    #define CYBSP_SWDCK P23_5
+    #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+    #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT23
+#define CYBSP_SWDIO_PORT_NUM 23U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_23_pin_6_HSIOM
+    #define ioss_0_port_23_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_23_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_23_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO_HAL_PORT_PIN P23_6
+    #define CYBSP_SWDIO P23_6
+    #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
+    #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+    #define CYBSP_WIFI_SDIO_CLK (P24_2)
+    #define CYBSP_WIFI_SDIO_CMD (P24_3)
+    #define CYBSP_WIFI_SDIO_D0 (P25_0)
+    #define CYBSP_WIFI_SDIO_D1 (P25_1)
+    #define CYBSP_WIFI_SDIO_D2 (P25_2)
+    #define CYBSP_WIFI_SDIO_D3 (P25_3)
+    #define CYBSP_WIFI_HOST_WAKE (P25_4)
+    #define CYBSP_WIFI_WL_REG_ON (P25_6)
+    #define CYBSP_BT_UART_RX (P32_0)
+    #define CYBSP_BT_UART_TX (P32_1)
+    #define CYBSP_BT_UART_RTS (P32_2)
+    #define CYBSP_BT_UART_CTS (P32_3)
+    #define CYBSP_BT_HOST_WAKE (P32_4)
+    #define CYBSP_BT_DEVICE_WAKE (P32_5)
+    #define CYBSP_BT_POWER (P32_6)
+    #define CYBSP_QSPI_SCK (P6_3)
+    #define CYBSP_QSPI_SS (P6_5)
+    #define CYBSP_QSPI_FLASH_SSEL CYBSP_QSPI_SS
+    #define CYBSP_POT (P6_6)
+    #define CYBSP_QSPI_D0 (P7_1)
+    #define CYBSP_QSPI_D1 (P7_2)
+    #define CYBSP_QSPI_D2 (P7_3)
+    #define CYBSP_QSPI_D3 (P7_4)
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+void reserve_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
new file mode 100644
index 0000000..f877724
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
@@ -0,0 +1,507 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 4.0.0.974
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x00U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeEnCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x00U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeDisCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x00U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_eraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x00U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_chipEraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x00U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_programCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x00U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x00U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegWipCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x00U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x00U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /* The Data rate of data */
+    .dataRate = CY_SMIF_SDR,
+    /* This specifies the presence of the dummy field */
+    .dummyCyclesPresence = CY_SMIF_NOT_PRESENT,
+    /* This specifies the presence of the mode field */
+    .modePresence = CY_SMIF_NOT_PRESENT,
+    /* The high byte of a 16-bit mode. This value is 0x0 when there is no higher byte mode present */
+    .modeH = 0x00,
+    /* The Data rate of mode */
+    .modeRate = CY_SMIF_SDR,
+    /* The Data rate of address */
+    .addrRate = CY_SMIF_SDR,
+    /* This specifies the width of the command field */
+    .cmdPresence = CY_SMIF_PRESENT_1BYTE,
+    /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
+    .commandH = 0x00,
+    /* The Data rate of command */
+    .cmdRate = CY_SMIF_SDR
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readSfdpCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x5AU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 8U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
+static cy_stc_smif_hybrid_region_info_t SFDP_SlaveSlot_0_regionInfoStorage[16];
+
+static cy_stc_smif_hybrid_region_info_t *SFDP_SlaveSlot_0_regionInfo[16] = {
+    &SFDP_SlaveSlot_0_regionInfoStorage[0],
+    &SFDP_SlaveSlot_0_regionInfoStorage[1],
+    &SFDP_SlaveSlot_0_regionInfoStorage[2],
+    &SFDP_SlaveSlot_0_regionInfoStorage[3],
+    &SFDP_SlaveSlot_0_regionInfoStorage[4],
+    &SFDP_SlaveSlot_0_regionInfoStorage[5],
+    &SFDP_SlaveSlot_0_regionInfoStorage[6],
+    &SFDP_SlaveSlot_0_regionInfoStorage[7],
+    &SFDP_SlaveSlot_0_regionInfoStorage[8],
+    &SFDP_SlaveSlot_0_regionInfoStorage[9],
+    &SFDP_SlaveSlot_0_regionInfoStorage[10],
+    &SFDP_SlaveSlot_0_regionInfoStorage[11],
+    &SFDP_SlaveSlot_0_regionInfoStorage[12],
+    &SFDP_SlaveSlot_0_regionInfoStorage[13],
+    &SFDP_SlaveSlot_0_regionInfoStorage[14],
+    &SFDP_SlaveSlot_0_regionInfoStorage[15]
+};
+#endif
+
+cy_stc_smif_mem_device_cfg_t deviceCfg_SFDP_SlaveSlot_0 =
+{
+    /* Specifies the number of address bytes used by the memory slave device. */
+    .numOfAddrBytes = 0x03U,
+    /* The size of the memory. */
+    .memSize = 0x0000100U,
+    /* Specifies the Read command. */
+    .readCmd = &SFDP_SlaveSlot_0_readCmd,
+    /* Specifies the Write Enable command. */
+    .writeEnCmd = &SFDP_SlaveSlot_0_writeEnCmd,
+    /* Specifies the Write Disable command. */
+    .writeDisCmd = &SFDP_SlaveSlot_0_writeDisCmd,
+    /* Specifies the Erase command. */
+    .eraseCmd = &SFDP_SlaveSlot_0_eraseCmd,
+    /* Specifies the sector size of each erase. */
+    .eraseSize = 0x0001000U,
+    /* Specifies the Chip Erase command. */
+    .chipEraseCmd = &SFDP_SlaveSlot_0_chipEraseCmd,
+    /* Specifies the Program command. */
+    .programCmd = &SFDP_SlaveSlot_0_programCmd,
+    /* Specifies the page size for programming. */
+    .programSize = 0x0000100U,
+    /* Specifies the command to read the QE-containing status register. */
+    .readStsRegQeCmd = &SFDP_SlaveSlot_0_readStsRegQeCmd,
+    /* Specifies the command to read the WIP-containing status register. */
+    .readStsRegWipCmd = &SFDP_SlaveSlot_0_readStsRegWipCmd,
+    /* Specifies the read SFDP command */
+    .readSfdpCmd = &SFDP_SlaveSlot_0_readSfdpCmd,
+    /* Specifies the command to write into the QE-containing status register. */
+    .writeStsRegQeCmd = &SFDP_SlaveSlot_0_writeStsRegQeCmd,
+    /* The mask for the status register. */
+    .stsRegBusyMask = 0x00U,
+    /* The mask for the status register. */
+    .stsRegQuadEnableMask = 0x00U,
+    /* The max time for the erase type-1 cycle-time in ms. */
+    .eraseTime = 1U,
+    /* The max time for the chip-erase cycle-time in ms. */
+    .chipEraseTime = 16U,
+    /* The max time for the page-program cycle-time in us. */
+    .programTime = 8U,
+#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
+    /* Points to NULL or to structure with info about sectors for hybrid memory. */
+    .hybridRegionCount = 0U,
+    .hybridRegionInfo = SFDP_SlaveSlot_0_regionInfo
+#endif
+};
+
+const cy_stc_smif_mem_config_t SFDP_SlaveSlot_0 =
+{
+    /* Determines the slot number where the memory device is placed. */
+    .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+    /* Flags. */
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    .flags = CY_SMIF_FLAG_SMIF_REV_3 | CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_CRYPTO_EN | CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MERGE_ENABLE,
+#else
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN | CY_SMIF_FLAG_CRYPTO_EN | CY_SMIF_FLAG_DETECT_SFDP | CY_SMIF_FLAG_MERGE_ENABLE,
+#endif /* CY_IP_MXSMIF_VERSION */
+    /* The data-line selection options for a slave device. */
+    .dataSelect = CY_SMIF_DATA_SEL0,
+    /* The base address the memory slave is mapped to in the PSoC memory map.
+    Valid when the memory-mapped mode is enabled. */
+    .baseAddress = 0x60000000U,
+    /* The size allocated in the PSoC memory map, for the memory slave device.
+    The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+    .memMappedSize = 0x800000U,
+    /* If this memory device is one of the devices in the dual quad SPI configuration.
+    Valid when the memory mapped mode is enabled. */
+    .dualQuadSlots = 0,
+    /* The configuration of the device. */
+    .deviceCfg = &deviceCfg_SFDP_SlaveSlot_0,
+#if (CY_IP_MXSMIF_VERSION >= 2)
+    /** Continous transfer merge timeout.
+     * After this period the memory device is deselected. A later transfer, even from a
+     * continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
+     * This configuration parameter is available for CAT1B devices. */
+    .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_256_CYCLES
+#else
+#error Features used by this file require CY_IP_MXSMIF_VERSION >= 2.
+#endif /* CY_IP_MXSMIF_VERSION */
+};
+
+const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM] = {
+   &SFDP_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t smifBlockConfig =
+{
+    /* The number of SMIF memories defined. */
+    .memCount = CY_SMIF_DEVICE_NUM,
+    /* The pointer to the array of memory config structures of size memCount. */
+    .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+    /* The version of the SMIF driver. */
+    .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+    /* The version of the SMIF driver. */
+    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
new file mode 100644
index 0000000..d9b08eb
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
@@ -0,0 +1,80 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 4.0.0.974
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_CFG_TOOL_VERSION           (400)
+
+/* Supported QSPI Driver version */
+#define CY_SMIF_DRV_VERSION_REQUIRED       (100)
+
+#if !defined(CY_SMIF_DRV_VERSION)
+    #define CY_SMIF_DRV_VERSION            (100)
+#endif
+
+/* Check the used Driver version */
+#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION)
+   #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
+#endif
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeEnCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeDisCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_eraseCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_chipEraseCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_programCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegQeCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readStsRegWipCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_writeStsRegQeCmd;
+extern cy_stc_smif_mem_cmd_t SFDP_SlaveSlot_0_readSfdpCmd;
+
+extern cy_stc_smif_mem_device_cfg_t deviceCfg_SFDP_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t SFDP_SlaveSlot_0;
+
+#define Auto_detect_SFDP_SlaveSlot_0_readCmd SFDP_SlaveSlot_0_readCmd
+#define Auto_detect_SFDP_SlaveSlot_0_writeEnCmd SFDP_SlaveSlot_0_writeEnCmd
+#define Auto_detect_SFDP_SlaveSlot_0_writeDisCmd SFDP_SlaveSlot_0_writeDisCmd
+#define Auto_detect_SFDP_SlaveSlot_0_eraseCmd SFDP_SlaveSlot_0_eraseCmd
+#define Auto_detect_SFDP_SlaveSlot_0_chipEraseCmd SFDP_SlaveSlot_0_chipEraseCmd
+#define Auto_detect_SFDP_SlaveSlot_0_programCmd SFDP_SlaveSlot_0_programCmd
+#define Auto_detect_SFDP_SlaveSlot_0_readStsRegQeCmd SFDP_SlaveSlot_0_readStsRegQeCmd
+#define Auto_detect_SFDP_SlaveSlot_0_readStsRegWipCmd SFDP_SlaveSlot_0_readStsRegWipCmd
+#define Auto_detect_SFDP_SlaveSlot_0_writeStsRegQeCmd SFDP_SlaveSlot_0_writeStsRegQeCmd
+#define Auto_detect_SFDP_SlaveSlot_0_readSfdpCmd SFDP_SlaveSlot_0_readSfdpCmd
+#define deviceCfg_Auto_detect_SFDP_SlaveSlot_0 deviceCfg_SFDP_SlaveSlot_0
+#define Auto_detect_SFDP_SlaveSlot_0 SFDP_SlaveSlot_0
+
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CYCFG_QSPI_MEMSLOT_H*/
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
new file mode 100644
index 0000000..2e8a2ce
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
@@ -0,0 +1,50 @@
+/*******************************************************************************
+* File Name: cycfg_routing.h
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_ROUTING_H)
+#define CYCFG_ROUTING_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+static inline void init_cycfg_routing(void) {}
+
+#define ioss_0_port_21_pin_0_ANALOG P21_0_SRSS_WCO_IN
+#define ioss_0_port_21_pin_1_ANALOG P21_1_SRSS_WCO_OUT
+#define ioss_0_port_23_pin_4_HSIOM P23_4_CPUSS_SWJ_SWO_TDO
+#define ioss_0_port_23_pin_5_HSIOM P23_5_CPUSS_SWJ_SWCLK_TCLK
+#define ioss_0_port_23_pin_6_HSIOM P23_6_CPUSS_SWJ_SWDIO_TMS
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_ROUTING_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
new file mode 100644
index 0000000..ca14ba0
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
@@ -0,0 +1,789 @@
+/*******************************************************************************
+* File Name: cycfg_system.c
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_system.h"
+
+#define CY_CFG_SYSCLK_ECO_ERROR 1
+#define CY_CFG_SYSCLK_ALTHF_ERROR 2
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+#define CY_CFG_SYSCLK_FLL_ERROR 4
+#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
+#define CY_CFG_SYSCLK_CLKFAST_0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_0_INT_DIVIDER 0
+#define CY_CFG_SYSCLK_CLKFAST_0_FRAC_DIVIDER 0
+#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_MULT 500U
+#define CY_CFG_SYSCLK_FLL_REFDIV 40U
+#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE2
+#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true
+#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U
+#define CY_CFG_SYSCLK_FLL_IGAIN 9U
+#define CY_CFG_SYSCLK_FLL_PGAIN 0U
+#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U
+#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
+#define CY_CFG_SYSCLK_FLL_CCO_FREQ 235U
+#define CY_CFG_SYSCLK_FLL_OUT_FREQ 50000000
+#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 50UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF1_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 250UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
+#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF2_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 196UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH2
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 144UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH3
+#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH4
+#define CY_CFG_SYSCLK_CLKHF5_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF5_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ 8UL
+#define CY_CFG_SYSCLK_CLKHF5_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH5
+#define CY_CFG_SYSCLK_CLKHF6_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF6_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF6_FREQ_MHZ 8UL
+#define CY_CFG_SYSCLK_CLKHF6_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH5
+#define CY_CFG_SYSCLK_CLKHF7_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF7_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF7_FREQ_MHZ 8UL
+#define CY_CFG_SYSCLK_CLKHF7_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH5
+#define CY_CFG_SYSCLK_ILO0_ENABLED 1
+#define CY_CFG_SYSCLK_ILO0_HIBERNATE true
+#define CY_CFG_SYSCLK_ILO1_ENABLED 1
+#define CY_CFG_SYSCLK_ILO1_HIBERNATE true
+#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH6_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH6_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH6_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0
+#define CY_CFG_SYSCLK_PLL0_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 62
+#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 2
+#define CY_CFG_SYSCLK_PLL0_FRAC_DIV 8388608
+#define CY_CFG_SYSCLK_PLL0_FRAC_DITHER_EN false
+#define CY_CFG_SYSCLK_PLL0_FRAC_EN true
+#define CY_CFG_SYSCLK_PLL0_LF_MODE false
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 250000000
+#define CY_CFG_SYSCLK_PLL1_ENABLED 1
+#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 73
+#define CY_CFG_SYSCLK_PLL1_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 3
+#define CY_CFG_SYSCLK_PLL1_FRAC_DIV 8388608
+#define CY_CFG_SYSCLK_PLL1_FRAC_DITHER_EN false
+#define CY_CFG_SYSCLK_PLL1_FRAC_EN true
+#define CY_CFG_SYSCLK_PLL1_LF_MODE false
+#define CY_CFG_SYSCLK_PLL1_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 196000000
+#define CY_CFG_SYSCLK_PLL2_ENABLED 1
+#define CY_CFG_SYSCLK_PLL2_FEEDBACK_DIV 36
+#define CY_CFG_SYSCLK_PLL2_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL2_OUTPUT_DIV 2
+#define CY_CFG_SYSCLK_PLL2_LF_MODE false
+#define CY_CFG_SYSCLK_PLL2_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+#define CY_CFG_SYSCLK_PLL2_OUTPUT_FREQ 144000000
+#define CY_CFG_SYSCLK_PLL3_ENABLED 1
+#define CY_CFG_SYSCLK_PLL3_FEEDBACK_DIV 25
+#define CY_CFG_SYSCLK_PLL3_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL3_OUTPUT_DIV 2
+#define CY_CFG_SYSCLK_PLL3_LF_MODE false
+#define CY_CFG_SYSCLK_PLL3_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+#define CY_CFG_SYSCLK_PLL3_OUTPUT_FREQ 100000000
+#define CY_CFG_SYSCLK_WCO_ENABLED 1
+#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT21
+#define CY_CFG_SYSCLK_WCO_IN_PIN 0U
+#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT21
+#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U
+#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED
+#define CY_CFG_PWR_ENABLED 1
+#define CY_CFG_PWR_INIT 1
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_REGULATOR_MODE_MIN false
+#define CY_CFG_PWR_USING_ULP 0
+
+#if (!defined(CY_DEVICE_SECURE))
+    static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig = 
+    {
+        .fllMult = 500U,
+        .refDiv = 40U,
+        .ccoRange = CY_SYSCLK_FLL_CCO_RANGE2,
+        .enableOutputDiv = true,
+        .lockTolerance = 10U,
+        .igain = 9U,
+        .pgain = 0U,
+        .settlingCount = 8U,
+        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+        .cco_Freq = 235U,
+    };
+#endif //(!defined(CY_DEVICE_SECURE))
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj = 
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 0U,
+        .channel_num = 0U,
+    };
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj = 
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 1U,
+        .channel_num = 0U,
+    };
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj = 
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 2U,
+        .channel_num = 0U,
+    };
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj = 
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 3U,
+        .channel_num = 0U,
+    };
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj = 
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 4U,
+        .channel_num = 0U,
+    };
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj = 
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 5U,
+        .channel_num = 0U,
+    };
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj = 
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 6U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_0_pllConfig = 
+{
+    .feedbackDiv = 62,
+    .referenceDiv = 1,
+    .outputDiv = 2,
+    .lfMode = false,
+    .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+    .fracDiv = 8388608,
+    .fracDitherEn = false,
+    .fracEn = true,
+};
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll400m_1_pllConfig = 
+{
+    .feedbackDiv = 73,
+    .referenceDiv = 1,
+    .outputDiv = 3,
+    .lfMode = false,
+    .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+    .fracDiv = 8388608,
+    .fracDitherEn = false,
+    .fracEn = true,
+};
+#if (!defined(CY_DEVICE_SECURE))
+    static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig = 
+    {
+        .feedbackDiv = 36,
+        .referenceDiv = 1,
+        .outputDiv = 2,
+        .lfMode = false,
+        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+    };
+    static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = 
+    {
+        .feedbackDiv = 25,
+        .referenceDiv = 1,
+        .outputDiv = 2,
+        .lfMode = false,
+        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+    };
+#endif //(!defined(CY_DEVICE_SECURE))
+
+__WEAK void cycfg_ClockStartupError(uint32_t error)
+{
+    (void)error; /* Suppress the compiler warning */
+    while(1);
+}
+#if !defined (CY_CFG_SYSCLK_ILO0_ENABLED)
+    __STATIC_INLINE void Cy_SysClk_Ilo0DeInit()
+    {
+        if(Cy_SysPm_IsBgRefCtrl())
+        {
+            Cy_SysPm_BgRefCtrl(false);
+            Cy_WDT_Unlock();
+            Cy_SysClk_IloSrcDisable(0);
+            Cy_SysClk_IloSrcHibernateOn(0, false);
+            Cy_WDT_Lock();
+            Cy_SysPm_BgRefCtrl(true);
+        }
+        else
+        {
+            Cy_WDT_Unlock();
+            Cy_SysClk_IloSrcDisable(0);
+            Cy_SysClk_IloSrcHibernateOn(0, false);
+            Cy_WDT_Lock();
+        }
+    }
+#endif //!defined (CY_CFG_SYSCLK_ILO0_ENABLED)
+#if !defined (CY_CFG_SYSCLK_ILO1_ENABLED)
+    __STATIC_INLINE void Cy_SysClk_Ilo1DeInit()
+    {
+        Cy_SysClk_IloSrcDisable(1);
+        Cy_SysClk_IloSrcHibernateOn(1, false);
+    }
+#endif //!defined (CY_CFG_SYSCLK_ILO1_ENABLED)
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_FllDeInit()
+    {
+        Cy_SysClk_FllDisable();
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkBakInit()
+    {
+        Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_ClkFast_0_Init()
+{
+    Cy_SysClk_ClkFastSrcSetDivider(0, CY_CFG_SYSCLK_CLKFAST_0_INT_DIVIDER, CY_CFG_SYSCLK_CLKFAST_0_FRAC_DIVIDER);
+}
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_FllInit()
+    {
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+        }
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+        }
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
+{
+    Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF0, false);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF1, false);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF2, false);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF3, false);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF4, false);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf5Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF5, CY_CFG_SYSCLK_CLKHF5_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF5, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF5, false);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF5);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf6Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF6, CY_CFG_SYSCLK_CLKHF6_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF6, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF6, false);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF6);
+}
+__STATIC_INLINE void Cy_SysClk_ClkHf7Init()
+{
+    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF7, CY_CFG_SYSCLK_CLKHF7_CLKPATH);
+    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF7, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    Cy_SysClk_ClkHfDirectSel(CY_CFG_SYSCLK_CLKHF7, false);
+    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF7);
+}
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_Ilo0Init()
+    {
+        /* The WDT is unlocked in the default startup code */
+        Cy_SysClk_IloSrcEnable(0);
+        Cy_SysClk_IloSrcHibernateOn(0, true);
+    }
+    __STATIC_INLINE void Cy_SysClk_Ilo1Init()
+    {
+        /* The WDT is unlocked in the default startup code */
+        Cy_SysClk_IloSrcEnable(1);
+        Cy_SysClk_IloSrcHibernateOn(1, true);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_ClkLfInit()
+{
+    /* The WDT is unlocked in the default startup code */
+    Cy_SysClk_ClkLfSetSource(CY_CFG_SYSCLK_CLKLF_SOURCE);
+}
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
+    {
+        Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkPath1Init()
+    {
+        Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkPath2Init()
+    {
+        Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkPath3Init()
+    {
+        Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
+    {
+        Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkPath5Init()
+    {
+        Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE);
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkPath6Init()
+    {
+        Cy_SysClk_ClkPathSetSource(6U, CY_CFG_SYSCLK_CLKPATH6_SOURCE);
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkPeriInit()
+    {
+        Cy_SysClk_ClkPeriSetDivider(0U);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void Cy_SysClk_Pll0Init()
+{
+    Cy_SysClk_PllDisable(SRSS_PLL_400M_0_PATH_NUM);
+
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_400M_0_PATH_NUM, &srss_0_clock_0_pll400m_0_pllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_400M_0_PATH_NUM, 10000u))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+}
+__STATIC_INLINE void Cy_SysClk_Pll1Init()
+{
+    Cy_SysClk_PllDisable(SRSS_PLL_400M_1_PATH_NUM);
+
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_400M_1_PATH_NUM, &srss_0_clock_0_pll400m_1_pllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_400M_1_PATH_NUM, 10000u))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+}
+__STATIC_INLINE void Cy_SysClk_Pll2Init()
+{
+    Cy_SysClk_PllDisable(SRSS_PLL_200M_0_PATH_NUM);
+
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_200M_0_PATH_NUM, &srss_0_clock_0_pll_0_pllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_200M_0_PATH_NUM, 10000u))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+}
+__STATIC_INLINE void Cy_SysClk_Pll3Init()
+{
+    Cy_SysClk_PllDisable(SRSS_PLL_200M_1_PATH_NUM);
+
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(SRSS_PLL_200M_1_PATH_NUM, &srss_0_clock_0_pll_1_pllConfig))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_PLL_200M_1_PATH_NUM, 10000u))
+    {
+        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+    }
+}
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_WcoInit()
+    {
+        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT21, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
+        }
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+__STATIC_INLINE void init_cycfg_power(void)
+{
+    /* **Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD** */
+    #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+        #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+            if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+            {
+                Cy_SysLib_ResetBackupDomain();
+                Cy_SysClk_IloDisable();
+                Cy_SysClk_IloInit();
+            }
+        #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
+    #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+    /* **System Active Low Power Profile(LPACTIVE/LPSLEEP) Configuration** */
+    #if (CY_CFG_PWR_SYS_LP_PROFILE_MODE)
+        Cy_SysPm_SystemLpActiveEnter();
+    #endif /* CY_CFG_PWR_SYS_ACTIVE_MODE */
+
+    /* **System Regulators Low Current Configuration** */
+    #if CY_CFG_PWR_REGULATOR_MODE_MIN
+        Cy_SysPm_SystemSetMinRegulatorCurrent();
+    #else
+        Cy_SysPm_SystemSetNormalRegulatorCurrent();
+    #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
+
+}
+
+
+void init_cycfg_system(void)
+{
+    Cy_SysClk_PeriPclkAssignDivider(PCLK_CPUSS_CLOCK_TRACE_IN, CY_SYSCLK_DIV_8_BIT, 2U);
+    #ifdef CY_CFG_PWR_ENABLED
+        #ifdef CY_CFG_PWR_INIT
+            init_cycfg_power();
+        #else
+            #warning Power system will not be configured. Update power personality to v1.20 or later.
+        #endif /* CY_CFG_PWR_INIT */
+    #endif /* CY_CFG_PWR_ENABLED */
+    
+        /* Disable FLL */
+        Cy_SysClk_FllDeInit();
+    
+    #ifdef CY_CFG_SYSCLK_ILO0_ENABLED
+        Cy_SysClk_Ilo0Init();
+    #else
+        Cy_SysClk_Ilo0DeInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_ILO1_ENABLED
+        Cy_SysClk_Ilo1Init();
+    #else
+        Cy_SysClk_Ilo1DeInit();
+    #endif
+    
+    /* Enable all source clocks */
+    #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+        Cy_SysClk_PiloInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+        Cy_SysClk_WcoInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+        Cy_SysClk_EcoInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+        Cy_SysClk_ClkLfInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+        Cy_SysClk_ExtClkInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+        Cy_SysClk_AltHfInit();
+    #endif
+    
+        #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+            Cy_SysClk_ClkPeriInit();
+        #endif
+    
+    /* Configure Path Clocks */
+    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+        Cy_SysClk_ClkPath1Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+        Cy_SysClk_ClkPath2Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+        Cy_SysClk_ClkPath3Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+        Cy_SysClk_ClkPath4Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+        Cy_SysClk_ClkPath5Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+        Cy_SysClk_ClkPath6Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+        Cy_SysClk_ClkPath7Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+        Cy_SysClk_ClkPath8Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+        Cy_SysClk_ClkPath9Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+        Cy_SysClk_ClkPath10Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+        Cy_SysClk_ClkPath11Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+        Cy_SysClk_ClkPath12Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+        Cy_SysClk_ClkPath13Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+        Cy_SysClk_ClkPath14Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+        Cy_SysClk_ClkPath15Init();
+    #endif
+    
+    /* Configure and enable PLLs */
+    #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+        Cy_SysClk_Pll0Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+        Cy_SysClk_Pll1Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
+        Cy_SysClk_Pll2Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
+        Cy_SysClk_Pll3Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
+        Cy_SysClk_Pll4Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
+        Cy_SysClk_Pll5Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
+        Cy_SysClk_Pll6Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
+        Cy_SysClk_Pll7Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
+        Cy_SysClk_Pll8Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
+        Cy_SysClk_Pll9Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
+        Cy_SysClk_Pll10Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
+        Cy_SysClk_Pll11Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
+       Cy_SysClk_Pll12Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
+        Cy_SysClk_Pll13Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
+        Cy_SysClk_Pll14Init();
+    #endif
+    
+    /* Configure HF clocks */
+    #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+        Cy_SysClk_ClkHf1Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+        Cy_SysClk_ClkHf2Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+        Cy_SysClk_ClkHf3Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+        Cy_SysClk_ClkHf4Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+        Cy_SysClk_ClkHf5Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+        Cy_SysClk_ClkHf6Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+        Cy_SysClk_ClkHf7Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+        Cy_SysClk_ClkHf8Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+        Cy_SysClk_ClkHf9Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+        Cy_SysClk_ClkHf10Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+        Cy_SysClk_ClkHf11Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+        Cy_SysClk_ClkHf12Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+        Cy_SysClk_ClkHf13Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+        Cy_SysClk_ClkHf14Init();
+    #endif
+    #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+        Cy_SysClk_ClkHf15Init();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+        Cy_SysClk_ClkAltSysTickInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+        Cy_SysClk_ClkPumpInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+        Cy_SysClk_ClkBakInit();
+    #endif
+    
+    /* Configure default enabled clocks */
+    #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+        Cy_SysClk_IloInit();
+    #endif
+    
+    #ifndef CY_CFG_SYSCLK_IMO_ENABLED
+        #error the IMO must be enabled for proper chip operation
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+        Cy_SysClk_MfoInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+        Cy_SysClk_ClkMfInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+        Cy_SysClk_ClkPath0Init();
+    #endif
+    /* Configure and enable FLL */
+    #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+        Cy_SysClk_FllInit();
+    #endif
+    
+    Cy_SysClk_ClkHf0Init();
+    
+    #ifdef CY_CFG_SYSCLK_CLKFAST_0_ENABLED
+        Cy_SysClk_ClkFast_0_Init();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_CLKFAST_1_ENABLED
+        Cy_SysClk_ClkFast_1_Init();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+        Cy_SysClk_ClkSlowInit();
+    #endif
+    
+    #ifdef CY_CFG_SYSCLK_CLKMEM_ENABLED
+        Cy_SysClk_ClkMemInit();
+    #endif
+    
+#if defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
+        Cy_SysClk_EcoPrescalerInit();
+#endif //defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
+    /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+    SystemCoreClockUpdate();
+}
+
+void reserve_cycfg_system(void)
+{
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_6_obj);
+#endif //defined (CY_USING_HAL)
+}
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
new file mode 100644
index 0000000..f66c1bb
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
@@ -0,0 +1,127 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Configurator Backend 3.0.0
+* device-db 4.2.0.3480
+* mtb-pdl-cat1 3.3.0.21979
+*
+********************************************************************************
+* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_wdt.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
+#define srss_0_clock_0_hfclk_1_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF1 1UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH_NUM 1UL
+#define srss_0_clock_0_hfclk_2_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF2 2UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 2UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 3UL
+#define srss_0_clock_0_hfclk_4_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF4 4UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 4UL
+#define srss_0_clock_0_hfclk_5_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF5 5UL
+#define CY_CFG_SYSCLK_CLKHF5_CLKPATH_NUM 5UL
+#define srss_0_clock_0_hfclk_6_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF6 6UL
+#define CY_CFG_SYSCLK_CLKHF6_CLKPATH_NUM 5UL
+#define srss_0_clock_0_hfclk_7_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF7 7UL
+#define CY_CFG_SYSCLK_CLKHF7_CLKPATH_NUM 5UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_ilo_1_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_ILO
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_pathmux_5_ENABLED 1U
+#define srss_0_clock_0_pathmux_6_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll400m_0_ENABLED 1U
+#define srss_0_clock_0_pll400m_1_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_pll_1_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP_RAM 0x11UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP_OFF 0x12UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_LP_PROFILE_MODE 0
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj;
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_6_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_system(void);
+void reserve_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */
diff --git a/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg b/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg
new file mode 100644
index 0000000..24b90b9
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/qspi_config.cfg
@@ -0,0 +1,29 @@
+################################################################################
+# File Name: qspi_config.cfg
+#
+# Description:
+# This file contains a SMIF Bank layout for use with OpenOCD.
+# This file was automatically generated and should not be modified.
+# QSPI Configurator: 4.0.0.974
+#
+################################################################################
+# Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+set SMIF_BANKS {
+  0 {addr 0x60000000 size 0x800000 psize 0x0000100 esize 0x0001000}
+}
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct
new file mode 100644
index 0000000..8627ef0
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/linker.sct
@@ -0,0 +1,115 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file xmc7200d_x8384_cm0plus.sct
+;* \version 1.0
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM0+ core.
+; You can change the memory allocation by editing the RAM and Flash defines.
+; Your changes must be aligned with the corresponding defines for the CM7 core in 'xxx_cm7.sct',
+; where 'xx' is the device group; for example, 'xmc7200d_x8384_cm7.sct'.
+
+#define SRAM_START_RESERVE              0
+#define SRAM_PRIVATE_FOR_SROM           0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
+#define STACK_SIZE                      0x1000
+#define RAMVECTORS_ALIGNMENT            128
+
+; SRAM reservations
+#define SRAM_BASE_ADDRESS               0x28000000  /* SRAM START */
+#define CM0PLUS_SRAM_RESERVE            0x00020000
+#define BASE_SRAM_CM0P                  SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
+#define SIZE_SRAM_CM0P                  CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
+#define SRAM_CM0P_START                 BASE_SRAM_CM0P
+#define SRAM_CM0P_SIZE                  SIZE_SRAM_CM0P
+
+; Code flash reservations
+#define CODE_FLASH_BASE_ADDRESS         0x10000000  /* FLASH START */
+#define CM0PLUS_CODE_FLASH_RESERVE      0x00080000
+#define BASE_CODE_FLASH_CM0P            CODE_FLASH_BASE_ADDRESS
+#define SIZE_CODE_FLASH_CM0P            CM0PLUS_CODE_FLASH_RESERVE
+#define CODE_FLASH_CM0P_START           BASE_CODE_FLASH_CM0P
+#define CODE_FLASH_CM0P_SIZE            SIZE_CODE_FLASH_CM0P
+
+; Cortex-M0+ application flash area
+LR_IROM1 CODE_FLASH_CM0P_START CODE_FLASH_CM0P_SIZE
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS SRAM_CM0P_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+        * (.bss.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY SRAM_CM0P_START+SRAM_CM0P_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
+    {
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (SRAM_CM0P_START+SRAM_CM0P_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+}
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_cm0plus.s b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_cm0plus.s
new file mode 100644
index 0000000..55722ca
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_cm0plus.s
@@ -0,0 +1,213 @@
+;/**************************************************************************//**
+; * @file     startup_cm0plus.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0plus Device
+; * @version  V1.0.1
+; * @date     23. July 2019
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+
+
+;<h> Stack Configuration
+;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;</h>
+
+CPUSS_RAM0_CTL0     EQU 0x40201300
+CPUSS_RAM1_CTL0     EQU 0x40201380
+CPUSS_RAM2_CTL0     EQU 0x402013a0
+
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA     RESET, DATA, READONLY
+                EXPORT   __Vectors
+                EXPORT   __Vectors_End
+                EXPORT   __Vectors_Size
+
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length|
+
+__Vectors       DCD      |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length|         ;     Top of Stack
+                DCD      Reset_Handler                       ;     Reset Handler
+                DCD      NMI_Handler                         ; -14 NMI Handler
+                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      SVC_Handler                         ;  -5 SVCall Handler
+                DCD      0                                   ;     Reserved
+                DCD      0                                   ;     Reserved
+                DCD      PendSV_Handler                      ;  -2 PendSV Handler
+                DCD      SysTick_Handler                     ;  -1 SysTick Handler
+
+                ; Interrupts
+                DCD     Default_Intr_Handler                   ; CPU User Interrupt #0
+                DCD     Default_Intr_Handler                   ; CPU User Interrupt #1
+                DCD     CM0P_CpuIntr2_Handler                   ; CPU User Interrupt #2
+                DCD     CM0P_CpuIntr3_Handler                   ; CPU User Interrupt #3
+                DCD     CM0P_CpuIntr4_Handler                   ; CPU User Interrupt #4
+                DCD     CM0P_CpuIntr5_Handler                   ; CPU User Interrupt #5
+                DCD     CM0P_CpuIntr6_Handler                   ; CPU User Interrupt #6
+                DCD     CM0P_CpuIntr7_Handler                   ; CPU User Interrupt #7
+                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #0
+                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #1
+                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #2
+                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #3
+                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #4
+                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #5
+                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #6
+                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #7
+
+__Vectors_End
+__Vectors_Size  EQU      __Vectors_End - __Vectors
+                EXPORT __ramVectors
+                AREA    RESET_RAM, READWRITE, NOINIT
+__ramVectors    SPACE   __Vectors_Size
+
+                AREA     |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT   Reset_Handler             [WEAK]
+                IMPORT   SystemInit
+                IMPORT   CyMain
+
+                ; Disable global interrupts
+                CPSID I
+
+                ; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
+                ; Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet
+                ; Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
+                ; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
+                MOVS r0, #1
+                LSLS r0, r0, #19
+                LDR  r1, =CPUSS_RAM0_CTL0
+                LDR  r2, [r1]
+                ORRS r2, r0
+                STR  r2, [r1]
+                LDR  r1, =CPUSS_RAM1_CTL0
+                LDR  r2, [r1]
+                ORRS r2, r0
+                STR  r2, [r1]
+                LDR  r1, =CPUSS_RAM2_CTL0
+                LDR  r2, [r1]
+                ORRS r2, r0
+                STR  r2, [r1]
+
+                ; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration,
+                ; because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device
+                ; Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted)
+                LDR     r3, =|Image$$ARM_LIB_STACK$$ZI$$Base|
+                LDR     r1, =|Image$$ARM_LIB_STACK$$ZI$$Length|
+                ADD     r1, r1, r3 ; r1 = stack top
+                MOV     r0, r1
+                LDR     r3, =0x100
+                SUBS    r0, r0, r3 ; r0 = stack offset
+
+                MOVS    r2, #0  ; clear value
+                MOVS    r3, #0  ; clear value
+loopstackclean
+                STM     r0!, {r2, r3}
+                CMP     r0, r1
+                BNE     loopstackclean
+
+                LDR      R0, =SystemInit
+                BLX      R0
+                LDR      R0, =CyMain
+                BX       R0
+                ENDP
+
+Default_Handler     PROC
+                    EXPORT  Default_Handler                         [WEAK]
+                    EXPORT  CM0P_CpuIntr2_Handler                   [WEAK]
+                    EXPORT  CM0P_CpuIntr3_Handler                   [WEAK]
+                    EXPORT  CM0P_CpuIntr4_Handler                   [WEAK]
+                    EXPORT  CM0P_CpuIntr5_Handler                   [WEAK]
+                    EXPORT  CM0P_CpuIntr6_Handler                   [WEAK]
+                    EXPORT  CM0P_CpuIntr7_Handler                   [WEAK]
+
+CM0P_CpuIntr2_Handler
+CM0P_CpuIntr3_Handler
+CM0P_CpuIntr4_Handler
+CM0P_CpuIntr5_Handler
+CM0P_CpuIntr6_Handler
+CM0P_CpuIntr7_Handler
+                    B       .
+                    ENDP
+
+Cy_SysLib_FaultHandler PROC
+                    EXPORT  Cy_SysLib_FaultHandler    [WEAK]
+                    B       .
+                    ENDP
+
+; The default macro is not used for HardFault_Handler
+; because this results in a poor debug illusion.
+HardFault_Handler   PROC
+                    EXPORT HardFault_Handler          [WEAK]
+                    movs r0, #4
+                    mov r1, LR
+                    tst r0, r1
+                    beq L_MSP
+                    mrs r0, PSP
+                    bl L_API_call
+L_MSP
+                    mrs r0, MSP
+L_API_call
+                    bl Cy_SysLib_FaultHandler
+                    ENDP
+
+; Macro to define default exception/interrupt handlers.
+; Default handler are weak symbols with an endless loop.
+; They can be overwritten by real handlers.
+                MACRO
+                Set_Default_Handler  $Handler_Name
+$Handler_Name   PROC
+                EXPORT   $Handler_Name             [WEAK]
+                B        .
+                ENDP
+                MEND
+
+
+; Default exception/interrupt handler
+
+                Set_Default_Handler  NMI_Handler
+                Set_Default_Handler  SVC_Handler
+                Set_Default_Handler  PendSV_Handler
+                Set_Default_Handler  SysTick_Handler
+
+                Set_Default_Handler  Default_Intr_Handler
+
+
+                ALIGN
+
+
+                END
+
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld
new file mode 100644
index 0000000..96d2f68
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld
@@ -0,0 +1,399 @@
+/***************************************************************************//**
+* \file xmc7200d_x8384_cm0plus.ld
+* \version 1.0.0
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+GROUP(-lgcc -lc -lnosys )
+SEARCH_DIR(.)
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM0+ SRAM */
+STACK_SIZE = 0x1000;
+RAMVECTORS_ALIGNMENT                = 128;
+
+sram_start_reserve                  = 0;
+sram_private_for_srom               = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
+
+cm0plus_sram_reserve                = 0x00020000; /* cm0 sram size */
+cm0plus_code_flash_reserve          = 0x00080000; /* cm7_0 sram size */
+cm7_0_code_flash_reserve            = 0x00200000;
+
+sram_base_address                   = 0x28000000;
+code_flash_base_address             = 0x10000000;
+code_flash_total_size               = 0x00080000;
+
+_base_SRAM_CM0P                     = sram_base_address + sram_start_reserve + sram_private_for_srom;
+_size_SRAM_CM0P                     = cm0plus_sram_reserve - sram_start_reserve - sram_private_for_srom;
+_base_CODE_FLASH_CM0P               = code_flash_base_address;
+_size_CODE_FLASH_CM0P               = cm0plus_code_flash_reserve;
+
+/* Fixed Addesses */
+_base_WORK_FLASH                    = 0x14000000;
+_size_WORK_FLASH                    = 0x00040000;   /* 256K Work flash */
+_base_SFLASH_USER_DATA              = 0x17000800;
+_size_SFLASH_USER_DATA              = 0x00000800;
+_base_SFLASH_NAR                    = 0x17001A00;
+_size_SFLASH_NAR                    = 0x00000200;
+_base_SFLASH_PUB_KEY                = 0x17006400;
+_size_SFLASH_PUB_KEY                = 0x00000C00;
+_base_SFLASH_APP_PROT               = 0x17007600;
+_size_SFLASH_APP_PROT               = 0x00000200;
+_base_SFLASH_TOC2                   = 0x17007C00;
+_size_SFLASH_TOC2                   = 0x00000200;
+_base_XIP                           = 0x60000000;
+_size_XIP                           = 0x08000000;
+_base_EFUSE                         = 0x90700000;
+_size_EFUSE                         = 0x00100000;
+
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+    /* The ram and flash regions control RAM and flash memory allocation for the CM33 core.
+     */
+    cm0_ram         (rxw)       : ORIGIN = _base_SRAM_CM0P,             LENGTH = _size_SRAM_CM0P
+    cm0_flash       (rx)        : ORIGIN = _base_CODE_FLASH_CM0P,       LENGTH = _size_CODE_FLASH_CM0P
+
+    /* This is a 256K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+     * You can assign sections to this memory region for only one of the cores.
+     */
+    em_eeprom           (rw)        : ORIGIN = _base_WORK_FLASH,            LENGTH = _size_WORK_FLASH           /* WORK flash */
+
+    /* The following regions define device specific memory regions and must not be changed. */
+    sflash_user_data    (rx)        : ORIGIN = _base_SFLASH_USER_DATA,      LENGTH = _size_SFLASH_USER_DATA     /* Supervisory flash: User data */
+    sflash_nar          (rx)        : ORIGIN = _base_SFLASH_NAR,            LENGTH = _size_SFLASH_NAR            /* Supervisory flash: Normal Access Restrictions (NAR) */
+    sflash_public_key   (rx)        : ORIGIN = _base_SFLASH_PUB_KEY,        LENGTH = _size_SFLASH_PUB_KEY       /* Supervisory flash: Public Key */
+    sflash_app_prot     (rx)        : ORIGIN = _base_SFLASH_APP_PROT,       LENGTH = _size_SFLASH_APP_PROT
+    sflash_toc_2        (rx)        : ORIGIN = _base_SFLASH_TOC2,           LENGTH = _size_SFLASH_TOC2          /* Supervisory flash: Table of Content # 2 */
+    xip                 (rx)        : ORIGIN = _base_XIP,                   LENGTH = _size_XIP                  /* XIP: 128 MB */
+    efuse               (rx)        : ORIGIN = _base_EFUSE,                 LENGTH = _size_EFUSE                /* 1MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+SECTIONS
+{
+    .cy_app_header :
+    {
+        __app_header_start = .;
+        KEEP(*(.cy_app_header))
+    } > cm0_flash
+    
+    /* Cortex-M0+ application flash area */
+    .text :
+    {
+        /* Cortex-M0+ flash vector table must be aligned to 1024 bytes */
+        . = ALIGN(1024);
+        __Vectors = . ;
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        . = ALIGN(4);
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        /* Read-only code (constants). */
+        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+        KEEP(*(.eh_frame*))
+    } > cm0_flash
+
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > cm0_flash
+
+    __exidx_start = .;
+
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > cm0_flash
+    __exidx_end = .;
+
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+
+        /* Copy data section to RAM */
+        LONG (__etext)                                      /* From */
+        LONG (__data_start__)                               /* To   */
+        LONG ((__data_end__ - __data_start__)/4)            /* Size */
+
+        __copy_table_end__ = .;
+    } > cm0_flash
+
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG ((__bss_end__ - __bss_start__)/4)
+        __zero_table_end__ = .;
+    } > cm0_flash
+
+    __etext =  . ;
+
+
+    .ramVectors (NOLOAD) :
+    {
+        . = ALIGN(RAMVECTORS_ALIGNMENT);
+        __ram_vectors_start__ = .;
+        KEEP(*(.ram_vectors))
+        __ram_vectors_end__   = .;
+    } > cm0_ram
+
+
+    .data __ram_vectors_end__ :
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+
+        KEEP(*(.cy_ramfunc*))
+        . = ALIGN(4);
+
+        __data_end__ = .;
+
+    } > cm0_ram AT>cm0_flash
+
+
+    /* Place variables in the section that should not be initialized during the
+    *  device startup.
+    */
+    .noinit (NOLOAD) : ALIGN(8)
+    {
+      KEEP(*(.noinit))
+    } > cm0_ram
+
+
+    /* The uninitialized global or static variables are placed in this section.
+    *
+    * The NOLOAD attribute tells linker that .bss section does not consume
+    * any space in the image. The NOLOAD attribute changes the .bss type to
+    * NOBITS, and that  makes linker to A) not allocate section in memory, and
+    * A) put information to clear the section with all zeros during application
+    * loading.
+    *
+    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+    * This  makes linker to A) allocate zeroed section in memory, and B) copy
+    * this section to RAM during application loading.
+    */
+    .bss (NOLOAD):
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > cm0_ram
+
+
+    .heap (NOLOAD):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        . = ORIGIN(cm0_ram) + LENGTH(cm0_ram) - STACK_SIZE;
+        __HeapLimit = .;
+    } > cm0_ram
+
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        KEEP(*(.stack*))
+    } > cm0_ram
+
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(cm0_ram) + LENGTH(cm0_ram);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+    /* Used for the digital signature of the secure application.
+    * The size of the section depends on the required data size. */
+    .cy_app_signature :
+    {
+        . = ALIGN(4);
+        __app_image_end = .;
+        KEEP(*(.cy_app_signature))
+    } > cm0_flash
+
+    /* Emulated EEPROM Flash area */
+    .cy_em_eeprom :
+    {
+        KEEP(*(.cy_em_eeprom))
+    } > em_eeprom
+
+
+    /* Supervisory Flash: User data */
+    .cy_sflash_user_data :
+    {
+        KEEP(*(.cy_sflash_user_data))
+    } > sflash_user_data
+
+
+    /* Supervisory Flash: Normal Access Restrictions (NAR) */
+    .cy_sflash_nar :
+    {
+        KEEP(*(.cy_sflash_nar))
+    } > sflash_nar
+
+
+    /* Supervisory Flash: Public Key */
+    .cy_sflash_public_key :
+    {
+        KEEP(*(.cy_sflash_public_key))
+    } > sflash_public_key
+
+
+    /* Supervisory Flash: Table of Content # 2 */
+    .cy_toc_part2 :
+    {
+        KEEP(*(.cy_toc_part2))
+    } > sflash_toc_2
+
+    /* Places the code in the Execute in Place (XIP) section. See the smif driver
+    *  documentation for details.
+    */
+    cy_xip :
+    {
+        __cy_xip_start = .;
+        KEEP(*(.cy_xip))
+        __cy_xip_end = .;
+    } > xip
+
+
+    /* eFuse */
+    .cy_efuse :
+    {
+        KEEP(*(.cy_efuse))
+    } > efuse
+}
+
+/*============================================================
+ * Symbols for use by secure config
+ *============================================================
+ */
+__secure_object_size = __app_image_end - __app_header_start;
+__app_header_vtable_offset = __Vectors - __app_header_start;
+
+/*============================================================
+ * Symbols for use by cymcuelftool
+ *============================================================
+ */
+__cy_app_verify_start = ORIGIN(cm0_flash);
+__cy_app_verify_length = __secure_object_size;
+
+/* Check application header placement */
+ASSERT(__app_header_start == ORIGIN(cm0_flash), "Incorrect app header placement")
+
+/* EOF */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_cm0plus.S b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_cm0plus.S
new file mode 100644
index 0000000..7765114
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_cm0plus.S
@@ -0,0 +1,200 @@
+/**************************************************************************//**
+ * @file     startup_cm0plus.S
+ * @brief    CMSIS-Core(M) Device Startup File for Cortex-M0plus Device
+ * @version  V2.2.0
+ * @date     26. May 2021
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#define CPUSS_RAM0_CTL0     0x40201300
+#define CPUSS_RAM1_CTL0     0x40201380
+#define CPUSS_RAM2_CTL0     0x402013a0
+
+
+                .syntax  unified
+                .arch    armv6-m
+
+                .section .vectors
+                .align   2
+                .globl   __Vectors
+                .globl   __Vectors_End
+                .globl   __Vectors_Size
+                .global  CM0P_CpuIntr2_Handler
+                .global  CM0P_CpuIntr3_Handler
+                .global  CM0P_CpuIntr4_Handler
+                .global  CM0P_CpuIntr5_Handler
+                .global  CM0P_CpuIntr6_Handler
+                .global  CM0P_CpuIntr7_Handler
+
+__Vectors:
+                .long    __StackTop                         /*     Top of Stack */
+                .long    Reset_Handler                      /*     Reset Handler */
+                .long    NMI_Handler                        /* -14 NMI Handler */
+                .long    HardFault_Handler                  /* -13 Hard Fault Handler */
+                .long    0                                  /*     Reserved */
+                .long    0                                  /*     Reserved */
+                .long    0                                  /*     Reserved */
+                .long    0                                  /*     Reserved */
+                .long    0                                  /*     Reserved */
+                .long    0                                  /*     Reserved */
+                .long    0                                  /*     Reserved */
+                .long    SVC_Handler                        /*  -5 SVCall Handler */
+                .long    0                                  /*     Reserved */
+                .long    0                                  /*     Reserved */
+                .long    PendSV_Handler                     /*  -2 PendSV Handler */
+                .long    SysTick_Handler                    /*  -1 SysTick Handler */
+
+                /* Interrupts */
+                .long    Default_Intr_Handler               /* CPU User Interrupt #0 */
+                .long    Default_Intr_Handler               /* CPU User Interrupt #1 */
+                .long    CM0P_CpuIntr2_Handler              /* CPU User Interrupt #2 */
+                .long    CM0P_CpuIntr3_Handler              /* CPU User Interrupt #3 */
+                .long    CM0P_CpuIntr4_Handler              /* CPU User Interrupt #4 */
+                .long    CM0P_CpuIntr5_Handler              /* CPU User Interrupt #5 */
+                .long    CM0P_CpuIntr6_Handler              /* CPU User Interrupt #6 */
+                .long    CM0P_CpuIntr7_Handler              /* CPU User Interrupt #7 */
+                .long    Default_Intr_Handler               /* Internal SW Interrupt #0 */
+                .long    Default_Intr_Handler               /* Internal SW Interrupt #1 */
+                .long    Default_Intr_Handler               /* Internal SW Interrupt #2 */
+                .long    Default_Intr_Handler               /* Internal SW Interrupt #3 */
+                .long    Default_Intr_Handler               /* Internal SW Interrupt #4 */
+                .long    Default_Intr_Handler               /* Internal SW Interrupt #5 */
+                .long    Default_Intr_Handler               /* Internal SW Interrupt #6 */
+                .long    Default_Intr_Handler               /* Internal SW Interrupt #7 */
+
+__Vectors_End:
+                .equ     __Vectors_Size, __Vectors_End - __Vectors
+                .size    __Vectors, . - __Vectors
+
+                .section .ram_vectors
+                .align 2
+                .globl __ramVectors
+__ramVectors:
+                .space  __Vectors_Size
+                .size   __ramVectors, . - __ramVectors
+
+                .thumb
+                .section .text
+                .align   2
+
+                .thumb_func
+                .type    Reset_Handler, %function
+                .globl   Reset_Handler
+                .extern  __cmsis_start
+                .fnstart
+Reset_Handler:
+                /* CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
+                 * Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet
+                 * Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
+                 * or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
+                 */
+                movs r0, #1
+                lsls r0, r0, #19
+                ldr  r1, =CPUSS_RAM0_CTL0
+                ldr  r2, [r1]
+                orrs r2, r0
+                str  r2, [r1]
+                ldr  r1, =CPUSS_RAM1_CTL0
+                ldr  r2, [r1]
+                orrs r2, r0
+                str  r2, [r1]
+                ldr  r1, =CPUSS_RAM2_CTL0
+                ldr  r2, [r1]
+                orrs r2, r0
+                str  r2, [r1]
+
+                /* Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration,
+                 * because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device
+                 * Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted)
+                 */
+                ldr     r0, =__StackTop-0x100
+                ldr     r1, =__StackTop
+                movs    r2, #0
+                movs    r3, #0
+loopstackclean:
+                stmia   r0!, {r2, r3}
+                cmp     r0, r1
+                bcc.n   loopstackclean
+
+                bl       SystemInit
+
+                bl       CyMain
+
+                .fnend
+                .size    Reset_Handler, . - Reset_Handler
+
+                .thumb_func
+                .type    Default_Handler, %function
+                .weak    Default_Handler
+Default_Handler:
+                b        .
+                .size    Default_Handler, . - Default_Handler
+                .weak    Cy_SysLib_FaultHandler
+                .type    Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+                b    .
+                .size    Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+                .type Fault_Handler, %function
+
+Fault_Handler:
+/*              Storing LR content for Creator call stack trace */
+                push {LR}
+                movs r0, #4
+                mov r1, LR
+                tst r0, r1
+                beq .L_MSP
+                mrs r0, PSP
+                b .L_API_call
+.L_MSP:
+                mrs r0, MSP
+/*              Compensation of stack pointer address due to pushing 4 bytes of LR */
+                adds r0, r0, #4
+.L_API_call:
+                bl Cy_SysLib_FaultHandler
+                b   .
+                .size    Fault_Handler, . - Fault_Handler
+
+                .macro    Def_Fault_Handler    fault_handler_name
+                .weak    \fault_handler_name
+                .set    \fault_handler_name, Fault_Handler
+                .endm
+
+/*              Macro to define default exception/interrupt handlers.
+ *              Default handler are weak symbols with an endless loop.
+ *              They can be overwritten by real handlers.
+ */
+                .macro   Def_Irq_Handler  Handler_Name
+                .weak    \Handler_Name
+                .set     \Handler_Name, Default_Handler
+                .endm
+
+/*              Default exception/interrupt handlers */
+                Def_Irq_Handler  NMI_Handler
+
+                Def_Fault_Handler    HardFault_Handler
+
+                Def_Irq_Handler  SVC_Handler
+                Def_Irq_Handler  PendSV_Handler
+                Def_Irq_Handler  SysTick_Handler
+                Def_Irq_Handler  Default_Intr_Handler
+
+                .end
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf
new file mode 100644
index 0000000..62813e2
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/linker.icf
@@ -0,0 +1,122 @@
+/*******************************************************************************
+* \file xmc7200d_x8384_cm0plus.icf
+* \version 1.0.0
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+define symbol RAMVECTORS_ALIGNMENT              = 128;
+
+define symbol sram_start_reserve                = 0;
+define symbol sram_private_for_srom             = 0x00000800; /* Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
+
+define symbol cm0plus_sram_reserve              = 0x00020000; /* cm0 sram size */
+define symbol cm0plus_code_flash_reserve        = 0x00080000; /* cm7_0 sram size */
+define symbol cm7_0_code_flash_reserve          = 0x00200000;
+
+define symbol sram_base_address                 = 0x28000000;
+define symbol code_flash_base_address           = 0x10000000;
+define symbol code_flash_total_size             = 0x00080000;
+
+define symbol ecc_init_width                    = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */
+
+define symbol cm0plus_heap_reserve              = 0x00001000;
+define symbol cm0plus_stack_reserve             = 0x00001000;
+
+define symbol heap_reserve                      = cm0plus_heap_reserve;
+define symbol stack_reserve                     = (cm0plus_stack_reserve + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */
+
+
+define symbol _base_SRAM_CM0P                   = sram_base_address + sram_start_reserve + sram_private_for_srom;
+define symbol _size_SRAM_CM0P                   = cm0plus_sram_reserve - sram_start_reserve - sram_private_for_srom;
+define symbol _base_CODE_FLASH_CM0P             = code_flash_base_address;
+define symbol _size_CODE_FLASH_CM0P             = cm0plus_code_flash_reserve;
+define symbol _base_CODE_FLASH_CM7_0            = code_flash_base_address + cm0plus_code_flash_reserve;
+define symbol _size_CODE_FLASH_CM7_0            = cm7_0_code_flash_reserve;
+define symbol _base_CODE_FLASH_CM7_1            = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
+define symbol _size_CODE_FLASH_CM7_1            = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
+
+/*============================================================
+ * Memory definitions
+ *============================================================
+ */
+
+define memory mem with size = 4G;
+
+define region SRAM                              = mem:[from _base_SRAM_CM0P          size _size_SRAM_CM0P           ];
+define region CODE_FLASH                        = mem:[from _base_CODE_FLASH_CM0P    size _size_CODE_FLASH_CM0P     ];
+define region CODE_FLASH_CM7_0                  = mem:[from _base_CODE_FLASH_CM7_0   size _size_CODE_FLASH_CM7_0    ];
+define region CODE_FLASH_CM7_1                  = mem:[from _base_CODE_FLASH_CM7_1   size _size_CODE_FLASH_CM7_1    ];
+
+/*============================================================
+ * Block definitions
+ *============================================================
+ */
+define block CSTACK         with alignment = 8, size = stack_reserve { };
+define block HEAP           with expanding size, alignment = 8, minimum size = heap_reserve { };
+define block HEAP_STACK     { block HEAP, last block CSTACK };
+
+/*============================================================
+ * Initialization
+ *============================================================
+ */
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*============================================================
+ * Placement
+ *============================================================
+ */
+
+/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
+/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */
+
+place at start of CODE_FLASH  { section .intvec };
+place in          CODE_FLASH  { readonly };
+
+place in          SRAM  { readwrite };
+place at end   of SRAM  { block HEAP_STACK };
+
+keep {  section .intvec  };
+
+/*============================================================
+ * Symbols for use by application
+ *============================================================
+ */
+/* The start of CM7_0/1 vector table is required by CM0+ application to correctly
+ * set CPUSS->CM7_0/1_VECTOR_TABLE_BASE register before releasing CM7_0 or CM7_1 from reset
+ */
+
+define exported symbol __ecc_init_sram_start_address = start(SRAM);
+define exported symbol __ecc_init_sram_end_address   = end(SRAM);
+
+/* EOF */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_cm0plus.s b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_cm0plus.s
new file mode 100644
index 0000000..16e9782
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_cm0plus.s
@@ -0,0 +1,370 @@
+;/**************************************************************************//**
+; * @file     startup_cm0plus.s
+; * @brief    CMSIS Core Device Startup File for
+; *           ARMCM0plus Device
+; * @version  V1.0.0
+; * @date     09. July 2018
+; ******************************************************************************/
+;/*
+; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+
+;************************************************************************
+;* Local definitions
+;************************************************************************
+
+; Set a sufficient startup stack size for correct operation of C startup code (startup.c)
+STARTUP_STACK_SIZE_DOUBLE_WORDS    EQU 32
+
+VTOR                               EQU 0xe000ed08
+
+CPUSS_RAM0_CTL0                    EQU 0x40201300
+CPUSS_RAM1_CTL0                    EQU 0x40201380
+CPUSS_RAM2_CTL0                    EQU 0x402013a0
+
+
+;************************************************************************
+;* Import symbols
+;************************************************************************
+
+        EXTERN  CM0P_CpuIntr2_Handler
+        EXTERN  CM0P_CpuIntr3_Handler
+        EXTERN  CM0P_CpuIntr4_Handler
+        EXTERN  CM0P_CpuIntr5_Handler
+        EXTERN  CM0P_CpuIntr6_Handler
+        EXTERN  CM0P_CpuIntr7_Handler
+        EXTERN  __iar_program_start
+        EXTERN  __iar_data_init3
+        EXTERN  __iar_dynamic_initialization
+        EXTERN  SystemInit
+        EXTERN  CyMain
+
+
+;************************************************************************
+;* Export symbols
+;************************************************************************
+
+        PUBLIC  __vector_table
+        PUBLIC  __vector_table_0x1c
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+        PUBLIC  __ramVectors
+        PUBLIC  Cy_u32StartupStackStartAddress
+        PUBLIC  Cy_u32StartupStackEndAddress
+
+
+;************************************************************************
+;* Vector Table and RAM Vector Table
+;************************************************************************
+
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        ; align to 256 byte, because CM0_VECTOR_TABLE_BASE register only supports address bits [31:8] (Note: for VTOR a 128-byte alignment would be ok)
+        SECTION .intvec:CODE:ROOT(8)
+        DATA
+
+__vector_table:
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+__vector_table_0x1c:
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     0
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External interrupts              PowerMode    Description
+
+        DCD     DefaultInt_Handler           ; DeepSleep    CPU User Interrupt #0 ; updated in RAM vector table with corresponding SROM vector table entry (after ROM-to-RAM copy)
+        DCD     DefaultInt_Handler           ; DeepSleep    CPU User Interrupt #1 ; updated in RAM vector table with corresponding SROM vector table entry (after ROM-to-RAM copy)
+        DCD     CM0P_CpuIntr2_Handler      ; DeepSleep    CPU User Interrupt #2
+        DCD     CM0P_CpuIntr3_Handler      ; DeepSleep    CPU User Interrupt #3
+        DCD     CM0P_CpuIntr4_Handler      ; DeepSleep    CPU User Interrupt #4
+        DCD     CM0P_CpuIntr5_Handler      ; DeepSleep    CPU User Interrupt #5
+        DCD     CM0P_CpuIntr6_Handler      ; DeepSleep    CPU User Interrupt #6
+        DCD     CM0P_CpuIntr7_Handler      ; DeepSleep    CPU User Interrupt #7
+
+        ; These IRQs can only be triggered by SW via NVIC regs
+        DCD     CpuUserInt8_Handler      ; Active       CPU User Interrupt #8
+        DCD     CpuUserInt9_Handler      ; Active       CPU User Interrupt #9
+        DCD     CpuUserInt10_Handler     ; Active       CPU User Interrupt #10
+        DCD     CpuUserInt11_Handler     ; Active       CPU User Interrupt #11
+        DCD     CpuUserInt12_Handler     ; Active       CPU User Interrupt #12
+        DCD     CpuUserInt13_Handler     ; Active       CPU User Interrupt #13
+        DCD     CpuUserInt14_Handler     ; Active       CPU User Interrupt #14
+        DCD     CpuUserInt15_Handler     ; Active       CPU User Interrupt #15
+__Vectors_End:
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+        ; use same alignment like vector table in ROM above (even though VTOR minimum requirement would be 128 bytes if not used in combination with CM0_VECTOR_TABLE_BASE register)
+        SECTION .intvec_ram:DATA:ROOT(8)
+__ramVectors:
+        DS8     __Vectors_Size
+
+
+;************************************************************************
+;* Start-up Code
+;************************************************************************
+
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler:
+
+; Disable global interrupts
+        CPSID   I
+
+; Update Vector Table Offset Register with address of user ROM table
+; (will be updated later to user RAM table address in C startup code)
+        LDR  r0, =__vector_table
+        LDR  r1, =VTOR
+        STR  r0, [r1]
+        DSB
+
+; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
+; Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet
+; Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
+; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
+        MOVS r0, #1
+        LSLS r0, r0, #19
+        LDR  r1, =CPUSS_RAM0_CTL0
+        LDR  r2, [r1]
+        ORRS r2, r0
+        STR  r2, [r1]
+        LDR  r1, =CPUSS_RAM1_CTL0
+        LDR  r2, [r1]
+        ORRS r2, r0
+        STR  r2, [r1]
+        LDR  r1, =CPUSS_RAM2_CTL0
+        LDR  r2, [r1]
+        ORRS r2, r0
+        STR  r2, [r1]
+
+; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration,
+; because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device
+; Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted)
+        MOVS r0, #0 ; clear value
+        MOVS r1, #0 ; clear value
+        LDR  r2, Cy_u32StartupStackStartAddress
+startup_stack_ecc_init_loop:
+        STM  r2!, {r0, r1}
+        CMP  r2, sp
+        BNE  startup_stack_ecc_init_loop
+; Call C startup code (no ANSI C context established yet!)
+        LDR   r0, =SystemInit
+        BLX   r0
+
+        LDR   r0, =CyMain
+        BLX   r0
+
+; Note: Control flow does not necessarily return here.
+; On some tool-chains (e.g. IAR) control flow will never return from
+; the system library.
+Cy_Main_Exited:
+        B    Cy_Main_Exited
+
+;************************************************************************
+;* Literal pool
+;************************************************************************
+
+        ALIGNROM 2
+
+        LTORG
+
+        DATA
+
+        ALIGNROM 2
+
+STARTUP_STACK_SIZE_BYTES    EQU (STARTUP_STACK_SIZE_DOUBLE_WORDS * 8)  ; Multiplication does not work in below data definition directive, so an additional define is created
+
+Cy_u32StartupStackStartAddress:
+        DCD (sfe(CSTACK) - STARTUP_STACK_SIZE_BYTES)
+
+Cy_u32StartupStackEndAddress:
+        DCD (sfe(CSTACK) - 1)
+
+
+
+;************************************************************************
+;* Default and weak implementation of interrupt handlers
+;************************************************************************
+
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+NMI_Handler:
+        B NMI_Handler
+
+;-----------------------------------------
+
+        PUBWEAK Cy_SysLib_FaultHandler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Cy_SysLib_FaultHandler:
+        B Cy_SysLib_FaultHandler
+
+;-----------------------------------------
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+HardFault_Handler:
+        IMPORT Cy_SysLib_FaultHandler
+        MOVS r0, #4
+        MOV  r1, lr
+        TST  r0, r1
+        BEQ  L_MSP
+        MRS  r0, PSP
+        B    L_API_call
+L_MSP
+        MRS  r0, MSP
+L_API_call
+        ; Storing LR content for Creator call stack trace
+        PUSH {lr}
+        LDR  r1, =Cy_SysLib_FaultHandler
+        BLX  r1
+
+;-----------------------------------------
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SVC_Handler:
+        B SVC_Handler
+
+;-----------------------------------------
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+PendSV_Handler:
+        B PendSV_Handler
+
+;-----------------------------------------
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+SysTick_Handler:
+        B SysTick_Handler
+
+
+;-----------------------------------------
+
+
+        PUBWEAK DefaultInt_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+DefaultInt_Handler:
+        B DefaultInt_Handler
+
+;-----------------------------------------
+
+        ; External interrupts
+        ; Traveo II CPU User Interrupts 0-7 handlers are defined in the project interrupt mapping file
+        ; Traveo II CPU User Interrupts 8-15 can only be used as SW interrupts and need to be defined by user (weak implementation provided below)
+
+
+        PUBWEAK CpuUserInt8_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CpuUserInt8_Handler:
+        B CpuUserInt8_Handler
+
+;-----------------------------------------
+
+        PUBWEAK CpuUserInt9_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CpuUserInt9_Handler:
+        B CpuUserInt9_Handler
+
+;-----------------------------------------
+
+        PUBWEAK CpuUserInt10_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CpuUserInt10_Handler:
+        B CpuUserInt10_Handler
+
+;-----------------------------------------
+
+        PUBWEAK CpuUserInt11_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CpuUserInt11_Handler:
+        B CpuUserInt11_Handler
+
+;-----------------------------------------
+
+        PUBWEAK CpuUserInt12_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CpuUserInt12_Handler:
+        B CpuUserInt12_Handler
+
+;-----------------------------------------
+
+        PUBWEAK CpuUserInt13_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CpuUserInt13_Handler:
+        B CpuUserInt13_Handler
+
+;-----------------------------------------
+
+        PUBWEAK CpuUserInt14_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CpuUserInt14_Handler:
+        B CpuUserInt14_Handler
+
+;-----------------------------------------
+
+        PUBWEAK CpuUserInt15_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+CpuUserInt15_Handler:
+        B CpuUserInt15_Handler
+
+;-----------------------------------------
+
+
+;************************************************************************
+;* File end
+;************************************************************************
+
+        END
+
+
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
new file mode 100644
index 0000000..3d691a3
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
@@ -0,0 +1,702 @@
+/***************************************************************************//**
+* \file system_cm0plus.c
+* \version 1.0
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+*
+* Initializes the system:
+* - Unlocks and disables WDT.
+* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
+* - Calls \ref SystemCoreClockUpdate().
+*
+*******************************************************************************/
+
+
+#include <stdbool.h>
+#include "system_cat1c.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_sysclk.h"
+#include "cy_wdt.h"
+#include "cmsis_compiler.h"
+
+#define CY_SYS_CM7_PWR_CTL_KEY_OPEN  (0x05FAUL)
+#define CY_SYS_CM7_PWR_CTL_KEY_CLOSE (0xFA05UL)
+
+void Cy_DefaultUserHandler(void);
+static void CopyVectorTable(void);
+static void InitMemoryEccClearArea(uint32_t u32StartAddr, uint32_t u32EndAddr);
+static void InitMemoryEcc(void);
+static void EnableEcc(void);
+static void PrepareSystemCallInfrastructure(void);
+
+#define DEFAULT_HANDLER_NAME                            Cy_DefaultUserHandler
+
+CY_NOINIT cy_israddress Cy_SystemIrqUserTable[CPUSS_SYSTEM_INT_NR] ;
+
+CY_NOINIT cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer ;
+
+extern uint32_t Cy_u32StartupStackStartAddress;
+extern uint32_t Cy_u32StartupStackEndAddress;
+extern void * __Vectors;
+extern void * __Vectors_Size;
+extern cy_israddress __ramVectors[];
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT       (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT      (8000000UL)
+
+/** Default system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (100000000UL)
+
+/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M7_0) or CLK_FAST(Cortex-M7_1) system core clock */
+CY_NOINIT uint32_t SystemCoreClock ;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_Hfclk0FreqHz ;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_PeriClkFreqHz ;
+
+/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_AhbFreqHz ;
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD  (0x8000u)
+#define CY_DELAY_1K_THRESHOLD           (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD   (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD           (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD   (CY_DELAY_1M_THRESHOLD - 1u)
+
+CY_NOINIT uint32_t cy_delayFreqHz ;
+
+CY_NOINIT uint32_t cy_delayFreqKhz ;
+
+CY_NOINIT uint32_t cy_delayFreqMhz ;
+
+
+/*****************************************************************************
+* Global variable definitions (declared in header file with 'extern')
+*****************************************************************************/
+// CAUTION: Static or global initialized and non-const variables will not have their init value yet!
+
+
+#define SRAM_BEGIN_ADDR                     (BASE_SRAM_CM0P)
+#define SRAM_END_ADDR                       (CY_SRAM_BASE + CY_SRAM_SIZE)
+#define STARTUP_STACK_OFFSEST               (0x100) /* 32 2-words are cleaned by startup */
+
+#define ECC_INIT_WIDTH_BYTES                8
+#define SROM_VECTOR_TABLE_BASE_ADDRESS      0x00000000
+#define VECTOR_TABLE_OFFSET_IRQ0            0x40
+#define VECTOR_TABLE_OFFSET_IRQ1            0x44
+
+#if defined(__ARMCC_VERSION)
+extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit;            /* for (default) One Region model */
+extern void __main(void);
+#elif defined (__GNUC__)
+extern unsigned int __StackTop;
+#elif defined (__ICCARM__)
+extern unsigned int CSTACK$$Limit;                      /* for (default) One Region model */
+#endif
+
+/******************************************************************************/
+
+/** Define an abstract type for the chosen ECC initialization granularity */
+typedef uint64_t  ecc_init_width_t;
+
+/* Provide empty __WEAK implementation for the low-level initialization
+   routine required by the RTOS-enabled applications.
+   clib-support library provides FreeRTOS-specific implementation:
+   https://github.com/Infineon/clib-support */
+void cy_toolchain_init(void);
+__WEAK void cy_toolchain_init(void)
+{
+}
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+/* GCC: newlib crt0 _start executes software_init_hook.
+   The cy_toolchain_init hook provided by clib-support library must execute
+   after static data initialization and before static constructors. */
+void software_init_hook();
+void software_init_hook()
+{
+    cy_toolchain_init();
+}
+#elif defined(__ICCARM__)
+/* Initialize data section */
+void __iar_data_init3(void);
+
+/* Call the constructors of all global objects */
+void __iar_dynamic_initialization(void);
+
+/* Define strong version to return zero for __iar_program_start
+   to skip data sections initialization (__iar_data_init3). */
+int __low_level_init(void);
+int __low_level_init(void)
+{
+    return 0;
+}
+#else
+/**/
+#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */
+
+
+void CyMain(void)
+{
+#if defined(__ICCARM__)
+    /* Initialize data section */
+    __iar_data_init3();
+
+    /* Initialization hook for RTOS environment  */
+    cy_toolchain_init();
+
+    /* Call the constructors of all global objects */
+    __iar_dynamic_initialization();
+#endif
+
+    __PROGRAM_START();
+}
+
+
+void SystemInit(void)
+{
+    /* startup Init */
+    InitMemoryEcc();
+    EnableEcc();
+    CopyVectorTable();
+    PrepareSystemCallInfrastructure();
+    /* startup Init done */
+
+    SystemIrqInit();
+
+    Cy_WDT_Unlock();
+    Cy_WDT_Disable();
+
+    Cy_SystemInit();
+    SystemCoreClockUpdate();
+
+}
+
+
+/*******************************************************************************
+* Function Name: EnableEcc
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+static void EnableEcc(void)
+{
+    /* Enable ECC checking in SRAM controllers again (had been switched off by assembly startup code) */
+    CPUSS->RAM0_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
+#if (CPUSS_RAMC1_PRESENT == 1u)
+    CPUSS->RAM1_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
+#endif
+#if (CPUSS_RAMC2_PRESENT == 1u)
+    CPUSS->RAM2_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
+#endif
+}
+
+
+/*******************************************************************************
+* Function Name: InitMemoryEcc
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+static void InitMemoryEcc(void)
+{
+    uint32_t *sp = (uint32_t*)&__INITIAL_SP;
+    uint32_t u32StckLow = (uint32_t)sp - STARTUP_STACK_OFFSEST;
+    uint32_t u32StackHigh = (uint32_t)sp;
+
+    InitMemoryEccClearArea(SRAM_BEGIN_ADDR, u32StckLow);
+    InitMemoryEccClearArea(u32StackHigh, SRAM_END_ADDR);
+}
+
+
+/**
+ *****************************************************************************
+ ** Clears an area by writing '0' using a pointer of type #ecc_init_width_t
+ **
+ ** \param u32StartAddr    Start address of area to be cleared,
+ **                        must be aligned to #ECC_INIT_WIDTH_BYTES
+ ** \param u32EndAddr      Last address within area to be cleared, (u32EndAddr+1)
+ **                        must be aligned to #ECC_INIT_WIDTH_BYTES
+ **
+ ** \return none
+ *****************************************************************************/
+static void InitMemoryEccClearArea(uint32_t u32StartAddr, uint32_t u32EndAddr)
+{
+    volatile ecc_init_width_t * pRam = (volatile ecc_init_width_t *) u32StartAddr;
+    ecc_init_width_t Zero = 0;
+
+    for(; (uint32_t)pRam < u32EndAddr; pRam++)
+    {
+        // Note: Even if ecc_init_width_t is uint64_t, this will be compiled as two 32-bit accesses
+        //       in case of CM0+, because there is no STRD instruction specified in ARMv6-M Thumb
+        *pRam = Zero;
+    }
+}
+
+
+/**
+ *****************************************************************************
+ ** Copies the vector table from ROM to RAM and updates the VTOR (CMx vector
+ ** table base register) accordingly
+ **
+ ** \return none
+ *****************************************************************************/
+static void CopyVectorTable(void)
+{
+    const uint8_t    u8NrOfVectors = (uint8_t) ((uint32_t) &__Vectors_Size / 4);
+    uint32_t * const pu32RamTable  = (uint32_t *) __ramVectors;
+    uint32_t * const pu32RomTable  = (uint32_t *) (&__Vectors);
+
+
+    for(uint8_t u8Index = 0; u8Index < u8NrOfVectors; u8Index++)
+    {
+        pu32RamTable[u8Index] = pu32RomTable[u8Index];
+    }
+
+    SCB->VTOR = (uint32_t) pu32RamTable;
+}
+
+/**
+ *****************************************************************************
+ ** Prepares necessary settings to get SROM system calls working
+ **
+ ** \return none
+ *****************************************************************************/
+static void PrepareSystemCallInfrastructure(void)
+{
+    const uint8_t u8Irq0Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ0 / 4);
+    const uint8_t u8Irq1Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ1 / 4);
+    uint32_t * const pu32RamTable   = (uint32_t *) __ramVectors;
+    uint32_t * const pu32SromTable  = (uint32_t *) SROM_VECTOR_TABLE_BASE_ADDRESS;
+
+    // Use IRQ0 and IRQ1 handlers from SROM vector table
+    pu32RamTable[u8Irq0Index] = pu32SromTable[u8Irq0Index];
+    pu32RamTable[u8Irq1Index] = pu32SromTable[u8Irq1Index];
+
+    NVIC_SetPriority(NvicMux0_IRQn, 1);
+    NVIC_SetPriority(NvicMux1_IRQn, 0);
+    NVIC_EnableIRQ(NvicMux0_IRQn);
+    NVIC_EnableIRQ(NvicMux1_IRQn);
+
+    // Only item left is clearing of PRIMASK:
+    // This should be done by the application at a later point in time (e.g. in main())
+}
+
+/*******************************************************************************
+* Function Name: SystemIrqInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+void SystemIrqInit(void)
+{
+    for (int i=0; i<(int)CPUSS_SYSTEM_INT_NR; i++)
+    {
+        Cy_SystemIrqUserTable[i] = DEFAULT_HANDLER_NAME;
+    }
+
+    Cy_SysInt_SystemIrqUserTableRamPointer = Cy_SystemIrqUserTable;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+     /* Empty weak function. The actual implementation to be in the app
+      * generated strong function.
+     */
+}
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+    uint32_t pathFreqHz;
+    uint32_t clkHfPath;
+
+    /* Get frequency for the high-frequency clock*/
+    clkHfPath = CY_SYSCLK_CLK_CORE_HF_PATH_NUM;
+
+    pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+    SystemCoreClock = pathFreqHz;
+
+    cy_Hfclk0FreqHz = SystemCoreClock;
+
+    /* Get Peripheral clock Frequency*/
+    clkHfPath = CY_SYSCLK_CLK_PERI_HF_PATH_NUM;
+
+    pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+    cy_PeriClkFreqHz = pathFreqHz;
+
+    /* Sets clock frequency for Delay API */
+    cy_delayFreqHz = SystemCoreClock;
+    cy_delayFreqMhz = (uint32_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+    cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+
+    /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
+    cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
+}
+
+
+uint32_t Cy_SysGetCM7Status(uint8_t core)
+{
+    uint32_t regValue = 0u;
+
+    CY_ASSERT(core < CORE_MAX);
+
+    if(core == CORE_CM7_0)
+    {
+        /* Get current power mode */
+        regValue = _FLD2VAL(CPUSS_CM7_0_PWR_CTL_PWR_MODE, CPUSS->CM7_0_PWR_CTL);
+    }
+    else if(core == CORE_CM7_1)
+    {
+        /* Get current power mode */
+        regValue = _FLD2VAL(CPUSS_CM7_1_PWR_CTL_PWR_MODE, CPUSS->CM7_1_PWR_CTL);
+    }
+    else
+    {
+        /* */
+    }
+
+    return (regValue);
+}
+
+
+void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset)
+{
+    uint32_t cmStatus;
+    uint32_t interruptState;
+    uint32_t regValue;
+
+    CY_ASSERT(core < CORE_MAX);
+
+    interruptState = Cy_SaveIRQ();
+
+    cmStatus = Cy_SysGetCM7Status(core);
+    if(cmStatus == CY_SYS_CM7_STATUS_ENABLED)
+    {
+        // Set core into reset first, so that new settings can get effective
+        // This branch is e.g. entered if a debugger is connected that would power-up the CM7,
+        // but let it run in ROM boot or pause its execution by keeping CPU_WAIT bit set.
+        Cy_SysResetCM7(core);
+    }
+
+    // CLK_HF1, by default is disabled for use by CM7_0/1, hence enable
+    SRSS->CLK_ROOT_SELECT[1] |= SRSS_CLK_ROOT_SELECT_ENABLE_Msk;
+
+    if(core == CORE_CM7_0)
+    {
+        /* Adjust the vector address */
+        CPUSS->CM7_0_VECTOR_TABLE_BASE = vectorTableOffset;
+
+        /* Enable the Power Control Key */
+        regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk);
+        regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
+        regValue |= CY_SYS_CM7_STATUS_ENABLED;
+        CPUSS->CM7_0_PWR_CTL = regValue;
+
+        while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL)
+        {
+            /* Wait for the power mode to take effect */
+        }
+
+        CPUSS->CM7_0_CTL &= ~(0x1 << CPUSS_CM7_0_CTL_CPU_WAIT_Pos);
+    }
+    else if(core == CORE_CM7_1)
+    {
+        /* Adjust the vector address */
+        CPUSS->CM7_1_VECTOR_TABLE_BASE = vectorTableOffset;
+
+        /* Enable the Power Control Key */
+        regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk);
+        regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
+        regValue |= CY_SYS_CM7_STATUS_ENABLED;
+        CPUSS->CM7_1_PWR_CTL = regValue;
+
+        while((CPUSS->CM7_1_STATUS & CPUSS_CM7_1_STATUS_PWR_DONE_Msk) == 0UL)
+        {
+            /* Wait for the power mode to take effect */
+        }
+
+        CPUSS->CM7_1_CTL &= ~(0x1 << CPUSS_CM7_1_CTL_CPU_WAIT_Pos);
+    }
+
+    Cy_RestoreIRQ(interruptState);
+
+}
+
+
+void Cy_SysDisableCM7(uint8_t core)
+{
+    uint32_t regValue;
+
+    CY_ASSERT(core < CORE_MAX);
+
+    if(core == CORE_CM7_0)
+    {
+        regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk);
+        regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
+        regValue |= CY_SYS_CM7_STATUS_DISABLED;
+        CPUSS->CM7_0_PWR_CTL = regValue;
+
+        while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL)
+        {
+            /* Wait for the power mode to take effect */
+        }
+
+    }
+    else if(core == CORE_CM7_1)
+    {
+        regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk);
+        regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
+        regValue |= CY_SYS_CM7_STATUS_DISABLED;
+        CPUSS->CM7_1_PWR_CTL = regValue;
+
+        while((CPUSS->CM7_1_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL)
+        {
+            /* Wait for the power mode to take effect */
+        }
+    }
+}
+
+
+void Cy_SysRetainCM7(uint8_t core)
+{
+    uint32_t cmStatus;
+    uint32_t  interruptState;
+    uint32_t regValue;
+
+    interruptState = Cy_SaveIRQ();
+
+    cmStatus = Cy_SysGetCM7Status(core);
+    if(cmStatus == CY_SYS_CM7_STATUS_ENABLED)
+    {
+        if(core == CORE_CM7_0)
+        {
+            regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk);
+            regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
+            regValue |= CY_SYS_CM7_STATUS_RETAINED;
+            CPUSS->CM7_0_PWR_CTL = regValue;
+        }
+        else if(core == CORE_CM7_1)
+        {
+            regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk);
+            regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
+            regValue |= CY_SYS_CM7_STATUS_RETAINED;
+            CPUSS->CM7_1_PWR_CTL = regValue;
+        }
+    }
+
+    Cy_RestoreIRQ(interruptState);
+}
+
+
+void Cy_SysResetCM7(uint8_t core)
+{
+    uint32_t regValue;
+
+    CY_ASSERT(core < CORE_MAX);
+
+    if(core == CORE_CM7_0)
+    {
+        regValue = CPUSS->CM7_0_PWR_CTL & ~(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_0_PWR_CTL_PWR_MODE_Msk);
+        regValue |= _VAL2FLD(CPUSS_CM7_0_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
+        regValue |= CY_SYS_CM7_STATUS_RESET;
+        CPUSS->CM7_0_PWR_CTL = regValue;
+
+        while((CPUSS->CM7_0_STATUS & CPUSS_CM7_0_STATUS_PWR_DONE_Msk) == 0UL)
+        {
+            /* Wait for the power mode to take effect */
+        }
+    }
+    else if(core == CORE_CM7_1)
+    {
+        regValue = CPUSS->CM7_1_PWR_CTL & ~(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM7_1_PWR_CTL_PWR_MODE_Msk);
+        regValue |= _VAL2FLD(CPUSS_CM7_1_PWR_CTL_VECTKEYSTAT, CY_SYS_CM7_PWR_CTL_KEY_OPEN);
+        regValue |= CY_SYS_CM7_STATUS_RESET;
+        CPUSS->CM7_1_PWR_CTL = regValue;
+
+        while((CPUSS->CM7_1_STATUS & CPUSS_CM7_1_STATUS_PWR_DONE_Msk) == 0UL)
+        {
+            /* Wait for the power mode to take effect */
+        }
+    }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DefaultUserHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU attempts to call IRQ that has not been mapped to user functions.
+*
+*******************************************************************************/
+void Cy_DefaultUserHandler(void)
+{
+    // This IRQ occurred because CPU attempted to call IRQ that has not been mapped to user function
+    while(1);
+}
+
+
+/*******************************************************************************
+* Function Name: CM0P_CpuIntr_HandlerInline
+****************************************************************************//**
+*
+* The Inline handler for CPU interrupt.
+* The system interrupt mapped to CPU interrupt will be fetched and executed
+*
+*******************************************************************************/
+__STATIC_FORCEINLINE void CM0P_CpuIntr_HandlerInline(uint8_t intrNum)
+{
+    uint32_t system_int_idx;
+    cy_israddress handler;
+
+    if (_FLD2VAL(CPUSS_CM0_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM0_INT_STATUS_BASE[intrNum]))
+    {
+        system_int_idx = _FLD2VAL(CPUSS_CM0_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM0_INT_STATUS_BASE[intrNum]);
+        handler = Cy_SystemIrqUserTable[system_int_idx];
+        if(handler != NULL)
+        handler(); // jump to system interrupt handler
+    }
+    else
+    {
+        // Triggered by software or because of software cleared a peripheral interrupt flag but did not clear the pending flag at NVIC
+    }
+    NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
+}
+
+
+/*******************************************************************************
+* Function Name: CpuIntr2_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt2 occurs.
+*
+*******************************************************************************/
+void CM0P_CpuIntr2_Handler(void)
+{
+    CM0P_CpuIntr_HandlerInline(2);
+}
+
+
+/*******************************************************************************
+* Function Name: CpuIntr3_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt3 occurs.
+*
+*******************************************************************************/
+void CM0P_CpuIntr3_Handler(void)
+{
+    CM0P_CpuIntr_HandlerInline(3);
+}
+
+
+/*******************************************************************************
+* Function Name: CpuIntr4_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt4 occurs.
+*
+*******************************************************************************/
+void CM0P_CpuIntr4_Handler(void)
+{
+    CM0P_CpuIntr_HandlerInline(4);
+}
+
+/*******************************************************************************
+* Function Name: CpuIntr5_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt5 occurs.
+*
+*******************************************************************************/
+void CM0P_CpuIntr5_Handler(void)
+{
+    CM0P_CpuIntr_HandlerInline(5);
+}
+
+
+/*******************************************************************************
+* Function Name: CpuIntr6_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt6 occurs.
+*
+*******************************************************************************/
+void CM0P_CpuIntr6_Handler(void)
+{
+    CM0P_CpuIntr_HandlerInline(6);
+}
+
+
+/*******************************************************************************
+* Function Name: CpuIntr7_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt7 occurs.
+*
+*******************************************************************************/
+void CM0P_CpuIntr7_Handler(void)
+{
+    CM0P_CpuIntr_HandlerInline(7);
+}
+
+
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h
new file mode 100644
index 0000000..3540379
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h
@@ -0,0 +1,9 @@
+#ifndef __STARTUP_CAT1C_H__
+#define __STARTUP_CAT1C_H__
+
+#define FIXED_EXP_NR            (15u)
+#define VECTORTABLE_SIZE        (16u + FIXED_EXP_NR + 1u) /* +1 is for Stack pointer */
+#define VECTORTABLE_ALIGN       (128) /* alignment for 85 entries (32x4=128) is 2^7=128 bytes */
+
+
+#endif /* __STARTUP_CAT1C_H__ */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
new file mode 100644
index 0000000..c2c36d9
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
@@ -0,0 +1,393 @@
+/***************************************************************************//**
+* \file startup_cm7.c
+* \version 1.0
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+#include "cy_syslib.h"
+#include "cmsis_compiler.h"
+#include "startup_cat1c.h"
+#include "core_cm7.h"
+#include "system_cat1c.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+extern void CM7_CpuIntr_Handler(uint8_t intrNum);
+
+void Reset_Handler(void);
+
+/* Internal Reference */
+void Default_Handler(void);
+void Default_NMIException_Handler(void);
+void Default_Fault_Handler(void);
+void SysLib_FaultHandler(uint32_t const *faultStackAddr);
+__WEAK void cy_toolchain_init(void);
+void FpuEnable(void);
+
+
+#if defined(__ARMCC_VERSION)
+extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit;
+interrupt_type extern void __main(void);
+cy_israddress __ramVectors[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#elif defined (__GNUC__)
+extern unsigned int __StackTop;
+extern uint32_t __StackLimit;
+cy_israddress __ramVectors[VECTORTABLE_SIZE]   __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#elif defined (__ICCARM__)
+extern unsigned int CSTACK$$Limit;
+interrupt_type extern void  __cmain();
+cy_israddress __ramVectors[VECTORTABLE_SIZE]   __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#else
+    #error "An unsupported toolchain"
+#endif  /* (__ARMCC_VERSION) */
+
+/* SCB->CPACR */
+#define SCB_CPACR_CP10_CP11_ENABLE      (0xFUL << 20u)
+
+/*******************************************************************************
+* Function Name: FpuEnable
+****************************************************************************//**
+*
+* Enables the FPU if it is used. The function is called from the startup file.
+*
+*******************************************************************************/
+void FpuEnable(void)
+{
+    #if defined (__FPU_USED) && (__FPU_USED == 1U)
+        uint32_t  interruptState;
+        interruptState = Cy_SaveIRQ();
+        SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
+        __DSB();
+        __ISB();
+        Cy_RestoreIRQ(interruptState);
+    #endif /* (__FPU_USED) && (__FPU_USED == 1U) */
+}
+
+
+void SysLib_FaultHandler(uint32_t const *faultStackAddr)
+{
+    Cy_SysLib_FaultHandler(faultStackAddr);
+}
+
+/* Exception Vector Table & Handlers */
+/*----------------------------------------------------------------*/
+void Default_NMIException_Handler(void)
+{
+    __asm volatile(
+        "bkpt #10\n"
+        "B .\n"
+    );
+}
+
+void Default_Fault_Handler(void)
+{
+    __asm (
+        "MRS R0, CONTROL\n"
+        "TST R0, #2\n"
+        "ITE EQ\n"
+        "MRSEQ R0, MSP\n"
+        "MRSNE R0, PSP\n"
+        "B SysLib_FaultHandler\n"
+    );
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void)
+{
+    while(1);
+}
+
+
+/*******************************************************************************
+* Function Name: Default_CM7_CpuIntr0_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt0 occurs.
+*
+*******************************************************************************/
+void Default_CpuIntr0_Handler(void)
+{
+    CM7_CpuIntr_Handler(0);
+}
+
+
+/*******************************************************************************
+* Function Name: Default_CM7_CpuIntr1_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt1 occurs.
+*
+*******************************************************************************/
+void Default_CpuIntr1_Handler(void)
+{
+    CM7_CpuIntr_Handler(1);
+}
+
+
+/*******************************************************************************
+* Function Name: Default_CM7_CpuIntr2_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt2 occurs.
+*
+*******************************************************************************/
+void Default_CpuIntr2_Handler(void)
+{
+    CM7_CpuIntr_Handler(2);
+}
+
+
+/*******************************************************************************
+* Function Name: Default_CM7_CpuIntr3_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt3 occurs.
+*
+*******************************************************************************/
+void Default_CpuIntr3_Handler(void)
+{
+    CM7_CpuIntr_Handler(3);
+}
+
+
+/*******************************************************************************
+* Function Name: Default_CM7_CpuIntr4_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt4 occurs.
+*
+*******************************************************************************/
+void Default_CpuIntr4_Handler(void)
+{
+    CM7_CpuIntr_Handler(4);
+}
+
+/*******************************************************************************
+* Function Name: Default_CM7_CpuIntr5_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt5 occurs.
+*
+*******************************************************************************/
+void Default_CpuIntr5_Handler(void)
+{
+    CM7_CpuIntr_Handler(5);
+}
+
+
+/*******************************************************************************
+* Function Name: Default_CM7_CpuIntr6_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt6 occurs.
+*
+*******************************************************************************/
+void Default_CpuIntr6_Handler(void)
+{
+    CM7_CpuIntr_Handler(6);
+}
+
+
+/*******************************************************************************
+* Function Name: Default_CM7_CpuIntr7_Handler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt7 occurs.
+*
+*******************************************************************************/
+void Default_CpuIntr7_Handler(void)
+{
+    CM7_CpuIntr_Handler(7);
+}
+
+
+void NMIException_Handler   (void) __attribute__ ((weak, alias("Default_NMIException_Handler")));
+void HardFault_Handler      (void) __attribute__ ((weak, alias("Default_Fault_Handler")));
+void MemManage_Handler      (void) __attribute__ ((weak, alias("Default_Fault_Handler")));
+void BusFault_Handler       (void) __attribute__ ((weak, alias("Default_Fault_Handler")));
+void UsageFault_Handler     (void) __attribute__ ((weak, alias("Default_Fault_Handler")));
+void SVC_Handler            (void) __attribute__ ((weak, alias("Default_Handler")));
+void DebugMon_Handler       (void) __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler         (void) __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler        (void) __attribute__ ((weak, alias("Default_Handler")));
+void CM7_CpuIntr0_Handler   (void) __attribute__ ((weak, alias("Default_CpuIntr0_Handler")));
+void CM7_CpuIntr1_Handler   (void) __attribute__ ((weak, alias("Default_CpuIntr1_Handler")));
+void CM7_CpuIntr2_Handler   (void) __attribute__ ((weak, alias("Default_CpuIntr2_Handler")));
+void CM7_CpuIntr3_Handler   (void) __attribute__ ((weak, alias("Default_CpuIntr3_Handler")));
+void CM7_CpuIntr4_Handler   (void) __attribute__ ((weak, alias("Default_CpuIntr4_Handler")));
+void CM7_CpuIntr5_Handler   (void) __attribute__ ((weak, alias("Default_CpuIntr5_Handler")));
+void CM7_CpuIntr6_Handler   (void) __attribute__ ((weak, alias("Default_CpuIntr6_Handler")));
+void CM7_CpuIntr7_Handler   (void) __attribute__ ((weak, alias("Default_CpuIntr7_Handler")));
+
+extern const cy_israddress __Vectors[VECTORTABLE_SIZE];
+const cy_israddress __Vectors[VECTORTABLE_SIZE] __VECTOR_TABLE_ATTRIBUTE = {
+    (cy_israddress)&__INITIAL_SP,
+    (cy_israddress)Reset_Handler,               /* initial PC/Reset */
+    (cy_israddress)NMIException_Handler,        /* NMI */
+    (cy_israddress)HardFault_Handler,           /* Hard Fault*/
+    (cy_israddress)MemManage_Handler,           /* Memory Manage Fault */
+    (cy_israddress)BusFault_Handler,            /* Bus Fault */
+    (cy_israddress)UsageFault_Handler,          /* Usage Fault */
+    0,                                          /* RESERVED */
+    0,                                          /* RESERVED */
+    0,                                          /* RESERVED */
+    0,                                          /* RESERVED */
+    (cy_israddress)SVC_Handler,                 /* SVC */
+    (cy_israddress)DebugMon_Handler,            /* debug */
+    0,                                          /* RESERVED */
+    (cy_israddress)PendSV_Handler,              /* Pend SV */
+    (cy_israddress)SysTick_Handler,             /* systick */
+    /* External interrupts */
+    (cy_israddress)CM7_CpuIntr0_Handler,
+    (cy_israddress)CM7_CpuIntr1_Handler,
+    (cy_israddress)CM7_CpuIntr2_Handler,
+    (cy_israddress)CM7_CpuIntr3_Handler,
+    (cy_israddress)CM7_CpuIntr4_Handler,
+    (cy_israddress)CM7_CpuIntr5_Handler,
+    (cy_israddress)CM7_CpuIntr6_Handler,
+    (cy_israddress)CM7_CpuIntr7_Handler,
+    /* Internal interrupts */
+    (cy_israddress)Default_Handler,
+    (cy_israddress)Default_Handler,
+    (cy_israddress)Default_Handler,
+    (cy_israddress)Default_Handler,
+    (cy_israddress)Default_Handler,
+    (cy_israddress)Default_Handler,
+    (cy_israddress)Default_Handler,
+    (cy_israddress)Default_Handler
+};
+
+
+/* Provide empty __WEAK implementation for the low-level initialization
+   routine required by the RTOS-enabled applications.
+   clib-support library provides FreeRTOS-specific implementation:
+   https://github.com/Infineon/clib-support */
+void cy_toolchain_init(void);
+__WEAK void cy_toolchain_init(void)
+{
+}
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+/* GCC: newlib crt0 _start executes software_init_hook.
+   The cy_toolchain_init hook provided by clib-support library must execute
+   after static data initialization and before static constructors. */
+void software_init_hook();
+void software_init_hook()
+{
+    cy_toolchain_init();
+}
+#elif defined(__ICCARM__)
+/* Initialize data section */
+void __iar_data_init3(void);
+
+/* Call the constructors of all global objects */
+void __iar_dynamic_initialization(void);
+
+/* Define strong version to return zero for __iar_program_start
+   to skip data sections initialization (__iar_data_init3). */
+int __low_level_init(void);
+int __low_level_init(void)
+{
+    return 0;
+}
+#else
+/**/
+#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */
+
+
+// Reset Handler
+void Reset_Handler(void)
+{
+    /* disable global interrupt */
+    __disable_irq();
+
+    /* Allow write access to Vector Table Offset Register and ITCM/DTCM configuration register
+     * (CPUSS_CM7_X_CTL.PPB_LOCK[3] and CPUSS_CM7_X_CTL.PPB_LOCK[1:0]) */
+#ifdef CORE_NAME_CM7_1
+    CPUSS->CM7_1_CTL &= ~(0xB);
+#elif CORE_NAME_CM7_0
+    CPUSS->CM7_0_CTL &= ~(0xB);
+#else
+    #error "Not valid"
+#endif
+
+    __DSB();
+    __ISB();
+
+    /* Enable ITCM and DTCM */
+    SCB->ITCMCR = SCB->ITCMCR | 0x7; /* Set ITCMCR.EN, .RMW and .RETEN fields */
+    SCB->DTCMCR = SCB->DTCMCR | 0x7; /* Set DTCMCR.EN, .RMW and .RETEN fields */
+
+    /* Enable FPU if present */
+    FpuEnable();
+
+    /* copy vector table */
+    for (uint32_t count = 0; count < VECTORTABLE_SIZE; count++)
+    {
+        __ramVectors[count] =__Vectors[count];
+    }
+
+    SCB->VTOR = (uint32_t)__ramVectors;
+
+    __DSB();
+    __ISB();
+
+#ifdef ENABLE_CM7_INSTRUCTION_CACHE
+    SCB_EnableICache();
+#endif /* ENABLE_CM7_INSTRUCTION_CACHE */
+#ifdef ENABLE_CM7_DATA_CACHE
+    SCB_EnableDCache();
+#else
+    // Ensure that the undefined valid bits in the cache RAM are set to invalid if cache is disabled, because the application
+    // may call further cache maintenance functions (e.g. SCB_CleanInvalidateDCache) independent of the "cache enabled" state.
+    SCB_InvalidateDCache();
+#endif /* ENABLE_CM7_DATA_CACHE */
+
+    SystemInit();
+
+#if defined(__ICCARM__)
+    /* Initialize data section */
+    __iar_data_init3();
+
+    /* Initialization hook for RTOS environment  */
+    cy_toolchain_init();
+
+    /* Call the constructors of all global objects */
+    __iar_dynamic_initialization();
+#endif
+
+    /* c-runtime */
+    __PROGRAM_START();
+}
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h
new file mode 100644
index 0000000..8c67ae9
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h
@@ -0,0 +1,555 @@
+/***************************************************************************//**
+* \file system_cat1c.h
+* \version 1.0
+*
+* \brief Device system header file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+#ifndef _SYSTEM_FACELIFT_H_
+#define _SYSTEM_FACELIFT_H_
+
+/**
+* \addtogroup group_system_config_cm7
+* \{
+* Provides device startup, system configuration, and linker script files.
+* The system startup provides the followings features:
+* - \ref group_system_config_device_memory_definition_cm7
+* - \ref group_system_config_device_initialization_cm7
+* - \ref group_system_config_heap_stack_config_cm7
+* - \ref group_system_config_default_handlers_cm7
+* - \ref group_system_config_device_vector_table_cm7
+* - \ref group_system_config_cm7_functions
+*
+* \section group_system_config_configuration_cm7 Configuration Considerations
+*
+* \subsection group_system_config_device_memory_definition_cm7 Device Memory Definition
+* Allocation of different types of memory such as the flash, RAM etc., for the CPU is defined by the linker scripts.
+*
+* \note - The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see warnings during the build process. To eliminate build
+* warnings in your project, you can simply comment out or remove the relevant
+* code in the linker file.
+*
+* \note - There is a common linker script for both CM7_0 and CM7_1 core.
+* By default it links for CM7_0 core. But if the application is built for CM7_1, then a linker option _CORE_cm7_1 is provided in build system.
+* For example, below piece of code is implemented in the build system.
+* \code
+* ifeq ($(TOOLCHAIN),IAR)
+* LDFLAGS += --config_def _CORE_cm7_1_=1
+* else ifeq ($(TOOLCHAIN),GCC_ARM)
+* LDFLAGS += -Wl,'--defsym=_CORE_cm7_1_=1'
+* endif
+* \endcode
+*
+* <b>ARM GCC</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
+* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
+* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM7() function call.
+* By default,
+* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
+* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
+*
+* Change the flash and RAM sizes by editing the macro values in the
+* linker files for both CPUs:
+* - 'xx_yy_cm0plus.ld', where 'xx_yy' is the device group:
+* \code
+* cm0_ram (rxw)  : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P
+* cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P,LENGTH = _size_CODE_FLASH_CM0P
+* \endcode
+* - 'xx_yy_cm7.ld', where 'xx_yy' is the device group:
+* \code
+* ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM
+* flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P
+* flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
+* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
+* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
+* same value as the flash LENGTH in 'xx_yy_cm0plus.ld') in the 'xx_yy_cm7.ld' file,
+* where 'xx_yy' is the device group.
+*
+* - Do this by editing the the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
+* in the 'system_xx.h', where 'xx' is the device family:\n
+* \code
+* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
+* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
+* \endcode
+* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
+*
+* <b>ARM Compiler</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'.
+*
+* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
+* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM7() function call.
+* By default,
+* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
+* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see the warnings during the build process:
+* L6314W (no section matches pattern) and/or L6329W
+* (pattern only matches removed unused sections). In your project, you can
+* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+* the linker. You can also comment out or remove the relevant code in the linker
+* file.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_yy_cm0plus.sct', where 'xx_yy' is the device group:
+* \code
+* #define SRAM_BASE_ADDRESS               0x28000000
+* #define CM0PLUS_SRAM_RESERVE            0x00020000
+* #define CODE_FLASH_BASE_ADDRESS         0x10000000
+* #define CM0PLUS_CODE_FLASH_RESERVE      0x00080000
+* \endcode
+* - 'xx_yy_cm7.sct', where 'xx_yy' is the device group:
+* \code
+* #define SRAM_BASE_ADDRESS               0x28000000 //SRAM START
+* #define CM7_0_SRAM_RESERVE              0x00060000 //cm7_0 sram size
+* #define BASE_SRAM_CM7_0                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
+* #define SIZE_SRAM_CM7_0                 CM7_0_SRAM_RESERVE
+* //In case of dual CM7-core MCU device device
+* #define SIZE_SRAM_CM7_1                 SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_0_SRAM_RESERVE
+* #define BASE_SRAM_CM7_1                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE
+*
+* #define CODE_FLASH_BASE_ADDRESS         0x10000000 //FLASH START
+* #define CM7_0_CODE_FLASH_RESERVE        0x00200000 //cm7_0 flash size
+* #define BASE_CODE_FLASH_CM7_0           CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
+* #define SIZE_CODE_FLASH_CM7_0           CM7_0_CODE_FLASH_RESERVE
+* //In case of dual CM7-core MCU device device
+* #define BASE_CODE_FLASH_CM7_1           CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE
+* #define SIZE_CODE_FLASH_CM7_1           CODE_FLASH_TOTAL_SIZE - CM0PLUS_CODE_FLASH_RESERVE - CM7_0_CODE_FLASH_RESERVE
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
+* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
+* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
+* same value as the flash LENGTH in 'xx_yy_cm0plus.sct') in the 'xx_yy_cm7.sct' file,
+* where 'xx_yy' is the device group.
+*
+* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
+* in the 'system_xx.h', where 'xx' is the device family:\n
+* \code
+* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
+* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
+* \endcode
+* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
+
+* <b>IAR</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
+* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'.
+* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
+* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM7() function call.
+* By default,
+* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
+* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_yy_cm0plus.icf', where 'xx_yy' is the device group:
+* \code
+* define symbol sram_base_address                 = 0x28000000;
+* define symbol cm0plus_sram_reserve              = 0x00020000; //cm0 sram size
+* define symbol code_flash_base_address           = 0x10000000;
+* define symbol cm0plus_code_flash_reserve        = 0x00080000; //cm0 flash size
+* \endcode
+* - 'xx_yy_cm7.icf', where 'xx_yy' is the device group:
+* \code
+* define symbol sram_base_address                 = 0x28000000;
+* define symbol cm7_0_sram_reserve                = 0x00060000;
+* define symbol _base_SRAM_CM7_0                  = sram_base_address + cm0plus_sram_reserve;
+* define symbol _size_SRAM_CM7_0                  = cm7_0_sram_reserve;
+* //In case of dual CM7-core MCU device device
+* define symbol _base_SRAM_CM7_1                  = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
+* define symbol _size_SRAM_CM7_1                  = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve;
+*
+* define symbol code_flash_base_address           = 0x10000000;
+* define symbol cm7_0_code_flash_reserve          = 0x00200000;
+* define symbol _base_CODE_FLASH_CM7_0            = code_flash_base_address + cm0plus_code_flash_reserve;
+* define symbol _size_CODE_FLASH_CM7_0            = cm7_0_code_flash_reserve;
+* //In case of dual CM7-core MCU device device
+* define symbol _base_CODE_FLASH_CM7_1            = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
+* define symbol _size_CODE_FLASH_CM7_1            = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
+* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
+* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
+* same value as the flash LENGTH in 'xx_yy_cm0plus.icf') in the 'xx_yy_cm7.icf' file,
+* where 'xx_yy' is the device group.
+*
+* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
+* in the 'system_xx.h', where 'xx' is the device family:\n
+* \code
+* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
+* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
+* \endcode
+* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
+*
+* \subsection group_system_config_device_initialization_cm7 Device Initialization
+* After a power-on-reset (POR), the CM0+ starts boot-ROM directly from ROM and boot-ROM starts CM0+ startup.
+* The CM0+ startup starts CM0+ user application. The CM0+ user application enables CM7 cores and starts CM7 startup.
+* The startup code is the piece of code which is executed after every system reset.
+* It initializes the system components like, memory, FPU, interrupts, clock, etc. and calls application's main() function.
+* The startup code is always build as part of user application. There are two different startup codes for CM0+ and CM7 core.
+*
+* The CM0+ startup code implements the following functions to run the CM0+ application:
+*
+* 1. In the Reset Handler, it disables global interrupts
+* 3. Disables the SRAM ECC checking: CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Facelift parts with CM7 core,
+*     sets CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet.
+* 4. Calls SystemInit() function
+*   - Initializes and enables the SRAM memory for ECC
+*   - Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)
+*   - Sets the CM0+ IRQ0 and IRQ1 handlers from SROM vector table, sets the CM0+ IRQ0 and IRQ1priority,
+*      then enables these interrupts: the SROM APIs are executed by CM0+ core in interrupt context using IRQ0 and IRQ1.
+*      So, proper interrupt handler addresses and priorities need to be configured for IRQ0 and IRQ1
+*   - Unlocks and disable WDT (Watchdog timer)
+*   - Calls the SystemCoreClockUpdate()
+* 5. Executes main() application
+*
+* The CM7 startup code implement the following functions to run the CM7 user application:
+*
+* 1. In the Reset handler, it disables global interrupts
+* 2. Allows write access to Vector Table Offset Register and ITCM/DTCM configuration register
+* 3. Enables CM7 core ITCM and DTCM
+* 4. Enables the FPU if it is used
+* 5. Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)
+* 6. Enables the CM7 core instruction and data cache
+* 7. Calls SystemInit() function
+*    - Unlocks and disable WDT (Watchdog timer)
+*    - Calls the SystemCoreClockUpdate()
+* 6. Executes CM7 main() application
+*
+* \subsection group_system_config_heap_stack_config_cm7 Heap and Stack Configuration
+* By default, the stack size is set to 0x00001000 and the Heap size is allocated
+* dynamically to the whole available free memory up to stack memory.
+* The Stack grows from higher to lower address. The Stack top or start is assigned to end of SRAM address.
+* The Heap grows opposite of Stack. It grows from lower to higher address.
+* The Heap top starts from end of used data section till Stack end.
+*
+* \subsubsection group_system_config_heap_stack_config_gcc_cm7 ARM GCC
+* <b>Editing source code files</b>\n
+* The stack size is defined in the linker script files: 'xx_yy_zz.ld',
+* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
+* 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
+* Change the stack size by modifying the following line:\n
+* \code STACK_SIZE = 0x1000; \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_mdk_cm7 ARM Compiler
+* <b>Editing source code files</b>\n
+* The stack size is defined in the linker script files: 'xx_yy_zz.sct',
+* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
+* 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'.
+* Change the stack size by modifying the following line:\n
+* \code #define STACK_SIZE 0x1000 \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_iar_cm7 IAR
+* <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the linker script files: 'xx_yy_zz.icf',
+* where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
+* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'.
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code define symbol cm7_stack_reserve = 0x00001000; \endcode
+*
+* \subsection group_system_config_default_handlers_cm7 Default Interrupt Handlers Definition
+* The default interrupt handler functions are defined as weak functions to a dummy
+* handler in the startup file. The naming convention for the interrupt handler names
+* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
+* user code by defining the handler function using the same name. For example:
+* \code
+* void scb_0_interrupt_IRQHandler(void)
+*{
+*    ...
+*}
+* \endcode
+*
+* \subsection group_system_config_device_vector_table_cm7 Vectors Table Copy from Flash to RAM
+* This process uses memory sections defined in the linker script. The startup
+* code actually defines the contents of the vector table and performs the copy.
+*
+* \subsubsection group_system_config_device_vector_table_gcc_cm7 ARM GCC
+* The linker script file is 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
+* It defines sections and locations in memory.\n
+*       Copy interrupt vectors from flash to RAM: \n
+*       From: \code LONG (__Vectors) \endcode
+*       To:   \code LONG (__ram_vectors_start__) \endcode
+*       Size: \code LONG (__Vectors_End - __Vectors) \endcode
+* The vector table address (and the vector table itself) are defined in the
+*  startup files (e.g. startup_cm0plus.S and startup_cm7.c).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_mdk_cm7 ARM Compiler
+* The linker script file is 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and
+* 'xmc7100d_x4160_cm0plus.sct'. The linker script specifies that the vector table
+* (RESET_RAM) shall be first in the RAM section.\n
+* RESET_RAM represents the vector table. It is defined in the startup
+* files  (e.g. startup_cm0plus.S and startup_cm7.c).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_iar_cm7 IAR
+* The linker script file is 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example, 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and '
+* 'xmc7100d_x4160_cm0plus.icf'.\n
+* The vector table address (and the vector table itself) are defined in the
+* startup files (e.g. startup_cm0plus.S and startup_cm7.c).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \section group_system_config_changelog_cm7 Changelog
+*   <table class="doxtable">
+*   <tr>
+*       <th>Version</th>
+*       <th>Changes</th>
+*       <th>Reason for Change</th>
+*   </tr>
+*   <tr>
+*       <td>1.0</td>
+*       <td>Initial version</td>
+*       <td></td>
+*   </tr>
+* </table>
+*
+* \defgroup group_system_config_macro_cm7 Macros
+* \{
+*   \defgroup group_system_config_system_macro_cm7 System Macros
+* \}
+* \defgroup group_system_config_functions_cm7 Functions
+* \{
+*   \defgroup group_system_config_cm7_functions Cortex-M7 Control
+* \}
+* \}
+*/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Include files
+*******************************************************************************/
+#include <stdint.h>
+#include "xmc7xxx_partition.h"
+
+/*******************************************************************************
+* Global preprocessor symbols/macros ('define')
+*******************************************************************************/
+#if ((defined(__GNUC__)        &&  (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+     (defined (__ICCARM__)     &&  (__CORE__ == __ARM6M__))  || \
+     (defined(__ARMCC_VERSION) &&  (__TARGET_ARCH_THUMB == 3)))
+    #define CY_SYSTEM_CPU_CM0P          1UL
+#else
+    #define CY_SYSTEM_CPU_CM0P          0UL
+#endif
+
+
+/*******************************************************************************
+*
+*                      START OF USER SETTINGS HERE
+*                      ===========================
+*
+*                 All lines with '<<<' can be set by user.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_system_config_system_macro_cm7
+* \{
+*/
+
+/*******************************************************************************
+*
+*                         END OF USER SETTINGS HERE
+*                         =========================
+*
+*******************************************************************************/
+
+/**  Start address of the Cortex-M7_0 application */
+#ifndef CY_CORTEX_M7_0_APPL_ADDR
+    #define CY_CORTEX_M7_0_APPL_ADDR        BASE_CODE_FLASH_CM7_0
+#endif
+
+/**  Start address of the Cortex-M7_1 application */
+#ifndef CY_CORTEX_M7_1_APPL_ADDR
+    #define CY_CORTEX_M7_1_APPL_ADDR        BASE_CODE_FLASH_CM7_1
+#endif
+
+/** The Cortex-M7 core is enabled: power on, clock on, no isolate, no reset and no retain. */
+#define CY_SYS_CM7_STATUS_ENABLED   (3U)
+/** The Cortex-M7 core is disabled: power off, clock off, isolate, reset and no retain. */
+#define CY_SYS_CM7_STATUS_DISABLED  (0U)
+/** The Cortex-M7 core is retained. power off, clock off, isolate, no reset and retain. */
+#define CY_SYS_CM7_STATUS_RETAINED  (2U)
+/** The Cortex-M7 core is in the Reset mode: clock off, no isolated, no retain and reset. */
+#define CY_SYS_CM7_STATUS_RESET     (1U)
+/** \} group_system_config_system_macro_cm7 */
+
+/** \cond */
+/** Cortex-M7 core 0 */
+#define CORE_CM7_0                  (0U)
+/** Cortex-M7 core 1 */
+#define CORE_CM7_1                  (1U)
+/** Error Selection */
+#define CORE_MAX                    (2U)
+
+extern uint32_t cy_delayFreqHz;
+extern uint32_t cy_delayFreqKhz;
+extern uint32_t  cy_delayFreqMhz;
+
+extern uint32_t SystemCoreClock;
+extern uint32_t cy_Hfclk0FreqHz;
+extern uint32_t cy_PeriClkFreqHz;
+extern uint32_t cy_AhbFreqHz;
+
+extern void SystemInit(void);
+extern void SystemIrqInit(void);
+extern void SystemCoreClockUpdate(void);
+
+/** \endcond */
+
+/**
+* \addtogroup group_system_config_cm7_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysGetCM7Status
+****************************************************************************//**
+*
+* Gets the Cortex-M7 core power mode.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \return \ref group_system_config_system_macro_cm7 \n
+* If 0: CY_SYS_CM7_STATUS_DISABLED \n
+*      1: CY_SYS_CM7_STATUS_RESET \n
+*      2: CY_SYS_CM7_STATUS_RETAINED \n
+*      3: CY_SYS_CM7_STATUS_ENABLED \n
+*
+******************************************************************************/
+extern uint32_t Cy_SysGetCM7Status(uint8_t core);
+/*******************************************************************************
+* Function Name: Cy_SysEnableCM7
+****************************************************************************//**
+*
+* Enables the Cortex-M7 core. The CPU is enabled once if it was in the disabled
+* or retained mode.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \param vectorTableOffset The offset of the vector table base address from
+* memory address 0x00000000. The offset should be multiple to 1024 bytes.
+*
+*******************************************************************************/
+extern void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset);
+/*******************************************************************************
+* Function Name: Cy_SysDisableCM7
+****************************************************************************//**
+*
+* Disables the Cortex-M7 core.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \warning Do not call the function while the Cortex-M7 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+extern void Cy_SysDisableCM7(uint8_t core);
+/*******************************************************************************
+* Function Name: Cy_SysRetainCM7
+****************************************************************************//**
+*
+* Retains the Cortex-M7 core.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \warning Do not call the function while the Cortex-M7 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+extern void Cy_SysRetainCM7(uint8_t core);
+/*******************************************************************************
+* Function Name: Cy_SysResetCM7
+****************************************************************************//**
+*
+* Resets the Cortex-M7 core.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \warning Do not call the function while the Cortex-M7 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+extern void Cy_SysResetCM7(uint8_t core);
+/** \} group_system_config_cm7_functions */
+
+
+/** \cond */
+
+extern void     Default_Handler (void);
+
+extern void     Cy_SystemInit(void);
+extern void     Cy_SystemInitFpuEnable(void);
+extern void     CyMain(void);
+
+#define Cy_SaveIRQ      Cy_SysLib_EnterCriticalSection
+#define Cy_RestoreIRQ   Cy_SysLib_ExitCriticalSection
+/** \endcond */
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_FACELIFT_H_ */
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
new file mode 100644
index 0000000..650b3b9
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
@@ -0,0 +1,249 @@
+/***************************************************************************//**
+* \file system_cm7.c
+* \version 1.0
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdbool.h>
+#include "system_cat1c.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_sysclk.h"
+#include "cy_wdt.h"
+
+
+void Cy_DefaultUserHandler(void);
+
+#define DEFAULT_HANDLER_NAME                            Cy_DefaultUserHandler
+
+CY_NOINIT cy_israddress Cy_SystemIrqUserTable[CPUSS_SYSTEM_INT_NR] ;
+
+CY_NOINIT cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer ;
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT       (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT      (8000000UL)
+
+/** Default system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (8000000UL)
+
+/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M7_0) or CLK_FAST(Cortex-M7_1) system core clock */
+CY_NOINIT uint32_t SystemCoreClock ;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_Hfclk0FreqHz ;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_PeriClkFreqHz ;
+
+/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_AhbFreqHz ;
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD  (0x8000u)
+#define CY_DELAY_1K_THRESHOLD           (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD   (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD           (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD   (CY_DELAY_1M_THRESHOLD - 1u)
+
+CY_NOINIT uint32_t cy_delayFreqHz ;
+
+CY_NOINIT uint32_t cy_delayFreqKhz ;
+
+CY_NOINIT uint32_t cy_delayFreqMhz ;
+
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+* \cond
+* Initializes the system:
+* - Unlocks and disables WDT.
+* - Calls the Cy_SystemInit() function.
+* - Calls \ref SystemCoreClockUpdate().
+* \endcond
+*******************************************************************************/
+void SystemInit(void)
+{
+
+    /* if CM0+ is not enabled then unlock and disable WDT */
+#ifdef __CM0P_PRESENT
+    #if (__CM0P_PRESENT == 0)
+
+    /* Release reset for all groups IP except group 0 */
+    (void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
+    (void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
+    (void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
+    (void)Cy_SysClk_PeriGroupSetSlaveCtl(4, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
+    (void)Cy_SysClk_PeriGroupSetSlaveCtl(5, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
+    (void)Cy_SysClk_PeriGroupSetSlaveCtl(6, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
+    (void)Cy_SysClk_PeriGroupSetSlaveCtl(8, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
+    (void)Cy_SysClk_PeriGroupSetSlaveCtl(9, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFU); /* Suppress a compiler warning about unused return value */
+
+    /* Unlock and disable WDT */
+        Cy_WDT_Unlock();
+        Cy_WDT_Disable();
+
+    #endif /* (__CM0P_PRESENT == 0) */
+#endif /* __CM0P_PRESENT */
+
+    Cy_SystemInit();
+    SystemCoreClockUpdate();
+
+    SystemIrqInit();
+}
+
+/*******************************************************************************
+* Function Name: SystemIrqInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+void SystemIrqInit(void)
+{
+    for (int i=0; i<(int)CPUSS_SYSTEM_INT_NR; i++)
+    {
+        Cy_SystemIrqUserTable[i] = DEFAULT_HANDLER_NAME;
+    }
+
+    Cy_SysInt_SystemIrqUserTableRamPointer = Cy_SystemIrqUserTable;
+}
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+     /* Empty weak function. The actual implementation to be in the user application
+      * as strong function.
+     */
+}
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock, \ref
+* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+    uint32_t pathFreqHz;
+    uint32_t clkHfPath;
+
+    /* Get frequency for the high-frequency clock # 0 */
+    clkHfPath = CY_SYSCLK_CLK_CORE_HF_PATH_NUM;
+
+    pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+    SystemCoreClock = pathFreqHz;
+
+    cy_Hfclk0FreqHz = SystemCoreClock;
+
+    /* Get frequency for the high-frequency clock # 2 , whcih is used for PERI PCLK*/
+    clkHfPath = CY_SYSCLK_CLK_PERI_HF_PATH_NUM;
+
+    pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+    cy_PeriClkFreqHz = pathFreqHz;
+
+    /* Sets clock frequency for Delay API */
+    cy_delayFreqHz = SystemCoreClock;
+    cy_delayFreqMhz = (uint32_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+    cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+
+    /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
+    cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_DefaultUserHandler
+****************************************************************************//**
+*
+*The Handler is called when the CPU attempts to call IRQ that has not been mapped to user functions.
+*
+*
+*******************************************************************************/
+void Cy_DefaultUserHandler(void)
+{
+    // This IRQ occurred because CPU attempted to call IRQ that has not been mapped to user function
+    while(1);
+}
+
+
+/*******************************************************************************
+* Function Name: CM7_CpuIntr_Handler
+****************************************************************************//**
+*
+* The Inline handler for CPU interrupt.
+* The system interrupt mapped to CPU interrupt will be fetched and executed
+*
+*******************************************************************************/
+void CM7_CpuIntr_Handler(uint8_t intrNum)
+{
+    uint32_t system_int_idx;
+    cy_israddress handler;
+
+    if(CY_IS_CM7_CORE_0 && (_FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_0_INT_STATUS[intrNum])))
+    {
+        system_int_idx = _FLD2VAL(CPUSS_CM7_0_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_0_INT_STATUS[intrNum]);
+        handler = Cy_SystemIrqUserTable[system_int_idx];
+        if(handler != NULL)
+        handler(); // jump to system interrupt handler
+    }
+    else if(CY_IS_CM7_CORE_1 && (_FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_VALID, CPUSS_CM7_1_INT_STATUS[intrNum])))
+    {
+        system_int_idx = _FLD2VAL(CPUSS_CM7_1_INT_STATUS_SYSTEM_INT_IDX, CPUSS_CM7_1_INT_STATUS[intrNum]);
+        handler = Cy_SystemIrqUserTable[system_int_idx];
+        if(handler != NULL)
+        handler(); // jump to system interrupt handler
+    }
+    else
+    {
+        // Triggered by software or because of software cleared a peripheral interrupt flag but did not clear the pending flag at NVIC
+    }
+    NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
+}
+
+
+
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7xDUAL_CM0P_SLEEP/README.md b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7xDUAL_CM0P_SLEEP/README.md
new file mode 100644
index 0000000..e39310b
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7xDUAL_CM0P_SLEEP/README.md
@@ -0,0 +1,30 @@
+# XMC7xDUAL Cortex M0+ DeepSleep prebuilt image (XMC7xDUAL_CM0P_SLEEP)
+
+### Overview
+DeepSleep prebuilt application image is executed on the Cortex M0+ core of the XMC dual CM7-core MCU (CM0+, CM7_0 and CM7_1).
+The image is provided as C array ready to be compiled as part of the Cortex M7_0 application.
+The Cortex M0+ application code is placed to internal flash by the Cortex M7_0 linker script.
+
+DeepSleep prebuilt image executes the following steps:
+- starts CM7_0 core at CY_CORTEX_M7_0_APPL_ADDR. (check the address in partition.h in pdl repo)
+- starts CM7_1 core at CY_CORTEX_M7_1_APPL_ADDR. (check the address in partition.h in pdl repo)
+- puts the CM0+ core into Deep Sleep.
+
+Note: After CM7_0 boots up, a delay of 1 second is added before CM7_1 boots up. This is to take care of race condition if both the cores try to configure the same clock.
+
+### Usage
+
+This image is used by default by all Infineon BSPs that target XMC Dual-Core MCU.
+
+To use this image in the custom BSP, adjust the BSP target makefile to
+add the COMPONENT_XMC7xDUAL_CM0P_SLEEP directory to the list of components
+discovered by ModusToolbox build system:
+
+```
+COMPONENTS+=XMC7xDUAL_CM0P_SLEEP
+```
+
+Make sure there is a single XMC7xDUAL_CM0P_* component included in the COMPONENTS list.
+
+---
+Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation.
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7xDUAL_CM0P_SLEEP/xmc7100d_cm0p_sleep.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7xDUAL_CM0P_SLEEP/xmc7100d_cm0p_sleep.c
new file mode 100644
index 0000000..daf59dd
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7xDUAL_CM0P_SLEEP/xmc7100d_cm0p_sleep.c
@@ -0,0 +1,565 @@
+/***************************************************************************//**
+* \file xmc7100d_cm0p_sleep.c
+*
+* \brief
+* Cortex-M0+ prebuilt application image.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) 2018-2021 Cypress Semiconductor Corporation (an Infineon
+* company) or an affiliate of Cypress Semiconductor Corporation
+* SPDX-License-Identifier: LicenseRef-PBL
+*
+* Licensed under the Permissive Binary License
+*******************************************************************************/
+
+#include <stdint.h>
+#include "cy_device_headers.h"
+
+#if defined(CY_DEVICE_TVIIBH4M)
+
+#if defined(__APPLE__) && defined(__clang__)
+__attribute__ ((__section__("__CY_M0P_IMAGE,__cy_m0p_image"), used))
+#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cy_m0p_image"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cy_m0p_image"
+#else
+#error "An unsupported toolchain"
+#endif
+const uint8_t cy_m0p_image[] = {
+    0x00u, 0x00u, 0x02u, 0x28u, 0x69u, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9fu, 0x01u, 0x00u, 0x10u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x69u, 0x0au, 0x00u, 0x10u, 0x9du, 0x0au, 0x00u, 0x10u,
+    0xd1u, 0x0au, 0x00u, 0x10u, 0x05u, 0x0bu, 0x00u, 0x10u, 0x39u, 0x0bu, 0x00u, 0x10u, 0x6du, 0x0bu, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u,
+    0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x1cu, 0x10u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0xbcu, 0x1fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u,
+    0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x20u, 0x10u, 0x00u, 0x28u, 0xbcu, 0x1fu, 0x00u, 0x10u, 0x40u, 0x22u, 0x92u, 0x02u, 0x9au, 0x1au, 0x92u, 0x46u,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x17u, 0x4bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x13u, 0x4bu, 0x9du, 0x46u, 0xffu, 0xf7u,
+    0xf3u, 0xffu, 0x00u, 0x21u, 0x8bu, 0x46u, 0x0fu, 0x46u, 0x13u, 0x48u, 0x14u, 0x4au, 0x12u, 0x1au, 0x01u, 0xf0u,
+    0xf2u, 0xfeu, 0x0eu, 0x4bu, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x0du, 0x4bu, 0x00u, 0x2bu, 0x00u, 0xd0u,
+    0x98u, 0x47u, 0x00u, 0x20u, 0x00u, 0x21u, 0x04u, 0x00u, 0x0du, 0x00u, 0x0du, 0x48u, 0x00u, 0x28u, 0x02u, 0xd0u,
+    0x0cu, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0xf0u, 0xb1u, 0xfeu, 0x20u, 0x00u, 0x29u, 0x00u, 0x00u, 0xf0u,
+    0x1fu, 0xfbu, 0x01u, 0xf0u, 0x95u, 0xfeu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x99u, 0x07u, 0x00u, 0x10u, 0x00u, 0x00u, 0x02u, 0x28u, 0x1cu, 0x10u, 0x00u, 0x28u, 0x70u, 0x10u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u,
+    0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u,
+    0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x01u, 0x20u, 0xc0u, 0x04u, 0x13u, 0x49u, 0x0au, 0x68u,
+    0x02u, 0x43u, 0x0au, 0x60u, 0x12u, 0x49u, 0x0au, 0x68u, 0x02u, 0x43u, 0x0au, 0x60u, 0x11u, 0x49u, 0x0au, 0x68u,
+    0x02u, 0x43u, 0x0au, 0x60u, 0x10u, 0x48u, 0x11u, 0x49u, 0x00u, 0x22u, 0x00u, 0x23u, 0x0cu, 0xc0u, 0x88u, 0x42u,
+    0xfcu, 0xd3u, 0x00u, 0xf0u, 0x6fu, 0xfbu, 0x00u, 0xf0u, 0x03u, 0xfbu, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u,
+    0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x02u, 0xe0u, 0xefu, 0xf3u,
+    0x08u, 0x80u, 0x04u, 0x30u, 0x00u, 0xf0u, 0xfcu, 0xf9u, 0xfeu, 0xe7u, 0x00u, 0x00u, 0x00u, 0x13u, 0x20u, 0x40u,
+    0x80u, 0x13u, 0x20u, 0x40u, 0xa0u, 0x13u, 0x20u, 0x40u, 0x00u, 0xffu, 0x01u, 0x28u, 0x00u, 0x00u, 0x02u, 0x28u,
+    0x92u, 0x23u, 0xdbu, 0x00u, 0xc0u, 0x18u, 0x03u, 0x4bu, 0x80u, 0x00u, 0xc0u, 0x58u, 0x80u, 0x06u, 0x80u, 0x0fu,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x03u, 0x00u, 0x00u, 0x20u, 0x07u, 0x2bu, 0x08u, 0xd8u,
+    0x92u, 0x22u, 0xd2u, 0x00u, 0x9bu, 0x18u, 0x03u, 0x4au, 0x9bu, 0x00u, 0x9bu, 0x58u, 0x01u, 0x30u, 0x1bu, 0x0au,
+    0x98u, 0x43u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x02u, 0x4bu, 0x18u, 0x69u, 0x40u, 0x07u, 0xc0u, 0x0fu,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x27u, 0x40u, 0x04u, 0x4bu, 0x05u, 0x4au, 0xd0u, 0x58u, 0x03u, 0x23u,
+    0x18u, 0x40u, 0x98u, 0x42u, 0x00u, 0xd1u, 0x02u, 0x20u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x24u, 0x15u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u,
+    0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x3cu, 0x10u, 0x00u, 0x28u, 0x09u, 0x4au, 0x83u, 0x00u,
+    0x99u, 0x18u, 0x90u, 0x22u, 0x52u, 0x01u, 0x88u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u,
+    0x05u, 0x4au, 0x9bu, 0x18u, 0x58u, 0x68u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xfcu, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u,
+    0xe5u, 0xffu, 0x88u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0x19u, 0xd0u, 0x09u, 0xd8u, 0x01u, 0x28u, 0x10u, 0xd0u,
+    0x02u, 0x28u, 0x11u, 0xd0u, 0x43u, 0x42u, 0x58u, 0x41u, 0x0fu, 0x4bu, 0x40u, 0x42u, 0x18u, 0x40u, 0x10u, 0xbdu,
+    0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x12u, 0xd0u, 0x03u, 0x33u, 0x98u, 0x42u, 0x07u, 0xd0u, 0x00u, 0x20u,
+    0xf5u, 0xe7u, 0x0au, 0x4bu, 0x18u, 0x68u, 0xf2u, 0xe7u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0xefu, 0xe7u, 0x08u, 0x4au,
+    0x08u, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0xf2u, 0xdau, 0x80u, 0x20u, 0x00u, 0x02u, 0xe7u, 0xe7u, 0xffu, 0xf7u,
+    0x9bu, 0xffu, 0x00u, 0x28u, 0xebu, 0xd0u, 0xf7u, 0xe7u, 0x00u, 0x12u, 0x7au, 0x00u, 0x38u, 0x10u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x15u, 0x00u, 0x00u, 0x14u, 0x4au, 0x15u, 0x4bu, 0x10u, 0xb5u, 0xd3u, 0x58u,
+    0x0fu, 0x24u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u,
+    0xd3u, 0x58u, 0xd9u, 0x04u, 0x1bu, 0x0cu, 0xdbu, 0xb2u, 0x03u, 0x81u, 0x0fu, 0x4bu, 0xc9u, 0x0cu, 0xd3u, 0x58u,
+    0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, 0xc1u, 0x72u, 0xd9u, 0x02u,
+    0x9bu, 0x00u, 0x9bu, 0x0fu, 0x83u, 0x73u, 0x09u, 0x4bu, 0xc9u, 0x0cu, 0xd3u, 0x58u, 0x81u, 0x81u, 0x5au, 0x05u,
+    0xdbu, 0x01u, 0x52u, 0x0fu, 0xdbu, 0x0du, 0x82u, 0x71u, 0x03u, 0x82u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u,
+    0x30u, 0x15u, 0x00u, 0x00u, 0x34u, 0x15u, 0x00u, 0x00u, 0x38u, 0x15u, 0x00u, 0x00u, 0x3cu, 0x15u, 0x00u, 0x00u,
+    0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x18u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0xbbu, 0xfdu,
+    0x14u, 0x4bu, 0x28u, 0x01u, 0xc5u, 0x18u, 0xc8u, 0x23u, 0x1fu, 0x26u, 0x5bu, 0x01u, 0xebu, 0x58u, 0x19u, 0x0au,
+    0x31u, 0x40u, 0x61u, 0x70u, 0x07u, 0x21u, 0x23u, 0x70u, 0x1au, 0x0cu, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0x32u, 0x40u,
+    0x23u, 0x71u, 0x0du, 0x4bu, 0xa2u, 0x70u, 0xebu, 0x58u, 0x1au, 0x02u, 0x12u, 0x0au, 0xa2u, 0x60u, 0x1au, 0x0fu,
+    0xf3u, 0x40u, 0x0au, 0x40u, 0x55u, 0x1eu, 0xaau, 0x41u, 0x63u, 0x73u, 0x08u, 0x4bu, 0x22u, 0x73u, 0xc0u, 0x18u,
+    0x03u, 0x68u, 0x00u, 0x20u, 0xdau, 0xb2u, 0x22u, 0x61u, 0x1au, 0x0cu, 0xf3u, 0x40u, 0x11u, 0x40u, 0x21u, 0x75u,
+    0x63u, 0x75u, 0x70u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, 0x04u, 0x19u, 0x00u, 0x00u, 0x08u, 0x19u, 0x26u, 0x40u,
+    0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x18u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x83u, 0xfdu,
+    0xb0u, 0x23u, 0x7fu, 0x22u, 0x1fu, 0x20u, 0xdbu, 0x00u, 0xedu, 0x18u, 0x09u, 0x4bu, 0xadu, 0x00u, 0xebu, 0x58u,
+    0x1au, 0x40u, 0x22u, 0x70u, 0x1au, 0x0cu, 0x02u, 0x40u, 0xa2u, 0x70u, 0x1au, 0x01u, 0xc2u, 0x40u, 0x19u, 0x0au,
+    0x9bu, 0x00u, 0x01u, 0x40u, 0x9bu, 0x0fu, 0x00u, 0x20u, 0x61u, 0x70u, 0xe2u, 0x70u, 0x23u, 0x71u, 0x70u, 0xbdu,
+    0x00u, 0x00u, 0x26u, 0x40u, 0x42u, 0x1eu, 0x06u, 0x4bu, 0x01u, 0x2au, 0x05u, 0xd8u, 0x90u, 0x30u, 0xffu, 0x30u,
+    0x00u, 0x01u, 0x18u, 0x58u, 0xc0u, 0x0fu, 0x70u, 0x47u, 0x02u, 0x4au, 0x80u, 0x18u, 0x80u, 0x00u, 0xf8u, 0xe7u,
+    0x00u, 0x00u, 0x26u, 0x40u, 0x7du, 0x05u, 0x00u, 0x00u, 0x03u, 0x00u, 0x01u, 0x38u, 0x10u, 0xb5u, 0x01u, 0x28u,
+    0x02u, 0xd8u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x10u, 0xbdu, 0xd8u, 0x1eu, 0xffu, 0xf7u, 0xc1u, 0xffu, 0xfau, 0xe7u,
+    0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x3du, 0xd1u,
+    0x14u, 0x22u, 0x21u, 0x00u, 0x04u, 0xa8u, 0x01u, 0xf0u, 0x3eu, 0xfdu, 0x04u, 0xa8u, 0xffu, 0xf7u, 0x44u, 0xffu,
+    0x33u, 0x4au, 0x34u, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x04u, 0xabu, 0x9cu, 0x7bu, 0x02u, 0x3cu,
+    0x63u, 0x1eu, 0x9cu, 0x41u, 0x04u, 0xa9u, 0xc8u, 0x79u, 0x01u, 0x23u, 0x41u, 0x1eu, 0x88u, 0x41u, 0x00u, 0x27u,
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+    0x13u, 0x40u, 0x42u, 0x46u, 0x02u, 0x40u, 0x01u, 0x32u, 0x58u, 0xe7u, 0x03u, 0x9bu, 0x00u, 0x24u, 0x00u, 0x2bu,
+    0x00u, 0xd0u, 0x5cu, 0xe7u, 0x05u, 0xaeu, 0x0eu, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0x96u, 0xffu, 0xf7u,
+    0x0du, 0xfbu, 0x00u, 0x23u, 0x0fu, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0x96u, 0xffu, 0xf7u, 0x2cu, 0xfbu,
+    0x4du, 0xe7u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xfeu, 0x02u, 0x1eu, 0x00u, 0xd1u, 0x46u, 0xe7u, 0x03u, 0x00u,
+    0x41u, 0x46u, 0x8bu, 0x43u, 0xdbu, 0xb2u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x3fu, 0xe7u, 0x00u, 0x21u, 0x28u, 0x00u,
+    0xffu, 0xf7u, 0x00u, 0xfdu, 0x00u, 0x28u, 0x00u, 0xd1u, 0x0eu, 0xe7u, 0x37u, 0xe7u, 0x30u, 0x00u, 0xffu, 0xf7u,
+    0xcfu, 0xfeu, 0xf0u, 0x23u, 0x02u, 0x03u, 0x1bu, 0x03u, 0x13u, 0x40u, 0x42u, 0x46u, 0x02u, 0x40u, 0x01u, 0x32u,
+    0xa7u, 0xe7u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xc4u, 0xfeu, 0xf0u, 0x23u, 0x02u, 0x03u, 0x1bu, 0x03u, 0x13u, 0x40u,
+    0x42u, 0x46u, 0x02u, 0x40u, 0x01u, 0x32u, 0x1au, 0x43u, 0x03u, 0x23u, 0x03u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u,
+    0xe1u, 0xfcu, 0x00u, 0x28u, 0x00u, 0xd1u, 0xefu, 0xe6u, 0x18u, 0xe7u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb0u, 0xfeu,
+    0x02u, 0x1eu, 0x00u, 0xd1u, 0x12u, 0xe7u, 0x03u, 0x00u, 0x41u, 0x46u, 0x8bu, 0x43u, 0xdbu, 0xb2u, 0x00u, 0x2bu,
+    0x00u, 0xd0u, 0x0bu, 0xe7u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xccu, 0xfcu, 0x00u, 0x28u, 0x00u, 0xd1u,
+    0xdau, 0xe6u, 0x03u, 0xe7u, 0x43u, 0x46u, 0xa0u, 0x22u, 0x1cu, 0x40u, 0x01u, 0x34u, 0x12u, 0x03u, 0x22u, 0x43u,
+    0xdau, 0xe7u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x94u, 0xfeu, 0x43u, 0x46u, 0x02u, 0x00u, 0x9au, 0x43u, 0xd2u, 0xb2u,
+    0x10u, 0x32u, 0x18u, 0x40u, 0x12u, 0x03u, 0x01u, 0x30u, 0x02u, 0x43u, 0xe8u, 0xe6u, 0x05u, 0xabu, 0x00u, 0x93u,
+    0x9bu, 0x46u, 0x0du, 0x22u, 0x00u, 0x23u, 0x00u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x9fu, 0xfau, 0x30u, 0x00u,
+    0xffu, 0xf7u, 0x7eu, 0xfeu, 0x03u, 0x06u, 0x1au, 0xd5u, 0x7fu, 0x27u, 0xb0u, 0x3cu, 0x05u, 0x9bu, 0x38u, 0x40u,
+    0xa0u, 0x40u, 0x9cu, 0x46u, 0x60u, 0x44u, 0x05u, 0x90u, 0x30u, 0x00u, 0x07u, 0x34u, 0xffu, 0xf7u, 0x70u, 0xfeu,
+    0x03u, 0x06u, 0xf3u, 0xd4u, 0x81u, 0x21u, 0x7fu, 0x23u, 0x89u, 0x00u, 0x8cu, 0x46u, 0x03u, 0x40u, 0xa3u, 0x40u,
+    0x05u, 0x9au, 0x62u, 0x44u, 0x9bu, 0x18u, 0x05u, 0x93u, 0x5bu, 0x46u, 0x00u, 0x93u, 0xe4u, 0xe6u, 0x02u, 0x24u,
+    0xf0u, 0xe7u, 0xc0u, 0x46u, 0x03u, 0x00u, 0x00u, 0xb5u, 0xdau, 0x6cu, 0x85u, 0xb0u, 0x53u, 0x68u, 0x08u, 0x00u,
+    0x08u, 0x32u, 0x19u, 0x02u, 0x01u, 0x91u, 0x02u, 0x92u, 0x69u, 0x46u, 0x03u, 0x22u, 0x1bu, 0x0eu, 0x0au, 0x73u,
+    0x4bu, 0x73u, 0x01u, 0xa9u, 0xffu, 0xf7u, 0x76u, 0xfeu, 0x05u, 0xb0u, 0x00u, 0xbdu, 0x10u, 0xb5u, 0xffu, 0xf7u,
+    0x6du, 0xfeu, 0x80u, 0x6cu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x67u, 0xfeu, 0xc2u, 0x6cu,
+    0xd0u, 0x79u, 0x02u, 0x30u, 0x80u, 0x00u, 0x10u, 0x18u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x1cu, 0x21u, 0x01u, 0x23u,
+    0x1bu, 0x04u, 0x98u, 0x42u, 0x01u, 0xd3u, 0x00u, 0x0cu, 0x10u, 0x39u, 0x1bu, 0x0au, 0x98u, 0x42u, 0x01u, 0xd3u,
+    0x00u, 0x0au, 0x08u, 0x39u, 0x1bu, 0x09u, 0x98u, 0x42u, 0x01u, 0xd3u, 0x00u, 0x09u, 0x04u, 0x39u, 0x02u, 0xa2u,
+    0x10u, 0x5cu, 0x40u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x04u, 0x03u, 0x02u, 0x02u, 0x01u, 0x01u, 0x01u, 0x01u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x03u, 0xd1u, 0xffu, 0xf7u,
+    0xddu, 0xffu, 0x20u, 0x30u, 0x02u, 0xe0u, 0x08u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u,
+    0x06u, 0x20u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x7au, 0xf8u, 0x01u, 0x20u, 0x00u, 0xf0u, 0xa7u, 0xf8u, 0x00u, 0x00u,
+    0x08u, 0x4bu, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x00u, 0x21u, 0x00u, 0xe0u, 0x00u, 0xbfu,
+    0x05u, 0x4bu, 0x18u, 0x68u, 0x83u, 0x6au, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x20u, 0x00u, 0x00u, 0xf0u,
+    0x95u, 0xf8u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, 0xb8u, 0x1fu, 0x00u, 0x10u, 0x70u, 0xb5u, 0x00u, 0x26u,
+    0x0cu, 0x4du, 0x0du, 0x4cu, 0x64u, 0x1bu, 0xa4u, 0x10u, 0xa6u, 0x42u, 0x09u, 0xd1u, 0x00u, 0x26u, 0x00u, 0xf0u,
+    0x87u, 0xf8u, 0x0au, 0x4du, 0x0au, 0x4cu, 0x64u, 0x1bu, 0xa4u, 0x10u, 0xa6u, 0x42u, 0x05u, 0xd1u, 0x70u, 0xbdu,
+    0xb3u, 0x00u, 0xebu, 0x58u, 0x98u, 0x47u, 0x01u, 0x36u, 0xeeu, 0xe7u, 0xb3u, 0x00u, 0xebu, 0x58u, 0x98u, 0x47u,
+    0x01u, 0x36u, 0xf2u, 0xe7u, 0xe4u, 0x08u, 0x00u, 0x28u, 0xe4u, 0x08u, 0x00u, 0x28u, 0xe4u, 0x08u, 0x00u, 0x28u,
+    0xe8u, 0x08u, 0x00u, 0x28u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x9au, 0x42u, 0x00u, 0xd1u, 0x10u, 0xbdu, 0xccu, 0x5cu,
+    0xc4u, 0x54u, 0x01u, 0x33u, 0xf8u, 0xe7u, 0x03u, 0x00u, 0x82u, 0x18u, 0x93u, 0x42u, 0x00u, 0xd1u, 0x70u, 0x47u,
+    0x19u, 0x70u, 0x01u, 0x33u, 0xf9u, 0xe7u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x1fu, 0x29u, 0x04u, 0xd9u,
+    0x16u, 0x23u, 0x03u, 0x60u, 0x01u, 0x20u, 0x40u, 0x42u, 0x70u, 0xbdu, 0x43u, 0x6cu, 0x00u, 0x2bu, 0x04u, 0xd0u,
+    0x8au, 0x00u, 0x9bu, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0x08u, 0xd1u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x32u, 0xf8u,
+    0x2au, 0x00u, 0x01u, 0x00u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x1bu, 0xf8u, 0xedu, 0xe7u, 0x00u, 0x20u, 0x01u, 0x2au,
+    0xeau, 0xd0u, 0x51u, 0x1cu, 0x03u, 0xd1u, 0x16u, 0x23u, 0x01u, 0x30u, 0x23u, 0x60u, 0xe4u, 0xe7u, 0x00u, 0x24u,
+    0x28u, 0x00u, 0x1cu, 0x60u, 0x90u, 0x47u, 0x20u, 0x00u, 0xdeu, 0xe7u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x03u, 0x4bu,
+    0x01u, 0x00u, 0x18u, 0x68u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x80u, 0x08u, 0x00u, 0x28u,
+    0x00u, 0x23u, 0x70u, 0xb5u, 0x06u, 0x4du, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x2bu, 0x60u, 0x00u, 0xf0u,
+    0x15u, 0xf8u, 0x43u, 0x1cu, 0x03u, 0xd1u, 0x2bu, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x23u, 0x60u, 0x70u, 0xbdu,
+    0x6cu, 0x10u, 0x00u, 0x28u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x01u, 0xf8u, 0x10u, 0xbdu, 0x58u, 0x22u, 0x01u, 0x20u,
+    0x01u, 0x4bu, 0x40u, 0x42u, 0x1au, 0x60u, 0x70u, 0x47u, 0x6cu, 0x10u, 0x00u, 0x28u, 0x58u, 0x22u, 0x01u, 0x20u,
+    0x01u, 0x4bu, 0x40u, 0x42u, 0x1au, 0x60u, 0x70u, 0x47u, 0x6cu, 0x10u, 0x00u, 0x28u, 0xfeu, 0xe7u, 0xc0u, 0x46u,
+    0xf8u, 0xb5u, 0xc0u, 0x46u, 0xf8u, 0xbcu, 0x08u, 0xbcu, 0x9eu, 0x46u, 0x70u, 0x47u, 0xf8u, 0xb5u, 0xc0u, 0x46u,
+    0xf8u, 0xbcu, 0x08u, 0xbcu, 0x9eu, 0x46u, 0x70u, 0x47u, 0x84u, 0x08u, 0x00u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x74u, 0xb2u, 0x01u, 0x81u, 0xb0u, 0xabu, 0x30u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x08u, 0x01u, 0x81u,
+    0xb0u, 0xb0u, 0xabu, 0xf0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x3fu, 0x02u, 0x01u, 0x81u, 0xb0u, 0xabu, 0x30u, 0x80u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x06u, 0x01u, 0x81u, 0xb0u, 0xb0u, 0xabu, 0xf0u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0xd8u, 0xe0u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x70u, 0xe1u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xb0u, 0x80u,
+    0xd0u, 0xe1u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x98u, 0xefu, 0xffu, 0x7fu, 0xb0u, 0xa9u, 0x02u, 0x80u,
+    0x2cu, 0xf0u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x80u, 0xf0u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u,
+    0x8cu, 0xf0u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xaau, 0x80u, 0xc0u, 0xf0u, 0xffu, 0x7fu, 0x94u, 0xffu, 0xffu, 0x7fu,
+    0x88u, 0xf1u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x84u, 0xf1u, 0xffu, 0x7fu, 0xaau, 0x3fu, 0x39u, 0x80u,
+    0xd0u, 0xf1u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0xdcu, 0xf1u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xaau, 0x80u,
+    0x1cu, 0xf2u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x30u, 0xf2u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u,
+    0x2cu, 0xf2u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x34u, 0xf2u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u,
+    0xc4u, 0xf2u, 0xffu, 0x7fu, 0xaau, 0x0fu, 0xb2u, 0x80u, 0x2cu, 0xf3u, 0xffu, 0x7fu, 0x50u, 0xffu, 0xffu, 0x7fu,
+    0x10u, 0xf6u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x2cu, 0xf6u, 0xffu, 0x7fu, 0x4cu, 0xffu, 0xffu, 0x7fu,
+    0x8cu, 0xf8u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0xfcu, 0xf9u, 0xffu, 0x7fu, 0x00u, 0x84u, 0x04u, 0x80u,
+    0x0cu, 0xfau, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x0cu, 0xfau, 0xffu, 0x7fu, 0x38u, 0xffu, 0xffu, 0x7fu,
+    0xf4u, 0xfcu, 0xffu, 0x7fu, 0x00u, 0x84u, 0x04u, 0x80u, 0x14u, 0xfdu, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u,
+    0x2cu, 0xfdu, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0xdcu, 0x20u, 0x00u, 0x10u, 0x80u, 0x08u, 0x00u, 0x28u,
+    0x6cu, 0x00u, 0x00u, 0x00u, 0x1cu, 0x10u, 0x00u, 0x28u, 0x54u, 0x00u, 0x00u, 0x00u, 0x84u, 0x08u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0xa9u, 0x00u, 0x00u, 0x10u, 0x81u, 0x00u, 0x00u, 0x10u,
+};
+#endif /* defined(CY_DEVICE_TVIIBH4M) */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7xDUAL_CM0P_SLEEP/xmc7200d_cm0p_sleep.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7xDUAL_CM0P_SLEEP/xmc7200d_cm0p_sleep.c
new file mode 100644
index 0000000..2d27402
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7xDUAL_CM0P_SLEEP/xmc7200d_cm0p_sleep.c
@@ -0,0 +1,566 @@
+/***************************************************************************//**
+* \file xmc7200d_cm0p_sleep.c
+*
+* \brief
+* Cortex-M0+ prebuilt application image.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) 2018-2021 Cypress Semiconductor Corporation (an Infineon
+* company) or an affiliate of Cypress Semiconductor Corporation
+* SPDX-License-Identifier: LicenseRef-PBL
+*
+* Licensed under the Permissive Binary License
+*******************************************************************************/
+
+#include <stdint.h>
+#include "cy_device_headers.h"
+
+#if defined(CY_DEVICE_TVIIBH8M)
+
+#if defined(__APPLE__) && defined(__clang__)
+__attribute__ ((__section__("__CY_M0P_IMAGE,__cy_m0p_image"), used))
+#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cy_m0p_image"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cy_m0p_image"
+#else
+#error "An unsupported toolchain"
+#endif
+const uint8_t cy_m0p_image[] = {
+    0x00u, 0x00u, 0x02u, 0x28u, 0x69u, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9fu, 0x01u, 0x00u, 0x10u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x71u, 0x0au, 0x00u, 0x10u, 0xa5u, 0x0au, 0x00u, 0x10u,
+    0xd9u, 0x0au, 0x00u, 0x10u, 0x0du, 0x0bu, 0x00u, 0x10u, 0x41u, 0x0bu, 0x00u, 0x10u, 0x75u, 0x0bu, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u,
+    0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x0cu, 0x12u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0xc4u, 0x1fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u,
+    0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x10u, 0x12u, 0x00u, 0x28u, 0xc4u, 0x1fu, 0x00u, 0x10u, 0x40u, 0x22u, 0x92u, 0x02u, 0x9au, 0x1au, 0x92u, 0x46u,
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+    0xeeu, 0xe7u, 0xb3u, 0x00u, 0xebu, 0x58u, 0x98u, 0x47u, 0x01u, 0x36u, 0xf2u, 0xe7u, 0xe4u, 0x08u, 0x00u, 0x28u,
+    0xe4u, 0x08u, 0x00u, 0x28u, 0xe4u, 0x08u, 0x00u, 0x28u, 0xe8u, 0x08u, 0x00u, 0x28u, 0x00u, 0x23u, 0x10u, 0xb5u,
+    0x9au, 0x42u, 0x00u, 0xd1u, 0x10u, 0xbdu, 0xccu, 0x5cu, 0xc4u, 0x54u, 0x01u, 0x33u, 0xf8u, 0xe7u, 0x03u, 0x00u,
+    0x82u, 0x18u, 0x93u, 0x42u, 0x00u, 0xd1u, 0x70u, 0x47u, 0x19u, 0x70u, 0x01u, 0x33u, 0xf9u, 0xe7u, 0x70u, 0xb5u,
+    0x04u, 0x00u, 0x0du, 0x00u, 0x1fu, 0x29u, 0x04u, 0xd9u, 0x16u, 0x23u, 0x03u, 0x60u, 0x01u, 0x20u, 0x40u, 0x42u,
+    0x70u, 0xbdu, 0x43u, 0x6cu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x8au, 0x00u, 0x9bu, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au,
+    0x08u, 0xd1u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x32u, 0xf8u, 0x2au, 0x00u, 0x01u, 0x00u, 0x20u, 0x00u, 0x00u, 0xf0u,
+    0x1bu, 0xf8u, 0xedu, 0xe7u, 0x00u, 0x20u, 0x01u, 0x2au, 0xeau, 0xd0u, 0x51u, 0x1cu, 0x03u, 0xd1u, 0x16u, 0x23u,
+    0x01u, 0x30u, 0x23u, 0x60u, 0xe4u, 0xe7u, 0x00u, 0x24u, 0x28u, 0x00u, 0x1cu, 0x60u, 0x90u, 0x47u, 0x20u, 0x00u,
+    0xdeu, 0xe7u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x03u, 0x4bu, 0x01u, 0x00u, 0x18u, 0x68u, 0xffu, 0xf7u, 0xcfu, 0xffu,
+    0x10u, 0xbdu, 0xc0u, 0x46u, 0x80u, 0x08u, 0x00u, 0x28u, 0x00u, 0x23u, 0x70u, 0xb5u, 0x06u, 0x4du, 0x04u, 0x00u,
+    0x08u, 0x00u, 0x11u, 0x00u, 0x2bu, 0x60u, 0x00u, 0xf0u, 0x15u, 0xf8u, 0x43u, 0x1cu, 0x03u, 0xd1u, 0x2bu, 0x68u,
+    0x00u, 0x2bu, 0x00u, 0xd0u, 0x23u, 0x60u, 0x70u, 0xbdu, 0x5cu, 0x12u, 0x00u, 0x28u, 0x10u, 0xb5u, 0x00u, 0xf0u,
+    0x01u, 0xf8u, 0x10u, 0xbdu, 0x58u, 0x22u, 0x01u, 0x20u, 0x01u, 0x4bu, 0x40u, 0x42u, 0x1au, 0x60u, 0x70u, 0x47u,
+    0x5cu, 0x12u, 0x00u, 0x28u, 0x58u, 0x22u, 0x01u, 0x20u, 0x01u, 0x4bu, 0x40u, 0x42u, 0x1au, 0x60u, 0x70u, 0x47u,
+    0x5cu, 0x12u, 0x00u, 0x28u, 0xfeu, 0xe7u, 0xc0u, 0x46u, 0xf8u, 0xb5u, 0xc0u, 0x46u, 0xf8u, 0xbcu, 0x08u, 0xbcu,
+    0x9eu, 0x46u, 0x70u, 0x47u, 0xf8u, 0xb5u, 0xc0u, 0x46u, 0xf8u, 0xbcu, 0x08u, 0xbcu, 0x9eu, 0x46u, 0x70u, 0x47u,
+    0x84u, 0x08u, 0x00u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x74u, 0xb2u, 0x01u, 0x81u, 0xb0u, 0xabu, 0x30u, 0x80u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x08u, 0x01u, 0x81u, 0xb0u, 0xb0u, 0xabu, 0xf0u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x3fu, 0x02u, 0x01u, 0x81u, 0xb0u, 0xabu, 0x30u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x06u, 0x01u, 0x81u,
+    0xb0u, 0xb0u, 0xabu, 0xf0u, 0x00u, 0x00u, 0x00u, 0x00u, 0xd0u, 0xe0u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u,
+    0x68u, 0xe1u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xb0u, 0x80u, 0xc8u, 0xe1u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u,
+    0x98u, 0xefu, 0xffu, 0x7fu, 0xb0u, 0xa9u, 0x02u, 0x80u, 0x2cu, 0xf0u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u,
+    0x80u, 0xf0u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x8cu, 0xf0u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xaau, 0x80u,
+    0xc0u, 0xf0u, 0xffu, 0x7fu, 0x94u, 0xffu, 0xffu, 0x7fu, 0x88u, 0xf1u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u,
+    0x84u, 0xf1u, 0xffu, 0x7fu, 0xaau, 0x3fu, 0x39u, 0x80u, 0xd0u, 0xf1u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u,
+    0xdcu, 0xf1u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xaau, 0x80u, 0x1cu, 0xf2u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u,
+    0x30u, 0xf2u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x2cu, 0xf2u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u,
+    0x34u, 0xf2u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0xc4u, 0xf2u, 0xffu, 0x7fu, 0xaau, 0x0fu, 0xb2u, 0x80u,
+    0x2cu, 0xf3u, 0xffu, 0x7fu, 0x50u, 0xffu, 0xffu, 0x7fu, 0x10u, 0xf6u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u,
+    0x2cu, 0xf6u, 0xffu, 0x7fu, 0x4cu, 0xffu, 0xffu, 0x7fu, 0x8cu, 0xf8u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u,
+    0xfcu, 0xf9u, 0xffu, 0x7fu, 0x00u, 0x84u, 0x04u, 0x80u, 0x0cu, 0xfau, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u,
+    0x0cu, 0xfau, 0xffu, 0x7fu, 0x38u, 0xffu, 0xffu, 0x7fu, 0xf4u, 0xfcu, 0xffu, 0x7fu, 0x00u, 0x84u, 0x04u, 0x80u,
+    0x14u, 0xfdu, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x2cu, 0xfdu, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u,
+    0xe4u, 0x20u, 0x00u, 0x10u, 0x80u, 0x08u, 0x00u, 0x28u, 0x6cu, 0x00u, 0x00u, 0x00u, 0x0cu, 0x12u, 0x00u, 0x28u,
+    0x54u, 0x00u, 0x00u, 0x00u, 0x84u, 0x08u, 0x00u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xa9u, 0x00u, 0x00u, 0x10u, 0x81u, 0x00u, 0x00u, 0x10u,
+   
+};
+#endif /* defined(CY_DEVICE_TVIIBH8M) */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/README.md b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/README.md
new file mode 100644
index 0000000..ec1a18b
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/README.md
@@ -0,0 +1,27 @@
+# XMC7x Cortex M0+ DeepSleep prebuilt image (XMC7x_CM0P_SLEEP)
+
+### Overview
+DeepSleep prebuilt application image is executed on the Cortex M0+ core of the XMC dual-core MCU.
+The image is provided as C array ready to be compiled as part of the Cortex M7_0 application.
+The Cortex M0+ application code is placed to internal flash by the Cortex M7_0 linker script.
+
+DeepSleep prebuilt image executes the following steps:
+- starts CM7_0 core at CY_CORTEX_M7_0_APPL_ADDR. (check the address in partition.h in pdl repo)
+- puts the CM0+ core into Deep Sleep.
+
+### Usage
+
+This image is used by default by all Infineon BSPs that target XMC Dual-Core MCU.
+
+To use this image in the custom BSP, adjust the BSP target makefile to
+add the COMPONENT_XMC7x_CM0P_SLEEP directory to the list of components
+discovered by ModusToolbox build system:
+
+```
+COMPONENTS+=XMC7x_CM0P_SLEEP
+```
+
+Make sure there is a single XMC7x_CM0P_* component included in the COMPONENTS list.
+
+---
+Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation.
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/xmc7100_cm0p_sleep.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/xmc7100_cm0p_sleep.c
new file mode 100644
index 0000000..c71ed4b
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/xmc7100_cm0p_sleep.c
@@ -0,0 +1,561 @@
+/***************************************************************************//**
+* \file xmc7100_cm0p_sleep.c
+*
+* \brief
+* Cortex-M0+ prebuilt application image.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) 2018-2021 Cypress Semiconductor Corporation (an Infineon
+* company) or an affiliate of Cypress Semiconductor Corporation
+* SPDX-License-Identifier: LicenseRef-PBL
+*
+* Licensed under the Permissive Binary License
+*******************************************************************************/
+
+#include <stdint.h>
+#include "cy_device_headers.h"
+
+#if defined(CY_DEVICE_TVIIBH4M)
+
+#if defined(__APPLE__) && defined(__clang__)
+__attribute__ ((__section__("__CY_M0P_IMAGE,__cy_m0p_image"), used))
+#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cy_m0p_image"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cy_m0p_image"
+#else
+#error "An unsupported toolchain"
+#endif
+const uint8_t cy_m0p_image[] = {
+    0x00u, 0x00u, 0x02u, 0x28u, 0x69u, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9fu, 0x01u, 0x00u, 0x10u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x25u, 0x0au, 0x00u, 0x10u, 0x59u, 0x0au, 0x00u, 0x10u,
+    0x8du, 0x0au, 0x00u, 0x10u, 0xc1u, 0x0au, 0x00u, 0x10u, 0xf5u, 0x0au, 0x00u, 0x10u, 0x29u, 0x0bu, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u,
+    0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x1cu, 0x10u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x78u, 0x1fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u,
+    0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x20u, 0x10u, 0x00u, 0x28u, 0x78u, 0x1fu, 0x00u, 0x10u, 0x40u, 0x22u, 0x92u, 0x02u, 0x9au, 0x1au, 0x92u, 0x46u,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x17u, 0x4bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x13u, 0x4bu, 0x9du, 0x46u, 0xffu, 0xf7u,
+    0xf3u, 0xffu, 0x00u, 0x21u, 0x8bu, 0x46u, 0x0fu, 0x46u, 0x13u, 0x48u, 0x14u, 0x4au, 0x12u, 0x1au, 0x01u, 0xf0u,
+    0xd0u, 0xfeu, 0x0eu, 0x4bu, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x0du, 0x4bu, 0x00u, 0x2bu, 0x00u, 0xd0u,
+    0x98u, 0x47u, 0x00u, 0x20u, 0x00u, 0x21u, 0x04u, 0x00u, 0x0du, 0x00u, 0x0du, 0x48u, 0x00u, 0x28u, 0x02u, 0xd0u,
+    0x0cu, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0xf0u, 0x8fu, 0xfeu, 0x20u, 0x00u, 0x29u, 0x00u, 0x00u, 0xf0u,
+    0x07u, 0xfbu, 0x01u, 0xf0u, 0x73u, 0xfeu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x55u, 0x07u, 0x00u, 0x10u, 0x00u, 0x00u, 0x02u, 0x28u, 0x1cu, 0x10u, 0x00u, 0x28u, 0x70u, 0x10u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u,
+    0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u,
+    0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x01u, 0x20u, 0xc0u, 0x04u, 0x13u, 0x49u, 0x0au, 0x68u,
+    0x02u, 0x43u, 0x0au, 0x60u, 0x12u, 0x49u, 0x0au, 0x68u, 0x02u, 0x43u, 0x0au, 0x60u, 0x11u, 0x49u, 0x0au, 0x68u,
+    0x02u, 0x43u, 0x0au, 0x60u, 0x10u, 0x48u, 0x11u, 0x49u, 0x00u, 0x22u, 0x00u, 0x23u, 0x0cu, 0xc0u, 0x88u, 0x42u,
+    0xfcu, 0xd3u, 0x00u, 0xf0u, 0x4du, 0xfbu, 0x00u, 0xf0u, 0xe1u, 0xfau, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u,
+    0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x02u, 0xe0u, 0xefu, 0xf3u,
+    0x08u, 0x80u, 0x04u, 0x30u, 0x00u, 0xf0u, 0xe4u, 0xf9u, 0xfeu, 0xe7u, 0x00u, 0x00u, 0x00u, 0x13u, 0x20u, 0x40u,
+    0x80u, 0x13u, 0x20u, 0x40u, 0xa0u, 0x13u, 0x20u, 0x40u, 0x00u, 0xffu, 0x01u, 0x28u, 0x00u, 0x00u, 0x02u, 0x28u,
+    0x92u, 0x23u, 0xdbu, 0x00u, 0xc0u, 0x18u, 0x03u, 0x4bu, 0x80u, 0x00u, 0xc0u, 0x58u, 0x80u, 0x06u, 0x80u, 0x0fu,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x03u, 0x00u, 0x00u, 0x20u, 0x07u, 0x2bu, 0x08u, 0xd8u,
+    0x92u, 0x22u, 0xd2u, 0x00u, 0x9bu, 0x18u, 0x03u, 0x4au, 0x9bu, 0x00u, 0x9bu, 0x58u, 0x01u, 0x30u, 0x1bu, 0x0au,
+    0x98u, 0x43u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x02u, 0x4bu, 0x18u, 0x69u, 0x40u, 0x07u, 0xc0u, 0x0fu,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x27u, 0x40u, 0x04u, 0x4bu, 0x05u, 0x4au, 0xd0u, 0x58u, 0x03u, 0x23u,
+    0x18u, 0x40u, 0x98u, 0x42u, 0x00u, 0xd1u, 0x02u, 0x20u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x24u, 0x15u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u,
+    0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x3cu, 0x10u, 0x00u, 0x28u, 0x09u, 0x4au, 0x83u, 0x00u,
+    0x99u, 0x18u, 0x90u, 0x22u, 0x52u, 0x01u, 0x88u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u,
+    0x05u, 0x4au, 0x9bu, 0x18u, 0x58u, 0x68u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xfcu, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u,
+    0xe5u, 0xffu, 0x88u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0x19u, 0xd0u, 0x09u, 0xd8u, 0x01u, 0x28u, 0x10u, 0xd0u,
+    0x02u, 0x28u, 0x11u, 0xd0u, 0x43u, 0x42u, 0x58u, 0x41u, 0x0fu, 0x4bu, 0x40u, 0x42u, 0x18u, 0x40u, 0x10u, 0xbdu,
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+    0x01u, 0x00u, 0x00u, 0x00u, 0x98u, 0x20u, 0x00u, 0x10u, 0x80u, 0x08u, 0x00u, 0x28u, 0x6cu, 0x00u, 0x00u, 0x00u,
+    0x1cu, 0x10u, 0x00u, 0x28u, 0x54u, 0x00u, 0x00u, 0x00u, 0x84u, 0x08u, 0x00u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xa9u, 0x00u, 0x00u, 0x10u,
+    0x81u, 0x00u, 0x00u, 0x10u,
+};
+#endif /* defined(CY_DEVICE_TVIIBH4M) */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/xmc7200_cm0p_sleep.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/xmc7200_cm0p_sleep.c
new file mode 100644
index 0000000..82f3e6c
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/xmc7200_cm0p_sleep.c
@@ -0,0 +1,561 @@
+/***************************************************************************//**
+* \file xmc7200_cm0p_sleep.c
+*
+* \brief
+* Cortex-M0+ prebuilt application image.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) 2018-2021 Cypress Semiconductor Corporation (an Infineon
+* company) or an affiliate of Cypress Semiconductor Corporation
+* SPDX-License-Identifier: LicenseRef-PBL
+*
+* Licensed under the Permissive Binary License
+*******************************************************************************/
+
+#include <stdint.h>
+#include "cy_device_headers.h"
+
+#if defined(CY_DEVICE_TVIIBH8M)
+
+#if defined(__APPLE__) && defined(__clang__)
+__attribute__ ((__section__("__CY_M0P_IMAGE,__cy_m0p_image"), used))
+#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cy_m0p_image"), used))
+#elif defined(__ICCARM__)
+#pragma  location=".cy_m0p_image"
+#else
+#error "An unsupported toolchain"
+#endif
+const uint8_t cy_m0p_image[] = {
+    0x00u, 0x00u, 0x02u, 0x28u, 0x69u, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9fu, 0x01u, 0x00u, 0x10u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x2du, 0x0au, 0x00u, 0x10u, 0x61u, 0x0au, 0x00u, 0x10u,
+    0x95u, 0x0au, 0x00u, 0x10u, 0xc9u, 0x0au, 0x00u, 0x10u, 0xfdu, 0x0au, 0x00u, 0x10u, 0x31u, 0x0bu, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u, 0x9bu, 0x01u, 0x00u, 0x10u,
+    0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u,
+    0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x0cu, 0x12u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x1fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u,
+    0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x10u, 0x12u, 0x00u, 0x28u, 0x80u, 0x1fu, 0x00u, 0x10u, 0x40u, 0x22u, 0x92u, 0x02u, 0x9au, 0x1au, 0x92u, 0x46u,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x17u, 0x4bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x13u, 0x4bu, 0x9du, 0x46u, 0xffu, 0xf7u,
+    0xf3u, 0xffu, 0x00u, 0x21u, 0x8bu, 0x46u, 0x0fu, 0x46u, 0x13u, 0x48u, 0x14u, 0x4au, 0x12u, 0x1au, 0x01u, 0xf0u,
+    0xd4u, 0xfeu, 0x0eu, 0x4bu, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x0du, 0x4bu, 0x00u, 0x2bu, 0x00u, 0xd0u,
+    0x98u, 0x47u, 0x00u, 0x20u, 0x00u, 0x21u, 0x04u, 0x00u, 0x0du, 0x00u, 0x0du, 0x48u, 0x00u, 0x28u, 0x02u, 0xd0u,
+    0x0cu, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0xf0u, 0x93u, 0xfeu, 0x20u, 0x00u, 0x29u, 0x00u, 0x00u, 0xf0u,
+    0x07u, 0xfbu, 0x01u, 0xf0u, 0x77u, 0xfeu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x55u, 0x07u, 0x00u, 0x10u, 0x00u, 0x00u, 0x02u, 0x28u, 0x0cu, 0x12u, 0x00u, 0x28u, 0x60u, 0x12u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u,
+    0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u,
+    0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x01u, 0x20u, 0xc0u, 0x04u, 0x13u, 0x49u, 0x0au, 0x68u,
+    0x02u, 0x43u, 0x0au, 0x60u, 0x12u, 0x49u, 0x0au, 0x68u, 0x02u, 0x43u, 0x0au, 0x60u, 0x11u, 0x49u, 0x0au, 0x68u,
+    0x02u, 0x43u, 0x0au, 0x60u, 0x10u, 0x48u, 0x11u, 0x49u, 0x00u, 0x22u, 0x00u, 0x23u, 0x0cu, 0xc0u, 0x88u, 0x42u,
+    0xfcu, 0xd3u, 0x00u, 0xf0u, 0x4fu, 0xfbu, 0x00u, 0xf0u, 0xe1u, 0xfau, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u,
+    0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x02u, 0xe0u, 0xefu, 0xf3u,
+    0x08u, 0x80u, 0x04u, 0x30u, 0x00u, 0xf0u, 0xe4u, 0xf9u, 0xfeu, 0xe7u, 0x00u, 0x00u, 0x00u, 0x13u, 0x20u, 0x40u,
+    0x80u, 0x13u, 0x20u, 0x40u, 0xa0u, 0x13u, 0x20u, 0x40u, 0x00u, 0xffu, 0x01u, 0x28u, 0x00u, 0x00u, 0x02u, 0x28u,
+    0x92u, 0x23u, 0xdbu, 0x00u, 0xc0u, 0x18u, 0x03u, 0x4bu, 0x80u, 0x00u, 0xc0u, 0x58u, 0x80u, 0x06u, 0x80u, 0x0fu,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x03u, 0x00u, 0x00u, 0x20u, 0x07u, 0x2bu, 0x08u, 0xd8u,
+    0x92u, 0x22u, 0xd2u, 0x00u, 0x9bu, 0x18u, 0x03u, 0x4au, 0x9bu, 0x00u, 0x9bu, 0x58u, 0x01u, 0x30u, 0x1bu, 0x0au,
+    0x98u, 0x43u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x02u, 0x4bu, 0x18u, 0x69u, 0x40u, 0x07u, 0xc0u, 0x0fu,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x27u, 0x40u, 0x04u, 0x4bu, 0x05u, 0x4au, 0xd0u, 0x58u, 0x03u, 0x23u,
+    0x18u, 0x40u, 0x98u, 0x42u, 0x00u, 0xd1u, 0x02u, 0x20u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x24u, 0x15u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u,
+    0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x2cu, 0x12u, 0x00u, 0x28u, 0x09u, 0x4au, 0x83u, 0x00u,
+    0x99u, 0x18u, 0x90u, 0x22u, 0x52u, 0x01u, 0x88u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u,
+    0x05u, 0x4au, 0x9bu, 0x18u, 0x58u, 0x68u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u,
+    0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xfcu, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u,
+    0xe5u, 0xffu, 0x88u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0x19u, 0xd0u, 0x09u, 0xd8u, 0x01u, 0x28u, 0x10u, 0xd0u,
+    0x02u, 0x28u, 0x11u, 0xd0u, 0x43u, 0x42u, 0x58u, 0x41u, 0x0fu, 0x4bu, 0x40u, 0x42u, 0x18u, 0x40u, 0x10u, 0xbdu,
+    0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x12u, 0xd0u, 0x03u, 0x33u, 0x98u, 0x42u, 0x07u, 0xd0u, 0x00u, 0x20u,
+    0xf5u, 0xe7u, 0x0au, 0x4bu, 0x18u, 0x68u, 0xf2u, 0xe7u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0xefu, 0xe7u, 0x08u, 0x4au,
+    0x08u, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0xf2u, 0xdau, 0x80u, 0x20u, 0x00u, 0x02u, 0xe7u, 0xe7u, 0xffu, 0xf7u,
+    0x9bu, 0xffu, 0x00u, 0x28u, 0xebu, 0xd0u, 0xf7u, 0xe7u, 0x00u, 0x12u, 0x7au, 0x00u, 0x28u, 0x12u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x15u, 0x00u, 0x00u, 0x14u, 0x4au, 0x15u, 0x4bu, 0x10u, 0xb5u, 0xd3u, 0x58u,
+    0x0fu, 0x24u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u,
+    0xd3u, 0x58u, 0xd9u, 0x04u, 0x1bu, 0x0cu, 0xdbu, 0xb2u, 0x03u, 0x81u, 0x0fu, 0x4bu, 0xc9u, 0x0cu, 0xd3u, 0x58u,
+    0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, 0xc1u, 0x72u, 0xd9u, 0x02u,
+    0x9bu, 0x00u, 0x9bu, 0x0fu, 0x83u, 0x73u, 0x09u, 0x4bu, 0xc9u, 0x0cu, 0xd3u, 0x58u, 0x81u, 0x81u, 0x5au, 0x05u,
+    0xdbu, 0x01u, 0x52u, 0x0fu, 0xdbu, 0x0du, 0x82u, 0x71u, 0x03u, 0x82u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u,
+    0x30u, 0x15u, 0x00u, 0x00u, 0x34u, 0x15u, 0x00u, 0x00u, 0x38u, 0x15u, 0x00u, 0x00u, 0x3cu, 0x15u, 0x00u, 0x00u,
+    0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x18u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x9du, 0xfdu,
+    0x14u, 0x4bu, 0x28u, 0x01u, 0xc5u, 0x18u, 0xc8u, 0x23u, 0x1fu, 0x26u, 0x5bu, 0x01u, 0xebu, 0x58u, 0x19u, 0x0au,
+    0x31u, 0x40u, 0x61u, 0x70u, 0x07u, 0x21u, 0x23u, 0x70u, 0x1au, 0x0cu, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0x32u, 0x40u,
+    0x23u, 0x71u, 0x0du, 0x4bu, 0xa2u, 0x70u, 0xebu, 0x58u, 0x1au, 0x02u, 0x12u, 0x0au, 0xa2u, 0x60u, 0x1au, 0x0fu,
+    0xf3u, 0x40u, 0x0au, 0x40u, 0x55u, 0x1eu, 0xaau, 0x41u, 0x63u, 0x73u, 0x08u, 0x4bu, 0x22u, 0x73u, 0xc0u, 0x18u,
+    0x03u, 0x68u, 0x00u, 0x20u, 0xdau, 0xb2u, 0x22u, 0x61u, 0x1au, 0x0cu, 0xf3u, 0x40u, 0x11u, 0x40u, 0x21u, 0x75u,
+    0x63u, 0x75u, 0x70u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, 0x04u, 0x19u, 0x00u, 0x00u, 0x08u, 0x19u, 0x26u, 0x40u,
+    0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x18u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x65u, 0xfdu,
+    0xb0u, 0x23u, 0x7fu, 0x22u, 0x1fu, 0x20u, 0xdbu, 0x00u, 0xedu, 0x18u, 0x09u, 0x4bu, 0xadu, 0x00u, 0xebu, 0x58u,
+    0x1au, 0x40u, 0x22u, 0x70u, 0x1au, 0x0cu, 0x02u, 0x40u, 0xa2u, 0x70u, 0x1au, 0x01u, 0xc2u, 0x40u, 0x19u, 0x0au,
+    0x9bu, 0x00u, 0x01u, 0x40u, 0x9bu, 0x0fu, 0x00u, 0x20u, 0x61u, 0x70u, 0xe2u, 0x70u, 0x23u, 0x71u, 0x70u, 0xbdu,
+    0x00u, 0x00u, 0x26u, 0x40u, 0x42u, 0x1eu, 0x06u, 0x4bu, 0x01u, 0x2au, 0x05u, 0xd8u, 0x90u, 0x30u, 0xffu, 0x30u,
+    0x00u, 0x01u, 0x18u, 0x58u, 0xc0u, 0x0fu, 0x70u, 0x47u, 0x02u, 0x4au, 0x80u, 0x18u, 0x80u, 0x00u, 0xf8u, 0xe7u,
+    0x00u, 0x00u, 0x26u, 0x40u, 0x7du, 0x05u, 0x00u, 0x00u, 0x03u, 0x00u, 0x01u, 0x38u, 0x10u, 0xb5u, 0x01u, 0x28u,
+    0x02u, 0xd8u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x10u, 0xbdu, 0xd8u, 0x1eu, 0xffu, 0xf7u, 0xc1u, 0xffu, 0xfau, 0xe7u,
+    0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x3du, 0xd1u,
+    0x14u, 0x22u, 0x21u, 0x00u, 0x04u, 0xa8u, 0x01u, 0xf0u, 0x20u, 0xfdu, 0x04u, 0xa8u, 0xffu, 0xf7u, 0x44u, 0xffu,
+    0x33u, 0x4au, 0x34u, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x04u, 0xabu, 0x9cu, 0x7bu, 0x02u, 0x3cu,
+    0x63u, 0x1eu, 0x9cu, 0x41u, 0x04u, 0xa9u, 0xc8u, 0x79u, 0x01u, 0x23u, 0x41u, 0x1eu, 0x88u, 0x41u, 0x00u, 0x27u,
+    0x04u, 0xaau, 0x04u, 0x9du, 0x92u, 0x88u, 0x1cu, 0x40u, 0xc0u, 0x18u, 0x03u, 0x93u, 0x00u, 0x2cu, 0x1au, 0xd0u,
+    0x00u, 0x2au, 0x18u, 0xd0u, 0x00u, 0x23u, 0x19u, 0x00u, 0x00u, 0xf0u, 0x10u, 0xfcu, 0x02u, 0x90u, 0x01u, 0x91u,
+    0x00u, 0x2fu, 0x30u, 0xd0u, 0x29u, 0x0au, 0x28u, 0x06u, 0x00u, 0x25u, 0x03u, 0x9cu, 0x32u, 0x00u, 0x2bu, 0x00u,
+    0x00u, 0x19u, 0x69u, 0x41u, 0x00u, 0xf0u, 0x02u, 0xfcu, 0x02u, 0x9au, 0x01u, 0x9bu, 0x00u, 0xf0u, 0xdeu, 0xfbu,
+    0x0eu, 0x02u, 0x00u, 0x0eu, 0x06u, 0x43u, 0x30u, 0x00u, 0x0bu, 0xb0u, 0xf0u, 0xbdu, 0x04u, 0x2cu, 0xfau, 0xd8u,
+    0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x01u, 0xf0u, 0xe0u, 0xfcu, 0x20u, 0x00u, 0x04u, 0xa9u, 0xffu, 0xf7u,
+    0xa3u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8eu, 0xffu, 0x00u, 0x24u, 0xa0u, 0x42u, 0x04u, 0xd0u, 0x04u, 0xabu,
+    0x1cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x04u, 0xabu, 0x1du, 0x78u, 0x5au, 0x78u, 0x98u, 0x78u,
+    0x5fu, 0x7bu, 0x06u, 0x9bu, 0xc1u, 0xe7u, 0x32u, 0x00u, 0x3bu, 0x00u, 0x28u, 0x00u, 0x39u, 0x00u, 0x00u, 0xf0u,
+    0xd5u, 0xfbu, 0x02u, 0x9cu, 0x01u, 0x9bu, 0x62u, 0x08u, 0x01u, 0x9cu, 0xdeu, 0x07u, 0x32u, 0x43u, 0x63u, 0x08u,
+    0x80u, 0x18u, 0x59u, 0x41u, 0x23u, 0x00u, 0x02u, 0x9au, 0x00u, 0xf0u, 0xa8u, 0xfbu, 0x06u, 0x00u, 0xcau, 0xe7u,
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+    0x05u, 0xabu, 0x00u, 0x93u, 0x9bu, 0x46u, 0x0du, 0x22u, 0x00u, 0x23u, 0x00u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u,
+    0x9fu, 0xfau, 0x30u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xfeu, 0x03u, 0x06u, 0x1au, 0xd5u, 0x7fu, 0x27u, 0xb0u, 0x3cu,
+    0x05u, 0x9bu, 0x38u, 0x40u, 0xa0u, 0x40u, 0x9cu, 0x46u, 0x60u, 0x44u, 0x05u, 0x90u, 0x30u, 0x00u, 0x07u, 0x34u,
+    0xffu, 0xf7u, 0x70u, 0xfeu, 0x03u, 0x06u, 0xf3u, 0xd4u, 0x81u, 0x21u, 0x7fu, 0x23u, 0x89u, 0x00u, 0x8cu, 0x46u,
+    0x03u, 0x40u, 0xa3u, 0x40u, 0x05u, 0x9au, 0x62u, 0x44u, 0x9bu, 0x18u, 0x05u, 0x93u, 0x5bu, 0x46u, 0x00u, 0x93u,
+    0xe4u, 0xe6u, 0x02u, 0x24u, 0xf0u, 0xe7u, 0xc0u, 0x46u, 0x03u, 0x00u, 0x00u, 0xb5u, 0xdau, 0x6cu, 0x85u, 0xb0u,
+    0x53u, 0x68u, 0x08u, 0x00u, 0x08u, 0x32u, 0x19u, 0x02u, 0x01u, 0x91u, 0x02u, 0x92u, 0x69u, 0x46u, 0x03u, 0x22u,
+    0x1bu, 0x0eu, 0x0au, 0x73u, 0x4bu, 0x73u, 0x01u, 0xa9u, 0xffu, 0xf7u, 0x76u, 0xfeu, 0x05u, 0xb0u, 0x00u, 0xbdu,
+    0x10u, 0xb5u, 0xffu, 0xf7u, 0x6du, 0xfeu, 0x80u, 0x6cu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x10u, 0xb5u, 0xffu, 0xf7u,
+    0x67u, 0xfeu, 0xc2u, 0x6cu, 0xd0u, 0x79u, 0x02u, 0x30u, 0x80u, 0x00u, 0x10u, 0x18u, 0x10u, 0xbdu, 0xc0u, 0x46u,
+    0x1cu, 0x21u, 0x01u, 0x23u, 0x1bu, 0x04u, 0x98u, 0x42u, 0x01u, 0xd3u, 0x00u, 0x0cu, 0x10u, 0x39u, 0x1bu, 0x0au,
+    0x98u, 0x42u, 0x01u, 0xd3u, 0x00u, 0x0au, 0x08u, 0x39u, 0x1bu, 0x09u, 0x98u, 0x42u, 0x01u, 0xd3u, 0x00u, 0x09u,
+    0x04u, 0x39u, 0x02u, 0xa2u, 0x10u, 0x5cu, 0x40u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x04u, 0x03u, 0x02u, 0x02u,
+    0x01u, 0x01u, 0x01u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u,
+    0x03u, 0xd1u, 0xffu, 0xf7u, 0xddu, 0xffu, 0x20u, 0x30u, 0x02u, 0xe0u, 0x08u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xffu,
+    0x10u, 0xbdu, 0xc0u, 0x46u, 0x06u, 0x20u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x7au, 0xf8u, 0x01u, 0x20u, 0x00u, 0xf0u,
+    0xa7u, 0xf8u, 0x00u, 0x00u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x00u, 0x21u,
+    0x00u, 0xe0u, 0x00u, 0xbfu, 0x05u, 0x4bu, 0x18u, 0x68u, 0x83u, 0x6au, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u,
+    0x20u, 0x00u, 0x00u, 0xf0u, 0x95u, 0xf8u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7cu, 0x1fu, 0x00u, 0x10u,
+    0x70u, 0xb5u, 0x00u, 0x26u, 0x0cu, 0x4du, 0x0du, 0x4cu, 0x64u, 0x1bu, 0xa4u, 0x10u, 0xa6u, 0x42u, 0x09u, 0xd1u,
+    0x00u, 0x26u, 0x00u, 0xf0u, 0x87u, 0xf8u, 0x0au, 0x4du, 0x0au, 0x4cu, 0x64u, 0x1bu, 0xa4u, 0x10u, 0xa6u, 0x42u,
+    0x05u, 0xd1u, 0x70u, 0xbdu, 0xb3u, 0x00u, 0xebu, 0x58u, 0x98u, 0x47u, 0x01u, 0x36u, 0xeeu, 0xe7u, 0xb3u, 0x00u,
+    0xebu, 0x58u, 0x98u, 0x47u, 0x01u, 0x36u, 0xf2u, 0xe7u, 0xe4u, 0x08u, 0x00u, 0x28u, 0xe4u, 0x08u, 0x00u, 0x28u,
+    0xe4u, 0x08u, 0x00u, 0x28u, 0xe8u, 0x08u, 0x00u, 0x28u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x9au, 0x42u, 0x00u, 0xd1u,
+    0x10u, 0xbdu, 0xccu, 0x5cu, 0xc4u, 0x54u, 0x01u, 0x33u, 0xf8u, 0xe7u, 0x03u, 0x00u, 0x82u, 0x18u, 0x93u, 0x42u,
+    0x00u, 0xd1u, 0x70u, 0x47u, 0x19u, 0x70u, 0x01u, 0x33u, 0xf9u, 0xe7u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u,
+    0x1fu, 0x29u, 0x04u, 0xd9u, 0x16u, 0x23u, 0x03u, 0x60u, 0x01u, 0x20u, 0x40u, 0x42u, 0x70u, 0xbdu, 0x43u, 0x6cu,
+    0x00u, 0x2bu, 0x04u, 0xd0u, 0x8au, 0x00u, 0x9bu, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0x08u, 0xd1u, 0x20u, 0x00u,
+    0x00u, 0xf0u, 0x32u, 0xf8u, 0x2au, 0x00u, 0x01u, 0x00u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x1bu, 0xf8u, 0xedu, 0xe7u,
+    0x00u, 0x20u, 0x01u, 0x2au, 0xeau, 0xd0u, 0x51u, 0x1cu, 0x03u, 0xd1u, 0x16u, 0x23u, 0x01u, 0x30u, 0x23u, 0x60u,
+    0xe4u, 0xe7u, 0x00u, 0x24u, 0x28u, 0x00u, 0x1cu, 0x60u, 0x90u, 0x47u, 0x20u, 0x00u, 0xdeu, 0xe7u, 0x00u, 0x00u,
+    0x10u, 0xb5u, 0x03u, 0x4bu, 0x01u, 0x00u, 0x18u, 0x68u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u,
+    0x80u, 0x08u, 0x00u, 0x28u, 0x00u, 0x23u, 0x70u, 0xb5u, 0x06u, 0x4du, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u,
+    0x2bu, 0x60u, 0x00u, 0xf0u, 0x15u, 0xf8u, 0x43u, 0x1cu, 0x03u, 0xd1u, 0x2bu, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd0u,
+    0x23u, 0x60u, 0x70u, 0xbdu, 0x5cu, 0x12u, 0x00u, 0x28u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x01u, 0xf8u, 0x10u, 0xbdu,
+    0x58u, 0x22u, 0x01u, 0x20u, 0x01u, 0x4bu, 0x40u, 0x42u, 0x1au, 0x60u, 0x70u, 0x47u, 0x5cu, 0x12u, 0x00u, 0x28u,
+    0x58u, 0x22u, 0x01u, 0x20u, 0x01u, 0x4bu, 0x40u, 0x42u, 0x1au, 0x60u, 0x70u, 0x47u, 0x5cu, 0x12u, 0x00u, 0x28u,
+    0xfeu, 0xe7u, 0xc0u, 0x46u, 0xf8u, 0xb5u, 0xc0u, 0x46u, 0xf8u, 0xbcu, 0x08u, 0xbcu, 0x9eu, 0x46u, 0x70u, 0x47u,
+    0xf8u, 0xb5u, 0xc0u, 0x46u, 0xf8u, 0xbcu, 0x08u, 0xbcu, 0x9eu, 0x46u, 0x70u, 0x47u, 0x84u, 0x08u, 0x00u, 0x28u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x74u, 0xb2u, 0x01u, 0x81u, 0xb0u, 0xabu, 0x30u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x80u, 0x08u, 0x01u, 0x81u, 0xb0u, 0xb0u, 0xabu, 0xf0u, 0x00u, 0x00u, 0x00u, 0x00u, 0x3fu, 0x02u, 0x01u, 0x81u,
+    0xb0u, 0xabu, 0x30u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x06u, 0x01u, 0x81u, 0xb0u, 0xb0u, 0xabu, 0xf0u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x14u, 0xe1u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0xacu, 0xe1u, 0xffu, 0x7fu,
+    0xb0u, 0xb0u, 0xb0u, 0x80u, 0x0cu, 0xe2u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x98u, 0xefu, 0xffu, 0x7fu,
+    0xb0u, 0xa9u, 0x02u, 0x80u, 0x2cu, 0xf0u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x80u, 0xf0u, 0xffu, 0x7fu,
+    0x01u, 0x00u, 0x00u, 0x00u, 0x8cu, 0xf0u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xaau, 0x80u, 0xc0u, 0xf0u, 0xffu, 0x7fu,
+    0x94u, 0xffu, 0xffu, 0x7fu, 0x88u, 0xf1u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0x84u, 0xf1u, 0xffu, 0x7fu,
+    0xaau, 0x3fu, 0x39u, 0x80u, 0xd0u, 0xf1u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0xdcu, 0xf1u, 0xffu, 0x7fu,
+    0xb0u, 0xb0u, 0xaau, 0x80u, 0x1cu, 0xf2u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x30u, 0xf2u, 0xffu, 0x7fu,
+    0x01u, 0x00u, 0x00u, 0x00u, 0x2cu, 0xf2u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x34u, 0xf2u, 0xffu, 0x7fu,
+    0x01u, 0x00u, 0x00u, 0x00u, 0xc4u, 0xf2u, 0xffu, 0x7fu, 0xaau, 0x0fu, 0xb2u, 0x80u, 0x2cu, 0xf3u, 0xffu, 0x7fu,
+    0x50u, 0xffu, 0xffu, 0x7fu, 0x10u, 0xf6u, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x2cu, 0xf6u, 0xffu, 0x7fu,
+    0x4cu, 0xffu, 0xffu, 0x7fu, 0x8cu, 0xf8u, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0xfcu, 0xf9u, 0xffu, 0x7fu,
+    0x00u, 0x84u, 0x04u, 0x80u, 0x0cu, 0xfau, 0xffu, 0x7fu, 0xb0u, 0xb0u, 0xa8u, 0x80u, 0x0cu, 0xfau, 0xffu, 0x7fu,
+    0x38u, 0xffu, 0xffu, 0x7fu, 0xf4u, 0xfcu, 0xffu, 0x7fu, 0x00u, 0x84u, 0x04u, 0x80u, 0x14u, 0xfdu, 0xffu, 0x7fu,
+    0xb0u, 0xb0u, 0xa8u, 0x80u, 0x2cu, 0xfdu, 0xffu, 0x7fu, 0x01u, 0x00u, 0x00u, 0x00u, 0xa0u, 0x20u, 0x00u, 0x10u,
+    0x80u, 0x08u, 0x00u, 0x28u, 0x6cu, 0x00u, 0x00u, 0x00u, 0x0cu, 0x12u, 0x00u, 0x28u, 0x54u, 0x00u, 0x00u, 0x00u,
+    0x84u, 0x08u, 0x00u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+    0x00u, 0x00u, 0x00u, 0x00u, 0xa9u, 0x00u, 0x00u, 0x10u, 0x81u, 0x00u, 0x00u, 0x10u,
+};
+#endif /* defined(CY_DEVICE_TVIIBH8M) */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/mtb_cat1cm0p.h b/boot/cypress/platforms/BSP/XMC7000/system/mtb_cat1cm0p.h
new file mode 100644
index 0000000..9ebe939
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/mtb_cat1cm0p.h
@@ -0,0 +1,35 @@
+/***************************************************************************//**
+* \file mtb_cat1cm0p.h
+* \version 1.0
+*
+* \brief
+* Provides a macro for BSP to indicate whether a prebuilt CM0P image is in use.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) (2022), Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if defined(COMPONENT_CAT1A)
+#if defined(COMPONENT_CM0P_BLESS) || defined(COMPONENT_CM0P_CRYPTO) || defined(COMPONENT_CM0P_SECURE) || defined(COMPONENT_CM0P_SLEEP)
+    #define CY_USING_PREBUILT_CM0P_IMAGE
+#endif /* defined(COMPONENT_CM0P_BLESS) || defined(COMPONENT_CM0P_CRYPTO) || defined(COMPONENT_CM0P_SECURE) || defined(COMPONENT_CM0P_SLEEP) */
+#elif defined(COMPONENT_CAT1C)
+#if defined(COMPONENT_XMC7x_CM0P_SLEEP) || defined(COMPONENT_XMC7xDUAL_CM0P_SLEEP)
+    #define CY_USING_PREBUILT_CM0P_IMAGE
+#endif /* defined(COMPONENT_XMC7x_CM0P_SLEEP) || defined(COMPONENT_XMC7xDUAL_CM0P_SLEEP) */
+#endif /* COMPONENT_CAT1A, COMPONENT_CAT1C */
\ No newline at end of file
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h
new file mode 100644
index 0000000..3540379
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h
@@ -0,0 +1,9 @@
+#ifndef __STARTUP_CAT1C_H__
+#define __STARTUP_CAT1C_H__
+
+#define FIXED_EXP_NR            (15u)
+#define VECTORTABLE_SIZE        (16u + FIXED_EXP_NR + 1u) /* +1 is for Stack pointer */
+#define VECTORTABLE_ALIGN       (128) /* alignment for 85 entries (32x4=128) is 2^7=128 bytes */
+
+
+#endif /* __STARTUP_CAT1C_H__ */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
new file mode 100644
index 0000000..8c67ae9
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
@@ -0,0 +1,555 @@
+/***************************************************************************//**
+* \file system_cat1c.h
+* \version 1.0
+*
+* \brief Device system header file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+#ifndef _SYSTEM_FACELIFT_H_
+#define _SYSTEM_FACELIFT_H_
+
+/**
+* \addtogroup group_system_config_cm7
+* \{
+* Provides device startup, system configuration, and linker script files.
+* The system startup provides the followings features:
+* - \ref group_system_config_device_memory_definition_cm7
+* - \ref group_system_config_device_initialization_cm7
+* - \ref group_system_config_heap_stack_config_cm7
+* - \ref group_system_config_default_handlers_cm7
+* - \ref group_system_config_device_vector_table_cm7
+* - \ref group_system_config_cm7_functions
+*
+* \section group_system_config_configuration_cm7 Configuration Considerations
+*
+* \subsection group_system_config_device_memory_definition_cm7 Device Memory Definition
+* Allocation of different types of memory such as the flash, RAM etc., for the CPU is defined by the linker scripts.
+*
+* \note - The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see warnings during the build process. To eliminate build
+* warnings in your project, you can simply comment out or remove the relevant
+* code in the linker file.
+*
+* \note - There is a common linker script for both CM7_0 and CM7_1 core.
+* By default it links for CM7_0 core. But if the application is built for CM7_1, then a linker option _CORE_cm7_1 is provided in build system.
+* For example, below piece of code is implemented in the build system.
+* \code
+* ifeq ($(TOOLCHAIN),IAR)
+* LDFLAGS += --config_def _CORE_cm7_1_=1
+* else ifeq ($(TOOLCHAIN),GCC_ARM)
+* LDFLAGS += -Wl,'--defsym=_CORE_cm7_1_=1'
+* endif
+* \endcode
+*
+* <b>ARM GCC</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
+* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
+* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM7() function call.
+* By default,
+* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
+* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
+*
+* Change the flash and RAM sizes by editing the macro values in the
+* linker files for both CPUs:
+* - 'xx_yy_cm0plus.ld', where 'xx_yy' is the device group:
+* \code
+* cm0_ram (rxw)  : ORIGIN = _base_SRAM_CM0P, LENGTH = _size_SRAM_CM0P
+* cm0_flash (rx) : ORIGIN = _base_CODE_FLASH_CM0P,LENGTH = _size_CODE_FLASH_CM0P
+* \endcode
+* - 'xx_yy_cm7.ld', where 'xx_yy' is the device group:
+* \code
+* ram (rxw) : ORIGIN = _base_SRAM, LENGTH = _size_SRAM
+* flash_cm0p (rx) : ORIGIN = _base_CODE_FLASH_CM0P, LENGTH = _size_CODE_FLASH_CM0P
+* flash (rx) : ORIGIN = _base_CODE_FLASH, LENGTH = _size_CODE_FLASH
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
+* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
+* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
+* same value as the flash LENGTH in 'xx_yy_cm0plus.ld') in the 'xx_yy_cm7.ld' file,
+* where 'xx_yy' is the device group.
+*
+* - Do this by editing the the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
+* in the 'system_xx.h', where 'xx' is the device family:\n
+* \code
+* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
+* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
+* \endcode
+* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
+*
+* <b>ARM Compiler</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'.
+*
+* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
+* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM7() function call.
+* By default,
+* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
+* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see the warnings during the build process:
+* L6314W (no section matches pattern) and/or L6329W
+* (pattern only matches removed unused sections). In your project, you can
+* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+* the linker. You can also comment out or remove the relevant code in the linker
+* file.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_yy_cm0plus.sct', where 'xx_yy' is the device group:
+* \code
+* #define SRAM_BASE_ADDRESS               0x28000000
+* #define CM0PLUS_SRAM_RESERVE            0x00020000
+* #define CODE_FLASH_BASE_ADDRESS         0x10000000
+* #define CM0PLUS_CODE_FLASH_RESERVE      0x00080000
+* \endcode
+* - 'xx_yy_cm7.sct', where 'xx_yy' is the device group:
+* \code
+* #define SRAM_BASE_ADDRESS               0x28000000 //SRAM START
+* #define CM7_0_SRAM_RESERVE              0x00060000 //cm7_0 sram size
+* #define BASE_SRAM_CM7_0                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
+* #define SIZE_SRAM_CM7_0                 CM7_0_SRAM_RESERVE
+* //In case of dual CM7-core MCU device device
+* #define SIZE_SRAM_CM7_1                 SRAM_TOTAL_SIZE - CM0PLUS_SRAM_RESERVE - CM7_0_SRAM_RESERVE
+* #define BASE_SRAM_CM7_1                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE
+*
+* #define CODE_FLASH_BASE_ADDRESS         0x10000000 //FLASH START
+* #define CM7_0_CODE_FLASH_RESERVE        0x00200000 //cm7_0 flash size
+* #define BASE_CODE_FLASH_CM7_0           CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
+* #define SIZE_CODE_FLASH_CM7_0           CM7_0_CODE_FLASH_RESERVE
+* //In case of dual CM7-core MCU device device
+* #define BASE_CODE_FLASH_CM7_1           CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE
+* #define SIZE_CODE_FLASH_CM7_1           CODE_FLASH_TOTAL_SIZE - CM0PLUS_CODE_FLASH_RESERVE - CM7_0_CODE_FLASH_RESERVE
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
+* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
+* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
+* same value as the flash LENGTH in 'xx_yy_cm0plus.sct') in the 'xx_yy_cm7.sct' file,
+* where 'xx_yy' is the device group.
+*
+* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
+* in the 'system_xx.h', where 'xx' is the device family:\n
+* \code
+* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
+* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
+* \endcode
+* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
+
+* <b>IAR</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
+* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'.
+* \note If the start of the Cortex-M7_0 or Cortex-M7_1 application image is changed, the value
+* of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM7() function call.
+* By default,
+* - the COMPONENT_XMC7x_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual-core MCU device (CM0+, CM7_0).
+* - the COMPONENT_XMC7xDUAL_CM0P_SLEEP prebuilt image is used for the CM0p core of the XMC dual CM7-core MCU device (CM0+, CM7_0 and CM7_1).
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_yy_cm0plus.icf', where 'xx_yy' is the device group:
+* \code
+* define symbol sram_base_address                 = 0x28000000;
+* define symbol cm0plus_sram_reserve              = 0x00020000; //cm0 sram size
+* define symbol code_flash_base_address           = 0x10000000;
+* define symbol cm0plus_code_flash_reserve        = 0x00080000; //cm0 flash size
+* \endcode
+* - 'xx_yy_cm7.icf', where 'xx_yy' is the device group:
+* \code
+* define symbol sram_base_address                 = 0x28000000;
+* define symbol cm7_0_sram_reserve                = 0x00060000;
+* define symbol _base_SRAM_CM7_0                  = sram_base_address + cm0plus_sram_reserve;
+* define symbol _size_SRAM_CM7_0                  = cm7_0_sram_reserve;
+* //In case of dual CM7-core MCU device device
+* define symbol _base_SRAM_CM7_1                  = sram_base_address + cm0plus_sram_reserve + cm7_0_sram_reserve;
+* define symbol _size_SRAM_CM7_1                  = sram_total_size - cm0plus_sram_reserve - cm7_0_sram_reserve;
+*
+* define symbol code_flash_base_address           = 0x10000000;
+* define symbol cm7_0_code_flash_reserve          = 0x00200000;
+* define symbol _base_CODE_FLASH_CM7_0            = code_flash_base_address + cm0plus_code_flash_reserve;
+* define symbol _size_CODE_FLASH_CM7_0            = cm7_0_code_flash_reserve;
+* //In case of dual CM7-core MCU device device
+* define symbol _base_CODE_FLASH_CM7_1            = code_flash_base_address + cm0plus_code_flash_reserve + cm7_0_code_flash_reserve;
+* define symbol _size_CODE_FLASH_CM7_1            = code_flash_total_size - cm0plus_code_flash_reserve - cm7_0_code_flash_reserve;
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR
+* macro to the ROM ORIGIN's value (0x10000000) + FLASH_CM0P_SIZE
+* value (0x80000, the size of a flash image of the Cortex-M0+ application should be the
+* same value as the flash LENGTH in 'xx_yy_cm0plus.icf') in the 'xx_yy_cm7.icf' file,
+* where 'xx_yy' is the device group.
+*
+* - Do this by editing the \ref CY_CORTEX_M7_0_APPL_ADDR or \ref CY_CORTEX_M7_1_APPL_ADDR value
+* in the 'system_xx.h', where 'xx' is the device family:\n
+* \code
+* #define CY_CORTEX_M7_0_APPL_ADDR BASE_CODE_FLASH_CM7_0
+* #define CY_CORTEX_M7_1_APPL_ADDR BASE_CODE_FLASH_CM7_1
+* \endcode
+* 'BASE_CODE_FLASH_CM7_0' and ''BASE_CODE_FLASH_CM7_1' macros are defined in the xmc7xxx_partition.h
+*
+* \subsection group_system_config_device_initialization_cm7 Device Initialization
+* After a power-on-reset (POR), the CM0+ starts boot-ROM directly from ROM and boot-ROM starts CM0+ startup.
+* The CM0+ startup starts CM0+ user application. The CM0+ user application enables CM7 cores and starts CM7 startup.
+* The startup code is the piece of code which is executed after every system reset.
+* It initializes the system components like, memory, FPU, interrupts, clock, etc. and calls application's main() function.
+* The startup code is always build as part of user application. There are two different startup codes for CM0+ and CM7 core.
+*
+* The CM0+ startup code implements the following functions to run the CM0+ application:
+*
+* 1. In the Reset Handler, it disables global interrupts
+* 3. Disables the SRAM ECC checking: CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Facelift parts with CM7 core,
+*     sets CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet.
+* 4. Calls SystemInit() function
+*   - Initializes and enables the SRAM memory for ECC
+*   - Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)
+*   - Sets the CM0+ IRQ0 and IRQ1 handlers from SROM vector table, sets the CM0+ IRQ0 and IRQ1priority,
+*      then enables these interrupts: the SROM APIs are executed by CM0+ core in interrupt context using IRQ0 and IRQ1.
+*      So, proper interrupt handler addresses and priorities need to be configured for IRQ0 and IRQ1
+*   - Unlocks and disable WDT (Watchdog timer)
+*   - Calls the SystemCoreClockUpdate()
+* 5. Executes main() application
+*
+* The CM7 startup code implement the following functions to run the CM7 user application:
+*
+* 1. In the Reset handler, it disables global interrupts
+* 2. Allows write access to Vector Table Offset Register and ITCM/DTCM configuration register
+* 3. Enables CM7 core ITCM and DTCM
+* 4. Enables the FPU if it is used
+* 5. Copies the vector table from ROM to RAM and updates the VTOR (Vector Table Offset Register)
+* 6. Enables the CM7 core instruction and data cache
+* 7. Calls SystemInit() function
+*    - Unlocks and disable WDT (Watchdog timer)
+*    - Calls the SystemCoreClockUpdate()
+* 6. Executes CM7 main() application
+*
+* \subsection group_system_config_heap_stack_config_cm7 Heap and Stack Configuration
+* By default, the stack size is set to 0x00001000 and the Heap size is allocated
+* dynamically to the whole available free memory up to stack memory.
+* The Stack grows from higher to lower address. The Stack top or start is assigned to end of SRAM address.
+* The Heap grows opposite of Stack. It grows from lower to higher address.
+* The Heap top starts from end of used data section till Stack end.
+*
+* \subsubsection group_system_config_heap_stack_config_gcc_cm7 ARM GCC
+* <b>Editing source code files</b>\n
+* The stack size is defined in the linker script files: 'xx_yy_zz.ld',
+* 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
+* 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
+* Change the stack size by modifying the following line:\n
+* \code STACK_SIZE = 0x1000; \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_mdk_cm7 ARM Compiler
+* <b>Editing source code files</b>\n
+* The stack size is defined in the linker script files: 'xx_yy_zz.sct',
+* 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
+* 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and 'xmc7100d_x4160_cm0plus.sct'.
+* Change the stack size by modifying the following line:\n
+* \code #define STACK_SIZE 0x1000 \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_iar_cm7 IAR
+* <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the linker script files: 'xx_yy_zz.icf',
+* where 'xx_ yy' is the device group, and 'zz' is the target CPU; for example,
+* 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and 'xmc7100d_x4160_cm0plus.icf'.
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code define symbol cm7_stack_reserve = 0x00001000; \endcode
+*
+* \subsection group_system_config_default_handlers_cm7 Default Interrupt Handlers Definition
+* The default interrupt handler functions are defined as weak functions to a dummy
+* handler in the startup file. The naming convention for the interrupt handler names
+* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
+* user code by defining the handler function using the same name. For example:
+* \code
+* void scb_0_interrupt_IRQHandler(void)
+*{
+*    ...
+*}
+* \endcode
+*
+* \subsection group_system_config_device_vector_table_cm7 Vectors Table Copy from Flash to RAM
+* This process uses memory sections defined in the linker script. The startup
+* code actually defines the contents of the vector table and performs the copy.
+*
+* \subsubsection group_system_config_device_vector_table_gcc_cm7 ARM GCC
+* The linker script file is 'xx_yy_zz.ld', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example, 'xmc7200d_x8384_cm7.ld', 'xmc7100d_x4160_cm7.ld', 'xmc7200d_x8384_cm0plus.ld' and 'xmc7100d_x4160_cm0plus.ld'.
+* It defines sections and locations in memory.\n
+*       Copy interrupt vectors from flash to RAM: \n
+*       From: \code LONG (__Vectors) \endcode
+*       To:   \code LONG (__ram_vectors_start__) \endcode
+*       Size: \code LONG (__Vectors_End - __Vectors) \endcode
+* The vector table address (and the vector table itself) are defined in the
+*  startup files (e.g. startup_cm0plus.S and startup_cm7.c).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_mdk_cm7 ARM Compiler
+* The linker script file is 'xx_yy_zz.sct', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example 'xmc7200d_x8384_cm7.sct', 'xmc7100d_x4160_cm7.sct', 'xmc7200d_x8384_cm0plus.sct' and
+* 'xmc7100d_x4160_cm0plus.sct'. The linker script specifies that the vector table
+* (RESET_RAM) shall be first in the RAM section.\n
+* RESET_RAM represents the vector table. It is defined in the startup
+* files  (e.g. startup_cm0plus.S and startup_cm7.c).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_iar_cm7 IAR
+* The linker script file is 'xx_yy_zz.icf', where 'xx_ yy' is the device group, and 'zz' is the target CPU;
+* for example, 'xmc7200d_x8384_cm7.icf','xmc7100d_x4160_cm7.icf','xmc7200d_x8384_cm0plus.icf' and '
+* 'xmc7100d_x4160_cm0plus.icf'.\n
+* The vector table address (and the vector table itself) are defined in the
+* startup files (e.g. startup_cm0plus.S and startup_cm7.c).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \section group_system_config_changelog_cm7 Changelog
+*   <table class="doxtable">
+*   <tr>
+*       <th>Version</th>
+*       <th>Changes</th>
+*       <th>Reason for Change</th>
+*   </tr>
+*   <tr>
+*       <td>1.0</td>
+*       <td>Initial version</td>
+*       <td></td>
+*   </tr>
+* </table>
+*
+* \defgroup group_system_config_macro_cm7 Macros
+* \{
+*   \defgroup group_system_config_system_macro_cm7 System Macros
+* \}
+* \defgroup group_system_config_functions_cm7 Functions
+* \{
+*   \defgroup group_system_config_cm7_functions Cortex-M7 Control
+* \}
+* \}
+*/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Include files
+*******************************************************************************/
+#include <stdint.h>
+#include "xmc7xxx_partition.h"
+
+/*******************************************************************************
+* Global preprocessor symbols/macros ('define')
+*******************************************************************************/
+#if ((defined(__GNUC__)        &&  (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+     (defined (__ICCARM__)     &&  (__CORE__ == __ARM6M__))  || \
+     (defined(__ARMCC_VERSION) &&  (__TARGET_ARCH_THUMB == 3)))
+    #define CY_SYSTEM_CPU_CM0P          1UL
+#else
+    #define CY_SYSTEM_CPU_CM0P          0UL
+#endif
+
+
+/*******************************************************************************
+*
+*                      START OF USER SETTINGS HERE
+*                      ===========================
+*
+*                 All lines with '<<<' can be set by user.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_system_config_system_macro_cm7
+* \{
+*/
+
+/*******************************************************************************
+*
+*                         END OF USER SETTINGS HERE
+*                         =========================
+*
+*******************************************************************************/
+
+/**  Start address of the Cortex-M7_0 application */
+#ifndef CY_CORTEX_M7_0_APPL_ADDR
+    #define CY_CORTEX_M7_0_APPL_ADDR        BASE_CODE_FLASH_CM7_0
+#endif
+
+/**  Start address of the Cortex-M7_1 application */
+#ifndef CY_CORTEX_M7_1_APPL_ADDR
+    #define CY_CORTEX_M7_1_APPL_ADDR        BASE_CODE_FLASH_CM7_1
+#endif
+
+/** The Cortex-M7 core is enabled: power on, clock on, no isolate, no reset and no retain. */
+#define CY_SYS_CM7_STATUS_ENABLED   (3U)
+/** The Cortex-M7 core is disabled: power off, clock off, isolate, reset and no retain. */
+#define CY_SYS_CM7_STATUS_DISABLED  (0U)
+/** The Cortex-M7 core is retained. power off, clock off, isolate, no reset and retain. */
+#define CY_SYS_CM7_STATUS_RETAINED  (2U)
+/** The Cortex-M7 core is in the Reset mode: clock off, no isolated, no retain and reset. */
+#define CY_SYS_CM7_STATUS_RESET     (1U)
+/** \} group_system_config_system_macro_cm7 */
+
+/** \cond */
+/** Cortex-M7 core 0 */
+#define CORE_CM7_0                  (0U)
+/** Cortex-M7 core 1 */
+#define CORE_CM7_1                  (1U)
+/** Error Selection */
+#define CORE_MAX                    (2U)
+
+extern uint32_t cy_delayFreqHz;
+extern uint32_t cy_delayFreqKhz;
+extern uint32_t  cy_delayFreqMhz;
+
+extern uint32_t SystemCoreClock;
+extern uint32_t cy_Hfclk0FreqHz;
+extern uint32_t cy_PeriClkFreqHz;
+extern uint32_t cy_AhbFreqHz;
+
+extern void SystemInit(void);
+extern void SystemIrqInit(void);
+extern void SystemCoreClockUpdate(void);
+
+/** \endcond */
+
+/**
+* \addtogroup group_system_config_cm7_functions
+* \{
+*/
+/*******************************************************************************
+* Function Name: Cy_SysGetCM7Status
+****************************************************************************//**
+*
+* Gets the Cortex-M7 core power mode.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \return \ref group_system_config_system_macro_cm7 \n
+* If 0: CY_SYS_CM7_STATUS_DISABLED \n
+*      1: CY_SYS_CM7_STATUS_RESET \n
+*      2: CY_SYS_CM7_STATUS_RETAINED \n
+*      3: CY_SYS_CM7_STATUS_ENABLED \n
+*
+******************************************************************************/
+extern uint32_t Cy_SysGetCM7Status(uint8_t core);
+/*******************************************************************************
+* Function Name: Cy_SysEnableCM7
+****************************************************************************//**
+*
+* Enables the Cortex-M7 core. The CPU is enabled once if it was in the disabled
+* or retained mode.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \param vectorTableOffset The offset of the vector table base address from
+* memory address 0x00000000. The offset should be multiple to 1024 bytes.
+*
+*******************************************************************************/
+extern void Cy_SysEnableCM7(uint8_t core, uint32_t vectorTableOffset);
+/*******************************************************************************
+* Function Name: Cy_SysDisableCM7
+****************************************************************************//**
+*
+* Disables the Cortex-M7 core.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \warning Do not call the function while the Cortex-M7 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+extern void Cy_SysDisableCM7(uint8_t core);
+/*******************************************************************************
+* Function Name: Cy_SysRetainCM7
+****************************************************************************//**
+*
+* Retains the Cortex-M7 core.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \warning Do not call the function while the Cortex-M7 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+extern void Cy_SysRetainCM7(uint8_t core);
+/*******************************************************************************
+* Function Name: Cy_SysResetCM7
+****************************************************************************//**
+*
+* Resets the Cortex-M7 core.
+*
+* \param core Core type (CM7_0 or CM7_1).
+*
+* \warning Do not call the function while the Cortex-M7 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M7 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+extern void Cy_SysResetCM7(uint8_t core);
+/** \} group_system_config_cm7_functions */
+
+
+/** \cond */
+
+extern void     Default_Handler (void);
+
+extern void     Cy_SystemInit(void);
+extern void     Cy_SystemInitFpuEnable(void);
+extern void     CyMain(void);
+
+#define Cy_SaveIRQ      Cy_SysLib_EnterCriticalSection
+#define Cy_RestoreIRQ   Cy_SysLib_ExitCriticalSection
+/** \endcond */
+
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_FACELIFT_H_ */
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h b/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
new file mode 100644
index 0000000..cd6530d
--- /dev/null
+++ b/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
@@ -0,0 +1,39 @@
+#if !defined(LAYOUT_CAT1C_H)
+#define LAYOUT_CAT1C_H
+
+#define STACK_SIZE                      0x1000
+#define RAMVECTORS_ALIGNMENT            128
+
+#define SRAM_START_RESERVE              0
+#define SRAM_PRIVATE_FOR_SROM           0x800 /* 2K Private SRAM for SROM (e.g. API processing). Reserved at the beginning */
+
+/* RAM */
+#define SRAM_BASE_ADDRESS               0x28000000  /* SRAM START */
+#define CM0PLUS_SRAM_RESERVE            0x20000     /* 128K (SRAM0/128KB) -> cm0plus */
+#define CM7_0_SRAM_RESERVE              0x80000 - CM0PLUS_SRAM_RESERVE /* (SRAM0/384KB) -> cm7_0 */
+
+/* FLASH */
+#define CODE_FLASH_BASE_ADDRESS         0x10000000  /* FLASH START */
+#define CM0PLUS_CODE_FLASH_RESERVE      0x80000     /* 512K CM0P FLASH SIZE */
+#define CM7_0_CODE_FLASH_RESERVE        0x200000    /* 2048K CM7_0 FLASH SIZE */
+
+/* SRAM reservations */
+#define BASE_SRAM_CM0P                  SRAM_BASE_ADDRESS + SRAM_START_RESERVE + SRAM_PRIVATE_FOR_SROM
+#define SIZE_SRAM_CM0P                  CM0PLUS_SRAM_RESERVE - SRAM_START_RESERVE - SRAM_PRIVATE_FOR_SROM
+#define BASE_SRAM_CM7_0                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE
+#define SIZE_SRAM_CM7_0                 CM7_0_SRAM_RESERVE
+#define BASE_SRAM_CM7_1                 SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE + CM7_0_SRAM_RESERVE
+
+/* Code flash reservations */
+#define BASE_CODE_FLASH_CM0P            CODE_FLASH_BASE_ADDRESS
+#define SIZE_CODE_FLASH_CM0P            CM0PLUS_CODE_FLASH_RESERVE
+#define BASE_CODE_FLASH_CM7_0           CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE
+#define SIZE_CODE_FLASH_CM7_0           CM7_0_CODE_FLASH_RESERVE
+#define BASE_CODE_FLASH_CM7_1           CODE_FLASH_BASE_ADDRESS + CM0PLUS_CODE_FLASH_RESERVE + CM7_0_CODE_FLASH_RESERVE
+
+
+
+#endif /* LAYOUT_CAT1C_H */
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/CYW20829.md b/boot/cypress/platforms/CYW20829.md
index 79694e9..c499a8a 100644
--- a/boot/cypress/platforms/CYW20829.md
+++ b/boot/cypress/platforms/CYW20829.md
@@ -62,7 +62,7 @@
 
 ### Default memory map
 
-The repository provides a set of predefined memory maps in JSON files. They are located in `platforms/cy_flash_pal/flash_CYW20829/flashmap`. One can use the predefined flash map or define your own using the predefined file as a template.
+The repository provides a set of predefined memory maps in JSON files. They are located in `platforms/memory/CYW20829/flashmap`. One can use the predefined flash map or define your own using the predefined file as a template.
 
 ### Encrypted image support
 
@@ -100,11 +100,11 @@
 
 Example build command for MCUBootApp:
 
-    make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
+    make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
 
 Example build command for BlinkyApp:
 
-    make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
+    make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
 
 ### Rollback protection Support
 
@@ -139,7 +139,7 @@
 
 In second case MCUBootApp is considered to be multi-image configuration with 2 images. 24 bits of 32 available eFuses are dedicated to image id 1, and 8 bits to image id 2. 
 
-This distribusion can be changed by user at initial provisioning stage and SHOULD NOT be changed at later reprovisioning stages.
+This distribution can be changed by user at initial provisioning stage and SHOULD NOT be changed at later reprovisioning stages.
 
 `"value": [2, 3]` filed sets corresponding value for image ids. Here `4` would be assigned to image id `1` and `5` to image id `2`.
 
@@ -155,16 +155,16 @@
 Examples of the build command with the rollback counter support for a `single image` and **OVERWRITE** mode:  
 for MCUBootApp:  
 
-    make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 APP_DEFAULT_POLICY=./policy/policy_secure.json BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json LCS=SECURE
+    make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 APP_DEFAULT_POLICY=./policy/policy_secure.json BUILDCFG=Debug FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json LCS=SECURE
 
 for BlinkyApp with TLVs containing rollback counter data:  
  - BOOT slot:  
 
-        make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json  
+    	make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json  
 
  - UPGRADE slot:  
 
-        make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
+    	make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json  
 
 #### NV-counter update
 
@@ -172,7 +172,7 @@
 
 The CYW20829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of Efuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `cysecuretools` under `targets/cyw20829/packets/apps`. The `reprovisioning` application is used for NV-counter updates.
 
-To enable the rollback counter feaure, one have to use a JSON flash map with the `"service_app"` section. Sample flash maps are located in `boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot`.
+To enable the rollback counter feaure, one have to use a JSON flash map with the `"service_app"` section. Sample flash maps are located in `boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot`.
 
 The service application is supplied as a precompiled binary executed from RAM by BootROM. User should program either `cyapp_reprovisioning_signed.hex` (located at `./MCUBootApp/out/CYW20829/Debug/cyapp_reprovisioning_signed.hex`) or similar binary `./packets/apps/reprovisioning/cyapp_reprovisioning_signed.bin` (with the `"address"` specified in the `"service_app"` section of JSON flash map). Some other data is required for BootROM to execute the service app - this data is prepared by MCUBootApp.
 
@@ -220,23 +220,23 @@
 
 for MCUBootApp:  
 
-    make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 APP_DEFAULT_POLICY=./policy/policy_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json LCS=SECURE USE_HW_ROLLBACK_PROT=1
+    make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 APP_DEFAULT_POLICY=./policy/policy_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json LCS=SECURE USE_HW_ROLLBACK_PROT=1
 
 for BlinkyApp with TLVs containing rollback counter data:
  - BOOT slot, IMG_ID=1:  
  
-        make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=1  
+   	make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=1  
  - UPGRADE slot, IMG_ID=1:  
  
-        make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=1
+    	make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=1
 
  - BOOT slot, IMG_ID=2:  
  
-        make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=2  
+    	make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=2  
     
  - UPGRADE slot, IMG_ID=2:  
     
-        make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=2
+    	make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=2
     
 **Attention!** Don't omit `clean_boot` and `clean_upgrade` to avoid any issues!   
 
diff --git a/boot/cypress/platforms/CYW20829.mk b/boot/cypress/platforms/CYW20829.mk
index d72f804..23db7cf 100644
--- a/boot/cypress/platforms/CYW20829.mk
+++ b/boot/cypress/platforms/CYW20829.mk
@@ -36,7 +36,7 @@
 # MCU device selection, based on target device.
 # Default chips are used for supported platforms
 # This can be redefined in case of other chip usage
-DEVICE ?= CYW20829B0LKML
+DEVICE ?= CYW20829A0LKML
 # If PSVP build is required
 ifeq ($(CYW20829_PSVP), 1)
 SERVICE_APP_PLATFORM_SUFFIX := _psvp
@@ -58,6 +58,10 @@
 # Default upgrade method
 PLATFORM_DEFAULT_USE_OVERWRITE ?= 0
 
+# Minimum erase size of underlying memory hardware
+PLATFORM_MEMORY_ALIGN := 0x1000
+PLATFORM_MAX_TRAILER_PAGE_SIZE := 0x1000
+
 # Device flash start
 FLASH_START := 0x60000000
 FLASH_XIP_START := 0x08000000
@@ -71,12 +75,6 @@
 
 ifeq ($(APP_NAME), MCUBootApp)
 
-PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/platforms/cy_flash_pal
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/flash_qspi
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/include
-PLATFORM_SOURCES_FLASH := $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/*.c)
-PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/*.c)
-
 # Platform dependend utils files
 PLATFORM_APP_SOURCES := $(PRJ_DIR)/platforms/utils/$(FAMILY)/cyw_platform_utils.c
 PLATFORM_INCLUDE_DIRS_UTILS := $(PRJ_DIR)/platforms/utils/$(FAMILY)
@@ -121,6 +119,8 @@
 USE_CUSTOM_MEMORY_MAP ?= 1
 
 PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE ?= 4096U
+
+# Default memory single chunk size
 PLATFORM_CHUNK_SIZE := 4096U
 ###############################################################################
 
@@ -189,11 +189,6 @@
 
 PLATFORM_DEFINES_APP += -DUSER_APP_START_OFF=0x20000
 
-PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/platforms/cy_flash_pal
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/flash_qspi
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/include
-PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/*.c)
-
 PLATFORM_DEFAULT_IMG_VER_ARG ?= 1.0.0
 
 SIGN_IMG_ID = $(shell expr $(IMG_ID) - 1)
@@ -212,7 +207,6 @@
 	$(shell $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PRJ_DIR) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH))
 
 	$(info SIGN_ARGS <-> $(SIGN_ARGS))
-
 	$(shell cysecuretools -q -t cyw20829 -p $(APP_DEFAULT_POLICY) sign-image $(SIGN_ARGS))
 
 	$(GCC_PATH)/bin/arm-none-eabi-objcopy --change-address=$(HEADER_OFFSET) -I binary -O ihex $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).bin $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex
@@ -235,15 +229,13 @@
 PLATFORM_SYSTEM_FILE_NAME := ns_system_$(PLATFORM_SUFFIX).c
 PLATFORM_SOURCES_PDL_STARTUP := ns_start_$(PLATFORM_SUFFIX).c
 
-PLATFORM_SOURCES_RETARGET_IO := $(wildcard $(PRJ_DIR)/libs/retarget-io/*.c)
-
 PLATFORM_SOURCES_HAL := $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/pin_packages/cyhal_cyw20829_56_qfn.c
 PLATFORM_SOURCES_HAL += $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/triggers/cyhal_triggers_cyw20829.c
 PLATFORM_SOURCES_HAL += $(wildcard $(PRJ_DIR)/libs/mtb-hal-cat1/source/*.c)
 
 PLATFORM_INCLUDE_DIRS_PDL_STARTUP := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system
 
-PLATFORM_INCLUDE_DIRS_RETARGET_IO := $(PRJ_DIR)/libs/retarget-io
+PLATFORM_INCLUDE_RETARGET_IO := $(PRJ_DIR)/libs/retarget-io
 
 PLATFORM_INCLUDE_DIRS_HAL := $(PRJ_DIR)/libs/mtb-hal-cat1/include
 PLATFORM_INCLUDE_DIRS_HAL += $(PRJ_DIR)/libs/mtb-hal-cat1/include_pvt
diff --git a/boot/cypress/platforms/PSOC6.md b/boot/cypress/platforms/PSOC6.md
index 22798c7..720683d 100644
--- a/boot/cypress/platforms/PSOC6.md
+++ b/boot/cypress/platforms/PSOC6.md
@@ -4,10 +4,11 @@
 
 ### Default memory map
 
-This repository provides a set of predefined memory maps in JSON files. They are located in `platforms/cy_flash_pal/flash_psoc6/flashmap`. One can use the predefined flash map or define its own using the predefined file as a template.
+This repository provides a set of predefined memory maps in JSON files. They are located in `platforms/memory/PSOC6/flashmap`. One can use the predefined flash map or define its own using the predefined file as a template.
 
 ### JSON flash map
 As absolute addresses are used in JSON flash maps, the placement of flash area in internal or external memory is derived from its address. For instance:
+
 ```
         "application_1": {
             "address": {
@@ -34,6 +35,7 @@
 Some Flash ICs have large erase block. For SEMPER™ Secure NOR Flash it is 256 kilobytes, so placing each image trailer in a separate erase block seems a waste.
 
 Specific technique is needed to place all trailers of the shared secondary slot in the single erase block. Since the whole erase block with trailer is occasionally cleared by MCUBoot, image padding is required to place trailers at different addresses and to avoid unintended erasing of image bytes.
+
 ```
               /|           |-----------|           |
              / |           |           |           |
@@ -75,7 +77,7 @@
 
 An example of the command:
 
-    make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json ENC_IMG=1
+    make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json ENC_IMG=1
 
 NOTE: Debug configuration of MCUBootApp with Multi-image encrypted upgrades in external flash (built with flags `BUILDCFG=Debug` `MCUBOOT_IMG_NUMBER=2 USE_EXTERNAL_FLASH=1 ENC_IMG=1`) is set to use optimization level `-O2 -g3` to fit into `0x18000` allocated for `MCUBootApp`.
 
diff --git a/boot/cypress/platforms/PSOC6.mk b/boot/cypress/platforms/PSOC6.mk
index 991ec3f..1362b04 100644
--- a/boot/cypress/platforms/PSOC6.mk
+++ b/boot/cypress/platforms/PSOC6.mk
@@ -81,8 +81,8 @@
 
 #UART default config
 ifeq ($(PLATFORM), PSOC_062_512K)
-UART_TX_DEFAULT ?= P10_1
-UART_RX_DEFAULT ?= P10_0
+UART_TX_DEFAULT ?= P5_1
+UART_RX_DEFAULT ?= P5_0
 else ifeq ($(PLATFORM), PSOC_061_512K)
 # INFO: Since 061 platform development 
 # is happening on processor module (PM),
@@ -94,17 +94,33 @@
 # Definitions for BlinkyApp
 UART_TX_DEFAULT ?= P10_1
 UART_RX_DEFAULT ?= P10_0
+
 else
 UART_TX_DEFAULT ?= P5_1
 UART_RX_DEFAULT ?= P5_0
 endif
 
+DEFINES += CY_DEBUG_UART_TX=$(UART_TX_DEFAULT)
+DEFINES += CY_DEBUG_UART_RX=$(UART_RX_DEFAULT)
+DEFINES += CYBSP_DEBUG_UART_TX=$(UART_TX_DEFAULT)
+DEFINES += CYBSP_DEBUG_UART_RX=$(UART_RX_DEFAULT)
+
 # Add device name to defines
 DEFINES += $(DEVICE)
+DEFINES += CY_USING_HAL
+DEFINES += CORE_NAME_$(CORE)_0=1
+DEFINES += COMPONENT_CAT1 COMPONENT_CAT1A COMPONENT_$(CORE)
+
+# Minimum erase size of underlying memory hardware
+PLATFORM_MEMORY_ALIGN := 0x200
+PLATFORM_MAX_TRAILER_PAGE_SIZE := 0x200
 
 # Default upgrade method
 PLATFORM_DEFAULT_USE_OVERWRITE ?= 0
 
+# Default chung size
+PLATFORM_CHUNK_SIZE := 512U
+
 ###############################################################################
 # Application specific libraries
 ###############################################################################
@@ -121,23 +137,8 @@
 CORE_SUFFIX = m4
 endif
 
-# Add retartget IO implementation using pdl
-PLATFORM_SOURCES_RETARGET_IO_PDL := $(wildcard $(THIS_APP_PATH)/retarget_io_pdl/*.c)
-
-# Collect dirrectories containing headers for PLATFORM
-PLATFORM_INCLUDE_RETARGET_IO_PDL := $(THIS_APP_PATH)/retarget_io_pdl
-
-# PSOC6HAL source files
-PLATFORM_SOURCES_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_crypto_common.c
-PLATFORM_SOURCES_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_hwmgr.c
-
-# needed for Crypto HW Acceleration and headers inclusion, do not use for peripherals
-# peripherals should be accessed
-PLATFORM_INCLUDE_DIRS_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include
-PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include
-PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include_pvt
-PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages
-
+PLATFORM_APP_SOURCES += $(PRJ_DIR)/platforms/utils/$(FAMILY)/cyw_platform_utils.c
+PLATFORM_INCLUDE_DIRS_UTILS := $(PRJ_DIR)/platforms/utils/$(FAMILY)
 ###############################################################################
 # Application dependent definitions
 # MCUBootApp default settings
@@ -145,33 +146,10 @@
 USE_CRYPTO_HW ?= 1
 ###############################################################################
 
-PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/platforms/cy_flash_pal
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/include
-PLATFORM_SOURCES_FLASH := $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/*.c)
-
-ifneq ($(USE_EXTERNAL_FLASH), 1)
-PLATFORM_SOURCES_FLASH := $(filter-out $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c, $(PLATFORM_SOURCES_FLASH))
-endif
-
-ifeq ($(USE_EXTERNAL_FLASH), 1)
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/flash_qspi
-PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/flash_qspi/*.c)
-ifeq ($(BUILDCFG), Debug)
-# Include files with statically defined SMIF configuration to enable
-# OpenOCD debugging of external memory
-PLATFORM_SOURCES_FLASH += cy_serial_flash_prog.c
-PLATFORM_SOURCES_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg
-endif
-endif
-
-# Platform dependend utils files
-PLATFORM_APP_SOURCES := $(PRJ_DIR)/platforms/utils/$(FAMILY)/cyw_platform_utils.c
 ifeq ($(PLATFORM), $(filter $(PLATFORM), PSOC_061_2M PSOC_061_1M PSOC_061_512K))
 # FIXME: not needed for real PSoC 61!
 PLATFORM_APP_SOURCES += $(PRJ_DIR)/platforms/utils/$(FAMILY)/psoc6_02_cm0p_sleep.c
 endif
-PLATFORM_INCLUDE_DIRS_UTILS := $(PRJ_DIR)/platforms/utils/$(FAMILY)
 
 # Post build job to execute for platform
 post_build: $(OUT_CFG)/$(APP_NAME)_unsigned.hex
@@ -240,12 +218,14 @@
 # from external memory in XIP mode.
 PLATFORM_DEFAULT_PRIMARY_IMG_START ?= $(PLATFORM_DEFAULT_USER_APP_START)
 
-PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/platforms/cy_flash_pal
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/include
+#PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/platforms/memory
+#PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/memory/$(FAMILY)
+#PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/memory/flash_map_backend
+#PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/memory/$(FAMILY)/include
 
 ifeq ($(USE_EXTERNAL_FLASH), 1)
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/flash_qspi
-PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/flash_qspi/*.c)
+#PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/memory/$(FAMILY)/flash_qspi
+#PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/platforms/memory/$(FAMILY)/flash_qspi/*.c)
 endif
 
 # We still need this for MCUBoot apps signing
@@ -330,11 +310,9 @@
 $(info PLATFORM_INCLUDE_DIRS_HAL_MCUB --> $(PLATFORM_INCLUDE_DIRS_HAL_MCUB))
 $(info PLATFORM_INCLUDE_DIRS_PDL_STARTUP --> $(PLATFORM_INCLUDE_DIRS_PDL_STARTUP))
 $(info PLATFORM_INCLUDE_DIRS_UTILS --> $(PLATFORM_INCLUDE_DIRS_UTILS))
-$(info PLATFORM_INCLUDE_RETARGET_IO_PDL --> $(PLATFORM_INCLUDE_RETARGET_IO_PDL))
 $(info PLATFORM_SIGN_ARGS --> $(PLATFORM_SIGN_ARGS))
 $(info PLATFORM_SOURCES_FLASH <-> $(PLATFORM_SOURCES_FLASH))
 $(info PLATFORM_SOURCES_HAL_MCUB --> $(PLATFORM_SOURCES_HAL_MCUB))
-$(info PLATFORM_SOURCES_RETARGET_IO_PDL --> $(PLATFORM_SOURCES_RETARGET_IO_PDL))
 $(info PLATFORM_STARTUP_FILE --> $(PLATFORM_STARTUP_FILE))
 $(info PLATFORM_SUFFIX <-> $(PLATFORM_SUFFIX))
 $(info PLATFORM_SYSTEM_FILE_NAME --> $(PLATFORM_SYSTEM_FILE_NAME))
diff --git a/boot/cypress/platforms/XMC7000.md b/boot/cypress/platforms/XMC7000.md
new file mode 100644
index 0000000..e52bffd
--- /dev/null
+++ b/boot/cypress/platforms/XMC7000.md
@@ -0,0 +1,65 @@
+## XMC7000 boot configuration description
+MCUBoot application supports `overwrite` and `swap` upgrade modes for XMC7200 and XMC7100 platforms.
+
+Following commands can be used as an example to build a project
+- Overwrite mode
+
+    make clean app APP_NAME=MCUBootApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM0P APP_CORE=CM7 APP_CORE_ID=0
+
+    make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1
+
+    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 CORE_ID=0 IMG_TYPE=UPGRADE IMG_ID=1
+
+- Swap mode
+
+    make clean app APP_NAME=MCUBootApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_swap_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM0P APP_CORE=CM7 APP_CORE_ID=0
+
+    make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_swap_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1
+
+    make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_swap_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 CORE_ID=0 IMG_TYPE=UPGRADE IMG_ID=1
+
+Build parameters description:
+`
+
+## XMC7000 Secure boot configuration description
+XMC7000 internal flash boot module can be used in secure configuration.
+A complete description and instructions for configuring a secure boot can be found in reference manual `AN234802`.
+
+MCUBoot makefile supports secure image build configuration for XMC7200 and XMC7100 devices.
+To prepare a secure MCUBoot image, the user must configure the public key and specify the appropriate parameters for the TOC2 structure in the `cy_si_config.c`, `cy_si_key.c` files and execute the make command with the additional variables `USE_SECURE_MODE=1`, `SECURE_MODE_KEY_NAME=<name>`.
+
+- Step to generate custom RSA2048 keys:
+    cysecuretools -t xmc7200 create-key --key-type RSA2048 -o ./keys/cypress-test-rsa2k.pem ./keys/cypress-test-rsa2k.pub --format PEM
+
+- Step to generate `cy_si_key.c` file:
+    cysecuretools convert-key -k ./keys/cypress-test-rsa2k.pub -o ./platforms/utils/XMC7000/cy_si_key.c --fmt secure_boot --endian little
+
+Previous two steps can be executed with single Makefile command.
+    make gen_secure_cfgs PLATFORM=XMC7200 SECURE_MODE_KEY_TYPE=RSA2048 KEY_NAME=cypress-test-rsa2k
+
+- Step to run MCUBootApp build with secure flash boot config
+    make clean app APP_NAME=MCUBootApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM0P APP_CORE=CM7 APP_CORE_ID=0 USE_SECURE_MODE=1 SECURE_MODE_KEY_NAME=cypress-test-rsa2k
+
+- Example how to configure openocd script:
+
+    set QSPI_FLASHLOADER platforms/BSP/XMC7000/CAT1C_SMIF.FLM
+    source [find interface/kitprog3.cfg]
+    set ENABLE_ACQUIRE 0
+    set ACQUIRE_TIMEOUT 2000
+
+    transport select swd
+    source [find target/cat1c.cfg]
+    cat1c sflash_restrictions 1
+
+    targets
+
+    init; reset init;
+
+    flash erase_address     0x17007C00              0x00000200
+    flash erase_address     0x17006400              0x00000C00
+
+    program `./MCUBootApp/out/XMC7200/Debug/MCUBootApp.hex`
+
+    resume;
+    reset;
+    shutdown
diff --git a/boot/cypress/platforms/XMC7000.mk b/boot/cypress/platforms/XMC7000.mk
new file mode 100644
index 0000000..de101e0
--- /dev/null
+++ b/boot/cypress/platforms/XMC7000.mk
@@ -0,0 +1,293 @@
+################################################################################
+# \file XMC7000.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe supported boards and platforms for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+include host.mk
+
+# PDL category suffix to resolve common path in pdl
+PDL_CAT_SUFFIX := 1C
+CRYPTO_ACC_TYPE := MXCRYPTO
+
+# MCU device selection, based on target device.
+# Default chips are used for supported platforms
+# This can be redefined in case of other chip usage
+ifeq ($(PLATFORM), XMC7200)
+# base kit KIT_XMC72_EVK
+DEVICE ?= XMC7200D_E272K8384
+else ifeq ($(PLATFORM), XMC7100)
+DEVICE ?= XMC7100D_E272K4160
+endif
+
+# Led default config
+ifeq ($(PLATFORM), XMC7200)
+LED_PORT_DEFAULT ?= GPIO_PRT16
+LED_PIN_DEFAULT ?= 1U
+else ifeq ($(PLATFORM), XMC7100)
+LED_PORT_DEFAULT ?= GPIO_PRT16
+LED_PIN_DEFAULT ?= 1U
+endif
+
+#UART default config
+ifeq ($(PLATFORM), XMC7200)
+UART_TX_DEFAULT ?= P13_1
+UART_RX_DEFAULT ?= P13_0
+else ifeq ($(PLATFORM), XMC7100)
+UART_TX_DEFAULT ?= P13_1
+UART_RX_DEFAULT ?= P13_0
+endif
+
+# Add device name to defines
+DEFINES += $(DEVICE)
+
+# Default upgrade method
+PLATFORM_DEFAULT_USE_OVERWRITE ?= 0
+
+PLATFORM_CHUNK_SIZE := 0x200
+
+# Minimum erase size of underlying memory hardware
+PLATFORM_MEMORY_ALIGN := 0x200
+PLATFORM_MAX_TRAILER_PAGE_SIZE := 0x8000
+
+###############################################################################
+# Application specific libraries
+###############################################################################
+# MCUBootApp
+###############################################################################
+THIS_APP_PATH = $(PRJ_DIR)/libs
+
+APP_CORE ?= CM7
+CORE ?= CM0P
+CORE_ID ?= 0
+APP_CORE_ID ?= 0
+
+ifeq ($(APP_NAME), MCUBootApp)
+
+ifeq ($(CORE), CM0P)
+CORE_SUFFIX = m0plus
+else
+CORE_SUFFIX = m7
+PLATFORM_SOURCES_CM0P_SLEEP := $(PRJ_DIR)/platforms/BSP/XMC7000/system/COMPONENT_XMC7x_CM0P_SLEEP/xmc7200_cm0p_sleep.c
+endif
+
+# PSOC6HAL source files
+# PLATFORM_SOURCES_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_crypto_common.c
+# PLATFORM_SOURCES_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_hwmgr.c
+
+# needed for Crypto HW Acceleration and headers inclusion, do not use for peripherals
+# peripherals should be accessed
+# PLATFORM_INCLUDE_DIRS_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include
+# PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include
+# PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include_pvt
+# PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/pin_packages
+
+###############################################################################
+# Application dependent definitions
+# MCUBootApp default settings
+
+USE_CRYPTO_HW ?= 0
+###############################################################################
+
+# Platform dependend utils files
+PLATFORM_APP_SOURCES := $(PRJ_DIR)/platforms/utils/$(FAMILY)/cyw_platform_utils.c
+PLATFORM_APP_SOURCES += $(PLATFORM_SOURCES_CM0P_SLEEP)
+PLATFORM_INCLUDE_DIRS_UTILS := $(PRJ_DIR)/platforms/utils/$(FAMILY)
+
+ifeq ($(USE_SECURE_MODE), 1)
+PLATFORM_APP_SOURCES += $(PRJ_DIR)/platforms/utils/$(FAMILY)/cy_si_config.c
+PLATFORM_APP_SOURCES += $(PRJ_DIR)/platforms/utils/$(FAMILY)/cy_si_key.c
+endif
+
+# Post build job to execute for platform
+post_build: $(OUT_CFG)/$(APP_NAME)_unsigned.hex
+ifeq ($(POST_BUILD_ENABLE), 1)
+	$(info [POST BUILD] - Executing post build script for $(APP_NAME))
+
+ifeq ($(USE_SECURE_MODE), 1)
+	cysecuretools -t $(PLATFORM) sign-cysaf -i $(OUT_CFG)/$(APP_NAME).elf --key-path ./keys/$(SECURE_MODE_KEY_NAME).pem --output $(OUT_CFG)/$(APP_NAME)_secure.elf; \
+	$(GCC_PATH)/bin/arm-none-eabi-objcopy -O ihex $(OUT_APP)/$(APP_NAME)_secure.elf $(OUT_APP)/$(APP_NAME)_secure.hex; \
+	$(GCC_PATH)/bin/arm-none-eabi-objcopy $(OUT_APP)/$(APP_NAME)_secure.elf -S -O binary $(OUT_APP)/$(APP_NAME)_secure.bin --remove-section .cy_sflash_user_data --remove-section .cy_toc_part2; \
+	mv -f $(OUT_APP)/$(APP_NAME)_secure.elf $(OUT_APP)/$(APP_NAME).elf; \
+	mv -f $(OUT_APP)/$(APP_NAME)_secure.hex $(OUT_APP)/$(APP_NAME).hex; \
+	mv -f $(OUT_APP)/$(APP_NAME)_secure.bin $(OUT_APP)/$(APP_NAME).bin
+
+else
+	cp -f $(OUT_CFG)/$(APP_NAME)_unsigned.hex $(OUT_CFG)/$(APP_NAME).hex
+endif
+	$(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME).hex > $(OUT_CFG)/$(APP_NAME).objdump
+
+else
+	$(info Post build is disabled by POST_BUILD_ENABLE parameter)
+endif # POST_BUILD_ENABLE
+endif ## MCUBootApp
+
+###############################################################################
+# BlinkyApp
+###############################################################################
+ifeq ($(APP_NAME), BlinkyApp)
+
+CORE := $(APP_CORE)
+LDFLAGS_PLATFORM := -Wl,--defsym=_CORE_$(CORE)_$(CORE_ID)_=1
+ifeq ($(CORE), CM0P)
+CORE_SUFFIX = m0plus
+else
+CORE_SUFFIX = m7
+endif
+
+PLATFORM_DEFAULT_ERASED_VALUE := 0xff
+
+# Define start of application, RAM start and size, slot size
+ifeq ($(FAMILY), XMC7000)
+	PLATFORM_DEFAULT_RAM_START ?= 0x28050000
+	PLATFORM_DEFAULT_RAM_SIZE  ?= 0x30000
+endif
+# Default start address of application (boot)
+PLATFORM_USER_APP_START ?= $(PRIMARY_IMG_START)
+# For PSOC6 platform PRIMARY_IMG_START start is the same as USER_APP_START
+# This parameter can be different in cases when code is resided in
+# flash mapped to one address range, but executed using different bus
+# for access with another address range. For example, execution of code
+# from external memory in XIP mode.
+PLATFORM_DEFAULT_PRIMARY_IMG_START ?= $(PLATFORM_DEFAULT_USER_APP_START)
+
+# We still need this for MCUBoot apps signing
+IMGTOOL_PATH ?=	../../scripts/imgtool.py
+
+PLATFORM_DEFAULT_IMG_VER_ARG ?= 1.0.0
+
+PLATFORM_SIGN_ARGS := --header-size 1024 --align 8
+
+# Set parameters needed for signing
+ifeq ($(IMG_TYPE), UPGRADE)
+	# Use encryption and random initial vector for image
+	ifeq ($(ENC_IMG), 1)
+		PLATFORM_SIGN_ARGS += --encrypt ../../$(ENC_KEY_FILE).pem
+		PLATFORM_SIGN_ARGS += --use-random-iv
+	endif
+endif
+
+# Post build action to execute after main build job
+post_build: $(OUT_CFG)/$(APP_NAME).bin
+ifeq ($(POST_BUILD_ENABLE), 1)
+	$(info [POST BUILD] - Executing post build script for $(APP_NAME))
+	$(shell mv -f $(OUT_CFG)/$(APP_NAME).bin $(OUT_CFG)/$(APP_NAME)_unsigned.bin)
+	cysecuretools -t $(PLATFORM) sign-image $(SIGN_ARGS) -S $(SLOT_SIZE) -R $(ERASED_VALUE) $(UPGRADE_TYPE) --key-path keys/$(SIGN_KEY_FILE).pem --image $(OUT_CFG)/$(APP_NAME)_unsigned.bin --output $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex --hex-addr=$(HEADER_OFFSET)
+	$(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex > $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).objdump
+else
+	$(info Post build is disabled by POST_BUILD_ENABLE parameter)
+endif # POST_BUILD_ENABLE
+endif ## BlinkyApp
+
+
+###############################################################################
+# Toolchain
+###############################################################################
+# Define build flags specific to a certain platform
+CFLAGS_PLATFORM := -mcpu=cortex-$(CORE_SUFFIX) -mfloat-abi=soft -fno-stack-protector -fstrict-aliasing
+
+###############################################################################
+# Common libraries
+###############################################################################
+ifeq ($(CORE), CM0P)
+PLATFORM_SYSTEM_FILE_NAME := system_cm0plus.c
+PLATFORM_STARTUP_FILE := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/startup_cm0plus.S
+else ifeq ($(CORE), CM7)
+PLATFORM_SYSTEM_FILE_NAME := system_cm7.c
+PLATFORM_STARTUP_FILE := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/startup_cm7.S
+endif
+
+PLATFORM_INCLUDE_DIRS_PDL_STARTUP := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system
+PLATFORM_INCLUDE_DIRS_PDL_STARTUP += $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)
+
+PLATFORM_DEFINES_LIBS := -DCY_USING_HAL
+PLATFORM_DEFINES_LIBS += -DCOMPONENT_$(CORE)
+PLATFORM_DEFINES_LIBS += -DCOMPONENT_$(CORE)_$(CORE_ID)
+PLATFORM_DEFINES_LIBS += -DCORE_NAME_$(CORE)_$(CORE_ID)=1
+PLATFORM_DEFINES_LIBS += -DCOMPONENT_CAT1
+PLATFORM_DEFINES_LIBS += -DCOMPONENT_CAT1C
+PLATFORM_DEFINES_LIBS += -DCOMPONENT_CAT1C8M
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### PSOC6.mk ####)
+$(info APP_CORE <-- $(APP_CORE))
+$(info APP_NAME <-- $(APP_NAME))
+$(info BOOT_RECORD <-- $(BOOT_RECORD))
+$(info BUILDCFG <-- $(BUILDCFG))
+$(info CFLAGS_PLATFORM --> $(CFLAGS_PLATFORM))
+$(info COMPILER <-- $(COMPILER))
+$(info CORE <-> $(CORE))
+$(info CORE_SUFFIX <-- $(CORE_SUFFIX))
+$(info DEFINES --> $(DEFINES))
+$(info DEVICE <-> $(DEVICE))
+$(info ENC_IMG <-- $(ENC_IMG))
+$(info ENC_KEY_FILE <-- $(ENC_KEY_FILE))
+$(info ERASED_VALUE <-- $(ERASED_VALUE))
+$(info FAMILY <-- $(FAMILY))
+$(info GCC_PATH <-- $(GCC_PATH))
+$(info HEADER_OFFSET <-- $(HEADER_OFFSET))
+$(info IMGTOOL_PATH <-> $(IMGTOOL_PATH))
+$(info IMG_TYPE <-- $(IMG_TYPE))
+$(info LED_PIN_DEFAULT --> $(LED_PIN_DEFAULT))
+$(info LED_PORT_DEFAULT --> $(LED_PORT_DEFAULT))
+$(info OUT_CFG <-- $(OUT_CFG))
+$(info PDL_CAT_SUFFIX <-> $(PDL_CAT_SUFFIX))
+$(info PLATFORM <-- $(PLATFORM))
+$(info PLATFORM_APP_SOURCES --> $(PLATFORM_APP_SOURCES))
+$(info PLATFORM_DEFAULT_ERASED_VALUE --> $(PLATFORM_DEFAULT_ERASED_VALUE))
+$(info PLATFORM_DEFAULT_IMG_VER_ARG --> $(PLATFORM_DEFAULT_IMG_VER_ARG))
+$(info PLATFORM_DEFAULT_PRIMARY_IMG_START --> $(PLATFORM_DEFAULT_PRIMARY_IMG_START))
+$(info PLATFORM_DEFAULT_RAM_SIZE --> $(PLATFORM_DEFAULT_RAM_SIZE))
+$(info PLATFORM_DEFAULT_RAM_START --> $(PLATFORM_DEFAULT_RAM_START))
+$(info PLATFORM_DEFAULT_USER_APP_START <-- $(PLATFORM_DEFAULT_USER_APP_START))
+$(info PLATFORM_DEFAULT_USE_OVERWRITE --> $(PLATFORM_DEFAULT_USE_OVERWRITE))
+$(info PLATFORM_INCLUDE_DIRS_FLASH --> $(PLATFORM_INCLUDE_DIRS_FLASH))
+$(info PLATFORM_INCLUDE_DIRS_HAL_MCUB --> $(PLATFORM_INCLUDE_DIRS_HAL_MCUB))
+$(info PLATFORM_INCLUDE_DIRS_PDL_STARTUP --> $(PLATFORM_INCLUDE_DIRS_PDL_STARTUP))
+$(info PLATFORM_INCLUDE_DIRS_UTILS --> $(PLATFORM_INCLUDE_DIRS_UTILS))
+$(info PLATFORM_INCLUDE_RETARGET_IO_PDL --> $(PLATFORM_INCLUDE_RETARGET_IO_PDL))
+$(info PLATFORM_SIGN_ARGS --> $(PLATFORM_SIGN_ARGS))
+$(info PLATFORM_SOURCES_FLASH <-> $(PLATFORM_SOURCES_FLASH))
+$(info PLATFORM_SOURCES_HAL_MCUB --> $(PLATFORM_SOURCES_HAL_MCUB))
+$(info PLATFORM_SOURCES_RETARGET_IO_PDL --> $(PLATFORM_SOURCES_RETARGET_IO_PDL))
+$(info PLATFORM_STARTUP_FILE --> $(PLATFORM_STARTUP_FILE))
+$(info PLATFORM_SUFFIX <-> $(PLATFORM_SUFFIX))
+$(info PLATFORM_SYSTEM_FILE_NAME --> $(PLATFORM_SYSTEM_FILE_NAME))
+$(info PLATFORM_USER_APP_START --> $(PLATFORM_USER_APP_START))
+$(info POST_BUILD_ENABLE <-- $(POST_BUILD_ENABLE))
+$(info PRIMARY_IMG_START <-- $(PRIMARY_IMG_START))
+$(info PRJ_DIR <-- $(PRJ_DIR))
+$(info PYTHON_PATH <-- $(PYTHON_PATH))
+$(info SIGN_ARGS <-- $(SIGN_ARGS))
+$(info SIGN_KEY_FILE <-- $(SIGN_KEY_FILE))
+$(info SLOT_SIZE <-- $(SLOT_SIZE))
+$(info THIS_APP_PATH <-- $(THIS_APP_PATH))
+$(info UART_RX_DEFAULT --> $(UART_RX_DEFAULT))
+$(info UART_TX_DEFAULT --> $(UART_TX_DEFAULT))
+$(info UPGRADE_SUFFIX <-- $(UPGRADE_SUFFIX))
+$(info UPGRADE_TYPE <-- $(UPGRADE_TYPE))
+$(info USE_CRYPTO_HW --> $(USE_CRYPTO_HW))
+$(info USE_EXTERNAL_FLASH <-- $(USE_EXTERNAL_FLASH))
+$(info USE_XIP <-- $(USE_XIP))
+endif
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_flash_map.c b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_flash_map.c
deleted file mode 100644
index 3ea5773..0000000
--- a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_flash_map.c
+++ /dev/null
@@ -1,419 +0,0 @@
-/*
- * Copyright (c) 2018 Nordic Semiconductor ASA
- * Copyright (c) 2020 Cypress Semiconductor Corporation
- * Copyright (c) 2022 Infineon Technologies AG
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <stdbool.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <string.h>
-
-#include "mcuboot_config/mcuboot_config.h"
-#include "flash_map_backend/flash_map_backend.h"
-#include "sysflash/sysflash.h"
-
-#include "bootutil/bootutil_log.h"
-#include "bootutil/bootutil_public.h"
-
-#include "cy_flash.h"
-
-#ifdef NEED_MAX_COUNTERS
-#undef NEED_MAX_COUNTERS
-#endif 
-
-#define NEED_FLASH_MAP /*must be before "cy_flash_map.h"*/
-
-#include "cy_flash_map.h"
-
-#include "cy_smif_cyw20829.h"
-
-#ifdef MCUBOOT_SWAP_USING_STATUS
-#include "swap_status.h"
-#endif
-
-#ifndef CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE
-/* This is the value of external flash bytes after an erase */
-#define CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE  (0xFFu)
-#endif
-
-/*
- * Returns device flash start based on supported fd_id
- */
-int flash_device_base(uint8_t fd_id, uintptr_t *ret)
-{
-   int rc = -1;
-
-    if (NULL != ret) {
-
-        if (FLASH_DEVICE_INTERNAL_FLASH == fd_id) {
-            *ret = CY_FLASH_BASE;
-            rc = 0;
-        }
-        else if ((fd_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
-            *ret = CY_FLASH_BASE;
-            rc = 0;
-        }
-        else {
-            BOOT_LOG_ERR("invalid flash ID %u; expected %u or %u",
-                         (unsigned)fd_id, FLASH_DEVICE_INTERNAL_FLASH,
-                         FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX));
-        }
-    }
-
-    return rc;
-}
-
-/*
- * Opens the area for use. id is one of the `fa_id`s
- */
-int flash_area_open(uint8_t id, const struct flash_area **fa)
-{
-    int ret = -1;
-    uint32_t i = 0u;
-
-    if (NULL != fa) {
-        while (NULL != boot_area_descs[i]) {
-            if (id == boot_area_descs[i]->fa_id) {
-                *fa = boot_area_descs[i];
-                ret = 0;
-                break;
-            }
-            i++;
-        }
-
-        if (ret == 0 &&
-            ((*fa)->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) != 0u) {
-
-            qspi_enable();
-        }
-    }
-
-    return ret;
-}
-
-/*
- * Clear pointer to flash area fa
- */
-void flash_area_close(const struct flash_area *fa)
-{
-    (void)fa; /* Nothing to do there */
-
-    if (NULL != fa) {
-        if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
-            qspi_disable();
-        }
-    }
-}
-
-/*
- * Reads `len` bytes of flash memory at `off` to the buffer at `dst`
- */
-int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
-                     uint32_t len)
-{
-    int rc = -1;
-    size_t addr;
-    uintptr_t flash_base = 0u;
-
-    if ( (NULL != fa) && (NULL != dst) ) {
-
-        if (off > fa->fa_size ||
-            len > fa->fa_size ||
-            off + len > fa->fa_size) {
-
-            return BOOT_EBADARGS;
-        }
-
-        rc = flash_device_base(fa->fa_device_id, &flash_base);
-
-        if (0 == rc) {
-            /* Convert to absolute address inside a device */
-            addr = flash_base + fa->fa_off + off;
-            rc = cyw20829_smif_read(fa, addr, dst, len);
-        }
-    }
-
-    return rc;
-}
-
-/*
- * Writes `len` bytes of flash memory at `off` from the buffer at `src`
- */
-int flash_area_write(const struct flash_area *fa, uint32_t off,
-                     const void *src, uint32_t len)
-{
-    int rc = -1;
-    size_t write_start_addr = 0u;
-    uintptr_t flash_base = 0u;
-
-    if ( (NULL != fa) && (NULL != src) ) {
-
-        if (off > fa->fa_size ||
-            len > fa->fa_size ||
-            off + len > fa->fa_size) {
-
-            return BOOT_EBADARGS;
-        }
-
-        rc = flash_device_base(fa->fa_device_id, &flash_base);
-
-        if (0 == rc) {
-            /* Convert to absolute address inside a device */
-            write_start_addr = flash_base + fa->fa_off + off;
-            rc = cyw20829_smif_write(fa, write_start_addr, src, len);
-        }
-    }
-
-    return (int) rc;
-}
-
-/*< Erases `len` bytes of flash memory at `off` */
-int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
-{
-    int rc = -1;
-    size_t erase_start_addr = 0u;
-    uintptr_t flash_base = 0u;
-
-    if (NULL != fa) {
-
-        if (off > fa->fa_size ||
-            len > fa->fa_size ||
-            off + len > fa->fa_size) {
-
-            return BOOT_EBADARGS;
-        }
-
-        rc = flash_device_base(fa->fa_device_id, &flash_base);
-
-        if (0 == rc) {
-            /* Convert to absolute address inside a device */
-            erase_start_addr = flash_base + fa->fa_off + off;
-            rc = cyw20829_smif_erase(erase_start_addr, len);
-        }
-    }
-
-    return rc;
-}
-
-/*< Returns this `flash_area`s alignment */
-size_t flash_area_align(const struct flash_area *fa)
-{
-    size_t rc = 0u; /* error code (alignment cannot be zero) */
-
-    if (NULL != fa) {
-
-        if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
-            rc = qspi_get_erase_size();
-        }
-    }
-
-    return rc;
-}
-
-#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
-/*< Initializes an array of flash_area elements for the slot's sectors */
-int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa)
-{
-    int rc = -1;
-
-    if (fa != NULL && cnt != NULL) {
-        if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
-            (void)idx;
-            (void)cnt;
-            rc = 0;
-        }
-    }
-
-    return rc;
-}
-#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
-
-/*
- * This depends on the mappings defined in sysflash.h.
- * MCUBoot uses continuous numbering for the primary slot, the secondary slot,
- * and the scratch while zephyr might number it differently.
- */
-int flash_area_id_from_multi_image_slot(int image_index, int slot)
-{
-    int rc;
-    if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
-        return -1;
-    }
-
-    switch (slot) {
-        case 0:
-            rc = (int)FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index);
-            break;
-        case 1:
-            rc = (int)FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index);
-            break;
-        case 2:
-            rc = (int)FLASH_AREA_IMAGE_SCRATCH;
-            break;
-        default:
-            rc = -1; /* flash_area_open will fail on that */
-            break;
-    }
-    return rc;
-}
-
-int flash_area_id_from_image_slot(int slot)
-{
-    return flash_area_id_from_multi_image_slot(0, slot);
-}
-
-int flash_area_id_to_multi_image_slot(int image_index, int area_id)
-{
-    if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
-        return -1;
-    }
-
-    if (area_id == (int) FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index)) {
-        return 0;
-    }
-    if (area_id == (int) FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index)) {
-        return 1;
-    }
-
-    return -1;
-}
-
-int flash_area_id_to_image_slot(int area_id)
-{
-    return flash_area_id_to_multi_image_slot(0, area_id);
-}
-
-uint8_t flash_area_erased_val(const struct flash_area *fa)
-{
-    uint8_t rc = 0;
-
-    if (NULL != fa) {
-        if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
-            rc = (uint8_t) CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE;
-        }
-    }
-
-    return rc;
-}
-
-#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
-int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
-{
-    int rc = 0;
-    uint32_t i = 0u;
-    struct flash_area *fa = NULL;
-    size_t sectors_n = 0u;
-    uint32_t my_sector_addr = 0u;
-    uint32_t my_sector_size = 0u;
-
-    while (NULL != boot_area_descs[i]) {
-        if (idx == (int) boot_area_descs[i]->fa_id) {
-            fa = boot_area_descs[i];
-            break;
-        }
-        i++;
-    }
-
-    if ( (NULL != fa) && (NULL != cnt) && (NULL != ret) ) {
-
-        size_t sector_size = 0;
-        size_t area_size = fa->fa_size;
-
-        if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) != 0u) {
-            /* implement for SMIF */
-            /* lets assume they are equal */
-#ifdef MCUBOOT_SWAP_USING_STATUS
-            int32_t qspi_status = qspi_get_status();
-
-            if (EXT_FLASH_DEV_DISABLED != qspi_status) {
-                sector_size = qspi_get_erase_size();
-            }
-            else {
-                sector_size = CY_FLASH_SIZEOF_ROW;
-            }
-#else /* MCUBOOT_SWAP_USING_STATUS */
-            sector_size = CY_FLASH_SIZEOF_ROW;
-#endif /* MCUBOOT_SWAP_USING_STATUS */
-        }
-        else {
-            /* fa->fa_device_id = FLASH_DEVICE_UNDEFINED,
-               in this case the area should be empty with a very simple sector size of 1 byte */
-            area_size = 0u;
-            sector_size = 1u;
-        }
-
-        sectors_n = (area_size + (sector_size - 1U)) / sector_size;
-
-        BOOT_LOG_DBG(" * FA: %u, off = 0x%" PRIx32
-                     ", area_size = %lu, sector_size = %lu, sectors_n = %lu",
-                     (unsigned)fa->fa_id, fa->fa_off, (unsigned long)area_size,
-                     (unsigned long)sector_size, (unsigned long)sectors_n);
-
-        if (sectors_n > (size_t)MCUBOOT_MAX_IMG_SECTORS) {
-
-                BOOT_LOG_DBG(" + FA: %u, sectors_n(%lu) > MCUBOOT_MAX_IMG_SECTORS(%u) -> sector_size * 2",
-                             (unsigned)fa->fa_id, (unsigned long)sectors_n,
-                             (unsigned int) MCUBOOT_MAX_IMG_SECTORS);
-                sector_size *= 2u;
-            }
-
-        sectors_n = 0u;
-        my_sector_addr = fa->fa_off;
-
-        while (area_size > 0u) {
-
-            my_sector_size = sector_size;
-#ifdef MCUBOOT_SWAP_USING_SCRATCH
-            uint32_t my_sector_offs = my_sector_addr % my_sector_size;
-
-            if (my_sector_offs != 0u) {
-                my_sector_size = sector_size - my_sector_offs;
-            }
-
-            if (my_sector_size > area_size) {
-                my_sector_size = area_size;
-            }
-#endif /* MCUBOOT_SWAP_USING_SCRATCH */
-            ret[sectors_n].fs_size = my_sector_size;
-            ret[sectors_n].fs_off = my_sector_addr;
-
-            my_sector_addr += my_sector_size;
-            area_size -= my_sector_size;
-            sectors_n++;
-        }
-
-        if (sectors_n <= *cnt) {
-            *cnt = sectors_n;
-        }
-        else {
-            rc = -1;
-        }
-    }
-    else {
-        rc = -1;
-    }
-
-    return rc;
-}
-#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_smif_cyw20829.c b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_smif_cyw20829.c
deleted file mode 100644
index f8daf7d..0000000
--- a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_smif_cyw20829.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/***************************************************************************//**
-* \file cy_smif_psoc6.c
-* \version 1.0
-*
-* \brief
-*  This is the source file of external flash driver adoption layer between PSoC6
-*  and standard MCUBoot code.
-*
-********************************************************************************
-* \copyright
-*
-* (c) 2020, Cypress Semiconductor Corporation
-* or a subsidiary of Cypress Semiconductor Corporation. All rights
-* reserved.
-*
-* This software, including source code, documentation and related
-* materials ("Software"), is owned by Cypress Semiconductor
-* Corporation or one of its subsidiaries ("Cypress") and is protected by
-* and subject to worldwide patent protection (United States and foreign),
-* United States copyright laws and international treaty provisions.
-* Therefore, you may use this Software only as provided in the license
-* agreement accompanying the software package from which you
-* obtained this Software ("EULA").
-*
-* If no EULA applies, Cypress hereby grants you a personal, non-
-* exclusive, non-transferable license to copy, modify, and compile the
-* Software source code solely for use in connection with Cypress?s
-* integrated circuit products. Any reproduction, modification, translation,
-* compilation, or representation of this Software except as specified
-* above is prohibited without the express written permission of Cypress.
-*
-* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
-* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
-* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-* PARTICULAR PURPOSE. Cypress reserves the right to make
-* changes to the Software without notice. Cypress does not assume any
-* liability arising out of the application or use of the Software or any
-* product or circuit described in the Software. Cypress does not
-* authorize its products for use in any products where a malfunction or
-* failure of the Cypress product may reasonably be expected to result in
-* significant property damage, injury or death ("High Risk Product"). By
-* including Cypress's product in a High Risk Product, the manufacturer
-* of such system or application assumes all risk of such use and in doing
-* so agrees to indemnify Cypress against all liability.
-*
-******************************************************************************/
-#include "string.h"
-#include "stdlib.h"
-#include "stdbool.h"
-
-#include "flash_map_backend/flash_map_backend.h"
-#include <sysflash/sysflash.h>
-
-#include "cy_device_headers.h"
-#include "cy_smif_cyw20829.h"
-#include "cy_flash.h"
-#include "cy_syspm.h"
-
-#include "flash_qspi.h"
-
-#define CYW20829_WR_SUCCESS                    (0)
-#define CYW20829_WR_ERROR_INVALID_PARAMETER    (1)
-#define CYW20829_WR_ERROR_FLASH_WRITE          (2)
-
-#define CYW20829_FLASH_ERASE_BLOCK_SIZE	CY_FLASH_SIZEOF_ROW /* CYW20829 Flash erases by Row */
-
-int cyw20829_smif_read(const struct flash_area *fap,
-                                        offset_t addr,
-                                        void *data,
-                                        size_t len)
-{
-    int rc = -1;
-    cy_stc_smif_mem_config_t *cfg;
-    cy_en_smif_status_t st;
-    uint32_t address;
-
-    cfg = qspi_get_memory_config(FLASH_DEVICE_GET_EXT_INDEX(fap->fa_device_id));
-
-    address = (uint32_t) addr - CY_XIP_BASE;
-
-    st = Cy_SMIF_MemRead(qspi_get_device(), cfg, address, data, len, qspi_get_context());
-    if (st == CY_SMIF_SUCCESS) {
-        rc = 0;
-    }
-    return rc;
-}
-
-int cyw20829_smif_write(const struct flash_area *fap,
-                                        offset_t addr,
-                                        const void *data,
-                                        size_t len)
-{
-    int rc = -1;
-    cy_en_smif_status_t st;
-    cy_stc_smif_mem_config_t *cfg;
-    uint32_t address;
-
-    cfg =  qspi_get_memory_config(FLASH_DEVICE_GET_EXT_INDEX(fap->fa_device_id));
-
-    address = (uint32_t) addr - CY_XIP_BASE;
-
-    /* NOTE:
-     * External flash chip used on PSVP for 20829 requires memory
-     * to be erased before write for correct operation.
-     */
-    st = Cy_SMIF_MemEraseSector(qspi_get_device(), cfg, address, qspi_get_erase_size(), qspi_get_context());
-
-    if (st == CY_SMIF_SUCCESS) {
-        st = Cy_SMIF_MemWrite(qspi_get_device(), cfg, address, data, len, qspi_get_context());
-    }
-    if (st == CY_SMIF_SUCCESS) {
-        rc = 0;
-    }
-    return rc;
-}
-
-int cyw20829_smif_erase(offset_t addr, size_t size)
-{
-    int rc = -1;
-    cy_en_smif_status_t st = CY_SMIF_SUCCESS;
-
-    if (size > 0u)
-    {
-        /* It is erase sector-only
-         *
-         * There is no power-safe way to erase flash partially
-         * this leads upgrade slots have to be at least
-         * eraseSectorSize far from each other;
-         */
-        cy_stc_smif_mem_config_t *memCfg = qspi_get_memory_config(0);
-        uint32_t eraseSize = qspi_get_erase_size();
-
-        uint32_t address = ((uint32_t)addr - CY_XIP_BASE) & ~((uint32_t)(eraseSize - 1u));
-
-        while ((size > 0u) && (CY_SMIF_SUCCESS == st))
-        {
-            st = Cy_SMIF_MemEraseSector(qspi_get_device(),
-                                            memCfg,
-                                            address,
-                                            eraseSize,
-                                            qspi_get_context());
-
-            size -= (size >= eraseSize) ? eraseSize : size;
-            address += eraseSize;
-        }
-
-        if (st == CY_SMIF_SUCCESS) {
-            rc = 0;
-        }
-    }
-
-    return rc;
-}
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/cy_smif_cyw20829.h b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/cy_smif_cyw20829.h
deleted file mode 100644
index 42b0c1e..0000000
--- a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/cy_smif_cyw20829.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*******************************************************************************
-* \file cy_smif_psoc6.h
-* \version 1.0
-*
-* \brief
-*  This is the header file for PSoC6 SMIF driver adoption layer.
-*
-********************************************************************************
-* \copyright
-*
-* © 2019, Cypress Semiconductor Corporation
-* or a subsidiary of Cypress Semiconductor Corporation. All rights
-* reserved.
-*
-* This software, including source code, documentation and related
-* materials ("Software"), is owned by Cypress Semiconductor
-* Corporation or one of its subsidiaries ("Cypress") and is protected by
-* and subject to worldwide patent protection (United States and foreign),
-* United States copyright laws and international treaty provisions.
-* Therefore, you may use this Software only as provided in the license
-* agreement accompanying the software package from which you
-* obtained this Software ("EULA").
-*
-* If no EULA applies, Cypress hereby grants you a personal, non-
-* exclusive, non-transferable license to copy, modify, and compile the
-* Software source code solely for use in connection with Cypress?s
-* integrated circuit products. Any reproduction, modification, translation,
-* compilation, or representation of this Software except as specified
-* above is prohibited without the express written permission of Cypress.
-*
-* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
-* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
-* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-* PARTICULAR PURPOSE. Cypress reserves the right to make
-* changes to the Software without notice. Cypress does not assume any
-* liability arising out of the application or use of the Software or any
-* product or circuit described in the Software. Cypress does not
-* authorize its products for use in any products where a malfunction or
-* failure of the Cypress product may reasonably be expected to result in
-* significant property damage, injury or death ("High Risk Product"). By
-* including Cypress's product in a High Risk Product, the manufacturer
-* of such system or application assumes all risk of such use and in doing
-* so agrees to indemnify Cypress against all liability.
-*
-******************************************************************************/
-
-#ifndef CY_SMIF_CYW20829_H_
-#define CY_SMIF_CYW20829_H_
-
-#include "stddef.h"
-#include "stdbool.h"
-
-#include "flash_qspi.h"
-
-typedef unsigned long offset_t;
-
-int cyw20829_smif_read(const struct flash_area *fap, offset_t addr, void *data, size_t len);
-int cyw20829_smif_write(const struct flash_area *fap, offset_t addr, const void *data, size_t len);
-int cyw20829_smif_erase(offset_t addr, size_t size);
-
-#endif /* CY_SMIF_CYW20829_H_ */
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/flash_map_backend/flash_map_backend.h b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/flash_map_backend/flash_map_backend.h
deleted file mode 100644
index 82c5578..0000000
--- a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/flash_map_backend/flash_map_backend.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (c) 2018 Nordic Semiconductor ASA
- * Copyright (c) 2015 Runtime Inc
- * Copyright (c) 2020 Cypress Semiconductor Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
- /*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
- /*******************************************************************************/
-
-#ifndef FLASH_MAP_BACKEND_H
-#define FLASH_MAP_BACKEND_H
-
-#include "cy_flash.h"
-#define FLASH_DEVICE_INDEX_MASK                 (0x7Fu)
-#define FLASH_DEVICE_GET_EXT_INDEX(n)           ((n) & FLASH_DEVICE_INDEX_MASK)
-#define FLASH_DEVICE_UNDEFINED                  (0x00u)
-#define FLASH_DEVICE_EXTERNAL_FLAG              (0x80u)
-#define FLASH_DEVICE_INTERNAL_FLASH             (0x7Fu)
-#define FLASH_DEVICE_EXTERNAL_FLASH(index)      (FLASH_DEVICE_EXTERNAL_FLAG | index)
-
-#ifndef CY_BOOT_EXTERNAL_DEVICE_INDEX
-/* assume first(one) SMIF device is used */
-#define CY_BOOT_EXTERNAL_DEVICE_INDEX           (0u)
-#endif
-
-/**
- *
- * Provides abstraction of flash regions for type of use.
- * I.e. dude where's my image?
- *
- * System will contain a map which contains flash areas. Every
- * region will contain flash identifier, offset within flash and length.
- *
- * 1. This system map could be in a file within filesystem (Initializer
- * must know/figure out where the filesystem is at).
- * 2. Map could be at fixed location for project (compiled to code)
- * 3. Map could be at specific place in flash (put in place at mfg time).
- *
- * Note that the map you use must be valid for BSP it's for,
- * match the linker scripts when platform executes from flash,
- * and match the target offset specified in download script.
- */
-#include <inttypes.h>
-
-/**
- * @brief Structure describing an area on a flash device.
- *
- * Multiple flash devices may be available in the system, each of
- * which may have its own areas. For this reason, flash areas track
- * which flash device they are part of.
- */
-struct flash_area {
-    /**
-     * This flash area's ID; unique in the system.
-     */
-    uint8_t fa_id;
-
-    /**
-     * ID of the flash device this area is a part of.
-     */
-    uint8_t fa_device_id;
-
-    uint16_t pad16;
-
-    /**
-     * This area's offset, relative to the beginning of its flash
-     * device's storage.
-     */
-    uint32_t fa_off;
-
-    /**
-     * This area's size, in bytes.
-     */
-    uint32_t fa_size;
-};
-
-static inline uint8_t flash_area_get_id(const struct flash_area *fa)
-{
-    return fa->fa_id;
-}
-
-static inline uint8_t flash_area_get_device_id(const struct flash_area *fa)
-{
-    return fa->fa_device_id;
-}
-
-static inline uint32_t flash_area_get_off(const struct flash_area *fa)
-{
-    return fa->fa_off;
-}
-
-static inline uint32_t flash_area_get_size(const struct flash_area *fa)
-{
-    return fa->fa_size;
-}
-
-/**
- * @brief Structure describing a sector within a flash area.
- *
- * Each sector has an offset relative to the start of its flash area
- * (NOT relative to the start of its flash device), and a size. A
- * flash area may contain sectors with different sizes.
- */
-struct flash_sector {
-    /**
-     * Offset of this sector, from the start of its flash area (not device).
-     */
-    uint32_t fs_off;
-
-    /**
-     * Size of this sector, in bytes.
-     */
-    uint32_t fs_size;
-};
-
-static inline uint32_t flash_sector_get_off(const struct flash_sector *fs)
-{
-    return fs->fs_off;
-}
-
-static inline uint32_t flash_sector_get_size(const struct flash_sector *fs)
-{
-    return fs->fs_size;
-}
-
-struct flash_map_entry {
-    uint32_t magic;
-    struct flash_area area;
-    unsigned int ref_count;
-};
-
-/*
- * Retrieve a memory-mapped flash device's base address.
- * On success, the address will be stored in the value pointed to by
- * ret.
- * Returns 0 on success, or an error code on failure.
- */
-int flash_device_base(uint8_t fd_id, uintptr_t *ret);
-
-/*< Opens the area for use. id is one of the `fa_id`s */
-int flash_area_open(uint8_t id, const struct flash_area **fa);
-void flash_area_close(const struct flash_area *fa);
-/*< Reads `len` bytes of flash memory at `off` to the buffer at `dst` */
-int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
-                     uint32_t len);
-/*< Writes `len` bytes of flash memory at `off` from the buffer at `src` */
-int flash_area_write(const struct flash_area *fa, uint32_t off,
-                     const void *src, uint32_t len);
-/*< Erases `len` bytes of flash memory at `off` */
-int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len);
-/*< Returns this `flash_area`s alignment */
-size_t flash_area_align(const struct flash_area *fa);
-/*< Initializes an array of flash_area elements for the slot's sectors */
-int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa);
-/*< Returns the `fa_id` for slot, where slot is 0 (primary) or 1 (secondary) */
-int flash_area_id_from_image_slot(int slot);
-/*< Returns the slot, for the `fa_id` supplied */
-int flash_area_id_to_image_slot(int area_id);
-
-int flash_area_id_from_multi_image_slot(int image_index, int slot);
-int flash_area_id_to_multi_image_slot(int image_index, int area_id);
-#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
-int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret);
-#endif
-/*
- * Returns the value expected to be read when accesing any erased
- * flash byte.
- */
-uint8_t flash_area_erased_val(const struct flash_area *fa);
-
-// *****************************************************************************
-#ifdef MCUBOOT_ENC_IMAGES_XIP
-
-#include "bootutil/image.h"
-#include "bootutil/enc_key.h"
-
-int bootutil_img_encrypt(struct enc_key_data *enc_state, int image_index,
-        struct image_header *hdr, const struct flash_area *fap, uint32_t off, uint32_t sz,
-        uint32_t blk_off, uint8_t *buf);
-#endif /* MCUBOOT_ENC_IMAGES_XIP */
-
-
-#endif /* FLASH_MAP_BACKEND_H */
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_flash_map.c b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_flash_map.c
deleted file mode 100644
index a3f23b8..0000000
--- a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_flash_map.c
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- * Copyright (c) 2018 Nordic Semiconductor ASA
- * Copyright (c) 2020 Cypress Semiconductor Corporation
- * Copyright (c) 2022 Infineon Technologies AG
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <stdbool.h>
-#include <stdio.h>
-#include <stdint.h>
-#include <string.h>
-
-#include "mcuboot_config/mcuboot_config.h"
-#include "flash_map_backend/flash_map_backend.h"
-#include <sysflash/sysflash.h>
-
-#include "bootutil/bootutil_log.h"
-#include "bootutil/bootutil_public.h"
-#include "bootutil/fault_injection_hardening.h" /* for FIH_PANIC */
-
-#include "cy_flash.h"
-#include "cy_flash_map.h"
-
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
-#include "cy_smif_psoc6.h"
-#endif
-
-#ifdef MCUBOOT_SWAP_USING_STATUS
-#include "swap_status.h"
-#endif
-
-#ifndef CY_BOOT_INTERNAL_FLASH_ERASE_VALUE
-/* This is the value of internal flash bytes after an erase */
-#define CY_BOOT_INTERNAL_FLASH_ERASE_VALUE  (0x00u)
-#endif /* CY_BOOT_INTERNAL_FLASH_ERASE_VALUE */
-
-#ifndef CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE
-/* This is the value of external flash bytes after an erase */
-#define CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE  (0xFFu)
-#endif /* CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE */
-
-/*
- * Returns device flash start based on supported fd_id
- */
-int flash_device_base(uint8_t fd_id, uintptr_t *ret)
-{
-    int rc = -1;
-
-    if (ret != NULL) {
-        if (FLASH_DEVICE_INTERNAL_FLASH == fd_id) {
-            *ret = CY_FLASH_BASE;
-            rc = 0;
-        }
-    #ifdef CY_BOOT_USE_EXTERNAL_FLASH
-        else if ((fd_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
-            *ret = CY_SMIF_BASE_MEM_OFFSET;
-            rc = 0;
-        }
-    #endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-        else {
-            BOOT_LOG_ERR("invalid flash ID %u; expected %u or %u",
-                        (unsigned)fd_id, FLASH_DEVICE_INTERNAL_FLASH,
-                        FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX));
-        }
-    }
-
-    return rc;
-}
-
-/*
- * Opens the area for use. id is one of the `fa_id`s
- */
-int flash_area_open(uint8_t id, const struct flash_area **fa)
-{
-    int rc = -1;
-    uint32_t i = 0u;
-
-    if (fa != NULL) {
-        while (boot_area_descs[i] != NULL) {
-
-            if (id == boot_area_descs[i]->fa_id) {
-                *fa = boot_area_descs[i];
-                rc = 0;
-                break;
-            }
-            i++;
-        }
-    }
-
-    return rc;
-}
-
-/*
- * Clear pointer to flash area fa
- */
-void flash_area_close(const struct flash_area *fa)
-{
-    (void)fa; /* Nothing to do there */
-}
-
-/*
- * Reads `len` bytes of flash memory at `off` to the buffer at `dst`
- */
-int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
-                     uint32_t len)
-{
-    int rc = -1;
-    uintptr_t addr = 0u;
-    uintptr_t flash_base = 0u;
-    void* src;
-
-    if ((dst != NULL) && (fa != NULL)) {
-
-        if (off > fa->fa_size ||
-            len > fa->fa_size ||
-            off + len > fa->fa_size) {
-
-            return BOOT_EBADARGS;
-        }
-
-        rc = flash_device_base(fa->fa_device_id, &flash_base);
-
-        if (0 == rc) {
-
-            addr = flash_base + fa->fa_off + off;
-
-            if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
-                /* Convert from uintptr_t to void*, MISRA C 11.6 */
-                (void)memcpy((void *)&src, (void const *)&addr, sizeof(void*));
-                /* flash read by simple memory copying */
-                (void)memcpy(dst, src, (size_t)len);
-            }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
-            else {
-                rc = psoc6_smif_read(fa, addr, dst, len);
-            }
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-        }
-    }
-
-    return rc;
-}
-
-/*
- * Writes `len` bytes of flash memory at `off` from the buffer at `src`
- */
-int flash_area_write(const struct flash_area *fa, uint32_t off,
-                     const void *src, uint32_t len)
-{
-    int rc = BOOT_EFLASH;
-    uintptr_t write_start_addr = 0u;
-    uintptr_t write_end_addr = 0u;
-    const uint32_t * row_ptr = NULL;
-    uintptr_t flash_base = 0u;
-
-    if ((src != NULL) && (fa != NULL)) {
-
-        if (off > fa->fa_size ||
-            len > fa->fa_size ||
-            off + len > fa->fa_size) {
-
-            return BOOT_EBADARGS;
-        }
-
-        rc = flash_device_base(fa->fa_device_id, &flash_base);
-
-        if (0 == rc) {
-
-            write_start_addr = flash_base + fa->fa_off + off;
-            write_end_addr = flash_base + fa->fa_off + off + len;
-
-            if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
-
-                uint32_t row_number = 0u;
-                uint32_t row_addr = 0u;
-
-                if (len % CY_FLASH_SIZEOF_ROW != 0u) {
-                    return BOOT_EBADARGS;
-                }
-
-                if (write_start_addr % CY_FLASH_SIZEOF_ROW != 0u) {
-                    return BOOT_EBADARGS;
-                }
-
-                row_number = (write_end_addr - write_start_addr) / CY_FLASH_SIZEOF_ROW;
-                row_addr = write_start_addr;
-
-                row_ptr = (const uint32_t *) src;
-
-                for (uint32_t i = 0; i < row_number; i++) {
-                    if (Cy_Flash_WriteRow(row_addr, row_ptr) != CY_FLASH_DRV_SUCCESS) {
-                        rc = BOOT_EFLASH;
-                        break;
-                    }
-
-                    row_addr += (uint32_t) CY_FLASH_SIZEOF_ROW;
-                    row_ptr = row_ptr + CY_FLASH_SIZEOF_ROW / 4U;
-                }
-            }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
-            else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) != 0u) {
-                rc = psoc6_smif_write(fa, write_start_addr, src, len);
-            }
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-            else {
-                return BOOT_EFLASH;
-            }
-        }
-    }
-
-    return rc;
-}
-
-/*< Erases `len` bytes of flash memory at `off` */
-int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
-{
-    int rc = -1;
-    uintptr_t erase_start_addr = 0u;
-    uintptr_t erase_end_addr = 0u;
-    uintptr_t flash_base = 0u;
-
-    if (fa != NULL) {
-        if (off > fa->fa_size ||
-            len > fa->fa_size ||
-            off + len > fa->fa_size) {
-
-            return BOOT_EBADARGS;
-        }
-
-        rc = flash_device_base(fa->fa_device_id, &flash_base);
-
-        if (0 == rc) {
-            erase_start_addr = flash_base + fa->fa_off + off;
-            erase_end_addr = flash_base + fa->fa_off + off + len;
-
-            if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
-                uint32_t row_number = 0u;
-                uint32_t row_addr = 0u;
-                uint32_t row_start_addr = (erase_start_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;
-                uint32_t row_end_addr = (erase_end_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;
-
-                /* assume single row needs to be erased */
-                if (row_start_addr == row_end_addr) {
-                    if (Cy_Flash_EraseRow(row_start_addr) != CY_FLASH_DRV_SUCCESS) {
-                        rc = BOOT_EFLASH;
-                    }
-                }
-                else {
-                    row_number = (row_end_addr - row_start_addr) / CY_FLASH_SIZEOF_ROW;
-
-                    while (row_number != 0u) {
-                        row_number--;
-                        row_addr = row_start_addr + row_number * (uint32_t) CY_FLASH_SIZEOF_ROW;
-                        if (Cy_Flash_EraseRow(row_addr) != CY_FLASH_DRV_SUCCESS) {
-                            rc = BOOT_EFLASH;
-                            break;
-                        }
-                    }
-                }
-            }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
-            else {
-                rc = psoc6_smif_erase(erase_start_addr, len);
-            }
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-        }
-    }
-
-    return rc;
-}
-
-/*< Returns this `flash_area`s alignment */
-size_t flash_area_align(const struct flash_area *fa)
-{
-    size_t rc = 0u; /* error code (alignment cannot be zero) */
-
-    if (fa != NULL) {
-        if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
-            rc = CY_FLASH_ALIGN;
-        }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
-        else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
-            rc = qspi_get_prog_size();
-        }
-        else {
-            /* No action required */
-        }
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-    }
-
-    return rc;
-}
-
-#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
-/*< Initializes an array of flash_area elements for the slot's sectors */
-int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa)
-{
-    int rc = -1;
-
-    if (cnt != NULL && fa != NULL) {
-        if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
-            (void)idx;
-            (void)cnt;
-            rc = 0;
-        }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
-        else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
-            (void)idx;
-            (void)cnt;
-            rc = 0;
-        }
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-        else {
-            /* incorrect/non-existing flash device id */
-            rc = -1;
-        }
-    }
-
-    return rc;
-}
-#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
-
-/*
- * This depends on the mappings defined in sysflash.h.
- * MCUBoot uses continuous numbering for the primary slot, the secondary slot,
- * and the scratch while zephyr might number it differently.
- */
-int flash_area_id_from_multi_image_slot(int image_index, int slot)
-{
-    int rc = -1;
-    if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
-        return -1;
-    }
-
-    switch (slot) {
-        case 0:
-            rc = (int)FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index);
-            break;
-        case 1:
-            rc = (int)FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index);
-            break;
-        case 2:
-            rc = (int)FLASH_AREA_IMAGE_SCRATCH;
-            break;
-        default:
-            rc = -1; /* flash_area_open will fail on that */
-            break;
-    }
-    return rc;
-}
-
-int flash_area_id_from_image_slot(int slot)
-{
-    return flash_area_id_from_multi_image_slot(0, slot);
-}
-
-int flash_area_id_to_multi_image_slot(int image_index, int area_id)
-{
-    if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
-        return -1;
-    }
-
-    if ((int) FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index) == area_id) {
-        return 0;
-    }
-    if ((int) FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index) == area_id) {
-        return 1;
-    }
-
-    return -1;
-}
-
-int flash_area_id_to_image_slot(int area_id)
-{
-    return flash_area_id_to_multi_image_slot(0, area_id);
-}
-
-uint8_t flash_area_erased_val(const struct flash_area *fa)
-{
-    uint8_t ret = 0u;
-
-    if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
-        ret = (uint8_t) CY_BOOT_INTERNAL_FLASH_ERASE_VALUE;
-    }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
-    else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) != 0u) {
-        ret = (uint8_t) CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE;
-    }
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-    else {
-        ret = 0u; /* The variable is reassigned to make the statement comply with the MISRA rule 15.7 */
-        FIH_PANIC; /* There is no appropriate error code */
-    }
-
-    return ret;
-}
-
-#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
-int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
-{
-    int rc = 0;
-    uint32_t i = 0u;
-    struct flash_area *fa = NULL;
-    size_t sectors_n = 0u;
-    uint32_t my_sector_addr = 0u;
-    uint32_t my_sector_size = 0u;
-
-    while (boot_area_descs[i] != NULL) {
-        if (idx == (int) boot_area_descs[i]->fa_id) {
-            fa = boot_area_descs[i];
-            break;
-        }
-        i++;
-    }
-
-    if ((fa != NULL) && (cnt != NULL) && (ret != NULL)) {
-        size_t sector_size = 0;
-        size_t area_size = fa->fa_size;
-
-        if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
-            sector_size = CY_FLASH_SIZEOF_ROW;
-#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && defined(MCUBOOT_SWAP_USING_STATUS) && !defined(MCUBOOT_SWAP_USING_SCRATCH)
-            if ((int) FLASH_AREA_IMAGE_SWAP_STATUS == idx) {
-                sector_size = CY_FLASH_SIZEOF_ROW;
-            }
-            else {
-                sector_size = qspi_get_erase_size();
-            }
-#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && defined(MCUBOOT_SWAP_USING_STATUS) && !defined(MCUBOOT_SWAP_USING_SCRATCH) */
-        }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
-        else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
-        /* implement for SMIF */
-        /* lets assume they are equal */
-#if defined(MCUBOOT_SWAP_USING_STATUS) || defined(USE_XIP)
-            sector_size = qspi_get_erase_size();
-#else
-            sector_size = CY_FLASH_SIZEOF_ROW;
-#endif /* MCUBOOT_SWAP_USING_STATUS */
-        }
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
-        else {
-            /* fa->fa_device_id = FLASH_DEVICE_UNDEFINED,
-               in this case the area should be empty with a very simple sector size of 1 byte */
-            area_size = 0u;
-            sector_size = 1u;
-        }
-
-        sectors_n = (area_size + (sector_size - 1U)) / sector_size;
-
-        if (sectors_n > (size_t)MCUBOOT_MAX_IMG_SECTORS) {
-            sector_size *= 2u;
-        }
-
-        sectors_n = 0;
-        my_sector_addr = fa->fa_off;
-        while (area_size > 0u) {
-            my_sector_size = sector_size;
-#ifdef MCUBOOT_SWAP_USING_SCRATCH
-            uint32_t my_sector_offs = my_sector_addr % my_sector_size;
-
-            if (my_sector_offs != 0u) {
-                my_sector_size = sector_size - my_sector_offs;
-            }
-
-            if (my_sector_size > area_size) {
-                my_sector_size = area_size;
-            }
-#endif /* MCUBOOT_SWAP_USING_SCRATCH */
-            ret[sectors_n].fs_size = my_sector_size;
-            ret[sectors_n].fs_off = my_sector_addr;
-
-            my_sector_addr += my_sector_size;
-            if (area_size >= my_sector_size) {
-            	area_size -= my_sector_size;
-            	sectors_n++;
-            }
-            else {
-            	area_size = 0;
-            }
-        }
-
-        if (sectors_n <= *cnt) {
-            *cnt = sectors_n;
-        }
-        else {
-            rc = -1;
-        }
-    }
-    else {
-        rc = -1;
-    }
-
-    return rc;
-}
-#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c
deleted file mode 100644
index d8f7a7e..0000000
--- a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/***************************************************************************//**
-* \file cy_smif_psoc6.c
-* \version 1.0
-*
-* \brief
-*  This is the source file of external flash driver adoption layer between PSoC6
-*  and standard MCUBoot code.
-*
-********************************************************************************
-* \copyright
-*
-* (c) 2020, Cypress Semiconductor Corporation
-* or a subsidiary of Cypress Semiconductor Corporation. All rights
-* reserved.
-*
-* This software, including source code, documentation and related
-* materials ("Software"), is owned by Cypress Semiconductor
-* Corporation or one of its subsidiaries ("Cypress") and is protected by
-* and subject to worldwide patent protection (United States and foreign),
-* United States copyright laws and international treaty provisions.
-* Therefore, you may use this Software only as provided in the license
-* agreement accompanying the software package from which you
-* obtained this Software ("EULA").
-*
-* If no EULA applies, Cypress hereby grants you a personal, non-
-* exclusive, non-transferable license to copy, modify, and compile the
-* Software source code solely for use in connection with Cypress?s
-* integrated circuit products. Any reproduction, modification, translation,
-* compilation, or representation of this Software except as specified
-* above is prohibited without the express written permission of Cypress.
-*
-* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
-* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
-* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-* PARTICULAR PURPOSE. Cypress reserves the right to make
-* changes to the Software without notice. Cypress does not assume any
-* liability arising out of the application or use of the Software or any
-* product or circuit described in the Software. Cypress does not
-* authorize its products for use in any products where a malfunction or
-* failure of the Cypress product may reasonably be expected to result in
-* significant property damage, injury or death ("High Risk Product"). By
-* including Cypress's product in a High Risk Product, the manufacturer
-* of such system or application assumes all risk of such use and in doing
-* so agrees to indemnify Cypress against all liability.
-*
-******************************************************************************/
-#ifndef CYW20829
-
-#include "string.h"
-#include "stdlib.h"
-#include "stdbool.h"
-
-#include "flash_map_backend/flash_map_backend.h"
-#include <sysflash/sysflash.h>
-
-#include "cy_device_headers.h"
-#include "cy_smif_psoc6.h"
-#include "cy_flash.h"
-#include "cy_syspm.h"
-
-#include "flash_qspi.h"
-
-#define PSOC6_WR_SUCCESS                    (0)
-#define PSOC6_WR_ERROR_INVALID_PARAMETER    (1)
-#define PSOC6_WR_ERROR_FLASH_WRITE          (2)
-
-#define PSOC6_FLASH_ERASE_BLOCK_SIZE	CY_FLASH_SIZEOF_ROW /* PSoC6 Flash erases by Row */
-
-int psoc6_smif_read(const struct flash_area *fap,
-                                        offset_t addr,
-                                        void *data,
-                                        size_t len)
-{
-    int rc = -1;
-    cy_stc_smif_mem_config_t *cfg;
-    cy_en_smif_status_t st;
-    uint32_t address;
-
-    cfg = qspi_get_memory_config(FLASH_DEVICE_GET_EXT_INDEX(fap->fa_device_id));
-
-    address = (uint32_t) addr - CY_SMIF_BASE_MEM_OFFSET;
-
-    st = Cy_SMIF_MemRead(qspi_get_device(), cfg, address, data, len, qspi_get_context());
-    if (st == CY_SMIF_SUCCESS) {
-        rc = 0;
-    }
-    return rc;
-}
-
-int psoc6_smif_write(const struct flash_area *fap,
-                                        offset_t addr,
-                                        const void *data,
-                                        size_t len)
-{
-    int rc = -1;
-    cy_en_smif_status_t st;
-    cy_stc_smif_mem_config_t *cfg;
-    uint32_t address;
-
-    cfg =  qspi_get_memory_config(FLASH_DEVICE_GET_EXT_INDEX(fap->fa_device_id));
-
-    address = (uint32_t) addr - CY_SMIF_BASE_MEM_OFFSET;
-
-    st = Cy_SMIF_MemWrite(qspi_get_device(), cfg, address, data, len, qspi_get_context());
-    if (st == CY_SMIF_SUCCESS) {
-        rc = 0;
-    }
-    return rc;
-}
-
-int psoc6_smif_erase(offset_t addr, size_t size)
-{
-    int rc = -1;
-    cy_en_smif_status_t st = CY_SMIF_SUCCESS;
-    uint32_t address;
-
-    if (size > 0u)
-    {
-        /* It is erase sector-only
-         *
-         * There is no power-safe way to erase flash partially
-         * this leads upgrade slots have to be at least
-         * eraseSectorSize far from each other;
-         */
-        cy_stc_smif_mem_config_t *memCfg = qspi_get_memory_config(0);
-
-        address = ((uint32_t)addr - CY_SMIF_BASE_MEM_OFFSET ) & ~((uint32_t)(memCfg->deviceCfg->eraseSize - 1u));
-
-        while ((size > 0u) && (CY_SMIF_SUCCESS == st))
-        {
-            st = Cy_SMIF_MemEraseSector(qspi_get_device(),
-                                            memCfg,
-                                            address,
-                                            memCfg->deviceCfg->eraseSize,
-                                            qspi_get_context());
-
-            size -= (size >= memCfg->deviceCfg->eraseSize) ? memCfg->deviceCfg->eraseSize : size;
-            address += memCfg->deviceCfg->eraseSize;
-        }
-
-        if (st == CY_SMIF_SUCCESS) {
-            rc = 0;
-        }
-    }
-
-    return rc;
-}
-
-#endif /* CY20829 */
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h
deleted file mode 100644
index 219f3c9..0000000
--- a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/***************************************************************************//**
-* \file cy_smif_psoc6.h
-* \version 1.0
-*
-* \brief
-*  This is the header file for PSoC6 SMIF driver adoption layer.
-*
-********************************************************************************
-* \copyright
-*
-* © 2019, Cypress Semiconductor Corporation
-* or a subsidiary of Cypress Semiconductor Corporation. All rights
-* reserved.
-*
-* This software, including source code, documentation and related
-* materials ("Software"), is owned by Cypress Semiconductor
-* Corporation or one of its subsidiaries ("Cypress") and is protected by
-* and subject to worldwide patent protection (United States and foreign),
-* United States copyright laws and international treaty provisions.
-* Therefore, you may use this Software only as provided in the license
-* agreement accompanying the software package from which you
-* obtained this Software ("EULA").
-*
-* If no EULA applies, Cypress hereby grants you a personal, non-
-* exclusive, non-transferable license to copy, modify, and compile the
-* Software source code solely for use in connection with Cypress?s
-* integrated circuit products. Any reproduction, modification, translation,
-* compilation, or representation of this Software except as specified
-* above is prohibited without the express written permission of Cypress.
-*
-* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
-* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
-* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-* PARTICULAR PURPOSE. Cypress reserves the right to make
-* changes to the Software without notice. Cypress does not assume any
-* liability arising out of the application or use of the Software or any
-* product or circuit described in the Software. Cypress does not
-* authorize its products for use in any products where a malfunction or
-* failure of the Cypress product may reasonably be expected to result in
-* significant property damage, injury or death ("High Risk Product"). By
-* including Cypress's product in a High Risk Product, the manufacturer
-* of such system or application assumes all risk of such use and in doing
-* so agrees to indemnify Cypress against all liability.
-*
-******************************************************************************/
-
-#ifndef CY_SMIF_PSOC6_H_
-#define CY_SMIF_PSOC6_H_
-
-#ifndef CYW20829
-
-#include "stddef.h"
-#include "stdbool.h"
-
-#include "flash_qspi.h"
-
-typedef unsigned long offset_t;
-
-int psoc6_smif_read(const struct flash_area *fap, offset_t addr, void *data, size_t len);
-int psoc6_smif_write(const struct flash_area *fap, offset_t addr, const void *data, size_t len);
-int psoc6_smif_erase(offset_t addr, size_t size);
-
-#endif /* CY_SMIF_PSOC6_H_ */
-
-#endif /* CYW20829 */
diff --git a/boot/cypress/platforms/cy_flash_pal/sysflash/sysflash.h b/boot/cypress/platforms/cy_flash_pal/sysflash/sysflash.h
deleted file mode 100644
index dfe015f..0000000
--- a/boot/cypress/platforms/cy_flash_pal/sysflash/sysflash.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright (c) 2020 Cypress Semiconductor Corporation
- * Copyright (c) 2022 Infineon Technologies AG
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements.  See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership.  The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License.  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied.  See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef SYSFLASH_H
-#define SYSFLASH_H
-
-#include <stdint.h>
-#include "cy_syslib.h"
-
-#ifndef MCUBOOT_IMAGE_NUMBER
-#ifdef MCUBootApp
-#warning Undefined MCUBOOT_IMAGE_NUMBER. Assuming 1 (single-image).
-#endif /* MCUBootApp */
-#define MCUBOOT_IMAGE_NUMBER 1
-#endif /* MCUBOOT_IMAGE_NUMBER */
-
-#if (MCUBOOT_IMAGE_NUMBER < 1 || MCUBOOT_IMAGE_NUMBER > 4)
-#error Unsupported MCUBOOT_IMAGE_NUMBER. Set it to between 1 and 4.
-#endif /* (MCUBOOT_IMAGE_NUMBER < 1 || MCUBOOT_IMAGE_NUMBER > 4) */
-
-#define FLASH_AREA_BOOTLOADER        ( 0u)
-
-#define FLASH_AREA_IMG_1_PRIMARY     ( 1u)
-#define FLASH_AREA_IMG_1_SECONDARY   ( 2u)
-
-#define FLASH_AREA_IMAGE_SCRATCH     ( 3u)
-
-#if MCUBOOT_IMAGE_NUMBER >= 2
-#define FLASH_AREA_IMG_2_PRIMARY     ( 4u)
-#define FLASH_AREA_IMG_2_SECONDARY   ( 5u)
-#endif /* MCUBOOT_IMAGE_NUMBER >= 2 */
-
-#define FLASH_AREA_IMAGE_SWAP_STATUS ( 7u)
-
-#if MCUBOOT_IMAGE_NUMBER >= 3
-#define FLASH_AREA_IMG_3_PRIMARY     ( 8u)
-#define FLASH_AREA_IMG_3_SECONDARY   ( 9u)
-#endif /* MCUBOOT_IMAGE_NUMBER >= 3 */
-
-#if MCUBOOT_IMAGE_NUMBER == 4
-#define FLASH_AREA_IMG_4_PRIMARY     (10u)
-#define FLASH_AREA_IMG_4_SECONDARY   (11u)
-#endif /* MCUBOOT_IMAGE_NUMBER == 4 */
-
-#define FLASH_AREA_ERROR             255u  /* Invalid flash area */
-
-#ifdef PSOC6
-#define CY_SMIF_BASE_MEM_OFFSET             0x18000000u
-#endif /* PSOC6 */
-
-/* This defines if External Flash (SMIF) will be used for Upgrade Slots */
-#ifdef CYW20829
-#define CY_FLASH_BASE                       CY_XIP_BASE
-#define CY_SMIF_BASE_MEM_OFFSET             CY_FLASH_BASE
-#define CY_FLASH_SIZEOF_ROW                 4096u
-#endif /* CYW20829 */
-
-/* use PDL-defined offset or one from SMIF config */
-#define CY_SMIF_BASE                        (CY_XIP_BASE)
-
-#define CY_FLASH_ALIGN                      (CY_FLASH_SIZEOF_ROW)
-#define CY_FLASH_DEVICE_BASE                (CY_FLASH_BASE)
-
-#define CY_IMG_HDR_SIZE                     0x400
-#define BOOT_MAX_SWAP_STATUS_SECTORS        (64)
-
-__STATIC_INLINE uint8_t FLASH_AREA_IMAGE_PRIMARY(uint32_t img_idx)
-{
-    uint8_t result = FLASH_AREA_ERROR;
-
-    if (img_idx < (uint32_t)MCUBOOT_IMAGE_NUMBER) {
-        static const uint8_t areas[] = {
-            FLASH_AREA_IMG_1_PRIMARY,
-#if MCUBOOT_IMAGE_NUMBER >= 2
-            FLASH_AREA_IMG_2_PRIMARY,
-#endif /* MCUBOOT_IMAGE_NUMBER >= 2 */
-#if MCUBOOT_IMAGE_NUMBER >= 3
-            FLASH_AREA_IMG_3_PRIMARY,
-#endif /* MCUBOOT_IMAGE_NUMBER >= 3 */
-#if MCUBOOT_IMAGE_NUMBER == 4
-            FLASH_AREA_IMG_4_PRIMARY
-#endif /* MCUBOOT_IMAGE_NUMBER == 4 */
-        };
-
-        result = areas[img_idx];
-    }
-
-    return result;
-}
-
-__STATIC_INLINE uint8_t FLASH_AREA_IMAGE_SECONDARY(uint32_t img_idx)
-{
-    uint8_t result = FLASH_AREA_ERROR;
-
-    if (img_idx < (uint32_t)MCUBOOT_IMAGE_NUMBER) {
-        static const uint8_t areas[] = {
-            FLASH_AREA_IMG_1_SECONDARY,
-#if MCUBOOT_IMAGE_NUMBER >= 2
-            FLASH_AREA_IMG_2_SECONDARY,
-#endif /* MCUBOOT_IMAGE_NUMBER >= 2 */
-#if MCUBOOT_IMAGE_NUMBER >= 3
-            FLASH_AREA_IMG_3_SECONDARY,
-#endif /* MCUBOOT_IMAGE_NUMBER >= 3 */
-#if MCUBOOT_IMAGE_NUMBER == 4
-            FLASH_AREA_IMG_4_SECONDARY
-#endif /* MCUBOOT_IMAGE_NUMBER == 4 */
-        };
-
-        result = areas[img_idx];
-    }
-
-    return result;
-}
-
-#endif /* SYSFLASH_H */
diff --git a/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c b/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c
new file mode 100644
index 0000000..ee78156
--- /dev/null
+++ b/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c
@@ -0,0 +1,236 @@
+/********************************************************************************
+* Copyright 2021 Infineon Technologies AG
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
+
+#include "set_img_ok.h"
+
+static uint8_t row_buff[FLASH_ROW_BUF_SZ];
+
+#ifndef USE_XIP
+
+/**
+ * @brief Function reads value of img_ok flag from address.
+ * 
+ * @param address - address of img_ok flag in primary img trailer
+ * @return int - value at address
+ */
+static int read_img_ok_value(uint32_t address)
+{
+    return *(volatile uint8_t *)address;
+}
+
+/**
+ * @brief Function sets img_ok flag value to primary image trailer.
+ * 
+ * @param address - address of img_ok flag in primary img trailer
+ * @param value - value corresponding to img_ok set
+ * 
+ * @return - operation status. 0 - set succesfully, -1 - failed to set.
+ */
+static int write_img_ok_value(uint32_t address, uint8_t value)
+{
+    int rc = -1;
+    uint32_t row_addr = 0;
+
+    uint32_t row_mask = CY_FLASH_SIZEOF_ROW /* is a power of 2 */ - 1u;
+    cy_en_flashdrv_status_t st;
+
+    /* Accepting an arbitrary address */
+    row_addr = address & ~row_mask;
+
+    /* Preserving the row */
+    (void)memcpy(row_buff, (void *)row_addr, sizeof(row_buff));
+
+    /* Modifying the target byte */
+    row_buff[address & row_mask] = value;
+
+    /* Programming the updated row back */
+    st = Cy_Flash_ProgramRow(row_addr, (const uint32_t *)row_buff);
+
+    if (CY_FLASH_DRV_SUCCESS == st) {
+        rc = 0;
+    }
+
+    return rc;
+}
+
+#else
+
+/**
+ * @brief Function sets img_ok value to primary slot trailer
+ *        when application is executed from external memory 
+ *        in XIP mode. This function is executed from RAM since
+ *        it reconfigures SMIF block from XIP to MMIO mode, then
+ *        writes img_ok set value and switches back to XIP mode.
+ *
+ * @param address - address of img_ok flag in primary img trailer
+ * @param value - value corresponding to img_ok set
+ * 
+ * @return - operation status. 1 - already set, 0 - set succesfully,
+ *                              -1 - failed to set.
+ */
+CY_RAMFUNC_BEGIN
+static int set_img_ok_ram(uint32_t address, uint8_t value)
+{
+    int32_t rc = IMG_OK_SET_FAILED;
+    uint32_t try_count = 10U;
+
+    cy_en_smif_status_t stat = CY_SMIF_BUSY;
+    SMIF_Type *QSPIPort = SMIF0;
+    cy_stc_smif_context_t QSPI_context;
+    cy_en_smif_mode_t mode = CY_SMIF_NORMAL;
+
+    Cy_SMIF_SetMode(SMIF0, CY_SMIF_NORMAL);
+    mode = Cy_SMIF_GetMode(QSPIPort);
+
+    if (mode != CY_SMIF_NORMAL) {
+        CY_HALT();
+    }
+
+    for (try_count = 0U; try_count < 10U; try_count++) {
+
+        stat = Cy_SMIF_MemInit(QSPIPort, &smifBlockConfig_sfdp, &QSPI_context);
+
+        if (CY_SMIF_SUCCESS == stat) {
+            break;
+        }
+
+        Cy_SysLib_Delay(500U);
+    }
+
+    if (stat == CY_SMIF_SUCCESS) {
+
+        cy_stc_smif_mem_config_t *cfg = smifBlockConfig_sfdp.memConfig[0];
+        /* Determine row start address, where image trailer is allocated */
+        uint32_t erase_len = cfg->deviceCfg->eraseSize;
+        uint32_t row_mask = erase_len /* is a power of two */ - 1u;
+        uint32_t row_addr = (address - CY_XIP_BASE) & ~row_mask;
+        /* Determine start address of image trailer
+         * The minimum erase size area is allocated
+         * for trailer, but reading the whole area is
+         * not nessesary since data is only located at
+         * first 0x200 bytes. Trailer size is taken as 0x200
+         * to keep consistency with internal memory
+         * implementation, where min_erase_size is 0x200
+         */
+        uint32_t img_trailer_addr = address - CY_XIP_BASE + USER_SWAP_IMAGE_OK_OFFS - IMG_TRAILER_SZ;
+        uint32_t img_ok_mask = FLASH_ROW_BUF_SZ /* is a power of 2 */ - 1u; 
+
+        cy_en_smif_status_t st = Cy_SMIF_MemRead(QSPIPort, cfg,
+                                                img_trailer_addr, row_buff, FLASH_ROW_BUF_SZ,
+                                                &QSPI_context);
+
+        if (CY_SMIF_SUCCESS == st) {
+            
+            if (row_buff[address & img_ok_mask] != value) {
+                
+                row_buff[address & img_ok_mask] = value;
+
+                /* Programming the updated block back */
+                st = Cy_SMIF_MemEraseSector(QSPIPort, cfg,
+                                            row_addr, erase_len,
+                                            &QSPI_context);
+
+                if (CY_SMIF_SUCCESS == st) {
+                    st = Cy_SMIF_MemWrite(QSPIPort, cfg,
+                                            img_trailer_addr, row_buff, FLASH_ROW_BUF_SZ,
+                                            &QSPI_context);
+                    if (CY_SMIF_SUCCESS == st) {
+                        rc = IMG_OK_SET_SUCCESS;
+                    }
+                }
+                else {
+                    rc = IMG_OK_SET_FAILED;
+                }
+            }
+            else {
+                rc = IMG_OK_ALREADY_SET;
+            }
+        }
+        else {
+            rc = IMG_OK_SET_FAILED;
+        }
+
+        stat = Cy_SMIF_CacheEnable(QSPIPort, CY_SMIF_CACHE_FAST);
+
+        if (CY_SMIF_SUCCESS == stat) {
+            Cy_SMIF_SetMode(QSPIPort, CY_SMIF_MEMORY);
+            mode = Cy_SMIF_GetMode(QSPIPort);
+
+            if (mode != CY_SMIF_MEMORY) {
+                CY_HALT();
+            }
+        }
+    }
+    else {
+        /* do nothing */
+    }
+
+    return rc;
+}
+CY_RAMFUNC_END
+
+#endif /* USE_XIP */
+
+/**
+ * @brief Public function to confirm that upgraded application is operable
+ * after swap. Should be called from main code of user application. 
+ * It sets mcuboot flag img_ok in primary (boot) image trailer.
+ * MCUBootApp checks img_ok flag at first reset after upgrade and
+ * validates successful swap.
+ * 
+ * @param address - address of img_ok flag in primary img trailer
+ * @param value - value corresponding to img_ok set
+ * 
+ * @return - operation status. 1 - already set, 0 - set succesfully,
+ *                              -1 - failed to set.
+ */
+int set_img_ok(uint32_t address, uint8_t value)
+{
+    int32_t rc = -1;
+
+    /* Write Image OK flag to the slot trailer, so MCUBoot-loader
+     * will not revert new image
+     */
+#ifdef USE_XIP
+    /*
+     * When switching from XIP execution mode to RAM function
+     * it is required to clear and disable SMIF cache. set_img_ok_ram
+     * is then turns cache on before return. If it is not done - return
+     * to execution from RAM to XIP hangs indefinitely.
+     */
+    Cy_SMIF_CacheDisable(SMIF0, CY_SMIF_CACHE_FAST);
+    Cy_SMIF_CacheInvalidate(SMIF0, CY_SMIF_CACHE_FAST);
+    rc = set_img_ok_ram(address, value);
+
+#else
+    Cy_Flash_Init();
+    Cy_Flashc_MainWriteEnable();
+
+    if (read_img_ok_value(address) != value) {
+        rc = write_img_ok_value(address, value);
+    }
+    else {
+        rc = IMG_OK_ALREADY_SET;
+    }
+#endif /* USE_XIP */
+
+    return rc;
+}
+
+#endif /* !(SWAP_DISABLED) && defined(UPGRADE_IMAGE) */
diff --git a/boot/cypress/platforms/img_confirm/set_img_ok.h b/boot/cypress/platforms/img_confirm/set_img_ok.h
index 60f98e8..ee9f424 100644
--- a/boot/cypress/platforms/img_confirm/set_img_ok.h
+++ b/boot/cypress/platforms/img_confirm/set_img_ok.h
@@ -22,11 +22,10 @@
 #if defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829)
 #include "flash_qspi.h"
 #endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829) */
-#include "sysflash/sysflash.h"
 #include <string.h>
 
-#define FLASH_ROW_BUF_SZ        CY_FLASH_ALIGN
-#define IMG_TRAILER_SZ          CY_FLASH_ALIGN
+#define FLASH_ROW_BUF_SZ        MEMORY_ALIGN
+#define IMG_TRAILER_SZ          MEMORY_ALIGN
 
 #define USER_SWAP_IMAGE_OK_OFFS (24)
 #define USER_SWAP_IMAGE_OK      (1)
@@ -38,4 +37,4 @@
 
 int set_img_ok(uint32_t address, uint8_t value);
 
-#endif /* SET_IMG_OK_H */
\ No newline at end of file
+#endif /* SET_IMG_OK_H */
diff --git a/boot/cypress/platforms/memory/CYW20829/flash_map_backend_platform.h b/boot/cypress/platforms/memory/CYW20829/flash_map_backend_platform.h
new file mode 100644
index 0000000..dc6010e
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW20829/flash_map_backend_platform.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2015 Runtime Inc
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ /*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+ /*******************************************************************************/
+
+#ifndef FLASH_MAP_BACKEND_PLATFORM_H
+#define FLASH_MAP_BACKEND_PLATFORM_H
+
+#include "bootutil/image.h"
+#include "flash_map_backend/flash_map_backend.h"
+
+#include <assert.h>
+
+#define FLASH_DEVICE_INDEX_MASK                 (0x7Fu)
+#define FLASH_DEVICE_GET_EXT_INDEX(n)           ((n) & FLASH_DEVICE_INDEX_MASK)
+#define FLASH_DEVICE_UNDEFINED                  (0x00u)
+#define FLASH_DEVICE_EXTERNAL_FLAG              (0x80u)
+#define FLASH_DEVICE_INTERNAL_FLASH             (0x7Fu)
+#define FLASH_DEVICE_EXTERNAL_FLASH(index)      (FLASH_DEVICE_EXTERNAL_FLAG | (index) )
+
+#ifndef CY_BOOT_EXTERNAL_DEVICE_INDEX
+/* assume first(one) SMIF device is used */
+#define CY_BOOT_EXTERNAL_DEVICE_INDEX           (0u)
+
+#ifndef SMIF_MEM_START_PLATFORM
+#define SMIF_MEM_START_PLATFORM                 (CY_XIP_BASE)
+#endif /* SMIF_MEM_START_PLATFORM */
+#endif
+
+#ifndef EXTERNAL_MEMORY_ERASE_VALUE_PLATFORM
+/* This is the value of external flash bytes after an erase */
+#define EXTERNAL_MEMORY_ERASE_VALUE_PLATFORM    (0xFFu)
+#endif /* INTERNAL_MEMORY_ERASE_VALUE_PLATFORM */
+
+static inline const struct flash_area_interface* flash_area_get_api(uint8_t fd_id)
+{
+    assert((fd_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG);
+    (void)fd_id;
+
+    extern const struct flash_area_interface external_mem_interface;
+    return &external_mem_interface;
+}
+
+#endif /* FLASH_MAP_BACKEND_PLATFORM_H */
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/cy_smif_hybrid_sect.c b/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.c
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/cy_smif_hybrid_sect.c
rename to boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.c
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/cy_smif_hybrid_sect.h b/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.h
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/cy_smif_hybrid_sect.h
rename to boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.h
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.c b/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.c
similarity index 98%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.c
rename to boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.c
index 9933ff6..120aab4 100644
--- a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.c
+++ b/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.c
@@ -72,6 +72,7 @@
 
 #include "flash_qspi.h"
 #include "cy_smif_hybrid_sect.h"
+#include "flash_map_backend_platform.h"
 
 #define CY_SMIF_SYSCLK_HFCLK_DIVIDER     CY_SYSCLK_CLKHF_DIVIDE_BY_2
 
@@ -547,6 +548,11 @@
     return stat;
 }
 
+uint8_t qspi_get_erased_val(void) 
+{
+    return EXTERNAL_MEMORY_ERASE_VALUE_PLATFORM;
+}
+
 uint32_t qspi_get_prog_size(void)
 {
     cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.h b/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.h
similarity index 98%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.h
rename to boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.h
index e8c4953..5ce3fd0 100644
--- a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.h
+++ b/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.h
@@ -59,7 +59,7 @@
 cy_en_smif_status_t qspi_init(cy_stc_smif_block_config_t *blk_config);
 cy_en_smif_status_t qspi_init_hardware(void);
 void qspi_deinit(uint32_t smif_id);
-
+uint8_t qspi_get_erased_val(void);
 uint32_t qspi_get_prog_size(void);
 uint32_t qspi_get_erase_size(void);
 uint32_t qspi_get_mem_size(void);
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_multi2.json b/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_overwrite_multi2.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_multi2.json
rename to boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_overwrite_multi2.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_single.json b/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_overwrite_single.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_single.json
rename to boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_overwrite_single.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_multi2.json b/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_multi2.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_multi2.json
rename to boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_multi2.json
diff --git a/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_shared.json b/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_shared.json
new file mode 100644
index 0000000..40593c3
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_shared.json
@@ -0,0 +1,81 @@
+{
+    "external_flash": [
+        {
+            "model": "FM25W04",
+            "mode": "XIP"
+        }
+    ],
+    "boot_and_upgrade":
+    {
+        "bootloader": {
+            "address": {
+                "description": "Address of the bootloader",
+                "value": "0x60000000"
+            },
+            "size": {
+                "description": "Size of the bootloader",
+                "value": "0x20000"
+            },
+            "scratch_address": {
+                "description": "Address of the scratch area",
+                "value": "0x6007E000"
+            },
+            "scratch_size": {
+                "description": "Size of the scratch area",
+                "value": "0x2000"
+            },
+            "status_address": {
+                "description": "Address of the swap status partition",
+                "value": "0x6005C000"
+            },
+            "status_size": {
+                "description": "Size of the swap status partition",
+                "value": "0x1C000"
+            }
+        },
+        "application_1": {
+            "address": {
+                "description": "Address of the application primary slot",
+                "value": "0x60020000"
+            },
+            "size": {
+                "description": "Size of the application primary slot",
+                "value": "0x10000"
+            },
+            "shared_slot": {
+                "description": "Using shared secondary slot",
+                "value": true
+            },
+            "upgrade_address": {
+                "description": "Address of the application secondary slot",
+                "value": "0x60040000"
+            },
+            "upgrade_size": {
+                "description": "Size of the application secondary slot",
+                "value": "0x10000"
+            }
+        },
+        "application_2": {
+            "address": {
+                "description": "Address of the application primary slot",
+                "value": "0x60030000"
+            },
+            "size": {
+                "description": "Size of the application primary slot",
+                "value": "0x10000"
+            },
+            "shared_slot": {
+                "description": "Using shared secondary slot",
+                "value": true
+            },
+            "upgrade_address": {
+                "description": "Address of the application secondary slot",
+                "value": "0x60041000"
+            },
+            "upgrade_size": {
+                "description": "Size of the application secondary slot",
+                "value": "0x10000"
+            }
+        }
+    }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_single.json b/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_single.json
rename to boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json b/boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json
rename to boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json b/boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
rename to boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json b/boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json
rename to boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json b/boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
rename to boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
diff --git a/boot/cypress/platforms/memory/PSOC6/flash_map_backend_platform.h b/boot/cypress/platforms/memory/PSOC6/flash_map_backend_platform.h
new file mode 100644
index 0000000..bdfedbd
--- /dev/null
+++ b/boot/cypress/platforms/memory/PSOC6/flash_map_backend_platform.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2015 Runtime Inc
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ /*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+ /*******************************************************************************/
+
+#ifndef FLASH_MAP_BACKEND_PLATFORM_H
+#define FLASH_MAP_BACKEND_PLATFORM_H
+
+#include "flash_map_backend/flash_map_backend.h"
+
+#include <assert.h>
+
+#define FLASH_DEVICE_INDEX_MASK                 (0x7Fu)
+#define FLASH_DEVICE_GET_EXT_INDEX(n)           ((n) & FLASH_DEVICE_INDEX_MASK)
+#define FLASH_DEVICE_UNDEFINED                  (0x00u)
+#define FLASH_DEVICE_EXTERNAL_FLAG              (0x80u)
+#define FLASH_DEVICE_INTERNAL_FLASH             (0x7Fu)
+#define FLASH_DEVICE_EXTERNAL_FLASH(index)      (FLASH_DEVICE_EXTERNAL_FLAG | index)
+
+#ifndef CY_BOOT_EXTERNAL_DEVICE_INDEX
+/* assume first(one) SMIF device is used */
+#define CY_BOOT_EXTERNAL_DEVICE_INDEX           (0u)
+#endif
+
+#ifndef INTERNAL_MEMORY_ERASE_VALUE_PLATFORM
+/* This is the value of internal flash bytes after an erase */
+#define INTERNAL_MEMORY_ERASE_VALUE_PLATFORM  (0x00u)
+#endif /* INTERNAL_MEMORY_ERASE_VALUE_PLATFORM */
+
+#ifndef INTERNAL_MEMORY_ERASE_SIZE_PLATFORM
+#define INTERNAL_MEMORY_ERASE_SIZE_PLATFORM     (0x200u)
+#endif /* INTERNAL_MEMORY_ERASE_SIZE_PLATFORM */
+
+#if defined CY_BOOT_USE_EXTERNAL_FLASH
+
+#ifndef EXTERNAL_MEMORY_ERASE_VALUE_PLATFORM
+#define EXTERNAL_MEMORY_ERASE_VALUE_PLATFORM     (0xFFu)
+#endif /* EXTERNAL_MEMORY_ERASE_VALUE_PLATFORM */
+
+#ifndef EXTERNAL_MEMORY_ERASE_SIZE_PLATFORM
+#define EXTERNAL_MEMORY_ERASE_SIZE_PLATFORM     (0x40000u)
+#endif /* EXTERNAL_MEMORY_ERASE_SIZE_PLATFORM */
+
+#ifndef SMIF_MEM_START_PLATFORM
+#define SMIF_MEM_START_PLATFORM                 (CY_XIP_BASE)
+#endif /* SMIF_MEM_START_PLATFORM */
+
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+
+static inline const struct flash_area_interface* flash_area_get_api(uint8_t fd_id)
+{
+    if (FLASH_DEVICE_INTERNAL_FLASH == fd_id) {
+        extern const struct flash_area_interface internal_mem_interface;
+        return &internal_mem_interface;
+    }
+
+#if defined CY_BOOT_USE_EXTERNAL_FLASH
+    if ((fd_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+        extern const struct flash_area_interface external_mem_interface;
+        return &external_mem_interface;
+    }
+#endif
+
+    assert(false);
+    return NULL;
+}
+
+#endif /* FLASH_MAP_BACKEND_PLATFORM_H */
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c
similarity index 98%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
rename to boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c
index 5718bf5..0f33265 100644
--- a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
+++ b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c
@@ -67,6 +67,8 @@
 #include <stdio.h>
 #include "flash_qspi.h"
 
+#include "flash_map_backend_platform.h"
+
 #define CY_SMIF_SYSCLK_HFCLK_DIVIDER     CY_SYSCLK_CLKHF_DIVIDE_BY_2
 
 #define CY_SMIF_INIT_TRY_COUNT           (10U)
@@ -222,7 +224,7 @@
     .blockEvent = (uint32_t)CY_SMIF_BUS_ERROR
 };
 
-#ifdef CM0P
+#ifdef BOOT_CM0P
 static cy_stc_sysint_t smifIntConfig =
 {/* ATTENTION: make sure proper Interrupts configured for CM0p or M4 cores */
 #if (CY_CPU_CORTEX_M0P)
@@ -333,7 +335,7 @@
     .vohSel = 0UL,
 };
 
-#ifdef CM0P
+#ifdef BOOT_CM0P
 static void Isr_SMIF(void)
 {
     Cy_SMIF_Interrupt(QSPIPort, &QSPI_context);
@@ -368,7 +370,7 @@
      * Setup the interrupt for the SMIF block.  For the CM0 there
      * is a two stage process to setup the interrupts.
      */
-#ifdef CM0P
+#ifdef BOOT_CM0P
     (void)Cy_SysInt_Init(&smifIntConfig, Isr_SMIF);
 #endif
 
@@ -381,7 +383,7 @@
     /* Set the polling delay in micro seconds to check memory device availability */
     Cy_SMIF_SetReadyPollingDelay(CY_CHECK_MEMORY_AVAILABILITY_DELAY_US, &QSPI_context);
 
-#ifdef CM0P
+#ifdef BOOT_CM0P
     NVIC_EnableIRQ(smifIntConfig.intrSrc); /* Finally, Enable the SMIF interrupt */
 #endif
 
@@ -474,6 +476,11 @@
     return stat;
 }
 
+uint8_t qspi_get_erased_val(void) 
+{
+    return EXTERNAL_MEMORY_ERASE_VALUE_PLATFORM;
+}
+
 uint32_t qspi_get_prog_size(void)
 {
     cy_stc_smif_mem_config_t **memCfg = smifBlockConfig_sfdp.memConfig;
@@ -500,7 +507,7 @@
 
     (void)Cy_SysClk_ClkHfDisable(CY_SYSCLK_CLKHF_IN_CLKPATH2);
 
-#ifdef CM0P
+#ifdef BOOT_CM0P
     NVIC_DisableIRQ(smifIntConfig.intrSrc);
     Cy_SysInt_DisconnectInterruptSource(smifIntConfig.intrSrc, smifIntConfig.cm0pSrc);
 #endif
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.h
similarity index 98%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
rename to boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.h
index ff42980..26ffd72 100644
--- a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
+++ b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.h
@@ -58,6 +58,8 @@
 cy_en_smif_status_t qspi_init_sfdp(uint32_t smif_id);
 cy_en_smif_status_t qspi_init(cy_stc_smif_block_config_t *blk_config);
 cy_en_smif_status_t qspi_init_hardware(void);
+void qspi_deinit(uint32_t smif_id);
+uint8_t qspi_get_erased_val(void);
 uint32_t qspi_get_prog_size(void);
 uint32_t qspi_get_erase_size(void);
 uint32_t qspi_get_mem_size(void);
@@ -66,8 +68,6 @@
 cy_stc_smif_context_t *qspi_get_context(void);
 cy_stc_smif_mem_config_t *qspi_get_memory_config(uint8_t index);
 
-void qspi_deinit(uint32_t smif_id);
-
 void qspi_set_mode(cy_en_smif_mode_t mode);
 cy_en_smif_mode_t qspi_get_mode(void);
 
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_overwrite_multi.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_overwrite_multi.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi_smif.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_overwrite_multi_smif.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi_smif.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_overwrite_multi_smif.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_overwrite_single.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_overwrite_single.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single_smif.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_overwrite_single_smif.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single_smif.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_overwrite_single_smif.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_multi.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_multi.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_multi.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_multi.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_multi_smif.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_multi_smif.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_multi_smif.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_multi_smif.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_shared.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_shared.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_shared.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_shared.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_single.json
similarity index 92%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_single.json
index ca0f119..e801ee0 100644
--- a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json
+++ b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_single.json
@@ -8,11 +8,11 @@
             },
             "size": {
                 "description": "Size of the bootloader",
-                "value": "0x18000"
+                "value": "0x28000"
             },
             "scratch_address": {
                 "description": "Address of the scratch area",
-                "value": "0x10040000"
+                "value": "0x10050000"
             },
             "scratch_size": {
                 "description": "Size of the scratch area",
@@ -20,7 +20,7 @@
             },
             "status_address": {
                 "description": "Address of the swap status partition",
-                "value": "0x10038000"
+                "value": "0x10048000"
             },
             "status_size": {
                 "description": "Size of the swap status partition",
@@ -30,7 +30,7 @@
         "application_1": {
             "address": {
                 "description": "Address of the application primary slot",
-                "value": "0x10018000"
+                "value": "0x10028000"
             },
             "size": {
                 "description": "Size of the application primary slot",
@@ -38,7 +38,7 @@
             },
             "upgrade_address": {
                 "description": "Address of the application secondary slot",
-                "value": "0x10028000"
+                "value": "0x10038000"
             },
             "upgrade_size": {
                 "description": "Size of the application secondary slot",
@@ -46,4 +46,4 @@
             }
         }
     }
-}
\ No newline at end of file
+}
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_cm0p.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_single_cm0p.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_cm0p.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_single_cm0p.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_single_smif.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_swap_single_smif.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_overwrite.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_xip_overwrite.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_overwrite.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_xip_overwrite.json
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_swap.json b/boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_xip_swap.json
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_swap.json
rename to boot/cypress/platforms/memory/PSOC6/flashmap/psoc6_xip_swap.json
diff --git a/boot/cypress/platforms/memory/PSOC6/internal_memory.c b/boot/cypress/platforms/memory/PSOC6/internal_memory.c
new file mode 100644
index 0000000..a207a3a
--- /dev/null
+++ b/boot/cypress/platforms/memory/PSOC6/internal_memory.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2022 Infineon Technologies AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include "bootutil/bootutil.h"
+#include "cy_flash.h"
+#include <stdint.h>
+
+#include "flash_map_backend_platform.h"
+
+static uint32_t get_base_address(uint8_t fa_device_id)
+{
+    uint32_t res = 0;
+
+    if (FLASH_DEVICE_INTERNAL_FLASH == fa_device_id) {
+        res = CY_FLASH_BASE;
+    }
+#ifdef CY_BOOT_USE_EXTERNAL_FLASH
+    else if ((fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+        res = CY_XIP_BASE;
+    }
+#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+    else {
+        res = 0U;
+    }
+
+    return res;
+}
+
+static uint32_t get_min_erase_size(uint8_t fa_device_id)
+{
+    (void) fa_device_id;
+
+    return INTERNAL_MEMORY_ERASE_SIZE_PLATFORM;
+}
+
+static uint8_t get_erase_val(uint8_t fa_device_id)
+{
+    (void) fa_device_id;
+
+    return INTERNAL_MEMORY_ERASE_VALUE_PLATFORM;
+}
+
+/*
+ * Reads `len` bytes of flash memory at `off` to the buffer at `dst`
+ */
+static int read(uint8_t fa_device_id, uintptr_t addr, void *dst, uint32_t len)
+{
+    (void) fa_device_id;
+
+    int rc = -1;
+    void* src;
+    void * result = NULL;
+
+    /* Convert from uintptr_t to void*, MISRA C 11.6 */
+    (void)memcpy((void *)&src, (void const *)&addr, sizeof(void*));
+    /* flash read by simple memory copying */
+    result = memcpy(dst, src, (size_t)len);
+    if (result == dst) {
+        rc = 0;
+    }
+
+    return rc;
+}
+
+/*
+ * Writes `len` bytes of flash memory at `off` from the buffer at `src`
+ */
+static int write(uint8_t fa_device_id, uintptr_t addr, const void *src, uint32_t len)
+{
+    (void) fa_device_id;
+
+    int rc = BOOT_EFLASH;
+    uintptr_t write_end_addr = 0u;
+    const uint32_t * row_ptr = NULL;
+    uint32_t row_number = 0u;
+    uint32_t row_addr = 0u;
+
+    if (src != NULL) {
+
+        write_end_addr = addr + len;
+
+        if (len % CY_FLASH_SIZEOF_ROW != 0u) {
+            rc = BOOT_EBADARGS;
+        }
+        else if (addr % CY_FLASH_SIZEOF_ROW != 0u) {
+            rc = BOOT_EBADARGS;
+        }
+        else {
+            /* do nothing */
+        }
+        if (rc != BOOT_EBADARGS) {
+
+            row_number = (write_end_addr - addr) / CY_FLASH_SIZEOF_ROW;
+            row_addr = addr;
+
+            row_ptr = (const uint32_t *) src;
+
+            for (uint32_t i = 0; i < row_number; i++) {
+                if (Cy_Flash_WriteRow(row_addr, row_ptr) != CY_FLASH_DRV_SUCCESS) {
+                    rc = BOOT_EFLASH;
+                    break;
+                }
+                else {
+                    rc = 0;
+                }
+
+                row_addr += (uint32_t) CY_FLASH_SIZEOF_ROW;
+                row_ptr = row_ptr + CY_FLASH_SIZEOF_ROW / 4U;
+            }
+
+        }
+    }
+
+    return rc;
+}
+
+/*< Erases `len` bytes of flash memory at `off` */
+static int erase(uint8_t fa_device_id, uintptr_t addr, uint32_t len)
+{
+    (void) fa_device_id;
+
+    int rc = -1;
+    uintptr_t erase_end_addr = 0u;
+    uint32_t row_number = 0u;
+    uint32_t row_addr = 0u;
+
+    erase_end_addr = addr + len;
+    uint32_t row_start_addr = (addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;
+    uint32_t row_end_addr = (erase_end_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;
+
+    /* assume single row needs to be erased */
+    if (row_start_addr == row_end_addr) {
+        if (Cy_Flash_EraseRow(row_start_addr) != CY_FLASH_DRV_SUCCESS) {
+            rc = BOOT_EFLASH;
+        }
+        else {
+            rc = 0;
+        }
+    }
+    else {
+        row_number = (row_end_addr - row_start_addr) / CY_FLASH_SIZEOF_ROW;
+
+        while (row_number != 0u) {
+            row_number--;
+            row_addr = row_start_addr + row_number * (uint32_t) CY_FLASH_SIZEOF_ROW;
+            if (Cy_Flash_EraseRow(row_addr) != CY_FLASH_DRV_SUCCESS) {
+                rc = BOOT_EFLASH;
+                break;
+            }
+            else {
+                rc = 0;
+            }
+        }
+    }
+
+    return rc;
+}
+
+static int open(uint8_t fa_device_id)
+{
+    (void) fa_device_id;
+
+    return 0;
+}
+
+static void close(uint8_t fa_device_id)
+{
+    (void) fa_device_id;
+}
+
+const struct flash_area_interface internal_mem_interface = {
+    .open             = &open,
+    .close            = &close,
+    .read             = &read,
+    .write            = &write,
+    .erase            = &erase,
+    .get_erase_val    = &get_erase_val,
+    .get_erase_size   = &get_min_erase_size,
+    .get_base_address = &get_base_address};
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c b/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.c
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
rename to boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.c
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.h b/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.h
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.h
rename to boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.h
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/qspi_config.cfg b/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/qspi_config.cfg
similarity index 100%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/qspi_config.cfg
rename to boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/qspi_config.cfg
diff --git a/boot/cypress/platforms/memory/XMC7000/flash_map_backend_platform.h b/boot/cypress/platforms/memory/XMC7000/flash_map_backend_platform.h
new file mode 100644
index 0000000..b6f601b
--- /dev/null
+++ b/boot/cypress/platforms/memory/XMC7000/flash_map_backend_platform.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2015 Runtime Inc
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+/*******************************************************************************/
+
+#ifndef FLASH_MAP_BACKEND_PLATFORM_H
+#define FLASH_MAP_BACKEND_PLATFORM_H
+
+#include <assert.h>
+
+#include "cy_flash.h"
+#include "flash_map_backend/flash_map_backend.h"
+#include "memorymap.h"
+
+static inline const struct flash_area_interface* flash_area_get_api(uint8_t fd_id)
+{
+    extern const struct flash_area_interface internal_mem_interface;
+    extern const struct flash_area_interface internal_mem_eeprom_interface;
+
+    const struct flash_area_interface* interface = NULL;
+
+    switch (fd_id) {
+        case INTERNAL_FLASH_CODE_LARGE:
+        case INTERNAL_FLASH_CODE_SMALL:
+            interface = &internal_mem_interface;
+            break;
+
+        case INTERNAL_FLASH_WORK_LARGE:
+        case INTERNAL_FLASH_WORK_SMALL:
+            interface = &internal_mem_eeprom_interface;
+            break;
+
+        default:
+            assert(false);
+            interface = NULL;
+            break;
+    }
+
+    return interface;
+}
+
+#endif /* FLASH_MAP_BACKEND_PLATFORM_H */
diff --git a/boot/cypress/platforms/memory/XMC7000/flashmap/platform.json b/boot/cypress/platforms/memory/XMC7000/flashmap/platform.json
new file mode 100644
index 0000000..f768d1c
--- /dev/null
+++ b/boot/cypress/platforms/memory/XMC7000/flashmap/platform.json
@@ -0,0 +1,50 @@
+{
+    "memory_regions":
+    [
+        {
+            "address"       : "0x10000000",
+            "size"          : "0x7F0000",
+            "erase_size"    : "0x8000",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_CODE_LARGE"
+        },
+
+        {
+            "address"       : "0x107F0000",
+            "size"          : "0x40000",
+            "erase_size"    : "0x2000",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_CODE_SMALL"
+        },
+
+        {
+            "address"       : "0x14000000",
+            "size"          : "0x30000",
+            "erase_size"    : "0x800",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_WORK_LARGE"
+        },
+
+        {
+            "address"       : "0x14030000",
+            "size"          : "0x30000",
+            "erase_size"    : "0x80",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_WORK_SMALL"
+        }
+    ],
+
+    "core_list":
+    [
+        {
+            "name"      : "CM0",
+            "id"        : 0
+        },
+
+        {
+            "name"      : "CM4",
+            "id"        : 1
+        }
+    ]
+
+}
diff --git a/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json
new file mode 100644
index 0000000..fa2033f
--- /dev/null
+++ b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json
@@ -0,0 +1,19 @@
+{
+    "bootloader":
+    {
+        "bootloader_area":
+        {
+            "address"           : "0x10000000",
+            "size"              : "0x20000"
+        }
+    },
+    "application_1":
+    {
+        "slots":
+        {
+            "boot"              : "0x10020000",
+            "upgrade"           : "0x10040000",
+            "size"              : "0x20000"
+        }
+    }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7000_swap_single.json b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7000_swap_single.json
new file mode 100644
index 0000000..45530d6
--- /dev/null
+++ b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7000_swap_single.json
@@ -0,0 +1,31 @@
+{
+    "bootloader":
+    {
+        "bootloader_area":
+        {
+            "address"           : "0x10000000",
+            "size"              : "0x20000"
+        },
+
+        "status_area":
+        {
+            "address"           : "0x14030000",
+            "size"              : "0x2800"
+        },
+
+        "scratch_area":
+        {
+            "address"           : "0x14000000",
+            "size"              : "0x8000"
+        }
+    },
+    "application_1":
+    {
+        "slots":
+        {
+            "boot"              : "0x10020000",
+            "upgrade"           : "0x10040000",
+            "size"              : "0x20000"
+        }
+    }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7100_platform.json b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7100_platform.json
new file mode 100644
index 0000000..047bd37
--- /dev/null
+++ b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7100_platform.json
@@ -0,0 +1,55 @@
+{
+    "memory_regions":
+    [
+        {
+            "address"       : "0x10000000",
+            "size"          : "0x3F0000",
+            "erase_size"    : "0x8000",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_CODE_LARGE"
+        },
+
+        {
+            "address"       : "0x107F0000",
+            "size"          : "0x20000",
+            "erase_size"    : "0x2000",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_CODE_SMALL"
+        },
+
+        {
+            "address"       : "0x14000000",
+            "size"          : "0x30000",
+            "erase_size"    : "0x800",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_WORK_LARGE"
+        },
+
+        {
+            "address"       : "0x14030000",
+            "size"          : "0x10000",
+            "erase_size"    : "0x80",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_WORK_SMALL"
+        }
+    ],
+
+    "core_list":
+    [
+        {
+            "name"      : "CM0P",
+            "id"        : 0
+        },
+
+        {
+            "name"      : "CM7_0",
+            "id"        : 1
+        },
+
+        {
+            "name"      : "CM7_1",
+            "id"        : 2
+        }
+    ]
+
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7200_platform.json b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7200_platform.json
new file mode 100644
index 0000000..6fbbc0e
--- /dev/null
+++ b/boot/cypress/platforms/memory/XMC7000/flashmap/xmc7200_platform.json
@@ -0,0 +1,55 @@
+{
+    "memory_regions":
+    [
+        {
+            "address"       : "0x10000000",
+            "size"          : "0x7F0000",
+            "erase_size"    : "0x8000",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_CODE_LARGE"
+        },
+
+        {
+            "address"       : "0x107F0000",
+            "size"          : "0x40000",
+            "erase_size"    : "0x2000",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_CODE_SMALL"
+        },
+
+        {
+            "address"       : "0x14000000",
+            "size"          : "0x30000",
+            "erase_size"    : "0x800",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_WORK_LARGE"
+        },
+
+        {
+            "address"       : "0x14030000",
+            "size"          : "0x10000",
+            "erase_size"    : "0x80",
+            "erase_value"   : "0xFF",
+            "type"          : "INTERNAL_FLASH_WORK_SMALL"
+        }
+    ],
+
+    "core_list":
+    [
+        {
+            "name"      : "CM0P",
+            "id"        : 0
+        },
+
+        {
+            "name"      : "CM7_0",
+            "id"        : 1
+        },
+
+        {
+            "name"      : "CM7_1",
+            "id"        : 2
+        }
+    ]
+
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c b/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c
new file mode 100644
index 0000000..f5fa320
--- /dev/null
+++ b/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2022 Infineon Technologies AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <stdint.h>
+
+#include "bootutil/bootutil.h"
+#include "cy_flash.h"
+#include "flash_map_backend_platform.h"
+
+static int erase(uint8_t fa_device_id, uintptr_t addr, uint32_t len);
+
+static uint32_t get_min_erase_size(uint8_t fa_device_id)
+{
+    return flash_devices[fa_device_id].erase_size;
+}
+
+static uint8_t get_erase_val(uint8_t fa_device_id)
+{
+    return flash_devices[fa_device_id].erase_val;
+}
+
+static inline uint32_t get_base_address(uint8_t fa_device_id)
+{
+    return flash_devices[fa_device_id].address;
+}
+
+/*
+ * Reads `len` bytes of flash memory at `off` to the buffer at `dst`
+ */
+static int read(uint8_t fa_device_id, uintptr_t addr, void *dst, uint32_t len)
+{
+    (void)fa_device_id;
+
+    int rc = -1;
+    void *src;
+    void *result = NULL;
+
+    /* Convert from uintptr_t to void*, MISRA C 11.6 */
+    (void)memcpy((void *)&src, (void const *)&addr, sizeof(void *));
+    /* flash read by simple memory copying */
+    result = memcpy(dst, src, (size_t)len);
+    if (result == dst) {
+        rc = 0;
+    }
+
+    return rc;
+}
+
+/*
+ * Writes `len` bytes of flash memory at `off` from the buffer at `src`
+ */
+static int write(uint8_t fa_device_id, uintptr_t addr, const void *src,
+                 uint32_t len)
+{
+    (void)fa_device_id;
+
+    int rc                   = BOOT_EFLASH;
+    uintptr_t write_end_addr = 0u;
+    const uint32_t *row_ptr  = NULL;
+    uint32_t row_number      = 0u;
+    uint32_t row_addr        = 0u;
+    uint32_t write_sz        = CY_FLASH_SIZEOF_ROW;
+
+    if (src != NULL) {
+        write_end_addr = addr + len;
+
+        if (len % write_sz != 0u) {
+            rc = BOOT_EBADARGS;
+        } else if (addr % write_sz != 0u) {
+            rc = BOOT_EBADARGS;
+        } else {
+            /* do nothing */
+        }
+        if (rc != BOOT_EBADARGS) {
+            row_number = (write_end_addr - addr) / write_sz;
+            row_addr   = addr;
+
+            row_ptr = (const uint32_t *)src;
+
+            for (uint32_t i = 0; i < row_number; i++) {
+                if (Cy_Flash_ProgramRow(row_addr, row_ptr) !=
+                    CY_FLASH_DRV_SUCCESS) {
+                    rc = BOOT_EFLASH;
+                    break;
+                } else {
+                    rc = 0;
+                }
+                row_addr += (uint32_t)write_sz;
+                row_ptr = row_ptr + write_sz / 4U;
+            }
+        }
+    }
+
+    return rc;
+}
+
+/*< Erases `len` bytes of flash memory at `off` */
+static int erase(uint8_t fa_device_id, uintptr_t addr, uint32_t len)
+{
+    int rc                   = -1;
+    uint32_t row_addr        = 0u;
+    uint32_t erase_sz        = flash_devices[fa_device_id].erase_size;
+    uintptr_t erase_end_addr = addr + len;
+    uint32_t row_start_addr  = (addr / erase_sz) * erase_sz;
+    uint32_t row_end_addr    = (erase_end_addr / erase_sz) * erase_sz;
+    uint32_t row_number      = (row_end_addr - row_start_addr) / erase_sz;
+
+    /* assume single row needs to be erased */
+    if (row_start_addr == row_end_addr) {
+        row_number = 1U;
+    }
+
+    while (row_number != 0u) {
+        row_number--;
+        row_addr = row_start_addr + row_number * (uint32_t)erase_sz;
+        if (Cy_Flash_EraseSector(row_addr) != CY_FLASH_DRV_SUCCESS) {
+            rc = BOOT_EFLASH;
+            break;
+        } else {
+            rc = 0;
+        }
+    }
+
+    return rc;
+}
+
+static int open(uint8_t fa_device_id)
+{
+    (void)fa_device_id;
+
+    Cy_Flashc_MainWriteEnable();
+
+    return 0;
+}
+
+static void close(uint8_t fa_device_id)
+{
+    (void)fa_device_id;
+}
+
+const struct flash_area_interface internal_mem_interface = {
+    .open             = &open,
+    .close            = &close,
+    .read             = &read,
+    .write            = &write,
+    .erase            = &erase,
+    .get_erase_val    = &get_erase_val,
+    .get_erase_size   = &get_min_erase_size,
+    .get_base_address = &get_base_address};
diff --git a/boot/cypress/platforms/memory/XMC7000/internal_memory_work.c b/boot/cypress/platforms/memory/XMC7000/internal_memory_work.c
new file mode 100644
index 0000000..0886985
--- /dev/null
+++ b/boot/cypress/platforms/memory/XMC7000/internal_memory_work.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2022 Infineon Technologies AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <stdint.h>
+
+#include "bootutil/bootutil.h"
+#include "cy_flash.h"
+#include "flash_map_backend_platform.h"
+
+static int erase(uint8_t fa_device_id, uintptr_t addr, uint32_t len);
+static int write(uint8_t fa_device_id, uintptr_t addr, const void *src,
+                 uint32_t len);
+
+static uint32_t get_min_erase_size(uint8_t fa_device_id)
+{
+    return flash_devices[fa_device_id].erase_size;
+}
+
+static uint8_t get_erase_val(uint8_t fa_device_id)
+{
+    return flash_devices[fa_device_id].erase_val;
+}
+
+static inline uint32_t get_base_address(uint8_t fa_device_id)
+{
+    return flash_devices[fa_device_id].address;
+}
+
+/*
+ * Reads `len` bytes of flash memory at `off` to the buffer at `dst`
+ */
+static int read(uint8_t fa_device_id, uintptr_t addr, void *dst, uint32_t len)
+{
+    (void)fa_device_id;
+
+    int rc = -1;
+    void *src;
+    void *result = NULL;
+
+    /* Convert from uintptr_t to void*, MISRA C 11.6 */
+    (void)memcpy((void *)&src, (void const *)&addr, sizeof(void *));
+    /* flash read by simple memory copying */
+    result = memcpy(dst, src, (size_t)len);
+    if (result == dst) {
+        rc = 0;
+    }
+
+    return rc;
+}
+
+/*
+ * Writes `len` bytes of flash memory at `off` from the buffer at `src`
+ */
+static int write(uint8_t fa_device_id, uintptr_t addr, const void *src,
+                 uint32_t len)
+{
+    (void)fa_device_id;
+
+    int rc                   = BOOT_EFLASH;
+    uintptr_t write_end_addr = 0u;
+    const uint32_t *row_ptr  = NULL;
+    uint32_t row_number      = 0u;
+    uint32_t row_addr        = 0u;
+    uint32_t write_sz        = 0x80;
+
+    cy_stc_flash_programrow_config_t cfg = {
+        .blocking = CY_FLASH_PROGRAMROW_BLOCKING,
+        .dataLoc  = CY_FLASH_PROGRAMROW_DATA_LOCATION_SRAM,
+        .intrMask = CY_FLASH_PROGRAMROW_NOT_SET_INTR_MASK,
+        .dataSize = CY_FLASH_PROGRAMROW_DATA_SIZE_1024BIT};
+
+    if (src != NULL) {
+        write_end_addr = addr + len;
+
+        if (len % write_sz != 0u) {
+            rc = BOOT_EBADARGS;
+        } else if (addr % write_sz != 0u) {
+            rc = BOOT_EBADARGS;
+        } else {
+            /* do nothing */
+        }
+        if (rc != BOOT_EBADARGS) {
+            row_number = (write_end_addr - addr) / write_sz;
+            row_addr   = addr;
+
+            row_ptr = (const uint32_t *)src;
+
+            for (uint32_t i = 0; i < row_number; i++) {
+                cfg.destAddr = (const uint32_t *)row_addr;
+                cfg.dataAddr = (const uint32_t *)row_ptr;
+
+                if (Cy_Flash_Program_WorkFlash(&cfg) != CY_FLASH_DRV_SUCCESS) {
+                    rc = BOOT_EFLASH;
+                    break;
+                } else {
+                    rc = 0;
+                }
+                row_addr += (uint32_t)write_sz;
+                row_ptr = row_ptr + write_sz / 4U;
+            }
+        }
+    }
+
+    return rc;
+}
+
+/*< Erases `len` bytes of flash memory at `off` */
+static int erase(uint8_t fa_device_id, uintptr_t addr, uint32_t len)
+{
+    int rc                   = -1;
+    uint32_t row_addr        = 0u;
+    uint32_t erase_sz        = flash_devices[fa_device_id].erase_size;
+    uintptr_t erase_end_addr = addr + len;
+    uint32_t row_start_addr  = (addr / erase_sz) * erase_sz;
+    uint32_t row_end_addr    = (erase_end_addr / erase_sz) * erase_sz;
+    uint32_t row_number      = (row_end_addr - row_start_addr) / erase_sz;
+
+    /* assume single row needs to be erased */
+    if (row_start_addr == row_end_addr) {
+        row_number = 1U;
+    }
+
+    while (row_number != 0u) {
+        row_number--;
+        row_addr = row_start_addr + row_number * (uint32_t)erase_sz;
+        if (Cy_Flash_EraseSector(row_addr) != CY_FLASH_DRV_SUCCESS) {
+            rc = BOOT_EFLASH;
+            break;
+        } else {
+            rc = 0;
+        }
+    }
+
+    return rc;
+}
+
+static int open(uint8_t fa_device_id)
+{
+    (void)fa_device_id;
+
+    Cy_Flashc_WorkWriteEnable();
+
+    return 0;
+}
+
+static void close(uint8_t fa_device_id)
+{
+    (void)fa_device_id;
+}
+
+const struct flash_area_interface internal_mem_eeprom_interface = {
+    .open             = &open,
+    .close            = &close,
+    .read             = &read,
+    .write            = &write,
+    .erase            = &erase,
+    .get_erase_val    = &get_erase_val,
+    .get_erase_size   = &get_min_erase_size,
+    .get_base_address = &get_base_address};
diff --git a/boot/cypress/platforms/memory/cy_flash_map.c b/boot/cypress/platforms/memory/cy_flash_map.c
new file mode 100644
index 0000000..bd57ec0
--- /dev/null
+++ b/boot/cypress/platforms/memory/cy_flash_map.c
@@ -0,0 +1,349 @@
+/*
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2022 Infineon Technologies AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <sysflash/sysflash.h>
+
+#include "bootutil/bootutil_log.h"
+#include "bootutil/bootutil_public.h"
+#include "bootutil/fault_injection_hardening.h" /* for FIH_PANIC */
+#include "cy_flash.h"
+#include "flash_map_backend_platform.h"
+#include "mcuboot_config/mcuboot_config.h"
+#include "memorymap.h"
+
+/*
+ * Macro takes flash API parameters fa, off and len
+ * Checks flash area boundaries considering off and len
+ * Returns absolute address of flash area memory where
+ * operation should execute
+ */
+#define MEM_VALIDATE_AND_GET_ADDRES(fa, off, len, addr, rc)          \
+    uintptr_t mem_base = 0u;                                         \
+    if ((fa) != NULL) {                                              \
+        if ((off) > (fa)->fa_size ||                                 \
+            (len) > (fa)->fa_size ||                                 \
+            (off) + (len) > (fa)->fa_size) {                         \
+            (rc) = BOOT_EBADARGS;                                    \
+        }                                                            \
+        if (flash_area_get_api((fa)->fa_device_id) != NULL) {        \
+            (rc) = flash_device_base((fa)->fa_device_id, &mem_base); \
+            if ((0 == (rc)) && (mem_base != 0u)) {                   \
+                (addr) = mem_base + (fa)->fa_off + (off);            \
+            }                                                        \
+        }                                                            \
+    }
+
+/*
+ * PORTING GUIDE: REQUIRED
+ * Returns device flash start based on supported fd_id
+ */
+int flash_device_base(uint8_t fd_id, uintptr_t *ret)
+{
+    int rc = -1;
+
+    if (ret != NULL) {
+        if (flash_area_get_api(fd_id) != NULL) {
+            *ret = flash_area_get_api(fd_id)->get_base_address(fd_id);
+            rc = 0;
+        }
+    }
+
+    return rc;
+}
+
+/*
+ * PORTING GUIDE: REQUIRED
+ * Opens the area for use. id is one of the `fa_id`s
+ */
+int flash_area_open(uint8_t fa_id, const struct flash_area **fa)
+{
+    int rc = -1;
+    uint32_t i = 0u;
+
+    if (fa != NULL) {
+        while (boot_area_descs[i] != NULL) {
+            if (fa_id == boot_area_descs[i]->fa_id) {
+                *fa = boot_area_descs[i];
+                if (flash_area_get_api((*fa)->fa_device_id) != NULL) {
+                    rc = flash_area_get_api((*fa)->fa_device_id)->open((*fa)->fa_device_id);
+                    break;
+                }
+            }
+            i++;
+        }
+    }
+
+    return rc;
+}
+
+/*
+ * PORTING GUIDE: REQUIRED
+ * Clear pointer to flash area fa
+ */
+void flash_area_close(const struct flash_area *fa)
+{
+    if (fa != NULL) {
+        if (flash_area_get_api(fa->fa_device_id) != NULL) {
+            flash_area_get_api(fa->fa_device_id)->close(fa->fa_device_id);
+        }
+    }
+}
+
+/*
+ * PORTING GUIDE: REQUIRED
+ * Reads `len` bytes of flash memory at `off` to the buffer at `dst`
+ */
+int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
+                    uint32_t len)
+{
+    int rc = -1;
+    uintptr_t addr = 0u;
+
+    MEM_VALIDATE_AND_GET_ADDRES(fa, off, len, addr, rc);
+    if (addr != 0u) {
+        rc = flash_area_get_api(fa->fa_device_id)->read(fa->fa_device_id, addr, dst, len);
+    } else {
+        /* do nothing */
+    }
+
+    return rc;
+}
+
+/*
+ * PORTING GUIDE: REQUIRED
+ * Writes `len` bytes of flash memory at `off` from the buffer at `src`
+ */
+int flash_area_write(const struct flash_area *fa, uint32_t off,
+                     const void *src, uint32_t len)
+{
+    int rc = BOOT_EFLASH;
+    uintptr_t addr = 0u;
+
+    MEM_VALIDATE_AND_GET_ADDRES(fa, off, len, addr, rc);
+    if (addr != 0u) {
+        rc = flash_area_get_api(fa->fa_device_id)->write(fa->fa_device_id, addr, src, len);
+    } else {
+        /* do nothing */
+    }
+
+    return rc;
+}
+
+/*
+ * PORTING GUIDE: REQUIRED
+ * Erases `len` bytes of flash memory at `off`
+ */
+int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
+{
+    int rc = -1;
+    uintptr_t addr = 0u;
+
+    MEM_VALIDATE_AND_GET_ADDRES(fa, off, len, addr, rc);
+    if (addr != 0u) {
+        rc = flash_area_get_api(fa->fa_device_id)->erase(fa->fa_device_id, addr, len);
+    } else {
+        /* do nothing */
+    }
+
+    return rc;
+}
+
+/*
+ * PORTING GUIDE: REQUIRED
+ * Returns this `flash_area`s alignment
+ */
+size_t flash_area_align(const struct flash_area *fa)
+{
+    size_t rc = 0u; /* error code (alignment cannot be zero) */
+
+    if ((fa != NULL) && (flash_area_get_api(fa->fa_device_id) != NULL)) {
+        rc = flash_area_get_api(fa->fa_device_id)->get_erase_size(fa->fa_device_id);
+    }
+
+    return rc;
+}
+
+/*
+ * PORTING GUIDE: REQUIRED
+ * This depends on the mappings defined in sysflash.h.
+ * MCUBoot uses continuous numbering for the primary slot, the secondary slot,
+ * and the scratch while zephyr might number it differently.
+ */
+int flash_area_id_from_multi_image_slot(int image_index, int slot)
+{
+    int rc = -1;
+    if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
+        return -1;
+    }
+
+    switch (slot) {
+        case 0:
+            rc = (int)FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index);
+            break;
+        case 1:
+            rc = (int)FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index);
+            break;
+#ifdef MCUBOOT_SWAP_USING_SCRATCH
+        case 2:
+            rc = (int)FLASH_AREA_IMAGE_SCRATCH;
+            break;
+#endif
+        default:
+            rc = -1; /* flash_area_open will fail on that */
+            break;
+    }
+    return rc;
+}
+
+/* PORTING GUIDE: REQUIRED */
+int flash_area_id_from_image_slot(int slot)
+{
+    return flash_area_id_from_multi_image_slot(0, slot);
+}
+
+/* PORTING GUIDE: REQUIRED */
+int flash_area_id_to_multi_image_slot(int image_index, int area_id)
+{
+    if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
+        return -1;
+    }
+
+    if ((int)FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index) == area_id) {
+        return 0;
+    }
+    if ((int)FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index) == area_id) {
+        return 1;
+    }
+
+    return -1;
+}
+
+/* PORTING GUIDE: NOT REQUIRED
+ * This API is not used in mcuboot common code. It exists, however
+ * to complement flash_area_id_from_image_slot()
+ */
+
+int flash_area_id_to_image_slot(int area_id)
+{
+    return flash_area_id_to_multi_image_slot(0, area_id);
+}
+
+/* PORTING GUIDE: REQUIRED
+ * Returns the value expected to be read when accesing any erased
+ * flash byte.
+ */
+uint8_t flash_area_erased_val(const struct flash_area *fa)
+{
+    if ((fa != NULL) && (flash_area_get_api(fa->fa_device_id))) {
+        return flash_area_get_api(fa->fa_device_id)->get_erase_val(fa->fa_device_id);
+    } else {
+        return 0u;
+    }
+}
+
+#ifdef MCUBOOT_USE_FLASH_AREA_GET_SECTORS
+
+static int flash_area_get_fa_from_area_id(int idx, struct flash_area **fa)
+{
+    int rc = -1;
+    uint32_t i = 0u;
+
+    while (boot_area_descs[i] != NULL) {
+        if (idx == (int)boot_area_descs[i]->fa_id) {
+            *fa = boot_area_descs[i];
+            rc = 0;
+            break;
+        }
+        i++;
+    }
+
+    return rc;
+}
+
+int flash_area_get_sectors(int idx, uint32_t *cnt, struct flash_sector *ret)
+{
+    int rc = 0;
+    struct flash_area *fa = NULL;
+    size_t sectors_n = 0u;
+    uint32_t my_sector_addr = 0u;
+    uint32_t my_sector_size = 0u;
+
+    rc = flash_area_get_fa_from_area_id(idx, &fa);
+
+    if ((fa != NULL) && (cnt != NULL) && (ret != NULL) && (rc == 0) && (flash_area_get_api(fa->fa_device_id) != NULL)) {
+        size_t sector_size = flash_area_get_api(fa->fa_device_id)->get_erase_size(fa->fa_device_id);
+        size_t area_size = fa->fa_size;
+
+        sectors_n = (area_size + (sector_size - 1U)) / sector_size;
+
+        if (sectors_n > (size_t)MCUBOOT_MAX_IMG_SECTORS) {
+            sector_size *= 2u;
+        }
+
+        sectors_n = 0;
+        my_sector_addr = fa->fa_off;
+        while (area_size > 0u) {
+            my_sector_size = sector_size;
+#ifdef MCUBOOT_SWAP_USING_SCRATCH
+            uint32_t my_sector_offs = my_sector_addr % my_sector_size;
+
+            if (my_sector_offs != 0u) {
+                my_sector_size = sector_size - my_sector_offs;
+            }
+
+            if (my_sector_size > area_size) {
+                my_sector_size = area_size;
+            }
+#endif /* MCUBOOT_SWAP_USING_SCRATCH */
+            ret[sectors_n].fs_size = my_sector_size;
+            ret[sectors_n].fs_off = my_sector_addr;
+
+            my_sector_addr += my_sector_size;
+            if (area_size >= my_sector_size) {
+                area_size -= my_sector_size;
+                sectors_n++;
+            } else {
+                area_size = 0;
+                sectors_n++;
+            }
+        }
+
+        if (sectors_n <= *cnt) {
+            *cnt = sectors_n;
+        } else {
+            rc = -1;
+        }
+    } else {
+        rc = -1;
+    }
+
+    return rc;
+}
+#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
diff --git a/boot/cypress/platforms/memory/external_memory/external_memory.c b/boot/cypress/platforms/memory/external_memory/external_memory.c
new file mode 100644
index 0000000..c9a58ff
--- /dev/null
+++ b/boot/cypress/platforms/memory/external_memory/external_memory.c
@@ -0,0 +1,196 @@
+/**
+ * \file external_memory.c
+ * \version 1.0
+ *
+ * \brief
+ *  This is the source file of external flash driver adoption layer between
+ *PSoC6 and standard MCUBoot code.
+ *
+ ********************************************************************************
+ * \copyright
+ *
+ * (c) 2020, Cypress Semiconductor Corporation
+ * or a subsidiary of Cypress Semiconductor Corporation. All rights
+ * reserved.
+ *
+ * This software, including source code, documentation and related
+ * materials ("Software"), is owned by Cypress Semiconductor
+ * Corporation or one of its subsidiaries ("Cypress") and is protected by
+ * and subject to worldwide patent protection (United States and foreign),
+ * United States copyright laws and international treaty provisions.
+ * Therefore, you may use this Software only as provided in the license
+ * agreement accompanying the software package from which you
+ * obtained this Software ("EULA").
+ *
+ * If no EULA applies, Cypress hereby grants you a personal, non-
+ * exclusive, non-transferable license to copy, modify, and compile the
+ * Software source code solely for use in connection with Cypress?s
+ * integrated circuit products. Any reproduction, modification, translation,
+ * compilation, or representation of this Software except as specified
+ * above is prohibited without the express written permission of Cypress.
+ *
+ * Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO
+ * WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING,
+ * BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE. Cypress reserves the right to make
+ * changes to the Software without notice. Cypress does not assume any
+ * liability arising out of the application or use of the Software or any
+ * product or circuit described in the Software. Cypress does not
+ * authorize its products for use in any products where a malfunction or
+ * failure of the Cypress product may reasonably be expected to result in
+ * significant property damage, injury or death ("High Risk Product"). By
+ * including Cypress's product in a High Risk Product, the manufacturer
+ * of such system or application assumes all risk of such use and in doing
+ * so agrees to indemnify Cypress against all liability.
+ *
+ ******************************************************************************/
+#include <stdbool.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sysflash/sysflash.h>
+
+#include "cy_device_headers.h"
+#include "cy_flash.h"
+#include "cy_syspm.h"
+#include "flash_map_backend/flash_map_backend.h"
+#include "flash_map_backend_platform.h"
+#include "flash_qspi.h"
+
+static uint32_t get_base_address(uint8_t fa_device_id)
+{
+    uint32_t res = 0U;
+
+    if ((fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) ==
+        FLASH_DEVICE_EXTERNAL_FLAG) {
+        res = SMIF_MEM_START_PLATFORM;
+    } else {
+        res = 0U;
+    }
+
+    return res;
+}
+
+static uint32_t get_min_erase_size(uint8_t fa_device_id)
+{
+    (void)fa_device_id;
+
+    return qspi_get_erase_size();
+}
+
+static uint8_t get_erase_val(uint8_t fa_device_id)
+{
+    (void)fa_device_id;
+
+    return EXTERNAL_MEMORY_ERASE_VALUE_PLATFORM;
+}
+
+static int read(uint8_t fa_device_id, uintptr_t addr, void *data, uint32_t len)
+{
+    (void)fa_device_id;
+
+    int rc = -1;
+    cy_stc_smif_mem_config_t *cfg;
+    cy_en_smif_status_t st;
+    uint32_t offset;
+
+    cfg = qspi_get_memory_config(0u);
+
+    offset = (uint32_t)addr - SMIF_MEM_START_PLATFORM;
+
+    st = Cy_SMIF_MemRead(qspi_get_device(), cfg, offset, data, len,
+                         qspi_get_context());
+    if (st == CY_SMIF_SUCCESS) {
+        rc = 0;
+    }
+    return rc;
+}
+
+static int write(uint8_t fa_device_id, uintptr_t addr, const void *data,
+                 uint32_t len)
+{
+    (void)fa_device_id;
+
+    int rc                 = -1;
+    cy_en_smif_status_t st = CY_SMIF_SUCCESS;
+    cy_stc_smif_mem_config_t *cfg;
+    uint32_t offset;
+
+    cfg = qspi_get_memory_config(0u);
+
+    offset = (uint32_t)addr - SMIF_MEM_START_PLATFORM;
+
+#if defined CYW20829
+    st = Cy_SMIF_MemEraseSector(qspi_get_device(), cfg, offset,
+                                qspi_get_erase_size(), qspi_get_context());
+
+    if (st == CY_SMIF_SUCCESS) {
+#endif /* CYW20829 */
+        st = Cy_SMIF_MemWrite(qspi_get_device(), cfg, offset, data, len,
+                              qspi_get_context());
+#if defined CYW20829
+    }
+#endif
+    if (st == CY_SMIF_SUCCESS) {
+        rc = 0;
+    }
+    return rc;
+}
+
+static int erase(uint8_t fa_device_id, uintptr_t addr, uint32_t size)
+{
+    (void)fa_device_id;
+
+    int rc                 = -1;
+    cy_en_smif_status_t st = CY_SMIF_SUCCESS;
+    uint32_t offset;
+
+    if (size > 0u) {
+        /* It is erase sector-only
+         *
+         * There is no power-safe way to erase flash partially
+         * this leads upgrade slots have to be at least
+         * eraseSectorSize far from each other;
+         */
+        cy_stc_smif_mem_config_t *memCfg = qspi_get_memory_config(0);
+        uint32_t eraseSize               = qspi_get_erase_size();
+
+        offset = ((uint32_t)addr - SMIF_MEM_START_PLATFORM) & ~((uint32_t)(eraseSize - 1u));
+
+        while ((size > 0u) && (CY_SMIF_SUCCESS == st)) {
+            st = Cy_SMIF_MemEraseSector(qspi_get_device(), memCfg, offset,
+                                        eraseSize, qspi_get_context());
+
+            size -= (size >= eraseSize) ? eraseSize : size;
+            offset += eraseSize;
+        }
+
+        if (st == CY_SMIF_SUCCESS) {
+            rc = 0;
+        }
+    }
+
+    return rc;
+}
+
+static int open(uint8_t fa_device_id)
+{
+    (void)fa_device_id;
+
+    return 0;
+}
+
+static void close(uint8_t fa_device_id)
+{
+    (void)fa_device_id;
+}
+
+const struct flash_area_interface external_mem_interface = {
+    .open             = &open,
+    .close            = &close,
+    .read             = &read,
+    .write            = &write,
+    .erase            = &erase,
+    .get_erase_val    = &get_erase_val,
+    .get_erase_size   = &get_min_erase_size,
+    .get_base_address = &get_base_address};
diff --git a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h b/boot/cypress/platforms/memory/flash_map_backend/flash_map_backend.h
similarity index 81%
rename from boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h
rename to boot/cypress/platforms/memory/flash_map_backend/flash_map_backend.h
index 194f798..13002c3 100644
--- a/boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h
+++ b/boot/cypress/platforms/memory/flash_map_backend/flash_map_backend.h
@@ -28,19 +28,8 @@
 #ifndef FLASH_MAP_BACKEND_H
 #define FLASH_MAP_BACKEND_H
 
-#include <mcuboot_config/mcuboot_config.h>
 #include "cy_flash.h"
-#define FLASH_DEVICE_INDEX_MASK                 (0x7Fu)
-#define FLASH_DEVICE_GET_EXT_INDEX(n)           ((n) & FLASH_DEVICE_INDEX_MASK)
-#define FLASH_DEVICE_UNDEFINED                  (0x00u)
-#define FLASH_DEVICE_EXTERNAL_FLAG              (0x80u)
-#define FLASH_DEVICE_INTERNAL_FLASH             (0x7Fu)
-#define FLASH_DEVICE_EXTERNAL_FLASH(index)      (FLASH_DEVICE_EXTERNAL_FLAG | index)
-
-#ifndef CY_BOOT_EXTERNAL_DEVICE_INDEX
-/* assume first(one) SMIF device is used */
-#define CY_BOOT_EXTERNAL_DEVICE_INDEX           (0u)
-#endif
+#include "mcuboot_config/mcuboot_config.h"
 
 /**
  *
@@ -60,6 +49,18 @@
  * and match the target offset specified in download script.
  */
 #include <inttypes.h>
+#include <stdlib.h>
+
+struct flash_area_interface {
+    int (*open)(uint8_t fa_device_id);
+    void (*close)(uint8_t fa_device_id);
+    int (*read)(uint8_t fa_device_id, uintptr_t addr, void *dst, uint32_t len);
+    int (*write)(uint8_t fa_device_id, uintptr_t addr, const void *src, uint32_t len);
+    int (*erase)(uint8_t fa_device_id, uintptr_t addr, uint32_t len);
+    uint8_t (*get_erase_val)(uint8_t fa_device_id);
+    uint32_t (*get_erase_size)(uint8_t fa_device_id);
+    uint32_t (*get_base_address)(uint8_t fa_device_id);
+};
 
 /**
  * @brief Structure describing an area on a flash device.
@@ -79,8 +80,6 @@
      */
     uint8_t fa_device_id;
 
-    uint16_t pad16;
-
     /**
      * This area's offset, relative to the beginning of its flash
      * device's storage.
@@ -93,6 +92,33 @@
     uint32_t fa_size;
 };
 
+struct flash_device {
+    /**
+     * Device address.
+     */
+    uint32_t address;
+
+    /**
+     * Device capacity, in bytes.
+     */
+    uint32_t size;
+
+    /**
+     * Device erase size, in bytes.
+     */
+    uint32_t erase_size;
+
+    /**
+     * Device erase size, in bytes.
+     */
+    uint8_t erase_val;
+
+    /**
+     * Device id, same as fa_device_id.
+     */
+    uint8_t device_id;
+};
+
 static inline uint8_t flash_area_get_id(const struct flash_area *fa)
 {
     return fa->fa_id;
@@ -157,20 +183,18 @@
 int flash_device_base(uint8_t fd_id, uintptr_t *ret);
 
 /*< Opens the area for use. id is one of the `fa_id`s */
-int flash_area_open(uint8_t id, const struct flash_area **fa);
+int flash_area_open(uint8_t fa_id, const struct flash_area **fa);
 void flash_area_close(const struct flash_area *fa);
 /*< Reads `len` bytes of flash memory at `off` to the buffer at `dst` */
 int flash_area_read(const struct flash_area *fa, uint32_t off, void *dst,
-                     uint32_t len);
+                    uint32_t len);
 /*< Writes `len` bytes of flash memory at `off` from the buffer at `src` */
-int flash_area_write(const struct flash_area *fa, uint32_t off,
-                     const void *src, uint32_t len);
+int flash_area_write(const struct flash_area *fa, uint32_t off, const void *src,
+                     uint32_t len);
 /*< Erases `len` bytes of flash memory at `off` */
 int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len);
 /*< Returns this `flash_area`s alignment */
 size_t flash_area_align(const struct flash_area *fa);
-/*< Initializes an array of flash_area elements for the slot's sectors */
-int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa);
 /*< Returns the `fa_id` for slot, where slot is 0 (primary) or 1 (secondary) */
 int flash_area_id_from_image_slot(int slot);
 /*< Returns the slot, for the `fa_id` supplied */
diff --git a/boot/cypress/platforms/memory/sysflash/sysflash.h b/boot/cypress/platforms/memory/sysflash/sysflash.h
new file mode 100644
index 0000000..544a8c6
--- /dev/null
+++ b/boot/cypress/platforms/memory/sysflash/sysflash.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2022 Infineon Technologies AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements.  See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership.  The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License.  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied.  See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef SYSFLASH_H
+#define SYSFLASH_H
+
+#include <stdint.h>
+#include "cy_syslib.h"
+#include "memorymap.h"
+
+#ifndef MCUBOOT_IMAGE_NUMBER
+#ifdef MCUBootApp
+#warning Undefined MCUBOOT_IMAGE_NUMBER. Assuming 1 (single-image).
+#endif /* MCUBootApp */
+#define MCUBOOT_IMAGE_NUMBER                 1u
+#endif /* MCUBOOT_IMAGE_NUMBER */
+
+#define FLASH_AREA_ERROR                    255u  /* Invalid flash area */
+
+#define SLOTS_FOR_IMAGE                     ( 2u)
+
+#if (MCUBOOT_IMAGE_NUMBER < 1 || MCUBOOT_IMAGE_NUMBER > 16)
+#error Unsupported MCUBOOT_IMAGE_NUMBER. Set it to between 1 and 16.
+#endif /* (MCUBOOT_IMAGE_NUMBER < 1 || MCUBOOT_IMAGE_NUMBER > 16) */
+
+#define BOOT_MAX_SWAP_STATUS_SECTORS        (64)
+
+__STATIC_INLINE uint8_t FLASH_AREA_IMAGE_PRIMARY(uint32_t img_idx)
+{
+#if defined(MEMORYMAP_GENERATED_AREAS)
+    return memory_areas_primary[img_idx];
+#else
+    uint32_t flash_area_id = FLASH_AREA_ERROR;
+
+    switch (img_idx)
+    {
+        case 0:
+        {
+            flash_area_id = FLASH_AREA_IMG_1_PRIMARY;
+            break;
+        }
+
+        case 1:
+        {
+            /* (img_idx + 1) because img_idx starts from 0, _IMAGE_NUMBER from 1 */
+            flash_area_id = SLOTS_FOR_IMAGE * (img_idx + 1u);
+            break;
+        }
+
+        default:
+        {
+            /* 7 now is used for FLASH_AREA_IMAGE_SWAP_STATUS */
+            if (img_idx < (uint32_t)MCUBOOT_IMAGE_NUMBER)
+            {
+                flash_area_id = SLOTS_FOR_IMAGE * (img_idx + 1u) + 2u;
+            }
+            break;
+        }
+    }
+
+    if (flash_area_id > (unsigned)UINT8_MAX)
+    {
+        flash_area_id = FLASH_AREA_ERROR;
+    }
+
+    return (uint8_t)flash_area_id;
+#endif
+}
+
+__STATIC_INLINE uint8_t FLASH_AREA_IMAGE_SECONDARY(uint32_t img_idx)
+{
+#if defined(MEMORYMAP_GENERATED_AREAS)
+    return memory_areas_secondary[img_idx];
+#else
+    uint32_t flash_area_id = FLASH_AREA_ERROR;
+
+    switch (img_idx)
+    {
+        case 0:
+        {
+            flash_area_id = FLASH_AREA_IMG_1_SECONDARY;
+            break;
+        }
+
+        case 1:
+        {
+            /* (img_idx + 1) because img_idx starts from 0, _IMAGE_NUMBER from 1 */
+            flash_area_id = SLOTS_FOR_IMAGE * (img_idx + 1u) + 1u;
+            break;
+        }
+
+        default:
+        {
+            if (img_idx < (uint32_t)MCUBOOT_IMAGE_NUMBER)
+            {
+                flash_area_id = SLOTS_FOR_IMAGE * (img_idx + 1u) + 3u;
+            }
+            break;
+        }
+    }
+
+    if (flash_area_id > (unsigned)UINT8_MAX)
+    {
+        flash_area_id = FLASH_AREA_ERROR;
+    }
+
+    return (uint8_t)flash_area_id;
+#endif
+}
+
+#endif /* SYSFLASH_H */
diff --git a/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c
index c460034..7f32826 100644
--- a/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c
@@ -15,26 +15,33 @@
  * limitations under the License.
  */
 
+#if defined MCUBOOT_HW_ROLLBACK_PROT
+
 #include <stdint.h>
 #include "bootutil/bootutil_log.h"
+
+#define NEED_MAX_COUNTERS
+#include "memorymap.h"
+
 #include "cy_security_cnt_platform.h"
 #include "cy_service_app.h"
 #include "sysflash/sysflash.h"
 #include "cy_efuse.h"
 
-#if defined MCUBOOT_HW_ROLLBACK_PROT
-
-#ifdef NEED_FLASH_MAP
-#undef NEED_FLASH_MAP
-#endif
-
-#define NEED_MAX_COUNTERS
-#include "cy_flash_map.h"
-
 #define TEST_BIT(var, pos) (0U != ((var) & (1UL << (pos))))
 
 #define NV_COUNTER_EFUSE_OFFSET  0x60
 
+/**
+ * Since we are using the array bits_per_cnt[] to store bits destribution for each image,
+ * we need to know place, where bits for a desired image start.
+ * This function is intended to find a start position in the array bits_per_cnt[] for
+ * a desired image_id.
+ * 
+ * @param image_id Index of the image (from 0)
+ * 
+ * @return         Start position of bit(s) for desired image_id
+ */
 static uint8_t get_array_member(uint32_t image_id)
 {
     uint8_t start_bit_for_image_id = 0;
@@ -47,6 +54,17 @@
     return start_bit_for_image_id;
 }
 
+/** 
+ * Extracts security counter for the desired image from the full NV-counter of device
+ * (e-fuse) and converts it to integer value, in decimal form.
+ * 
+ * @param image_id      Index of the image (from 0)
+ * 
+ * @param nv_counter    Full e-fuse value as it's written in an NV register.
+ * 
+ * @return              Counter's value encoded in 'fih_uint', in decimal form
+ */
+
 static fih_uint counter_extract(uint32_t image_id, fih_uint nv_counter)
 {
     uint32_t res = 0U;
@@ -54,8 +72,7 @@
     uint8_t bits_for_current_image = bits_per_cnt[image_id];
 
     while (TEST_BIT(fih_uint_decode(nv_counter), start_bit_for_image_id) && 
-            bits_for_current_image != 0U)
-    {
+            bits_for_current_image != 0U) {
         ++res;
         ++start_bit_for_image_id;
         --bits_for_current_image;
@@ -65,8 +82,17 @@
 }
 
 /**
- * Extracts security counter for the desired image from full NV
- * counter and converts it to integer value.
+ * Converts security counter for the desired image from full NV-counter 
+ * to a decimal integer value with validation of all bits in 'nv_counter'.
+ * If NV-counter has bit(s) in position for another 'image_id', it returns an error.
+ * For example, the folowing case updates counter for image 0 - it returns an error
+ * because the counter for image 0 contains bits in position for the image 1:
+ * *************************************************
+ *  bits for image 1  | 5 bits are reserved for image 0
+ * ***************************
+ *                   1111111 *
+ * ***************************
+ * 
  * Efuse stores nv counter value as a consequent bits. This means
  * NV counter set to 5 in policy would be written as 0x1F.
  * Only one security counter is available in system. Maximum value is 32.
@@ -75,21 +101,23 @@
  *
  * @param image_id          Index of the image (from 0)
  *
- * @param nv_counter        Full security counter to get specific efuse value for desired image
+ * @param nv_counter        Image security counter read out from TLV packet of image_id.
  * 
  * @param extracted_img_cnt Pointer to a variable, where extracted counter for the 'image_id'
  *                          would be stored
- *
  * @return                  FIH_FAILURE on failure, otherwise FIH_SUCCESS.
- *                      
+ * 
+ * @warning                 Don't use this function inside of 'platform_security_counter_get' or
+ *                          'platform_security_counter_update' functions.
+ *                          For this purpose please use the function 'counter_extract'.
  */
 
 fih_int platform_security_counter_check_extract(uint32_t image_id, fih_uint nv_counter, fih_uint *extracted_img_cnt)
 {
     fih_int fih_ret = FIH_FAILURE;
-    uint32_t arr_size = sizeof(bits_per_cnt)/sizeof(bits_per_cnt[0]);
+    uint32_t arr_size = sizeof(bits_per_cnt) / sizeof(bits_per_cnt[0]);
     
-    if (image_id > (arr_size-1U)) {
+    if (image_id > (arr_size - 1U)) {
         BOOT_LOG_ERR("Incorrect input parameter Image ID");
         FIH_RET(fih_ret);
     }
@@ -99,18 +127,17 @@
     uint32_t bit_mask_to_check_others_images = 0U;
 
     /* Check if full NV-counter has any bits of others image_id */
-        /* Set up the number of bits equal to bits_for_current_image */
-    for (uint32_t j = 0; j < bits_for_current_image; ++j)
-    {
+    /* Set up the number of bits equal to bits_for_current_image */
+    for (uint32_t j = 0; j < bits_for_current_image; ++j) {
         bit_mask_to_check_others_images <<= 1U;
         bit_mask_to_check_others_images |= 1U;
     }
-        /* Move bit_mask_to_check_others_images at place for image_id */
+    /* Move bit_mask_to_check_others_images at place for image_id */
     bit_mask_to_check_others_images <<= start_bit_for_image_id;
 
     /* Return an error if recieved full NV-counter has any bits of others image_id */
-    if( !(~bit_mask_to_check_others_images & fih_uint_decode(nv_counter)) )
-    {
+    if(FIH_TRUE == fih_uint_eq(fih_uint_encode(
+        (uint32_t)(~bit_mask_to_check_others_images & fih_uint_decode(nv_counter))), FIH_UINT_ZERO)) {
         /* Extract number of set bits from full NV-counter in the upgrade image */
         *extracted_img_cnt = counter_extract(image_id, nv_counter);
 
@@ -131,38 +158,37 @@
  *
  * @return                  FIH_SUCESS on success; FIH_FAILURE on failure.
  */
-fih_int platform_security_counter_get(uint32_t image_id, fih_uint *security_cnt) {
-
+fih_int platform_security_counter_get(uint32_t image_id, fih_uint *security_cnt) 
+{
     fih_int fih_ret = FIH_FAILURE;      
-    uint32_t arr_size = sizeof(bits_per_cnt)/sizeof(bits_per_cnt[0]);
+    uint32_t arr_size = sizeof(bits_per_cnt) / sizeof(bits_per_cnt[0]);
 
-    if (image_id > (arr_size-1U)) {
+    if (image_id > (arr_size - 1U)) {
         BOOT_LOG_ERR("Incorrect input parameter Image ID");
         FIH_RET(fih_ret);
     }
 
     cy_en_efuse_status_t efuse_stat = CY_EFUSE_ERR_UNC;
     uint32_t nv_counter = 0;
-    fih_uint nv_counter_secure = (fih_uint)FIH_FAILURE;
+    fih_uint nv_counter_secure = FIH_UINT_MAX;
 
     /* Init also enables Efuse block */
     efuse_stat = Cy_EFUSE_Init(EFUSE);
 
-    if (efuse_stat == CY_EFUSE_SUCCESS) {
-
+    if (CY_EFUSE_SUCCESS == efuse_stat) {
         efuse_stat = Cy_EFUSE_ReadWord(EFUSE, &nv_counter, NV_COUNTER_EFUSE_OFFSET);
 
-        if (efuse_stat == CY_EFUSE_SUCCESS){
+        if (efuse_stat == CY_EFUSE_SUCCESS) {
             /* Read value of counter from efuse twice to ensure value is not compromised */
             nv_counter_secure = fih_uint_encode(nv_counter);
             nv_counter = 0U;
             efuse_stat = Cy_EFUSE_ReadWord(EFUSE, &nv_counter, NV_COUNTER_EFUSE_OFFSET);
         }
-        if (efuse_stat == CY_EFUSE_SUCCESS){
+        if (CY_EFUSE_SUCCESS == efuse_stat) {
 
-            if (fih_uint_eq(nv_counter_secure, fih_uint_encode(nv_counter))) {
+            if (FIH_TRUE == fih_uint_eq(nv_counter_secure, fih_uint_encode(nv_counter))) {
 
-                *security_cnt = counter_extract(image_id, nv_counter);
+                *security_cnt = counter_extract(image_id, fih_uint_encode(nv_counter));
 
                 fih_ret = FIH_SUCCESS;
             }
@@ -185,14 +211,16 @@
  * @param image_id          The image number for which you want to get a security counter,
  *                          saved in EFUSE (from 0)
  * @param img_security_cnt  Full new NV security counter
+ * 
  * @param reprov_packet     Pointer to a reprovisioning packet containing new NV counter.
+ * 
  * @return                  0 on success; nonzero on failure.
  */
-int32_t platform_security_counter_update(uint32_t image_id, uint32_t img_security_cnt, uint8_t * reprov_packet)
+int32_t platform_security_counter_update(uint32_t image_id, fih_uint img_security_cnt, uint8_t * reprov_packet)
 {
     int32_t rc = -1;
     fih_int fih_rc = FIH_FAILURE;
-    fih_uint efuse_img_counter = (fih_uint)FIH_FAILURE;
+    fih_uint efuse_img_counter = FIH_UINT_MAX;
     fih_uint packet_img_counter = counter_extract(image_id, img_security_cnt);
 
     /* Read value of security counter stored in chips efuses.
@@ -206,17 +234,17 @@
         * stored security counter value for that image index.
         */
 
-        BOOT_LOG_DBG("image_id = %u, packet_img_counter = %u, efuse_img_counter = %u \n",
-                image_id, packet_img_counter, fih_uint_decode(efuse_img_counter));
-
-        if ((packet_img_counter > fih_uint_decode(efuse_img_counter)) &&
-             (packet_img_counter <= MAX_SEC_COUNTER_VAL)) {
+        BOOT_LOG_DBG("image_id = %u, packet_img_counter = %u, efuse_img_counter = %u\n",
+                image_id, fih_uint_decode(packet_img_counter), fih_uint_decode(efuse_img_counter));
+        
+        if (FIH_TRUE == fih_uint_gt(packet_img_counter, efuse_img_counter) &&
+            FIH_TRUE == fih_uint_le(packet_img_counter, fih_uint_encode(MAX_SEC_COUNTER_VAL))) {
 
             BOOT_LOG_INF("service_app is called\n", __func__ );
             /* Attention: This function initiates system reset */
             call_service_app(reprov_packet);
             /* Runtime should never get here. Panic statement added to secure
-             * sutiation when hacker initiates skip of call_service_app function. 
+             * situation when hacker initiates skip of call_service_app function.
             */
             FIH_PANIC;
         }
@@ -225,7 +253,7 @@
         }
     }
 
-return rc;
+    return rc;
 }
 
 #endif /* defined MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h
index c64eadd..f712a8d 100644
--- a/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h
@@ -45,16 +45,27 @@
  * @param image_id          The image number for which you want to get a security counter,
  *                          saved in EFUSE (from 0)
  * @param img_security_cnt  Security counter value of image: appropriated bit array inside of 32bits
+ * 
  * @param reprov_packet     Pointer to a reprovisioning packet containing NV counter.
+ * 
  * @return                  0 on success; nonzero on failure.
  */
 
-int32_t platform_security_counter_update(uint32_t image_id, uint32_t img_security_cnt, uint8_t * reprov_packet);
+int32_t platform_security_counter_update(uint32_t image_id, fih_uint img_security_cnt, uint8_t * reprov_packet);
 
 
 /**
- * Extracts security counter for the desired image from full NV
- * counter and converts it to integer value.
+ * Converts security counter for the desired image from full NV-counter 
+ * to a decimal integer value with validation of all bits in 'nv_counter'.
+ * If NV-counter has bit(s) in position for another 'image_id', it returns an error.
+ * For example, the folowing case updates counter for image 0 - it returns an error
+ * because the counter for image 0 contains bits in position for the image 1:
+ * *************************************************
+ *  bits for image 1  | 5 bits are reserved for image 0
+ * ***************************
+ *                   1111111 *
+ * ***************************
+ * 
  * Efuse stores nv counter value as a consequent bits. This means
  * NV counter set to 5 in policy would be written as 0x1F.
  * Only one security counter is available in system. Maximum value is 32.
@@ -63,13 +74,15 @@
  *
  * @param image_id          Index of the image (from 0)
  *
- * @param nv_counter        Full security counter to get specific efuse value for desired image
+ * @param nv_counter        Image security counter read out from TLV packet of image_id.
  * 
  * @param extracted_img_cnt Pointer to a variable, where extracted counter for the 'image_id'
  *                          would be stored
- *
  * @return                  FIH_FAILURE on failure, otherwise FIH_SUCCESS.
- *
+ * 
+ * @warning                 Don't use this function inside of 'platform_security_counter_get' or
+ *                          'platform_security_counter_update' functions.
+ *                          For this purpose please use the function 'counter_extract'.
  */
 
 fih_int platform_security_counter_check_extract(uint32_t image_id, fih_uint nv_counter, fih_uint *extracted_img_cnt);
diff --git a/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c
index eb1615a..5afd417 100644
--- a/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c
@@ -20,10 +20,11 @@
 
 #include "bootutil/image.h"
 #include "bootutil_priv.h"
-#include "sysflash/sysflash.h"
+#include "flash_map_backend_platform.h"
 #include "cy_service_app.h"
 #include "flash_qspi.h"
-#include "cy_smif_cyw20829.h"
+
+extern const struct flash_area_interface external_mem_interface;
 
 #if defined MCUBOOT_HW_ROLLBACK_PROT
 
@@ -181,12 +182,13 @@
             rc = 0;
         }
         else {
-            rc = cyw20829_smif_erase((CY_XIP_BASE + SERVICE_APP_DESC_OFFSET), qspi_get_erase_size());
+            rc = external_mem_interface.erase(
+                FLASH_DEVICE_EXTERNAL_FLASH(0),
+                (CY_XIP_BASE + SERVICE_APP_DESC_OFFSET), qspi_get_erase_size());
             if (0 == rc) {
                 if (CYAPP_SUCCESS == SRSS->TST_DEBUG_STATUS) {
                     rc = 0;
-                }
-                else {
+                } else {
                     rc = -1;
                 }
             }
diff --git a/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c
index 17a4e08..4218fe8 100644
--- a/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c
+++ b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c
@@ -49,7 +49,7 @@
  *
  * @return                  0 on success; nonzero on failure.
  */
-int32_t platform_security_counter_update(uint32_t img_security_cnt, void * custom_data)
+int32_t platform_security_counter_update(fih_uint img_security_cnt, void *custom_data)
 {
     (void)img_security_cnt;
     (void)custom_data;
diff --git a/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h
index 69874c9..b1fad71 100644
--- a/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h
+++ b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h
@@ -40,6 +40,6 @@
  *
  * @return                  0 on success; nonzero on failure.
  */
-int32_t platform_security_counter_update(uint32_t img_security_cnt, void * custom_data);
+int32_t platform_security_counter_update(fih_uint img_security_cnt, void *custom_data);
 
 #endif /* CY_SECURITY_CNT_PLATFORM_H */
diff --git a/boot/cypress/platforms/security_counter/cy_security_cnt.c b/boot/cypress/platforms/security_counter/cy_security_cnt.c
index 17ede62..abd9b6b 100644
--- a/boot/cypress/platforms/security_counter/cy_security_cnt.c
+++ b/boot/cypress/platforms/security_counter/cy_security_cnt.c
@@ -25,7 +25,7 @@
 boot_nv_security_counter_init(void)
 {
     /* Do nothing. */
-    return 0;
+    FIH_RET(FIH_SUCCESS);
 }
 
 fih_int
@@ -41,9 +41,8 @@
 }
 
 int32_t
-boot_nv_security_counter_update(uint32_t image_id, uint32_t img_security_cnt, void * custom_data)
+boot_nv_security_counter_update(uint32_t image_id, fih_uint img_security_cnt, void *custom_data)
 {
-
     int32_t rc = platform_security_counter_update(image_id, img_security_cnt, (uint8_t *)custom_data);
 
     /* Do nothing. */
diff --git a/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c b/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c
index 92953f4..3d52bd0 100644
--- a/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c
+++ b/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c
@@ -30,7 +30,7 @@
 #ifdef CYW20829
 
 #define CY_GET_XIP_REMAP_ADDR(addr)     ((addr) - CY_XIP_BASE + CY_XIP_REMAP_OFFSET)
-#define CY_GET_XIP_REMAP_ADDR_FIH(addr) fih_uint_encode(fih_uint_decode((addr)) - CY_XIP_BASE + CY_XIP_REMAP_OFFSET)
+#define CY_GET_XIP_REMAP_ADDR_FIH(addr) fih_uint_encode(CY_GET_XIP_REMAP_ADDR(addr))
 
 #define CY_GET_SRAM0_REMAP_ADDR(addr)   ((addr) - CY_SRAM0_BASE + CY_SRAM0_REMAP_OFFSET)
 
@@ -298,8 +298,8 @@
 CY_RAMFUNC_BEGIN
 __NO_RETURN void platform_RunNextApp(fih_uint toc2_addr, uint32_t *key, uint32_t *iv)
 {
-    fih_uint l1_app_descr_addr = (fih_uint)FIH_FAILURE;
-    fih_uint ns_vect_tbl_addr = (fih_uint)FIH_FAILURE;
+    fih_uint l1_app_descr_addr = FIH_UINT_MAX;
+    fih_uint ns_vect_tbl_addr = FIH_UINT_MAX;
 
     uint32_t bootstrap_src_addr = 0u;
     uint32_t bootstrap_dst_addr = 0u;
diff --git a/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.c b/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.c
index 2329670..cafea5e 100644
--- a/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.c
+++ b/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.c
@@ -68,11 +68,11 @@
  *
  * @param app_addr  FIH-protected address of the app's vector table.
  */
-#ifdef CM0P
+#ifdef BOOT_CM0P
 __NO_RETURN void psoc6_launch_cm0p_app(fih_uint app_addr)
 #else
 __NO_RETURN void psoc6_launch_cm4_app(fih_uint app_addr)
-#endif /* CM0P */
+#endif /* BOOT_CM0P */
 {
     register vect_tbl_start_t* const vect_tbl1 = (vect_tbl_start_t*)fih_uint_decode(app_addr);
     register vect_tbl_start_t* const vect_tbl2 = (vect_tbl_start_t*)fih_uint_decode(app_addr);
@@ -97,7 +97,7 @@
         (void)memset(__bss_start__,  0, (size_t)((uintptr_t)__bss_end__  - (uintptr_t)__bss_start__));
 
         /* Relocate Vector Table */
-        #ifdef CM0P
+        #ifdef BOOT_CM0P
             CPUSS->CM0_VECTOR_TABLE_BASE = (uintptr_t)vect_tbl1;
             if((uintptr_t)CPUSS->CM0_VECTOR_TABLE_BASE != (uintptr_t)vect_tbl2)
             {
@@ -109,7 +109,7 @@
             {
                 break;
             }
-        #endif /* CM0P */
+        #endif /* BOOT_CM0P */
             SCB->VTOR = (uintptr_t)vect_tbl1;
             if((uintptr_t)SCB->VTOR != (uintptr_t)vect_tbl2)
             {
diff --git a/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.h b/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.h
index 3e514e0..571e4f2 100644
--- a/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.h
+++ b/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.h
@@ -29,7 +29,7 @@
 #include "cy_pdl.h"
 #include "bootutil/fault_injection_hardening.h"
 
-#if defined CM0P
+#if defined BOOT_CM0P
 /**
  * Starts the application on the Cortex-M0+ core. MCUBoot is also running on
  * this core, so we just clean up memory, set up the vector table and stack,
@@ -38,7 +38,7 @@
  * @param app_addr  FIH-protected address of the app's vector table.
  */
 __NO_RETURN void psoc6_launch_cm0p_app(fih_uint app_addr);
-#elif defined CM4
+#elif defined BOOT_CM4
 /**
  * Starts the application on the Cortex-M4 core. MCUBoot is also running on
  * this core, so we just clean up memory, set up the vector table and stack,
diff --git a/boot/cypress/platforms/utils/XMC7000/cy_si_config.c b/boot/cypress/platforms/utils/XMC7000/cy_si_config.c
new file mode 100644
index 0000000..4a2d076
--- /dev/null
+++ b/boot/cypress/platforms/utils/XMC7000/cy_si_config.c
@@ -0,0 +1,80 @@
+/********************************************************************************
+* Copyright 2023 Infineon Technologies AG
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cmsis_compiler.h"
+#include "cy_crypto_common.h"
+#include "cy_si_config.h"
+#include "cy_si_keystorage.h"
+#include "cy_syslib.h"
+
+/** Linker script symbols */
+extern const char __app_header_vtable_offset[];
+extern const char __secure_object_size[];
+
+#define CY_M0PLUS_SI_VECTOR_OFFSET ((uint32_t)__app_header_vtable_offset)
+#define CY_M0PLUS_SI_SIZE ((uint32_t)__secure_object_size)
+#define CY_SI_VT_OFFSET (CY_M0PLUS_SI_VECTOR_OFFSET) - offsetof(cy_stc_si_appheader_t, core0Vt) /**< CM0+ VT Offset */
+#define CY_SI_CPUID (0xC6000000UL)                                                              /**< CM0+ ARM CPUID[15:4] Reg shifted to [31:20] */
+#define CY_SI_CORE_IDX (0UL)                                                                    /**< CM0+ core ID */
+
+/** Flashboot parameters */
+#define CY_SI_FLASHBOOT_FLAGS                                              \
+    ((CY_SI_FLASHBOOT_CLK_100MHZ << CY_SI_TOC_FLAGS_CLOCKS_POS) |          \
+     (CY_SI_FLASHBOOT_WAIT_20MS << CY_SI_TOC_FLAGS_DELAY_POS) |            \
+     (CY_SI_FLASHBOOT_SWJ_ENABLE << CY_SI_TOC_FLAGS_SWJEN_POS) |           \
+     (CY_SI_FLASHBOOT_VALIDATE_ENABLE << CY_SI_TOC_FLAGS_APP_VERIFY_POS) | \
+     (CY_SI_FLASHBOOT_FBLOADER_DISABLE << CY_SI_TOC_FLAGS_FBLOADER_ENABLE_POS))
+
+extern const cy_stc_si_toc_t cy_toc2;
+/** TOC2 in SFlash */
+CY_SECTION(".cy_toc_part2")
+__USED const cy_stc_si_toc_t cy_toc2 = {
+    .objSize        = CY_SI_TOC2_OBJECTSIZE,         /* Offset+0x00: Object Size (Bytes) excluding CRC */
+    .magicNum       = CY_SI_TOC2_MAGICNUMBER,        /* Offset+0x04: TOC2 ID (magic number) */
+    .smifCfgAddr    = 0UL,                           /* Offset+0x08: SMIF config list pointer */
+    .cm0pappAddr1   = CY_SI_SECURE_FLASH_BEGIN,      /* Offset+0x0C: App1 (CM0+ First User App Object) addr */
+    .cm0pappFormat1 = CY_SI_APP_FORMAT_CYPRESS,      /* Offset+0x10: App1 Format */
+    .cm0pappAddr2   = CY_SI_USERAPP_FLASH_BEGIN,     /* Offset+0x14: App2 (CM0+ Second User App Object) addr */
+    .cm0pappFormat2 = CY_SI_APP_FORMAT_BASIC,        /* Offset+0x18: App2 Format */
+    .cm71appAddr1   = CY_SI_CM71_1stAPP_FLASH_BEGIN, /* Offset+0x1C: App3 (CM7_1 1st User App Object) addr */
+    .cm71appAddr2   = CY_SI_CM71_2ndAPP_FLASH_BEGIN, /* Offset+0x20: App4 (CM7_1 2nd User App Object) addr */
+    .cm72appAddr1   = CY_SI_CM72_1stAPP_FLASH_BEGIN, /* Offset+0x24: App5 (CM7_2 1st User App Object) addr */
+    .cm72appAddr2   = CY_SI_CM72_2ndAPP_FLASH_BEGIN, /* Offset+0x28: App6 (CM7_2 1st User App Object) addr */
+    .reserved1      = {0UL},                         /* Offset+0x2C-0xFB: Reserved area 212Bytes */
+    .securityMarker = CY_SECURITY_NOT_ENHANCED,      /* Offset+0xFC Security Enhance Marker */
+    .shashObj       = 3UL,                           /* Offset+0x100: Number of verified additional objects (S-HASH)*/
+    .sigKeyAddr     = CY_SI_PUBLIC_KEY,              /* Offset+0x104: Addr of signature verification key */
+    .swpuAddr       = CY_SI_SWPU_BEGIN,              /* Offset+0x108: Addr of SWPU Objects */
+    .toc2Addr       = (uint32_t)&cy_toc2,            /* Offset+0x10C: TOC2_OBJECT_ADDR */
+    .addObj         = {0UL},                         /* Offset+0x110-0x1F4: Reserved area 232Bytes */
+    .tocFlags       = CY_SI_FLASHBOOT_FLAGS,         /* Flashboot flags stored in TOC2 */
+    .crc            = 0UL,                           /* Offset+0x1FC: Reserved area 1Byte */
+};
+
+/** Secure Application header */
+CY_SECTION(".cy_app_header")
+__USED const cy_stc_si_appheader_t cy_si_appHeader = {
+    .objSize       = CY_M0PLUS_SI_SIZE,
+    .appId         = (CY_SI_APP_VERSION | CY_SI_APP_ID_SECUREIMG),
+    .appAttributes = 0UL,                          /* Reserved */
+    .numCores      = 1UL,                          /* Only CM0+ */
+    .core0Vt       = CY_SI_VT_OFFSET,              /* CM0+ VT offset */
+    .core0Id       = CY_SI_CPUID | CY_SI_CORE_IDX, /* CM0+ core ID */
+};
+/** Secure Image Digital signature (Populated by cymcuelftool) */
+CY_SECTION(".cy_app_signature")
+__USED CY_ALIGN(4) const uint8_t cy_si_appSignature[CY_SI_SECURE_DIGSIG_SIZE] = {0u};
diff --git a/boot/cypress/platforms/utils/XMC7000/cy_si_config.h b/boot/cypress/platforms/utils/XMC7000/cy_si_config.h
new file mode 100644
index 0000000..90d071a
--- /dev/null
+++ b/boot/cypress/platforms/utils/XMC7000/cy_si_config.h
@@ -0,0 +1,810 @@
+/*******************************************************************************
+* \file cy_si_config.h
+* \version 1.00
+*
+* \brief
+* Definitions and function prototypes for Secure Image.
+*
+********************************************************************************
+* \copyright
+* Copyright 2023, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#ifndef CY_SI_CONFIG_H
+#define CY_SI_CONFIG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/***************************************
+*               Macros
+***************************************/
+
+
+/***************************************
+*               TOC2
+***************************************/
+/** \addtogroup group_secure_image_macro
+* \{
+*/
+
+/** \defgroup group_secure_image_flashboot_clock_macros Flash Boot clock selection 
+* Clock selection for Flash boot execution.
+* \{
+*/
+#define CY_SI_FLASHBOOT_CLK_8MHZ            (0UL)            /**< 8MHz clock selection for Flashboot */
+#define CY_SI_FLASHBOOT_CLK_25MHZ           (1UL)            /**< 25MHz clock selection for Flashboot */
+#define CY_SI_FLASHBOOT_CLK_50MHZ           (2UL)            /**< 50MHz clock selection for Flashboot */
+#define CY_SI_FLASHBOOT_CLK_100MHZ          (3UL)            /**< USER Configuration */
+/** \} group_secure_image_flashboot_clock_macros */
+
+/** \defgroup group_secure_image_flashboot_wait_macros Flash Boot wait window 
+* Debugger wait window selection for Flash boot execution.
+* \{
+*/
+#define CY_SI_FLASHBOOT_WAIT_20MS           (0UL)            /**< 20ms debugger wait window for Flashboot */
+#define CY_SI_FLASHBOOT_WAIT_10MS           (1UL)            /**< 10ms debugger wait window for Flashboot */
+#define CY_SI_FLASHBOOT_WAIT_1MS            (2UL)            /**< 1ms debugger wait window for Flashboot */
+#define CY_SI_FLASHBOOT_WAIT_0MS            (3UL)            /**< 0ms debugger wait window for Flashboot */
+#define CY_SI_FLASHBOOT_WAIT_100MS          (4UL)            /**< 100ms debugger wait window for Flashboot */
+/** \} group_secure_image_flashboot_wait_macros */
+
+/** \defgroup group_secure_image_debug_pin_configuration
+* Debugger pin configuration.
+* \{
+*/
+#define CY_SI_FLASHBOOT_SWJ_DISABLE         (1UL)            /**< Do not enable SWJ pins in Flash boot. Listen window is skipped */
+#define CY_SI_FLASHBOOT_SWJ_ENABLE          (2UL)            /**< Enable SWJ pins in Flash boot  */
+/** \} group_secure_image_debug_pin_configuration */
+
+/** \defgroup group_secure_image_flashboot_validate_macros Flash Boot validation 
+* Flash boot validation selection in chip NORMAL mode.
+* \{
+*/
+#define CY_SI_FLASHBOOT_VALIDATE_DISABLE    (1UL)            /**< Do not validate app1 in NORMAL mode */
+#define CY_SI_FLASHBOOT_VALIDATE_ENABLE     (2UL)            /**< Validate app1 in NORMAL mode */
+/** \} group_secure_image_flashboot_validate_macros */
+
+/** \defgroup group_secure_image_FLASH_LOADER_loader_configuration
+* Flash boot loader configuration.
+* \{
+*/
+#define CY_SI_FLASHBOOT_FBLOADER_ENABLE     (1UL)            /**< Internal bootloader is launched if the other bootloader conditions are met  */
+#define CY_SI_FLASHBOOT_FBLOADER_DISABLE    (2UL)            /**< Internal bootloader is disabled */
+/** \} group_secure_image_FLASH_LOADER_loader_configuration */
+
+/** \defgroup group_secure_image_app_format_macros Application format
+* Application format selection for secure boot.
+* \{
+*/
+#define CY_SI_APP_FORMAT_BASIC              (0UL)               /**< Basic application format (no header) */
+#define CY_SI_APP_FORMAT_CYPRESS            (1UL)               /**< Cypress application format (Cypress header) */
+#define CY_SI_APP_FORMAT_SIMPLIFIED         (2UL)               /**< Simplified application format (no header) */
+/** \} group_secure_image_app_format_macros */
+
+/** \defgroup group_security_enhancement_marker_macros Security enhancement configuration
+* Security enhancement configuration for secure boot.
+* \{
+*/
+#define CY_SECURITY_NOT_ENHANCED            (0x00000000)    /**< No Security Enhanced */
+#define CY_SECURITY_ENHANCED                (0xFEDEEDDF)    /**< Security Enhanced */
+/** \} group_security_enhancement_marker_macros */
+
+/** \defgroup group_secure_image_address_macros Application Addresses 
+* Secure Image and User application addresses. These define the addresses used by both the secure image and
+* secure boot flow and must match those defined in the linker scripts.
+* \{
+*/
+#define CY_SI_SECURE_FLASH_BEGIN            (0x10000000UL)  /**< Secure Image begin Flash address Configure depends on System.*/
+#define CY_SI_USERAPP_FLASH_BEGIN           (0UL)           /**< Non second application image */
+#define CY_SI_SECOND_APP_FLASH_BEGIN        (0x10010000UL)  /**< Second application image begin Flash address Configure depends on System.*/
+/** \} group_secure_image_address_macros */
+
+/** \} group_secure_image_macro */
+
+
+/***************************************
+*         Access Restriction
+***************************************/
+/** \addtogroup group_normal_access_restriction_macro
+* \{
+*/
+
+/** \defgroup group_CM0+_acc_restriction_macros Normal Access restriction
+* Normal Access restriction for CM0+ access port.
+* \{
+*/
+#define CY_SI_CM0_ENABLE                (0UL)  /**< CM0 ACCESS PORT ENABLE */
+#define CY_SI_CM0_DISABLE_TMP           (1UL)  /**< CM0 ACCESS PORT TEMPORARY DISABLE */
+#define CY_SI_CM0_DISABLE               (2UL)  /**< CM0 ACCESS PORT PERMANENTLY_DISABLE */
+/** \} group_CM0+_acc_restriction_macros */
+
+/** \defgroup group_CM7_acc_restriction_macros Normal Access restriction
+* Normal Access restriction for CM7 access port.
+* \{
+*/
+#define CY_SI_CM7_ENABLE                (0UL)  /**< CM7 ACCESS PORT ENABLE */
+#define CY_SI_CM7_DISABLE_TMP           (1UL)  /**< CM7 ACCESS PORT TEMPORARY DISABLE */
+#define CY_SI_CM7_DISABLE               (2UL)  /**< CM7 ACCESS PORT PERMANENTLY_DISABLE */
+/** \} group_CM7_acc_restriction_macros */
+
+/** \defgroup group_SYS_acc_restriction_macros Normal Access restriction
+* Normal Access restriction for System access port.
+* \{
+*/
+#define CY_SI_SYS_ENABLE                (0UL)  /**< SYS ACCESS PORT ENABLE */
+#define CY_SI_SYS_DISABLE_TMP           (1UL)  /**< SYS ACCESS PORT TEMPORARY DISABLE */
+#define CY_SI_SYS_DISABLE               (2UL)  /**< SYS ACCESS PORT PERMANENTLY_DISABLE */
+/** \} group_SYS_acc_restriction_macros */
+
+/** \defgroup group_MPU_enable_macros System access port MPU enable
+* System access port MPU enable.
+* \{
+*/
+#define CY_SI_MPU_DISABLE               (0UL)  /**< MPU disable. Not configure MPU by boot process */
+#define CY_SI_MPU_ENABLE                (1UL)  /**< MPU disable. Configure MPU by boot process */
+/** \} group_MPU_enable_macros */
+
+/** \defgroup group_MPU_direct_exe_macros System access port MPU direct execute configuration
+* System access port MPU direct execute configuration.
+* \{
+*/
+#define CY_SI_DIRECT_EXE_DISABLE        (1UL)  /**< Disable Direct Execute system call functionality */
+#define CY_SI_DIRECT_EXE_ENABLE         (0UL)  /**< Enable Direct Execute system call functionality */
+/** \} group_MPU_direct_exe_macros */
+
+/** \defgroup group_MPU_Flash_acc_macros SYS access port MPU flash access configuration
+* SYS access port MPU flash access configuration.
+* \{
+*/
+#define CY_SI_FLASH_ENABLE              (0UL)  /**< FLASH accessible :Entire region */
+#define CY_SI_FLASH_ENABLE_7_8          (1UL)  /**< FLASH accessible :7/8 */
+#define CY_SI_FLASH_ENABLE_3_4          (2UL)  /**< FLASH accessible :3/4 */
+#define CY_SI_FLASH_ENABLE_HALF         (3UL)  /**< FLASH accessible :HALF */
+#define CY_SI_FLASH_ENABLE_1_4          (4UL)  /**< FLASH accessible :1/4 */
+#define CY_SI_FLASH_ENABLE_1_8          (5UL)  /**< FLASH accessible :1/8 */
+#define CY_SI_FLASH_ENABLE_1_16         (6UL)  /**< FLASH accessible :1/16 */
+#define CY_SI_FLASH_DISABLE             (7UL)  /**< FLASH accessible :NOTHING */
+/** \} group_MPU_Flash_acc_macros */
+
+/** \defgroup group_MPU_RAM0_acc_macros SYS access port MPU RAM0 access configuration
+* SYS access port MPU RAM0 access configuration.
+* \{
+*/
+#define CY_SI_RAM0_ENABLE               (0UL)  /**< RAM0 accessible :Entire region */
+#define CY_SI_RAM0_ENABLE_7_8           (1UL)  /**< RAM0 accessible :7/8 */
+#define CY_SI_RAM0_ENABLE_3_4           (2UL)  /**< RAM0 accessible :3/4 */
+#define CY_SI_RAM0_ENABLE_HAFL          (3UL)  /**< RAM0 accessible :HALF */
+#define CY_SI_RAM0_ENABLE_1_4           (4UL)  /**< RAM0 accessible :1/4 */
+#define CY_SI_RAM0_ENABLE_1_8           (5UL)  /**< RAM0 accessible :1/8 */
+#define CY_SI_RAM0_ENABLE_1_16          (6UL)  /**< RAM0 accessible :1/16 */
+#define CY_SI_RAM0_DISABLE              (7UL)  /**< RAM0 accessible :DISABLE */
+/** \} group_MPU_RAM0_acc_macros */
+
+/** \defgroup group_MPU_WFlash_acc_macros SYS access port MPU work flash access configuration
+* SYS access port MPU work flash access configuration.
+* \{
+*/
+#define CY_SI_WORK_FLASH_ENABLE         (0UL)  /**< WORK FLASH accessible :Entire region */
+#define CY_SI_WORK_FLASH_ENABLE_HALF    (1UL)  /**< WORK FLASH accessible :HALF */
+#define CY_SI_WORK_FLASH_ENABLE_1_4     (2UL)  /**< WORK FLASH accessible :1/4 */
+#define CY_SI_WORK_FLASH_DISABLE        (3UL)  /**< WORK FLASH accessible :NOTHING */
+/** \} group_MPU_WFlash_acc_macros */
+
+/** \defgroup group_MPU_SFlash_acc_macros SYS access port MPU Sflash access configuration
+* SYS access port MPU Sflash access configuration.
+* \{
+*/
+#define CY_SI_SFLASH_ENABLE             (0UL)  /**< SFLASH accessible :Entire region */
+#define CY_SI_SFLASH_ENABLE_HAFL        (1UL)  /**< SFLASH accessible :HALF */
+#define CY_SI_SFLASH_ENABLE_1_4         (2UL)  /**< SFLASH accessible :1/4 */
+#define CY_SI_SFLASH_DISABLE            (3UL)  /**< SFLASH accessible :NOTHING */
+/** \} group_MPU_SFlash_acc_macros */
+
+/** \defgroup group_MPU_MMIO_acc_macros SYS access port MPU MMIO access configuration
+* SYS access port MPU MMIO access configuration.
+* \{
+*/
+#define CY_SI_MMIO_ENABLE               (0UL)  /**< MMIO accessible :All MMIO register */
+#define CY_SI_MMIO_ENABLE_IPC           (1UL)  /**< Only IPC MMIO registers accessible(system calls) */
+#define CY_SI_MMIO_DISABLE              (2UL)  /**< No MMIO access */
+/** \} group_MPU_MMIO_acc_macros */
+
+/** \defgroup group_MPU_SMIF_acc_macros SYS access port MPU SMIF access configuration
+* SYS access port MPU SMIF access configuration.
+* \{
+*/
+#define CY_SI_SMIF_XIP_ENABLE           (0UL)  /**< SMIF XIP Enable */
+#define CY_SI_SMIF_XIP_DISABLE          (1UL)  /**< SMIF XIP Disable */
+/** \} group_MPU_SMIF_acc_macros */
+
+/** \} group_normal_access_restriction_macro */
+
+
+/***************************************
+*    Application Protection
+***************************************/
+/** \addtogroup group_application_protection_macro
+* \{
+*/
+
+/** \defgroup group_SWPU_number_macros Number of SWPU configuration
+* Number of SWPU configuration.
+* \{
+*/
+#define N_FWPU                (0UL)  /**< Number of flash write protection Max 16 Configure depends on System.*/
+#define N_ERPU                (1UL)  /**< Number of efuse read  protection Max  4 Configure depends on System.*/
+#define N_EWPU                (1UL)  /**< Number of efuse write protection Max  4 Configure depends on System.*/
+/** \} group_SWPU_number_macros */
+
+/** \defgroup group_SWPU_enable_attribute_macros SWPU enable and attribute configuration
+* SWPU enable and attribute configuration.
+* \{
+*/
+#define APP_PROT_ENABLE       (1UL)  /**< Application Protection Enable */
+#define APP_PROT_DISABLE      (0UL)  /**< Application Protection Disable */
+#define APP_PROT_ALLOW        (1UL)  /**< Access Allow */
+#define APP_PROT_PROHIBIT     (0UL)  /**< Access Prohibit */
+/** \} group_SWPU_enable_attribute_macros */
+
+/** \} group_application_protection_macro */
+
+
+/***************************************
+*    Application Header
+***************************************/
+/** \addtogroup group_application_header_macro
+* \{
+*/
+
+/** \defgroup group_Secure_Image_virsion_macros Secure Image version configuration
+* Secure Image version configuration.
+* \{
+*/
+#define CY_SI_VERSION_MAJOR             (0UL)       /**< Major version Configure depends on System.*/
+#define CY_SI_VERSION_MINOR             (1UL)       /**< Minor version Configure depends on System.*/
+/** \} group_Secure_Image_virsion_macros */
+
+/** \defgroup group_secure_image_app_type_macros Application type
+* Application type selection for secure boot.
+* \{
+*/
+#define CY_SI_APP_ID_FLASHBOOT          (0x8001UL)  /**< Flash boot ID Type */
+#define CY_SI_APP_ID_SECUREIMG          (0x8002UL)  //(0x0UL)     /**< Secure image ID Type */
+#define CY_SI_APP_ID_BOOTLOADER         (0x8003UL)  /**< Bootloader ID Type */
+/** \} group_secure_image_app_type_macros */
+
+/** \} group_application_header_macro */
+
+
+/***************************************
+*    Application Authentication
+***************************************/
+/** \addtogroup group_application_authentication_macro
+* \{
+*/
+
+/** \defgroup group_applicagtion_image_macros Application image address configuration
+* Application image address configuration for authentication.
+* \{
+*/
+#define CY_SI_SECURE_FLASH_BEGIN_CM7    (0x10020000UL)  /**< Secure Image begin Flash address. Configure depends on System. */
+#define CY_M7_SI_SIZE                   (0x0000FE00UL)  /**< Authentication Size Configure depends on System. */
+#define CY_SI_SIGNATURE_ADDR            (CY_SI_SECURE_FLASH_BEGIN_CM7 + CY_M7_SI_SIZE)  /**< Signature address Configure depends on System. */
+/** \} group_applicagtion_image_macros */
+
+/** \} group_application_authentication_macro */
+
+
+/***************************************
+*            Constants
+***************************************/
+/** \cond INTERNAL */
+
+/* TOC2 */
+#define CY_SI_TOC_FLAGS_CLOCKS_POS          (0UL)           /**< Bit position of Flashboot clock selection */
+#define CY_SI_TOC_FLAGS_DELAY_POS           (2UL)           /**< Bit position of Flashboot wait window selection */
+#define CY_SI_TOC_FLAGS_SWJEN_POS           (5UL)           /**< Bit position of SWJ pin configuration */
+#define CY_SI_TOC_FLAGS_APP_VERIFY_POS      (7UL)           /**< Bit position of Flashboot NORMAL mode app1 validation */
+#define CY_SI_TOC_FLAGS_FBLOADER_ENABLE_POS (9UL)           /**< Bit position of Flashboot Loader Enable */
+
+#define CY_SI_TOC2_OBJECTSIZE               (0x000001FCUL)  /**< Number of TOC2 object */
+#define CY_SI_TOC2_MAGICNUMBER              (0x01211220UL)  /**< TOC2 identifier */
+#define CY_SI_CM71_1stAPP_FLASH_BEGIN       (0UL)           /**< Address of CM7_1 First User Application Object */
+#define CY_SI_CM71_2ndAPP_FLASH_BEGIN       (0UL)           /**< Address of CM7_1 Second User Application Object */
+#define CY_SI_CM72_1stAPP_FLASH_BEGIN       (0UL)           /**< Address of CM7_2 First User Application Object */
+#define CY_SI_CM72_2ndAPP_FLASH_BEGIN       (0UL)           /**< Address of CM7_2 Second User Application Object */
+#define CY_SI_PUBLIC_KEY                    (0x17006400UL)  /**< PUBLIC KEY address in SFlash */
+#define CY_SI_SWPU_BEGIN                    (0x17007600UL)  /**< Address of SWPU configuration */
+#define CY_SI_SECURE_DIGSIG_SIZE            (512u)          /**< Size (in Bytes) of the digital signature for RSA-4K*/
+
+/* Access Restriction */
+#define CY_SI_CM0_AP_POS                    (0UL)  /**< Bit position of CM0 ACCESS PORT*/
+#define CY_SI_CM7_AP_POS                    (2UL)  /**< Bit position of CM7 ACCESS PORT*/
+#define CY_SI_SYS_AP_POS                    (4UL)  /**< Bit position of SYS ACCESS PORT*/
+#define CY_SI_AP_MPU_POS                    (6UL)  /**< Bit position of MPU ACCESS PORT */
+#define CY_SI_DIRECT_EXECUTE_POS            (7UL)  /**< Bit position of DIRECT EXE */
+#define CY_SI_FLASH_POS                     (8UL)  /**< Bit position of FLASH ACCESS */
+#define CY_SI_RAM0_POS                      (11UL) /**< Bit position of RAM0 ACCESS */
+#define CY_SI_WORK_FLASH_POS                (14UL) /**< Bit position of WORK FLASH ACCESS */
+#define CY_SI_SFLASH_POS                    (16UL) /**< Bit position of SFLASH ACCESS */
+#define CY_SI_MMIO_POS                      (18UL) /**< Bit position of MMIO ACCESS */
+#define CY_SI_SMIF_XIP_POS                  (20UL) /**< Bit position of SMIF XIP ACCESS */
+
+/* Application Header */
+#define CY_SI_APP_VERSION     ((CY_SI_VERSION_MAJOR << 24u) | (CY_SI_VERSION_MINOR << 16u)) /**< App Version */
+
+/* Application Protection */
+#define OBJECT_SIZE           (4UL * 4u + N_FWPU *16u + N_ERPU *16u + N_EWPU *16u)  /**< Number of Object Size (bytes) */
+
+/* Application Authentication */
+#define CY_FB_PBKEY_STRUCT_OFFSET  (8u)  /**< Public key offset */
+
+/* Flash boot functions */
+#define CY_SI_IMGVAL_VERIFYAPP_ADDR     ((volatile uint32_t *)0x17002040UL)         /**< Flash boot verify app function address */
+#define CY_SI_IMGVAL_VERIFYAPP_REG      (*(uint32_t *)CY_SI_IMGVAL_VERIFYAPP_ADDR)  /**< Flash boot verify app function register */
+#define CY_SI_IMGVAL_VALIDKEY_ADDR      ((volatile uint32_t *)0x17002044UL)         /**< Flash boot validate key function address */
+#define CY_SI_IMGVAL_VALIDKEY_REG       (*(uint32_t *)CY_SI_IMGVAL_VALIDKEY_ADDR)   /**< Flash boot validate key function register */
+
+
+/***************************************
+*     SFlash function typedefs
+***************************************/
+typedef uint32_t (*sflash_verifyapp_func_t)(uint32_t param0, uint32_t param1, uint32_t param2,
+                                 cy_stc_crypto_rsa_pub_key_t *param3);
+typedef uint32_t (*sflash_validkey_func_t)(uint32_t param0, cy_stc_crypto_rsa_pub_key_t *param1);
+
+
+/***************************************
+*               Structs
+***************************************/
+
+/**
+  * \brief TOC2 Structure
+  */
+typedef struct{
+    volatile uint32_t objSize;          /**< Object size (Bytes) */
+    volatile uint32_t magicNum;         /**< TOC ID (magic number) */
+    volatile uint32_t smifCfgAddr;      /**< SMIF configuration structure */
+    volatile uint32_t cm0pappAddr1;     /**< First user application object address */
+    volatile uint32_t cm0pappFormat1;   /**< First user application format */
+    volatile uint32_t cm0pappAddr2;     /**< Second user application object address */
+    volatile uint32_t cm0pappFormat2;   /**< Second user application format */
+    volatile uint32_t cm71appAddr1;     /**< Second user application format */
+    volatile uint32_t cm71appAddr2;     /**< Second user application format */
+    volatile uint32_t cm72appAddr1;     /**< Second user application format */
+    volatile uint32_t cm72appAddr2;     /**< Second user application format */
+    volatile uint32_t reserved1[52];    /**< Second user application format */
+    volatile uint32_t securityMarker;   /**< Security Update Marker */
+    volatile uint32_t shashObj;         /**< Number of additional objects to be verified (S-HASH) */
+    volatile uint32_t sigKeyAddr;       /**< Signature verification key address */
+    volatile uint32_t swpuAddr;         /**< Address of SWPU object */
+    volatile uint32_t toc2Addr;         /**< Address of TOC2 */
+    volatile uint32_t addObj[58];       /**< Additional objects to include in S-HASH */
+    volatile uint32_t tocFlags;         /**< Flags in TOC to control Flash boot options */
+    volatile uint32_t crc;              /**< Reserved */
+}cy_stc_si_toc_t;
+
+/**
+  * \brief JTAG Restriction Structure
+  */
+typedef struct{
+    volatile uint32_t nar;             /**< Normal Access Restrictions */
+    volatile uint32_t ndar;            /**< Normal Dead Access Restrictions */
+}cy_stc_si_nar_t;
+
+/**
+  * \brief Application Protection structure
+  */
+typedef struct {
+    uint32_t reserved0   : 2;                      /**< Reserved */
+    uint32_t addr30      : 30;                     /**< Base address for FWPU */
+} appprot_flash_write_prot_addr_t;
+
+typedef struct {
+    uint32_t region_size : 30;                     /**< Region size for FWPU */
+    uint32_t reserved0   : 1;                      /**< Reserved */
+    uint32_t enable      : 1;                      /**< Enable for FWPU */
+} appprot_flash_write_prot_size_t;
+
+typedef struct {
+    uint32_t offset      : 16;                     /**< Offset address for ERPU/EWPU */
+    uint32_t reserved0   : 16;                     /**< Reserved */
+} appprot_efuse_prot_offset_t;
+
+typedef struct {
+    uint32_t region_size : 16;                     /**< Region size for ERPU/EWPU */
+    uint32_t reserved0   : 15;                     /**< Reserved */
+    uint32_t enable      : 1;                      /**< Enable for ERPU/EWPU */
+} appprot_efuse_prot_size_t;
+
+typedef struct {
+    uint32_t urw         : 1;                      /**< User accsee attribute */
+    uint32_t prw         : 1;                      /**< Privileged accsee attribute */
+    uint32_t ns          : 1;                      /**< Secure accsee attribute */
+    uint32_t reserved0   : 13;                     /**< Reserved */
+    uint32_t pc_mask     : 16;                     /**< PC mask setting */
+} appprot_prot_att_t;
+
+typedef struct{
+    volatile uint32_t               objSize;       /**< Number of configured elements */
+    volatile uint32_t               n_fwpu;        /**< Number of FWPU objects */
+#if N_FWPU >= 1
+    appprot_flash_write_prot_addr_t fwpu0_adr;     /**< FWPU0 base address */
+    appprot_flash_write_prot_size_t fwpu0_size;    /**< FWPU0 region size and enable */
+    appprot_prot_att_t              fwpu0_sl_att;  /**< FWPU0 slave attribute */
+    appprot_prot_att_t              fwpu0_ms_att;  /**< FWPU0 master attribute */
+#endif
+#if N_FWPU >= 2
+    appprot_flash_write_prot_addr_t fwpu1_adr;     /**< FWPU1 base address */
+    appprot_flash_write_prot_size_t fwpu1_size;    /**< FWPU1 region size and enable */
+    appprot_prot_att_t              fwpu1_sl_att;  /**< FWPU1 slave attribute */
+    appprot_prot_att_t              fwpu1_ms_att;  /**< FWPU1 master attribute */
+#endif
+#if N_FWPU >= 3
+    appprot_flash_write_prot_addr_t fwpu2_adr;     /**< FWPU2 base address */
+    appprot_flash_write_prot_size_t fwpu2_size;    /**< FWPU2 region size and enable */
+    appprot_prot_att_t              fwpu2_sl_att;  /**< FWPU2 slave attribute */
+    appprot_prot_att_t              fwpu2_ms_att;  /**< FWPU2 master attribute */
+#endif
+#if N_FWPU >= 4
+    appprot_flash_write_prot_addr_t fwpu3_adr;     /**< FWPU3 base address */
+    appprot_flash_write_prot_size_t fwpu3_size;    /**< FWPU3 region size and enable */
+    appprot_prot_att_t              fwpu3_sl_att;  /**< FWPU3 slave attribute */
+    appprot_prot_att_t              fwpu3_ms_att;  /**< FWPU3 master attribute */
+#endif
+#if N_FWPU >= 5
+    appprot_flash_write_prot_addr_t fwpu4_adr;     /**< FWPU4 base address */
+    appprot_flash_write_prot_size_t fwpu4_size;    /**< FWPU4 region size and enable */
+    appprot_prot_att_t              fwpu4_sl_att;  /**< FWPU4 slave attribute */
+    appprot_prot_att_t              fwpu4_ms_att;  /**< FWPU4 master attribute */
+#endif
+#if N_FWPU >= 6
+    appprot_flash_write_prot_addr_t fwpu5_adr;     /**< FWPU5 base address */
+    appprot_flash_write_prot_size_t fwpu5_size;    /**< FWPU5 region size and enable */
+    appprot_prot_att_t              fwpu5_sl_att;  /**< FWPU5 slave attribute */
+    appprot_prot_att_t              fwpu5_ms_att;  /**< FWPU5 master attribute */
+#endif
+#if N_FWPU >= 7
+    appprot_flash_write_prot_addr_t fwpu6_adr;     /**< FWPU6 base address */
+    appprot_flash_write_prot_size_t fwpu6_size;    /**< FWPU6 region size and enable */
+    appprot_prot_att_t              fwpu6_sl_att;  /**< FWPU6 slave attribute */
+    appprot_prot_att_t              fwpu6_ms_att;  /**< FWPU6 master attribute */
+#endif
+#if N_FWPU >= 8
+    appprot_flash_write_prot_addr_t fwpu7_adr;     /**< FWPU7 base address */
+    appprot_flash_write_prot_size_t fwpu7_size;    /**< FWPU7 region size and enable */
+    appprot_prot_att_t              fwpu7_sl_att;  /**< FWPU7 slave attribute */
+    appprot_prot_att_t              fwpu7_ms_att;  /**< FWPU7 master attribute */
+#endif
+#if N_FWPU >= 9
+    appprot_flash_write_prot_addr_t fwpu8_adr;     /**< FWPU8 base address */
+    appprot_flash_write_prot_size_t fwpu8_size;    /**< FWPU8 region size and enable */
+    appprot_prot_att_t              fwpu8_sl_att;  /**< FWPU8 slave attribute */
+    appprot_prot_att_t              fwpu8_ms_att;  /**< FWPU8 master attribute */
+#endif
+#if N_FWPU >= 10
+    appprot_flash_write_prot_addr_t fwpu9_adr;     /**< FWPU9 base address */
+    appprot_flash_write_prot_size_t fwpu9_size;    /**< FWPU9 region size and enable */
+    appprot_prot_att_t              fwpu9_sl_att;  /**< FWPU9 slave attribute */
+    appprot_prot_att_t              fwpu9_ms_att;  /**< FWPU9 master attribute */
+#endif
+#if N_FWPU >= 11
+    appprot_flash_write_prot_addr_t fwpu10_adr;    /**< FWPU10 base address */
+    appprot_flash_write_prot_size_t fwpu10_size;   /**< FWPU10 region size and enable */
+    appprot_prot_att_t              fwpu10_sl_att  /**< FWPU10 slave attribute */;
+    appprot_prot_att_t              fwpu10_ms_att  /**< FWPU10 master attribute */;
+#endif
+#if N_FWPU >= 12
+    appprot_flash_write_prot_addr_t fwpu11_adr;    /**< FWPU11 base address */
+    appprot_flash_write_prot_size_t fwpu11_size;   /**< FWPU11 region size and enable */
+    appprot_prot_att_t              fwpu11_sl_att  /**< FWPU11 slave attribute */;
+    appprot_prot_att_t              fwpu11_ms_att  /**< FWPU11 master attribute */;
+#endif
+#if N_FWPU >= 13
+    appprot_flash_write_prot_addr_t fwpu12_adr;    /**< FWPU12 base address */
+    appprot_flash_write_prot_size_t fwpu12_size;   /**< FWPU12 region size and enable */
+    appprot_prot_att_t              fwpu12_sl_att  /**< FWPU12 slave attribute */;
+    appprot_prot_att_t              fwpu12_ms_att  /**< FWPU12 master attribute */;
+#endif
+#if N_FWPU >= 14
+    appprot_flash_write_prot_addr_t fwpu13_adr;    /**< FWPU13 base address */
+    appprot_flash_write_prot_size_t fwpu13_size;   /**< FWPU13 region size and enable */
+    appprot_prot_att_t              fwpu13_sl_att  /**< FWPU13 slave attribute */;
+    appprot_prot_att_t              fwpu13_ms_att  /**< FWPU13 master attribute */;
+#endif
+#if N_FWPU >= 15
+    appprot_flash_write_prot_addr_t fwpu14_adr;    /**< FWPU14 base address */
+    appprot_flash_write_prot_size_t fwpu14_size;   /**< FWPU14 region size and enable */
+    appprot_prot_att_t              fwpu14_sl_att  /**< FWPU14 slave attribute */;
+    appprot_prot_att_t              fwpu14_ms_att  /**< FWPU14 master attribute */;
+#endif
+#if N_FWPU >= 16
+    appprot_flash_write_prot_addr_t fwpu15_adr;    /**< FWPU15 base address */
+    appprot_flash_write_prot_size_t fwpu15_size;   /**< FWPU15 region size and enable */
+    appprot_prot_att_t              fwpu15_sl_att  /**< FWPU15 slave attribute */;
+    appprot_prot_att_t              fwpu15_ms_att  /**< FWPU15 master attribute */;
+#endif
+
+    volatile uint32_t               n_erpu;        /**< Number of ERPU objects */
+#if N_ERPU >= 1
+    appprot_efuse_prot_offset_t     erpu0_offset;  /**< ERPU0 base address offset */
+    appprot_efuse_prot_size_t       erpu0_size;    /**< ERPU0 region size and enable */
+    appprot_prot_att_t              erpu0_sl_att;  /**< ERPU0 slave attribute */
+    appprot_prot_att_t              erpu0_ms_att;  /**< ERPU0 master attribute */
+#endif
+#if N_ERPU >= 2
+    appprot_efuse_prot_offset_t     erpu1_offset;  /**< ERPU1 base address offset */
+    appprot_efuse_prot_size_t       erpu1_size;    /**< ERPU1 region size and enable */
+    appprot_prot_att_t              erpu1_sl_att;  /**< ERPU1 slave attribute */
+    appprot_prot_att_t              erpu1_ms_att;  /**< ERPU1 master attribute */
+#endif
+#if N_ERPU >= 3
+    appprot_efuse_prot_offset_t     erpu2_offset;  /**< ERPU2 base address offset */
+    appprot_efuse_prot_size_t       erpu2_size;    /**< ERPU2 region size and enable */
+    appprot_prot_att_t              erpu2_sl_att;  /**< ERPU2 slave attribute */
+    appprot_prot_att_t              erpu2_ms_att;  /**< ERPU2 master attribute */
+#endif
+#if N_ERPU >= 4
+    appprot_efuse_prot_offset_t     erpu3_offset;  /**< ERPU0 base address offset */
+    appprot_efuse_prot_size_t       erpu3_size;    /**< ERPU0 region size and enable */
+    appprot_prot_att_t              erpu3_sl_att;  /**< ERPU0 slave attribute */
+    appprot_prot_att_t              erpu3_ms_att;  /**< ERPU0 master attribute */
+#endif
+    volatile uint32_t               n_ewpu;        /**< Number of ERPU objects */
+#if N_EWPU >= 1
+    appprot_efuse_prot_offset_t     ewpu0_offset;  /**< EWPU0 base address offset */
+    appprot_efuse_prot_size_t       ewpu0_size;    /**< EWPU0 region size and enable */
+    appprot_prot_att_t              ewpu0_sl_att;  /**< EWPU0 slave attribute */
+    appprot_prot_att_t              ewpu0_ms_att;  /**< EWPU0 master attribute */
+#endif
+#if N_EWPU >= 2
+    appprot_efuse_prot_offset_t     ewpu1_offset;  /**< EWPU1 base address offset */
+    appprot_efuse_prot_size_t       ewpu1_size;    /**< EWPU1 region size and enable */
+    appprot_prot_att_t              ewpu1_sl_att;  /**< EWPU1 slave attribute */
+    appprot_prot_att_t              ewpu1_ms_att;  /**< EWPU1 master attribute */
+#endif
+#if N_EWPU >= 3
+    appprot_efuse_prot_offset_t     ewpu2_offset;  /**< EWPU2 base address offset */
+    appprot_efuse_prot_size_t       ewpu2_size;    /**< EWPU2 region size and enable */
+    appprot_prot_att_t              ewpu2_sl_att;  /**< EWPU2 slave attribute */
+    appprot_prot_att_t              ewpu2_ms_att;  /**< EWPU2 master attribute */
+#endif
+#if N_EWPU >= 4
+    appprot_efuse_prot_offset_t     ewpu3_offset;  /**< EWPU3 base address offset */
+    appprot_efuse_prot_size_t       ewpu3_size;    /**< EWPU3 region size and enable */
+    appprot_prot_att_t              ewpu3_sl_att;  /**< EWPU3 slave attribute */
+    appprot_prot_att_t              ewpu3_ms_att;  /**< EWPU3 master attribute */
+#endif
+}cy_stc_si_app_prot_t;
+
+/**
+  * \brief Application header Structure
+  */
+typedef struct{
+    volatile uint32_t objSize;                   /**< Object size (Bytes) */
+    volatile uint32_t appId;                     /**< Application ID/version */
+    volatile uint32_t appAttributes;             /**< Attributes (reserved for future use) */
+    volatile uint32_t numCores;                  /**< Number of cores */
+    volatile uint32_t core0Vt;                   /**< (CM0+)VT offset - offset to the vector table from that entry */
+    volatile uint32_t core0Id;                   /**< CM0+ core ID */
+}cy_stc_si_appheader_t;
+
+/**
+  * \brief ReadUniqueID API Structure
+  */
+typedef struct
+{
+    uint32_t        : 24;                        /* Reserved */
+    uint32_t Opcode : 8;                         /**< Opecode for ReqdUniqueID API */
+} rd_unique_id_arg0_t;
+
+typedef struct
+{
+    rd_unique_id_arg0_t arg0;                    /** < \ref rd_unique_id_arg0_t */
+    uint32_t            resv[7ul];               /* Reserved */
+} rd_unique_id_args_t;
+
+/**
+  * \brief TransitiontoSecure API Structure
+  */
+typedef struct
+{
+    uint32_t        : 8;                         /* Reserved */
+    uint32_t Debug  : 8;                         /**< Debug flag 1: SECURE_WITH_DEBUG, others: SECURE*/
+    uint32_t        : 8;                         /* Reserved */
+    uint32_t Opcode : 8;                         /**< Opecode for TransitiontoSecure API */
+} trans_to_secure_arg0_t;
+
+typedef struct
+{
+    uint32_t Acc_restrict  : 32;                 /**< Access restriction*/
+} trans_to_secure_arg1_t;
+
+typedef struct
+{
+    uint32_t Dead_Acc_restrict  : 32;            /**< Dead Access restriction*/
+} trans_to_secure_arg2_t;
+
+typedef struct
+{
+    trans_to_secure_arg0_t arg0;                 /** < \ref trans_to_secure_arg0_t */
+    trans_to_secure_arg1_t arg1;                 /** < \ref trans_to_secure_arg1_t */
+    trans_to_secure_arg2_t arg2;                 /** < \ref trans_to_secure_arg2_t */
+    uint32_t               resv[5ul];            /* Reserved */
+} trans_to_secure_args_t;
+
+/**
+  * \brief TransitiontoRMA API Structure
+  */
+typedef struct
+{
+    uint32_t        : 24;                        /* Reserved */
+    uint32_t Opcode : 8;                         /**< Opecode for TransitiontoRMA API */
+} trans_to_rma_arg0_t;
+
+typedef struct
+{
+    uint32_t Objsize : 32;                       /**< Object Size */
+} trans_to_rma_arg1_t;
+
+typedef struct
+{
+    uint32_t CommandId : 32;                     /**< Command ID */
+} trans_to_rma_arg2_t;
+
+typedef struct
+{
+    uint32_t UniqueID_0 : 32;                    /**< Unique ID word 0*/
+} trans_to_rma_arg3_t;
+
+typedef struct
+{
+    uint32_t UniqueID_1 : 32;                    /**< Unique ID word 1*/
+} trans_to_rma_arg4_t;
+
+typedef struct
+{
+    uint32_t UniqueID_2 : 32;                    /**< Unique ID word 2 (3bytes) */
+} trans_to_rma_arg5_t;
+
+typedef struct
+{
+    uint32_t dataAddr : 32;                      /**< Signature address (4bytes) */
+} trans_to_rma_arg6_t;
+
+typedef struct
+{
+    trans_to_rma_arg0_t arg0;                    /** < \ref trans_to_rma_arg0_t */
+    trans_to_rma_arg1_t arg1;                    /** < \ref trans_to_rma_arg1_t */
+    trans_to_rma_arg2_t arg2;                    /** < \ref trans_to_rma_arg2_t */
+    trans_to_rma_arg3_t arg3;                    /** < \ref trans_to_rma_arg3_t */
+    trans_to_rma_arg4_t arg4;                    /** < \ref trans_to_rma_arg4_t */
+    trans_to_rma_arg5_t arg5;                    /** < \ref trans_to_rma_arg5_t */
+    trans_to_rma_arg6_t arg6;                    /** < \ref trans_to_rma_arg6_t */
+    uint32_t            resv[1ul];               /* Reserved */
+} trans_to_rma_args_t;
+
+/**
+  * \brief SROM API Structure
+  */
+typedef union
+{
+    uint32_t               arg[8ul];             /* Reserved */
+    rd_unique_id_args_t    RdUnId;               /**< ReadUniqueID API */
+    trans_to_secure_args_t TransitionToSecure;   /**< TransitiontoSecure API */   
+    trans_to_rma_args_t    TransitionToRMA;      /**< TransitiontoRMA API */
+} srom_api_args_t;
+
+
+/***************************************
+*        Function Prototypes
+***************************************/
+
+/**
+* \addtogroup group_secure_image_functions
+* \{
+*/
+
+/**
+* \addtogroup group_secure_image_functions_direct
+* \{
+*/
+__STATIC_INLINE uint32_t Cy_FB_VerifyApplication(uint32_t address, uint32_t length, uint32_t signature,
+                                 cy_stc_crypto_rsa_pub_key_t *publicKey);
+__STATIC_INLINE uint32_t Cy_FB_IsValidKey(uint32_t tocAddr, cy_stc_crypto_rsa_pub_key_t *publicKey);
+/** \} group_secure_image_functions_direct */
+
+/**
+* \addtogroup group_secure_image_functions_direct
+* \{
+*/
+
+/*******************************************************************************
+* Function Name: Cy_FB_VerifyApplication
+****************************************************************************//**
+*
+* \brief Verifies the secure application digital signature.
+*
+* This function relies on the assumption that the application digital signature
+* was calculated in the following manner:
+* 1. SHA-256 hash of the binary application image is calculated.
+* 2. The hash (digital digest) is signed using a RSA-1024/2056 <b>private</b> 
+*    key to generate the digital signature.
+* 3. The digital signature is placed in the application object in Cypress format.
+*
+* The application verification is performed by performing the following
+* operations:
+* 1. SHA-256 hash of the binary application image is calculated.
+* 2. The application digital signature is decrypted using the RSA-1024/2056
+*    <b>public</b> key.
+* 3. The hash and the decrypted digital signature are compared. If they are
+*    equivalent, the image is valid.
+*
+* \note This is a direct branch to a function residing in SFlash.
+*
+* \param address      
+* Staring address of the application area to be verified with secure signature.
+*
+* \param length
+* The length of the area to be verified.
+* 
+* \param signature
+* Starting address of the signature inside the application residing in Flash.
+* 
+* \param publicKey
+* Pointer to the public key structure.
+*
+* \return
+* - 1 if the digital secure signature verification succeeds.
+* - 0 if the digital secure signature verification of the application fails.
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_FB_VerifyApplication(uint32_t address, uint32_t length, 
+                                        uint32_t signature, cy_stc_crypto_rsa_pub_key_t *publicKey)
+{
+    sflash_verifyapp_func_t fp = (sflash_verifyapp_func_t)CY_SI_IMGVAL_VERIFYAPP_REG;
+    return ( fp(address, length, signature, publicKey) );
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_FB_IsValidKey
+****************************************************************************//**
+*
+* \brief Checks whether the Public Key structure is valid.
+*
+* The public key structure must be as specified as in cy_si_stc_public_key_t.
+* Supported signature schemes are:
+*   0x00: RSASSA-PKCS1-v1_5-2048
+*   0x01: RSASSA-PKCS1-v1_5-1024
+*
+* \note This is a direct branch to a function residing in SFlash.
+*
+* \return
+* - 1 if Public Key has a valid format
+* - 0 if Public Key has an invalid format
+*
+*******************************************************************************/
+__STATIC_INLINE uint32_t Cy_FB_IsValidKey(uint32_t tocAddr, cy_stc_crypto_rsa_pub_key_t *publicKey)
+{
+    sflash_validkey_func_t fp = (sflash_validkey_func_t)CY_SI_IMGVAL_VALIDKEY_REG;
+    return ( fp(tocAddr, publicKey) );
+}
+
+/** \} group_secure_image_functions_direct */
+
+/** \} group_secure_image_functions */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_SI_CONFIG_H */
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/utils/XMC7000/cy_si_keystorage.h b/boot/cypress/platforms/utils/XMC7000/cy_si_keystorage.h
new file mode 100644
index 0000000..647f66e
--- /dev/null
+++ b/boot/cypress/platforms/utils/XMC7000/cy_si_keystorage.h
@@ -0,0 +1,102 @@
+/*******************************************************************************
+* \file cy_si_keystorage.h
+* \version 1.10
+*
+* \brief
+* Secure key storage header for the secure image.
+*
+********************************************************************************
+* \copyright
+* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#ifndef CY_SI_KEYSTORAGE_H
+#define CY_SI_KEYSTORAGE_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include "cy_syslib.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/***************************************
+*               Macros
+***************************************/
+
+/** \addtogroup group_secure_image_macro
+* \{
+*/
+
+/** \defgroup group_secure_image_pubkey_macros Public Key Macros
+* Macros used to define the Public key.
+* \{
+*/    
+#define CY_SI_PUBLIC_KEY_RSA_2048       (0UL)   /**< RSASSA-PKCS1-v1_5-2048 signature scheme */
+#define CY_SI_PUBLIC_KEY_RSA_1024       (1UL)   /**< RSASSA-PKCS1-v1_5-1024 signature scheme */
+#define CY_SI_PUBLIC_KEY_STRUCT_OFFSET  (8UL)   /**< Offset to public key struct in number of bytes */
+#define CY_SI_PUBLIC_KEY_MODULOLENGTH   (256UL) /**< Modulus length of the RSA 2K key */
+/* #define CY_SI_PUBLIC_KEY_MODULOLENGTH   (384UL) */ /**< Modulus length of the RSA 3K key */
+/* #define CY_SI_PUBLIC_KEY_MODULOLENGTH   (512UL) */ /**< Modulus length of the RSA 4K key */
+#define CY_SI_PUBLIC_KEY_EXPLENGTH      (32UL)  /**< Exponent length of the RSA key */
+#define CY_SI_PUBLIC_KEY_SIZEOF_BYTE    (8UL)   /**< Size of Byte in number of bits */
+/** \} group_secure_image_pubkey_macros */
+
+/** \} group_secure_image_macro */
+
+
+/***************************************
+*               Structs
+***************************************/
+
+/**
+* \addtogroup group_secure_image_data_structures
+* \{
+*/
+
+/** Public key definition structure as expected by the Crypto driver */
+typedef struct
+{
+    uint32_t moduloAddr;            /**< Address of the public key modulus */
+    uint32_t moduloSize;            /**< Size (bits) of the modulus part of the public key */
+    uint32_t expAddr;               /**< Address of the public key exponent */
+    uint32_t expSize;               /**< Size (bits) of the exponent part of the public key */
+    uint32_t barrettAddr;           /**< Address of the Barret coefficient */
+    uint32_t inverseModuloAddr;     /**< Address of the binary inverse modulo */
+    uint32_t rBarAddr;              /**< Address of the (2^moduloLength mod modulo) */
+} cy_si_stc_crypto_public_key_t;
+
+/** Public key structure */
+typedef struct
+{
+    uint32_t objSize;                                           /**< Public key Object size */
+    uint32_t signatureScheme;                                   /**< Signature scheme */
+    cy_si_stc_crypto_public_key_t publicKeyStruct;              /**< Public key definition struct */
+    uint8_t  moduloData[CY_SI_PUBLIC_KEY_MODULOLENGTH];         /**< Modulo data */
+    uint8_t  expData[CY_SI_PUBLIC_KEY_EXPLENGTH];               /**< Exponent data */
+    uint8_t  barrettData[CY_SI_PUBLIC_KEY_MODULOLENGTH + 4UL];  /**< Barret coefficient data */
+    uint8_t  inverseModuloData[CY_SI_PUBLIC_KEY_MODULOLENGTH];  /**< Binary inverse modulo data */
+    uint8_t  rBarData[CY_SI_PUBLIC_KEY_MODULOLENGTH];           /**< 2^moduloLength mod modulo data */
+} cy_si_stc_public_key_t;
+
+/** \} group_secure_image_data_structures */
+
+
+/***************************************
+*               Globals
+***************************************/
+
+/** Public key in SFlash */
+extern const cy_si_stc_public_key_t cy_publicKey;
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_SI_KEYSTORAGE_H */
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/utils/XMC7000/cyw_platform_utils.c b/boot/cypress/platforms/utils/XMC7000/cyw_platform_utils.c
new file mode 100644
index 0000000..5e87042
--- /dev/null
+++ b/boot/cypress/platforms/utils/XMC7000/cyw_platform_utils.c
@@ -0,0 +1,79 @@
+/***************************************************************************//**
+* \file cyw_platform_utils.h
+*
+* \brief
+* xmc7000 platform utilities
+*
+********************************************************************************
+* \copyright
+* (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <string.h>
+#include "cyw_platform_utils.h"
+
+#define IVT_ALIGNMENT (0x3FFu) /* IVT alignment requires to have these bits as zeros in IVT */
+#define STACK_ALIGNMENT (7u) /* Per ARM AABI, a stack should be aligned to 64 bits, thus should have these bits as zeros */
+#define THUMB_CALL_MASK (1u) /* THUMB ISA requires the LSB of a function call address to be 1 */
+
+/* Symbols below are provided by the linker script: */
+extern uint8_t __data_start__[];
+extern uint8_t __data_end__[];
+
+extern uint8_t __bss_start__[];
+extern uint8_t __bss_end__[];
+
+extern uint8_t __HeapBase[];
+extern uint8_t __HeapLimit[];
+
+extern uint8_t __StackLimit[];
+extern uint8_t __StackTop[];
+
+/* An app begins with vector table that starts with: */
+typedef struct
+{
+    uint32_t stack_pointer;
+    void (*reset_handler)(void);
+} vect_tbl_start_t;
+
+/**
+ * Starts the application on the current core. MCUBoot is also running on
+ * this core, so we just clean up memory, set up the vector table and stack,
+ * and transfer control to the app's reset handler.
+ *
+ * @param app_addr  FIH-protected address of the app's vector table.
+ */
+void xmc7000_launch_cm7_app(fih_uint app_addr)
+{
+    register vect_tbl_start_t* const vect_tbl1 = (vect_tbl_start_t*)fih_uint_decode(app_addr);
+
+#if defined(APP_CORE_ID)
+# if APP_CORE_ID == 0
+    Cy_SysEnableCM7(CORE_CM7_0, (uintptr_t)vect_tbl1);
+# elif APP_CORE_ID == 1
+    Cy_SysEnableCM7(CORE_CM7_1, (uintptr_t)vect_tbl1);
+# endif
+#else
+# error "APP_CORE_ID is incorrect"
+#endif
+
+    for(;;)
+    {
+        (void)Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT);
+    }
+}
diff --git a/boot/cypress/platforms/utils/XMC7000/cyw_platform_utils.h b/boot/cypress/platforms/utils/XMC7000/cyw_platform_utils.h
new file mode 100644
index 0000000..87c7dc1
--- /dev/null
+++ b/boot/cypress/platforms/utils/XMC7000/cyw_platform_utils.h
@@ -0,0 +1,34 @@
+/***************************************************************************//**
+* \file cyw_platform_utils.h
+*
+* \brief
+* PSoC6 platform utilities
+*
+********************************************************************************
+* \copyright
+* (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#ifndef CYW_PLATFORMS_UTILS_H
+#define CYW_PLATFORMS_UTILS_H
+
+#include "cy_pdl.h"
+#include "bootutil/fault_injection_hardening.h"
+
+void xmc7000_launch_cm7_app(fih_uint app_addr);
+
+#endif /* CYW_PLATFORMS_UTILS_H */
diff --git a/boot/cypress/scripts/feature.py b/boot/cypress/scripts/feature.py
new file mode 100644
index 0000000..4bc428c
--- /dev/null
+++ b/boot/cypress/scripts/feature.py
@@ -0,0 +1,251 @@
+"""
+Copyright 2023 Cypress Semiconductor Corporation (an Infineon company)
+or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+
+import sys
+import json
+import click
+
+def load_json(file_path):
+    """
+    Loads JSON from file.
+    """
+
+    data_json = None
+
+    try:
+        with open(file_path, encoding="utf-8") as file:
+            data_json = json.load(file)
+
+    except FileNotFoundError:
+        print(f'\nERROR: Cannot find {file_path}')
+        sys.exit(-1)
+
+    return data_json
+
+
+class FieldsValidator:
+    """
+        Validation of required fields and their cross-dependencies.
+    """
+
+    @staticmethod
+    def validate(feature_json, properties_json):
+        """
+            Check 'target' and properties of a platform.
+        """
+        p_target = properties_json.get('target')
+        if p_target is None:
+            raise AttributeError('Field "target" must be present in platform_properties.json')
+
+        f_target = feature_json.get('target')
+        if f_target is None:
+            raise AttributeError('Field "target" must be present in a feature_config.json')
+
+        if f_target not in p_target:
+            raise AttributeError('Target in feature config is not correct.'
+                                    ' It must be among the target list of platform_properties.json')
+
+        f_security_setup = feature_json.get('security_setup')
+        p_security_setup = properties_json.get('security_setup')
+
+        if f_security_setup:
+
+            if p_security_setup is None:
+                raise AttributeError("This platform doesn't have any 'secure_setup' features")
+
+            if f_security_setup.get('hw_rollback_prot'):
+                if p_security_setup.get('hw_rollback_prot') is None:
+                    raise AttributeError("This platform doesn't have HW anti roll-back counter")
+
+            if f_security_setup.get('hw_crypto_acceleration'):
+                if p_security_setup.get('hw_crypto_acceleration') is None:
+                    raise AttributeError("The platform doesn't support HW crypto acceleration")
+
+            if f_security_setup.get('validate_upgrade').get('value') is False:
+                raise AttributeError("Deactivation of image validation during the upgrade \
+                                        process isn't implemented yet")
+
+
+class FeatureProcessor:
+
+    """
+        The general handler of all needed fields and filling the new mk-file.
+    """
+
+    settings_dict = {
+        'validate_boot'             :   'MCUBOOT_SKIP_IMAGE_VALIDATION',
+        'validate_upgrade'          :   'MCUBOOT_SKIP_UPGRADE_VALIDATION',
+        'dependency_check'          :   'MCUBOOT_DEPENDENCY_CHECK',
+        'serial_logging'            :   'MCUBOOT_LOG_LEVEL',
+        'hw_rollback_prot'          :   'USE_HW_ROLLBACK_PROT',
+        'hw_crypto_acceleration'    :   "USE_CRYPTO_HW",
+        'sw_downgrade_prev'         :   'USE_SW_DOWNGRADE_PREV',
+        'ram_app_staging'           :   'USE_STAGE_RAM_APPS',
+        'xip'                       :   'USE_XIP',
+        'image_encryption'          :   'ENC_IMG',
+        'fault_injection_hardening' :   'FIH_PROFILE_LEVEL',
+        'combine_hex'               :   'COMBINE_HEX',
+        'hw_key'                    :   'USE_HW_KEY'
+    }
+
+    debug_level_dict = {
+        'off'       :   '_OFF',
+        'error'     :   '_ERROR',
+        'warning'   :   '_WARNING',
+        'info'      :   '_INFO',
+        'debug'     :   '_DEBUG'
+    }
+
+    fih_level_dict = {
+        'off'       :   'OFF',
+        'low'       :   'LOW',
+        'medium'    :   'MEDIUM',
+        'high'      :   'HIGH'
+    }
+
+    def __init__(self, output_name):
+        self.out_f = output_name
+
+    @staticmethod
+    def generate_header_guard():
+        """
+            Print header line at the begining of a mk-file
+        """
+        guard_lines = ('# AUTO-GENERATED FILE, DO NOT EDIT.'
+                        ' ALL CHANGES WILL BE LOST! #\n\n')
+
+        return guard_lines
+
+    @staticmethod
+    def insert_res(val_to_check) -> str:
+        """
+            Simlpe check result and return the string with value.
+        """
+        return f' := {1 if val_to_check else 0}\n'
+
+    @staticmethod
+    def insert_inverted_res(val_to_check) -> str:
+        """
+            Simlpe check result and return the string with inverted value.
+        """
+        return f' := {0 if val_to_check else 1}\n'
+
+    def __prnt_dict_primitive_key(self, dict_feature_config, settings_dict_key, f_out):
+        """
+            Print kyes of 'feature_config' with bool type of 'value'
+        """
+        val = dict_feature_config.get(settings_dict_key).get('value')
+
+        if isinstance(val, bool):
+
+            # invert because variable use 'skip' command
+            need_invertion = set(("validate_boot", "validate_upgrade"))
+
+            f_out.write(self.settings_dict[settings_dict_key])
+
+            if settings_dict_key not in need_invertion:
+                f_out.write(FeatureProcessor.insert_res(val))
+            else:
+                f_out.write(FeatureProcessor.insert_inverted_res(val))
+
+
+    def __gen_fih_level(self, fih_value):
+        """
+            Print only FIH_
+        """
+        res = f"{self.settings_dict['fault_injection_hardening']} ?= "\
+              f"{self.fih_level_dict[fih_value]}\n"
+
+        return res
+
+    def __gen_debug_level(self, logging_value):
+        """
+            Print only MCUBOOT_LOG_LEVEL
+        """
+        param_txt = self.settings_dict['serial_logging']
+        res_str = f"{param_txt} ?= {param_txt}{self.debug_level_dict[logging_value]}\n"
+
+        return res_str
+
+
+    def __handle_dictionary(self, f_dict, f_out):
+        """
+            Handle any dictionary of 'feature_config'
+        """
+        dont_print_list = set(("validation_key", "version", "description", "target"))
+
+        for k in f_dict:
+
+            if k not in dont_print_list:
+                self.__prnt_dict_primitive_key(f_dict, k, f_out)
+
+            if k == 'fault_injection_hardening':
+                f_out.write(self.__gen_fih_level(f_dict.get(k).get("value")))
+
+            if k == 'serial_logging':
+                f_out.write(self.__gen_debug_level(f_dict.get(k).get("value")))
+
+
+    def make_file_generate(self, feature_json):
+        """
+            Processing all keys and creation of a mk-file
+        """
+
+        with open(self.out_f, "w", encoding='UTF-8') as f_out:
+            f_out.write(FeatureProcessor.generate_header_guard())
+
+            f_security_setup_dict = feature_json.get('security_setup')
+
+            # handling of 'security_setup' section
+            if f_security_setup_dict:
+                self.__handle_dictionary(f_security_setup_dict, f_out)
+
+            self.__handle_dictionary(feature_json, f_out)
+
+
+@click.group()
+def cli():
+    """
+        Feature config parser to run from CLI
+    """
+
+@cli.command()
+@click.option('-f', '--feature_config', required=True,
+              help='feature configuration file path')
+@click.option('-p', '--platform_properties', required=True,
+              help='platform properties file path')
+@click.option('-n', '--output_name', required=True,
+              help='the name of the make file that will be generated')
+
+
+def run(feature_config, platform_properties, output_name):
+    """
+        The main CLI command to run mk-file generation
+    """
+
+    feature_config_json = load_json(feature_config)
+    platform_properties_json = load_json(platform_properties)
+
+    FieldsValidator.validate(feature_config_json, platform_properties_json)
+
+    fprocessor = FeatureProcessor(output_name)
+    fprocessor.make_file_generate(feature_config_json)
+
+
+if __name__ == '__main__':
+    cli()
diff --git a/boot/cypress/scripts/find_cysectools.py b/boot/cypress/scripts/find_cysectools.py
index 9aae88e..7bea0fc 100644
--- a/boot/cypress/scripts/find_cysectools.py
+++ b/boot/cypress/scripts/find_cysectools.py
@@ -17,7 +17,7 @@
 import subprocess
 import sys
 
-package = 'cysecuretools' 
+package = 'cysecuretools'
 
 def find_cysectools(package_name):
 
diff --git a/boot/cypress/scripts/flashmap.py b/boot/cypress/scripts/flashmap.py
deleted file mode 100644
index 856e430..0000000
--- a/boot/cypress/scripts/flashmap.py
+++ /dev/null
@@ -1,935 +0,0 @@
-"""MCUBoot Flash Map Converter (JSON to .h)
-Copyright (c) 2022 Infineon Technologies AG
-"""
-
-import sys
-import getopt
-import json
-
-# Supported Platforms
-cm0pCore = {
-    'cortex-m0+': 'CM0P',
-    'cm0+': 'CM0P',
-    'm0+': 'CM0P',
-    'cortex-m0p': 'CM0P',
-    'cm0p': 'CM0P',
-    'm0p': 'CM0P',
-    'cortex-m0plus': 'CM0P',
-    'cm0plus': 'CM0P',
-    'm0plus': 'CM0P'
-}
-
-cm4Core = {
-    'cortex-m4': 'CM4',
-    'cm4': 'CM4',
-    'm4': 'CM4'
-}
-
-cm33Core = {
-    'cortex-m33': 'CM33',
-    'cm33': 'CM33',
-    'm33': 'CM33'
-}
-
-allCores_PSOC_06x = {**cm0pCore, **cm4Core}
-
-common_PSOC_061 = {
-    'flashAddr': 0x10000000,
-    'eraseSize': 0x200,  # 512 bytes
-    'smifAddr': 0x18000000,
-    'smifSize': 0x8000000,  # i.e., window size
-    'VTAlign': 0x400,  # Vector Table alignment
-    'allCores': cm4Core,
-    'bootCore': 'Cortex-M4',
-    'appCore': 'Cortex-M4'
-}
-
-common_PSOC_06x = {
-    'flashAddr': 0x10000000,
-    'eraseSize': 0x200,  # 512 bytes
-    'smifAddr': 0x18000000,
-    'smifSize': 0x8000000,  # i.e., window size
-    'VTAlign': 0x400,  # Vector Table alignment
-    'allCores': allCores_PSOC_06x,
-    'bootCore': 'Cortex-M0+',
-    'appCore': 'Cortex-M4'
-}
-
-platDict = {
-    'PSOC_061_2M': {
-        'flashSize': 0x200000,  # 2 MBytes
-        **common_PSOC_061
-    },
-    'PSOC_061_1M': {
-        'flashSize': 0x100000,  # 1 MByte
-        **common_PSOC_061
-    },
-    'PSOC_061_512K': {
-        'flashSize': 0x80000,  # 512 KBytes
-        **common_PSOC_061
-    },
-
-    'PSOC_062_2M': {
-        'flashSize': 0x200000,  # 2 MBytes
-        **common_PSOC_06x
-    },
-    'PSOC_062_1M': {
-        'flashSize': 0x100000,  # 1 MByte
-        **common_PSOC_06x
-    },
-    'PSOC_062_512K': {
-        'flashSize': 0x80000,  # 512 KBytes
-        **common_PSOC_06x
-    },
-
-    'PSOC_063_1M': {
-        'flashSize': 0x100000,  # 1 MByte
-        **common_PSOC_06x
-    },
-
-    'CYW20829': {
-        'flashSize': 0,  # n/a
-        'smifAddr': 0x60000000,
-        'smifSize': 0x8000000,  # i.e., window size
-        'VTAlign': 0x200,  # Vector Table alignment
-        'allCores': cm33Core,
-        'bootCore': 'Cortex-M33',
-        'appCore': 'Cortex-M33',
-        'bitsPerCnt': False
-    },
-
-
-}
-
-# Supported SPI Flash ICs
-flashDict = {
-    # Fudan
-    'FM25Q04': {
-        'flashSize': 0x80000,  # 4 Mbits
-        'eraseSize': 0x1000,  # 128 uniform sectors with 4K-byte each
-    },
-    'FM25W04': {
-        'flashSize': 0x80000,  # 4 Mbits
-        'eraseSize': 0x1000,  # 128 uniform sectors with 4K-byte each
-    },
-    'FM25Q08': {
-        'flashSize': 0x100000,  # 8 Mbits
-        'eraseSize': 0x1000,  # 256 uniform sectors with 4K-byte each
-    },
-    'FM25W08': {
-        'flashSize': 0x100000,  # 8 Mbits
-        'eraseSize': 0x1000,  # 256 uniform sectors with 4K-byte each
-    },
-    # Puya
-    'P25Q05H': {
-        'flashSize': 0x10000,  # 512 Kbits
-        'eraseSize': 0x1000,  # Uniform 4K-byte Sector Erase
-    },
-    'P25Q10H': {
-        'flashSize': 0x20000,  # 1 Mbit
-        'eraseSize': 0x1000,  # Uniform 4K-byte Sector Erase
-    },
-    'P25Q20H': {
-        'flashSize': 0x40000,  # 2 Mbits
-        'eraseSize': 0x1000,  # Uniform 4K-byte Sector Erase
-    },
-    'P25Q40H': {
-        'flashSize': 0x80000,  # 4 Mbits
-        'eraseSize': 0x1000,  # Uniform 4K-byte Sector Erase
-    },
-    # Infineon
-    'S25HS256T': {
-        'flashSize': 0x2000000,  # 256 Mbits
-        'eraseSize': 0x40000,  # Uniform Sector Architecture
-    },
-    'S25HS512T': {
-        'flashSize': 0x4000000,  # 512 Mbits
-        'eraseSize': 0x40000,  # Uniform Sector Architecture
-    },
-    'S25HS01GT': {
-        'flashSize': 0x8000000,  # 1 Gbit
-        'eraseSize': 0x40000,  # Uniform Sector Architecture
-    }
-}
-
-
-def is_overlap(fa1off, fa1size, fa2off, fa2size, align):
-    """Check if two flash areas on the same device overlap"""
-    mask = align - 1
-    assert align > 0 and (align & mask) == 0  # ensure align is a power of 2
-    fa1end = (fa1off + fa1size + mask) & ~mask
-    fa2end = (fa2off + fa2size + mask) & ~mask
-    fa1off = fa1off & ~mask
-    fa2off = fa2off & ~mask
-    return fa1off < fa2end and fa2off < fa1end
-
-
-def is_same_mem(fa1addr, fa2addr):
-    """Check if two addresses belong to the same memory"""
-    if fa1addr is None or fa2addr is None:
-        return False
-    mask = 0xFF000000
-    return (fa1addr & mask) == (fa2addr & mask)
-
-
-class CmdLineParams:
-    """Command line parameters"""
-
-    def __init__(self):
-        self.plat_id = ''
-        self.in_file = ''
-        self.out_file = ''
-        self.img_id = None
-        self.policy = None
-        self.set_core = False
-
-        usage = 'USAGE:\n' + sys.argv[0] + \
-                ''' -p <platform> -i <flash_map.json> -o <flash_map.h> -d <img_id>
-
-OPTIONS:
--h  --help       Display the usage information
--p  --platform=  Target (e.g., PSOC_062_512K)
--i  --ifile=     JSON flash map file
--o  --ofile=     C header file to be generated
--d  --img_id     ID of application to build
--c  --policy     Policy file in JSON format
--m  --core       Detect and set Cortex-M CORE
-'''
-
-        try:
-            opts, unused = getopt.getopt(
-                sys.argv[1:], 'hi:o:p:d:c:m',
-                ['help', 'platform=', 'ifile=', 'ofile=', 'img_id=', 'policy=', 'core'])
-            if len(unused) > 0:
-                print(usage, file=sys.stderr)
-                sys.exit(1)
-        except getopt.GetoptError:
-            print(usage, file=sys.stderr)
-            sys.exit(1)
-
-        for opt, arg in opts:
-            if opt in ('-h', '--help'):
-                print(usage, file=sys.stderr)
-                sys.exit()
-            elif opt in ('-p', '--platform'):
-                self.plat_id = arg
-            elif opt in ('-i', '--ifile'):
-                self.in_file = arg
-            elif opt in ('-o', '--ofile'):
-                self.out_file = arg
-            elif opt in ('-d', '--img_id'):
-                self.img_id = arg
-            elif opt in ('-c', '--policy'):
-                self.policy = arg
-            elif opt in ('-m', '--core'):
-                self.set_core = True
-
-        if len(self.in_file) == 0 or len(self.out_file) == 0:
-            print(usage, file=sys.stderr)
-            sys.exit(1)
-
-
-class AreaList:
-    """List of flash areas"""
-
-    def __init__(self, plat, flash, use_overwrite):
-        self.plat = plat
-        self.flash = flash
-        self.use_overwrite = use_overwrite
-        self.areas = []
-        self.peers = {}
-        self.trailers = {}
-        self.internal_flash = False
-        self.external_flash = False
-        self.external_flash_xip = False
-
-    def get_min_erase_size(self):
-        """Calculate minimum erase block size for int./ext. Flash """
-        return self.plat['eraseSize'] if self.plat['flashSize'] > 0 \
-            else self.flash['eraseSize']
-
-    def get_img_trailer_size(self):
-        """Calculate image trailer size"""
-        return self.get_min_erase_size()
-
-    def process_int_area(self, title, fa_addr, fa_size,
-                         img_trailer_size, shared_slot):
-        """Process internal flash area"""
-        fa_device_id = 'FLASH_DEVICE_INTERNAL_FLASH'
-        fa_off = fa_addr - self.plat['flashAddr']
-        if img_trailer_size is not None:
-            if self.use_overwrite:
-                if shared_slot:
-                    print('Shared slot', title,
-                          'is not supported in OVERWRITE mode',
-                          file=sys.stderr)
-                    sys.exit(7)
-            else:
-                # Check trailer alignment (start at the sector boundary)
-                align = (fa_off + fa_size - img_trailer_size) % \
-                        self.plat['eraseSize']
-                if align != 0:
-                    fa_addr += self.plat['eraseSize'] - align
-                    if fa_addr + fa_size <= \
-                            self.plat['flashAddr'] + self.plat['flashSize']:
-                        print('Misaligned', title,
-                              '- suggested address', hex(fa_addr),
-                              file=sys.stderr)
-                    else:
-                        print('Misaligned', title, file=sys.stderr)
-                    sys.exit(7)
-        else:
-            # Check alignment (flash area should start at the sector boundary)
-            if fa_off % self.plat['eraseSize'] != 0:
-                print('Misaligned', title, file=sys.stderr)
-                sys.exit(7)
-        slot_sectors = int((fa_off % self.plat['eraseSize'] +
-                            fa_size + self.plat['eraseSize'] - 1) //
-                           self.plat['eraseSize'])
-        return fa_device_id, fa_off, slot_sectors
-
-    def process_ext_area(self, title, fa_addr, fa_size,
-                         img_trailer_size, shared_slot):
-        """Process external flash area"""
-        if self.flash is None:
-            print('Unspecified SPI Flash IC',
-                  file=sys.stderr)
-            sys.exit(3)
-        if fa_addr + fa_size <= \
-                self.plat['smifAddr'] + self.flash['flashSize']:
-            flash_idx = 'CY_BOOT_EXTERNAL_DEVICE_INDEX'
-            fa_device_id = f'FLASH_DEVICE_EXTERNAL_FLASH({flash_idx})'
-            fa_off = fa_addr - self.plat['smifAddr']
-        else:
-            print('Misfitting', title, file=sys.stderr)
-            sys.exit(7)
-        if img_trailer_size is not None:
-            if self.use_overwrite:
-                if shared_slot:
-                    print('Shared slot', title,
-                          'is not supported in OVERWRITE mode',
-                          file=sys.stderr)
-                    sys.exit(7)
-            else:
-                # Check trailer alignment (start at the sector boundary)
-                align = (fa_off + fa_size - img_trailer_size) % \
-                        self.flash['eraseSize']
-                if align != 0:
-                    peer_addr = self.peers.get(fa_addr)
-                    if shared_slot:
-                        # Special case when using both int. and ext. memory
-                        if self.plat['flashSize'] > 0 and \
-                                align % self.plat['eraseSize'] == 0:
-                            print('Note:', title, 'requires', align,
-                                  'padding bytes before trailer',
-                                  file=sys.stderr)
-                        else:
-                            print('Misaligned', title, file=sys.stderr)
-                            sys.exit(7)
-                    elif is_same_mem(fa_addr, peer_addr) and \
-                            fa_addr % self.flash['eraseSize'] == \
-                            peer_addr % self.flash['eraseSize']:
-                        pass  # postpone checking
-                    else:
-                        fa_addr += self.flash['eraseSize'] - align
-                        if fa_addr + fa_size <= \
-                                self.plat['smifAddr'] + self.flash['flashSize']:
-                            print('Misaligned', title,
-                                  '- suggested address', hex(fa_addr),
-                                  file=sys.stderr)
-                        else:
-                            print('Misaligned', title, file=sys.stderr)
-                        sys.exit(7)
-        else:
-            # Check alignment (flash area should start at the sector boundary)
-            if fa_off % self.flash['eraseSize'] != 0:
-                print('Misaligned', title, file=sys.stderr)
-                sys.exit(7)
-        slot_sectors = int((fa_off % self.flash['eraseSize'] +
-                            fa_size + self.flash['eraseSize'] - 1) //
-                           self.flash['eraseSize'])
-        self.external_flash = True
-        if self.flash['XIP']:
-            self.external_flash_xip = True
-        return fa_device_id, fa_off, slot_sectors
-
-    def chk_area(self, fa_addr, fa_size, peer_addr=None):
-        """Check area location (internal/external flash)"""
-        if peer_addr is not None:
-            self.peers[peer_addr] = fa_addr
-        fa_limit = fa_addr + fa_size
-        if self.plat['flashSize'] and \
-                fa_addr >= self.plat['flashAddr'] and \
-                fa_limit <= self.plat['flashAddr'] + self.plat['flashSize']:
-            # Internal flash
-            self.internal_flash = True
-
-    def add_area(self, title,
-                 fa_id, fa_addr, fa_size,
-                 img_trailer_size=None, shared_slot=False):
-        """Add flash area to AreaList.
-        Internal/external flash is detected by address.
-        Returns number of sectors in a slot"""
-        if fa_size == 0:
-            print('Empty', title, file=sys.stderr)
-            sys.exit(7)
-
-        fa_limit = fa_addr + fa_size
-        if self.plat['flashSize'] and \
-                fa_addr >= self.plat['flashAddr'] and \
-                fa_limit <= self.plat['flashAddr'] + self.plat['flashSize']:
-            # Internal flash
-            fa_device_id, fa_off, slot_sectors = self.process_int_area(
-                title, fa_addr, fa_size, img_trailer_size, shared_slot)
-            align = self.plat['eraseSize']
-        elif self.plat['smifSize'] and \
-                fa_addr >= self.plat['smifAddr'] and \
-                fa_limit <= self.plat['smifAddr'] + self.plat['smifSize']:
-            # External flash
-            fa_device_id, fa_off, slot_sectors = self.process_ext_area(
-                title, fa_addr, fa_size, img_trailer_size, shared_slot)
-            align = self.flash['eraseSize']
-        else:
-            print('Invalid', title, file=sys.stderr)
-            sys.exit(7)
-
-        if shared_slot:
-            assert img_trailer_size is not None
-            tr_addr = fa_addr + fa_size - img_trailer_size
-            tr_name = self.trailers.get(tr_addr)
-            if tr_name is not None:
-                print('Same trailer address for', title, 'and', tr_name,
-                      file=sys.stderr)
-                sys.exit(7)
-            self.trailers[tr_addr] = title
-
-        # Ensure no flash areas on this device will overlap, except the
-        # shared slot
-        for area in self.areas:
-            if fa_device_id == area['fa_device_id']:
-                over = is_overlap(fa_off, fa_size,
-                                  area['fa_off'], area['fa_size'],
-                                  align)
-                if shared_slot and area['shared_slot']:
-                    if not over:  # images in shared slot should overlap
-                        print(title, 'is not shared with', area['title'],
-                              file=sys.stderr)
-                        sys.exit(7)
-                elif over:
-                    print(title, 'overlaps with', area['title'],
-                          file=sys.stderr)
-                    sys.exit(7)
-
-        self.areas.append({'title': title,
-                           'shared_slot': shared_slot,
-                           'fa_id': fa_id,
-                           'fa_device_id': fa_device_id,
-                           'fa_off': fa_off,
-                           'fa_size': fa_size})
-        return slot_sectors
-
-    def generate_c_source(self, params):
-        """Generate C source"""
-        c_array = 'flash_areas'
-
-        try:
-            with open(params.out_file, "w", encoding='UTF-8') as out_f:
-                out_f.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
-                            ' ALL CHANGES WILL BE LOST! */\n')
-                out_f.write(f'/* Platform: {params.plat_id} */\n')
-                out_f.write("#ifndef CY_FLASH_MAP_H\n")
-                out_f.write("#define CY_FLASH_MAP_H\n\n")
-
-                if self.plat.get('bitsPerCnt'):
-                    out_f.write('#ifdef NEED_FLASH_MAP\n')
-                out_f.write(f'static struct flash_area {c_array}[] = {{\n')
-                comma = len(self.areas)
-                area_count = 0
-                for area in self.areas:
-                    comma -= 1
-                    if area['fa_id'] is not None:
-                        sss = ' /* Shared secondary slot */' \
-                            if area['shared_slot'] else ''
-                        out_f.writelines('\n'.join([
-                            '    {' + sss,
-                            f"        .fa_id        = {area['fa_id']},",
-                            f"        .fa_device_id = {area['fa_device_id']},",
-                            f"        .fa_off       = {hex(area['fa_off'])}U,",
-                            f"        .fa_size      = {hex(area['fa_size'])}U",
-                            '    },' if comma else '    }', '']))
-                        area_count += 1
-                out_f.write('};\n\n'
-                            'struct flash_area *boot_area_descs[] = {\n')
-                for area_index in range(area_count):
-                    out_f.write(f'    &{c_array}[{area_index}U],\n')
-                out_f.write('    NULL\n};\n')
-
-                if self.plat.get('bitsPerCnt'):
-                    out_f.write('#endif /* NEED_FLASH_MAP */\n')
-                    out_f.close()
-
-                    # inserted here to fix misra 'header guard'
-                    list_counters = process_policy_20829(params.policy)
-                    if list_counters is not None:
-                        form_max_counter_array(list_counters, params.out_file)
-                    with open(params.out_file, "a", encoding='UTF-8') as out_f:
-                        out_f.write("#endif /* CY_FLASH_MAP_H */\n")
-                else:
-                    out_f.write("#endif /* CY_FLASH_MAP_H */\n")
-
-        except (FileNotFoundError, OSError):
-            print('Cannot create', params.out_file, file=sys.stderr)
-            sys.exit(4)
-
-
-def cvt_dec_or_hex(val, desc):
-    """Convert (hexa)decimal string to number"""
-    try:
-        return int(val, 0)
-    except ValueError:
-        print('Invalid value', val, 'for', desc, file=sys.stderr)
-        sys.exit(6)
-
-
-def get_val(obj, attr):
-    """Get JSON 'value'"""
-    obj = obj[attr]
-    try:
-        return cvt_dec_or_hex(obj['value'], obj['description'])
-    except KeyError as key:
-        print('Malformed JSON:', key,
-              'is missing in', "'" + attr + "'",
-              file=sys.stderr)
-        sys.exit(5)
-
-
-def get_bool(obj, attr, def_val=False):
-    """Get JSON boolean value (returns def_val if it is missing)"""
-    ret_val = def_val
-    obj = obj.get(attr)
-    if obj is not None:
-        try:
-            val = str(obj['value']).lower()
-            desc = obj['description']
-            if val == 'true':
-                ret_val = True
-            elif val == 'false':
-                ret_val = False
-            else:
-                print('Invalid value', val, 'for', desc, file=sys.stderr)
-                sys.exit(6)
-        except KeyError as key:
-            print('Malformed JSON:', key,
-                  'is missing in', "'" + attr + "'",
-                  file=sys.stderr)
-            sys.exit(5)
-    return ret_val
-
-
-def get_str(obj, attr, def_val=None):
-    """Get JSON string value (returns def_val if it is missing)"""
-    ret_val = def_val
-    obj = obj.get(attr)
-    if obj is not None:
-        try:
-            ret_val = str(obj['value'])
-        except KeyError as key:
-            print('Malformed JSON:', key,
-                  'is missing in', "'" + attr + "'",
-                  file=sys.stderr)
-            sys.exit(5)
-    return ret_val
-
-
-class AddrSize:
-    """Bootloader area"""
-
-    def __init__(self, bootloader, addr_name, size_name):
-        self.fa_addr = get_val(bootloader, addr_name)
-        self.fa_size = get_val(bootloader, size_name)
-
-
-def calc_status_size(boot_swap_status_row_sz, max_img_sectors,
-                     img_number, scratch_flag=True):
-    """Estimate status size, see swap_status.h"""
-    boot_swap_status_cnt_sz = 4
-    boot_swap_status_crc_sz = 4
-    boot_swap_status_mgcrec_sz = 4
-    boot_swap_status_trailer_size = 64
-    boot_swap_status_payld_sz = \
-        boot_swap_status_row_sz - boot_swap_status_mgcrec_sz - \
-        boot_swap_status_cnt_sz - boot_swap_status_crc_sz
-    boot_swap_status_sect_rows_num = \
-        int((max_img_sectors - 1) //
-            boot_swap_status_payld_sz) + 1
-    boot_swap_status_trail_rows_num = \
-        int((boot_swap_status_trailer_size - 1) //
-            boot_swap_status_payld_sz) + 1
-    boot_swap_status_d_size = \
-        boot_swap_status_row_sz * \
-        (boot_swap_status_sect_rows_num + boot_swap_status_trail_rows_num)
-    boot_swap_status_mult = 2
-    boot_swap_status_size = boot_swap_status_mult * boot_swap_status_d_size
-    status_zone_cnt = 2 * img_number
-    if scratch_flag:
-        status_zone_cnt += 1
-    return boot_swap_status_size * status_zone_cnt
-
-
-def process_json(in_file):
-    """Process JSON"""
-    try:
-        with open(in_file, encoding='UTF-8') as in_f:
-            try:
-                flash_map = json.load(in_f)
-            except ValueError:
-                print('Cannot parse', in_file, file=sys.stderr)
-                sys.exit(4)
-    except (FileNotFoundError, OSError):
-        print('Cannot open', in_file, file=sys.stderr)
-        sys.exit(4)
-    flash = flash_map.get('external_flash')
-    if flash is not None:
-        flash = flash[0]
-        model = flash.get('model')
-        mode = flash.get('mode')
-        if model is not None:
-            try:
-                flash = flashDict[model]
-            except KeyError:
-                print('Supported SPI Flash ICs are:',
-                      ', '.join(flashDict.keys()),
-                      file=sys.stderr)
-                sys.exit(3)
-        else:
-            try:
-                flash = {'flashSize': cvt_dec_or_hex(flash['flash-size'],
-                                                     'flash-size'),
-                         'eraseSize': cvt_dec_or_hex(flash['erase-size'],
-                                                     'erase-size')}
-            except KeyError as key:
-                print('Malformed JSON:', key,
-                      "is missing in 'external_flash'",
-                      file=sys.stderr)
-                sys.exit(3)
-        flash.update({'XIP': str(mode).upper() == 'XIP'})
-    return flash_map['boot_and_upgrade'], flash
-
-
-def process_images(area_list, boot_and_upgrade):
-    """Process images"""
-    app_count = 0
-    slot_sectors_max = 0
-    all_shared = get_bool(boot_and_upgrade['bootloader'], 'shared_slot')
-    any_shared = all_shared
-    app_core = None
-    apps_flash_map = [None, ]
-
-    for stage in range(2):
-        for app_index in range(1, 5):
-
-            app_flash_map = {}
-
-            try:
-                app_ident = f'application_{app_index}'
-                application = boot_and_upgrade[app_ident]
-                try:
-                    primary_addr = get_val(application, 'address')
-                    primary_size = get_val(application, 'size')
-                    secondary_addr = get_val(application, 'upgrade_address')
-                    secondary_size = get_val(application, 'upgrade_size')
-                except KeyError as key:
-                    print('Malformed JSON:', key, 'is missing',
-                          file=sys.stderr)
-                    sys.exit(5)
-                if stage == 0:
-                    if primary_size != secondary_size:
-                        print('Primary and secondary slot sizes'
-                              ' are different for', app_ident,
-                              file=sys.stderr)
-                        sys.exit(6)
-                    area_list.chk_area(primary_addr, primary_size)
-                    area_list.chk_area(secondary_addr, secondary_size,
-                                       primary_addr)
-                    if application.get('core') is None:
-                        if app_index == 1:
-                            app_core = area_list.plat['appCore']
-                    elif app_index > 1:
-                        print('"core" makes sense only for the 1st app',
-                              file=sys.stderr)
-                        sys.exit(6)
-                    else:
-                        app_core = get_str(application, 'core',
-                                           area_list.plat['appCore'])
-                    if app_index == 1:
-                        app_core = area_list.plat['allCores'].get(app_core.lower())
-                        if app_core is None:
-                            print('Unknown "core"', file=sys.stderr)
-                            sys.exit(6)
-                else:
-                    slot_sectors_max = max(
-                        slot_sectors_max,
-                        area_list.add_area(
-                            f'{app_ident} (primary slot)',
-                            f'FLASH_AREA_IMG_{app_index}_PRIMARY',
-                            primary_addr, primary_size,
-                            area_list.get_img_trailer_size()))
-                    shared_slot = get_bool(application, 'shared_slot', all_shared)
-                    any_shared = any_shared or shared_slot
-                    slot_sectors_max = max(
-                        slot_sectors_max,
-                        area_list.add_area(
-                            f'{app_ident} (secondary slot)',
-                            f'FLASH_AREA_IMG_{app_index}_SECONDARY',
-                            secondary_addr, secondary_size,
-                            area_list.get_img_trailer_size(),
-                            shared_slot))
-
-                    app_slot_prim = {"address": hex(primary_addr), "size": hex(primary_size)}
-                    app_slot_sec = {"address": hex(secondary_addr), "size": hex(secondary_size)}
-
-                    app_flash_map.update({"primary": app_slot_prim, "secondary": app_slot_sec})
-                    apps_flash_map.append(app_flash_map)
-
-                app_count = app_index
-
-            except KeyError:
-                break
-        if app_count == 0:
-            print('Malformed JSON: no application(s) found',
-                  file=sys.stderr)
-            sys.exit(5)
-
-    return app_core, app_count, slot_sectors_max, apps_flash_map, any_shared
-
-def process_policy_20829(in_policy):
-    """Process policy file to get data of NV-counter"""
-    list_counters = None
-
-    try:
-        with open(in_policy, encoding='UTF-8') as in_f:
-            try:
-                policy = json.load(in_f)
-            except ValueError:
-                print('\nERROR: Cannot parse', in_policy,'\n', file=sys.stderr)
-                sys.exit(4)
-            finally:
-                in_f.close()
-    except (FileNotFoundError, OSError):
-        print('Cannot open', in_policy, file=sys.stderr)
-        sys.exit(4)
-
-    try:
-        nv_cnt = policy["device_policy"]['reprovisioning']['nv_counter']
-        list_values = nv_cnt["value"]
-        list_counters = nv_cnt["bits_per_cnt"]
-    except KeyError:
-        print("\nERROR: Check path to 'nv_counter' and its correctness in policy file", in_policy,
-            ".\n", file=sys.stderr)
-        sys.exit(2)
-
-    #Check correctness of NV-counter
-    try:
-        len_list_value = len(list_values)
-        len_list_counters = len(list_counters)
-    except TypeError:
-        print("\nERROR: Fields 'value' and 'bits_per_cnt' of 'nv_counter' in policy file",
-            in_policy,"must be arrays.\n", file=sys.stderr)
-        sys.exit(2)
-
-    if len_list_value != len_list_counters:
-        print("\nERROR: Fields 'value' and 'bits_per_cnt' of 'nv_counter' in policy file",
-            in_policy,"must have the same size.\n", file=sys.stderr)
-        sys.exit(2)
-
-    sum_all_counters = 0
-    for i in range(len_list_value):
-        sum_all_counters += list_counters[i]
-        if list_values[i] > list_counters[i]:
-            print("\nERROR: Field 'value' cannot be more then 'bits_per_cnt'.", file=sys.stderr)
-            print("Check 'nv_counter' in policy file", in_policy,"\n", file=sys.stderr)
-            sys.exit(2)
-
-    sum_all_bit_nv_counter = 32
-    if sum_all_counters != sum_all_bit_nv_counter:
-        print("\nERROR: The sum of all 'bits_per_cnt' must be equal to 32.", file=sys.stderr)
-        print("Check 'nv_counter' in policy file", in_policy,"\n", file=sys.stderr)
-        sys.exit(2)
-
-    return list_counters
-
-
-def form_max_counter_array(in_list, out_file):
-    '''Write bit_per_count array to output file
-    There is expected, that "out_file" already exists'''
-
-    out_array_str = "\n#ifdef NEED_MAX_COUNTERS\nstatic const uint8_t bits_per_cnt[] = {"
-
-    #in_list is checked in prior function 'process_policy()'
-    for i, list_member in enumerate(in_list):
-        out_array_str += str(list_member)
-        if i < len(in_list) - 1:
-            out_array_str += ", "
-    out_array_str += "};\n#endif\n"
-
-    try:
-        with open(out_file, "a", encoding='UTF-8') as out_f:
-            out_f.write(out_array_str)
-    except (FileNotFoundError, OSError):
-        print('\nERROR: Cannot open ', out_file, file=sys.stderr)
-        sys.exit(7)
-
-
-def main():
-    """Flash map converter"""
-    params = CmdLineParams()
-
-    try:
-        plat = platDict[params.plat_id]
-    except KeyError:
-        print('Supported platforms are:', ', '.join(platDict.keys()),
-              file=sys.stderr)
-        sys.exit(2)
-
-    try:
-        boot_and_upgrade, flash = process_json(params.in_file)
-        bootloader = boot_and_upgrade['bootloader']
-        boot = AddrSize(bootloader, 'address', 'size')
-    except KeyError as key:
-        print('Malformed JSON:', key, 'is missing',
-              file=sys.stderr)
-        sys.exit(5)
-
-    try:
-        scratch = AddrSize(bootloader, 'scratch_address', 'scratch_size')
-    except KeyError:
-        scratch = None
-
-    try:
-        swap_status = AddrSize(bootloader, 'status_address', 'status_size')
-    except KeyError:
-        swap_status = None
-
-    # Create flash areas
-    area_list = AreaList(plat, flash, scratch is None and swap_status is None)
-    area_list.add_area('bootloader', 'FLASH_AREA_BOOTLOADER',
-                       boot.fa_addr, boot.fa_size)
-
-    # Service RAM app (optional)
-    service_app = boot_and_upgrade.get('service_app')
-    app_binary = None
-    input_params = None
-    app_desc = None
-    if service_app is not None:
-        if plat['flashSize'] > 0:
-            print('service_app is unsupported on this platform',
-                  file=sys.stderr)
-            sys.exit(7)
-        try:
-            app_binary = AddrSize(service_app, 'address', 'size')
-            input_params = AddrSize(service_app, 'params_address', 'params_size')
-            app_desc = AddrSize(service_app, 'desc_address', 'desc_size')
-            if input_params.fa_addr != app_binary.fa_addr + app_binary.fa_size or \
-                    app_desc.fa_addr != input_params.fa_addr + input_params.fa_size or \
-                    app_desc.fa_size != 0x20:
-                print('Malformed service_app definition', file=sys.stderr)
-                sys.exit(7)
-            area_list.add_area('service_app', None, app_binary.fa_addr,
-                               app_binary.fa_size + input_params.fa_size + app_desc.fa_size)
-        except KeyError as key:
-            print('Malformed JSON:', key, 'is missing',
-                  file=sys.stderr)
-            sys.exit(5)
-
-    # Fill flash areas
-    app_core, app_count, slot_sectors_max, apps_flash_map, shared_slot = \
-        process_images(area_list, boot_and_upgrade)
-
-    cy_img_hdr_size = 0x400
-    app_start = int(apps_flash_map[1].get("primary").get("address"), 0) + cy_img_hdr_size
-
-    if app_start % plat['VTAlign'] != 0:
-        print('Starting address', apps_flash_map[1].get("primary").get("address"),
-              '+', hex(cy_img_hdr_size),
-              'must be aligned to', hex(plat['VTAlign']),
-              file=sys.stderr)
-        sys.exit(7)
-
-    slot_sectors_max = max(slot_sectors_max, 32)
-
-    if swap_status is not None:
-        status_size_min = calc_status_size(area_list.get_min_erase_size(),
-                                           slot_sectors_max,
-                                           app_count,
-                                           scratch is not None)
-
-        if swap_status.fa_size < status_size_min:
-            print('Insufficient swap status area - suggested size',
-                  hex(status_size_min),
-                  file=sys.stderr)
-            sys.exit(7)
-        area_list.add_area('swap status partition',
-                           'FLASH_AREA_IMAGE_SWAP_STATUS',
-                           swap_status.fa_addr, swap_status.fa_size)
-
-    if scratch is not None:
-        area_list.add_area('scratch area',
-                           'FLASH_AREA_IMAGE_SCRATCH',
-                           scratch.fa_addr, scratch.fa_size)
-
-    # Compare size 'bit_per_cnt' and number of images.
-    # 'service_app' is used only when HW rollback counter exists
-    if plat.get('bitsPerCnt') is not None and service_app is not None:
-        plat['bitsPerCnt'] = True
-        list_counters = process_policy_20829(params.policy)
-        if list_counters is not None and len(list_counters) != app_count:
-            print("\nERROR: 'bits_per_cnt' must be present for each image!",
-                file=sys.stderr)
-            print("Please, check secure provisioning and reprovisioning policies.\n",
-                file=sys.stderr)
-            sys.exit(7)
-
-
-    # Image id parameter is not used for MCUBootApp
-    if params.img_id is None:
-        area_list.generate_c_source(params)
-
-    # Report necessary values back to make
-    print('# AUTO-GENERATED FILE, DO NOT EDIT. ALL CHANGES WILL BE LOST!')
-    print('BOOTLOADER_SIZE :=', hex(boot.fa_size))
-    if params.set_core:
-        print('CORE :=', plat['allCores'][plat['bootCore'].lower()])
-    print('APP_CORE :=', app_core)
-
-    if params.img_id is not None:
-        primary_img_start = apps_flash_map[int(params.img_id)].get("primary").get("address")
-        secondary_img_start = apps_flash_map[int(params.img_id)].get("secondary").get("address")
-        slot_size = apps_flash_map[int(params.img_id)].get("primary").get("size")
-
-        print('PRIMARY_IMG_START := ' + primary_img_start)
-        print('SECONDARY_IMG_START := ' + secondary_img_start)
-        print('SLOT_SIZE := ' + slot_size)
-    else:
-        print('MCUBOOT_IMAGE_NUMBER :=', app_count)
-        print('MAX_IMG_SECTORS :=', slot_sectors_max)
-
-    if area_list.use_overwrite:
-        print('USE_OVERWRITE := 1')
-    if area_list.external_flash:
-        print('USE_EXTERNAL_FLASH := 1')
-        if area_list.external_flash_xip:
-            print('USE_XIP := 1')
-    if shared_slot:
-        print('USE_SHARED_SLOT := 1')
-    if service_app is not None:
-        print('PLATFORM_SERVICE_APP_OFFSET :=',
-              hex(app_binary.fa_addr - plat['smifAddr']))
-        print('PLATFORM_SERVICE_APP_INPUT_PARAMS_OFFSET :=',
-              hex(input_params.fa_addr - plat['smifAddr']))
-        print('PLATFORM_SERVICE_APP_DESC_OFFSET :=',
-              hex(app_desc.fa_addr - plat['smifAddr']))
-        print('USE_HW_ROLLBACK_PROT := 1')
-
-
-if __name__ == '__main__':
-    main()
diff --git a/boot/cypress/scripts/memorymap.py b/boot/cypress/scripts/memorymap.py
new file mode 100644
index 0000000..5511c9a
--- /dev/null
+++ b/boot/cypress/scripts/memorymap.py
@@ -0,0 +1,1434 @@
+"""MCUBoot Flash Map Converter (JSON to .h)
+Copyright (c) 2022 Infineon Technologies AG
+"""
+
+import sys
+import getopt
+import json
+from enum import Enum
+import os.path
+
+class Error(Enum):
+    ''' Application error codes '''
+    ARG             = 1
+    POLICY          = 2
+    FLASH           = 3
+    IO              = 4
+    JSON            = 5
+    VALUE           = 6
+    CONFIG_MISMATCH = 7
+
+SERVICE_APP_SZ = 0x20
+
+c_array = 'flash_areas'
+
+# Supported Platforms
+cm0pCore = {
+    'cortex-m0+': 'CM0P',
+    'cm0+': 'CM0P',
+    'm0+': 'CM0P',
+    'cortex-m0p': 'CM0P',
+    'cm0p': 'CM0P',
+    'm0p': 'CM0P',
+    'cortex-m0plus': 'CM0P',
+    'cm0plus': 'CM0P',
+    'm0plus': 'CM0P'
+}
+
+cm4Core = {
+    'cortex-m4': 'CM4',
+    'cm4': 'CM4',
+    'm4': 'CM4'
+}
+
+cm33Core = {
+    'cortex-m33': 'CM33',
+    'cm33': 'CM33',
+    'm33': 'CM33'
+}
+
+cm7Core = {
+    'cortex-m7': 'CM7',
+    'cm7': 'CM7',
+    'm7': 'CM7'
+}
+
+allCores_PSOC_06x = {**cm0pCore, **cm4Core}
+
+common_PSOC_061 = {
+    'flashAddr': 0x10000000,
+    'eraseSize': 0x200,  # 512 bytes
+    'smifAddr': 0x18000000,
+    'smifSize': 0x8000000,  # i.e., window size
+    'VTAlign': 0x400,  # Vector Table alignment
+    'allCores': cm4Core,
+    'bootCore': 'Cortex-M4',
+    'appCore': 'Cortex-M4'
+}
+
+common_PSOC_06x = {
+    'flashAddr': 0x10000000,
+    'eraseSize': 0x200,  # 512 bytes
+    'smifAddr': 0x18000000,
+    'smifSize': 0x8000000,  # i.e., window size
+    'VTAlign': 0x400,  # Vector Table alignment
+    'allCores': allCores_PSOC_06x,
+    'bootCore': 'Cortex-M0+',
+    'appCore': 'Cortex-M4'
+}
+
+common_XMC7000 = {
+    'flashAddr': 0x10000000,
+    'eraseSize': 0x8000,  # 512 bytes
+    'smifAddr': 0x18000000,
+    'smifSize': 0x8000000,  # i.e., window size
+    'VTAlign': 0x400,  # Vector Table alignment
+    'allCores': cm7Core,
+    'bootCore': 'Cortex-M7',
+    'appCore': 'Cortex-M7'
+}
+
+common_PSE84 = {
+    'flashAddr': 0x32000000,
+    'flashSize': 0x40000,
+    'eraseSize': 0x20,  # 32 bytes
+    'smifAddr': 0x60000000, #secure address 
+    'smifSize': 0x4000000,  # i.e., window size
+    'VTAlign': 0x400,  # Vector Table alignment
+    'allCores': cm33Core,
+    'bootCore': 'Cortex-M33',
+    'appCore': 'Cortex-M33'
+}
+
+platDict = {
+    'PSOC_061_2M': {
+        'flashSize': 0x200000,  # 2 MBytes
+        **common_PSOC_061
+    },
+    'PSOC_061_1M': {
+        'flashSize': 0x100000,  # 1 MByte
+        **common_PSOC_061
+    },
+    'PSOC_061_512K': {
+        'flashSize': 0x80000,  # 512 KBytes
+        **common_PSOC_061
+    },
+
+    'PSOC_062_2M': {
+        'flashSize': 0x200000,  # 2 MBytes
+        **common_PSOC_06x
+    },
+    'PSOC_062_1M': {
+        'flashSize': 0x100000,  # 1 MByte
+        **common_PSOC_06x
+    },
+    'PSOC_062_512K': {
+        'flashSize': 0x80000,  # 512 KBytes
+        **common_PSOC_06x
+    },
+
+    'PSOC_063_1M': {
+        'flashSize': 0x100000,  # 1 MByte
+        **common_PSOC_06x
+    },
+
+    'XMC7200': {
+        'flashSize': 0x100000,  # 1 MByte
+        **common_XMC7000
+    },
+
+    'XMC7100': {
+        'flashSize': 0x100000,  # 1 MByte
+        **common_PSOC_06x
+    },
+
+    'CYW20829': {
+        'flashSize': 0,  # n/a
+        'smifAddr': 0x60000000,
+        'smifSize': 0x8000000,  # i.e., window size
+        'VTAlign': 0x200,  # Vector Table alignment
+        'allCores': cm33Core,
+        'bootCore': 'Cortex-M33',
+        'appCore': 'Cortex-M33',
+        'bitsPerCnt': False
+    },
+
+    'PSE84_L4': {
+        **common_PSE84
+    },
+
+    'PSE84_L2': {
+        **common_PSE84
+    }
+}
+
+# Supported SPI Flash ICs
+flashDict = {
+    # Fudan
+    'FM25Q04': {
+        'flashSize': 0x80000,  # 4 Mbits
+        'eraseSize': 0x1000,  # 128 uniform sectors with 4K-byte each
+    },
+    'FM25W04': {
+        'flashSize': 0x80000,  # 4 Mbits
+        'eraseSize': 0x1000,  # 128 uniform sectors with 4K-byte each
+    },
+    'FM25Q08': {
+        'flashSize': 0x100000,  # 8 Mbits
+        'eraseSize': 0x1000,  # 256 uniform sectors with 4K-byte each
+    },
+    'FM25W08': {
+        'flashSize': 0x100000,  # 8 Mbits
+        'eraseSize': 0x1000,  # 256 uniform sectors with 4K-byte each
+    },
+    # Puya
+    'P25Q05H': {
+        'flashSize': 0x10000,  # 512 Kbits
+        'eraseSize': 0x1000,  # Uniform 4K-byte Sector Erase
+    },
+    'P25Q10H': {
+        'flashSize': 0x20000,  # 1 Mbit
+        'eraseSize': 0x1000,  # Uniform 4K-byte Sector Erase
+    },
+    'P25Q20H': {
+        'flashSize': 0x40000,  # 2 Mbits
+        'eraseSize': 0x1000,  # Uniform 4K-byte Sector Erase
+    },
+    'P25Q40H': {
+        'flashSize': 0x80000,  # 4 Mbits
+        'eraseSize': 0x1000,  # Uniform 4K-byte Sector Erase
+    },
+    # Infineon
+    'S25HS256T': {
+        'flashSize': 0x2000000,  # 256 Mbits
+        'eraseSize': 0x40000,  # Uniform Sector Architecture
+    },
+    'S25HS512T': {
+        'flashSize': 0x4000000,  # 512 Mbits
+        'eraseSize': 0x40000,  # Uniform Sector Architecture
+    },
+    'S25HS01GT': {
+        'flashSize': 0x8000000,  # 1 Gbit
+        'eraseSize': 0x40000,  # Uniform Sector Architecture
+    }
+}
+
+
+def is_overlap(fa1off, fa1size, fa2off, fa2size, align):
+    """Check if two flash areas on the same device overlap"""
+    mask = align - 1
+    assert align > 0 and (align & mask) == 0  # ensure align is a power of 2
+    fa1end = (fa1off + fa1size + mask) & ~mask
+    fa2end = (fa2off + fa2size + mask) & ~mask
+    fa1off = fa1off & ~mask
+    fa2off = fa2off & ~mask
+    return fa1off < fa2end and fa2off < fa1end
+
+
+def is_same_mem(fa1addr, fa2addr):
+    """Check if two addresses belong to the same memory"""
+    if fa1addr is None or fa2addr is None:
+        return False
+    mask = 0xFF000000
+    return (fa1addr & mask) == (fa2addr & mask)
+
+
+class CmdLineParams:
+    """Command line parameters"""
+
+    def __init__(self):
+        self.plat_id = ''
+        self.in_file = ''
+        self.out_file = ''
+        self.fa_file = ''
+        self.img_id = None
+        self.policy = None
+        self.set_core = False
+        self.image_boot_config = False
+
+        usage = 'USAGE:\n' + sys.argv[0] + \
+                ''' -p <platform> -i <flash_map.json> -o <memorymap.c> -a <memorymap.h> -d <img_id> -c <policy.json>
+
+OPTIONS:
+-h  --help       Display the usage information
+-p  --platform=  Target (e.g., PSOC_062_512K)
+-i  --ifile=     JSON flash map file
+-o  --ofile=     C file to be generated
+-a  --fa_file=   path where to create 'memorymap.h'
+-d  --img_id     ID of application to build
+-c  --policy     Policy file in JSON format
+-m  --core       Detect and set Cortex-M CORE
+-x  --image_boot_config Generate image boot config structure
+'''
+
+        try:
+            opts, unused = getopt.getopt(
+                sys.argv[1:], 'hi:o:a:p:d:c:x:m',
+                ['help', 'platform=', 'ifile=', 'ofile=', "fa_file=", 'img_id=', 'policy=', 'core', 'image_boot_config'])
+        except getopt.GetoptError:
+            print(usage, file=sys.stderr)
+            sys.exit(Error.ARG)
+
+        for opt, arg in opts:
+            if opt in ('-h', '--help'):
+                print(usage, file=sys.stderr)
+                sys.exit()
+            elif opt in ('-p', '--platform'):
+                self.plat_id = arg
+            elif opt in ('-i', '--ifile'):
+                self.in_file = arg
+            elif opt in ('-o', '--ofile'):
+                self.out_file = arg
+            elif opt in ('-a', '--fa_file'):
+                self.fa_file = arg
+            elif opt in ('-d', '--img_id'):
+                self.img_id = arg
+            elif opt in ('-c', '--policy'):
+                self.policy = arg
+            elif opt in ('-m', '--core'):
+                self.set_core = True
+            elif opt in ('x', '--image_boot_config'):
+                self.image_boot_config = True
+
+        if len(self.in_file) == 0 or len(self.out_file) == 0 or len(self.fa_file) == 0:
+            print(usage, file=sys.stderr)
+            sys.exit(Error.ARG)
+
+
+class AreaList:
+    '''
+    A List of flash areas
+    ...
+
+    Attributes
+    ----------
+    plat : dict
+        Platform settings
+
+    flash : dict
+        External flash settings
+
+    use_overwrite : bool
+        Overwrite configuration in use
+
+    areas : list
+        Flash area parameter list
+
+    peers : set
+        Peers
+
+    trailers : set
+        Flash area trailers
+
+    internal_flash : bool
+        Internal flash in use
+
+    external_flash : bool
+        External flash in use
+
+    external_flash_xip : bool
+        External XIP in use
+
+    Methods
+    -------
+    get_min_erase_size:
+        Calculate minimum erase block size for int./ext. Flash
+
+    get_img_trailer_size:
+        Calculate image trailer size
+
+    process_int_area:
+        Process internal flash area
+
+    process_ext_area:
+        Process external flash area
+
+    chk_area:
+        Check area location (internal/external flash)
+
+    add_area:
+        Add flash area to AreaList.
+        Internal/external flash is detected by address.
+
+    generate_c_source:
+        Generate C source
+
+    create_flash_area_id:
+        Creates flash_area_id.h file.
+    '''
+
+    def __init__(self, plat, flash, use_overwrite):
+        self.plat = plat
+        self.flash = flash
+        self.use_overwrite = use_overwrite
+        self.areas = []
+        self.peers = {}
+        self.trailers = {}
+        self.internal_flash = False
+        self.external_flash = False
+        self.external_flash_xip = False
+
+    def get_min_erase_size(self):
+        '''Calculate minimum erase block size for int./ext. Flash '''
+        return self.plat['eraseSize'] if self.plat['flashSize'] > 0 \
+            else self.flash['eraseSize']
+
+    def get_img_trailer_size(self):
+        '''Calculate image trailer size'''
+        return self.get_min_erase_size()
+
+    def process_int_area(self, title, addr, fa_size,
+                         img_trailer_size, shared_slot):
+        '''
+        Process internal flash area
+        Parameters:
+        ----------
+        title : str
+            Area name
+
+        addr : int
+            Area address
+
+        fa_size : int
+            Area size
+
+        img_trailer_size : int
+            Trailer size
+
+        shared_slot : bool
+            Shared slot option in use
+
+        Returns:
+        ----------
+        fa_device_id : str
+
+        fa_off : int
+
+        slot_sectors : int
+        '''
+        fa_device_id = 'FLASH_DEVICE_INTERNAL_FLASH'
+        fa_off = addr - self.plat['flashAddr']
+        if img_trailer_size is not None:
+            if self.use_overwrite:
+                if shared_slot:
+                    print('Shared slot', title,
+                          'is not supported in OVERWRITE mode',
+                          file=sys.stderr)
+                    sys.exit(Error.CONFIG_MISMATCH)
+            else:
+                # Check trailer alignment (start at the sector boundary)
+                align = (fa_off + fa_size - img_trailer_size) % \
+                        self.plat['eraseSize']
+                if align != 0:
+                    addr += self.plat['eraseSize'] - align
+                    if addr + fa_size <= \
+                            self.plat['flashAddr'] + self.plat['flashSize']:
+                        print('Misaligned', title,
+                              '- suggested address', hex(addr),
+                              file=sys.stderr)
+                    else:
+                        print('Misaligned', title, file=sys.stderr)
+                    sys.exit(Error.CONFIG_MISMATCH)
+        else:
+            # Check alignment (flash area should start at the sector boundary)
+            if fa_off % self.plat['eraseSize'] != 0:
+                print('Misaligned', title, file=sys.stderr)
+                sys.exit(Error.CONFIG_MISMATCH)
+        slot_sectors = int((fa_off % self.plat['eraseSize'] +
+                            fa_size + self.plat['eraseSize'] - 1) //
+                           self.plat['eraseSize'])
+        return fa_device_id, fa_off, slot_sectors
+
+    def process_ext_area(self, title, addr, fa_size,
+                         img_trailer_size, shared_slot):
+        '''
+        Process external flash area
+        Parameters:
+        ----------
+        title : str
+            Area name
+
+        addr : int
+            Area address
+
+        fa_size : int
+            Area size
+
+        img_trailer_size : int
+            Trailer size
+
+        shared_slot : bool
+            Shared slot option in use
+
+        Returns:
+        ----------
+        fa_device_id : str
+
+        fa_off : int
+
+        slot_sectors : int
+        '''
+        if self.flash is None:
+            print('Unspecified SPI Flash IC',
+                  file=sys.stderr)
+            sys.exit(Error.FLASH)
+        if addr + fa_size <= \
+                self.plat['smifAddr'] + self.flash['flashSize']:
+            flash_idx = 'CY_BOOT_EXTERNAL_DEVICE_INDEX'
+            fa_device_id = f'FLASH_DEVICE_EXTERNAL_FLASH({flash_idx})'
+            fa_off = addr - self.plat['smifAddr']
+        else:
+            print('Misfitting', title, file=sys.stderr)
+            sys.exit(Error.CONFIG_MISMATCH)
+        if img_trailer_size is not None:
+            if self.use_overwrite:
+                if shared_slot:
+                    print('Shared slot', title,
+                          'is not supported in OVERWRITE mode',
+                          file=sys.stderr)
+                    sys.exit(Error.CONFIG_MISMATCH)
+            else:
+                # Check trailer alignment (start at the sector boundary)
+                align = (fa_off + fa_size - img_trailer_size) % \
+                        self.flash['eraseSize']
+                if align != 0:
+                    peer_addr = self.peers.get(addr)
+                    if shared_slot:
+                        # Special case when using both int. and ext. memory
+                        if self.plat['flashSize'] > 0 and \
+                                align % self.plat['eraseSize'] == 0:
+                            print('Note:', title, 'requires', align,
+                                  'padding bytes before trailer',
+                                  file=sys.stderr)
+                        else:
+                            print('Misaligned', title, file=sys.stderr)
+                            sys.exit(Error.CONFIG_MISMATCH)
+                    elif is_same_mem(addr, peer_addr) and \
+                            addr % self.flash['eraseSize'] == \
+                            peer_addr % self.flash['eraseSize']:
+                        pass  # postpone checking
+                    else:
+                        addr += self.flash['eraseSize'] - align
+                        if addr + fa_size <= \
+                                self.plat['smifAddr'] + self.flash['flashSize']:
+                            print('Misaligned', title,
+                                  '- suggested address', hex(addr),
+                                  file=sys.stderr)
+                        else:
+                            print('Misaligned', title, file=sys.stderr)
+                        sys.exit(Error.CONFIG_MISMATCH)
+        else:
+            # Check alignment (flash area should start at the sector boundary)
+            if fa_off % self.flash['eraseSize'] != 0:
+                print('Misaligned', title, file=sys.stderr)
+                sys.exit(Error.CONFIG_MISMATCH)
+        slot_sectors = int((fa_off % self.flash['eraseSize'] +
+                            fa_size + self.flash['eraseSize'] - 1) //
+                           self.flash['eraseSize'])
+        self.external_flash = True
+        if self.flash['XIP']:
+            self.external_flash_xip = True
+        return fa_device_id, fa_off, slot_sectors
+
+    def chk_area(self, addr, fa_size, peer_addr=None):
+        '''
+        Check area location (internal/external flash)
+        Parameters:
+        ----------
+        addr : int
+            Area address
+
+        fa_size : int
+            Area size
+
+        peer_addr : bool (optional)
+            Shared slot option in use
+
+        Returns:
+        ----------
+        None
+        '''
+        if peer_addr is not None:
+            self.peers[peer_addr] = addr
+        fa_limit = addr + fa_size
+        if self.plat['flashSize'] and \
+                addr >= self.plat['flashAddr'] and \
+                fa_limit <= self.plat['flashAddr'] + self.plat['flashSize']:
+            # Internal flash
+            self.internal_flash = True
+
+    def add_area(self, title,
+                 fa_id, addr, fa_size,
+                 img_trailer_size=None, shared_slot=False):
+        '''
+        Add flash area to AreaList.
+        Internal/external flash is detected by address.
+        Parameters:
+        ----------
+        title : str
+            Area name
+
+        fa_id : str
+            Area id
+
+        addr : int
+            Area address
+
+        fa_size : int
+            Area size
+
+        img_trailer_size : int
+            Trailer size (optional)
+
+        shared_slot : bool
+            Shared slot option in use (optional)
+
+        Returns:
+        ----------
+        slot_sectors : int
+            Number of sectors in a slot
+        '''
+        if fa_size == 0:
+            print('Empty', title, file=sys.stderr)
+            sys.exit(Error.CONFIG_MISMATCH)
+
+        fa_limit = addr + fa_size
+        if self.plat['flashSize'] and \
+                addr >= self.plat['flashAddr'] and \
+                fa_limit <= self.plat['flashAddr'] + self.plat['flashSize']:
+            # Internal flash
+            fa_device_id, fa_off, slot_sectors = self.process_int_area(
+                title, addr, fa_size, img_trailer_size, shared_slot)
+            align = self.plat['eraseSize']
+        elif self.plat['smifSize'] and \
+                addr >= self.plat['smifAddr'] and \
+                fa_limit <= self.plat['smifAddr'] + self.plat['smifSize']:
+            # External flash
+            fa_device_id, fa_off, slot_sectors = self.process_ext_area(
+                title, addr, fa_size, img_trailer_size, shared_slot)
+            align = self.flash['eraseSize']
+        else:
+            print('Invalid', title, file=sys.stderr)
+            sys.exit(Error.CONFIG_MISMATCH)
+
+        if shared_slot:
+            assert img_trailer_size is not None
+            tr_addr = addr + fa_size - img_trailer_size
+            tr_name = self.trailers.get(tr_addr)
+            if tr_name is not None:
+                print('Same trailer address for', title, 'and', tr_name,
+                      file=sys.stderr)
+                sys.exit(Error.CONFIG_MISMATCH)
+            self.trailers[tr_addr] = title
+
+        # Ensure no flash areas on this device will overlap, except the
+        # shared slot
+        for area in self.areas:
+            if fa_device_id == area['fa_device_id']:
+                over = is_overlap(fa_off, fa_size,
+                                  area['fa_off'], area['fa_size'],
+                                  align)
+                if shared_slot and area['shared_slot']:
+                    if not over:  # images in shared slot should overlap
+                        print(title, 'is not shared with', area['title'],
+                              file=sys.stderr)
+                        sys.exit(Error.CONFIG_MISMATCH)
+                elif over:
+                    print(title, 'overlaps with', area['title'],
+                          file=sys.stderr)
+                    sys.exit(Error.CONFIG_MISMATCH)
+
+        self.areas.append({'title': title,
+                           'shared_slot': shared_slot,
+                           'fa_id': fa_id,
+                           'fa_device_id': fa_device_id,
+                           'fa_off': fa_off,
+                           'fa_size': fa_size})
+        return slot_sectors
+
+    def generate_c_source(self, params):
+        '''
+        Generate C source
+        Parameters:
+        ----------
+        params : CmdLineParams
+            Application parameters
+
+        Returns:
+        ----------
+        None
+        '''
+        c_array = 'flash_areas'
+
+        try:
+            with open(params.out_file, "w", encoding='UTF-8') as out_f:
+
+                out_f.write(f'#include "{params.fa_file}"\n')
+                out_f.write(f'#include "flash_map_backend.h"\n\n')
+                out_f.write(f'#include "flash_map_backend_platform.h"\n\n')
+                out_f.write(f'struct flash_area {c_array}[] = {{\n')
+                comma = len(self.areas)
+                area_count = 0
+                for area in self.areas:
+                    comma -= 1
+                    if area['fa_id'] is not None:
+                        sss = ' /* Shared secondary slot */' \
+                            if area['shared_slot'] else ''
+                        out_f.writelines('\n'.join([
+                            '    {' + sss,
+                            f"        .fa_id        = {area['fa_id']},",
+                            f"        .fa_device_id = {area['fa_device_id']},",
+                            f"        .fa_off       = {hex(area['fa_off'])}U,",
+                            f"        .fa_size      = {hex(area['fa_size'])}U",
+                            '    },' if comma else '    }', '']))
+                        area_count += 1
+                out_f.write('};\n\n'
+                            'struct flash_area *boot_area_descs[] = {\n')
+                for area_index in range(area_count):
+                    out_f.write(f'    &{c_array}[{area_index}U],\n')
+                out_f.write('    NULL\n};\n')                
+                out_f.close()
+
+        except (FileNotFoundError, OSError):
+            print('Cannot create', params.out_file, file=sys.stderr)
+            sys.exit(Error.IO)
+
+    def create_flash_area_id(self, img_number, params):
+        """ Get 'img_number' and generate flash_area_id.h file' """
+
+        #check if params.fa_file already exists and it has FLASH_AREA_ID
+        if os.path.exists(params.fa_file):
+            with open(params.fa_file, "r", encoding='UTF-8') as fa_f:
+                content = fa_f.read()
+                res = content.find(f"FLASH_AREA_IMG_{img_number}_SECONDARY")
+                if res != -1:
+                    fa_f.close()
+                    return
+
+                fa_f.close()
+
+        try:
+            with open(params.fa_file, "w", encoding='UTF-8') as fa_f:
+                fa_f.write("#ifndef MEMORYMAP_H\n")
+                fa_f.write("#define MEMORYMAP_H\n\n")
+                fa_f.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
+                            ' ALL CHANGES WILL BE LOST! */\n')
+                fa_f.write(f'#include "flash_map_backend.h"\n\n')
+
+                fa_f.write(f'extern struct flash_area {c_array}[];\n')
+                fa_f.write(f'extern struct flash_area *boot_area_descs[];\n')
+
+                #we always have BOOTLOADER and IMG_1_
+                fa_f.write("#define FLASH_AREA_BOOTLOADER          ( 0u)\n\n")
+                fa_f.write("#define FLASH_AREA_IMG_1_PRIMARY       ( 1u)\n")
+                fa_f.write("#define FLASH_AREA_IMG_1_SECONDARY     ( 2u)\n\n")
+
+                fa_f.write("#define FLASH_AREA_IMAGE_SCRATCH       ( 3u)\n")
+                fa_f.write("#define FLASH_AREA_IMAGE_SWAP_STATUS   ( 7u)\n\n")
+
+                for img in range(2, img_number + 1):
+                    """ img_id_primary and img_id_secondary must be aligned with the
+                        flash_area_id, calculated in the functions
+                        __STATIC_INLINE uint8_t FLASH_AREA_IMAGE_PRIMARY(uint32_t img_idx) and
+                        __STATIC_INLINE uint8_t FLASH_AREA_IMAGE_SECONDARY(uint32_t img_idx),
+                        in boot/cypress/platforms/memory/sysflash/sysflash.h
+                    """
+
+                    slots_for_image = 2
+                    img_id_primary = None
+                    img_id_secondary = None
+
+                    if img == 2:
+                        img_id_primary = int(slots_for_image * img)
+                        img_id_secondary = int(slots_for_image * img + 1)
+
+                    #number 7 is used for FLASH_AREA_IMAGE_SWAP_STATUS, so the next is 8
+                    if img >= 3:
+                        img_id_primary = int(slots_for_image * img + 2)
+                        img_id_secondary = int(slots_for_image * img + 3)
+
+                    fa_f.write(f"#define FLASH_AREA_IMG_{img}_PRIMARY       ( {img_id_primary}u)\n")
+                    fa_f.write(f"#define FLASH_AREA_IMG_{img}_SECONDARY     ( {img_id_secondary}u)\n\n")
+                
+                if self.plat.get('bitsPerCnt'):
+                    fa_f.close()
+                    
+                    list_counters = process_policy_20829(params.policy)
+                    if list_counters is not None:
+                        form_max_counter_array(list_counters, params.fa_file)
+                else:
+                    fa_f.write("#endif /* MEMORYMAP_H */")
+                fa_f.close()
+
+        except (FileNotFoundError, OSError):
+            print('\nERROR: Cannot create ', params.fa_file, file=sys.stderr)
+            sys.exit(Error.IO)
+
+
+def cvt_dec_or_hex(val, desc):
+    """Convert (hexa)decimal string to number"""
+    try:
+        return int(val, 0)
+    except ValueError:
+        print('Invalid value', val, 'for', desc, file=sys.stderr)
+        sys.exit(Error.VALUE)
+
+
+def get_val(obj, attr):
+    """Get JSON 'value'"""
+    obj = obj[attr]
+    try:
+        return cvt_dec_or_hex(obj['value'], obj['description'])
+    except KeyError as key:
+        print('Malformed JSON:', key,
+              'is missing in', "'" + attr + "'",
+              file=sys.stderr)
+        sys.exit(Error.JSON)
+
+
+def get_bool(obj, attr, def_val=False):
+    """Get JSON boolean value (returns def_val if it is missing)"""
+    ret_val = def_val
+    obj = obj.get(attr)
+    if obj is not None:
+        try:
+            val = str(obj['value']).lower()
+            desc = obj['description']
+            if val == 'true':
+                ret_val = True
+            elif val == 'false':
+                ret_val = False
+            else:
+                print('Invalid value', val, 'for', desc, file=sys.stderr)
+                sys.exit(Error.VALUE)
+        except KeyError as key:
+            print('Malformed JSON:', key,
+                  'is missing in', "'" + attr + "'",
+                  file=sys.stderr)
+            sys.exit(Error.JSON)
+    return ret_val
+
+
+def get_str(obj, attr, def_val=None):
+    """Get JSON string value (returns def_val if it is missing)"""
+    ret_val = def_val
+    obj = obj.get(attr)
+    if obj is not None:
+        try:
+            ret_val = str(obj['value'])
+        except KeyError as key:
+            print('Malformed JSON:', key,
+                  'is missing in', "'" + attr + "'",
+                  file=sys.stderr)
+            sys.exit(Error.JSON)
+    return ret_val
+
+
+class AddrSize:
+    """Bootloader area"""
+
+    def __init__(self, bootloader, addr_name, size_name):
+        self.addr = get_val(bootloader, addr_name)
+        self.size = get_val(bootloader, size_name)
+
+
+def calc_status_size(boot_swap_status_row_sz, max_img_sectors,
+                     img_number, scratch_flag=True):
+    """Estimate status size, see swap_status.h"""
+    boot_swap_status_cnt_sz = 4
+    boot_swap_status_crc_sz = 4
+    boot_swap_status_mgcrec_sz = 4
+    boot_swap_status_trailer_size = 64
+    boot_swap_status_payld_sz = \
+        boot_swap_status_row_sz - boot_swap_status_mgcrec_sz - \
+        boot_swap_status_cnt_sz - boot_swap_status_crc_sz
+    boot_swap_status_sect_rows_num = \
+        int((max_img_sectors - 1) //
+            boot_swap_status_payld_sz) + 1
+    boot_swap_status_trail_rows_num = \
+        int((boot_swap_status_trailer_size - 1) //
+            boot_swap_status_payld_sz) + 1
+    boot_swap_status_d_size = \
+        boot_swap_status_row_sz * \
+        (boot_swap_status_sect_rows_num + boot_swap_status_trail_rows_num)
+    boot_swap_status_mult = 2
+    boot_swap_status_size = boot_swap_status_mult * boot_swap_status_d_size
+    status_zone_cnt = 2 * img_number
+    if scratch_flag:
+        status_zone_cnt += 1
+    return boot_swap_status_size * status_zone_cnt
+
+
+def process_json(in_file):
+    """Process JSON"""
+    try:
+        with open(in_file, encoding='UTF-8') as in_f:
+            try:
+                flash_map = json.load(in_f)
+            except ValueError:
+                print('Cannot parse', in_file, file=sys.stderr)
+                sys.exit(Error.IO)
+    except (FileNotFoundError, OSError):
+        print('Cannot open', in_file, file=sys.stderr)
+        sys.exit(Error.IO)
+    flash = flash_map.get('external_flash')
+    if flash is not None:
+        flash = flash[0]
+        model = flash.get('model')
+        mode = flash.get('mode')
+        if model is not None:
+            try:
+                flash = flashDict[model]
+            except KeyError:
+                print('Supported SPI Flash ICs are:',
+                      ', '.join(flashDict.keys()),
+                      file=sys.stderr)
+                sys.exit(Error.FLASH)
+        else:
+            try:
+                flash = {'flashSize': cvt_dec_or_hex(flash['flash-size'],
+                                                     'flash-size'),
+                         'eraseSize': cvt_dec_or_hex(flash['erase-size'],
+                                                     'erase-size')}
+            except KeyError as key:
+                print('Malformed JSON:', key,
+                      "is missing in 'external_flash'",
+                      file=sys.stderr)
+                sys.exit(Error.FLASH)
+        flash.update({'XIP': str(mode).upper() == 'XIP'})
+    return flash_map.get('boot_and_upgrade', None), flash_map.get('ram_app_staging', None), flash
+
+def process_boot_type(boot_and_upgrade):
+    image_boot_mode = []
+
+    for app_index in range(1, 5):
+        app_ident = f'application_{app_index}'
+        application = boot_and_upgrade.get(app_ident)
+
+        if application:
+            ram = application.get('ram', application.get('ram_boot'))
+
+            if ram:
+                image_boot_mode.append(
+                    {
+                        'mode': 'IMAGE_BOOT_MODE_FLASH' if application.get('ram') else 'IMAGE_BOOT_MODE_RAM',
+                        'address': ram.get('address', {}).get('value', 0),
+                        'size': ram.get('size', {}).get('value', 0),
+                    }
+                )
+
+    return image_boot_mode
+
+def generate_boot_type(image_boot_mode):
+    c_file = "image_boot_config.c"
+    h_file = "image_boot_config.h"
+    try:
+        with open(c_file, "w", encoding='UTF-8') as out_f:
+            out_f.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
+                        ' ALL CHANGES WILL BE LOST! */\n')
+            
+            out_f.write(f'#include "{h_file}"\n')
+            out_f.write('\nimage_boot_config_t image_boot_config[BOOT_IMAGE_NUMBER] = {\n')
+            for mode in image_boot_mode:
+                out_f.writelines('\n'.join([
+                    '\t{\n'
+                    f"\t\t.mode     = {mode['mode']},",
+                    f"\t\t.address  = {mode['address']},",
+                    f"\t\t.size     = {mode['size']},",
+                    '\t},\n']))
+            out_f.write('};\n')
+
+        with open(h_file, "w", encoding='UTF-8') as out_f:
+            out_f.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
+                        ' ALL CHANGES WILL BE LOST! */\n')
+            out_f.write('#ifndef IMAGE_BOOT_CONFIG_H\n')
+            out_f.write('#define IMAGE_BOOT_CONFIG_H\n')
+            out_f.write('#include "bootutil/bootutil.h"\n')
+            out_f.writelines('\n'.join([
+                ' ',
+                'typedef enum',
+                '{',
+                    '\tIMAGE_BOOT_MODE_FLASH = 0U,',
+                    '\tIMAGE_BOOT_MODE_RAM = 1U,',
+                '} image_boot_mode_t;',
+                '',
+                'typedef struct image_boot_config_s {',
+                    '\timage_boot_mode_t mode;',
+                    '\tuint32_t address;',
+                    '\tuint32_t size;',
+                '} image_boot_config_t;',
+                '',
+                'extern image_boot_config_t image_boot_config[BOOT_IMAGE_NUMBER];'
+            ]))
+            out_f.write('\n#endif /* IMAGE_BOOT_CONFIG_H */\n')
+
+    except (FileNotFoundError, OSError):
+        print('Cannot create', out_f, file=sys.stderr)
+        sys.exit(Error.IO)
+                         
+
+def process_images(area_list, boot_and_upgrade):
+    """Process images"""
+    app_count = 0
+    slot_sectors_max = 0
+    all_shared = get_bool(boot_and_upgrade['bootloader'], 'shared_slot')
+    any_shared = all_shared
+    app_core = None
+    apps_flash_map = [None, ]
+    apps_ram_map = [None, ]
+
+    for stage in range(2):
+        for app_index in range(1, 5):
+
+            app_flash_map = {}
+            app_ram_map = {}
+            app_ram_boot = False
+
+            try:
+                app_ident = f'application_{app_index}'
+                application = boot_and_upgrade[app_ident]
+
+                try:
+                    flash = application['flash']
+                except KeyError:
+                    #Backward compatibility
+                    flash = application
+
+                try:
+                    config = application['config']
+                except KeyError:
+                    #Backward compatibility
+                    config = application
+
+                try:
+                    ram = application['ram']
+                except KeyError:
+                    try:
+                        ram = application['ram_boot']
+                        app_ram_boot = True
+                    except KeyError:
+                        ram = None
+
+                try:
+                    primary_addr = get_val(flash, 'address')
+                    primary_size = get_val(flash, 'size')
+                    secondary_addr = get_val(flash, 'upgrade_address')
+                    secondary_size = get_val(flash, 'upgrade_size')
+
+                    if ram is not None:
+                        app_ram_addr = get_val(ram, 'address')
+                        app_ram_size = get_val(ram, 'size')
+                    else:
+                        app_ram_addr = None
+                        app_ram_size = None
+
+                except KeyError as key:
+                    print('Malformed JSON:', key, 'is missing',
+                          file=sys.stderr)
+                    sys.exit(Error.JSON)
+                if stage == 0:
+                    if primary_size != secondary_size:
+                        print('Primary and secondary slot sizes'
+                              ' are different for', app_ident,
+                              file=sys.stderr)
+                        sys.exit(Error.VALUE)
+                    area_list.chk_area(primary_addr, primary_size)
+                    area_list.chk_area(secondary_addr, secondary_size,
+                                       primary_addr)
+                    if config is None or config.get('core') is None:
+                        if app_index == 1:
+                            app_core = area_list.plat['appCore']
+                    elif app_index > 1:
+                        print('"core" makes sense only for the 1st app',
+                              file=sys.stderr)
+                        sys.exit(Error.VALUE)
+                    else:
+                        app_core = get_str(config, 'core',
+                                           area_list.plat['appCore'])
+                    if app_index == 1:
+                        app_core = area_list.plat['allCores'].get(app_core.lower())
+                        if app_core is None:
+                            print('Unknown "core"', file=sys.stderr)
+                            sys.exit(Error.VALUE)
+                else:
+                    slot_sectors_max = max(
+                        slot_sectors_max,
+                        area_list.add_area(
+                            f'{app_ident} (primary slot)',
+                            f'FLASH_AREA_IMG_{app_index}_PRIMARY',
+                            primary_addr, primary_size,
+                            area_list.get_img_trailer_size()))
+                    shared_slot = get_bool(flash, 'shared_slot', all_shared)
+                    any_shared = any_shared or shared_slot
+                    slot_sectors_max = max(
+                        slot_sectors_max,
+                        area_list.add_area(
+                            f'{app_ident} (secondary slot)',
+                            f'FLASH_AREA_IMG_{app_index}_SECONDARY',
+                            secondary_addr, secondary_size,
+                            area_list.get_img_trailer_size(),
+                            shared_slot))
+
+                    app_slot_prim = {"address": hex(primary_addr), "size": hex(primary_size)}
+                    app_slot_sec = {"address": hex(secondary_addr), "size": hex(secondary_size)}
+
+                    app_flash_map.update({"primary": app_slot_prim, "secondary": app_slot_sec})
+                    apps_flash_map.append(app_flash_map)
+
+                    if ram is not None:
+                        app_ram_map.update({"address": app_ram_addr
+                                            , "size": app_ram_size
+                                            , "ram_boot": app_ram_boot})
+                        apps_ram_map.append(app_ram_map)
+                    else:
+                        apps_ram_map = None
+
+                app_count = app_index
+
+            except KeyError:
+                break
+        if app_count == 0:
+            print('Malformed JSON: no application(s) found',
+                  file=sys.stderr)
+            sys.exit(Error.JSON)
+
+    return app_core, app_count, slot_sectors_max, apps_flash_map, apps_ram_map, any_shared
+
+
+def process_policy_20829(in_policy):
+    """Process policy file to get data of NV-counter"""
+    list_counters = None
+
+    try:
+        with open(in_policy, encoding='UTF-8') as in_f:
+            try:
+                policy = json.load(in_f)
+            except ValueError:
+                print('\nERROR: Cannot parse', in_policy,'\n', file=sys.stderr)
+                sys.exit(Error.IO)
+            finally:
+                in_f.close()
+    except (FileNotFoundError, OSError):
+        print('Cannot open', in_policy, file=sys.stderr)
+        sys.exit(Error.IO)
+
+    try:
+        nv_cnt = policy["device_policy"]['reprovisioning']['nv_counter']
+        list_values = nv_cnt["value"]
+        list_counters = nv_cnt["bits_per_cnt"]
+    except KeyError:
+        print("\nERROR: Check path to 'nv_counter' and its correctness in policy file", in_policy,
+            ".\n", file=sys.stderr)
+        sys.exit(Error.POLICY)
+
+    #Check correctness of NV-counter
+    try:
+        len_list_value = len(list_values)
+        len_list_counters = len(list_counters)
+    except TypeError:
+        print("\nERROR: Fields 'value' and 'bits_per_cnt' of 'nv_counter' in policy file",
+            in_policy,"must be arrays.\n", file=sys.stderr)
+        sys.exit(Error.POLICY)
+
+    if len_list_value != len_list_counters:
+        print("\nERROR: Fields 'value' and 'bits_per_cnt' of 'nv_counter' in policy file",
+            in_policy,"must have the same size.\n", file=sys.stderr)
+        sys.exit(Error.POLICY)
+
+    sum_all_counters = 0
+    for i in range(len_list_value):
+        sum_all_counters += list_counters[i]
+        if list_values[i] > list_counters[i]:
+            print("\nERROR: Field 'value' cannot be more then 'bits_per_cnt'.", file=sys.stderr)
+            print("Check 'nv_counter' in policy file", in_policy,"\n", file=sys.stderr)
+            sys.exit(Error.POLICY)
+
+    sum_all_bit_nv_counter = 32
+    if sum_all_counters != sum_all_bit_nv_counter:
+        print("\nERROR: The sum of all 'bits_per_cnt' must be equal to 32.", file=sys.stderr)
+        print("Check 'nv_counter' in policy file", in_policy,"\n", file=sys.stderr)
+        sys.exit(Error.POLICY)
+
+    return list_counters
+
+
+def form_max_counter_array(in_list, out_file):
+    '''Write bit_per_count array to output file
+    There is expected, that "out_file" already exists'''
+
+    #ifdef here is needed to fix Rule 12.2 MISRA violation
+    out_array_str = "\n#ifdef NEED_MAX_COUNTERS\nstatic const uint8_t bits_per_cnt[] = {"
+
+    #in_list is checked in prior function 'process_policy()'
+    for i, list_member in enumerate(in_list):
+        out_array_str += str(list_member)
+        if i < len(in_list) - 1:
+            out_array_str += ", "
+    out_array_str += "};\n#endif\n"
+
+    try:
+        with open(out_file, "a", encoding='UTF-8') as out_f:
+            out_f.write(out_array_str)
+            out_f.write("\n#endif /* MEMORYMAP_H */")
+    except (FileNotFoundError, OSError):
+        print('\nERROR: Cannot open ', out_file, file=sys.stderr)
+        sys.exit(Error.CONFIG_MISMATCH)
+
+
+def main():
+    """Flash map converter"""
+    params = CmdLineParams()
+
+    try:
+        plat = platDict[params.plat_id]
+    except KeyError:
+        print('Supported platforms are:', ', '.join(platDict.keys()),
+              file=sys.stderr)
+        sys.exit(Error.POLICY)
+
+    try:
+        boot_and_upgrade, ram_app_staging, flash = process_json(params.in_file)
+        bootloader = boot_and_upgrade['bootloader']
+        try:
+            bootloader_config = bootloader['config']
+        except KeyError:
+            #Backward compatibility
+            bootloader_config = bootloader
+
+        if ram_app_staging is not None:
+            try:
+                ram_app_staging_size = get_val(ram_app_staging, 'size')
+                ram_app_staging_ext_mem_addr = get_val(ram_app_staging, 'external_mememory_address')
+                ram_app_staging_sram_stage_addr = get_val(ram_app_staging, 'sram_stage_address')
+                ram_app_staging_reset_trigger = get_bool(ram_app_staging, 'reset_after_staging')
+            except KeyError:
+                ram_app_staging = None
+
+        try:
+            bootloader_flash = bootloader['flash']
+        except KeyError:
+            #Backward compatibility
+            bootloader_flash = bootloader
+
+        try:
+            bootloader_ram = bootloader['ram']
+        except KeyError:
+            #Backward compatibility
+            bootloader_ram = bootloader
+
+        boot_flash_area = AddrSize(bootloader_flash, 'address', 'size')
+        boot_ram_area = AddrSize(bootloader_ram, 'address', 'size')
+    except KeyError as key:
+        print('Malformed JSON:', key, 'is missing',
+              file=sys.stderr)
+        sys.exit(Error.JSON)
+
+    try:
+        scratch = AddrSize(bootloader_flash, 'scratch_address', 'scratch_size')
+    except KeyError:
+        scratch = None
+
+    try:
+        swap_status = AddrSize(bootloader_flash, 'status_address', 'status_size')
+    except KeyError:
+        swap_status = None
+
+    try:
+        bootloader_shared_data = bootloader['shared_data']
+        boot_shared_data_area = AddrSize(bootloader_shared_data, 'address', 'size')
+    except KeyError:
+        boot_shared_data_area = None
+
+    try:
+        bootloader_startup = get_bool(bootloader_config, 'startup')
+    except KeyError:
+        bootloader_startup = None
+
+    try:
+        ram_app_area = AddrSize(bootloader_config['ram_boot'], 'address', 'size')
+    except  KeyError:
+        ram_app_area = None
+
+
+    # Create flash areas
+    area_list = AreaList(plat, flash, scratch is None and swap_status is None)
+    area_list.add_area('bootloader', 'FLASH_AREA_BOOTLOADER',
+                       boot_flash_area.addr, boot_flash_area.size)
+
+    # Service RAM app (optional)
+    service_app = boot_and_upgrade.get('service_app')
+    app_binary = None
+    input_params = None
+    app_desc = None
+    if service_app is not None:
+        if plat['flashSize'] > 0:
+            print('service_app is unsupported on this platform',
+                  file=sys.stderr)
+            sys.exit(Error.CONFIG_MISMATCH)
+        try:
+            app_binary = AddrSize(service_app, 'address', 'size')
+            input_params = AddrSize(service_app, 'params_address', 'params_size')
+            app_desc = AddrSize(service_app, 'desc_address', 'desc_size')
+            if input_params.addr != app_binary.addr + app_binary.size or \
+                    app_desc.addr != input_params.addr + input_params.size or \
+                    app_desc.size != SERVICE_APP_SZ:
+                print('Malformed service_app definition', file=sys.stderr)
+                sys.exit(Error.CONFIG_MISMATCH)
+            area_list.add_area('service_app', None, app_binary.addr,
+                               app_binary.size + input_params.size + app_desc.size)
+        except KeyError as key:
+            print('Malformed JSON:', key, 'is missing',
+                  file=sys.stderr)
+            sys.exit(Error.JSON)
+
+    # Fill flash areas
+    app_core, app_count, slot_sectors_max, apps_flash_map, apps_ram_map, shared_slot = \
+        process_images(area_list, boot_and_upgrade)
+
+    if params.image_boot_config:
+        image_boot_mode = process_boot_type(boot_and_upgrade)
+
+        if image_boot_mode:
+            generate_boot_type(image_boot_mode)
+
+    cy_img_hdr_size = 0x400
+    app_start = int(apps_flash_map[1].get("primary").get("address"), 0) + cy_img_hdr_size
+
+    if app_start % plat['VTAlign'] != 0:
+        print('Starting address', apps_flash_map[1].get("primary").get("address"),
+              '+', hex(cy_img_hdr_size),
+              'must be aligned to', hex(plat['VTAlign']),
+              file=sys.stderr)
+        sys.exit(Error.CONFIG_MISMATCH)
+
+    slot_sectors_max = max(slot_sectors_max, 32)
+
+    if swap_status is not None:
+        status_size_min = calc_status_size(area_list.get_min_erase_size(),
+                                           slot_sectors_max,
+                                           app_count,
+                                           scratch is not None)
+
+        if swap_status.size < status_size_min:
+            print('Insufficient swap status area - suggested size',
+                  hex(status_size_min),
+                  file=sys.stderr)
+            sys.exit(Error.CONFIG_MISMATCH)
+        area_list.add_area('swap status partition',
+                           'FLASH_AREA_IMAGE_SWAP_STATUS',
+                           swap_status.addr, swap_status.size)
+
+    if scratch is not None:
+        area_list.add_area('scratch area',
+                           'FLASH_AREA_IMAGE_SCRATCH',
+                           scratch.addr, scratch.size)
+
+    # Compare size 'bit_per_cnt' and number of images.
+    # 'service_app' is used only when HW rollback counter exists
+    if plat.get('bitsPerCnt') is not None and service_app is not None:
+        plat['bitsPerCnt'] = True
+        list_counters = process_policy_20829(params.policy)
+        if list_counters is not None and len(list_counters) != app_count:
+            print("\nERROR: 'bits_per_cnt' must be present for each image!",
+                file=sys.stderr)
+            print("Please, check secure provisioning and reprovisioning policies.\n",
+                file=sys.stderr)
+            sys.exit(Error.CONFIG_MISMATCH)
+
+    # Image id parameter is not used for MCUBootApp
+    if params.img_id is None:
+        area_list.generate_c_source(params)
+
+    area_list.create_flash_area_id(app_count, params)
+
+    # Report necessary values back to make
+    print('# AUTO-GENERATED FILE, DO NOT EDIT. ALL CHANGES WILL BE LOST!')
+    if params.set_core:
+        print('CORE :=', plat['allCores'][plat['bootCore'].lower()])
+
+    if ram_app_staging is not None:
+        print('USE_STAGE_RAM_APPS := 1')
+        print('RAM_APP_STAGING_EXT_MEM_ADDR := ', hex(ram_app_staging_ext_mem_addr))
+        print('RAM_APP_STAGING_SRAM_MEM_ADDR :=', hex(ram_app_staging_sram_stage_addr))
+        print('RAM_APP_STAGING_SIZE := ', hex(ram_app_staging_size))
+        if ram_app_staging_reset_trigger is True:
+            print('RAM_APP_RESET_TRIGGER := 1')
+
+    if bootloader_startup is True:
+        print('BOOTLOADER_STARTUP := 1')
+
+    if ram_app_area is not None:
+        print('USE_MCUBOOT_RAM_LOAD := 1')
+        print('IMAGE_EXECUTABLE_RAM_START :=', hex(ram_app_area.addr))
+        print('IMAGE_EXECUTABLE_RAM_SIZE :=', hex(ram_app_area.size))
+
+    if boot_shared_data_area is not None:
+        print('USE_MEASURED_BOOT := 1')
+        print('USE_DATA_SHARING := 1')
+        print('BOOT_SHARED_DATA_ADDRESS :=', hex(boot_shared_data_area.addr)+'U')
+        print('BOOT_SHARED_DATA_SIZE :=', hex(boot_shared_data_area.size)+'U')
+        print('BOOT_SHARED_DATA_RECORD_SIZE :=', hex(boot_shared_data_area.size)+'U')
+
+    print('BOOTLOADER_ORIGIN :=', hex(boot_flash_area.addr))
+    print('BOOTLOADER_SIZE :=', hex(boot_flash_area.size))
+    print('BOOTLOADER_RAM_ORIGIN :=', hex(boot_ram_area.addr))
+    print('BOOTLOADER_RAM_SIZE :=', hex(boot_ram_area.size))
+    print('APP_CORE :=', app_core)
+
+    if params.img_id is not None:
+        primary_img_start = apps_flash_map[int(params.img_id)].get("primary").get("address")
+        secondary_img_start = apps_flash_map[int(params.img_id)].get("secondary").get("address")
+        slot_size = apps_flash_map[int(params.img_id)].get("primary").get("size")
+
+        if apps_ram_map:
+            image_ram_address = apps_ram_map[int(params.img_id)].get("address")
+            image_ram_size = apps_ram_map[int(params.img_id)].get("size")
+            image_ram_boot = apps_ram_map[int(params.img_id)].get("ram_boot")
+            if image_ram_address and image_ram_size:
+                print('IMG_RAM_ORIGIN := ' + hex(image_ram_address))
+                print('IMG_RAM_SIZE := ' + hex(image_ram_size))
+                if image_ram_boot is True:
+                    print('USE_MCUBOOT_RAM_LOAD := 1')
+
+        print('PRIMARY_IMG_START := ' + primary_img_start)
+        print('SECONDARY_IMG_START := ' + secondary_img_start)
+        print('SLOT_SIZE := ' + slot_size)
+    else:
+        if apps_ram_map:
+            ram_load_counter = 0
+            for img in apps_ram_map:
+                if img is not None and img.get("ram_boot"):
+                    ram_load_counter += 1
+
+            if ram_load_counter != 0:
+                if ram_load_counter == 1 and app_count == 1:
+                    print('USE_MCUBOOT_RAM_LOAD := 1')
+                    print(f'IMAGE_EXECUTABLE_RAM_START := {hex(apps_ram_map[1].get("address"))}')
+                    print(f'IMAGE_EXECUTABLE_RAM_SIZE := {hex(apps_ram_map[1].get("size"))}')
+                else:
+                    print('USE_MCUBOOT_MULTI_MEMORY_LOAD := 1')
+
+        print('MAX_IMG_SECTORS :=', slot_sectors_max)
+
+    print('MCUBOOT_IMAGE_NUMBER :=', app_count)
+    if area_list.external_flash:
+        print('USE_EXTERNAL_FLASH := 1')
+    if area_list.external_flash_xip:
+        print('USE_XIP := 1')
+
+    if area_list.use_overwrite:
+        print('USE_OVERWRITE := 1')
+    if shared_slot:
+        print('USE_SHARED_SLOT := 1')
+    if service_app is not None:
+        print('PLATFORM_SERVICE_APP_OFFSET :=',
+              hex(app_binary.addr - plat['smifAddr']))
+        print('PLATFORM_SERVICE_APP_INPUT_PARAMS_OFFSET :=',
+              hex(input_params.addr - plat['smifAddr']))
+        print('PLATFORM_SERVICE_APP_DESC_OFFSET :=',
+              hex(app_desc.addr - plat['smifAddr']))
+        print('USE_HW_ROLLBACK_PROT := 1')
+
+
+if __name__ == '__main__':
+    main()
diff --git a/boot/cypress/scripts/memorymap_rework.py b/boot/cypress/scripts/memorymap_rework.py
new file mode 100644
index 0000000..47e681e
--- /dev/null
+++ b/boot/cypress/scripts/memorymap_rework.py
@@ -0,0 +1,582 @@
+"""
+Copyright 2023 Cypress Semiconductor Corporation (an Infineon company)
+or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+"""
+
+import sys
+import json
+import click
+
+APP_LIMIT = 8
+
+settings_dict = {
+        'overwrite'                 :   'USE_OVERWRITE'
+    ,   'swap'                      :   'USE_SWAP'
+    ,   'status'                    :   'USE_STATUS'
+    ,   'scratch'                   :   'USE_SCRATCH'
+    ,   'measured_boot'             :   'USE_MEASURED_BOOT'
+    ,   'data_sharing'              :   'USE_DATA_SHARING'
+    ,   'ram_load'                  :   'USE_MCUBOOT_RAM_LOAD'
+    ,   'multi_memory_load'         :   'USE_MCUBOOT_MULTI_MEMORY_LOAD'
+    ,   'shared_slot'               :   'USE_SHARED_SLOT'
+    ,   'ram_load_address'          :   'IMAGE_EXECUTABLE_RAM_START'
+    ,   'ram_load_size'             :   'IMAGE_EXECUTABLE_RAM_SIZE'
+    ,   'shared_data_address'       :   'BOOT_SHARED_DATA_ADDRESS'
+    ,   'shared_data_size'          :   'BOOT_SHARED_DATA_SIZE'
+    ,   'shared_data_record_size'   :   'BOOT_SHARED_DATA_RECORD_SIZE'
+    ,   'bootloader_app_address'    :   'BOOTLOADER_ORIGIN'
+    ,   'bootloader_app_size'       :   'BOOTLOADER_SIZE'
+    ,   'bootloader_ram_address'    :   'BOOTLOADER_RAM_ORIGIN'
+    ,   'bootloader_ram_size'       :   'BOOTLOADER_RAM_SIZE'
+    ,   'application_count'         :   'MCUBOOT_IMAGE_NUMBER'
+    ,   'boot_image'                :   'BOOT_IMAGE_NUMBER'
+    ,   'sectors_count'             :   'MAX_IMG_SECTORS'
+    ,   'core'                      :   'CORE'
+    ,   'image_ram_address'         :   'IMG_RAM_ORIGIN'
+    ,   'image_ram_size'            :   'IMG_RAM_SIZE'
+    ,   'primary_image_start'       :   'PRIMARY_IMG_START'
+    ,   'secondary_image_start'     :   'SECONDARY_IMG_START'
+    ,   'image_size'                :   'SLOT_SIZE'
+}
+
+def header_guard_generate(file):
+    file.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
+                    ' ALL CHANGES WILL BE LOST! */\n')
+    file.write("#pragma once\n\n")
+
+def is_overlap(x : int, y : int) -> bool:
+    if x.start == x.stop or y.start == y.stop:
+        return False
+    return x.start < y.stop and y.start < x.stop
+
+def is_aligned(addr : int, sz : int) -> bool:
+    ''' Check address alignment '''
+    return addr % sz == 0
+
+class Memory:
+    ''' Memory handler '''
+    def __init__(self, addr, sz):
+        self.addr   : int = addr
+        self.sz     : int = sz
+
+    def overlaps_with(self, other) -> bool:
+        ''' Check Memory for intersection
+            @return Bool
+        '''
+        first = range(self.addr, self.addr + self.sz)
+        second = range(other.addr, other.addr + other.sz)
+
+        return is_overlap(first, second)
+
+    def fits_with(self, other) -> bool:
+        '''
+
+        '''
+        return \
+            self.addr >= other.addr and \
+            self.addr + self.sz <= other.addr + other.sz
+
+class MemoryRegion(Memory):
+    ''' Memory region handler '''
+    def __init__(self, addr, sz, erase_sz, erase_val, type):
+        super().__init__(addr, sz)
+        self.erase_sz   : int   = erase_sz
+        self.erase_val  : int   = erase_val
+        self.type               = type
+
+class BootloaderLayout:
+    '''
+        Handler for bootloader memory layout
+    '''
+    def __init__(self):
+        self.bootloader_area    : Memory    = None
+        self.ram                : Memory    = None
+        self.scratch_area       : Memory    = None
+        self.status_area        : Memory    = None
+        self.shared_data        : Memory    = None
+        self.shared_upgrade     : Memory    = None
+        self.core_name          : int       = None
+
+    @property
+    def has_shared_upgrade(self) -> bool:
+        return self.shared_upgrade is not None
+
+    @property
+    def has_shared_data(self) -> bool:
+        return self.shared_data is not None
+
+    @property
+    def has_scratch_area(self) -> bool:
+        return self.scratch_area is not None
+
+    @property
+    def has_status_area(self) -> bool:
+        return self.status_area is not None
+
+    def parse(self, section : json):
+        '''
+            Parse JSON section and init fields.
+        '''
+        try:
+            fields = ('bootloader_area', 'scratch_area', 'status_area', \
+                      'shared_data', 'shared_upgrade', 'ram')
+            for field in fields:
+                area = section.get(field)
+                if area:
+                    setattr(self, field, Memory(int(area['address'], 0),
+                                                int(area['size'], 0)))
+
+            core = section.get('core')
+            if core:
+                self.core_name = core
+
+        except KeyError as key:
+            print('Malformed JSON:', key, 'is missing')
+
+class MemoryAreaConfig:
+    '''
+        Handler for flash area configuration
+    '''
+    def __init__(self, area_name, device_name, offset, size):
+        self.fa_id          : str   = area_name
+        self.fa_device_id   : str   = device_name
+        self.fa_off         : int   = offset
+        self.fa_size        : int   = size
+
+class ApplicationLayout:
+    '''
+        Handler for application memory layout
+    '''
+    def __init__(self):
+        self.boot_area      : Memory        = None
+        self.upgrade_area   : Memory        = None
+        self.ram            : Memory        = None
+        self.ram_boot       : Memory        = None
+        self.core_name      : str           = None
+
+    @property
+    def has_ram_boot(self) -> bool:
+        return self.ram_boot is not None
+
+    @property
+    def has_upgrade_area(self) -> bool:
+        return self.upgrade_area is not None
+
+    def overlaps_with(self, other) -> bool:
+        return \
+            self.boot_area.overlaps_with(other.boot_area) or \
+            self.upgrade_area.overlaps_with(other.upgrade_area)
+
+    def parse(self, section : json):
+        '''
+            Parse JSON section and init fields.
+        '''
+        try:
+            slots = section['slots']
+            boot_address = int(slots['boot'], 0)
+            upgrade_address =  int(slots['upgrade'], 0)
+            slot_size = int(slots['size'], 0)
+
+            self.boot_area = Memory(boot_address, slot_size)
+            self.upgrade_area = Memory(upgrade_address, slot_size)
+
+            fields = ('ram', 'ram_boot')
+            for field in fields:
+                area = section.get(field)
+                if area:
+                    setattr(self, field, Memory(int(area['address'], 0),
+                                                int(area['size'], 0)))
+
+            core = section.get('core')
+            if core:
+                self.core_name = core
+
+        except KeyError as key:
+            print('Malformed JSON:', key, 'is missing')
+
+class MemoryMap:
+    '''
+        General handler
+    '''
+    def __init__(self):
+        self.boot_layout    : BootloaderLayout      = None
+        self.regions        : MemoryRegion          = []
+        self.region_types   : str                   = []
+        self.apps           : ApplicationLayout     = []
+        self.primary_slots  : str                   = []
+        self.secondary_slots: str                   = []
+        self.mem_areas      : MemoryAreaConfig      = []
+        self.param_dict                             = {}
+        self.map_json       : json                  = None
+        self.platform_json  : json                  = None
+        self.output_folder                          = None
+        self.output_name                            = None
+        self.max_sectors                            = 32
+
+    def __apps_init(self):
+        for image_number in range(1, APP_LIMIT):
+            app_ident   = f'application_{image_number}'
+            section     = self.map_json.get(app_ident)
+
+            if section:
+                app_layout = ApplicationLayout()
+                app_layout.parse(section)
+
+                self.apps.append(app_layout)
+            else:
+                break
+
+    def __boot_layout_init(self):
+        self.boot_layout = BootloaderLayout()
+        self.boot_layout.parse(self.map_json['bootloader'])
+
+    def __memory_regions_init(self):
+        memory_regions = self.platform_json['memory_regions']
+        for region in memory_regions:
+            try:
+                addr        = int(region['address'], 0)
+                size        = int(region['size'], 0)
+                erase_size  = int(region['erase_size'], 0)
+                erase_value = int(region['erase_value'], 0)
+                type        = str(region['type'])
+
+                if type not in self.region_types:
+                    self.region_types.append(type)
+
+                self.regions.append(MemoryRegion(addr, size, erase_size, erase_value, type))
+            except KeyError as key:
+                print('Malformed JSON:', key, 'is missing')
+
+        # Check regions for overlap
+        for this in self.regions:
+            for other in self.regions:
+                if this is other:
+                    continue
+                if this.overlaps_with(other):
+                    # TODO: Notify regions overlap
+                    raise Exception()
+
+    def __memory_area_find_region_id(self, area : Memory) -> int:
+        for region_id, region in enumerate(self.regions):
+            if area.fits_with(region):
+                return region_id
+        return None
+
+    def __memory_area_config_create(self, key):
+        param_dict = self.param_dict
+        area = param_dict[key][0]
+        area_name = param_dict[key][1]
+
+        region_id = self.__memory_area_find_region_id(area)
+        region = self.regions[region_id]
+        region_name = region.type
+
+        offset = area.addr - region.addr
+        size = area.sz
+
+        area_config = MemoryAreaConfig(area_name,\
+                                       region_name, \
+                                       offset, \
+                                       size)
+
+        self.mem_areas.append(area_config)
+
+        # Update max sectors
+        slot_sectors = int((offset % region.erase_sz +
+                            size + region.erase_sz - 1) //
+                            region.erase_sz)
+
+        self.max_sectors = max(self.max_sectors, slot_sectors)
+
+    def __memory_areas_create(self):
+        # Generate FA indexes
+        param_dict = self.param_dict
+        bootloader_area = self.boot_layout.bootloader_area
+        main_app = self.apps[0]
+        boot_area = main_app.boot_area
+        upgrade_area = main_app.upgrade_area
+        scratch_area = self.boot_layout.scratch_area
+
+        param_dict.update({'bootloader': [bootloader_area, 'FLASH_AREA_BOOTLOADER', 0]})
+        param_dict.update({'app_1_boot': [boot_area, 'FLASH_AREA_IMG_1_PRIMARY', 1]})
+        param_dict.update({'app_1_upgrade': [upgrade_area, 'FLASH_AREA_IMG_1_SECONDARY', 2]})
+
+        self.primary_slots.append('FLASH_AREA_IMG_1_PRIMARY')
+        self.secondary_slots.append('FLASH_AREA_IMG_1_SECONDARY')
+
+        # Generate scratch area index
+        if self.boot_layout.has_scratch_area:
+            param_dict.update({'scratch_area': [scratch_area, 'FLASH_AREA_IMAGE_SCRATCH', 3]})
+
+        # Generate multiple app area indexes
+        multi_app_area_idx = 4
+        if len(self.apps) > 1:
+            for app_id, app in enumerate(self.apps[1:], 1):
+                idx = multi_app_area_idx + (app_id-1) * 2
+                app_num = app_id + 1
+                key = f'app_{app_num}_boot'
+                fmt = f'FLASH_AREA_IMG_{app_num}_PRIMARY'
+                param_dict.update({key: [app.boot_area, fmt, idx]})
+
+                self.primary_slots.append(fmt)
+
+                key = f'app_{app_num}_upgrade'
+                fmt = f'FLASH_AREA_IMG_{app_num}_SECONDARY'
+                param_dict.update({key: [app.upgrade_area, fmt, idx+1]})
+
+                self.secondary_slots.append(fmt)
+
+        # Generate status area indexes
+        if self.boot_layout.has_status_area:
+            area = self.boot_layout.status_area
+            idx = multi_app_area_idx + (len(self.apps)-1) * 2
+            fmt = 'FLASH_AREA_IMAGE_SWAP_STATUS'
+            param_dict.update({'status_area': [area, fmt, idx]})
+
+        # Create areas
+        for key in param_dict:
+            self.__memory_area_config_create(key)
+
+    def __source_gen(self):
+        path = f'{self.output_folder}/{self.output_name}.c'
+        include = f'{self.output_name}.h'
+
+        with open(path, "w", encoding='UTF-8') as f_out:
+            f_out.write(f'#include "{include}"\n')
+            f_out.write(f'#include "flash_map_backend.h"\n\n')
+            f_out.write('struct flash_device flash_devices[] =\n')
+            f_out.write('{\n')
+            for region in self.regions:
+                f_out.write('\t{\n')
+                f_out.write(f'\t\t.address      = {hex(region.addr)}U,\n')
+                f_out.write(f'\t\t.size         = {hex(region.sz)}U,\n')
+                f_out.write(f'\t\t.erase_size   = {hex(region.erase_sz)}U,\n')
+                f_out.write(f'\t\t.erase_val    = {hex(region.erase_val)}U,\n')
+                f_out.write(f'\t\t.device_id    = {str(region.type)},\n')
+                f_out.write('\t},\n')
+            f_out.write('};\n\n')
+
+            f_out.write(f'struct flash_area flash_areas[] =\n')
+            f_out.write('{\n')
+            for area in self.mem_areas:
+                f_out.writelines('\n'.join([
+                    '\t{',
+                    f"\t\t.fa_id        = {area.fa_id},",
+                    f"\t\t.fa_device_id = {area.fa_device_id},",
+                    f"\t\t.fa_off       = {hex(area.fa_off)}U,",
+                    f"\t\t.fa_size      = {hex(area.fa_size)}U,",
+                    '\t},\n']))
+            f_out.write('};\n\n')
+
+            f_out.write('struct flash_area *boot_area_descs[] =\n')
+            f_out.write('{\n')
+            for index, area in enumerate(self.mem_areas):
+                f_out.write(f'\t&flash_areas[{index}U],\n')
+            f_out.write('\tNULL\n};\n\n')
+
+            f_out.write('uint8_t memory_areas_primary[] =\n')
+            f_out.write('{\n')
+            for slot in self.primary_slots:
+                f_out.write(f'\t{slot}, ')
+            f_out.write('\n};\n\n')
+
+            f_out.write('uint8_t memory_areas_secondary[] =\n')
+            f_out.write('{\n')
+            for slot in self.secondary_slots:
+                f_out.write(f'\t{slot}, ')
+            f_out.write('\n};\n\n')
+
+    def __header_gen(self):
+        path = f'{self.output_folder}/{self.output_name}.h'
+        with open(path, "w", encoding='UTF-8') as f_out:
+            header_guard_generate(f_out)
+
+            f_out.write(f'#include <stdint.h>\n')
+            f_out.write(f'#include "flash_map_backend.h"\n\n')
+            f_out.write(f'#define MEMORYMAP_GENERATED_AREAS 1\n\n')
+            f_out.write('extern struct flash_device flash_devices[];\n')
+            f_out.write('extern struct flash_area *boot_area_descs[];\n\n')
+            f_out.write('extern uint8_t memory_areas_primary[];\n')
+            f_out.write('extern uint8_t memory_areas_secondary[];\n\n')
+
+            f_out.write('enum \n{\n')
+            for id, type in enumerate(self.region_types):
+                f_out.write(f'\t{type} = {id}U,\n')
+            f_out.write('};\n\n')
+
+            f_out.write('enum \n{\n')
+            for area_param in self.param_dict.values():
+                f_out.write(f'\t{area_param[1]} = {area_param[2]}U,\n')
+            f_out.write('};\n\n')
+
+    def __bootloader_mk_file_gen(self):
+        boot = self.boot_layout
+        # Upgrade mode
+        if boot.scratch_area is None and boot.status_area is None:
+            print(settings_dict['overwrite'], ':= 1')
+        else:
+            print(settings_dict['overwrite'], ':= 0')
+            print(settings_dict['swap'], ':= 1')
+            print(settings_dict['scratch'], f':= {0 if boot.scratch_area is None else 1}')
+            print(settings_dict['status'], f':= {0 if boot.status_area is None else 1}')
+        print('# Shared data')
+        if boot.shared_data is not None:
+            shared_data = boot.shared_data
+            print(settings_dict['measured_boot'], ':= 1')
+            print(settings_dict['data_sharing'], ':= 1')
+
+            print(f'{settings_dict["shared_data_address"]} :=', hex(shared_data.addr))
+            print(f'{settings_dict["shared_data_size"]} :=', hex(shared_data.sz))
+            print(f'{settings_dict["shared_data_record_size"]} :=', hex(shared_data.sz))
+
+        print('# Bootloader app area')
+        print(f'{settings_dict["bootloader_app_address"]} :=', hex(boot.bootloader_area.addr))
+        print(f'{settings_dict["bootloader_app_size"]} :=', hex(boot.bootloader_area.sz))
+
+        print('# Bootloader ram area')
+        if boot.ram is not None:
+            print(f'{settings_dict["bootloader_ram_address"]} :=', hex(boot.ram.addr))
+            print(f'{settings_dict["bootloader_ram_size"]} :=', hex(boot.ram.sz))
+
+        print('# Application area')
+        for id, app in enumerate(self.apps):
+            print(f'APPLICATION_{id+1}_BOOT_SLOT_ADDRESS := {hex(app.boot_area.addr)}')
+            print(f'APPLICATION_{id+1}_BOOT_SLOT_SIZE := {hex(app.boot_area.sz)}')
+            print(f'APPLICATION_{id+1}_UPGRADE_SLOT_ADDRESS := {hex(app.upgrade_area.addr)}')
+            print(f'APPLICATION_{id+1}_UPGRADE_SLOT_SIZE := {hex(app.upgrade_area.sz)}')
+
+        print('# Ram load')
+        # Ram load single
+        if len(self.apps) == 1:
+            if self.apps[0].ram_boot is not None:
+                ram_boot = self.apps[0].ram_boot
+                print(settings_dict['ram_load'], ':= 1')
+                print(f'{settings_dict["ram_load_address"]} :=', hex(ram_boot.addr))
+                print(f'{settings_dict["ram_load_size"]} :=', hex(ram_boot.sz))
+        else:
+        # Ram load multiple
+            ram_boot_counter = 0
+            ram_addr_overlap_counter = 0
+
+            for app1 in self.apps:
+                for app2 in self.apps:
+                    if app1 is app2:
+                        continue
+                    if app1.overlaps_with(app2):
+                        ram_addr_overlap_counter += 1
+
+            for id, app in enumerate(self.apps):
+                if app.ram_boot is not None:
+                    ram_boot_counter += 1
+                    ram_boot = app.ram_boot
+
+                    print(f'APPLICATION_{id+1}_RAM_LOAD_ADDRESS := {hex(ram_boot.addr)}')
+                    print(f'APPLICATION_{id+1}_RAM_LOAD_SIZE := {hex(ram_boot.sz)}')
+
+            if ram_boot_counter != 0:
+                print(settings_dict['ram_load'], ':= 1')
+
+                if ram_boot_counter != len(self.apps) or ram_addr_overlap_counter == 0:
+                    print(settings_dict['multi_memory_load'], ':= 1')
+
+        print('# Mcuboot')
+        print(settings_dict['application_count'], f'= {len(self.apps)}')
+        print(settings_dict['sectors_count'], f'= {self.max_sectors}')
+
+    def __application_mk_file_gen(self):
+        app = self.apps[self.app_id-1]
+        boot = self.boot_layout
+        # Upgrade mode
+        if boot.scratch_area is None and boot.status_area is None:
+            print(settings_dict['overwrite'], ':= 1')
+        else:
+            print(settings_dict['overwrite'], ':= 0')
+            print(settings_dict['swap'], ':= 1')
+            print(settings_dict['scratch'], f':= {0 if boot.scratch_area is None else 1}')
+            print(settings_dict['status'], f':= {0 if boot.status_area is None else 1}')
+
+        print(settings_dict['application_count'], f'= {len(self.apps)}')
+        print(settings_dict['boot_image'], ':=', self.app_id)
+        print(settings_dict['primary_image_start'], ':=', hex(app.boot_area.addr))
+        print(settings_dict['secondary_image_start'], ':=', hex(app.upgrade_area.addr))
+        print(settings_dict['image_size'], ':=', hex(app.boot_area.sz))
+        if app.ram_boot:
+            print(settings_dict['ram_load'], ':= 1')
+        if app.ram:
+            print(settings_dict['image_ram_address'], ':=',  hex(app.ram.addr))
+            print(settings_dict['image_ram_size'], ':=',  hex(app.ram.sz))
+        if app.core_name:
+            print(settings_dict['core'], ':=',  app.core_name)
+
+    def parse(self, memory_map, platform_config, output_folder, output_name, app_id):
+        try:
+            with open(memory_map, "r", encoding='UTF-8') as f_in:
+                self.map_json = json.load(f_in)
+
+            with open(platform_config, "r", encoding='UTF-8') as f_in:
+                self.platform_json = json.load(f_in)
+
+            self.output_folder  = output_folder
+            self.output_name    = output_name
+
+            if app_id is not None:
+                self.app_id = int(app_id)
+
+            self.__memory_regions_init()
+            self.__boot_layout_init()
+            self.__apps_init()
+            self.__memory_areas_create()
+
+            self.__source_gen()
+            self.__header_gen()
+
+            if app_id is None:
+                self.__bootloader_mk_file_gen()
+            else:
+                self.__application_mk_file_gen()
+
+        except (FileNotFoundError, OSError):
+            print('\nERROR: Cannot open ', f_in, file=sys.stderr)
+            sys.exit(-1)
+
+
+@click.group()
+def cli():
+    '''
+        Memory map layout parser-configurator
+    '''
+
+@cli.command()
+@click.option('-i', '--memory_config', required=True,
+              help='memory configuration file path')
+@click.option('-p', '--platform_config', required=True,
+              help='platform configuration file path')
+@click.option('-n', '--output_name', required=True,
+              help='generated areas path')
+@click.option('-o', '--output_folder', required=True,
+              help='generated regions path')
+@click.option('-d', '--image_id', required=False,
+              help='application image number')
+
+def run(memory_config, platform_config, output_folder, output_name, image_id):
+    map = MemoryMap()
+    map.parse(memory_config,
+              platform_config,
+              output_folder,
+              output_name,
+              image_id)
+
+if __name__ == '__main__':
+    cli()
\ No newline at end of file
diff --git a/boot/cypress/toolchains.mk b/boot/cypress/toolchains.mk
index 71a8348..00df790 100644
--- a/boot/cypress/toolchains.mk
+++ b/boot/cypress/toolchains.mk
@@ -63,7 +63,7 @@
 	LD := $(CC)
 endif
 
-PDL_ELFTOOL := "hal/tools/$(HOST_OS)/elf/cymcuelftool"
+PDL_ELFTOOL := $(TOOLCHAIN_PATH)/../cymcuelftool-1.0/bin/cymcuelftool
 
 OBJDUMP  := "$(GCC_PATH)/bin/arm-none-eabi-objdump"
 OBJCOPY  := "$(GCC_PATH)/bin/arm-none-eabi-objcopy"
@@ -72,37 +72,47 @@
 ifeq ($(COMPILER), GCC_ARM)
 	# set build-in compiler flags
 	CFLAGS_COMMON :=  -mthumb -ffunction-sections -fdata-sections  -g -Wall -Wextra
+	CFLAGS_COMMON += -Wno-discarded-qualifiers -Wno-ignored-qualifiers # KILLME
+
+	ifeq ($(WARN_AS_ERR), 1)
+		CFLAGS_COMMON += -Werror
+	endif
+
 	ifeq ($(BUILDCFG), Debug)
 		CFLAGS_SPECIAL ?= -Og -g3
 		CFLAGS_COMMON += $(CFLAGS_SPECIAL)
 	else ifeq ($(BUILDCFG), Release)
-		CFLAGS_COMMON += -Os -g -DNDEBUG
+		ifeq ($(CFLAGS_OPTIMIZATION), )
+			# Blinky upgrade releas XIP WORKAROUND
+			CFLAGS_COMMON += -Os -g -DNDEBUG
+		endif
 	else
 $(error BUILDCFG : '$(BUILDCFG)' is not supported)
 	endif
 
-	# ifeq ($(CORE), CM33)
-	# 	CFLAGS_PLATFORM := -c -mcpu=cortex-m33+nodsp --specs=nano.specs
-	# else
-	# 	CFLAGS_PLATFORM := -mcpu=cortex-$(CORE_SUFFIX) -mfloat-abi=soft -fno-stack-protector -fstrict-aliasing
-	# endif
-
-	# $CFLAGS_PLATFORM is defined in plaform specific mk file
 	CFLAGS := $(CFLAGS_COMMON) $(CFLAGS_PLATFORM) $(INCLUDES)
 
 	CC_DEPEND = -MD -MP -MF
 
 	LDFLAGS_COMMON := -mcpu=cortex-$(CORE_SUFFIX) -mthumb -specs=nano.specs -ffunction-sections -fdata-sections  -Wl,--gc-sections -ffat-lto-objects -g --enable-objc-gc
+
+	ifeq ($(WARN_AS_ERR), 1)
+		LDFLAGS_COMMON += -Wl,--fatal-warnings
+	endif
+
 	ifeq ($(BUILDCFG), Debug)
 		LDFLAGS_SPECIAL ?= -Og
 		LDFLAGS_COMMON += $(LDFLAGS_SPECIAL)
 	else ifeq ($(BUILDCFG), Release)
-		LDFLAGS_OPTIMIZATION ?= -Os
+		ifeq ($(CFLAGS_OPTIMIZATION), )
+			# Blinky upgrade releas XIP WORKAROUND
+			LDFLAGS_OPTIMIZATION ?= -Os
+		endif
 	else
 $(error BUILDCFG : '$(BUILDCFG)' is not supported)
 	endif
 	LDFLAGS_NANO := -L "$(GCC_PATH)/arm-none-eabi/lib/thumb/v6-m"
-	LDFLAGS := $(LDFLAGS_COMMON) $(LDFLAGS_NANO)
+	LDFLAGS := $(LDFLAGS_COMMON) $(LDFLAGS_NANO) $(LDFLAGS_PLATFORM)
 endif
 
 ###############################################################################