Infineon: Switch to 1.9.0 code base, add xmc7000 family support, refactor memory layer
diff --git a/boot/espressif/secureboot-sign-rsa3072.conf b/boot/espressif/secureboot-sign-rsa3072.conf
new file mode 100644
index 0000000..66825e0
--- /dev/null
+++ b/boot/espressif/secureboot-sign-rsa3072.conf
@@ -0,0 +1,28 @@
+# SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ATTENTION:
+# This configuration file targets the building for CI environment and contains
+# a set of definitions to resemble a bootloader image for RELEASE environment.
+# Running the generated firmware image may result in irreversible operations
+# to the chip!
+
+CONFIG_SECURE_SIGNED_ON_BOOT=1
+CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME=1
+CONFIG_SECURE_BOOT=1
+CONFIG_SECURE_BOOT_V2_ENABLED=1
+CONFIG_SECURE_BOOT_SUPPORTS_RSA=1
+CONFIG_SECURE_FLASH_ENC_ENABLED=1
+CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE=1
+CONFIG_ESP_SIGN_KEY_FILE=root-rsa-3072.pem
+CONFIG_ESP_USE_MBEDTLS=1
+CONFIG_ESP_SIGN_RSA=1
+CONFIG_ESP_SIGN_RSA_LEN=3072
+CONFIG_ESP_BOOTLOADER_SIZE=0xF000
+CONFIG_ESP_APPLICATION_PRIMARY_START_ADDRESS=0x10000
+CONFIG_ESP_APPLICATION_SIZE=0x100000
+CONFIG_ESP_APPLICATION_SECONDARY_START_ADDRESS=0x110000
+CONFIG_ESP_MCUBOOT_WDT_ENABLE=1
+CONFIG_ESP_SCRATCH_OFFSET=0x210000
+CONFIG_ESP_SCRATCH_SIZE=0x40000