Infineon: Add PSoC63, PSoC61 platforms, update hw crypto acceleration, allow build on CM4 build
Release notes:
1. Added platforms PSoC63, PSoC61
2. Added possibility to build MCUBootApp for CM4 core and BlinkyApp for CM0p
3. Updated cy-mbedtls-acceleration package to support mbedtls-3.0
4. Change CY_SMIF_SYSCLK_HFCLK_DIVIDER to achieve increased SMIF clock source
5. Improved memory map configuration in json files
6. Added optional performance measurement macros
7. Improved usage of FIH types in security critical code branches
8. Updated documentation
9. Improved MISRAa nd CERT-C compliance
10. Switch to latest mtb-pdl-cat1 3.0.0
11. Fixed minor bugs
diff --git a/boot/bootutil/include/bootutil/boot_status.h b/boot/bootutil/include/bootutil/boot_status.h
index 0364870..d1be1e4 100644
--- a/boot/bootutil/include/bootutil/boot_status.h
+++ b/boot/bootutil/include/bootutil/boot_status.h
@@ -65,9 +65,9 @@
*/
/* General macros to handle TLV type */
-#define MAJOR_MASK 0xF /* 4 bit */
-#define MAJOR_POS 12 /* 12 bit */
-#define MINOR_MASK 0xFFF /* 12 bit */
+#define MAJOR_MASK 0xFu /* 4 bit */
+#define MAJOR_POS 12u /* 12 bit */
+#define MINOR_MASK 0xFFFu /* 12 bit */
#define SET_TLV_TYPE(major, minor) \
(((uint16_t)((major) & MAJOR_MASK) << MAJOR_POS) \
@@ -76,7 +76,7 @@
#define GET_MINOR(tlv_type) ((tlv_type) & MINOR_MASK)
/* Magic value which marks the beginning of shared data area in memory */
-#define SHARED_DATA_TLV_INFO_MAGIC 0x2016
+#define SHARED_DATA_TLV_INFO_MAGIC 0x2016u
/* Initial attestation specific macros */
@@ -84,28 +84,34 @@
* Major numbers (4 bit) to identify the
* consumer of shared data in runtime SW.
*/
-#define TLV_MAJOR_IAS 0x1
+#define TLV_MAJOR_IAS 0x1u
+#define TLV_MAJOR_FWU 0x2u
/* Initial attestation: Claim per SW components / SW modules */
/* Bits: 0-2 */
-#define SW_VERSION 0x00
-#define SW_SIGNER_ID 0x01
-/* Reserved 0x02 */
-#define SW_TYPE 0x03
+#define SW_VERSION 0x00u
+#define SW_SIGNER_ID 0x01u
+/* Reserved 0x02u */
+#define SW_TYPE 0x03u
/* Bits: 3-5 */
-#define SW_MEASURE_VALUE 0x08
-#define SW_MEASURE_TYPE 0x09
-#define SW_BOOT_RECORD 0x3F
+#define SW_MEASURE_VALUE 0x08u
+#define SW_MEASURE_TYPE 0x09u
+#define SW_BOOT_RECORD 0x3Fu
-#define MODULE_POS 6 /* 6 bit */
-#define CLAIM_MASK 0x3F /* 6 bit */
-#define MEASUREMENT_CLAIM_POS 3 /* 3 bit */
+#define MODULE_POS 6u /* 6 bit */
+#define MODULE_MASK 0x3Fu /* 6 bit */
+#define CLAIM_MASK 0x3Fu /* 6 bit */
+#define MEASUREMENT_CLAIM_POS 3u /* 3 bit */
#define GET_IAS_MODULE(tlv_type) ((uint16_t)GET_MINOR(tlv_type) >> MODULE_POS)
#define GET_IAS_CLAIM(tlv_type) (GET_MINOR(tlv_type) & CLAIM_MASK)
#define SET_IAS_MINOR(sw_module, claim) \
(((uint16_t)(sw_module) << MODULE_POS) | (claim))
+#define SET_FWU_MINOR(sw_module, claim) \
+ ((uint16_t)((sw_module & MODULE_MASK) << MODULE_POS) | \
+ (uint16_t)(claim & CLAIM_MASK))
+
/**
* Shared data TLV header. All fields in little endian.
*
diff --git a/boot/bootutil/include/bootutil/fault_injection_hardening.h b/boot/bootutil/include/bootutil/fault_injection_hardening.h
index a9c58ec..bccdbc2 100644
--- a/boot/bootutil/include/bootutil/fault_injection_hardening.h
+++ b/boot/bootutil/include/bootutil/fault_injection_hardening.h
@@ -88,6 +88,9 @@
extern "C" {
#endif /* __cplusplus */
+#define FIH_TRUE ((int)1)
+#define FIH_FALSE ((int)0)
+
/* Non-zero success value to defend against register resets. Zero is the most
* common value for a corrupted register so complex bit-patterns are used
*/
diff --git a/boot/bootutil/src/boot_record.c b/boot/bootutil/src/boot_record.c
index e3a2208..b6b0e50 100644
--- a/boot/bootutil/src/boot_record.c
+++ b/boot/bootutil/src/boot_record.c
@@ -24,6 +24,7 @@
#include "mcuboot_config/mcuboot_config.h"
#if defined(MCUBOOT_MEASURED_BOOT) || defined(MCUBOOT_DATA_SHARING)
+#include "bootutil/crypto/sha256.h"
#include "bootutil/boot_record.h"
#include "bootutil/boot_status.h"
#include "bootutil_priv.h"
@@ -62,6 +63,7 @@
return SHARED_MEMORY_GEN_ERROR;
}
+ /* Shared data section must be aligned as 'void*' */
assert(((uintptr_t)MCUBOOT_SHARED_DATA_BASE & 3u) == 0u);
boot_data = (struct shared_boot_data *)MCUBOOT_SHARED_DATA_BASE;
@@ -74,10 +76,6 @@
boot_data->header.tlv_tot_len = SHARED_DATA_HEADER_SIZE;
shared_memory_init_done = true;
}
- else if (boot_data->header.tlv_magic != SHARED_DATA_TLV_INFO_MAGIC ||
- boot_data->header.tlv_tot_len != SHARED_DATA_HEADER_SIZE) {
- return SHARED_MEMORY_CORRUPTED;
- }
/* Check whether TLV entry is already added.
* Get the boundaries of TLV section
@@ -236,4 +234,44 @@
return 0;
}
+
#endif /* MCUBOOT_MEASURED_BOOT */
+
+#ifdef MCUBOOT_DATA_SHARING
+
+int boot_save_shared_data(const struct image_header *hdr,
+ const struct flash_area *fap)
+{
+ uint16_t fwu_minor;
+ const struct flash_area *temp_fap;
+ uint8_t fwu_img_id = 0;
+ uint8_t i;
+
+ if (NULL == hdr || NULL == fap) {
+ return -1;
+ }
+
+ for (i = 0; i < MCUBOOT_IMAGE_NUMBER; i++) {
+ if (flash_area_open(FLASH_AREA_IMAGE_PRIMARY(i),
+ &temp_fap) != 0) {
+ return -1;
+ }
+
+ if (fap == temp_fap) {
+ fwu_img_id = i;
+ break;
+ }
+ }
+
+ if (MCUBOOT_IMAGE_NUMBER == i) {
+ return -1;
+ }
+
+ /* Currently hardcode it to 0 which indicates the full image. */
+ fwu_minor = SET_FWU_MINOR(fwu_img_id, SW_VERSION);
+ return boot_add_data_to_shared_area(TLV_MAJOR_FWU,
+ fwu_minor,
+ sizeof(hdr->ih_ver),
+ (const uint8_t *)&hdr->ih_ver);
+}
+#endif /* MCUBOOT_DATA_SHARING */
diff --git a/boot/bootutil/src/bootutil_misc.c b/boot/bootutil/src/bootutil_misc.c
index 75e53d3..b817640 100644
--- a/boot/bootutil/src/bootutil_misc.c
+++ b/boot/bootutil/src/bootutil_misc.c
@@ -157,13 +157,14 @@
}
#endif
+#ifndef MCUBOOT_SWAP_USING_STATUS
+
static inline uint32_t
boot_magic_off(const struct flash_area *fap)
{
return flash_area_get_size(fap) - BOOT_MAGIC_SZ;
}
-#ifndef MCUBOOT_SWAP_USING_STATUS
static inline uint32_t
boot_image_ok_off(const struct flash_area *fap)
diff --git a/boot/bootutil/src/bootutil_public.c b/boot/bootutil/src/bootutil_public.c
index f045fae..b1b4f60 100644
--- a/boot/bootutil/src/bootutil_public.c
+++ b/boot/bootutil/src/bootutil_public.c
@@ -240,13 +240,14 @@
return 0;
}
+#ifndef MCUBOOT_SWAP_USING_STATUS
+
static inline int
boot_read_copy_done(const struct flash_area *fap, uint8_t *copy_done)
{
return boot_read_flag(fap, copy_done, boot_copy_done_off(fap));
}
-#ifndef MCUBOOT_SWAP_USING_STATUS
int
boot_read_swap_state(const struct flash_area *fap,
@@ -429,9 +430,9 @@
int
boot_swap_type_multi(int image_index)
{
- const struct boot_swap_table *table;
- struct boot_swap_state primary_slot;
- struct boot_swap_state secondary_slot;
+ const struct boot_swap_table *table = NULL;
+ struct boot_swap_state primary_slot = {0};
+ struct boot_swap_state secondary_slot = {0};
int rc;
size_t i;
diff --git a/boot/bootutil/src/image_ec256.c b/boot/bootutil/src/image_ec256.c
index 9f0ed3d..69cd507 100644
--- a/boot/bootutil/src/image_ec256.c
+++ b/boot/bootutil/src/image_ec256.c
@@ -79,7 +79,7 @@
return -4;
}
- if (mbedtls_ecp_group_load(&ctx->grp, MBEDTLS_ECP_DP_SECP256R1)) {
+ if (mbedtls_ecp_group_load(&ctx->MBEDTLS_CONTEXT_MEMBER(grp), MBEDTLS_ECP_DP_SECP256R1)) {
return -5;
}
@@ -90,11 +90,14 @@
return -7;
}
- if (mbedtls_ecp_point_read_binary(&ctx->grp, &ctx->Q, *p, end - *p)) {
+ if (mbedtls_ecp_point_read_binary(&ctx->MBEDTLS_CONTEXT_MEMBER(grp),
+ &ctx->MBEDTLS_CONTEXT_MEMBER(Q),
+ *p, end - *p) != 0) {
return -8;
}
- if (mbedtls_ecp_check_pubkey(&ctx->grp, &ctx->Q)) {
+ if (mbedtls_ecp_check_pubkey(&ctx->MBEDTLS_CONTEXT_MEMBER(grp),
+ &ctx->MBEDTLS_CONTEXT_MEMBER(Q)) != 0) {
return -9;
}
return 0;
@@ -219,7 +222,7 @@
#else
rc = bootutil_import_key(&pubkey, end);
#endif
- if (rc) {
+ if (rc != 0) {
return -1;
}
@@ -234,9 +237,7 @@
* This is simplified, as the hash length is also 32 bytes.
*/
#ifdef CY_MBEDTLS_HW_ACCELERATION
- while (sig[slen - 1] == '\0') {
- slen--;
- }
+
rc = mbedtls_ecdsa_read_signature(&ctx, hash, hlen, sig, slen);
#else /* CY_MBEDTLS_HW_ACCELERATION */
diff --git a/boot/bootutil/src/swap_scratch.c b/boot/bootutil/src/swap_scratch.c
index fea6ce1..0097611 100644
--- a/boot/bootutil/src/swap_scratch.c
+++ b/boot/bootutil/src/swap_scratch.c
@@ -435,11 +435,11 @@
int
swap_status_source(struct boot_loader_state *state)
{
- const struct boot_status_table *table;
+ const struct boot_status_table *table = NULL;
#if MCUBOOT_SWAP_USING_SCRATCH
- struct boot_swap_state state_scratch;
+ struct boot_swap_state state_scratch = {0};
#endif
- struct boot_swap_state state_primary_slot;
+ struct boot_swap_state state_primary_slot = {0};
int rc;
size_t i;
uint8_t source;
diff --git a/boot/bootutil/src/swap_status_misc.c b/boot/bootutil/src/swap_status_misc.c
index 8512b02..c3f4017 100644
--- a/boot/bootutil/src/swap_status_misc.c
+++ b/boot/bootutil/src/swap_status_misc.c
@@ -242,6 +242,7 @@
const struct flash_area *fap = NULL;
uint32_t off;
uint8_t area_id;
+ uint8_t tmp_state;
int rc;
(void)state;
@@ -272,7 +273,7 @@
}
off = boot_status_off(fap) + boot_status_internal_off(bs, 1);
- uint8_t tmp_state = bs->state;
+ tmp_state = bs->state;
rc = swap_status_update(fap->fa_id, off, &tmp_state, 1);
if (rc != 0) {
@@ -591,7 +592,7 @@
const struct flash_area *fap,
const struct boot_status *bs)
{
- struct boot_swap_state swap_state;
+ struct boot_swap_state swap_state = {0};
uint8_t image_index;
int rc;
diff --git a/boot/cypress/.gitignore b/boot/cypress/.gitignore
index e8f03b4..5c96f68 100644
--- a/boot/cypress/.gitignore
+++ b/boot/cypress/.gitignore
@@ -29,7 +29,7 @@
# Pre_build autogenerated files
MCUBootApp/flashmap.mk
BlinkyApp/flashmap.mk
-cy_flash_pal/cy_flash_map.h
+platforms/cy_flash_pal/cy_flash_map.h
# Build dirs
*out/*/*
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.md b/boot/cypress/BlinkyApp/BlinkyApp.md
index f3f20da..4586a2c 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.md
+++ b/boot/cypress/BlinkyApp/BlinkyApp.md
@@ -1,18 +1,18 @@
-## Blinking LED test application for MCUBootApp bootloading application
+## Blinking LED test application for MCUBootApp bootloader application
### Description
-Implements a simple Blinky LED application to demonstrate the MCUBootApp bootloading application operation for the boot and upgrade processes.
+Implements a simple Blinky LED application to demonstrate the MCUBootApp bootloader application operation for the boot and upgrade processes.
It is validated and started by MCUBootApp, which is running on the CM0p core of PSoC™ 6 devices, or CM33 core for the CYW20829 device.
Functionality:
* Blinks red LED with 2 different rates, depending on the image type - BOOT or UPGRADE.
-* Prints debug info and the appplication version to the terminal at baud rate 115200.
+* Prints debug info and the application version to the terminal at baud rate 115200.
* Manages the watchdog-timer start in MCUBootApp as one of the confirmation mechanisms.
* Sets a special bit in flash to confirm that the image is operable (UPGRADE image).
-* Can be built for boot slot or UPGRADE slot of the bootloader.
+* Can be built for BOOT slot or UPGRADE slot of the bootloader.
* Can be used to evaluate `swap` and `overwrite only` upgrade modes.
### Hardware limitations
@@ -28,17 +28,17 @@
`FLASH_MAP` `make` parameter is used to provide an input file for pre-build action. Refer to `MCUBootApp.md` for details.
-The result of pre-build script is auto-generated `flashmap.mk` file with a set of makefile flags:
+The result of the pre-build script is an auto-generated `flashmap.mk` file with a set of makefile flags:
-`PRIMARY_IMG_START` - start address of primary image in flash, this value is defined in the JSON flash map as the `"value"` field of the address section for `"application_#"`.
+`PRIMARY_IMG_START` - start address of the primary image in flash, this value is defined in the JSON flash map as the `"value"` field of the address section for `"application_#"`.
-`SECONDARY_IMG_START`- start address of secondary image in flash, this value is defined in the JSON flash map as the `"upgrade_address"` field of the `"address"` section for `"application_#"`.
+`SECONDARY_IMG_START`- start address of the secondary image in flash, this value is defined in the JSON flash map as the `"upgrade_address"` field of the `"address"` section for `"application_#"`.
`SLOT_SIZE` - slot size for the primary and the secondary images, this value is taken from `"value"` field of `"size"` section of `"application_#"` from JSON file.
-`BOOTLOADER_SIZE` - size of Bootloader application, this value is defined in the JSON flash map as the `"size"` field of the address section for `"bootloader"`.
+`BOOTLOADER_SIZE` - size of the Bootloader application, this value is defined in the JSON flash map as the `"size"` field of the address section for `"bootloader"`.
-`USE_EXTERNAL_FLASH` - is set to 1 if flash map with `_smif` suffix is chosen.
+`USE_EXTERNAL_FLASH` - is set to 1 if a flash map with the `_smif` suffix is chosen.
`USE_XIP` - is set to 1 if the "external_flash" section with "mode": "XIP" is present in the flash map file.
@@ -47,7 +47,7 @@
`SLOT_SIZE ?= 0x40200` - for slot located in external flash of PsoC™ 6 kits
`SLOT_SIZE ?= 0x20000` - for slot located in external flash of CYW20829 kits
-The pre-build action also calls the GCC preprocessor, which replaces the defines to particular values in `BlinkyApp_template.ld`.
+During pre-build action, the GCC preprocessor is used to generate the target linker script from a template `BlinkyApp_template.ld`.
**Important (PSoC™ 6)**: ensure that the RAM areas of CM4-based BlinkyApp and CM0p-based MCUBootApp bootloader do not overlap.
@@ -55,60 +55,78 @@
### Building an application
+Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE 3.0**:
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/$(USERNAME)/ModusToolbox/tools_3.0/gcc
+
The supported platforms:
* PSOC_062_2M
* PSOC_062_1M
* PSOC_062_512K
+* PSOC_063_1M
* CYW20829
-The root directory for build is **boot/cypress.**
+The root directory is boot/cypress.
+Since BlinkyApp built for BOOT or UPGRADE slot has its own folder BlinkyApp/out/boot or BlinkyApp/out/upgrade consider using following jobs to clear build folder before build.
-**Single-image**
-
-The following command will build BlinkyApp as a regular HEX file for the primary (BOOT) slot to be used in single image case with `swap` upgrade type of Bootloader:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json IMG_ID=1
-
-To build an image for the secondary (UPGRADE) slot to be used in single image case with `swap` upgrade type of Bootloader:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json IMG_ID=1
-
-To build an image for the secondary (UPGRADE) slot to be used in single image case with `overwrite` upgrade type of Bootloader:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single.json IMG_ID=1
-
-**Multi-image**
-
-`BlinkyApp` can be built in multi-image bootloader configuration for PSoC™ 6 chips only.
-
-To obtain the appropriate hex files to use with multi-image MCUBootApp, makefile flag `IMG_ID` is used.
-
-`IMG_ID` flag value should correspond to `application_#` number of JSON file used for build. For example to build `BlinkyApp` for UPGRADE slot of second image following command is used:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single.json IMG_ID=2
-
-When this option is omitted, `IMG_ID=1` is assumed.
+The root directory for is **boot/cypress.**
+Since BlinkyApp built for BOOT or UPGRADE slot has its own folder `BlinkyApp/out/boot` or `BlinkyApp/out/upgrade` consider using following jobs to clear build folder before build:
+ - **clean_boot** - to clean the BOOT image directory
+ - **clean_upgrade** - to clean the UPGRADE image directory.
+
+These jobs also remove auto-generated files 'flashmap.mk' and 'cy_flash_map.h', which is required to eliminate possible errors.
**Upgrade mode dependency**
-`MCUBootApp` can upgrade an image either by overwriting the image from a secondary slot to a primary slot or by swapping the two images.
+`MCUBootApp` can upgrade an image either by overwriting the image from a secondary slot to a primary slot or by swapping the two images.
+To build `BlinkyApp` for different upgrade modes choose flash map JSON file with the corresponding suffix - either `_swap_` or `_overwrite_`.
+But hold in the mind, that `MCUBootApp` and `BlinkyApp` should use the same flash map file!
+For example: to building `MCUBootApp` and `BlinkyApp` in the 'single overwride' mode use the flash map file:
+`FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json`
-To build `BlinkyApp` for different upgrade mode choose flash map JSON file with the corresponding suffix - either _swap_ or _overwrite_.
+**Single-image**
+
+The following command will build BlinkyApp as a regular HEX file for the primary (BOOT) slot to be used in a single image case with `swap` upgrade type of Bootloader:
+
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json IMG_ID=1
+
+To build an image for the secondary (UPGRADE) slot to be used in a single image case with `swap` upgrade type of Bootloader:
+
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json IMG_ID=1
+
+To build an image for the secondary (UPGRADE) slot to be used in a single image case with `overwrite` upgrade type of Bootloader:
+
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json IMG_ID=1
+
+**Multi-image**
+
+**NOTE!** `MCUBootApp` should be build with multi-image support as well. Refer to the appropriated section of [MCUBootApp.md](../MCUBootApp/MCUBootApp.md).
+
+`BlinkyApp` can be built in multi-image bootloader configuration for PSoC™ 6 chips only.
+
+To obtain the appropriate hex files to use with multi-image MCUBootApp, the makefile flag `IMG_ID` is used.
+
+`IMG_ID` flag value should correspond to the `application_#` number of JSON flash map file used for the build. For example, to build `BlinkyApp` for the UPGRADE slot of the second image following command is used:
+
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json IMG_ID=2
+
+When this option is omitted, `IMG_ID=1` is assumed.
**Upgrade image for external memory (PSoC™ 6)**
+__NOTE__: Not supported with `PSoC™ 063` kits.
To prepare MCUBootApp for work with external memory, refer to [ExternalMemory.md](../MCUBootApp/ExternalMemory.md).
-To build a `BlinkyApp` upgrade image for external memory to be used in single image configuration with overwrite upgrade mode, use command:
+To build a `BlinkyApp` upgrade image for external memory to be used in a single image configuration with overwrite upgrade mode, use the command:
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single_smif.json IMG_ID=1
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single_smif.json IMG_ID=1
`ERASED_VALUE` defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S. For `CYW20289` default value is `0xff` since it only uses an external flash.
-In multi-image configuration, an upgrade image for the second application is built using command:
+In the multi-image configuration, an upgrade image for the second application is built using the command:
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi_smif.json IMG_ID=2
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi_smif.json IMG_ID=2
**Encrypted upgrade image**
@@ -116,11 +134,11 @@
To obtain an encrypted upgrade image of BlinkyApp, pass extra flag `ENC_IMG=1` in the command line, for example:
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single_smif.json IMG_ID=1 ENC_IMG=1
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json IMG_ID=1 ENC_IMG=1
-This also suggests that the user has already placed a corresponding *.pem key in the \keys folder. The key variables are defined in root Makefile as SIGN_KEY_FILE and ENC_KEY_FILE
+This also suggests that the user has already placed a corresponding *.pem key in the \keys folder. The key variables are defined in the root Makefile as SIGN_KEY_FILE and ENC_KEY_FILE
-Refer to [CYW20829.md](../platforms/CYW20829/CYW20829.md) for details of encrypted image build for the CYW20289 platfrom.
+Refer to [CYW20829.md](../platforms/CYW20829.md) for details of encrypted image build for the CYW20289 platfrom.
### Complete build flags description
- `BUILDCFG` - The configuration type
@@ -137,16 +155,16 @@
- `SLOT_SIZE` - The size of the primary/secondary slot of MCUBootApp. This app will be used with
- 0x%VALUE%
- `IMG_TYPE` - The slot of MCUBootApp, for which the image is being built.
- - `BOOT` (default) - A build image for the primary (BOOT) slot.
- - `UPGRADE` - A build image for the secondary (UPGRADE) slot.
+ - `BOOT (default)` - to build an image for the primary (BOOT) slot.
+ - `UPGRADE` - to build an image for the secondary (UPGRADE) slot.
- `ERASED_VALUE` - Define memory cell contents in the erased state.
- `0x0` - Internal memory.
- `0xff` - External memory.
-- `TOOLCHAIN_PATH` - The path to the GCC compiler to use for build.
+- `TOOLCHAIN_PATH` - The path to the GCC compiler to use for the build.
- Example: TOOLCHAIN_PATH=/home/user/ModusToolbox/tools_2.4/gcc
- Example: TOOLCHAIN_PATH=C:/ModusToolbox/tools_2.4/gcc
-Flags set by pre-build action.
+Flags are set by pre-build action. Result of pre-build can be found in autogenerated file `BlinkyApp/flashmap.mk`.
- `USE_OVERWRITE` - Define the Upgrade mode type of `MCUBootApp` to use with this app.
- `1` - For Overwrite mode.
@@ -168,7 +186,7 @@
### How to program an application
-BlinkyApp firmware can be programmed in different ways. The following instructions assume the usage of one of Cypress development kits, for example `CY8CPROTO_062_4343W`.
+BlinkyApp firmware can be programmed in different ways. The following instructions assume the usage of one of Cypress development kits, for example, `CY8CPROTO_062_4343W`.
1. Direct usage of OpenOCD.
@@ -176,13 +194,13 @@
The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in the ModusToolbox™ installation folder `ModusToolbox/tools_2.4/openocd`.
-Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION.hex` and `OPENOCD` paths:
+Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION.hex` and `OPENOCD_PATH` paths:
- export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
+ export OPENOCD_PATH=/Applications/ModusToolbox/tools_2.4/openocd
- ${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
- -f ${OPENOCD}/scripts/interface/kitprog3.cfg \
- -f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
+ ${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
+ -f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
+ -f ${OPENOCD_PATH}/scripts/target/psoc6_2m.cfg \
-c "init; reset init; program PATH_TO_APPLICATION.hex" \
-c "resume; reset; exit"
@@ -240,8 +258,8 @@
[BlinkyApp] UART initialized
[BlinkyApp] Retarget I/O set to 115200 baudrate
[BlinkyApp] Red led blinks with 1 sec period
- [BlinkyApp] Update watchdog timer started in MCUBootApp to mark sucessful start of user app
- [BlinkyApp] Turn off watchdog timer
+ [BlinkyApp] Update watchdog timer started in MCUBootApp to mark the successful start of the user app
+ [BlinkyApp] Turn off the watchdog timer
When the user application is programmed in the upgrade slot and the upgrade procedure was successful:
@@ -252,7 +270,7 @@
[BlinkyApp] UART initialized
[BlinkyApp] Retarget I/O set to 115200 baudrate
[BlinkyApp] Red led blinks with 0.25 sec period
- [BlinkyApp] Update watchdog timer started in MCUBootApp to mark sucessful start of user app
- [BlinkyApp] Turn off watchdog timer
- [BlinkyApp] Try to set img_ok to confirm upgrade image
+ [BlinkyApp] Update watchdog timer started in MCUBootApp to mark the successful start of the user app
+ [BlinkyApp] Turn off the watchdog timer
+ [BlinkyApp] Try to set img_ok to confirm the upgrade image
[BlinkyApp] SWAP Status : Image OK was set at 0x10027fe8.
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.mk b/boot/cypress/BlinkyApp/BlinkyApp.mk
index d06cd99..18cbfcf 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.mk
+++ b/boot/cypress/BlinkyApp/BlinkyApp.mk
@@ -41,21 +41,24 @@
ifneq ($(FLASH_MAP), )
$(CUR_APP_PATH)/flashmap.mk:
- $(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/cy_flash_pal/cy_flash_map.h -d $(IMG_ID) > $(CUR_APP_PATH)/flashmap.mk
+ $(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/cy_flash_pal/cy_flash_map.h -d $(IMG_ID) > $(CUR_APP_PATH)/flashmap.mk
include $(CUR_APP_PATH)/flashmap.mk
DEFINES_APP := -DCY_FLASH_MAP_JSON
endif
# TODO: optimize here and in MCUBootApp.mk
# Output folder
-OUT := $(APP_NAME)/out
+ifeq ($(IMG_ID), 1)
+ OUT := $(APP_NAME)/out
+else
+ OUT := $(APP_NAME)/out.id$(IMG_ID)
+endif
+
# Output folder to contain build artifacts
OUT_TARGET := $(OUT)/$(PLATFORM)
OUT_CFG := $(OUT_TARGET)/$(BUILDCFG)
-BOOTLOADER_SIZE ?= $(PLATFORM_BOOTLOADER_SIZE)
-
# Set build directory for BOOT and UPGRADE images
ifeq ($(IMG_TYPE), UPGRADE)
OUT_CFG := $(OUT_CFG)/upgrade
@@ -112,18 +115,48 @@
DEFINES_APP += -DUSER_APP_START=$(USER_APP_START)
DEFINES_APP += -DPRIMARY_IMG_START=$(PRIMARY_IMG_START)
DEFINES_APP += -DUSER_APP_SIZE=$(SLOT_SIZE)
+DEFINES_APP += -DAPP_$(APP_CORE)
DEFINES_APP += $(PLATFORM_DEFINES_APP)
+#Use default led if no command line parameter added
+ifeq ($(LED_PORT), )
+DEFINES_APP += -DLED_PORT=$(LED_PORT_DEFAULT)
+else
+DEFINES_APP += -DLED_PORT=GPIO_PRT$(LED_PORT)
+endif
+
+ifeq ($(LED_PIN), )
+DEFINES_APP += -DLED_PIN=$(LED_PIN_DEFAULT)
+else
+DEFINES_APP += -DLED_PIN=$(LED_PIN)
+endif
+
+#Use default UART if no command line parameter added
+ifeq ($(UART_TX), )
+DEFINES_APP += -DCY_DEBUG_UART_TX=$(UART_TX_DEFAULT)
+else
+DEFINES_APP += -DCY_DEBUG_UART_TX=$(UART_TX)
+endif
+
+ifeq ($(UART_RX), )
+DEFINES_APP += -DCY_DEBUG_UART_RX=$(UART_RX_DEFAULT)
+else
+DEFINES_APP += -DCY_DEBUG_UART_RX=$(UART_RX)
+endif
+
ifeq ($(USE_XIP), 1)
DEFINES_APP += -DUSE_XIP
+DEFINES_APP += -DCY_BOOT_USE_EXTERNAL_FLASH
LD_SUFFIX = _xip
endif
# Add version metadata to image
ifneq ($(IMG_VER), )
IMG_VER_ARG = -v "$(IMG_VER)"
+DEFINES_APP += -DIMG_VER_MSG=\"$(IMG_VER)\"
else
-IMG_VER_ARG = $(PLATFORM_DEFAULT_IMG_VER_ARG)
+IMG_VER_ARG = -v "$(PLATFORM_DEFAULT_IMG_VER_ARG)"
+DEFINES_APP += -DIMG_VER_MSG=\"$(PLATFORM_DEFAULT_IMG_VER_ARG)\"
$(info WARNING - setting platform default version number, to set custom value - pass IMG_VER=x.x.x argument to make command)
endif
@@ -137,13 +170,6 @@
# Collect Test Application sources
SOURCES_APP_SRC := $(wildcard $(CUR_APP_PATH)/*.c)
-# Include confirmation flag setting (img_ok) implementation
-ifeq ($(IMG_TYPE), UPGRADE)
-ifeq ($(USE_OVERWRITE), 0)
-SOURCES_APP_SRC += $(PRJ_DIR)/platforms/$(FAMILY)/img_confirm/set_img_ok.c
-endif
-endif
-
# Set offset for secondary image
ifeq ($(IMG_TYPE), UPGRADE)
HEADER_OFFSET := $(SECONDARY_IMG_START)
@@ -168,6 +194,14 @@
INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/../bootutil/include/bootutil)
# +++
+# Include confirmation flag setting (img_ok) implementation
+ifeq ($(IMG_TYPE), UPGRADE)
+ifeq ($(USE_OVERWRITE), 0)
+SOURCES_APP_SRC += $(PRJ_DIR)/platforms/img_confirm/$(FAMILY)/set_img_ok.c
+INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/platforms/img_confirm)
+endif
+endif
+
# Overwite path to linker script if custom is required, otherwise default from BSP is used
ifeq ($(COMPILER), GCC_ARM)
LINKER_SCRIPT := $(CUR_APP_PATH)/linker/$(APP_NAME).ld
@@ -183,6 +217,17 @@
UPGRADE_TYPE := --overwrite-only
endif
+ifeq ($(BOOT_RECORD_SW_TYPE), )
+ ifeq ($(IMG_TYPE), BOOT)
+ BOOT_RECORD_IMG_TYPE_STR = B_Blinky$(IMG_ID)
+ else
+ BOOT_RECORD_IMG_TYPE_STR = U_Blinky$(IMG_ID)
+ endif
+ BOOT_RECORD := --boot-record $(BOOT_RECORD_IMG_TYPE_STR)
+else
+ BOOT_RECORD := --boot-record $(BOOT_RECORD_SW_TYPE)
+endif
+
SIGN_ARGS := $(PLATFORM_SIGN_ARGS) $(IMG_VER_ARG) $(IMG_DEPS_ARG)
# Set parameters needed for signing
@@ -204,51 +249,68 @@
# Print debug information about all settings used and/or set in this file
ifeq ($(VERBOSE), 1)
$(info #### BlinkyApp.mk ####)
+$(info APP_CORE <-- $(APP_CORE))
$(info APP_NAME <-- $(APP_NAME))
-$(info ASM_FILES_APP <-> $(ASM_FILES_APP))
+$(info ASM_FILES_APP --> $(ASM_FILES_APP))
$(info ASM_FILES_STARTUP <-- $(ASM_FILES_STARTUP))
+$(info BOOT_RECORD --> $(BOOT_RECORD))
+$(info BOOT_RECORD_IMG_TYPE_STR <-- $(BOOT_RECORD_IMG_TYPE_STR))
+$(info BOOT_RECORD_SW_TYPE <-- $(BOOT_RECORD_SW_TYPE))
$(info BUILDCFG <-- $(BUILDCFG))
-$(info CC <-- $(CC))
-$(info CFLAGS <-- $(CFLAGS))
$(info COMPILER <-> $(COMPILER))
$(info CONFIRM <-- $(CONFIRM))
-$(info CORE <-- $(CORE))
$(info CURDIR <-- $(CURDIR))
$(info CUR_APP_PATH <-- $(CUR_APP_PATH))
-$(info DEFINES_APP <-> $(DEFINES_APP))
+$(info DEFINES_APP --> $(DEFINES_APP))
$(info ENC_IMG --> $(ENC_IMG))
$(info ERASED_VALUE <-> $(ERASED_VALUE))
+$(info FAMILY <-- $(FAMILY))
+$(info FLASH_MAP <-- $(FLASH_MAP))
+$(info HEADER_OFFSET --> $(HEADER_OFFSET))
+$(info IMG_DEPS_ARG <-- $(IMG_DEPS_ARG))
+$(info IMG_DEPS_ID <-- $(IMG_DEPS_ID))
+$(info IMG_DEPS_VER <-- $(IMG_DEPS_VER))
+$(info IMG_ID <-> $(IMG_ID))
$(info IMG_TYPE <-> $(IMG_TYPE))
-$(info INCLUDE_DIRS <-- $(INCLUDE_DIRS))
-$(info INCLUDE_DIRS_APP <-> $(INCLUDE_DIRS_APP))
-$(info LINKER_SCRIPT <-> $(LINKER_SCRIPT))
+$(info IMG_VER <-- $(IMG_VER))
+$(info IMG_VER_ARG <-- $(IMG_VER_ARG))
+$(info INCLUDE_DIRS_APP --> $(INCLUDE_DIRS_APP))
+$(info LED_PIN <-- $(LED_PIN))
+$(info LED_PIN_DEFAULT <-- $(LED_PIN_DEFAULT))
+$(info LED_PORT <-- $(LED_PORT))
+$(info LED_PORT_DEFAULT <-- $(LED_PORT_DEFAULT))
+$(info LINKER_SCRIPT --> $(LINKER_SCRIPT))
$(info OUT <-> $(OUT))
$(info OUT_CFG <-> $(OUT_CFG))
$(info OUT_TARGET <-> $(OUT_TARGET))
$(info PLATFORM <-- $(PLATFORM))
$(info PLATFORM_DEFAULT_ERASED_VALUE <-- $(PLATFORM_DEFAULT_ERASED_VALUE))
+$(info PLATFORM_DEFAULT_IMG_VER_ARG <-- $(PLATFORM_DEFAULT_IMG_VER_ARG))
$(info PLATFORM_DEFAULT_RAM_SIZE <-- $(PLATFORM_DEFAULT_RAM_SIZE))
$(info PLATFORM_DEFAULT_RAM_START <-- $(PLATFORM_DEFAULT_RAM_START))
-$(info PLATFORM_DEFAULT_SLOT_SIZE <-- $(PLATFORM_DEFAULT_SLOT_SIZE))
-$(info PLATFORM_DEFAULT_USER_APP_START <-- $(PLATFORM_DEFAULT_USER_APP_START))
-$(info PLATFORM_DEFAULT_PRIMARY_IMG_START <-- $(PLATFORM_DEFAULT_PRIMARY_IMG_START))
$(info PLATFORM_DEFAULT_USE_OVERWRITE <-- $(PLATFORM_DEFAULT_USE_OVERWRITE))
$(info PLATFORM_DEFINES_APP <-- $(PLATFORM_DEFINES_APP))
$(info PLATFORM_INCLUDE_DIRS_FLASH <-- $(PLATFORM_INCLUDE_DIRS_FLASH))
$(info PLATFORM_SIGN_ARGS <-- $(PLATFORM_SIGN_ARGS))
$(info PLATFORM_SOURCES_FLASH <-- $(PLATFORM_SOURCES_FLASH))
+$(info PLATFORM_USER_APP_START <-- $(PLATFORM_USER_APP_START))
+$(info PRIMARY_IMG_START <-- $(PRIMARY_IMG_START))
$(info PRJ_DIR <-- $(PRJ_DIR))
-$(info IMG_VER_ARG <-- $(IMG_VER_ARG))
-$(info IMG_DEPS_ARG <-- $(IMG_DEPS_ARG))
+$(info PYTHON_PATH <-- $(PYTHON_PATH))
+$(info SECONDARY_IMG_START <-- $(SECONDARY_IMG_START))
$(info SIGN_ARGS <-> $(SIGN_ARGS))
-$(info SLOT_SIZE <-> $(SLOT_SIZE))
-$(info SOURCES_APP <-> $(SOURCES_APP))
+$(info SLOT_SIZE <-- $(SLOT_SIZE))
+$(info SOURCES_APP --> $(SOURCES_APP))
$(info SOURCES_APP_SRC <-> $(SOURCES_APP_SRC))
+$(info UART_RX <-- $(UART_RX))
+$(info UART_RX_DEFAULT <-- $(UART_RX_DEFAULT))
+$(info UART_TX <-- $(UART_TX))
+$(info UART_TX_DEFAULT <-- $(UART_TX_DEFAULT))
$(info UPGRADE_SUFFIX --> $(UPGRADE_SUFFIX))
$(info UPGRADE_TYPE --> $(UPGRADE_TYPE))
$(info USER_APP_RAM_SIZE <-> $(USER_APP_RAM_SIZE))
$(info USER_APP_RAM_START <-> $(USER_APP_RAM_START))
$(info USER_APP_START <-> $(USER_APP_START))
-$(info PRIMARY_IMG_START <-> $(PRIMARY_IMG_START))
$(info USE_OVERWRITE <-> $(USE_OVERWRITE))
+$(info USE_XIP <-- $(USE_XIP))
endif
diff --git a/boot/cypress/BlinkyApp/libs.mk b/boot/cypress/BlinkyApp/libs.mk
index 08fc130..ff8637b 100644
--- a/boot/cypress/BlinkyApp/libs.mk
+++ b/boot/cypress/BlinkyApp/libs.mk
@@ -32,23 +32,36 @@
# Collect source files for Retarget-io
ifneq ($(PLATFORM), CYW20829)
+ifeq ($(APP_CORE), CM0P)
+SOURCES_RETARGET_IO := $(wildcard $(THIS_APP_PATH)/retarget_io_pdl/*.c)
+endif
+ifneq ($(APP_CORE), CM0P)
SOURCES_RETARGET_IO := $(wildcard $(CUR_LIBS_PATH)/retarget-io/*.c)
endif
+endif
SOURCES_WATCHDOG := $(wildcard $(CUR_LIBS_PATH)/watchdog/*.c)
# Collect source files for HAL
ifneq ($(PLATFORM), CYW20829)
+ifneq ($(APP_CORE), CM0P)
SOURCES_HAL_BLINKY := $(wildcard $(CUR_LIBS_PATH)/mtb-hal-cat1/source/*.c)
SOURCES_HAL_BLINKY += $(wildcard $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/*.c)
SOURCES_HAL_BLINKY += $(wildcard $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/*.c)
endif
+endif
# Retarget-io related include directories
+ifeq ($(APP_CORE), CM0P)
+INCLUDE_DIRS_RETARGET_IO := $(THIS_APP_PATH)/retarget_io_pdl
+endif
+ifneq ($(APP_CORE), CM0P)
INCLUDE_DIRS_RETARGET_IO := $(CUR_LIBS_PATH)/retarget-io
+endif
INCLUDE_DIRS_WATCHDOG := $(CUR_LIBS_PATH)/watchdog
# Collect dirrectories containing headers for PSOC6 HAL
ifneq ($(PLATFORM), CYW20829)
+ifneq ($(APP_CORE), CM0P)
INCLUDE_DIRS_HAL_BLINKY := $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A
INCLUDE_DIRS_HAL_BLINKY := $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include
INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/include
@@ -56,6 +69,7 @@
INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages
INCLUDE_DIRS_HAL_BLINKY += $(CUR_LIBS_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/triggers
endif
+endif
# Collected source files for libraries
SOURCES_LIBS += $(SOURCES_WATCHDOG)
@@ -75,6 +89,7 @@
# Print debug information about all settings used and/or set in this file
ifeq ($(VERBOSE), 1)
$(info #### libs.mk ####)
+$(info APP_CORE <-- $(APP_CORE))
$(info CUR_LIBS_PATH <-- $(CUR_LIBS_PATH))
$(info INCLUDE_DIRS_HAL_BLINKY <-> $(INCLUDE_DIRS_HAL_BLINKY))
$(info INCLUDE_DIRS_LIBS --> $(INCLUDE_DIRS_LIBS))
@@ -86,4 +101,5 @@
$(info SOURCES_LIBS --> $(SOURCES_LIBS))
$(info SOURCES_RETARGET_IO <-> $(SOURCES_RETARGET_IO))
$(info SOURCES_WATCHDOG <-> $(SOURCES_WATCHDOG))
+$(info THIS_APP_PATH <-- $(THIS_APP_PATH))
endif
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template.ld
new file mode 100644
index 0000000..b7044a7
--- /dev/null
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template.ld
@@ -0,0 +1,347 @@
+/***************************************************************************//**
+* \file cy8c6xxa_cm0plus.ld
+* \version 2.91
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x100E0000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#include <main.h>
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM0+ SRAM */
+STACK_SIZE = 0x1000;
+
+/* The size of the MCU boot header area at the start of FLASH */
+BOOT_HEADER_SIZE = 0x400;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+ */
+ ram (rwx) : ORIGIN = USER_APP_RAM_START, LENGTH = USER_APP_RAM_SIZE
+ flash (rx) : ORIGIN = USER_APP_START, LENGTH = USER_APP_SIZE
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ /* Cortex-M0+ application flash area */
+ .text ORIGIN(flash) + BOOT_HEADER_SIZE :
+ {
+ /* Cortex-M0+ flash vector table */
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ :
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram AT>flash
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ __HeapLimit = .;
+ } > ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Used for the digital signature of the secure application and the Bootloader SDK application.
+ * The size of the section depends on the required data size. */
+ .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+ {
+ KEEP(*(.cy_app_signature))
+ } > flash
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ cy_xip :
+ {
+ __cy_xip_start = .;
+ KEEP(*(.cy_xip))
+ __cy_xip_end = .;
+ } > xip
+
+
+}
+
+
+/* EOF */
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld
new file mode 100644
index 0000000..3a2a33c
--- /dev/null
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld
@@ -0,0 +1,368 @@
+/***************************************************************************//**
+* \file cy8c6xxa_cm0plus.ld
+* \version 2.91
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x100E0000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#include <main.h>
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM0+ SRAM */
+STACK_SIZE = 0x1000;
+
+/* The size of the MCU boot header area at the start of FLASH */
+BOOT_HEADER_SIZE = 0x400;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
+ */
+ ram (rwx) : ORIGIN = USER_APP_RAM_START, LENGTH = USER_APP_RAM_SIZE
+ flash (rx) : ORIGIN = USER_APP_START, LENGTH = USER_APP_SIZE
+
+ public_ram (rw) : ORIGIN = 0x08000000, LENGTH = 0x800
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+
+ /* Cortex-M0+ application flash area */
+ .text ORIGIN(flash) + BOOT_HEADER_SIZE :
+ {
+ /* Cortex-M0+ flash vector table */
+ . = ALIGN(4);
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+ . = ALIGN(4);
+
+ EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o
+ *cy_sysclk.o *cy_smif_hybrid_sect.o *flash_qspi.o
+ *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm0plus.o) *(.text)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm0plus.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ :
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ *cy_smif.o(.text*)
+ *cy_smif_memslot.o(.text*)
+ *cy_smif_sfdp.o(.text*)
+ *cy_sysclk.o(.text*)
+ *cy_smif_hybrid_sect.o(.text*)
+ *flash_qspi.o(.text*)
+ *cy_syslib.o(.text*)
+ *cy_syslib_ext.o(.text*)
+
+ __data_end__ = .;
+
+ } > ram AT>flash
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ __HeapLimit = .;
+ } > ram
+
+ .cy_sharedmem (NOLOAD):
+ {
+ . = ALIGN(4);
+ __public_ram_start__ = .;
+ KEEP(*(.cy_sharedmem))
+ . = ALIGN(4);
+ __public_ram_end__ = .;
+ } > public_ram
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Used for the digital signature of the secure application and the Bootloader SDK application.
+ * The size of the section depends on the required data size. */
+ .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+ {
+ KEEP(*(.cy_app_signature))
+ } > flash
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ cy_xip :
+ {
+ __cy_xip_start = .;
+ KEEP(*(.cy_xip))
+ __cy_xip_end = .;
+ } > xip
+
+
+}
+
+
+/* EOF */
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
index 55b307a..3e84aa3 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
@@ -132,7 +132,7 @@
EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o
*cy_sysclk.o *cy_smif_hybrid_sect.o *flash_qspi.o
- *cy_syslib.o *cy_syslib_gcc.o *system_psoc6_cm4.o) *(.text)
+ *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm4.o) *(.text)
KEEP(*(.init))
KEEP(*(.fini))
@@ -258,7 +258,7 @@
*cy_smif_hybrid_sect.o(.text*)
*flash_qspi.o(.text*)
*cy_syslib.o(.text*)
- *cy_syslib_gcc.o(.text*)
+ *cy_syslib_ext.o(.text*)
__data_end__ = .;
diff --git a/boot/cypress/BlinkyApp/main.c b/boot/cypress/BlinkyApp/main.c
index 59cee6a..900c870 100644
--- a/boot/cypress/BlinkyApp/main.c
+++ b/boot/cypress/BlinkyApp/main.c
@@ -4,7 +4,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*/
- /*
+/*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
@@ -23,147 +23,18 @@
* under the License.
*/
-#ifdef CYW20829
-#include <inttypes.h>
-#include "cybsp.h"
-#include "cycfg_pins.h"
-#include "cyhal_wdt.h"
-#else
-#include "system_psoc6.h"
-#endif /* CYW20829 */
-
-#include "cy_pdl.h"
-#include "cy_retarget_io.h"
-#include "cyhal.h"
-#include "watchdog.h"
-
-#include "flash_qspi.h"
+#include "platform.h"
#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
#include "set_img_ok.h"
#endif
-/* Define pins for UART debug output */
-#ifdef CYW20829
-#define CY_DEBUG_UART_TX (CYBSP_DEBUG_UART_TX)
-#define CY_DEBUG_UART_RX (CYBSP_DEBUG_UART_RX)
-#else
-#define CY_DEBUG_UART_TX (P5_1)
-#define CY_DEBUG_UART_RX (P5_0)
-#endif /* CYW20829 */
-
-#if defined(PSOC_062_2M)
-#define LED_PORT GPIO_PRT13
-#define LED_PIN 7U
-#elif defined(PSOC_062_1M)
-#define LED_PORT GPIO_PRT13
-#define LED_PIN 7U
-#elif defined(PSOC_062_512K)
-#define LED_PORT GPIO_PRT11
-#define LED_PIN 1U
-#elif defined(CYW20829)
-#define LED_PORT GPIO_PRT0
-#define LED_PIN 0U
-#endif
-
-const cy_stc_gpio_pin_config_t LED_config =
-{
- .outVal = 1,
- .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
- .hsiom = HSIOM_SEL_GPIO,
- .intEdge = CY_GPIO_INTR_DISABLE,
- .intMask = 0UL,
- .vtrip = CY_GPIO_VTRIP_CMOS,
- .slewRate = CY_GPIO_SLEW_FAST,
- .driveSel = CY_GPIO_DRIVE_FULL,
- .vregEn = 0UL,
- .ibufMode = 0UL,
- .vtripSel = 0UL,
- .vrefSel = 0UL,
- .vohSel = 0UL,
-};
-
-uint32_t smif_id = 1; /* Assume SlaveSelect_0 is used for External Memory */
-
-#ifdef BOOT_IMAGE
- #define BLINK_PERIOD (1000u)
- #define GREETING_MESSAGE_VER "[BlinkyApp] BlinkyApp v1.0 [CM4]\r\n"
- #define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 1 sec period\r\n"
-#elif defined(UPGRADE_IMAGE)
- #define BLINK_PERIOD (250u)
- #define GREETING_MESSAGE_VER "[BlinkyApp] BlinkyApp v2.0 [+]\r\n"
- #define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 0.25 sec period\r\n"
-#else
- #error "[BlinkyApp] Please specify type of image: -DBOOT_IMAGE or -DUPGRADE_IMAGE\r\n"
-#endif
-
-#define WATCHDOG_FREE_MESSAGE "[BlinkyApp] Turn off watchdog timer\r\n"
-
-static void check_result(int res)
-{
- if (res != CY_RSLT_SUCCESS) {
- CY_ASSERT(0);
- /* Loop forever... */
- for (;;) {}
- }
-}
-
-void test_app_init_hardware(void)
-{
- /* enable interrupts */
- __enable_irq();
-
- /* Disabling watchdog so it will not interrupt normal flow later */
- Cy_GPIO_Pin_Init(LED_PORT, LED_PIN, &LED_config);
-
- /* Initialize retarget-io to use the debug UART port */
- check_result(cy_retarget_io_init(CY_DEBUG_UART_TX, CY_DEBUG_UART_RX,
- CY_RETARGET_IO_BAUDRATE));
-
- printf("\n===========================\r\n");
- printf(GREETING_MESSAGE_VER);
- printf("===========================\r\n");
-
- printf("[BlinkyApp] GPIO initialized \r\n");
- printf("[BlinkyApp] UART initialized \r\n");
- printf("[BlinkyApp] Retarget I/O set to 115200 baudrate \r\n");
-
-#ifdef CYW20829
- cy_en_smif_status_t rc = CY_SMIF_CMD_NOT_FOUND;
-
- rc = qspi_init_sfdp(smif_id);
- if (CY_SMIF_SUCCESS == rc) {
- printf("[BlinkyApp] External Memory initialized w/ SFDP. \r\n");
- }
- else {
- printf("[BlinkyApp] External Memory initialization w/ SFDP FAILED: 0x%" PRIx32 " \r\n", (uint32_t)rc);
- }
-#endif /* CYW20829 */
-}
-
int main(void)
{
- uint32_t blinky_period = BLINK_PERIOD;
-
-#if defined CYW20829
- cybsp_init();
-#endif /* CYW20829 */
-
- test_app_init_hardware();
+ const char* detect_core_message = test_app_init_hardware();
printf(GREETING_MESSAGE_INFO);
- /* Disable watchdog timer to mark successful start up of application.
- * For PSOC6 WDT is disabled in SystemInit() function.
- */
- printf(WATCHDOG_FREE_MESSAGE);
-#ifdef CYW20829
- cyhal_wdt_t *cyw20829_wdt = NULL;
- cyhal_wdt_free(cyw20829_wdt);
-#else
- cy_wdg_free();
-#endif /* CYW20829 */
-
#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
int rc = -1;
@@ -176,20 +47,19 @@
if (IMG_OK_ALREADY_SET == rc) {
printf("[BlinkyApp] Img_ok is already set in trailer\r\n");
- }
- else if (IMG_OK_SET_SUCCESS == rc) {
+ } else if (IMG_OK_SET_SUCCESS == rc) {
printf("[BlinkyApp] SWAP Status : Image OK was set at 0x%08x.\r\n", IMG_OK_ADDR);
- }
- else {
+ } else {
printf("[BlinkyApp] SWAP Status : Failed to set Image OK.\r\n");
}
#endif /* !(SWAP_DISABLED) && defined(UPGRADE_IMAGE) */
- for (;;)
- {
+ printf("[BlinkyApp] Image type: " IMAGE_TYPE " on %s core\r\n", detect_core_message);
+
+ for (;;) {
/* Toggle the user LED periodically */
- Cy_SysLib_Delay(blinky_period/2);
+ Cy_SysLib_Delay(BLINK_PERIOD / 2);
/* Invert the USER LED state */
Cy_GPIO_Inv(LED_PORT, LED_PIN);
diff --git a/boot/cypress/BlinkyApp/platform.h b/boot/cypress/BlinkyApp/platform.h
new file mode 100644
index 0000000..a34650a
--- /dev/null
+++ b/boot/cypress/BlinkyApp/platform.h
@@ -0,0 +1,166 @@
+#ifndef PLATFORM_H
+#define PLATFORM_H
+
+#ifdef CYW20829
+#include <inttypes.h>
+
+#include "cybsp.h"
+#include "cycfg_pins.h"
+#include "cyhal_wdt.h"
+#else
+#include "system_psoc6.h"
+#endif /* CYW20829 */
+
+#include <stdio.h>
+
+#include "cy_pdl.h"
+#ifdef APP_CM0P
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+#include "cy_retarget_io_pdl.h"
+#else
+#include "cyhal.h"
+#include "cy_retarget_io.h"
+
+#endif /* APP_CM0P */
+#include "watchdog.h"
+
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829)
+#include "flash_qspi.h"
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829) */
+
+#ifdef BOOT_IMAGE
+#define IMAGE_TYPE "BOOT"
+#define BLINK_PERIOD (1000u)
+#define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 1 sec period\r\n"
+#elif defined(UPGRADE_IMAGE)
+#define IMAGE_TYPE "UPGRADE"
+#define BLINK_PERIOD (250u)
+#define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 0.25 sec period\r\n"
+#else
+#error "[BlinkyApp] Please specify type of image: -DBOOT_IMAGE or -DUPGRADE_IMAGE\r\n"
+#endif /* BOOT_IMAGE */
+
+#define GREETING_MESSAGE_VER "[BlinkyApp] Version:"
+
+#define WATCHDOG_FREE_MESSAGE "[BlinkyApp] Turn off watchdog timer\r\n"
+
+#define SMIF_ID (1U) /* Assume SlaveSelect_0 is used for External Memory */
+
+static const char* core33_message ="CM33";
+static const char* core0p_message ="CM0P";
+static const char* core4_message ="CM4";
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* defined(__cplusplus) */
+
+static inline const char* test_app_init_hardware(void)
+{
+ const char* detect_core_message = NULL;
+ (void) core33_message;
+ (void) core0p_message;
+ (void) core4_message;
+ cy_rslt_t res = CY_RSLT_TYPE_ERROR;
+
+ const cy_stc_gpio_pin_config_t LED_config = {
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+ .hsiom = HSIOM_SEL_GPIO,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_FULL,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+ };
+
+#ifdef CYW20829
+ cybsp_init();
+#elif defined APP_CM0P
+ init_cycfg_peripherals();
+ init_cycfg_pins();
+#endif /* CYW20829 */
+
+ /* enable interrupts */
+ __enable_irq();
+
+ /* Initialize led port */
+ Cy_GPIO_Pin_Init(LED_PORT, LED_PIN, &LED_config);
+
+ /* Initialize retarget-io to use the debug UART port */
+#ifdef APP_CM0P
+ res = cy_retarget_io_pdl_init(CY_RETARGET_IO_BAUDRATE);
+#else
+ res = cy_retarget_io_init(CY_DEBUG_UART_TX, CY_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);
+#endif /* APP_CM0P */
+
+ if (res != CY_RSLT_SUCCESS) {
+ CY_ASSERT(0);
+ /* Loop forever... */
+ for (;;) {
+ }
+ }
+
+ printf("\n===========================\r\n");
+ printf("%s %s\r\n", GREETING_MESSAGE_VER, IMG_VER_MSG);
+
+#ifdef CYW20829
+ detect_core_message = core33_message;
+
+ printf("===========================\r\n");
+
+ cy_en_smif_status_t rc = CY_SMIF_CMD_NOT_FOUND;
+ cyhal_wdt_t *cyw20829_wdt = NULL;
+
+ rc = qspi_init_sfdp(SMIF_ID);
+ if (CY_SMIF_SUCCESS == rc) {
+ printf("[BlinkyApp] External Memory initialized w/ SFDP. \r\n");
+ } else {
+ printf("[BlinkyApp] External Memory initialization w/ SFDP FAILED: 0x%" PRIx32 " \r\n", (uint32_t)rc);
+ }
+
+ /* Disable watchdog timer to mark successful start up of application. */
+ cyhal_wdt_free(cyw20829_wdt);
+
+#else
+ /* Determine on which core this app is running by polling CPUSS_IDENTITY register.
+ * This register contains bits field [8:11]. This field specifies the bus master
+ * identifier of the transfer that reads the register.
+ */
+#ifdef APP_CM0P
+
+ en_prot_master_t core = _FLD2VAL(CPUSS_IDENTITY_MS, CPUSS->IDENTITY);
+
+ if (CPUSS_MS_ID_CM4 == core) {
+ printf("\n[BlinkyApp] is compiled for CM0P core, started on CM4 instead. Execution Halted.\n");
+ CY_ASSERT(0);
+ }
+ else if (CPUSS_MS_ID_CM0 == core) {
+ detect_core_message = core0p_message;
+ }
+ else
+#endif /* APP_CM0P */
+ {
+ detect_core_message = core4_message;
+ }
+ printf("===========================\r\n");
+ cy_wdg_free();
+#endif /* CYW20829 */
+ printf("[BlinkyApp] GPIO initialized \r\n");
+ printf("[BlinkyApp] UART initialized \r\n");
+ printf("[BlinkyApp] Retarget I/O set to 115200 baudrate \r\n");
+ printf(WATCHDOG_FREE_MESSAGE);
+
+ return(detect_core_message);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* defined(__cplusplus) */
+
+#endif /* PLATFORM_H */
diff --git a/boot/cypress/MCUBootApp/ExternalMemory.md b/boot/cypress/MCUBootApp/ExternalMemory.md
index 70f862d..bfc8162 100644
--- a/boot/cypress/MCUBootApp/ExternalMemory.md
+++ b/boot/cypress/MCUBootApp/ExternalMemory.md
@@ -1,6 +1,6 @@
### Support of secondary slot in external memory for PSoC™ 6 devices
-* For the CYW20829 external memory support, see the [CYW20829.md](../platforms/CYW20829/CYW20829.md) file.
+* For the CYW20829 external memory support, see the [CYW20829.md](../platforms/CYW20829.md) file.
#### Description
@@ -74,19 +74,19 @@
When XIP mode is used primary slot of an image can be placed in external memory.
-This repository provides default flash map files with suffix _xip_ to be used for XIP mode in `cy_flash_pal/flash_%platform_name%/flashmap`.
+This repository provides default flash map files with suffix _xip_ to be used for XIP mode in `platforms/cy_flash_pal/flash_%platform_name%/flashmap`.
#### How to enable external memory support
External memory is enabled when `make` flag `USE_EXTERNAL_FLASH` is set to `1`. Value of this flag is set in auto-generated `flashmap.mk` files when field `"external_flash"` is present in JSON file.
-Default flash maps with suffix _smif_ are provided in `cy_flash_pal/flash_psoc6/flashmap` folder for PSoC™ 6 devices, where presense of external memory in system is optional.
+Default flash maps with suffix _smif_ are provided in `platforms/cy_flash_pal/flash_psoc6/flashmap` folder for PSoC™ 6 devices, where presense of external memory in system is optional.
Build MCUBootApp as described in the [MCUBootApp.md](MCUBootApp.md) file.
**Building an upgrade image for external memory:**
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE ERASED_VALUE=0xff FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single_smif.json IMG_ID=1
+ make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE ERASED_VALUE=0xff FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json IMG_ID=1
`ERASED_VALUE` - Defines the memory cell contents in the erased state. It is `0x00` for PSoC™ 6 internal flash and `0xff` for S25FL512S.
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.md b/boot/cypress/MCUBootApp/MCUBootApp.md
index d15f667..c07cb9e 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.md
+++ b/boot/cypress/MCUBootApp/MCUBootApp.md
@@ -1,14 +1,14 @@
-## MCUBootApp - demo bootloading application to use with Cypress targets
+## MCUBootApp - demo bootloader application to use with Cypress targets
### Solution description
-This solution demonstrates operation of MCUboot on Cypress PSoC™ 6 and CYW20829 devices.
+This solution demonstrates the operation of MCUboot on Cypress PSoC™ 6 and CYW20829 devices.
* Single-/Multi-image operation modes
* Overwrite/Swap upgrade modes
* Interrupted upgrade recovery for swap upgrades
* Upgrade image confirmation
-* Reverting of bad upgrade images
+* Revert bad upgrade images
* Secondary slots located in external flash
This demo supports PSoC™ 6 chips with the 1M-, 2M-, and 512K-flash on board, and the CYW20829 chip with no internal flash.
@@ -17,25 +17,28 @@
* `CY8CKIT-062-WIFI-BT`
* `CY8CPROTO-062S3-4343W`
* `CYW920829M2EVB-01`
+* `CYBLE-416045-EVAL`
+* `CY8CPROTO-063-BLE`
+* `CY8CKIT-062-BLE`
### Platfrom specifics
-MCUBootApp can be built for different platforms. So, the main application makefile `MCUBootApp.mk` operates with common build variables and flags. Most of them can be passed to build system as a `make` command parameter and each platform defines the default value prefixed with `PLATFORM_` in the corresponding makefile - `PSOC6.mk` or `CYW20829.mk`. The build flags and variables are described in detail in the following paragraphs.
+MCUBootApp can be built for different platforms. So, the main application makefile `MCUBootApp.mk` operates with common build variables and flags. Most of them can be passed to the build system as a `make` command parameter and each platform defines the default value prefixed with `PLATFORM_` in the corresponding makefile - `PSOC6.mk` or `CYW20829.mk`. The build flags and variables are described in detail in the following paragraphs.
### Memory maps
-The MCUboot terminology names a slot from which **boot** occurs as **primary** and a slot where an **upgrade** image is placed as **secondary**. Some platforms support both internal and external flash, some only external flash.
+The MCUboot terminology names a slot from which **boot** occurs as **primary** and a slot where an **upgrade** image is placed as **secondary**. Some platforms support both internal and external flash and some only external flash.
-The flash map of bootloader is defined at compile time and cannot be changed dynamically. Flash map is prepared in the industry-accepted JSON (JavaScript Object Notation) format. It should follow the rules described in section **How to modify flash map**.
+The flash map of the bootloader is defined at compile-time and cannot be changed dynamically. Flash map is prepared in the industry-accepted JSON (JavaScript Object Notation) format. It should follow the rules described in section **How to modify the flash map**.
-`MCUBootApp` contains JSON templates for flash maps with commonly used configurations. They can be found in `cy_flash_pal/flash_%platform_name%/flashmap` The slots' sizes are defined per platform to be compatible with all supported device families.
+`MCUBootApp` contains JSON templates for flash maps with commonly used configurations. They can be found in `platforms/cy_flash_pal/flash_%platform_name%/flashmap` The slots' sizes are defined per platform to be compatible with all supported device families.
The actual addresses are provided in corresponding platform doc files:
-- [PSOC6.md](../platforms/PSOC6/PSOC6.md)
-- [CYW20289.md](../platforms/CYW20829/CYW20829.md)
+- [PSOC6.md](../platforms/PSOC6.md)
+- [CYW20289.md](../platforms/CYW20829.md)
-#### How to modify flash map
+#### How to modify the flash map
When modifying slots sizes, ensure aligning new values with the linker script files for appropriate applications.
@@ -47,33 +50,43 @@
###### Flash map format
Flash map must have the `"boot_and_upgrade"` section, define the location of `MCUBootApp` and at least one image. For instance:
+
```
{
- "boot_and_upgrade": {
- "bootloader": {
- "address": {
+ "boot_and_upgrade":
+ {
+ "bootloader":
+ {
+ "address":
+ {
"description": "Address of the bootloader",
"value": "0x10000000"
},
- "size": {
+ "size":
+ {
"description": "Size of the bootloader",
"value": "0x18000"
}
},
- "application_1": {
- "address": {
+ "application_1":
+ {
+ "address":
+ {
"description": "Address of the application primary slot",
"value": "0x10018000"
},
- "size": {
+ "size":
+ {
"description": "Size of the application primary slot",
"value": "0x10000"
},
- "upgrade_address": {
+ "upgrade_address":
+ {
"description": "Address of the application secondary slot",
"value": "0x18030200"
},
- "upgrade_size": {
+ "upgrade_size":
+ {
"description": "Size of the application secondary slot",
"value": "0x10000"
}
@@ -81,9 +94,10 @@
}
}
```
+
Here an application identifier should follow the pattern, i.e., the 2nd image in the multi-image case is `"application_2"`, the 3rd is `"application_3"`, and so on. Up to four applications are supported at this moment.
-For each image the location and size of its primary slot is given in the `"address"` and `"size"` parameters. The location and size of the secondary slot is specified in the `"upgrade_address"` and `"upgrade_size"`. All four values described above are mandatory.
+For each image, the location and size of its primary slot are given in the `"address"` and `"size"` parameters. The location and size of the secondary slot are specified in the `"upgrade_address"` and `"upgrade_size"`. All four values described above are mandatory.
There also should be a mandatory `"bootloader"` section, describing the location and size of `MCUBootApp` in the `"address"` and `"size"` parameters, respectively.
@@ -91,14 +105,18 @@
```
Misaligned application_1 (secondary slot) - suggested address 0x18030200
```
-This gives the nearest larger address that satisfy the slot location requirements. Other errors, such as overlapping flash areas, are also checked and reported.
+This gives the nearest larger address that satisfies the slot location requirements. Other errors, such as overlapping flash areas, are also checked and reported.
###### Scratch area
-If there is a scratch area, what is generally true, its location and size is given in the `"scratch_address"` and `"scratch_size"` parameters of the `"bootloader"` subsection. For example:
+The scratch area location and size are given in the `"scratch_address"` and `"scratch_size"` parameters of the `"bootloader"` subsection.
+For example:
+
```
{
- "boot_and_upgrade": {
- "bootloader": {
+ "boot_and_upgrade":
+ {
+ "bootloader":
+ {
. . .
"scratch_address": {
"description": "Address of the scratch area",
@@ -114,10 +132,13 @@
###### Swap status partition
If the desired upgrade mode is `swap scratch with status partition`, one should define the `"status_address"` and `"status_size"` parameters in the `"bootloader"` subsection, e.g.:
+
```
{
- "boot_and_upgrade": {
- "bootloader": {
+ "boot_and_upgrade":
+ {
+ "bootloader":
+ {
. . .
"status_address": {
"description": "Address of the swap status partition",
@@ -137,7 +158,8 @@
To calculate the minimal correct size of the status partition, one could specify `"value": "0"` for the `"status_size"`. After the intentional `make` failure, copy the correct size from the error message.
###### External flash
-If an external flash memory is used, one should specify its parameters. The first way is specyfing the exact model:
+If external flash memory is used, one should specify its parameters. The first way is to specify the exact model:
+
```
{
"external_flash": [
@@ -148,7 +170,8 @@
"boot_and_upgrade": {
. . .
```
-However, the supported model list is incomplete. The known models are Infineon `S25HS256T`/`S25HS512T`/`S25HS01GT` SEMPER™ NOR Flash ICs, and a couple of SPI Flash ICs from other vendors. Another way is specyfing the important parameters, like:
+However, the supported model list is incomplete. The known models are Infineon `S25HS256T`/`S25HS512T`/`S25HS01GT` SEMPER™ NOR Flash ICs, and a couple of SPI Flash ICs from other vendors. Another way is specifying the important parameters, like:
+
```
{
"external_flash": [
@@ -160,9 +183,10 @@
"boot_and_upgrade": {
. . .
```
-for a typical 8-Mbit SPI flash with uniform 4-KByte erase blocks. While JSON list syntax is used for the `"external_flash"` section, only single instance is supported at this moment.
+for a typical 8-Mbit SPI flash with uniform 4-KByte erase blocks. While JSON list syntax is used for the `"external_flash"` section, only a single instance is supported at this moment.
If the main application image is located in the external flash, `XIP` (eXecute In Place) mode should be turned on. To do so, supply the corresponding `"mode"` parameter:
+
```
{
"external_flash": [
@@ -174,8 +198,9 @@
. . .
```
###### Service RAM Application
-The CYW20829 platform has a hardware-supported security counter. For more details on rollback protection support, refer to the [CYW20289.md](../platforms/CYW20829/CYW20829.md) file.
+The CYW20829 platform has a hardware-supported security counter. For more details on rollback protection support, refer to the [CYW20289.md](../platforms/CYW20829.md) file.
The mentioned feature requires a dedicated area in the flash memory to store the Service RAM Application and other required data. The layout of these areas is defined in the `"service_app"` JSON section:
+
```
. . .
"boot_and_upgrade":
@@ -183,7 +208,8 @@
"bootloader": {
. . .
},
- "service_app": {
+ "service_app":
+ {
"address": {
"description": "Address of the service application",
"value": "0x60070000"
@@ -213,13 +239,14 @@
. . .
```
###### Shared secondary slot
-In the multi-image case, one can reduce the utilization of flash memory by placing secondary images into the same area. This area is reffered to as **Shared secondary slot**. This is especially desirable if there are more than two images.
+In the multi-image case, one can reduce the utilization of flash memory by placing secondary images in the same area. This area is referred to as **Shared secondary slot**. This is especially desirable if there are more than two images.
-Important consideration is that this option assumes updates are performed in sequential manner (consider the Swap upgrade method): place the 1st image into the shared slot, reset to MCUBoot, check the updated image and set the Image OK flag for the 1st image, reset to MCUBoot for permanent swap. Then place the 2nd image into the shared slot, reset to MCUBoot, check the updated image and set the Image OK flag for the 2nd image, reset to MCUBoot for permanent swap, etc.
+An important consideration is that this option assumes updates are performed in a sequential manner (consider the Swap upgrade method): place the 1st image into the shared slot, reset to MCUBoot, check the updated image and set the Image OK flag for the 1st image, reset to MCUBoot for permanent swap. Then place the 2nd image into the shared slot, reset to MCUBoot, check the updated image, and set the Image OK flag for the 2nd image, reset to MCUBoot for permanent swap, etc.
-Take into account that it is possible to revert only the last updated image, as its previous version resides in the Shared secondary slot. There is no way to revert changes for previous images, as their backups are gone! That is trade-off of the Shared secondary slot.
+Take into account that it is possible to revert only the last updated image, as its previous version resides in the Shared secondary slot. There is no way to revert changes for previous images, as their backups are gone! That is the trade-off of the Shared secondary slot.
-Shared secondary slot is rather a virtual concept, we still create individual flash areas for all secondary images. However, this areas are now overlapped (this is prohibited in the standard multi-image scenario). Moreover, special placing of secondary slots is required, as described below. Consider the triple-image example:
+A shared secondary slot is rather a virtual concept, we still create individual flash areas for all secondary images. However, these areas are now overlapped (this is prohibited in the standard multi-image scenario). Moreover, the special placing of secondary slots is required, as described below. Consider the triple-image example:
+
```
| |---------| |\
| | | | \
@@ -235,11 +262,12 @@
| | | Trailer | /
| | |---------|/
```
-The purpose of such layout is to allow MCUBoot to understand what image is placed in the shared secondary slot. While secondary images now can (and should) overlap, their trailers must under no circumstances share the same address!
+The purpose of such a layout is to allow MCUBoot to understand what image is placed in the shared secondary slot. While secondary images now can (and should) overlap, their trailers must under no circumstances share the same address!
-Normally image trailer occupies the whole erase block (e.g. 512 bytes for PSoC™ 62 internal Flash, or 256 kilobytes for SEMPER™ Secure NOR Flash). There is a specific case when images are placed in both memory types, refer to the [PSOC6.md](../platforms/PSOC6/PSOC6.md) file.
+Normally image trailer occupies the whole erase block (e.g. 512 bytes for PSoC™ 62 internal Flash, or 256 kilobytes for SEMPER™ Secure NOR Flash). There is a specific case when images are placed in both memory types, refer to the [PSOC6.md](../platforms/PSOC6.md) file.
One can declare all secondary slots as shared using the following JSON syntax:
+
```
"boot_and_upgrade": {
"bootloader": {
@@ -251,6 +279,7 @@
},
```
Alternatively, this can be done for each application:
+
```
"boot_and_upgrade": {
"bootloader": {
@@ -272,23 +301,56 @@
},
. . .
```
-where `true` marks the shared slot, `false` marks the normal (non-shared) secondary slot. In theory, one can use a separate secondary slot for the 1st image, and shared secondary slot for all other images.
+where `true` marks the shared slot, `false` marks the normal (non-shared) secondary slot. In theory, one can use a separate secondary slot for the 1st image and a shared secondary slot for all other images.
When the `shared_slot` flag is set, different checks are performed at the pre-build stage. For instance, the following error is reported if image trailers appear at the same address:
```
Same trailer address for application_3 (secondary slot) and application_2 (secondary slot)
```
-As mentioned above, shared secondary slot is a virtual concept, so overlapped flash areas are created for each image's secondary slot. No separate flash area is created for the shared slot itself.
+As mentioned above, a shared secondary slot is a virtual concept, so overlapped flash areas are created for each image's secondary slot. No separate flash area is created for the shared slot itself.
**Upgrade process deviations**
-Shared slot feature has some differences and limitations in the update algorithm when there is one or more invalid images in primary slots and upgrade of these images is initiated through the shared upgrade slot (so-called **bootstrap** mode of bootloader). In this case, the bootloader allows to update the image even if other images are not valid (unlike the classic multi-image case). Bootloader however does not transfer control to these images until all primary slots become valid. ImageOK flag is set by updated images only after their successful validation and start.
+The shared slot feature has some differences and limitations in the update algorithm when there are one or more invalid images in primary slots and an upgrade of these images is initiated through the shared upgrade slot (so-called **bootstrap** mode of bootloader). In this case, the bootloader allows to update the image even if other images are not valid (unlike the classic multi-image case). Bootloader however does not transfer control to these images until all primary slots become valid. ImageOK flag is set by updated images only after their successful validation and start.
-Considering above there is a certain limitation for the shared slot mode. For **swap mode**, an update of valid slots is not possible as long as there is at least one image with an invalid prime slot.
+Considering the above there is a certain limitation for the shared slot mode. For **swap mode**, an update of valid slots is not possible as long as there is at least one image with an invalid prime slot.
-Attempting to upgrade a valid primary slot of one image with an invalid primary slot of another image may run a revert procedure the next time the bootloader is started (provided that the data of shared slot has not been changed before). Therefore, for the shared slot, it is recommended to first make all invalid primary slots valid and only then update other images through the shared slot.
+Attempting to upgrade a valid primary slot of one image with an invalid primary slot of another image may run a revert procedure the next time the bootloader is started (provided that the data of the shared slot has not been changed before). Therefore, for the shared slot, it is recommended to first make all invalid primary slots valid and only then update other images through the shared slot.
+
+###### Running on the specific core
+PSoC™ 6 platform has an option to select the core (i.e., either `Cortex-M4` or `Cortex-M0+`) on which the user application should be run. This is useful for multicore firmware. Selection is done in the `"core"` JSON section:
+
+```
+{
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ . . .
+ },
+ "application_1": {
+ "core": {
+ "description": "Run app on the specific core. PSoC6: CM0P or CM4",
+ "value": "CM0P"
+ },
+ "address": {
+ "description": "Address of the application primary slot",
+ "value": "0x10018000"
+ },
+ "size": {
+ "description": "Size of the application primary slot",
+ "value": "0x10000"
+ },
+ . . .
+ }
+ }
+}
+```
+If not specified, the default `CM4` core is assumed.
+
+Note that in the multi-image case this option makes sense only for `application_1`, as MCUBoot always starts the 1st image. Specifying `core` for other images is an error.
###### JSON syntax rules
+```
| Group | Item | Description |
|--------------------|-------------------|----------------------------------------------------------|
| `external_flash` | `model` | External flash model (if supported), e.g. `S25HS256T` |
@@ -319,6 +381,7 @@
| `application_1` | `upgrade_address` | Absolute address of the Secondary Slot of the 1st image |
| `application_1` | `upgrade_size` | Size (in bytes) of the Secondary Slot of the 1st image |
| `application_1` | `shared_slot` | Marking the shared secondary slot for the 1st image |
+| `application_1` | `core` | Specify the core to run an application (only on PSoC™ 6) |
| `address` | `value` | Value of the given address (hex or decimal) |
| `scratch_address` | `value` | Value of the Scratch Area address (hex or decimal) |
| `status_address` | `value` | Value of the Status Partition address (hex or decimal) |
@@ -328,26 +391,28 @@
| `status_size` | `value` | Value of the Status Partition size (hex or decimal) |
| `upgrade_size` | `value` | Value of the Secondary Slot size (hex or decimal) |
| `shared_slot` | `value` | Set to `true` for the Shared secondary slot |
+| `core` | `value` | Either `Cortex-M4` (default) or `Cortex-M0+` |
+```
###### Flash map internals
-When the `FLASH_MAP=` option is supplied to `make`, it involves the Python script `boot/cypress/scripts/flashmap.py`. It takes the JSON file and converts flash map into the C header file `boot/cypress/MCUBootApp/cy_flash_pal/cy_flash_map.h`.
+When the `FLASH_MAP=` option is supplied to `make`, it involves the Python script `boot/cypress/scripts/flashmap.py`. It takes the JSON file and converts flash map into the C header file `boot/cypress/platforms/cy_flash_pal/cy_flash_map.h`.
At the same time it creates the `boot/cypress/MCUBootApp/flashmap.mk`, which is conditionally included from the `boot/cypress/MCUBootApp/MCUBootApp.mk`. The generated file contains various definitions derived from the flash map, such as `MCUBOOT_IMAGE_NUMBER`, `MAX_IMG_SECTORS`, `USE_EXTERNAL_FLASH`, and `USE_XIP`. So, there is no need to specify these and similar parameters manually.
-Do not edit neither `sysflash/cy_flash_map.h` nor `flashmap.mk`, as both files are overwritten on every build.
+Do not edit either `sysflash/cy_flash_map.h` or `flashmap.mk`, as both files are overwritten on every build.
#### External flash
-Some Cypress devices, for example `CYW20829`, only have external flash, so all memory areas are located in external flash.
+Some Cypress devices, for example, `CYW20829`, only have an external flash, so all memory areas are located in an external flash.
-Hoewever, PSoC™ 6 chips has internal flash and, additionally, support the external memory connection. Thus, it is possible to place secondary (upgrade) slots in the external memory module and use most of internal flash for the primary image.
+However, PSoC™ 6 chips have internal flash and, additionally, support the external memory connection. Thus, it is possible to place secondary (upgrade) slots in the external memory module and use most of the internal flash for the primary image.
For more details on External Memory usage, refer to the [ExternalMemory.md](ExternalMemory.md) file.
#### PSoC™ 6 RAM
-RAM areas in the MCUBootApp bootloading application and BlinkyApp are defined as an example pair. If your user application requires a different RAM area, ensure that it is not overlapped with the MCUBootApp RAM area. The memory (stack) corruption of the bootloading application can cause a failure if SystemCall-served operations were invoked from the user app.
+RAM areas in the MCUBootApp bootloader application and BlinkyApp are defined as an example pair. If your user application requires a different RAM area, ensure that it is not overlapped with the MCUBootApp RAM area. The memory (stack) corruption of the bootloading application can cause a failure if SystemCall-served operations were invoked from the user app.
-The MCUBootApp linker script also contains the special section `public_ram`, which serves as a shared RAM area between the CM0p and CM4 cores. When CM4 and CM0p cores perform operations with internal flash, this area is used for the interprocessor data sharing.
+The MCUBootApp linker script also contains the special section `public_ram`, which serves as a shared RAM area between the CM0p and CM4 cores. When CM4 and CM0p cores perform operations with internal flash, this area is used for interprocessor data sharing.
#### CYW20829 RAM
@@ -359,24 +424,26 @@
The CYW20289 chip has hardware acceleration of the SHA256 algorithm only, and in other cases, uses pure software implementation of the cryptography based on MbedTLS.
-To enable the hardware acceleration in `MCUBootApp`, pass flag `USE_CRYPTO_HW=1` to `make` during build.
+To enable the hardware acceleration in `MCUBootApp`, pass flag `USE_CRYPTO_HW=1` to `make` during the build.
-The hardware cryptographic acceleration is disabled for all devices at the moment. `USE_CRYPTO_HW` flag is set to 0 by default. This package will be updated in next version.
+The hardware cryptographic acceleration is disabled for all devices at the moment. `USE_CRYPTO_HW` flag is set to 0 by default. This package will be updated in the next version.
-__NOTE__: Hardware acceleration is not available in current version of mcuboot since `cy-mbedtls-acceleration` does not support `mbedTLS 3.0` yet.
+__NOTE__: Hardware acceleration is not available in the current version of mcuboot since `cy-mbedtls-acceleration` does not support `mbedTLS 3.0` yet.
+
+__NOTE__: To reduce boot time for MCUBoot in `SWAP` mode, in the case when only **Primary slot** is programmed - disable `BOOTSTRAP` functionality. This happens because `BOOTSTRAP` uses additional slot validation, and it takes more time without hardware cryptography acceleration.
### Multi-image mode
Multi-image operation considers upgrading and verification of more than one image on a device.
-Single or multi-image mode is dictated by `MCUBOOT_IMAGE_NUMBER` `make` flag. This flag's value is set in auto-generated `flashmap.mk` file per flash map used. There is no need to pass it manually.
+Single or multi-image mode is dictated by the `MCUBOOT_IMAGE_NUMBER` `make` flag. This flag's value is set in an auto-generated `flashmap.mk` file per flash map used. There is no need to pass it manually.
-In Multi-image operation up to four images are supported.
+In Multi-image operation, up to four images are supported.
-Consider MCUBootApp with 2 images supported. Operation is the following:
+Consider MCUBootApp with 2 images supported. The operation is the following:
1. Verification of the Secondary_1 and Secondary_2 images.
-2. Upgrades Secondary to Primary if valid images found.
+2. Upgrades Secondary to Primary if valid images are found.
3. Verification of the Primary_1 and Primary_2 images.
4. Boots the image from the Primary_1 slot only.
5. Boots Primary_1 only if both - Primary_1 and Primary_2 are present and valid.
@@ -385,11 +452,11 @@
### Upgrade modes
-There are two different types of the upgrade process supported by MCUBootApp. For the `overwrite only` type of upgrade - the secondary image is simply copied to the primary slot after successful validation. No way to revert upgrade if the secondary image is inoperable.
+There are two different types of upgrade processes supported by MCUBootApp. For the `overwrite only` type of upgrade - the secondary image is simply copied to the primary slot after successful validation. No way to revert the upgrade if the secondary image is inoperable.
-For `swap` upgrade mode - images in the primary and secondary slots are swapped. Upgrade can be reverted if the secondary image did not confirm its operation.
+For `swap` upgrade mode - images in the primary and secondary slots are swapped. The upgrade can be reverted if the secondary image did not confirm its operation.
-Upgrade mode is the same for all images in Multi-image mode.
+Upgrade mode is the same for all images in the Multi-image mode.
#### Overwrite only
@@ -397,23 +464,23 @@
`#define MCUBOOT_OVERWRITE_ONLY 1`
-This flag's value is set in auto-generated `flashmap.mk` file per flash map used. There is no need to pass it manually.
+This flag's value is set in an auto-generated `flashmap.mk` file per flash map used. There is no need to pass it manually.
In Overwrite-only mode, MCUBootApp first checks if any upgrade image is present in the secondary slot(s), then validates the digital signature of the upgrade image in the secondary slot(s). If validation is successful, MCUBootApp starts copying the secondary slot content to the primary slot. After the copy is done, MCUBootApp starts the upgrade image execution from the primary slot.
-If the upgraded application does not work - there is no way to revert back to the previous working version. Only the new upgrade firmware can fix the previous broken upgrade.
+If the upgraded application does not work - there is no way to revert to the previous working version. Only the new upgrade firmware can fix the previously broken upgrade.
#### Swap mode
-For devices with a large minimum-erase size like PSoC™ 6 with 512 bytes and also for configurations, which use external flash with an even bigger minimum-erase size, there is an additional option in MCUBoot to use the dedicated `status partition` for robust storage of swap-related information.
+For devices with large minimum-erase size like PSoC™ 6 with 512 bytes and also for configurations, which use an external flash with an even bigger minimum-erase size, there is an additional option in MCUBoot to use the dedicated `status partition` for robust storage of swap-related information.
##### Why use swap with status partition
-Originally, the MCUboot library has been designed with a consideration that the minimum write/erase size of flash is always 8 bytes or less. This value is critical, because the swap algorithms use it to align portions of data that contain the swap operation status of each flash sector in a slot before writing to flash. Data alignment is also performed before writes of special-purpose data to the image trailer.
+Originally, the MCUboot library has been designed with the consideration that the minimum write/erase size of the flash is always 8 bytes or less. This value is critical because the swap algorithms use it to align portions of data that contain the swap operation status of each flash sector in a slot before writing to flash. Data alignment is also performed before the writing of special-purpose data to the image trailer.
Writing of the flash sector status or image trailer data will be the `single cycle` operation to ensure that the power loss and unpredicted resets robustness of bootloading applications. This requirement eliminates the usage of the `read-modify-write` type of operations with flash.
-`Swap with status partition` is implemented specifically to address devices with a large write/erase size. It is based on existing MCUboot swap algorithms, but does not have restriction of the 8-byte alignment. Instead, the minimum write/erase size can be specified by the user and the algorithm will calculate sizes of the status partition considering this value. All write/erase operations are aligned to this minimum write/erase size as well.
+`Swap with status partition` is implemented specifically to address devices with a large write/erase size. It is based on existing MCUboot swap algorithms but does not have restrictions on the 8-byte alignment. Instead, the minimum write/erase size can be specified by the user and the algorithm will calculate the sizes of the status partition considering this value. All write/erase operations are aligned to this minimum write/erase size as well.
##### Swap status partition description
@@ -433,7 +500,7 @@
* Image ok
* Boot image magic
-The principal diagram of the status partition:
+The principle diagram of the status partition:
```
+-+-+-+-+-+-+ +-+-+-+-+-+-+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ \
@@ -475,7 +542,7 @@
**Scheme legend:**
`PRIMARY` and `SECONDARY` are areas in the status partition to contain data regarding a corresponding slot in MCUboot.
-`D0`, `D1`, and `Dx` are duplicates of data described on the left. At least 2 duplicates are present in the system. This duplication is used to eliminate flash wear. Each of `Dx` contains valid data for `current swap step - 1`. Each swap operation for the flash sector updates the status for this sector in the current `Dx` and the value on `CNT` increases. The next operation checks the least value of `CNT` in the available `Dx`s, copies the data from `Dx` with `CNT+1` and updates the status of the current sector. This continues until all sectors in the slot are moved and then swapped.
+`D0`, `D1`, and `Dx` are duplicates of data described on the left. At least 2 duplicates are present in the system. This duplication is used to eliminate flash wear. Each of `Dx` contains valid data for `current swap step - 1`. Each swap operation for the flash sector updates the status for this sector in the current `Dx` and the value on `CNT` increases. The next operation checks the least value of `CNT` in the available `Dx`s, copies the data from `Dx` with `CNT+1`, and updates the status of the current sector. This continues until all sectors in the slot are moved and then swapped.
`CRC` - A 4-byte value - the checksum of data contained in the area.
`CNT` - A 4-byte value.
`swap_status_0`, `swap_status_1` - 1-byte values that contain the status for a corresponding image sector.
@@ -494,7 +561,7 @@
One slice of the `min write/erase` size can store data for the maximum number of 500 sectors: 512 - 4 (CRC) - 4 (CNT) - 4 (area magic) = 500. BOOT_MAX_IMG_SECTORS is 640, so 2 slices of `min write/erase` are allocated. The total size is 1024 bytes.
Image trailer data fits in 64 bytes, so one slice of the `min write/erase` size is allocated. The total size is 1024 + 512 = 1536 bytes.
-The number of duplicates 2. The total size is 1536 * 2 = 3072 bytes.
+The number of duplicates is 2. The total size is 1536 * 2 = 3072 bytes.
2 slots are used in the particular case PRIMARY and SECONDARY, each needs 3072 bytes to store swap status data. The total is 3072 * 2 = 6144 bytes.
The swap status partition occupies 6144 bytes of the flash area.
@@ -506,15 +573,15 @@
`Empty` - A fully-erased device.
`Ready` - `Empty` -The device is programmed with the MCUboot-based bootloading application - MCUBootApp in this case.
`Flashed` - Initial version v1.0 of the user application, BlinkyApp in this case, is flashed to the primary (BOOT) slot.
-`Upgraded` - The updated firmware image of the user application is delivered to the secondary slot (UPGRADE) and the bootloading application performs upgrade.
+`Upgraded` - The updated firmware image of the user application is delivered to the secondary slot (UPGRADE) and the bootloading application performs an upgrade.
It is expected that the product stays in the `Upgraded` state until the end of its lifecycle.
-If there is a need to wipe out product and flash new firmware directly to the primary (BOOT) slot, the device is transferred to the `Empty` or `Ready` state and then walks through all the states again.
+If there is a need to wipe out the product and flash new firmware directly to the primary (BOOT) slot, the device is transferred to the `Empty` or `Ready` state and then walks through all the states again.
### Hardware limitations
-This application is created to demonstrate the MCUboot library features and not as a reference examples. So, some considerations are taken.
+This application is created to demonstrate the MCUboot library features and not as a reference example. So, some considerations are taken.
1. `SCB5` is used to configure a serial port for debug prints. This is the most commonly used Serial Communication Block number among available Cypress PSoC™ 6 kits. To use custom hardware with this application, set custom `SCB*` and pins in the `cypress/MCUBootApp/custom_debug_uart_cfg.h` file and pass the `USE_CUSTOM_DEBUG_UART=1` parameter to the `make` command upon MCUBootApp build.
@@ -527,9 +594,10 @@
`CUSTOM_UART_RX_PIN` - Sets the pin number in the GPIO port used as RX of the debug serial port.
`CUSTOM_UART_TX_PIN` - Sets the pin number in the GPIO port used as TX of the debug serial port.
-The above-described applies only to the `PSoC™ 062` platform.
+The above-described applies to `PSoC™ 62` and `PSoC™ 63` platforms.
2. `CY_SMIF_SLAVE_SELECT_0` is used to define the chip select for the SMIF driver. This configuration is used on the evaluation kit for this example CY8CPROTO-062-4343W. To use custom hardware with this application, change the value of `smif_id` in `main.c` of MCUBootApp to a value that corresponds to your design.
+__NOTE__: SMIF driver not supported with `PSoC™ 063` based kits.
### Downloading solution assets
@@ -548,69 +616,113 @@
1. Choose Upgrade mode and number of images.
-`cy_flash_pal/flash_%platform_name%/flashmap` folder contains a set of predefined flash map JSON files with suffixes _overwrite_ or _swap_ for upgrade methods and _single_ or _multi_ for images number in its names. Depending on the file chosen upgrade method and images number is configured:
+`platforms/cy_flash_pal/flash_%platform_name%/flashmap` folder contains a set of predefined flash map JSON files with suffixes _overwrite_ or _swap_ for upgrade methods and _single_ or _multi_ for images number in its names. Depending on the file chosen upgrade method and images number are configured:
`USE_OVERWRITE` `make` flag is set to 1 or 0 for `overwrite` or `swap` mode;
-`MCUBOOT_IMAGE_NUMBER` flag is set to number of corresponding `application_#` sections in flash map file.
+`MCUBOOT_IMAGE_NUMBER` flag is set to a number of corresponding `application_#` sections in the flash map file.
-These flags values are set in auto-generated `flashmap.mk` file per flash map used. There is no need to pass them manually.
+These flag values are set in an auto-generated `flashmap.mk` file per flash map used. There is no need to pass them manually.
+
+__NOTE__: Do not use flash map JSON files with suffixes xip or smif for `PSoC™ 063` kits.
2. Enable the hardware acceleration of the cryptography on devices that support this feature.
Pass `USE_CRYPTO_HW=1` to the `make` command. This option is temporarily disabled by default - see paragraph **Hardware cryptography acceleration**.
-Additionally user can configure hardware rollback protection on the supported platforms. To do this flash map file from `cy_flash_pal/flash_%platform_name%/flashmap/hw_rollback_prot` folder should be used.
+Additionally, users can configure hardware rollback protection on the supported platforms. To do this flash map file from `platforms/cy_flash_pal/flash_%platform_name%/flashmap/hw_rollback_prot` folder should be used.
`USE_HW_ROLLBACK_PROT` `make` flag is set to 1 in auto-generated `flashmap.mk`.
-Rollback protection feature is currently supported on CYW20829 devices in Secure mode only.
+The rollback protection feature is currently supported on CYW20829 devices in Secure mode only.
### Building solution
Folder `boot/cypress` contains make-files infrastructure for building MCUBootApp bootloader applications. Example build commands are provided later in this document for different build configurations.
+Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE 3.0**:
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/$(USERNAME)/ModusToolbox/tools_3.0/gcc
+
* Build MCUBootApp in the `Debug` configuration for Single-image mode with swap upgrade.
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json
+ `PSoC™ 062`
-* Build MCUBootApp in `Release` configuration for Multi-image mode with overwrite update.
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi.json
+ `PSoC™ 063`
-The root directory for build is `boot/cypress`.
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_063_1M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json
+
+* Build MCUBootApp in `Release` configuration for Multi-image mode with overwriting update.
+
+ `PSoC™ 062`
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Release FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi.json
+
+ `PSoC™ 063`
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_063_1M BUILDCFG=Release FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi.json
+
+* Build MCUBootApp in `Debug` configuration for Single-image mode with swap upgrade and in `smif` mode.
+
+ `PSoC™ 062`
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json
+
+ `PSoC™ 063`
+
+ Supported only for `PLATFORM=PSOC_063_1M DEVICE=CY8C6347BZI-BLD53`
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_1M DEVICE=CY8C6347BZI-BLD53 BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json
+ `NOTE:` PSOC_062_1M platform is used here since kit, where particular MPN is installed is called CY8CKIT-062-BLE
+
+* Build MCUBootApp in `Debug` configuration for Single-image mode with swap upgrade and in `xip` mode.
+
+ `PSoC™ 062`
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_swap.json
+
+ `PSoC™ 063`
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_1M DEVICE=CY8C6347BZI-BLD53 BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_swap.json
+ `NOTE:` PSOC_062_1M platform is used here since kit, where particular MPN is installed is called CY8CKIT-062-BLE
+
+The root directory for the build is `boot/cypress`.
### Encrypted image support
-To protect firmware content from read, plain binary data can be encrypted. MCUBootApp supports the encrypted image in some implementations, depending on the platform.
+To protect firmware content from reading, plain binary data can be encrypted. MCUBootApp supports the encrypted image in some implementations, depending on the platform.
-On PSoC™ 6, an upgrade image can be encrypted and then programmed to corresponding Secondary slot of MCUBootApp. It is then decrypted and transferred to the primary slot using the preferred upgrade method. For more details on the encrypted image implementation, refer to the [PSOC6.md](../platforms/PSOC6/PSOC6.md) file.
+On PSoC™ 6, an upgrade image can be encrypted and then programmed to the corresponding Secondary slot of MCUBootApp. It is then decrypted and transferred to the primary slot using the preferred upgrade method. For more details on the encrypted image implementation, refer to the [PSOC6.md](../platforms/PSOC6.md) file.
-On CYW20829, an encrypted image is supported in both slots. The firmware here is located in external memory, so, the chip's SMIF block encrypted eXecution In Place (XIP) feature is used. Encrypted firmware is placed directly in the primary slot and is decrypted on the fly. The encrypted upgrade image is first validated by MCUBootApp in the secondary slot and then transferred to the primary slot as it is. For more details on the encrypted image implementation, refer to the [CYW20289.md](../platforms/CYW20829/CYW20829.md) file.
+On CYW20829, an encrypted image is supported in both slots. The firmware here is located in external memory, so, the chip's SMIF block encrypted eXecution In Place (XIP) feature is used. Encrypted firmware is placed directly in the primary slot and is decrypted on the fly. The encrypted upgrade image is first validated by MCUBootApp in the secondary slot and then transferred to the primary slot as it is. For more details on the encrypted image implementation, refer to the [CYW20289.md](../platforms/CYW20829.md) file.
### Rollback protection
MCUboot supports the security counter implementation to provide downgrade prevention. This mechanism allows the user to explicitly restrict the possibility to execute/upgrade images whose security counters are less than the current firmware counter. So, it can be guaranteed, that obsolete firmware with possible vulnerabilities can not be executed on the device.
**Currently, only the CYW20829 platform supports the hardware rollback counter protection.**
-For more details on the implementation, refer to the [CYW20289.md](../platforms/CYW20829/CYW20829.md) file.
+For more details on the implementation, refer to the [CYW20289.md](../platforms/CYW20829.md) file.
### Complete build flags and parameters description
Can be passed to `make` or set in makefiles.
-`MCUBOOT_LOG_LEVEL` - Can be set at `MCUBOOT_LOG_LEVEL_DEBUG` to enable the verbose output of MCUBootApp.
-`ENC_IMG` - When set to `1`, enables the encrypted image support in MCUBootApp.
-`APP_DEFAULT_POLICY` - The path to a policy file to use for signing MCUBootApp and user application (BlinkyApp) on the CYW20829 platform.
-`USE_BOOTSTRAP` - When set to `1` and Swap mode is enabled, the application in the secondary slot will overwrite the primary slot, if the primary slot application is invalid.
-`USE_CRYPTO_HW` - When set to `1`, uses the hardware accelerated cryptography on the PSoC™ 6 platform, and SHA-256 HW acceleration for the CYW20289 platform.
-`LSC` - The lifecycle state of the chip. Possible options are `SECURE` and `NORMAL_NO_SECURE` (effective on CYW20829 chip only).
+`MCUBOOT_LOG_LEVEL` - Can be set at `MCUBOOT_LOG_LEVEL_DEBUG` to enable the verbose output of MCUBootApp.
+`ENC_IMG` - When set to `1`, it enables the encrypted image support in MCUBootApp.
+`APP_DEFAULT_POLICY` - The path to a policy file to use for signing MCUBootApp and user application (BlinkyApp) on the CYW20829 platform.
+`USE_BOOTSTRAP` - When set to `1` and Swap mode is enabled, the application in the secondary slot will overwrite the primary slot if the primary slot application is invalid.
+`USE_CRYPTO_HW` - When set to `1`, uses the hardware-accelerated cryptography on the PSoC™ 6 platform, and SHA-256 HW acceleration for the CYW20289 platform.
+`LSC` - The lifecycle state of the chip. Possible options are `SECURE` and `NORMAL_NO_SECURE` (effective on CYW20829 chip only).
+`DEVICE` - is used to set a particular MPN for a platform since multiple MPNs are associated with one platform, for example:
+`PLATFORM=PSOC_062_1M DEVICE=CY8C6347BZI-BLD53`
-Set by script in auto-generated makefile file.
+The next flags will be set by script in auto-generated makefile 'flashmap.mk':
+`MCUBOOT_IMAGE_NUMBER` - The number of images to be supported by the current build of MCUBootApp.
+`USE_OVERWRITE` - `0` - Use swap with Scratch upgrade mode, `1` - use Overwrite only upgrade.
+`USE_EXTERNAL_FLASH` - When set to `1`, it enables the external memory support on the PSoC™ 6 platform. This value is always set to `1` on CYW20829.
+`USE_HW_ROLLBACK_PROT` - When set to `1`, it enables the hardware rollback protection on the CYW20829 platform with Secure mode enabled.
-`MCUBOOT_IMAGE_NUMBER` - The number of images to be supported by the current build of MCUBootApp.
-`USE_OVERWRITE` - `0` - Use swap with Scratch upgrade mode, `1` - use Overwrite only upgrade.
-`USE_EXTERNAL_FLASH` - When set to `1`, enables the external memory support on the PSoC™ 6 platform. This value is always set to `1` on CYW20829.
-`USE_HW_ROLLBACK_PROT` - When set to `1`, enables the hardware rollback protection on the CYW20829 platform with Secure mode enabled.
+Adding `clean` to `make` will clean the build folder, and files boot/cypress/MCUBootApp/flashmap.mk and boot/cypress/platforms/cy_flash_pal/cy_flash_map.h will be removed and re-generated.
### Programming solution
@@ -618,7 +730,7 @@
1. The direct usage of OpenOCD.
-The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in installation folder `ModusToolbox/tools_2.4/openocd`.
+The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in the installation folder `ModusToolbox/tools_2.4/openocd`.
Set environment variable `OPENOCD` to the path to the openocd folder in ModusToolbox™. Exact commands for programming images are provided in the corresponding platform readme files.
@@ -650,4 +762,4 @@
*Python/Python3* - ensure that you have the correct path referenced in `PATH`.
-*Msys2* - To use the systems path, navigate to the msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart the MSYS2 shell. This will inherit the system's path and find `python` installed in the regular way as well as `imgtool` and its dependencies.
+*Msys2* - To use the systems path, navigate to the msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, and restart the MSYS2 shell. This will inherit the system's path and find `python` installed in the regular way as well as `imgtool` and its dependencies.
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.mk b/boot/cypress/MCUBootApp/MCUBootApp.mk
index e6ed9ed..e2dae9f 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.mk
+++ b/boot/cypress/MCUBootApp/MCUBootApp.mk
@@ -35,7 +35,7 @@
ifneq ($(FLASH_MAP), )
$(CUR_APP_PATH)/flashmap.mk:
- $(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/cy_flash_pal/cy_flash_map.h > $(CUR_APP_PATH)/flashmap.mk
+ $(PYTHON_PATH) scripts/flashmap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/cy_flash_pal/cy_flash_map.h > $(CUR_APP_PATH)/flashmap.mk
include $(CUR_APP_PATH)/flashmap.mk
DEFINES_APP := -DCY_FLASH_MAP_JSON
endif
@@ -69,14 +69,13 @@
DEFINES_APP += -DMBEDTLS_CONFIG_FILE="\"mcuboot_crypto_config.h\""
DEFINES_APP += -DECC256_KEY_FILE="\"keys/$(SIGN_KEY_FILE).pub\""
DEFINES_APP += -D$(CORE)
+DEFINES_APP += -DAPP_$(APP_CORE)
DEFINES_APP += -DMCUBOOT_IMAGE_NUMBER=$(MCUBOOT_IMAGE_NUMBER)
DEFINES_APP += -DUSE_SHARED_SLOT=$(USE_SHARED_SLOT)
# Define MCUboot size and pass it to linker script
-BOOTLOADER_SIZE ?= $(PLATFORM_BOOTLOADER_SIZE)
LDFLAGS_DEFSYM += -Wl,--defsym,BOOTLOADER_SIZE=$(BOOTLOADER_SIZE)
-
APP_DEFAULT_POLICY ?= $(PLATFORM_APP_DEFAULT_POLICY)
ifeq ($(USE_EXTERNAL_FLASH), 1)
@@ -110,11 +109,26 @@
# Service RAM app size
DEFINES_APP += -DSERVICE_APP_SIZE=$(PLATFORM_SERVICE_APP_SIZE)
endif
-# Hardrware acceleration support
+# Hardware acceleration support
ifeq ($(USE_CRYPTO_HW), 1)
DEFINES_APP += -DMBEDTLS_USER_CONFIG_FILE="\"mcuboot_crypto_acc_config.h\""
DEFINES_APP += -DCY_CRYPTO_HAL_DISABLE
DEFINES_APP += -DCY_MBEDTLS_HW_ACCELERATION
+
+INCLUDE_DIRS_MBEDTLS_MXCRYPTO := $(CY_LIBS_PATH)/cy-mbedtls-acceleration
+INCLUDE_DIRS_MBEDTLS_MXCRYPTO += $(CY_LIBS_PATH)/cy-mbedtls-acceleration/COMPONENT_CAT1/include
+
+ifeq ($(PLATFORM), CYW20829)
+INCLUDE_DIRS_MBEDTLS_MXCRYPTO += $(CY_LIBS_PATH)/cy-mbedtls-acceleration/COMPONENT_CAT1/mbedtls_$(CRYPTO_ACC_TYPE)
+SOURCES_MBEDTLS_MXCRYPTO := $(wildcard $(CY_LIBS_PATH)/cy-mbedtls-acceleration/COMPONENT_CAT1/mbedtls_$(CRYPTO_ACC_TYPE)/*.c)
+DEFINES_APP += -Dcy_stc_cryptolite_context_sha256_t=cy_stc_cryptolite_context_sha_t
+else
+INCLUDE_DIRS_MBEDTLS_MXCRYPTO += $(CY_LIBS_PATH)/cy-mbedtls-acceleration/COMPONENT_CAT1/mbedtls_$(CRYPTO_ACC_TYPE)
+SOURCES_MBEDTLS_MXCRYPTO := $(wildcard $(CY_LIBS_PATH)/cy-mbedtls-acceleration/COMPONENT_CAT1/mbedtls_$(CRYPTO_ACC_TYPE)/*.c)
+endif
+
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS_MXCRYPTO))
+SOURCES_LIBS += $(SOURCES_MBEDTLS_MXCRYPTO)
endif
# Compile with user redefined values for UART HW, port, pins
@@ -122,6 +136,11 @@
DEFINES_APP += -DUSE_CUSTOM_DEBUG_UART=1
endif
+# Log timestamp information
+ifeq ($(USE_LOG_TIMESTAMP), 1)
+DEFINES_APP += -DUSE_LOG_TIMESTAMP
+endif
+
# Encrypted image support
ifeq ($(ENC_IMG), 1)
DEFINES_APP += -DENC_IMG=1
@@ -139,11 +158,34 @@
endif
endif
+ifeq ($(USE_MEASURED_BOOT), 1)
+DEFINES_APP += -DMCUBOOT_MEASURED_BOOT
+DEFINES_APP += -DMAX_BOOT_RECORD_SZ=512
+DEFINES_APP += -DMCUBOOT_SHARED_DATA_BASE=0x08000800
+DEFINES_APP += -DMCUBOOT_SHARED_DATA_SIZE=0x200
+endif
+
+ifeq ($(USE_DATA_SHARING), 1)
+DEFINES_APP += -DMCUBOOT_DATA_SHARING
+DEFINES_APP += -DMAX_BOOT_RECORD_SZ=512
+DEFINES_APP += -DMCUBOOT_SHARED_DATA_BASE=0x08000800
+DEFINES_APP += -DMCUBOOT_SHARED_DATA_SIZE=0x200
+endif
+
+ifeq ($(BOOT_RECORD_SW_TYPE), )
+BOOT_RECORD := --boot-record MCUBootApp
+else
+BOOT_RECORD := --boot-record $(BOOT_RECORD_SW_TYPE)
+endif
# Collect MCUBoot sourses
SOURCES_MCUBOOT := $(wildcard $(PRJ_DIR)/../bootutil/src/*.c)
# Collect MCUBoot Application sources
-SOURCES_APP_SRC := main.c cy_security_cnt.c keys.c
+SOURCES_APP_SRC := main.c keys.c
+ifeq ($(USE_EXEC_TIME_CHECK), 1)
+DEFINES_APP += -DUSE_EXEC_TIME_CHECK=1
+SOURCES_APP_SRC += misc/timebase_us.c
+endif
# Collect Flash Layer sources and header files dirs
INCLUDE_DIRS_FLASH := $(PLATFORM_INCLUDE_DIRS_FLASH)
@@ -182,28 +224,29 @@
# Print debug information about all settings used and/or set in this file
ifeq ($(VERBOSE), 1)
$(info #### MCUBootApp.mk ####)
+$(info APP_CORE <-- $(APP_CORE))
$(info APP_DEFAULT_POLICY --> $(APP_DEFAULT_POLICY))
$(info APP_NAME <-> $(APP_NAME))
$(info ASM_FILES_APP --> $(ASM_FILES_APP))
$(info ASM_FILES_STARTUP <-- $(ASM_FILES_STARTUP))
-$(info BOOTLOADER_SIZE <-> $(BOOTLOADER_SIZE))
+$(info BOOTLOADER_SIZE <-- $(BOOTLOADER_SIZE))
+$(info BOOT_RECORD --> $(BOOT_RECORD))
+$(info BOOT_RECORD_SW_TYPE <-- $(BOOT_RECORD_SW_TYPE))
$(info BUILDCFG <-- $(BUILDCFG))
$(info CFLAGS_OPTIMIZATION --> $(CFLAGS_OPTIMIZATION))
$(info COMPILER <-> $(COMPILER))
$(info CORE <-- $(CORE))
$(info CUR_APP_PATH <-- $(CUR_APP_PATH))
+$(info CY_LIBS_PATH <-- $(CY_LIBS_PATH))
$(info DEFINES_APP --> $(DEFINES_APP))
$(info ENC_IMG <-> $(ENC_IMG))
-$(info EXTERNAL_FLASH_PRIMARY_2_OFFSET <-> $(EXTERNAL_FLASH_PRIMARY_2_OFFSET))
-$(info EXTERNAL_FLASH_SCRATCH_OFFSET <-> $(EXTERNAL_FLASH_SCRATCH_OFFSET))
-$(info EXTERNAL_FLASH_SECONDARY_1_OFFSET <-> $(EXTERNAL_FLASH_SECONDARY_1_OFFSET))
-$(info EXTERNAL_FLASH_SECONDARY_2_OFFSET <-> $(EXTERNAL_FLASH_SECONDARY_2_OFFSET))
$(info FLASH_MAP <-- $(FLASH_MAP))
-$(info IMAGE_1_SLOT_SIZE <-> $(IMAGE_1_SLOT_SIZE))
-$(info IMAGE_2_SLOT_SIZE <-> $(IMAGE_2_SLOT_SIZE))
$(info INCLUDE_DIRS_APP --> $(INCLUDE_DIRS_APP))
$(info INCLUDE_DIRS_FLASH <-> $(INCLUDE_DIRS_FLASH))
+$(info INCLUDE_DIRS_LIBS --> $(INCLUDE_DIRS_LIBS))
+$(info INCLUDE_DIRS_MBEDTLS_MXCRYPTO <-> $(INCLUDE_DIRS_MBEDTLS_MXCRYPTO))
$(info INCLUDE_DIRS_MCUBOOT --> $(INCLUDE_DIRS_MCUBOOT))
+$(info INCLUDE_DIRS_UTILS <-> $(INCLUDE_DIRS_UTILS))
$(info LDFLAGS --> $(LDFLAGS))
$(info LDFLAGS_DEFSYM <-> $(LDFLAGS_DEFSYM))
$(info LINKER_SCRIPT --> $(LINKER_SCRIPT))
@@ -216,39 +259,35 @@
$(info PLATFORM <-- $(PLATFORM))
$(info PLATFORM_APP_DEFAULT_POLICY <-- $(PLATFORM_APP_DEFAULT_POLICY))
$(info PLATFORM_APP_SOURCES <-- $(PLATFORM_APP_SOURCES))
-$(info PLATFORM_BOOTLOADER_SIZE <-- $(PLATFORM_BOOTLOADER_SIZE))
-$(info PLATFORM_CHUNK_SIZE <-- $(PLATFORM_CHUNK_SIZE))
$(info PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE <-- $(PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE))
-$(info PLATFORM_EXTERNAL_FLASH_PRIMARY_2_OFFSET <-- $(PLATFORM_EXTERNAL_FLASH_PRIMARY_2_OFFSET))
-$(info PLATFORM_EXTERNAL_FLASH_SCRATCH_OFFSET <-- $(PLATFORM_EXTERNAL_FLASH_SCRATCH_OFFSET))
-$(info PLATFORM_EXTERNAL_FLASH_SECONDARY_1_OFFSET <-- $(PLATFORM_EXTERNAL_FLASH_SECONDARY_1_OFFSET))
-$(info PLATFORM_EXTERNAL_FLASH_SECONDARY_2_OFFSET <-- $(PLATFORM_EXTERNAL_FLASH_SECONDARY_2_OFFSET))
-$(info PLATFORM_IMAGE_1_SLOT_SIZE <-- $(PLATFORM_IMAGE_1_SLOT_SIZE))
-$(info PLATFORM_IMAGE_2_SLOT_SIZE <-- $(PLATFORM_IMAGE_2_SLOT_SIZE))
$(info PLATFORM_INCLUDE_DIRS_FLASH <-- $(PLATFORM_INCLUDE_DIRS_FLASH))
+$(info PLATFORM_INCLUDE_DIRS_UTILS <-- $(PLATFORM_INCLUDE_DIRS_UTILS))
$(info PLATFORM_MAX_IMG_SECTORS <-- $(PLATFORM_MAX_IMG_SECTORS))
-$(info PLATFORM_SCRATCH_SIZE <-- $(PLATFORM_SCRATCH_SIZE))
$(info PLATFORM_SERVICE_APP_DESC_OFFSET <-- $(PLATFORM_SERVICE_APP_DESC_OFFSET))
$(info PLATFORM_SERVICE_APP_INPUT_PARAMS_OFFSET <-- $(PLATFORM_SERVICE_APP_INPUT_PARAMS_OFFSET))
$(info PLATFORM_SERVICE_APP_OFFSET <-- $(PLATFORM_SERVICE_APP_OFFSET))
$(info PLATFORM_SERVICE_APP_SIZE <-- $(PLATFORM_SERVICE_APP_SIZE))
$(info PLATFORM_SOURCES_FLASH <-- $(PLATFORM_SOURCES_FLASH))
-$(info PLATFORM_STATUS_PARTITION_OFFSET <-- $(PLATFORM_STATUS_PARTITION_OFFSET))
$(info PRJ_DIR <-- $(PRJ_DIR))
$(info PYTHON_PATH <-- $(PYTHON_PATH))
-$(info SCRATCH_SIZE <-> $(SCRATCH_SIZE))
$(info SIGN_KEY_FILE <-- $(SIGN_KEY_FILE))
$(info SOURCES_APP --> $(SOURCES_APP))
$(info SOURCES_APP_SRC <-> $(SOURCES_APP_SRC))
$(info SOURCES_FLASH <-> $(SOURCES_FLASH))
+$(info SOURCES_LIBS --> $(SOURCES_LIBS))
+$(info SOURCES_MBEDTLS_MXCRYPTO <-> $(SOURCES_MBEDTLS_MXCRYPTO))
$(info SOURCES_MCUBOOT <-> $(SOURCES_MCUBOOT))
-$(info STATUS_PARTITION_OFFSET <-> $(STATUS_PARTITION_OFFSET))
$(info USE_BOOTSTRAP <-> $(USE_BOOTSTRAP))
$(info USE_CRYPTO_HW <-- $(USE_CRYPTO_HW))
$(info USE_CUSTOM_DEBUG_UART <-- $(USE_CUSTOM_DEBUG_UART))
-$(info USE_CUSTOM_MEMORY_MAP <-- $(USE_CUSTOM_MEMORY_MAP))
+$(info USE_DATA_SHARING <-- $(USE_DATA_SHARING))
+$(info USE_EXEC_TIME_CHECK <-- $(USE_EXEC_TIME_CHECK))
$(info USE_EXTERNAL_FLASH <-- $(USE_EXTERNAL_FLASH))
$(info USE_HW_ROLLBACK_PROT <-- $(USE_HW_ROLLBACK_PROT))
+$(info USE_LOG_TIMESTAMP <-- $(USE_LOG_TIMESTAMP))
+$(info USE_MEASURED_BOOT <-- $(USE_MEASURED_BOOT))
$(info USE_OVERWRITE <-- $(USE_OVERWRITE))
+$(info USE_SHARED_SLOT <-> $(USE_SHARED_SLOT))
+$(info USE_SW_DOWNGRADE_PREV <-- $(USE_SW_DOWNGRADE_PREV))
$(info USE_XIP <-- $(USE_XIP))
endif
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
index 9d9a32d..d721274 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
@@ -63,9 +63,9 @@
* Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
* where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.ld'.
*/
- ram (rwx) : ORIGIN = 0x08000800, LENGTH = 0x1F800
+ ram (rwx) : ORIGIN = 0x08000A00, LENGTH = 0x1F600
flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x17E90
- smif_struct (rx) : ORIGIN = 0x10017E90, LENGTH = 0x170
+ smif_struct (rx) : ORIGIN = 0x10017E90, LENGTH = 0x170
/* This is an unprotected public RAM region, with the placed .cy_sharedmem.
* This region is used to place objects that require full access from both cores.
@@ -74,6 +74,11 @@
*/
public_ram (rw) : ORIGIN = 0x08000000, LENGTH = 0x800
+ /* Shared data ram region.
+ * Used to store boot immage information in TLV format
+ */
+ shared_data_ram (rw) : ORIGIN = 0x08000800, LENGTH = 0x200
+
/* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
* You can assign sections to this memory region for only one of the cores.
* Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
@@ -336,6 +341,15 @@
} > public_ram
*/
+ .shared_ram (NOLOAD):
+ {
+ . = ALIGN(4);
+ __shared_ram_start__ = .;
+ KEEP(*(.shared_ram))
+ . = ALIGN(4);
+ __shared_ram_end__ = .;
+ } > shared_data_ram
+
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld
new file mode 100644
index 0000000..95b4b19
--- /dev/null
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld
@@ -0,0 +1,421 @@
+/***************************************************************************//**
+* \file cy8c6xx6_cm4.ld
+* \version 2.91
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM4 SRAM */
+STACK_SIZE = 0x1000;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+ /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+ * Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ */
+ ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x1F780
+ flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x80000
+
+ /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+ em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */
+
+ /* The following regions define device specific memory regions and must not be changed. */
+ sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */
+ sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */
+ sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */
+ sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */
+ sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */
+ xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */
+ efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ */
+
+
+SECTIONS
+{
+ /* Cortex-M4 application flash area */
+ .text :
+ {
+ /* Cortex-M4 flash vector table */
+ __Vectors = . ;
+ KEEP(*(.vectors))
+ . = ALIGN(4);
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ . = ALIGN(4);
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ /* Read-only code (constants). */
+ *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+
+ KEEP(*(.eh_frame*))
+ } > flash
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > flash
+
+ __exidx_start = .;
+
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+
+ /* Copy interrupt vectors from flash to RAM */
+ LONG (__Vectors) /* From */
+ LONG (__ram_vectors_start__) /* To */
+ LONG (__Vectors_End - __Vectors) /* Size */
+
+ /* Copy data section to RAM */
+ LONG (__etext) /* From */
+ LONG (__data_start__) /* To */
+ LONG (__data_end__ - __data_start__) /* Size */
+
+ __copy_table_end__ = .;
+ } > flash
+
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ __zero_table_end__ = .;
+ } > flash
+
+ __etext = . ;
+
+
+ .ramVectors (NOLOAD) : ALIGN(8)
+ {
+ __ram_vectors_start__ = .;
+ KEEP(*(.ram_vectors))
+ __ram_vectors_end__ = .;
+ } > ram
+
+
+ .data __ram_vectors_end__ :
+ {
+ . = ALIGN(4);
+ __data_start__ = .;
+
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+
+ KEEP(*(.cy_ramfunc*))
+ . = ALIGN(4);
+
+ __data_end__ = .;
+
+ } > ram AT>flash
+
+
+ /* Place variables in the section that should not be initialized during the
+ * device startup.
+ */
+ .noinit (NOLOAD) : ALIGN(8)
+ {
+ KEEP(*(.noinit))
+ } > ram
+
+
+ /* The uninitialized global or static variables are placed in this section.
+ *
+ * The NOLOAD attribute tells linker that .bss section does not consume
+ * any space in the image. The NOLOAD attribute changes the .bss type to
+ * NOBITS, and that makes linker to A) not allocate section in memory, and
+ * A) put information to clear the section with all zeros during application
+ * loading.
+ *
+ * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+ * This makes linker to A) allocate zeroed section in memory, and B) copy
+ * this section to RAM during application loading.
+ */
+ .bss (NOLOAD):
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > ram
+
+
+ .heap (NOLOAD):
+ {
+ __HeapBase = .;
+ __end__ = .;
+ end = __end__;
+ KEEP(*(.heap*))
+ . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+ __HeapLimit = .;
+ } > ram
+
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (NOLOAD):
+ {
+ KEEP(*(.stack*))
+ } > ram
+
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(ram) + LENGTH(ram);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+ /* Used for the digital signature of the secure application and the Bootloader SDK application.
+ * The size of the section depends on the required data size. */
+ .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+ {
+ KEEP(*(.cy_app_signature))
+ } > flash
+
+
+ /* Emulated EEPROM Flash area */
+ .cy_em_eeprom :
+ {
+ KEEP(*(.cy_em_eeprom))
+ } > em_eeprom
+
+
+ /* Supervisory Flash: User data */
+ .cy_sflash_user_data :
+ {
+ KEEP(*(.cy_sflash_user_data))
+ } > sflash_user_data
+
+
+ /* Supervisory Flash: Normal Access Restrictions (NAR) */
+ .cy_sflash_nar :
+ {
+ KEEP(*(.cy_sflash_nar))
+ } > sflash_nar
+
+
+ /* Supervisory Flash: Public Key */
+ .cy_sflash_public_key :
+ {
+ KEEP(*(.cy_sflash_public_key))
+ } > sflash_public_key
+
+
+ /* Supervisory Flash: Table of Content # 2 */
+ .cy_toc_part2 :
+ {
+ KEEP(*(.cy_toc_part2))
+ } > sflash_toc_2
+
+
+ /* Supervisory Flash: Table of Content # 2 Copy */
+ .cy_rtoc_part2 :
+ {
+ KEEP(*(.cy_rtoc_part2))
+ } > sflash_rtoc_2
+
+
+ /* Places the code in the Execute in Place (XIP) section. See the smif driver
+ * documentation for details.
+ */
+ cy_xip :
+ {
+ __cy_xip_start = .;
+ KEEP(*(.cy_xip))
+ __cy_xip_end = .;
+ } > xip
+
+
+ /* eFuse */
+ .cy_efuse :
+ {
+ KEEP(*(.cy_efuse))
+ } > efuse
+
+
+ /* These sections are used for additional metadata (silicon revision,
+ * Silicon/JTAG ID, etc.) storage.
+ */
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start = 0x10000000;
+__cy_memory_0_length = 0x00080000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start = 0x14000000;
+__cy_memory_1_length = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start = 0x16000000;
+__cy_memory_2_length = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start = 0x18000000;
+__cy_memory_3_length = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start = 0x90700000;
+__cy_memory_4_length = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CYW20829_Debug.launch b/boot/cypress/MCUBootApp/MCUBootApp_CYW20829_Debug.launch
deleted file mode 100644
index 3b3300a..0000000
--- a/boot/cypress/MCUBootApp/MCUBootApp_CYW20829_Debug.launch
+++ /dev/null
@@ -1,59 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
- <stringAttribute key="com.cypress.studio.launch.mode" value="debug"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
- <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerConnectionAddress" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="/Users/rnok/Downloads/ASSETS/cyopenocd/openocd_4.3_1445/bin/openocd"/>
- <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerLog" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s "/Users/rnok/Downloads/ASSETS/cyopenocd/openocd_4.3_1445/scripts" -s "./libs/TARGET_PSVP-CYW20829/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource" -c "set SMIF_LOADER /Users/rnok/repos/cyw20829/AnyCloud_CYW20829_Blinky_App/./libs/TARGET_PSVP-CYW20829/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/CYW208xx_SMIF.FLM" -c "source [find interface/kitprog3.cfg]" -c "puts stderr {Started by GNU MCU Eclipse}" -c "source [find target/cyw208xx.cfg]" -c "cyw208xx.cm33 configure -rtos auto -rtos-wipe-on-reset-halt 1" -c "gdb_breakpoint_override hard" -c "init; reset init""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
- <intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="flushregs"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="init"/>
- <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${cy_prj_path}/build/PSVP-CYW20829/Debug/mtb-example-anycloud-blinky.bin"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
- <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="/Users/rnok/repos/cyw20829/cy_mcuboot/boot/cypress/MCUBootApp/out/CYW20829/Debug/MCUBootApp.elf"/>
- <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
- <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
- <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cy_tools_path:CY_TOOL_arm-none-eabi-gdb_EXE}"/>
- <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
- <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
- <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
- <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="/Users/rnok/repos/cyw20829/cy_mcuboot/boot/cypress/MCUBootApp/out/CYW20829/Debug/MCUBootApp.elf"/>
- <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="MCUBootApp_CYW20829_Debug"/>
- <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
- <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
- <listAttribute key="org.eclipse.debug.ui.favoriteGroups">
- <listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
- </listAttribute>
- <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/>
- <stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
-</launchConfiguration>
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
index 9869e33..c2d97d8 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
@@ -30,6 +30,26 @@
#include <stdbool.h>
#include <stdio.h>
+#include <stdarg.h>
+#include <inttypes.h>
+#include "timestamp.h"
+
+static inline void print_msg(char const *format, ...)
+{
+ va_list args;
+ va_start(args, format);
+
+#ifdef USE_LOG_TIMESTAMP
+ (void)fprintf(stderr, "[%03" PRIu32 "s"
+ ".%03" PRIu32 "ms]",
+ log_timestamp_get()/1000U,
+ log_timestamp_get()%1000U);
+#endif
+
+ (void)vfprintf(stderr, format, args);
+
+ va_end(args);
+}
#define MCUBOOT_LOG_LEVEL_OFF 0
#define MCUBOOT_LOG_LEVEL_ERROR 1
@@ -58,44 +78,44 @@
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_ERROR
-#define MCUBOOT_LOG_ERR(_fmt, ...) \
- do { \
- if (sim_log_enabled(MCUBOOT_LOG_LEVEL_ERROR) != 0) { \
- (void)fprintf(stderr, "[ERR] " _fmt "\n\r", ##__VA_ARGS__); \
- } \
+#define MCUBOOT_LOG_ERR(_fmt, ...) \
+ do { \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_ERROR) != 0) { \
+ print_msg("[ERR] " _fmt "\n\r", ##__VA_ARGS__); \
+ } \
} while ((bool)0)
#else
#define MCUBOOT_LOG_ERR(...) IGNORE(__VA_ARGS__)
#endif
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_WARNING
-#define MCUBOOT_LOG_WRN(_fmt, ...) \
- do { \
- if (sim_log_enabled(MCUBOOT_LOG_LEVEL_WARNING) != 0) { \
- (void)fprintf(stderr, "[WRN] " _fmt "\n\r", ##__VA_ARGS__); \
- } \
+#define MCUBOOT_LOG_WRN(_fmt, ...) \
+ do { \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_WARNING) != 0) { \
+ print_msg("[WRN] " _fmt "\n\r", ##__VA_ARGS__); \
+ } \
} while ((bool)0)
#else
#define MCUBOOT_LOG_WRN(...) IGNORE(__VA_ARGS__)
#endif
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_INFO
-#define MCUBOOT_LOG_INF(_fmt, ...) \
- do { \
- if (sim_log_enabled(MCUBOOT_LOG_LEVEL_INFO) != 0) { \
- (void)fprintf(stderr, "[INF] " _fmt "\n\r", ##__VA_ARGS__); \
- } \
+#define MCUBOOT_LOG_INF(_fmt, ...) \
+ do { \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_INFO) != 0) { \
+ print_msg("[INF] " _fmt "\n\r", ##__VA_ARGS__); \
+ } \
} while ((bool)0)
#else
#define MCUBOOT_LOG_INF(...) IGNORE(__VA_ARGS__)
#endif
#if MCUBOOT_LOG_LEVEL >= MCUBOOT_LOG_LEVEL_DEBUG
-#define MCUBOOT_LOG_DBG(_fmt, ...) \
- do { \
- if (sim_log_enabled(MCUBOOT_LOG_LEVEL_DEBUG) != 0) { \
- (void)fprintf(stderr, "[DBG] " _fmt "\n\r", ##__VA_ARGS__); \
- } \
+#define MCUBOOT_LOG_DBG(_fmt, ...) \
+ do { \
+ if (sim_log_enabled(MCUBOOT_LOG_LEVEL_DEBUG) != 0) { \
+ print_msg("[DBG] " _fmt "\n\r", ##__VA_ARGS__); \
+ } \
} while ((bool)0)
#else
#define MCUBOOT_LOG_DBG(...) IGNORE(__VA_ARGS__)
diff --git a/boot/cypress/MCUBootApp/libs.mk b/boot/cypress/MCUBootApp/libs.mk
index da58c88..24bd642 100644
--- a/boot/cypress/MCUBootApp/libs.mk
+++ b/boot/cypress/MCUBootApp/libs.mk
@@ -62,6 +62,12 @@
INCLUDE_DIRS_WATCHDOG := $(THIS_APP_PATH)/watchdog
# MbedTLS related include directories
+ifeq ($(USE_CRYPTO_HW), 1)
+ifeq ($(PLATFORM), CYW20829)
+# Override mbedtls/compat-2.x.h for Cryptolite CBUS workaround
+INCLUDE_DIRS_MBEDTLS += $(PRJ_DIR)/platforms/crypto/CYW20829
+endif
+endif
INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include
INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include/mbedtls
INCLUDE_DIRS_MBEDTLS += $(MBEDTLS_PATH)/mbedtls/include/psa
@@ -85,6 +91,7 @@
$(info INCLUDE_DIRS_WATCHDOG <-> $(INCLUDE_DIRS_WATCHDOG))
$(info INCLUDE_RETARGET_IO_PDL <-> $(INCLUDE_RETARGET_IO_PDL))
$(info MBEDTLS_PATH <-- $(MBEDTLS_PATH))
+$(info PLATFORM <-- $(PLATFORM))
$(info PLATFORM_INCLUDE_DIRS_HAL_MCUB <-- $(PLATFORM_INCLUDE_DIRS_HAL_MCUB))
$(info PLATFORM_INCLUDE_RETARGET_IO_PDL <-- $(PLATFORM_INCLUDE_RETARGET_IO_PDL))
$(info PLATFORM_SOURCES_HAL_MCUB <-- $(PLATFORM_SOURCES_HAL_MCUB))
@@ -96,4 +103,5 @@
$(info SOURCES_RETARGET_IO_PDL <-> $(SOURCES_RETARGET_IO_PDL))
$(info SOURCES_WATCHDOG <-> $(SOURCES_WATCHDOG))
$(info THIS_APP_PATH <-- $(THIS_APP_PATH))
+$(info USE_CRYPTO_HW <-- $(USE_CRYPTO_HW))
endif
diff --git a/boot/cypress/MCUBootApp/main.c b/boot/cypress/MCUBootApp/main.c
index 6097173..b54e7e5 100644
--- a/boot/cypress/MCUBootApp/main.c
+++ b/boot/cypress/MCUBootApp/main.c
@@ -27,15 +27,20 @@
#include "cy_retarget_io.h"
#include "cybsp.h"
#include "cyhal_wdt.h"
-#include "cyw_20829_utils.h"
+#include "cyw_platform_utils.h"
#include "cy_service_app.h"
#else
#include "cy_retarget_io_pdl.h"
#include "cycfg_clocks.h"
#include "cycfg_peripherals.h"
-#endif /* CYW20829 */
+#if defined APP_CM0P || defined CM4
+#include "cyw_platform_utils.h"
+#endif /* defined APP_CM0P || defined CM4 */
+#endif /* defined CYW20829 || defined EXPLORER */
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829)
#include "flash_qspi.h"
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829) */
#include "cycfg_pins.h"
#include "cy_result.h"
@@ -52,6 +57,15 @@
#include "watchdog.h"
+#ifdef USE_EXEC_TIME_CHECK
+#include "misc/timebase_us.h"
+#include "misc/exec_time_check.h"
+#endif /* USE_EXEC_TIME_CHECK */
+
+#ifdef USE_LOG_TIMESTAMP
+#include "timestamp.h"
+#endif /* USE_LOG_TIMESTAMP */
+
#define CY_RSLT_MODULE_MCUBOOTAPP 0x500U
#define CY_RSLT_MODULE_MCUBOOTAPP_MAIN 0x51U
@@ -97,7 +111,7 @@
#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
qspi_deinit(SMIF_ID);
#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
- cyw20829_RunApp(app_addr, key, iv);
+ platform_RunNextApp(app_addr, key, iv);
}
#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP)
CY_RAMFUNC_END /* SMIF will be deinitialized in this case! */
@@ -141,22 +155,53 @@
return false;
}
#endif /* MCUBOOT_ENC_IMAGES_XIP */
+
+
+#ifdef APP_CM33
/* This function does not return */
+ BOOT_LOG_INF("Launching app on CM33 core");
BOOT_LOG_INF(BOOT_MSG_FINISH);
hw_deinit();
cyw20829_launch_app(app_addr, key, iv);
#else
- /* This function turns on CM4 and returns */
- BOOT_LOG_INF(BOOT_MSG_FINISH);
+#error "Application should run on Cortex-M33"
+#endif /* APP_CM33 */
- hw_deinit();
+#else /* defined CYW20829 || defined EXPLORER */
+
#ifdef USE_XIP
BOOT_LOG_DBG("XIP: Switch to SMIF XIP mode");
qspi_set_mode(CY_SMIF_MEMORY);
-#endif
+#endif /* USE_XIP */
+
+#ifdef APP_CM4
+ /* This function turns on CM4 and returns */
+ BOOT_LOG_INF("Launching app on CM4 core");
+ BOOT_LOG_INF(BOOT_MSG_FINISH);
+ hw_deinit();
+#ifdef CM0P
Cy_SysEnableCM4(fih_uint_decode(app_addr));
return true;
-#endif /* CYW20829 */
+#else
+ psoc6_launch_cm4_app(app_addr);
+#endif /* CM0P */
+
+#elif defined APP_CM0P
+#ifdef CM0P
+ /* This function does not return */
+ BOOT_LOG_INF("Launching app on CM0P core");
+ BOOT_LOG_INF(BOOT_MSG_FINISH);
+ hw_deinit();
+ psoc6_launch_cm0p_app(app_addr);
+#else
+#error "Application should run on Cortex-M4"
+#endif /* CM0P */
+
+#else
+#error "Application should run on either Cortex-M0+ or Cortex-M4"
+#endif /* APP_CM4 */
+
+#endif /* defined CYW20829 */
} else {
BOOT_LOG_ERR("Flash device ID not found");
return false;
@@ -187,6 +232,15 @@
init_cycfg_peripherals();
init_cycfg_pins();
#endif /* CYW20829 */
+
+#ifdef USE_EXEC_TIME_CHECK
+ timebase_us_init();
+#endif /* USE_EXEC_TIME_CHECK */
+
+#ifdef USE_LOG_TIMESTAMP
+ log_timestamp_init();
+#endif /* USE_LOG_TIMESTAMP */
+
/* enable interrupts */
__enable_irq();
@@ -197,13 +251,12 @@
* to keep CM4 disabled. Note that debugging of CM4 is not supported when it
* is disabled.
*/
-#ifndef CYW20829
-#if defined(CY_DEVICE_PSOC6ABLE2)
+#if !defined CYW20829
+#if defined(CY_DEVICE_PSOC6ABLE2) && !defined(CM4)
if (CY_SYS_CM4_STATUS_ENABLED == Cy_SysGetCM4Status()) {
Cy_SysDisableCM4();
}
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) && !defined(CM4) */
/* Initialize retarget-io to use the debug UART port (CYBSP_UART_HW) */
rc = cy_retarget_io_pdl_init(CY_RETARGET_IO_BAUDRATE);
#else
@@ -251,7 +304,17 @@
#endif /* CYW20829 && MCUBOOT_HW_ROLLBACK_PROT */
(void)memset(&rsp, 0, sizeof(rsp));
- FIH_CALL(boot_go, fih_rc, &rsp);
+#ifdef USE_EXEC_TIME_CHECK
+ {
+ uint32_t exec_time;
+ EXEC_TIME_CHECK_BEGIN(&exec_time);
+#endif /* USE_EXEC_TIME_CHECK */
+ FIH_CALL(boot_go, fih_rc, &rsp);
+#ifdef USE_EXEC_TIME_CHECK
+ EXEC_TIME_CHECK_END();
+ BOOT_LOG_INF("Exec time: %" PRIu32 " [ms]", exec_time / 1000U);
+ }
+#endif /* USE_EXEC_TIME_CHECK */
if (true == fih_eq(fih_rc, FIH_SUCCESS)) {
BOOT_LOG_INF("User Application validated successfully");
/* initialize watchdog timer. it should be updated from user app
@@ -309,4 +372,12 @@
qspi_deinit(SMIF_ID);
#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && !defined(MCUBOOT_ENC_IMAGES_XIP) */
#endif /* CYW20829 */
+
+#ifdef USE_EXEC_TIME_CHECK
+ timebase_us_deinit();
+#endif /* USE_EXEC_TIME_CHECK */
+
+#ifdef USE_LOG_TIMESTAMP
+ log_timestamp_deinit();
+#endif /* USE_LOG_TIMESTAMP */
}
diff --git a/boot/cypress/MCUBootApp/misc/exec_time_check.h b/boot/cypress/MCUBootApp/misc/exec_time_check.h
new file mode 100644
index 0000000..55d71f2
--- /dev/null
+++ b/boot/cypress/MCUBootApp/misc/exec_time_check.h
@@ -0,0 +1,56 @@
+/* Copyright 2022, Infineon Technologies AG. All rights reserved.
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef EXEC_TIME_CHECK_H
+#define EXEC_TIME_CHECK_H
+
+#include "timebase_us.h"
+
+/*******************************************************************************
+* Macro Definition: EXEC_TIME_CHECK_BEGIN
+* Macro Definition: EXEC_TIME_CHECK_END
+****************************************************************************//**
+*
+* \param result
+* Execution time result in micro seconds. Shall be declared as 32 bit.
+*
+* \funcusage
+* {
+* uint32_t time;
+*
+* EXEC_TIME_CHECK_BEGIN(&time);
+* CyDelayUs(1000);
+* EXEC_TIME_CHECK_END();
+*
+* printf("%"PRIu32"\n", time);
+* }
+*
+*******************************************************************************/
+#define EXEC_TIME_CHECK_BEGIN(result) \
+ do { \
+ uint32_t* const exec_check_res = (result); \
+ uint32_t exec_check_start = timebase_us_get_tick()
+
+#define EXEC_TIME_CHECK_END() \
+ *exec_check_res = timebase_us_get_tick() - exec_check_start; \
+ } while(false)
+
+
+#endif /* EXEC_TIME_CHECK_H */
\ No newline at end of file
diff --git a/boot/cypress/MCUBootApp/misc/timebase_us.c b/boot/cypress/MCUBootApp/misc/timebase_us.c
new file mode 100644
index 0000000..dfe2ffd
--- /dev/null
+++ b/boot/cypress/MCUBootApp/misc/timebase_us.c
@@ -0,0 +1,99 @@
+/* Copyright 2022, Infineon Technologies AG. All rights reserved.
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include "timebase_us.h"
+
+#include "cy_pdl.h"
+#include "bootutil/bootutil_log.h"
+
+static const cy_stc_tcpwm_counter_config_t tcpwm_config =
+{
+ .period = 0xFFFFFFFFU,
+ .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_8, /* Clk_counter = Clk_input / 4 */
+ .runMode = CY_TCPWM_COUNTER_CONTINUOUS, /* Wrap around at terminal count. */
+ .countDirection = CY_TCPWM_COUNTER_COUNT_UP, /* Up counter, counting from 0 to period value. */
+ .compareOrCapture = CY_TCPWM_COUNTER_MODE_COMPARE, /* Trigger interrupt/event signal when Counter value is equal to Compare0 */
+ .compare0 = 0U,
+ .compare1 = 0U,
+ .enableCompareSwap = false,
+ .interruptSources = CY_TCPWM_INT_NONE,
+ .captureInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_RISINGEDGE = 0UL) */
+ .captureInput = CY_TCPWM_INPUT_0,
+ .reloadInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_RISINGEDGE = 0UL) */
+ .reloadInput = CY_TCPWM_INPUT_0,
+ .startInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_RISINGEDGE = 0UL) */
+ .startInput = CY_TCPWM_INPUT_0,
+ .stopInputMode = CY_TCPWM_INPUT_RISINGEDGE, /* This input is NOT used, leave it in default state (CY_TCPWM_INPUT_RISINGEDGE = 0UL) */
+ .stopInput = CY_TCPWM_INPUT_0,
+ .countInputMode = CY_TCPWM_INPUT_LEVEL, /* Set this input to LEVEL and 1 (high logic level) */
+ .countInput = CY_TCPWM_INPUT_1 /* So the counter will count input clock periods (Clk_counter, taking into account the clock prescaler) */
+};
+
+/*******************************************************************************
+* Function Name: timebase_us_init
+****************************************************************************//**
+*
+* \brief Performs initialization of the TCPWM0 block as a microsecond time source.
+*
+*/
+void timebase_us_init(void)
+{
+#ifdef CYW20829
+ (void) Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN0, CY_SYSCLK_DIV_8_BIT, 0UL);
+#else
+ (void) Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 0UL);
+#endif
+ (void) Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0UL, 0UL);
+ (void) Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0UL);
+
+ (void) Cy_TCPWM_Counter_Init(TCPWM0, 0, &tcpwm_config);
+ Cy_TCPWM_Counter_Enable(TCPWM0, 0);
+ Cy_TCPWM_TriggerStart_Single(TCPWM0, 0);
+}
+
+/*******************************************************************************
+* Function Name: timebase_us_deinit
+****************************************************************************//**
+*
+* \brief Performs deinitialization of the TCPWM0.
+*
+*/
+void timebase_us_deinit(void)
+{
+ (void) Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0UL);
+
+ Cy_TCPWM_Counter_DeInit(TCPWM0, 0, &tcpwm_config);
+ Cy_TCPWM_Counter_Disable(TCPWM0, 0);
+ Cy_TCPWM_TriggerStopOrKill_Single(TCPWM0, 0);
+}
+
+/*******************************************************************************
+* Function Name: timebase_us_get_tick
+****************************************************************************//**
+*
+* \brief Returns current timer counter value
+*
+* \return current timer counter value as uint32_t
+*
+*/
+uint32_t timebase_us_get_tick(void)
+{
+ return Cy_TCPWM_Counter_GetCounter(TCPWM0, 0);
+}
\ No newline at end of file
diff --git a/boot/cypress/MCUBootApp/misc/timebase_us.h b/boot/cypress/MCUBootApp/misc/timebase_us.h
new file mode 100644
index 0000000..79d1482
--- /dev/null
+++ b/boot/cypress/MCUBootApp/misc/timebase_us.h
@@ -0,0 +1,30 @@
+/* Copyright 2022, Infineon Technologies AG. All rights reserved.
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef TIMEBASE_US_H
+#define TIMEBASE_US_H
+
+#include <inttypes.h>
+
+void timebase_us_init(void);
+void timebase_us_deinit(void);
+uint32_t timebase_us_get_tick(void);
+
+#endif /* TIMEBASE_US_H */
\ No newline at end of file
diff --git a/boot/cypress/MCUBootApp/timestamp.h b/boot/cypress/MCUBootApp/timestamp.h
new file mode 100644
index 0000000..afd6460
--- /dev/null
+++ b/boot/cypress/MCUBootApp/timestamp.h
@@ -0,0 +1,74 @@
+/* Copyright 2022, Infineon Technologies AG. All rights reserved.
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef TIMESTAMP_H
+#define TIMESTAMP_H
+
+#include "cy_pdl.h"
+
+#define TIMESTAMP_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_LF
+#define TIMESTAMP_DIVIDER (CY_SYSCLK_ILO_FREQ / 1000UL)
+
+/*******************************************************************************
+* Function Name: log_timestamp_get
+****************************************************************************//**
+*
+* \brief Get current timestamp counter value.
+*
+* \return Systic counter as timestamp reference.
+*/
+static inline uint32_t log_timestamp_get(void) {
+ return ((0x1000000UL - Cy_SysTick_GetValue()) / TIMESTAMP_DIVIDER);
+}
+
+/*******************************************************************************
+* Function Name: log_timestamp_reset
+****************************************************************************//**
+*
+* \brief Reset timestamp counter.
+*/
+static inline void log_timestamp_reset(void) {
+ Cy_SysTick_Init(TIMESTAMP_SOURCE, 0xFFFFFFu);
+ Cy_SysTick_DisableInterrupt();
+}
+
+/*******************************************************************************
+* Function Name: log_timestamp_init
+****************************************************************************//**
+*
+* \brief Initializate timestamp counter and SysTick timebase.
+*/
+static inline void log_timestamp_init(void) {
+ log_timestamp_reset();
+ Cy_SysTick_Clear();
+}
+
+/*******************************************************************************
+* Function Name: log_timestamp_deinit
+****************************************************************************//**
+*
+* \brief Deinitializate timestamp counter and SysTick timebase.
+*/
+static inline void log_timestamp_deinit(void) {
+ Cy_SysTick_Disable();
+ Cy_SysTick_Clear();
+}
+
+#endif /* TIMESTAMP_H */
diff --git a/boot/cypress/Makefile b/boot/cypress/Makefile
index d1c9b00..0f0a378 100644
--- a/boot/cypress/Makefile
+++ b/boot/cypress/Makefile
@@ -56,11 +56,6 @@
BUILDCFG ?= Debug
-ifeq ($(PLATFORM), CYW20829)
-# until mbedtls.3.0 support
-USE_CRYPTO_HW ?= 0
-endif
-
# Set of supported applications
APPS := MCUBootApp BlinkyApp
@@ -213,7 +208,7 @@
clean:
@echo "Cleanup out directory..."
- rm -f ./$(APP_NAME)/flashmap.mk ./cy_flash_pal/cy_flash_map.h
+ rm -f ./$(APP_NAME)/flashmap.mk ./platforms/cy_flash_pal/cy_flash_map.h
rm -rf $(OUT_TARGET)/$(BUILDCFG)
clean_boot:
@@ -292,6 +287,5 @@
$(info SOURCES_LIBS <-- $(SOURCES_LIBS))
$(info SOURCES_PLATFORM <-- $(SOURCES_PLATFORM))
$(info THREADS_NUM <-> $(THREADS_NUM))
-$(info USE_CRYPTO_HW --> $(USE_CRYPTO_HW))
$(info WARN_AS_ERR <-> $(WARN_AS_ERR))
endif
diff --git a/boot/cypress/README.md b/boot/cypress/README.md
index 8227da6..fb9d8ee 100644
--- a/boot/cypress/README.md
+++ b/boot/cypress/README.md
@@ -71,12 +71,16 @@
**GCC_ARM** is only supported (built and verified on GCC 9.3.1).
-It is included with [ModusToolbox™ Software Environment](https://www.cypress.com/products/modustoolbox) and can be found in folder `./ModusToolbox/tools_2.4/gcc`.
+It is included with [ModusToolbox™ Software Environment](https://www.cypress.com/products/modustoolbox).
The default installation folder is expected by the makefile build system.
To use another installation folder, version of **ModusToolbox™ IDE** or another GCC Compiler, specify the path to a toolchain using the **TOOLCHAIN_PATH** parameter.
+Below is an example on how to set toolchin path to the latest include with **ModusToolbox™ IDE 3.0**:
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/$(USERNAME)/ModusToolbox/tools_3.0/gcc
+
### Build environment troubleshooting
The following CLI/IDE are supported for project build:
diff --git a/boot/cypress/common_libs.mk b/boot/cypress/common_libs.mk
index d380107..954d385 100644
--- a/boot/cypress/common_libs.mk
+++ b/boot/cypress/common_libs.mk
@@ -34,7 +34,7 @@
SOURCES_PDL := $(wildcard $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/source/*.c)
SOURCES_PDL += $(wildcard $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/*.c)
-COMPONENT_CORE_PATH := $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/templates/COMPONENT_MTB/COMPONENT_$(CORE)
+COMPONENT_CORE_PATH := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)
# PDL startup related files
SYSTEM_FILE_NAME := $(PLATFORM_SYSTEM_FILE_NAME)
@@ -48,16 +48,18 @@
SOURCES_HAL := $(PLATFORM_SOURCES_HAL)
# Add platform folder to build
-SOURCES_PLATFORM := $(wildcard $(PRJ_DIR)/platforms/$(FAMILY)/*.c)
-SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/$(FAMILY)/secure/*.c)
+SOURCES_PLATFORM := $(wildcard $(PRJ_DIR)/platforms/BSP/$(FAMILY)/*.c)
+SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/security_counter/*.c)
+SOURCES_PLATFORM += $(wildcard $(PRJ_DIR)/platforms/security_counter/$(FAMILY)/*.c)
# PDL related include directories
INCLUDE_DIRS_PDL := $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/include
INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include/ip
INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/include
-INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/cmsis/include
INCLUDE_DIRS_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/templates/COMPONENT_MTB
+INCLUDE_DIRS_CMSIS += $(CY_LIBS_PATH)/cmsis/Core/Include
+
# core-libs related include directories
INCLUDE_DIRS_CORE_LIB := $(CY_LIBS_PATH)/core-lib/include
@@ -71,8 +73,10 @@
INCLUDE_DIRS_HAL := $(PLATFORM_INCLUDE_DIRS_HAL)
# Include platforms folder
-INCLUDE_DIRS_PLATFORM := $(PRJ_DIR)/platforms/$(FAMILY)
-INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/$(FAMILY)/secure
+INCLUDE_DIRS_PLATFORM := $(PRJ_DIR)/platforms//BSP/$(FAMILY)
+INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/security_counter/$(FAMILY)
+INCLUDE_DIRS_PLATFORM += $(PRJ_DIR)/platforms/security_counter
+INCLUDE_DIRS_PLATFORM += $(PLATFORM_INCLUDE_DIRS_PDL_STARTUP)
# Assembler startup file for platform
ASM_FILES_STARTUP := $(PLATFORM_STARTUP_FILE)
@@ -87,6 +91,7 @@
# Collected include directories for libraries
INCLUDE_DIRS_LIBS := $(addprefix -I,$(INCLUDE_DIRS_PDL))
+INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_CMSIS))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_PDL_STARTUP))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_CORE_LIB))
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_HAL))
@@ -94,7 +99,7 @@
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_RETARGET_IO))
# Syslib files
-ASM_FILES_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S
+ASM_FILES_PDL += $(CY_LIBS_PATH)/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S
ASM_FILES_LIBS := $(ASM_FILES_PDL)
diff --git a/boot/cypress/coverity/all_files/cert-c-custom.config b/boot/cypress/coverity/all_files/cert-c-custom.config
deleted file mode 100644
index 8443bef..0000000
--- a/boot/cypress/coverity/all_files/cert-c-custom.config
+++ /dev/null
@@ -1,8 +0,0 @@
-{
- "version": "2.0",
- "standard": "cert-c",
- "title": "CERT-C All Rules",
- "deviations": [
-
- ]
-}
diff --git a/boot/cypress/coverity/all_files/config_mcuboot_cert_c.json b/boot/cypress/coverity/all_files/config_mcuboot_cert_c.json
deleted file mode 100644
index c0d4834..0000000
--- a/boot/cypress/coverity/all_files/config_mcuboot_cert_c.json
+++ /dev/null
@@ -1,34 +0,0 @@
-{
- "script_config":{
- "coding_standard":"CERT C",
- "log_file":".\\coverity.log",
- "coverity_path":"C:\\Program Files\\Coverity\\Coverity Static Analysis\\bin",
- "report_to_testrail":false,
- "report_to_coverity_server":false,
- "project_source_path":".\\..\\..\\boot\\cypress",
- "deviations_config":".\\..\\..\\boot\\cypress\\coverity\\all_files\\cert-c-custom.config",
- "build_cmd":"make clean app POST_BUILD_ENABLE=0 APP_NAME=MCUBootApp PLATFORM=CYW20829",
- "manual_clean":true,
- "fail_condition":1
- },
- "coverity_config":{
- "coverity_project_name":"mcuboot",
- "coverity_stream_name":"develop",
- "analyze_options":[
- "--all"
- ],
- "compiler_type":"gcc",
- "compiler":"arm-none-eabi-gcc",
- "enable_checkers":[
- "ENUM_AS_BOOLEAN",
- "HFA"
- ],
- "disable_checkers":[
- "SECURE_CODING",
- "MISRA_CAST"
- ],
- "source_filter":[
-
- ]
- }
-}
diff --git a/boot/cypress/coverity/all_files/config_mcuboot_misra.json b/boot/cypress/coverity/all_files/config_mcuboot_misra.json
deleted file mode 100644
index 0dc6702..0000000
--- a/boot/cypress/coverity/all_files/config_mcuboot_misra.json
+++ /dev/null
@@ -1,33 +0,0 @@
-{
- "script_config":{
- "coding_standard":"MISRA",
- "log_file":".\\coverity.log",
- "coverity_path":"C:\\Program Files\\Coverity\\Coverity Static Analysis\\bin",
- "report_to_testrail":false,
- "report_to_coverity_server":false,
- "project_source_path":".\\..\\..\\boot\\cypress",
- "deviations_config":".\\..\\..\\boot\\cypress\\coverity\\all_files\\misrac2012_custom.config",
- "build_cmd":"make clean app POST_BUILD_ENABLE=0 APP_NAME=MCUBootApp PLATFORM=CYW20829",
- "manual_clean":true,
- "fail_condition":1
- },
- "coverity_config":{
- "coverity_project_name":"mcuboot",
- "coverity_stream_name":"develop",
- "analyze_options":[
- "--all"
- ],
- "compiler_type":"gcc",
- "compiler":"arm-none-eabi-gcc",
- "enable_checkers":[
- "ENUM_AS_BOOLEAN",
- "HFA"
- ],
- "disable_checkers":[
-
- ],
- "source_filter":[
-
- ]
- }
-}
diff --git a/boot/cypress/coverity/all_files/misrac2012_custom.config b/boot/cypress/coverity/all_files/misrac2012_custom.config
deleted file mode 100644
index 55d963e..0000000
--- a/boot/cypress/coverity/all_files/misrac2012_custom.config
+++ /dev/null
@@ -1,8 +0,0 @@
-{
- "version": "2.0",
- "standard": "misrac2012",
- "title": "MISRA C-2012 All Rules",
- "deviations": [
-
- ]
-}
diff --git a/boot/cypress/coverity/cyw20829/cert-c-custom.config b/boot/cypress/coverity/cyw20829/cert-c-custom.config
deleted file mode 100644
index 8443bef..0000000
--- a/boot/cypress/coverity/cyw20829/cert-c-custom.config
+++ /dev/null
@@ -1,8 +0,0 @@
-{
- "version": "2.0",
- "standard": "cert-c",
- "title": "CERT-C All Rules",
- "deviations": [
-
- ]
-}
diff --git a/boot/cypress/coverity/cyw20829/config_mcuboot_cert_c.json b/boot/cypress/coverity/cyw20829/config_mcuboot_cert_c.json
deleted file mode 100644
index 2229aa5..0000000
--- a/boot/cypress/coverity/cyw20829/config_mcuboot_cert_c.json
+++ /dev/null
@@ -1,578 +0,0 @@
-{
- "script_config":{
- "coding_standard":"CERT C",
- "log_file":".\\coverity.log",
- "coverity_path":"C:\\Program Files\\Coverity\\Coverity Static Analysis\\bin",
- "report_to_testrail":false,
- "report_to_coverity_server":false,
- "project_source_path":".\\..\\..\\boot\\cypress",
- "deviations_config":".\\..\\..\\boot\\cypress\\coverity\\cyw20829\\cert-c-custom.config",
- "build_cmd":"make clean app POST_BUILD_ENABLE=0 APP_NAME=MCUBootApp PLATFORM=CYW20829",
- "manual_clean":false,
- "fail_condition":2
- },
- "coverity_config":{
- "coverity_project_name":"mcuboot",
- "coverity_stream_name":"develop",
- "analyze_options":[
- "--all"
- ],
- "compiler_type":"gcc",
- "compiler":"arm-none-eabi-gcc",
- "enable_checkers":[
- "ENUM_AS_BOOLEAN",
- "HFA"
- ],
- "disable_checkers":[
- "SECURE_CODING",
- "MISRA_CAST"
- ],
- "source_filter":[
- "boot/cypress/libs/mtb-pdl-cat1",
- "boot/cypress/libs/mtb-hal-cat1",
- "boot/cypress/libs/cy-mbedtls-acceleration",
- "ext/mbedtls"
- ]
- },
- "suppress_list":{
- "/boot/cypress/libs/core-lib":{ "reason":"Third-party library" },
- "/boot/cypress/libs/cy-mbedtls-acceleration":{ "reason":"Third-party library" },
- "/boot/cypress/libs/mtb-hal-cat1":{ "reason":"Third-party library" },
- "/boot/cypress/libs/mtb-pdl-cat1":{ "reason":"Third-party library" },
- "/boot/cypress/libs/retarget-io":{ "reason":"Third-party library" },
- "/ext/mbedtls":{ "reason":"Third-party library" },
- "boot/bootutil/src/bootutil_misc.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "The operations were reviewed for possible wrap.",
- "count": 14
- },
- "CERT INT31-C":{
- "violations":[
- {
- "message": "Casting \"image_index\" from \"int\" to \"unsigned long\" without checking its value may result in lost or misinterpreted data.",
- "reason": "image_index can only be a positive number.",
- "count": 2
- }
- ]
- }
- }
- },
- "boot/bootutil/src/bootutil_public.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "The operations were reviewed for possible wrap.",
- "count": 9
- },
- "CERT INT31-C":{
- "violations":[
- {
- "message": "Casting \"flash_area_id\" from \"int\" to \"unsigned char\" without checking its value may result in lost or misinterpreted data.",
- "reason": "flash_area_id can only be a positive number.",
- "count": 1,
- "source_code": "rc = flash_area_open(flash_area_id, &fap);"
- },
- {
- "message": "Casting \"(image_num << 4) | swap_type\" from \"int\" to \"unsigned char\" without checking its value may result in lost or misinterpreted data.",
- "reason": "All operands are always positive numbers.",
- "count": 1,
- "source_code": "BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);"
- },
- {
- "message": "Casting \"image_index\" from \"int\" to \"unsigned long\" without checking its value may result in lost or misinterpreted data.",
- "reason": "image_index can only be a positive number.",
- "count": 4
- }
- ]
- }
- }
- },
- "boot/bootutil/src/encrypted.c":{
- "rules":{
- "CERT INT31-C":{
- "reason": "The results of the expresions were reviewed for not being misinterpreted.",
- "count": 5
- }
- }
- },
- "boot/bootutil/src/image_validate.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "Violations were reviewed for possible wrap.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/loader.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "Violations were reviewed for possible wrap.",
- "count": 2
- },
- "CERT INT31-C":{
- "reason": "Violations were reviewed for correct interpretation.",
- "count": 9
- }
- }
- },
- "boot/bootutil/src/tlv.c":{
- "rules":{
- "CERT INT30-C":{
- "violations":[
- {
- "message": "Unsigned integer operation \"it->tlv_off + 4UL\" may wrap.",
- "reason": "The operation is reviewed for possible wrap.",
- "count": 1,
- "source_code": "*off = it->tlv_off + sizeof(tlv);"
- },
- {
- "message": "Unsigned integer operation \"it->tlv_off += 4U + tlv.it_len\" may wrap.",
- "reason": "The operation is reviewed for possible wrap.",
- "count": 1,
- "source_code": "it->tlv_off += sizeof(tlv) + tlv.it_len;"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_scratch.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "Violations were reviewed for possible wrap.",
- "count": 13
- },
- "CERT INT31-C":{
- "reason": "Violations were reviewed for correct interpretation.",
- "count": 4
- },
- "CERT INT32-C":{
- "reason": "Violations were reviewed for possible overflow.",
- "count": 2
- }
- }
- },
- "boot/bootutil/src/image_ec256.c":{
- "rules":{
- "CERT INT31-C":{
- "violations":[
- {
- "message": "Casting \"end - pubkey\" from \"int\" to \"unsigned int\" without checking its value may result in lost or misinterpreted data.",
- "reason": "The result of the expresion was reviewed for not being misinterpreted.",
- "count": 1,
- "source": "rc = bootutil_ecdsa_p256_verify(&ctx, pubkey, end - pubkey, hash, sig, slen);"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status_misc.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"((uint32_t)slot + 1UL) * 16UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return boot_swap_size_off(fap) - (((uint32_t)slot + 1UL) * (uint32_t)BOOT_ENC_KEY_SIZE);"
- },
- {
- "message":"Unsigned integer operation \"boot_swap_size_off(fap) - ((uint32_t)slot + 1UL) * 16UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return boot_swap_size_off(fap) - (((uint32_t)slot + 1UL) * (uint32_t)BOOT_ENC_KEY_SIZE);"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status_part.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"4096UL * calc_rec_idx(offs)\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return BOOT_SWAP_STATUS_ROW_SZ * calc_rec_idx(offs);"
- },
- {
- "message":"Unsigned integer operation \"rec_offset + i * 8192UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "fin_offset = rec_offset + i * BOOT_SWAP_STATUS_D_SIZE;"
- },
- {
- "message":"Unsigned integer operation \"copy_counter + 1UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "uint32_t next_counter = copy_counter + 1U;"
- },
- {
- "message":"Unsigned integer operation \"rec_offset + copy_num * 8192UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "fin_offset = rec_offset + copy_num*BOOT_SWAP_STATUS_D_SIZE;"
- }
- ]
- }
- }
- },
- "boot/cypress/platforms/CYW20829/cy_security_cnt_platform.c":{
- "rules":{
- "CERT INT31-C": {
- "violations":[
- {
- "message":"Casting \"FIH_FAILURE\" from \"int\" to \"unsigned int\" without checking its value may result in lost or misinterpreted data.",
- "reason":"Type cast was reviewed for correctness.",
- "count":1,
- "source_code": "return (fih_uint)FIH_FAILURE;"
- },
- {
- "message":"Casting \"FIH_FAILURE\" from \"int\" to \"unsigned int\" without checking its value may result in lost or misinterpreted data.",
- "reason":"Type cast was reviewed for correctness.",
- "count":1,
- "source_code": "fih_uint nv_counter_secure = (fih_uint)FIH_FAILURE;"
- },
- {
- "message":"Casting \"FIH_FAILURE\" from \"int\" to \"unsigned int\" without checking its value may result in lost or misinterpreted data.",
- "reason":"Type cast was reviewed for correctness.",
- "count":1,
- "source_code": "fih_uint security_cnt = (fih_uint) FIH_FAILURE;"
- }
- ]
- },
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"j--\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "j--;"
- },
- {
- "message":"Unsigned integer operation \"32UL - j\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "if ((MAX_SEC_COUNTER_VAL - j) == i) {"
- }
- ]
- }
- }
- },
- "boot/cypress/platforms/CYW20829/cy_service_app.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"address % erase_size + len\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "(((address % erase_size) + len) > erase_size) ) {"
- }
- ]
- }
- }
- },
- "boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.c":{
- "rules":{
- "CERT INT31-C": {
- "violations":[
- {
- "message":"Casting \"c ^ stream_block[i]\" from \"int\" to \"unsigned char\" without checking its value may result in lost or misinterpreted data.",
- "reason":"False positive violation.",
- "count":1,
- "source_code": "*output++ = c ^ stream_block[i];"
- },
- {
- "message":"Casting \"FIH_FAILURE\" from \"int\" to \"unsigned int\" without checking its value may result in lost or misinterpreted data.",
- "reason":"Type cast was reviewed for correctness.",
- "count":1,
- "source_code": "fih_uint l1_app_descr_addr = (fih_uint)FIH_FAILURE;"
- },
- {
- "message":"Casting \"FIH_FAILURE\" from \"int\" to \"unsigned int\" without checking its value may result in lost or misinterpreted data.",
- "reason":"Type cast was reviewed for correctness.",
- "count":1,
- "source_code": "fih_uint ns_vect_tbl_addr = (fih_uint)FIH_FAILURE;"
- }
- ]
- },
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"xip_addr += 16UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "xip_addr += BOOTUTIL_CRYPTO_AES_CTR_BLOCK_SIZE;"
- },
- {
- "message":"Unsigned integer operation \"flash_base + fap->fa_off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "fa_addr = flash_base + fap->fa_off;"
- },
- {
- "message":"Unsigned integer operation \"flash_base + fa_pri->fa_off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "fa_addr = flash_base + fa_pri->fa_off;"
- },
- {
- "message":"Unsigned integer operation \"off += fa_addr - 1610612736UL + 134217728UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "off += CY_GET_XIP_REMAP_ADDR(fa_addr);"
- },
- {
- "message":"Unsigned integer operation \"(uintptr_t)bootstrap_dst_addr + bootstrap_size\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "fits_into((uintptr_t)bootstrap_dst_addr + bootstrap_size, 0,"
- },
- {
- "message":"Unsigned integer operation \"fih_uint_decode(fih_uint_decode(toc2_addr) + bootstrap_src_addr) - 1610612736UL + 134217728UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "ns_vect_tbl_addr = CY_GET_XIP_REMAP_ADDR_FIH(fih_uint_decode(toc2_addr) + bootstrap_src_addr);"
- },
- {
- "message":"Unsigned integer operation \"fih_uint_decode(toc2_addr) + bootstrap_src_addr\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "ns_vect_tbl_addr = CY_GET_XIP_REMAP_ADDR_FIH(fih_uint_decode(toc2_addr) + bootstrap_src_addr);"
- }
- ]
- }
- }
- },
- "boot/cypress/MCUBootApp/main.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"flash_base + rsp->br_image_off + rsp->br_hdr->ih_hdr_size\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return fih_uint_encode(flash_base +"
- },
- {
- "message":"Unsigned integer operation \"flash_base + rsp->br_image_off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return fih_uint_encode(flash_base +"
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_cyw208xx/cy_flash_map.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"flash_base + fa->fa_off + off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "addr = flash_base + fa->fa_off + off;"
- },
- {
- "message":"Unsigned integer operation \"flash_base + fa->fa_off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "addr = flash_base + fa->fa_off + off;"
- },
- {
- "message":"Unsigned integer operation \"flash_base + fa->fa_off + off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "write_start_addr = flash_base + fa->fa_off + off;"
- },
- {
- "message":"Unsigned integer operation \"flash_base + fa->fa_off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "write_start_addr = flash_base + fa->fa_off + off;"
- },
- {
- "message":"Unsigned integer operation \"flash_base + fa->fa_off + off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "erase_start_addr = flash_base + fa->fa_off + off;"
- },
- {
- "message":"Unsigned integer operation \"flash_base + fa->fa_off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "erase_start_addr = flash_base + fa->fa_off + off;"
- },
- {
- "message":"Unsigned integer operation \"area_size + (sector_size - 1U)\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "sectors_n = (area_size + (sector_size - 1U)) / sector_size;"
- },
- {
- "message":"Unsigned integer operation \"sector_size - 1U\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "sectors_n = (area_size + (sector_size - 1U)) / sector_size;"
- },
- {
- "message":"Unsigned integer operation \"my_sector_addr += my_sector_size\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "my_sector_addr += my_sector_size;"
- },
- {
- "message":"Unsigned integer operation \"area_size -= my_sector_size\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "area_size -= my_sector_size;"
- },
- {
- "message":"Unsigned integer operation \"sector_size *= 2U\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "sector_size *= 2u;"
- },
- {
- "message":"Unsigned integer operation \"sectors_n++\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "sectors_n++;"
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_cyw208xx/cy_smif_cyw20829.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"(uint32_t)addr - 1610612736UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":3
- },
- {
- "message":"Unsigned integer operation \"eraseSize - 1UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "uint32_t address = ((uint32_t)addr - CY_XIP_BASE) & ~((uint32_t)(eraseSize - 1u));"
- },
- {
- "message":"Unsigned integer operation \"address += eraseSize\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "address += eraseSize;"
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"length - 6U\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "if(id[length - 6u] != SEMPER_ID_MANUF)"
- },
- {
- "message":"Unsigned integer operation \"size--\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "size--;"
- },
- {
- "message":"Unsigned integer operation \"size + startPos\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "byteArray[size + startPos] = (uint8_t)(value & PARAM_ID_LSB_MASK);"
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"smif_id - 1UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "Cy_GPIO_Port_Deinit(qspi_SS_Configuration[smif_id-1U].SS_Port);"
- }
- ]
- }
- }
- },
- "/boot/cypress/libs/watchdog/watchdog.c":{
- "rules":{
- "CERT INT31-C": {
- "violations":[
- {
- "message":"Casting \"timeout - (1UL << 17U - ignore_bits) + Cy_WDT_GetCount()\" from \"unsigned long\" to \"unsigned short\" without checking its value may result in lost or misinterpreted data.",
- "reason":"Used free-running WDT with a maximum of 16-bit resolution.",
- "count":1,
- "source_code": "return (uint16_t)(timeout - (1UL << (17U - ignore_bits)) + Cy_WDT_GetCount());"
- }
- ]
- },
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"17U - ignore_bits\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return (uint16_t)(timeout - (1UL << (17U - ignore_bits)) + Cy_WDT_GetCount());"
- },
- {
- "message":"Unsigned integer operation \"timeout - (1UL << 17U - ignore_bits)\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return (uint16_t)(timeout - (1UL << (17U - ignore_bits)) + Cy_WDT_GetCount());"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/bootutil_priv.h":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"flash_sector_get_off(&state->imgs[0U][slot].sectors[sector]) - flash_sector_get_off(&state->imgs[0U][slot].sectors[0])\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"bs->idx - 1UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "uint32_t off = (bs->idx - BOOT_STATUS_IDX_0) * elem_sz;"
- },
- {
- "message":"Unsigned integer operation \"(bs->idx - 1UL) * elem_sz\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "uint32_t off = (bs->idx - BOOT_STATUS_IDX_0) * elem_sz;"
- }
- ]
- }
- }
- }
- }
-}
diff --git a/boot/cypress/coverity/cyw20829/config_mcuboot_misra.json b/boot/cypress/coverity/cyw20829/config_mcuboot_misra.json
deleted file mode 100644
index 98ec021..0000000
--- a/boot/cypress/coverity/cyw20829/config_mcuboot_misra.json
+++ /dev/null
@@ -1,897 +0,0 @@
-{
- "script_config":{
- "coding_standard":"MISRA",
- "log_file":".\\coverity.log",
- "coverity_path":"C:\\Program Files\\Coverity\\Coverity Static Analysis\\bin",
- "report_to_testrail":false,
- "report_to_coverity_server":false,
- "project_source_path":".\\..\\..\\boot\\cypress",
- "deviations_config":".\\..\\..\\boot\\cypress\\coverity\\cyw20829\\misrac2012_custom.config",
- "build_cmd":"make clean app POST_BUILD_ENABLE=0 APP_NAME=MCUBootApp PLATFORM=CYW20829",
- "manual_clean":false,
- "fail_condition":2
- },
- "coverity_config":{
- "coverity_project_name":"mcuboot",
- "coverity_stream_name":"develop",
- "analyze_options":[
- "--all"
- ],
- "compiler_type":"gcc",
- "compiler":"arm-none-eabi-gcc",
- "enable_checkers":[
- "ENUM_AS_BOOLEAN",
- "HFA"
- ],
- "disable_checkers":[
-
- ],
- "source_filter":[
- "boot/cypress/libs/mtb-pdl-cat1",
- "boot/cypress/libs/mtb-hal-cat1",
- "boot/cypress/libs/cy-mbedtls-acceleration",
- "ext/mbedtls"
- ]
- },
- "suppress_list":{
- "/boot/cypress/libs/core-lib":{ "reason":"Third-party library" },
- "/boot/cypress/libs/cy-mbedtls-acceleration":{ "reason":"Third-party library" },
- "/boot/cypress/libs/mtb-hal-cat1":{ "reason":"Third-party library" },
- "/boot/cypress/libs/mtb-pdl-cat1":{ "reason":"Third-party library" },
- "/boot/cypress/libs/retarget-io":{ "reason":"Third-party library" },
- "/boot/cypress/keys":{ "reason":"Doesn't contain source code files" },
- "ext/mbedtls":{ "reason":"Third-party library" },
- "boot/cypress/MCUBootApp/os":{ "reason":"Third-party library" },
- "boot/bootutil/include/bootutil":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 12
- },
- "MISRA C-2012 Rule 21.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 7
- },
- "MISRA C-2012 Rule 21.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 8
- }
- }
- },
- "boot/bootutil/src":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 21
- }
- }
- },
- "boot/bootutil/include/bootutil/fault_injection_hardening.h":{
- "rules":{
- "MISRA C-2012 Rule 8.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- }
- }
- },
- "boot/bootutil/include/bootutil/crypto/aes_ctr.h":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/include/bootutil/crypto/ecdsa_p256.h":{
- "rules":{
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 4
- }
- }
- },
- "boot/bootutil/include/bootutil/crypto/ecdh_p256.h":{
- "rules":{
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- }
- }
- },
- "boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The mcuboot_crypto_config.h file is based on mbedtls config template file.",
- "count": 56
- },
- "MISRA C-2012 Rule 21.1": {
- "violations":[
- {
- "message":"Defining or undefining a reserved name \"_CRT_SECURE_NO_DEPRECATE\", which is an identifier or macro name beginning with an underscore.",
- "reason":" _CRT_SECURE_NO_DEPRECATE cannot be renamed, because it is using in many files of the mbedtls library.",
- "count":1,
- "source_code": "#define _CRT_SECURE_NO_DEPRECATE 1"
- }
- ]
- }
- }
- },
- "boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 1
- }
- }
- },
- "boot/cypress/MCUBootApp/cy_security_cnt.c":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The mcuboot_crypto_config.h file is based on mbedtls config template file.",
- "count": 1
- }
- }
- },
- "boot/cypress/MCUBootApp/keys.c":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The mcuboot_crypto_config.h file is based on mbedtls config template file.",
- "count": 1
- }
- }
- },
- "boot/cypress/MCUBootApp/main.c":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The mcuboot_crypto_config.h file is based on mbedtls config template file.",
- "count": 1
- },
- "MISRA C-2012 Rule 10.4": {
- "violations":[
- {
- "message":"Essential type of the left hand operand \"1\" (boolean) is not the same as that of the right operand \"fih_eq(fih_rc, FIH_SUCCESS)\"(signed).",
- "reason":"fih_eq() is common MCUboot function.",
- "count":1,
- "source_code": "if (true == fih_eq(fih_rc, FIH_SUCCESS)) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "message": "Controlling expression \"!false\" is invariant.",
- "reason": "A violation occurs on \"while (true)\" code",
- "count": 3
- },
- "MISRA C-2012 Rule 21.6":{
- "violations":[
- {
- "message": "Using function \"fprintf\".",
- "reason": "fprintf function, which is used in default logging implementation of mcuboot is a part of standard input/output library",
- "count": 14
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/sysflash/sysflash.h":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 1
- }
- }
- },
- "boot/cypress/libs/watchdog":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 2
- }
- }
- },
- "boot/cypress/libs/watchdog/watchdog.h":{
- "rules":{
- "MISRA C-2012 Directive 4.10":{
- "reason": "Violation appears on the included library .h files.",
- "count": 1
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_cyw208xx":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 2
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_cyw208xx/cy_flash_map.c":{
- "rules":{
- "MISRA C-2012 Rule 21.6":{
- "violations":[
- {
- "message": "Using function \"fprintf\".",
- "reason": "fprintf function, which is used in default logging implementation of mcuboot is a part of standard input/output library",
- "count": 3
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/cy_flash_map.h":{
- "rules":{
- "MISRA C-2012 Rule 8.4":{
- "reason": "cy_flash_map.h is generated from json files.",
- "count": 1
- }
- }
- },
- "boot/cypress/platforms/CYW20829":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 21
- }
- }
- },
- "boot/cypress/platforms/CYW20829/cybsp.h":{
- "rules":{
- "MISRA C-2012 Directive 4.10":{
- "reason": "Violation appears on the included library .h files.",
- "count": 1
- }
- }
- },
- "boot/cypress/platforms/CYW20829/cybsp_doc.h":{
- "rules":{
- "MISRA C-2012 Directive 4.10":{
- "reason": "Violation appears on the included library .h files.",
- "count": 1
- }
- }
- },
- "boot/cypress/platforms/CYW20829/cybsp_types.h":{
- "rules":{
- "MISRA C-2012 Directive 4.10":{
- "reason": "Violation appears on the included library .h files.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/bootutil_misc.c":{
- "rules":{
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 9
- },
- "MISRA C-2012 Rule 15.7":{
- "message": "No non-empty terminating \"else\" statement.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 2.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 20.9":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 7
- },
- "MISRA C-2012 Rule 21.16":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 8.10":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 8.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 8.5":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/bootutil_priv.h":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/bootutil_public.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 12
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 26
- },
- "MISRA C-2012 Rule 11.8":{
- "violations":[
- {
- "message": "The type cast of the pointer expression \"buffer\" to type \"uint8_t *\" removes \"const\" qualifier from the pointed to type.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (p = (uint8_t *)buffer; len-- > 0; p++) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.2":{
- "violations":[
- {
- "message": "The condition clause expression of the for loop has persistent side-effects.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (p = (uint8_t *)buffer; len-- > 0; p++) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "violations":[
- {
- "message": "The condition \"rc == 1\" must be true.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "if (rc == BOOT_HOOK_REGULAR)"
- }
- ]
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 15.7":{
- "message": "No non-empty terminating \"else\" statement.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 16.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 16.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 6
- },
- "MISRA C-2012 Rule 16.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 16.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 2.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 8
- },
- "MISRA C-2012 Rule 7.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- }
- }
- },
- "boot/bootutil/src/caps.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 10
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 5
- },
- "MISRA C-2012 Rule 12.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- }
- }
- },
- "boot/bootutil/src/encrypted.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 9
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":7
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 19
- },
- "MISRA C-2012 Rule 11.8":{
- "violations":[
- {
- "message": "The type cast of the pointer expression \"bootutil_enc_key.key\" to type \"uint8_t *\" removes \"const\" qualifier from the pointed to type.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "cp = (uint8_t *)bootutil_enc_key.key;"
- }
- ]
- },
- "MISRA C-2012 Rule 14.2":{
- "violations":[
- {
- "message": "The third clause of the for loop has more than one persistent side-effect.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (off = 0; len > 0; off += BOOTUTIL_CRYPTO_SHA256_DIGEST_SIZE, ++counter) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 5
- },
- "MISRA C-2012 Rule 20.9":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 21.14":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 7.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/image_ec256.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 4
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":1
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 6
- },
- "MISRA C-2012 Rule 11.8":{
- "violations":[
- {
- "message": "The type cast of the pointer expression \"bootutil_keys[key_id].key\" to type \"uint8_t *\" removes \"const\" qualifier from the pointed to type.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "pubkey = (uint8_t *)bootutil_keys[key_id].key;"
- }
- ]
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 4
- },
- "MISRA C-2012 Rule 21.14":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 8.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/image_validate.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 9
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":6
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 12
- },
- "MISRA C-2012 Rule 11.9":{
- "violations":[
- {
- "message": "Literal \"0\" shall not be used as null pointer constant.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- }
- ]
- },
- "MISRA C-2012 Rule 14.2":{
- "violations":[
- {
- "message": "The expression \"blk_sz\" used in the for loop clauses is modified in the loop body.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (off = 0; off < size; off += blk_sz) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "violations":[
- {
- "message": "The condition \"0\" cannot be true.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "if (!EXPECTED_SIG_LEN(len) || len > sizeof(buf)) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 21
- },
- "MISRA C-2012 Rule 15.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 6
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":4
- },
- "MISRA C-2012 Rule 8.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/loader.c":{
- "rules":{
- "MISRA C-2012 Directive 4.7":{
- "reason": "REQUIRED violations will not be fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 12
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":43
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 38
- },
- "MISRA C-2012 Rule 11.6":{
- "violations":[
- {
- "message": "The expression \"entry_val\" of type \"uintptr_t\" is cast to type \"void *\".",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "*entry = (void *) entry_val;"
- }
- ]
- },
- "MISRA C-2012 Rule 11.9":{
- "violations":[
- {
- "message": "Literal \"0\" shall not be used as null pointer constant.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- }
- ]
- },
- "MISRA C-2012 Rule 13.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 13.5":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 14.2":{
- "violations":[
- {
- "message": "The first clause of the for loop is not empty, does not declare a loop counter or has a side-effect other than to set the loop counter.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (sect = 0, size = 0; sect < sect_count; sect++) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 7
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 22
- },
- "MISRA C-2012 Rule 15.7":{
- "message": "No non-empty terminating \"else\" statement.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 16.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 16.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 16.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 2.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 20.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 20.9":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 15
- },
- "MISRA C-2012 Rule 21.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":33
- },
- "MISRA C-2012 Rule 5.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":1
- },
- "MISRA C-2012 Rule 8.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/swap_misc.c":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 36
- }
- }
- },
- "boot/bootutil/src/swap_status.c":{
- "rules":{
- "MISRA C-2012 Rule 21.6":{
- "violations":[
- {
- "message": "Using function \"fprintf\".",
- "reason": "fprintf function, which is used in default logging implementation of mcuboot is a part of standard input/output library",
- "count": 2
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status_misc.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "violations":[
- {
- "message": "The expression \"1\" of non-boolean essential type is being interpreted as a boolean value for the operator \"? :\".",
- "reason": "False-positive violation.",
- "count": 1,
- "source_code": "BOOT_SET_SWAP_INFO_M(swap_info, 0u, (uint8_t)BOOT_SWAP_TYPE_NONE);"
- }
- ]
- },
- "MISRA C-2012 Rule 10.4":{
- "violations":[
- {
- "message": "Essential type of the left hand operand \"32U\" (signed) is not the same as that of the right operand \"1U\"(unsigned).",
- "reason": "MCUBOOT_MAX_IMG_SECTORS is passed as make parameter.",
- "count": 2
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "reason": "Ternary oprerator compares the constants.",
- "count": 3
- },
- "MISRA C-2012 Rule 21.6":{
- "violations":[
- {
- "message": "Using function \"fprintf\".",
- "reason": "fprintf function, which is used in default logging implementation of mcuboot is a part of standard input/output library",
- "count": 5
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status_part.c":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "violations":[
- {
- "message": "Essential type of the left hand operand \"offset\" (signed) is not the same as that of the right operand \"2UL * 8192UL\"(unsigned).",
- "reason": "BOOT_SWAP_STATUS_SIZE always has a value about a few kilobytes.",
- "count": 1,
- "source_code": "offset += BOOT_SWAP_STATUS_SIZE;"
- },
- {
- "message": "Essential type of the left hand operand \"32U\" (signed) is not the same as that of the right operand \"1U\"(unsigned).",
- "reason": "MCUBOOT_MAX_IMG_SECTORS is passed as make parameter.",
- "count": 5
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "reason": "Ternary oprerator compares the constants.",
- "count": 2
- }
- }
- },
- "boot/bootutil/src/swap_scratch.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 4
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":14
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 21
- },
- "MISRA C-2012 Rule 14.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 6
- },
- "MISRA C-2012 Rule 15.7":{
- "message": "No non-empty terminating \"else\" statement.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 20.9":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 5
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":12
- },
- "MISRA C-2012 Rule 8.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- }
- }
- },
- "boot/bootutil/src/tlv.c":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 19
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 15.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/cypress/platforms/CYW20829/cy_security_cnt_platform.c":{
- "rules":{
- "MISRA C-2012 Rule 10.4": {
- "violations":[
- {
- "message":"Essential type of the left hand operand \"1\" (boolean) is not the same as that of the right operand \"fih_eq(fih_rc, FIH_SUCCESS)\"(signed).",
- "reason":"fih_eq() is common MCUboot function.",
- "count":1,
- "source_code": "if (true == fih_eq(fih_rc, FIH_SUCCESS)) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "reason": "Violations occur in \"do { } while(false)\" pattern that is used in some macros of header files.",
- "count": 1
- }
- }
- },
- "boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.c":{
- "rules":{
- "MISRA C-2012 Rule 14.3":{
- "reason": "Violations occur in \"do { } while(false)\" pattern that is used in some macros of header files.",
- "count": 9
- },
- "MISRA C-2012 Rule 8.6":{
- "reason": "hsiniFppAnuR_92802wyc is used in ASM code",
- "count": 1
- }
- }
- },
- "boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.h":{
- "rules":{
- "MISRA C-2012 Rule 8.6":{
- "reason": "Symbols are defined in linker script.",
- "count": 8
- }
- }
- },
- "boot/cypress/platforms/CYW20829/cy_service_app.c":{
- "rules":{
- "MISRA C-2012 Rule 10.4": {
- "violations":[
- {
- "message":"Essential type of the left hand operand \"1610612736UL\" (unsigned) is not the same as that of the right operand \"491520\"(signed).",
- "reason":"CY_XIP_BASE is defined in PDL. SERVICE_APP_INPUT_PARAMS_OFFSET is passed as make parameter.",
- "count":1,
- "source_code": "rc = flash_write_packet((CY_XIP_BASE + SERVICE_APP_INPUT_PARAMS_OFFSET),"
- },
- {
- "message":"Essential type of the left hand operand \"1610612736UL\" (unsigned) is not the same as that of the right operand \"492544\"(signed).",
- "reason":"CY_XIP_BASE is defined in PDL. SERVICE_APP_DESC_OFFSET is passed as make parameter.",
- "count":1,
- "source_code": "rc = flash_write_packet((CY_XIP_BASE + SERVICE_APP_DESC_OFFSET),"
- },
- {
- "message":"Essential type of the left hand operand \"1610612736UL\" (unsigned) is not the same as that of the right operand \"492544\"(signed).",
- "reason":"CY_XIP_BASE is defined in PDL. SERVICE_APP_INPUT_PARAMS_OFFSET is passed as make parameter.",
- "count":1,
- "source_code": "rc = flash_read((CY_XIP_BASE + SERVICE_APP_DESC_OFFSET),"
- },
- {
- "message":"Essential type of the left hand operand \"1610612736UL\" (unsigned) is not the same as that of the right operand \"492544\"(signed).",
- "reason":"CY_XIP_BASE is defined in PDL. SERVICE_APP_DESC_OFFSET is passed as make parameter.",
- "count":1,
- "source_code": "rc = cyw20829_smif_erase((CY_XIP_BASE + SERVICE_APP_DESC_OFFSET), qspi_get_erase_size());"
- }
- ]
- }
- }
- }
- }
-}
diff --git a/boot/cypress/coverity/cyw20829/misrac2012_custom.config b/boot/cypress/coverity/cyw20829/misrac2012_custom.config
deleted file mode 100644
index 55d963e..0000000
--- a/boot/cypress/coverity/cyw20829/misrac2012_custom.config
+++ /dev/null
@@ -1,8 +0,0 @@
-{
- "version": "2.0",
- "standard": "misrac2012",
- "title": "MISRA C-2012 All Rules",
- "deviations": [
-
- ]
-}
diff --git a/boot/cypress/coverity/psoc062/cert-c-custom.config b/boot/cypress/coverity/psoc062/cert-c-custom.config
deleted file mode 100644
index 8443bef..0000000
--- a/boot/cypress/coverity/psoc062/cert-c-custom.config
+++ /dev/null
@@ -1,8 +0,0 @@
-{
- "version": "2.0",
- "standard": "cert-c",
- "title": "CERT-C All Rules",
- "deviations": [
-
- ]
-}
diff --git a/boot/cypress/coverity/psoc062/config_mcuboot_cert_c.json b/boot/cypress/coverity/psoc062/config_mcuboot_cert_c.json
deleted file mode 100644
index ce46968..0000000
--- a/boot/cypress/coverity/psoc062/config_mcuboot_cert_c.json
+++ /dev/null
@@ -1,533 +0,0 @@
-{
- "script_config":{
- "coding_standard":"CERT C",
- "log_file":".\\coverity.log",
- "coverity_path":"C:\\Program Files\\Coverity\\Coverity Static Analysis\\bin",
- "report_to_testrail":false,
- "report_to_coverity_server":false,
- "project_source_path":".\\..\\..\\boot\\cypress",
- "deviations_config":".\\..\\..\\boot\\cypress\\coverity\\psoc062\\cert-c-custom.config",
- "build_cmd":"make clean app POST_BUILD_ENABLE=0 APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M",
- "manual_clean":false,
- "fail_condition":2
- },
- "coverity_config":{
- "coverity_project_name":"mcuboot",
- "coverity_stream_name":"develop",
- "analyze_options":[
- "--all"
- ],
- "compiler_type":"gcc",
- "compiler":"arm-none-eabi-gcc",
- "enable_checkers":[
- "ENUM_AS_BOOLEAN",
- "HFA"
- ],
- "disable_checkers":[
- "SECURE_CODING",
- "MISRA_CAST"
- ],
- "source_filter":[
- "boot/cypress/libs/mtb-pdl-cat1",
- "boot/cypress/libs/mtb-hal-cat1",
- "boot/cypress/libs/cy-mbedtls-acceleration",
- "ext/mbedtls"
- ]
- },
- "suppress_list":{
- "/boot/cypress/libs/core-lib":{ "reason":"Third-party library" },
- "/boot/cypress/libs/cy-mbedtls-acceleration":{ "reason":"Third-party library" },
- "/boot/cypress/libs/mtb-hal-cat1":{ "reason":"Third-party library" },
- "/boot/cypress/libs/mtb-pdl-cat1":{ "reason":"Third-party library" },
- "/boot/cypress/libs/retarget-io":{ "reason":"Third-party library" },
- "/ext/mbedtls":{ "reason":"Third-party library" },
- "boot/bootutil/src/bootutil_misc.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "The operations were reviewed for possible wrap.",
- "count": 14
- },
- "CERT INT31-C":{
- "violations":[
- {
- "message": "Casting \"image_index\" from \"int\" to \"unsigned long\" without checking its value may result in lost or misinterpreted data.",
- "reason": "image_index can only be a positive number.",
- "count": 2
- }
- ]
- }
- }
- },
- "boot/bootutil/src/bootutil_public.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "The operations were reviewed for possible wrap.",
- "count": 9
- },
- "CERT INT31-C":{
- "violations":[
- {
- "message": "Casting \"flash_area_id\" from \"int\" to \"unsigned char\" without checking its value may result in lost or misinterpreted data.",
- "reason": "flash_area_id can only be a positive number.",
- "count": 1,
- "source_code": "rc = flash_area_open(flash_area_id, &fap);"
- },
- {
- "message": "Casting \"(image_num << 4) | swap_type\" from \"int\" to \"unsigned char\" without checking its value may result in lost or misinterpreted data.",
- "reason": "All operands are always positive numbers.",
- "count": 1,
- "source_code": "BOOT_SET_SWAP_INFO(swap_info, image_num, swap_type);"
- },
- {
- "message": "Casting \"image_index\" from \"int\" to \"unsigned long\" without checking its value may result in lost or misinterpreted data.",
- "reason": "image_index can only be a positive number.",
- "count": 4
- }
- ]
- }
- }
- },
- "boot/bootutil/src/encrypted.c":{
- "rules":{
- "CERT INT31-C":{
- "reason": "The results of the expresions were reviewed for not being misinterpreted.",
- "count": 5
- }
- }
- },
- "boot/bootutil/src/image_validate.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "Violations were reviewed for possible wrap.",
- "count": 4
- },
- "CERT INT31-C":{
- "violations":[
- {
- "message": "Casting \"image_index\" from \"int\" to \"unsigned long\" without checking its value may result in lost or misinterpreted data.",
- "reason": "image_index is always a positive number.",
- "count": 1,
- "source_code": "if (MUST_DECRYPT(fap, image_index, hdr) &&"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/loader.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "Violations were reviewed for possible wrap.",
- "count": 5
- },
- "CERT INT31-C":{
- "reason": "Violations were reviewed for correct interpretation.",
- "count": 12
- }
- }
- },
- "boot/bootutil/src/tlv.c":{
- "rules":{
- "CERT INT30-C":{
- "violations":[
- {
- "message": "Unsigned integer operation \"it->tlv_off + 4UL\" may wrap.",
- "reason": "The operation is reviewed for possible wrap.",
- "count": 1,
- "source_code": "*off = it->tlv_off + sizeof(tlv);"
- },
- {
- "message": "Unsigned integer operation \"it->tlv_off += 4U + tlv.it_len\" may wrap.",
- "reason": "The operation is reviewed for possible wrap.",
- "count": 1,
- "source_code": "it->tlv_off += sizeof(tlv) + tlv.it_len;"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_scratch.c":{
- "rules":{
- "CERT INT30-C":{
- "reason": "Violations were reviewed for possible wrap.",
- "count": 13
- },
- "CERT INT31-C":{
- "reason": "Violations were reviewed for correct interpretation.",
- "count": 4
- },
- "CERT INT32-C":{
- "reason": "Violations were reviewed for possible overflow.",
- "count": 6
- }
- }
- },
- "boot/bootutil/src/image_ec256.c":{
- "rules":{
- "CERT INT31-C":{
- "violations":[
- {
- "message": "Casting \"end - pubkey\" from \"int\" to \"unsigned int\" without checking its value may result in lost or misinterpreted data.",
- "reason": "The result of the expresion was reviewed for not being misinterpreted.",
- "count": 1,
- "source": "rc = bootutil_ecdsa_p256_verify(&ctx, pubkey, end - pubkey, hash, sig, slen);"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status_misc.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"((uint32_t)slot + 1UL) * 16UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return boot_swap_size_off(fap) - (((uint32_t)slot + 1UL) * (uint32_t)BOOT_ENC_KEY_SIZE);"
- },
- {
- "message":"Unsigned integer operation \"boot_swap_size_off(fap) - ((uint32_t)slot + 1UL) * 16UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return boot_swap_size_off(fap) - (((uint32_t)slot + 1UL) * (uint32_t)BOOT_ENC_KEY_SIZE);"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status_part.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"512UL * calc_rec_idx(offs)\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return BOOT_SWAP_STATUS_ROW_SZ * calc_rec_idx(offs);"
- },
- {
- "message":"Unsigned integer operation \"rec_offset + i * 2560UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":2,
- "source_code": "fin_offset = rec_offset + i * BOOT_SWAP_STATUS_D_SIZE;"
- },
- {
- "message":"Unsigned integer operation \"rec_offset + i * 1024UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":2,
- "source_code": "fin_offset = rec_offset + i * BOOT_SWAP_STATUS_D_SIZE;"
- },
- {
- "message":"Unsigned integer operation \"crc_fail++\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "crc_fail++;"
- },
- {
- "message":"Unsigned integer operation \"magic_fail++\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "magic_fail++;"
- },
- {
- "message":"Unsigned integer operation \"copy_counter + 1UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "uint32_t next_counter = copy_counter + 1U;"
- },
- {
- "message":"Unsigned integer operation \"rec_offset + copy_num * 2560UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "fin_offset = rec_offset + copy_num*BOOT_SWAP_STATUS_D_SIZE;"
- },
- {
- "message":"Unsigned integer operation \"rec_offset + copy_num * 1024UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "fin_offset = rec_offset + copy_num*BOOT_SWAP_STATUS_D_SIZE;"
- },
- {
- "message":"Unsigned integer operation \"rec_offs += 512UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "rec_offs += BOOT_SWAP_STATUS_ROW_SZ;"
- },
- {
- "message":"Unsigned integer operation \"fap->fa_size - primary_trailer_buf_sz\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "rc= flash_area_erase(fap, fap->fa_size - primary_trailer_buf_sz, primary_trailer_buf_sz);"
- },
- {
- "message":"Unsigned integer operation \"rec_offset + i * 1536UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":2,
- "source_code": "fin_offset = rec_offset + i * BOOT_SWAP_STATUS_D_SIZE;"
- },
- {
- "message":"Unsigned integer operation \"rec_offset + copy_num * 1536UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "fin_offset = rec_offset + copy_num*BOOT_SWAP_STATUS_D_SIZE;"
- }
- ]
- }
- }
- },
- "boot/cypress/MCUBootApp/main.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"flash_base + rsp->br_image_off + rsp->br_hdr->ih_hdr_size\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return fih_uint_encode(flash_base +"
- },
- {
- "message":"Unsigned integer operation \"flash_base + rsp->br_image_off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return fih_uint_encode(flash_base +"
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_psoc6/cy_flash_map.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"flash_base + fa->fa_off + off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":5
- },
- {
- "message":"Unsigned integer operation \"flash_base + fa->fa_off\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":5
- },
- {
- "message":"Unsigned integer operation \"flash_base + fa->fa_off + off + len\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":2
- },
- {
- "message":"Unsigned integer operation \"write_end_addr - write_start_addr\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "row_number = (write_end_addr - write_start_addr) / CY_FLASH_SIZEOF_ROW;"
- },
- {
- "message":"Unsigned integer operation \"erase_start_addr / 512U * 512U\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "uint32_t row_start_addr = (erase_start_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;"
- },
- {
- "message":"Unsigned integer operation \"erase_end_addr / 512U * 512U\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "uint32_t row_end_addr = (erase_end_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;"
- },
- {
- "message":"Unsigned integer operation \"area_size + (sector_size - 1U)\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "sectors_n = (area_size + (sector_size - 1U)) / sector_size;"
- },
- {
- "message":"Unsigned integer operation \"sector_size - 1U\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "sectors_n = (area_size + (sector_size - 1U)) / sector_size;"
- },
- {
- "message":"Unsigned integer operation \"sector_size *= 2U\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "sector_size *= 2u;"
- },
- {
- "message":"Unsigned integer operation \"my_sector_addr += my_sector_size\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "my_sector_addr += my_sector_size;"
- },
- {
- "message":"Unsigned integer operation \"area_size -= my_sector_size\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "area_size -= my_sector_size;"
- },
- {
- "message":"Unsigned integer operation \"sectors_n++\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "sectors_n++;"
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"(uint32_t)addr - 402653184UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":3
- },
- {
- "message":"Unsigned integer operation \"memCfg->deviceCfg->eraseSize - 1UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "address = ((uint32_t)addr - CY_SMIF_BASE_MEM_OFFSET ) & ~((uint32_t)(memCfg->deviceCfg->eraseSize - 1u));"
- },
- {
- "message":"Unsigned integer operation \"address += memCfg->deviceCfg->eraseSize\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "address += memCfg->deviceCfg->eraseSize;"
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"smif_id - 1UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "Cy_GPIO_Port_Deinit(qspi_SS_Configuration[smif_id-1U].SS_Port);"
- }
- ]
- }
- }
- },
- "/boot/cypress/libs/watchdog/watchdog.c":{
- "rules":{
- "CERT INT31-C": {
- "violations":[
- {
- "message":"Casting \"timeout - (1UL << 17U - ignore_bits) + Cy_WDT_GetCount()\" from \"unsigned long\" to \"unsigned short\" without checking its value may result in lost or misinterpreted data.",
- "reason":"Used free-running WDT with a maximum of 16-bit resolution.",
- "count":1,
- "source_code": "return (uint16_t)(timeout - (1UL << (17U - ignore_bits)) + Cy_WDT_GetCount());"
- }
- ]
- },
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"17U - ignore_bits\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return (uint16_t)(timeout - (1UL << (17U - ignore_bits)) + Cy_WDT_GetCount());"
- },
- {
- "message":"Unsigned integer operation \"timeout - (1UL << 17U - ignore_bits)\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "return (uint16_t)(timeout - (1UL << (17U - ignore_bits)) + Cy_WDT_GetCount());"
- }
- ]
- }
- }
- },
- "/boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c":{
- "rules":{
- "CERT INT31-C": {
- "violations":[
- {
- "message":"Casting \"cy_retarget_io_getchar()\" from \"unsigned char\" to \"char\" without checking its value may result in lost or misinterpreted data.",
- "reason":"Type cast was reviewed for correctness.",
- "count":1,
- "source_code": "*ptr = (char)cy_retarget_io_getchar();"
- },
- {
- "message":"Casting \"c\" from \"char\" to \"unsigned char\" without checking its value may result in lost or misinterpreted data.",
- "reason":"Type cast was reviewed for correctness.",
- "count":1,
- "source_code": "count = Cy_SCB_UART_Put(CYBSP_UART_HW, (uint8_t)c);"
- }
- ]
- },
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"Cy_SysClk_ClkPeriGetFrequency() * (1UL << frac_bits) + baudrate * oversample_value / 2UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1UL << frac_bits)) + ((baudrate * oversample_value) / 2U)) / (baudrate * oversample_value) - 1U;"
- },
- {
- "message":"Unsigned integer operation \"baudrate * oversample_value\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1UL << frac_bits)) + ((baudrate * oversample_value) / 2U)) / (baudrate * oversample_value) - 1U;"
- },
- {
- "message":"Unsigned integer operation \"(Cy_SysClk_ClkPeriGetFrequency() * (1UL << frac_bits) + baudrate * oversample_value / 2UL) / (baudrate * oversample_value) - 1UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "divider = ((Cy_SysClk_ClkPeriGetFrequency() * (1UL << frac_bits)) + ((baudrate * oversample_value) / 2U)) / (baudrate * oversample_value) - 1U;"
- },
- {
- "message":"Unsigned integer operation \"10UL * cy_delayFreqKhz\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "Cy_SysLib_DelayCycles(10U * cy_delayFreqKhz);"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/bootutil_priv.h":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"flash_sector_get_off(&state->imgs[state->curr_img_idx][slot].sectors[sector]) - flash_sector_get_off(&state->imgs[state->curr_img_idx][slot].sectors[0])\" may wrap.",
- "reason":"L2 C-CERT violations are not fixed in common MCUboot source files.",
- "count":1,
- "source_code": "return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -"
- },
- {
- "message":"Unsigned integer operation \"flash_sector_get_off(&state->imgs[0U][slot].sectors[sector]) - flash_sector_get_off(&state->imgs[0U][slot].sectors[0])\" may wrap.",
- "reason":"L2 C-CERT violations are not fixed in common MCUboot source files.",
- "count":1,
- "source_code": "return flash_sector_get_off(&BOOT_IMG(state, slot).sectors[sector]) -"
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status.c":{
- "rules":{
- "CERT INT30-C": {
- "violations":[
- {
- "message":"Unsigned integer operation \"bs->idx - 1UL\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "uint32_t off = (bs->idx - BOOT_STATUS_IDX_0) * elem_sz;"
- },
- {
- "message":"Unsigned integer operation \"(bs->idx - 1UL) * elem_sz\" may wrap.",
- "reason":"The operations were reviewed for possible overflow. All of them either performed with static data or checked (limited) prior to the operation.",
- "count":1,
- "source_code": "uint32_t off = (bs->idx - BOOT_STATUS_IDX_0) * elem_sz;"
- }
- ]
- }
- }
- }
- }
-}
diff --git a/boot/cypress/coverity/psoc062/config_mcuboot_misra.json b/boot/cypress/coverity/psoc062/config_mcuboot_misra.json
deleted file mode 100644
index 776096e..0000000
--- a/boot/cypress/coverity/psoc062/config_mcuboot_misra.json
+++ /dev/null
@@ -1,894 +0,0 @@
-{
- "script_config":{
- "coding_standard":"MISRA",
- "log_file":".\\coverity.log",
- "coverity_path":"C:\\Program Files\\Coverity\\Coverity Static Analysis\\bin",
- "report_to_testrail":false,
- "report_to_coverity_server":false,
- "project_source_path":".\\..\\..\\boot\\cypress",
- "deviations_config":".\\..\\..\\boot\\cypress\\coverity\\psoc062\\misrac2012-custom.config",
- "build_cmd":"make clean app POST_BUILD_ENABLE=0 APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M",
- "manual_clean":false,
- "fail_condition":2
- },
- "coverity_config":{
- "coverity_project_name":"mcuboot",
- "coverity_stream_name":"develop",
- "analyze_options":[
- "--all"
- ],
- "compiler_type":"gcc",
- "compiler":"arm-none-eabi-gcc",
- "enable_checkers":[
- "ENUM_AS_BOOLEAN",
- "HFA"
- ],
- "disable_checkers":[
-
- ],
- "source_filter":[
- "boot/cypress/libs/mtb-pdl-cat1",
- "boot/cypress/libs/mtb-hal-cat1",
- "boot/cypress/libs/cy-mbedtls-acceleration",
- "ext/mbedtls"
- ]
- },
- "suppress_list":{
- "/boot/cypress/libs/core-lib":{ "reason":"Third-party library" },
- "/boot/cypress/libs/cy-mbedtls-acceleration":{ "reason":"Third-party library" },
- "/boot/cypress/libs/mtb-hal-cat1":{ "reason":"Third-party library" },
- "/boot/cypress/libs/mtb-pdl-cat1":{ "reason":"Third-party library" },
- "/boot/cypress/libs/retarget-io":{ "reason":"Third-party library" },
- "/boot/cypress/keys":{ "reason":"Doesn't contain source code files" },
- "ext/mbedtls":{ "reason":"Third-party library" },
- "boot/cypress/MCUBootApp/os":{ "reason":"Third-party library" },
- "boot/bootutil/include/bootutil":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 12
- },
- "MISRA C-2012 Rule 21.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 7
- },
- "MISRA C-2012 Rule 21.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 10
- }
- }
- },
- "boot/bootutil/src":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 21
- }
- }
- },
- "boot/bootutil/include/bootutil/fault_injection_hardening.h":{
- "rules":{
- "MISRA C-2012 Rule 8.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- }
- }
- },
- "boot/bootutil/include/bootutil/crypto/aes_ctr.h":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/include/bootutil/ramload.h":{
- "rules":{
- "MISRA C-2012 Rule 21.2":{
- "violations":[
- {
- "message":"\"__RAMLOAD_H__\", an identifier or macro name beginning with an underscore, shall not be declared.",
- "reason":"REQUIRED violations are not fixed in common MCUboot source code.",
- "count":1,
- "source_code": "#define __RAMLOAD_H__"
- }
- ]
- }
- }
- },
- "boot/bootutil/include/bootutil/crypto/ecdsa_p256.h":{
- "rules":{
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 4
- }
- }
- },
- "boot/bootutil/include/bootutil/crypto/ecdh_p256.h":{
- "rules":{
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- }
- }
- },
- "boot/bootutil/include/bootutil/image.h":{
- "rules":{
- "MISRA C-2012 Rule 8.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/include/bootutil/enc_key.h":{
- "rules":{
- "MISRA C-2012 Rule 8.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 8
- }
- }
- },
- "boot/cypress/MCUBootApp/config/mcuboot_crypto_config.h":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The mcuboot_crypto_config.h file is based on mbedtls config template file.",
- "count": 56
- },
- "MISRA C-2012 Rule 21.1": {
- "violations":[
- {
- "message":"Defining or undefining a reserved name \"_CRT_SECURE_NO_DEPRECATE\", which is an identifier or macro name beginning with an underscore.",
- "reason":" _CRT_SECURE_NO_DEPRECATE cannot be renamed, because it is using in many files of the mbedtls library.",
- "count":1,
- "source_code": "#define _CRT_SECURE_NO_DEPRECATE 1"
- }
- ]
- }
- }
- },
- "boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 1
- }
- }
- },
- "boot/cypress/MCUBootApp/config/custom_debug_uart_cfg.h":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 1
- }
- }
- },
- "boot/cypress/MCUBootApp/cy_security_cnt.c":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The mcuboot_crypto_config.h file is based on mbedtls config template file.",
- "count": 1
- }
- }
- },
- "boot/cypress/MCUBootApp/keys.c":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The mcuboot_crypto_config.h file is based on mbedtls config template file.",
- "count": 1
- }
- }
- },
- "boot/cypress/MCUBootApp/main.c":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The mcuboot_crypto_config.h file is based on mbedtls config template file.",
- "count": 1
- },
- "MISRA C-2012 Rule 10.4": {
- "violations":[
- {
- "message":"Essential type of the left hand operand \"1\" (boolean) is not the same as that of the right operand \"fih_eq(fih_rc, FIH_SUCCESS)\"(signed).",
- "reason":"fih_eq() is common MCUboot function.",
- "count":1,
- "source_code": "if (true == fih_eq(fih_rc, FIH_SUCCESS)) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "message": "Controlling expression \"!false\" is invariant.",
- "reason": "A violation occurs on \"while (true)\" code",
- "count": 3
- },
- "MISRA C-2012 Rule 21.6":{
- "violations":[
- {
- "message": "Using function \"fprintf\".",
- "reason": "fprintf function, which is used in default logging implementation of mcuboot is a part of standard input/output library",
- "count": 14
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/sysflash/sysflash.h":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 1
- }
- }
- },
- "boot/cypress/libs/watchdog":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 2
- }
- }
- },
- "boot/cypress/libs/watchdog/watchdog.h":{
- "rules":{
- "MISRA C-2012 Directive 4.10":{
- "reason": "Violation appears on the included library .h files.",
- "count": 1
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_psoc6":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 4
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_psoc6/cy_flash_map.c":{
- "rules":{
- "MISRA C-2012 Rule 21.6":{
- "violations":[
- {
- "message": "Using function \"fprintf\".",
- "reason": "fprintf function, which is used in default logging implementation of mcuboot is a part of standard input/output library",
- "count": 3
- }
- ]
- },
- "MISRA C-2012 Rule 10.8":{
- "reason": "The constant is defined in PDL library",
- "count": 2
- },
- "MISRA C-2012 Rule 14.3":{
- "violations":[
- {
- "message": "Execution cannot reach this statement: \";\".",
- "reason": "The violation occurs on while {true}.",
- "count": 1,
- "source_code": "FIH_PANIC; /* There is no appropriate error code */"
- }
- ]
- }
- }
- },
- "boot/cypress/cy_flash_pal/cy_flash_map.h":{
- "rules":{
- "MISRA C-2012 Rule 8.4":{
- "reason": "cy_flash_map.h is generated from json files.",
- "count": 1
- }
- }
- },
- "boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c":{
- "rules":{
- "MISRA C-2012 Rule 10.3":{
- "reason": "The function and \"anonymous enum\" are defined in PDL library",
- "count": 5
- }
- }
- },
- "boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.c":{
- "rules":{
- "MISRA C-2012 Rule 10.3":{
- "reason": "The function and \"anonymous enum\" are defined in PDL library",
- "count": 3
- },
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 1
- },
- "MISRA C-2012 Rule 21.2":{
- "reason": "_read(), _write() replace the default implementation in \"newlibc\".",
- "count": 4
- }
- }
- },
- "boot/cypress/libs/retarget_io_pdl/cy_retarget_io_pdl.h":{
- "rules":{
- "MISRA C-2012 Directive 4.10":{
- "reason": "Violation appears on the included library .h files.",
- "count": 1
- },
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 1
- }
- }
- },
- "boot/cypress/platforms/PSOC6/cycfg_system.c":{
- "rules":{
- "MISRA C-2012 Rule 10.3":{
- "reason": "The function and \"anonymous enum\" are defined in PDL library",
- "count": 3
- },
- "MISRA C-2012 Rule 20.9":{
- "reason": "The identifiers are defined in PDL library",
- "count": 8
- }
- }
- },
- "boot/cypress/platforms/PSOC6":{
- "rules":{
- "MISRA C-2012 Rule 3.1":{
- "reason": "The violations occur on the \"http://...\" substring in the comments.",
- "count": 21
- }
- }
- },
- "boot/bootutil/src/bootutil_misc.c":{
- "rules":{
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 10
- },
- "MISRA C-2012 Rule 15.7":{
- "message": "No non-empty terminating \"else\" statement.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 2.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 20.9":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 7
- },
- "MISRA C-2012 Rule 21.16":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 8.10":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 8.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 8.5":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/bootutil_priv.h":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/bootutil_public.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 12
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 26
- },
- "MISRA C-2012 Rule 11.8":{
- "violations":[
- {
- "message": "The type cast of the pointer expression \"buffer\" to type \"uint8_t *\" removes \"const\" qualifier from the pointed to type.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (p = (uint8_t *)buffer; len-- > 0; p++) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.2":{
- "violations":[
- {
- "message": "The condition clause expression of the for loop has persistent side-effects.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (p = (uint8_t *)buffer; len-- > 0; p++) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "violations":[
- {
- "message": "The condition \"rc == 1\" must be true.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "if (rc == BOOT_HOOK_REGULAR)"
- }
- ]
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 15.7":{
- "message": "No non-empty terminating \"else\" statement.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 16.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 16.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 6
- },
- "MISRA C-2012 Rule 16.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 16.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 2.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 8
- },
- "MISRA C-2012 Rule 7.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- }
- }
- },
- "boot/bootutil/src/caps.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 10
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 5
- },
- "MISRA C-2012 Rule 12.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- }
- }
- },
- "boot/bootutil/src/encrypted.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 9
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":7
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 19
- },
- "MISRA C-2012 Rule 11.8":{
- "violations":[
- {
- "message": "The type cast of the pointer expression \"bootutil_enc_key.key\" to type \"uint8_t *\" removes \"const\" qualifier from the pointed to type.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "cp = (uint8_t *)bootutil_enc_key.key;"
- }
- ]
- },
- "MISRA C-2012 Rule 14.2":{
- "violations":[
- {
- "message": "The third clause of the for loop has more than one persistent side-effect.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (off = 0; len > 0; off += BOOTUTIL_CRYPTO_SHA256_DIGEST_SIZE, ++counter) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 4
- },
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 5
- },
- "MISRA C-2012 Rule 20.9":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 21.14":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 7.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/image_ec256.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 4
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":1
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 6
- },
- "MISRA C-2012 Rule 11.8":{
- "violations":[
- {
- "message": "The type cast of the pointer expression \"bootutil_keys[key_id].key\" to type \"uint8_t *\" removes \"const\" qualifier from the pointed to type.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "pubkey = (uint8_t *)bootutil_keys[key_id].key;"
- }
- ]
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 4
- },
- "MISRA C-2012 Rule 21.14":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 8.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/image_validate.c":{
- "rules":{
- "MISRA C-2012 Rule 2.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 9
- },
- "MISRA C-2012 Rule 2.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 9
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":6
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 12
- },
- "MISRA C-2012 Rule 11.9":{
- "violations":[
- {
- "message": "Literal \"0\" shall not be used as null pointer constant.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- }
- ]
- },
- "MISRA C-2012 Rule 14.2":{
- "violations":[
- {
- "message": "The expression \"blk_sz\" used in the for loop clauses is modified in the loop body.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (off = 0; off < size; off += blk_sz) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "violations":[
- {
- "message": "The condition \"0\" cannot be true.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "if (!EXPECTED_SIG_LEN(len) || len > sizeof(buf)) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 21
- },
- "MISRA C-2012 Rule 15.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 6
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":4
- },
- "MISRA C-2012 Rule 8.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/loader.c":{
- "rules":{
- "MISRA C-2012 Directive 4.7":{
- "reason": "REQUIRED violations will not be fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 12
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":48
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 58
- },
- "MISRA C-2012 Rule 11.6":{
- "violations":[
- {
- "message": "The expression \"entry_val\" of type \"uintptr_t\" is cast to type \"void *\".",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "*entry = (void *) entry_val;"
- }
- ]
- },
- "MISRA C-2012 Rule 11.9":{
- "violations":[
- {
- "message": "Literal \"0\" shall not be used as null pointer constant.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- }
- ]
- },
- "MISRA C-2012 Rule 13.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 13.5":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 14.2":{
- "violations":[
- {
- "message": "The first clause of the for loop is not empty, does not declare a loop counter or has a side-effect other than to set the loop counter.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1,
- "source_code": "for (sect = 0, size = 0; sect < sect_count; sect++) {"
- }
- ]
- },
- "MISRA C-2012 Rule 14.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 7
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 22
- },
- "MISRA C-2012 Rule 15.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 16.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 16.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 16.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 17.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 2.2":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 20.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 20.9":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 15
- },
- "MISRA C-2012 Rule 21.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":33
- },
- "MISRA C-2012 Rule 5.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":1
- },
- "MISRA C-2012 Rule 8.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- },
- "boot/bootutil/src/swap_misc.c":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 36
- }
- }
- },
- "boot/bootutil/src/swap_status.c":{
- "rules":{
- "MISRA C-2012 Rule 21.6":{
- "violations":[
- {
- "message": "Using function \"fprintf\".",
- "reason": "fprintf function, which is used in default logging implementation of mcuboot is a part of standard input/output library",
- "count": 2
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status_misc.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "violations":[
- {
- "message": "The expression \"1\" of non-boolean essential type is being interpreted as a boolean value for the operator \"? :\".",
- "reason": "False-positive violation.",
- "count": 1,
- "source_code": "BOOT_SET_SWAP_INFO_M(swap_info, 0u, (uint8_t)BOOT_SWAP_TYPE_NONE);"
- }
- ]
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "BOOT_IMAGE_NUMBER is defined in common MCUboot source file",
- "count": 2
- },
- "MISRA C-2012 Rule 14.3":{
- "reason": "Ternary oprerator compares the constants.",
- "count": 3
- },
- "MISRA C-2012 Rule 21.6":{
- "violations":[
- {
- "message": "Using function \"fprintf\".",
- "reason": "fprintf function, which is used in default logging implementation of mcuboot is a part of standard input/output library",
- "count": 5
- }
- ]
- }
- }
- },
- "boot/bootutil/src/swap_status_part.c":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "reason": "BOOT_IMAGE_NUMBER is defined in common MCUboot source file",
- "count": 6
- },
- "MISRA C-2012 Rule 14.3":{
- "reason": "Ternary oprerator compares the constants.",
- "count": 8
- }
- }
- },
- "boot/bootutil/src/swap_scratch.c":{
- "rules":{
- "MISRA C-2012 Rule 10.1":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 4
- },
- "MISRA C-2012 Rule 10.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":16
- },
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 22
- },
- "MISRA C-2012 Rule 14.3":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 6
- },
- "MISRA C-2012 Rule 15.7":{
- "message": "No non-empty terminating \"else\" statement.",
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 2
- },
- "MISRA C-2012 Rule 20.9":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 5
- },
- "MISRA C-2012 Rule 21.6":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count":12
- },
- "MISRA C-2012 Rule 8.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- }
- }
- },
- "boot/bootutil/src/tlv.c":{
- "rules":{
- "MISRA C-2012 Rule 10.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 19
- },
- "MISRA C-2012 Rule 14.4":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 3
- },
- "MISRA C-2012 Rule 15.7":{
- "reason": "REQUIRED violations are not fixed in common MCUboot source code.",
- "count": 1
- }
- }
- }
- }
-}
diff --git a/boot/cypress/coverity/psoc062/misrac2012-custom.config b/boot/cypress/coverity/psoc062/misrac2012-custom.config
deleted file mode 100644
index 55d963e..0000000
--- a/boot/cypress/coverity/psoc062/misrac2012-custom.config
+++ /dev/null
@@ -1,8 +0,0 @@
-{
- "version": "2.0",
- "standard": "misrac2012",
- "title": "MISRA C-2012 All Rules",
- "deviations": [
-
- ]
-}
diff --git a/boot/cypress/cppcheck/MCUBootApp/ignore_files.list b/boot/cypress/cppcheck/MCUBootApp/ignore_files.list
deleted file mode 100644
index 22c4abd..0000000
--- a/boot/cypress/cppcheck/MCUBootApp/ignore_files.list
+++ /dev/null
@@ -1,16 +0,0 @@
-../../ext/mbedtls/crypto/library
-../../ext/mbedtls/library
-libs/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_CM0P
-libs/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source
-libs/mtb-pdl-cat1/drivers/source
-libs/mtb-pdl-cat1/devices/COMPONENT_CAT1B/templates/COMPONENT_MTB/COMPONENT_CM33/non-secure
-libs/mtb-pdl-cat1/devices/COMPONENT_CAT1B/source
-libs/mtb-hal-cat1/COMPONENT_PSOC6HAL/source
-libs/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/source
-libs/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/source/pin_packages
-libs/mtb-hal-cat1/COMPONENT_PSOC6HAL/COMPONENT_CAT1B/source/triggers
-../../ext/mbedtls/include/mbedtls/check_config.h
-boot/cypress/libs/mtb-pdl-cat1/drivers/include/cy_smif.h
-boot/cypress/libs/mtb-pdl-cat1/cmsis/include/cmsis_gcc.h
-boot/cypress/libs/mtb-pdl-cat1/drivers/include/cy_mcwdt.h
-ext/mbedtls/include/mbedtls/check_config.h
\ No newline at end of file
diff --git a/boot/cypress/cppcheck/MCUBootApp/suppress_messages.list b/boot/cypress/cppcheck/MCUBootApp/suppress_messages.list
deleted file mode 100644
index 7585e88..0000000
--- a/boot/cypress/cppcheck/MCUBootApp/suppress_messages.list
+++ /dev/null
@@ -1,5 +0,0 @@
-severity@id@message@file@line
-style@constVariable@Variable 'primary_slot_sectors' can be declared with const@boot/bootutil/src/loader.c@1984:33
-style@constVariable@Variable 'secondary_slot_sectors' can be declared with const@boot/bootutil/src/loader.c@1985:33
-style@redundantInitialization@Redundant initialization for 'align'. The initialized value is overwritten before it is read.@boot/bootutil/src/swap_status_part.c@439:11
-style@knownConditionTrueFalse@Condition 'rc!=0' is always false@boot/bootutil/src/loader.c@1198:12
diff --git a/boot/cypress/cppcheck/MCUBootApp/suppress_types.list b/boot/cypress/cppcheck/MCUBootApp/suppress_types.list
deleted file mode 100644
index 97431f4..0000000
--- a/boot/cypress/cppcheck/MCUBootApp/suppress_types.list
+++ /dev/null
@@ -1,7 +0,0 @@
-missingInclude
-variableScope
-unusedFunction
-duplicateValueTernary
-unreadVariable
-redundantInitialization
-unmatchedSuppression
diff --git a/boot/cypress/cppcheck/cppcheck-htmlreport.py b/boot/cypress/cppcheck/cppcheck-htmlreport.py
deleted file mode 100644
index afc7380..0000000
--- a/boot/cypress/cppcheck/cppcheck-htmlreport.py
+++ /dev/null
@@ -1,696 +0,0 @@
-#! /usr/bin/python3
-
-from __future__ import unicode_literals
-
-import io
-import sys
-import optparse
-import os
-import operator
-
-from collections import Counter
-from pygments import highlight
-from pygments.lexers import guess_lexer_for_filename
-from pygments.formatters import HtmlFormatter
-from xml.sax import parse as xml_parse
-from xml.sax import SAXParseException as XmlParseException
-from xml.sax.handler import ContentHandler as XmlContentHandler
-from xml.sax.saxutils import escape
-"""
-Turns a cppcheck xml file into a browsable html report along
-with syntax highlighted source code.
-"""
-
-STYLE_FILE = """
-body {
- font: 13px Arial, Verdana, Sans-Serif;
- margin: 0;
- width: auto;
-}
-
-h1 {
- margin: 10px;
-}
-
-#footer > p {
- margin: 4px;
-}
-
-.error {
- background-color: #ffb7b7;
-}
-
-.error2 {
- background-color: #faa;
- border: 1px dotted black;
- display: inline-block;
- margin-left: 4px;
-}
-
-.inconclusive {
- background-color: #B6B6B4;
-}
-
-.inconclusive2 {
- background-color: #B6B6B4;
- border: 1px dotted black;
- display: inline-block;
- margin-left: 4px;
-}
-
-div.verbose {
- display: inline-block;
- vertical-align: top;
- cursor: help;
-}
-
-div.verbose div.content {
- display: none;
- position: absolute;
- padding: 10px;
- margin: 4px;
- max-width: 40%;
- white-space: pre-wrap;
- border: 1px solid black;
- background-color: #FFFFCC;
- cursor: auto;
-}
-
-.highlight .hll {
- padding: 1px;
-}
-
-#header {
- border-bottom: thin solid #aaa;
-}
-
-#menu {
- float: left;
- margin-top: 5px;
- text-align: left;
- width: 150px;
- height: 75%;
- position: fixed;
- overflow: auto;
- z-index: 1;
-}
-
-#menu_index {
- float: left;
- margin-top: 5px;
- padding-left: 5px;
- text-align: left;
- width: 200px;
- height: 75%;
- position: fixed;
- overflow: auto;
- z-index: 1;
-}
-
-#menu > a {
- display: block;
- margin-left: 10px;
- font: 12px;
- z-index: 1;
-}
-
-#filename {
- margin-left: 10px;
- font: 12px;
- z-index: 1;
-}
-
-.highlighttable {
- background-color:white;
- z-index: 10;
- position: relative;
- margin: -10 px;
-}
-
-#content {
- background-color: white;
- -webkit-box-sizing: content-box;
- -moz-box-sizing: content-box;
- box-sizing: content-box;
- float: left;
- margin: 5px;
- margin-left: 10px;
- padding: 0 10px 10px 10px;
- width: 80%;
- padding-left: 150px;
-}
-
-#content_index {
- background-color: white;
- -webkit-box-sizing: content-box;
- -moz-box-sizing: content-box;
- box-sizing: content-box;
- float: left;
- margin: 5px;
- margin-left: 10px;
- padding: 0 10px 10px 10px;
- width: 80%;
- padding-left: 200px;
-}
-
-.linenos {
- border-right: thin solid #aaa;
- color: lightgray;
- padding-right: 6px;
-}
-
-#footer {
- border-top: thin solid #aaa;
- clear: both;
- font-size: 90%;
- margin-top: 5px;
-}
-
-#footer ul {
- list-style-type: none;
- padding-left: 0;
-}
-"""
-
-HTML_HEAD = """
-<!DOCTYPE html>
-<html lang="en">
- <head>
- <meta charset="utf-8">
- <title>Cppcheck - HTML report - %s</title>
- <link rel="stylesheet" href="style.css">
- <style>
-%s
- </style>
- <script language="javascript">
- function getStyle(el,styleProp) {
- if (el.currentStyle)
- var y = el.currentStyle[styleProp];
- else if (window.getComputedStyle)
- var y = document.defaultView.getComputedStyle(el,null).getPropertyValue(styleProp);
- return y;
- }
- function toggle() {
- var el = this.expandable_content;
- var mark = this.expandable_marker;
- if (el.style.display == "block") {
- el.style.display = "none";
- mark.innerHTML = "[+]";
- } else {
- el.style.display = "block";
- mark.innerHTML = "[-]";
- }
- }
- function init_expandables() {
- var elts = document.getElementsByClassName("expandable");
- for (var i = 0; i < elts.length; i++) {
- var el = elts[i];
- var clickable = el.getElementsByTagName("span")[0];
- var marker = clickable.getElementsByClassName("marker")[0];
- var content = el.getElementsByClassName("content")[0];
- var width = clickable.clientWidth - parseInt(getStyle(content, "padding-left")) - parseInt(getStyle(content, "padding-right"));
- content.style.width = width + "px";
- clickable.expandable_content = content;
- clickable.expandable_marker = marker;
- clickable.onclick = toggle;
- }
- }
- function set_class_display(c, st) {
- var elements = document.querySelectorAll('.' + c),
- len = elements.length;
- for (i = 0; i < len; i++) {
- elements[i].style.display = st;
- }
- }
- function toggle_class_visibility(id) {
- var box = document.getElementById(id);
- set_class_display(id, box.checked ? '' : 'none');
- }
- </script>
- </head>
- <body onload="init_expandables()">
- <div id="header">
- <h1>Cppcheck report - %s: %s </h1>
- </div>
- <div id="menu" dir="rtl">
- <p id="filename"><a href="index.html">Defects:</a> %s</p>
-"""
-
-HTML_HEAD_END = """
- </div>
- <div id="content">
-"""
-
-HTML_FOOTER = """
- </div>
- <div id="footer">
- <p>
- Cppcheck %s - a tool for static C/C++ code analysis</br>
- </br>
- Internet: <a href="http://cppcheck.net">http://cppcheck.net</a></br>
- IRC: <a href="irc://irc.freenode.net/cppcheck">irc://irc.freenode.net/cppcheck</a></br>
- <p>
- </div>
- </body>
-</html>
-"""
-
-HTML_ERROR = "<span class='error2'><--- %s</span>\n"
-HTML_INCONCLUSIVE = "<span class='inconclusive2'><--- %s</span>\n"
-
-HTML_EXPANDABLE_ERROR = "<div class='verbose expandable'><span class='error2'><--- %s <span class='marker'>[+]</span></span><div class='content'>%s</div></div>\n"""
-HTML_EXPANDABLE_INCONCLUSIVE = "<div class='verbose expandable'><span class='inconclusive2'><--- %s <span class='marker'>[+]</span></span><div class='content'>%s</div></div>\n"""
-
-# escape() and unescape() takes care of &, < and >.
-html_escape_table = {
- '"': """,
- "'": "'"
-}
-html_unescape_table = {v: k for k, v in html_escape_table.items()}
-
-
-def html_escape(text):
- return escape(text, html_escape_table)
-
-
-class AnnotateCodeFormatter(HtmlFormatter):
- errors = []
-
- def wrap(self, source, outfile):
- line_no = 1
- for i, t in HtmlFormatter.wrap(self, source, outfile):
- # If this is a source code line we want to add a span tag at the
- # end.
- if i == 1:
- for error in self.errors:
- if error['line'] == line_no:
- try:
- if error['inconclusive'] == 'true':
- # only print verbose msg if it really differs
- # from actual message
- if error.get('verbose') and (error['verbose'] != error['msg']):
- index = t.rfind('\n')
- t = t[:index] + HTML_EXPANDABLE_INCONCLUSIVE % (error['msg'], html_escape(error['verbose'].replace("\\012", '\n'))) + t[index + 1:]
- else:
- t = t.replace('\n', HTML_INCONCLUSIVE % error['msg'])
- except KeyError:
- if error.get('verbose') and (error['verbose'] != error['msg']):
- index = t.rfind('\n')
- t = t[:index] + HTML_EXPANDABLE_ERROR % (error['msg'], html_escape(error['verbose'].replace("\\012", '\n'))) + t[index + 1:]
- else:
- t = t.replace('\n', HTML_ERROR % error['msg'])
-
- line_no = line_no + 1
- yield i, t
-
-
-class CppCheckHandler(XmlContentHandler):
-
- """Parses the cppcheck xml file and produces a list of all its errors."""
-
- def __init__(self):
- XmlContentHandler.__init__(self)
- self.errors = []
- self.version = '1'
- self.versionCppcheck = ''
-
- def startElement(self, name, attributes):
- if name == 'results':
- self.version = attributes.get('version', self.version)
-
- if self.version == '1':
- self.handleVersion1(name, attributes)
- else:
- self.handleVersion2(name, attributes)
-
- def handleVersion1(self, name, attributes):
- if name != 'error':
- return
-
- self.errors.append({
- 'file': attributes.get('file', ''),
- 'line': int(attributes.get('line', 0)),
- 'locations': [{
- 'file': attributes.get('file', ''),
- 'line': int(attributes.get('line', 0)),
- }],
- 'id': attributes['id'],
- 'severity': attributes['severity'],
- 'msg': attributes['msg']
- })
-
- def handleVersion2(self, name, attributes):
- if name == 'cppcheck':
- self.versionCppcheck = attributes['version']
- if name == 'error':
- error = {
- 'locations': [],
- 'file': '',
- 'line': 0,
- 'id': attributes['id'],
- 'severity': attributes['severity'],
- 'msg': attributes['msg'],
- 'verbose': attributes.get('verbose')
- }
-
- if 'inconclusive' in attributes:
- error['inconclusive'] = attributes['inconclusive']
- if 'cwe' in attributes:
- error['cwe'] = attributes['cwe']
-
- self.errors.append(error)
- elif name == 'location':
- assert self.errors
- error = self.errors[-1]
- locations = error['locations']
- file = attributes['file']
- line = int(attributes['line'])
- if not locations:
- error['file'] = file
- error['line'] = line
- locations.append({
- 'file': file,
- 'line': line,
- 'info': attributes.get('info')
- })
-
-if __name__ == '__main__':
- # Configure all the options this little utility is using.
- parser = optparse.OptionParser()
- parser.add_option('--title', dest='title',
- help='The title of the project.',
- default='[project name]')
- parser.add_option('--file', dest='file',
- help='The cppcheck xml output file to read defects '
- 'from. Default is reading from stdin.')
- parser.add_option('--report-dir', dest='report_dir',
- help='The directory where the HTML report content is '
- 'written.')
- parser.add_option('--source-dir', dest='source_dir',
- help='Base directory where source code files can be '
- 'found.')
- parser.add_option('--source-encoding', dest='source_encoding',
- help='Encoding of source code.', default='utf-8')
-
- # Parse options and make sure that we have an output directory set.
- options, args = parser.parse_args()
-
- try:
- sys.argv[1]
- except IndexError: # no arguments give, print --help
- parser.print_help()
- quit()
-
- if not options.report_dir:
- parser.error('No report directory set.')
-
- # Get the directory where source code files are located.
- source_dir = os.getcwd()
- if options.source_dir:
- source_dir = options.source_dir
-
- # Get the stream that we read cppcheck errors from.
- input_file = sys.stdin
- if options.file:
- if not os.path.exists(options.file):
- parser.error('cppcheck xml file: %s not found.' % options.file)
- input_file = io.open(options.file, 'r')
- else:
- parser.error('No cppcheck xml file specified. (--file=)')
-
- # Parse the xml file and produce a simple list of errors.
- print('Parsing xml report.')
- try:
- contentHandler = CppCheckHandler()
- xml_parse(input_file, contentHandler)
- except XmlParseException as msg:
- print('Failed to parse cppcheck xml file: %s' % msg)
- sys.exit(1)
-
- # We have a list of errors. But now we want to group them on
- # each source code file. Lets create a files dictionary that
- # will contain a list of all the errors in that file. For each
- # file we will also generate a HTML filename to use.
- files = {}
- file_no = 0
- for error in contentHandler.errors:
- filename = error['file']
- if filename not in files.keys():
- files[filename] = {
- 'errors': [], 'htmlfile': str(file_no) + '.html'}
- file_no = file_no + 1
- files[filename]['errors'].append(error)
-
- # Make sure that the report directory is created if it doesn't exist.
- print('Creating %s directory' % options.report_dir)
- if not os.path.exists(options.report_dir):
- os.mkdir(options.report_dir)
-
- # Generate a HTML file with syntax highlighted source code for each
- # file that contains one or more errors.
- print('Processing errors')
-
- decode_errors = []
- for filename, data in sorted(files.items()):
- htmlfile = data['htmlfile']
- errors = []
-
- for error in data['errors']:
- for location in error['locations']:
- if filename == location['file']:
- newError = dict(error)
-
- del newError['locations']
- newError['line'] = location['line']
- if location.get('info'):
- newError['msg'] = location['info']
- newError['severity'] = 'information'
- del newError['verbose']
-
- errors.append(newError)
-
- lines = []
- for error in errors:
- lines.append(error['line'])
-
- if filename == '':
- continue
-
- source_filename = os.path.join(source_dir, filename)
- try:
- with io.open(source_filename, 'r', encoding=options.source_encoding) as input_file:
- content = input_file.read()
- except IOError:
- if (error['id'] == 'unmatchedSuppression'):
- continue # file not found, bail out
- else:
- sys.stderr.write("ERROR: Source file '%s' not found.\n" %
- source_filename)
- continue
- except UnicodeDecodeError:
- sys.stderr.write("WARNING: Unicode decode error in '%s'.\n" %
- source_filename)
- decode_errors.append(source_filename[2:]) # "[2:]" gets rid of "./" at beginning
- continue
-
- htmlFormatter = AnnotateCodeFormatter(linenos=True,
- style='colorful',
- hl_lines=lines,
- lineanchors='line',
- encoding=options.source_encoding)
- htmlFormatter.errors = errors
-
- with io.open(os.path.join(options.report_dir, htmlfile), 'w', encoding='utf-8') as output_file:
- output_file.write(HTML_HEAD %
- (options.title,
- htmlFormatter.get_style_defs('.highlight'),
- options.title,
- filename,
- filename.split('/')[-1]))
-
- for error in sorted(errors, key=lambda k: k['line']):
- output_file.write("<a href='%s#line-%d'> %s %s</a>" % (data['htmlfile'], error['line'], error['id'], error['line']))
-
- output_file.write(HTML_HEAD_END)
- try:
- lexer = guess_lexer_for_filename(source_filename, '')
- except:
- sys.stderr.write("ERROR: Couldn't determine lexer for the file' " + source_filename + " '. Won't be able to syntax highlight this file.")
- output_file.write("\n <tr><td colspan='4'> Could not generated content because pygments failed to retrieve the determine code type.</td></tr>")
- output_file.write("\n <tr><td colspan='4'> Sorry about this.</td></tr>")
- continue
-
- if options.source_encoding:
- lexer.encoding = options.source_encoding
-
- output_file.write(
- highlight(content, lexer, htmlFormatter).decode(
- options.source_encoding))
-
- output_file.write(HTML_FOOTER % contentHandler.versionCppcheck)
-
- print(' ' + filename)
-
- # Generate a master index.html file that will contain a list of
- # all the errors created.
- print('Creating index.html')
-
- with io.open(os.path.join(options.report_dir, 'index.html'),
- 'w') as output_file:
-
- stats_count = 0
- stats = []
- for filename, data in sorted(files.items()):
- for error in data['errors']:
- stats.append(error['id']) # get the stats
- stats_count += 1
-
- counter = Counter(stats)
-
- stat_html = []
- # the following lines sort the stat primary by value (occurrences),
- # but if two IDs occur equally often, then we sort them alphabetically by warning ID
- try:
- cnt_max = counter.most_common()[0][1]
- except IndexError:
- cnt_max = 0
-
- try:
- cnt_min = counter.most_common()[-1][1]
- except IndexError:
- cnt_min = 0
-
- stat_fmt = " <tr><td><input type='checkbox' onclick='toggle_class_visibility(this.id)' id='{}' name='{}' checked></td><td>{}</td><td>{}</td></tr>"
- for occurrences in reversed(range(cnt_min, cnt_max + 1)):
- for _id in [k for k, v in sorted(counter.items()) if v == occurrences]:
- stat_html.append(stat_fmt.format(_id, _id, dict(counter.most_common())[_id], _id))
-
- output_file.write(HTML_HEAD.replace('id="menu" dir="rtl"', 'id="menu_index"', 1).replace("Defects:", "Defect summary;", 1) % (options.title, '', options.title, '', ''))
- output_file.write(' <table>')
- output_file.write(' <tr><th>Show</th><th>#</th><th>Defect ID</th></tr>')
- output_file.write(''.join(stat_html))
- output_file.write(' <tr><td></td><td>' + str(stats_count) + '</td><td>total</td></tr>')
- output_file.write(' </table>')
- output_file.write(' <a href="stats.html">Statistics</a></p>')
- output_file.write(HTML_HEAD_END.replace("content", "content_index", 1))
- output_file.write(' <table>\n')
-
- output_file.write(
- ' <tr><th>Line</th><th>Id</th><th>CWE</th><th>Severity</th><th>Message</th></tr>')
- for filename, data in sorted(files.items()):
- if filename in decode_errors: # don't print a link but a note
- output_file.write("\n <tr><td colspan='4'>%s</td></tr>" % (filename))
- output_file.write("\n <tr><td colspan='4'> Could not generated due to UnicodeDecodeError</td></tr>")
- else:
- if filename.endswith('*'): # assume unmatched suppression
- output_file.write(
- "\n <tr><td colspan='4'>%s</td></tr>" %
- (filename))
- else:
- output_file.write(
- "\n <tr><td colspan='4'><a href='%s'>%s</a></td></tr>" %
- (data['htmlfile'], filename))
-
- for error in sorted(data['errors'], key=lambda k: k['line']):
- error_class = ''
- try:
- if error['inconclusive'] == 'true':
- error_class = 'class="inconclusive"'
- error['severity'] += ", inconcl."
- except KeyError:
- pass
-
- try:
- if error['cwe']:
- cwe_url = "<a href='https://cwe.mitre.org/data/definitions/" + error['cwe'] + ".html'>" + error['cwe'] + "</a>"
- except KeyError:
- cwe_url = ""
-
- if error['severity'] == 'error':
- error_class = 'class="error"'
- if error['id'] == 'missingInclude':
- output_file.write(
- '\n <tr class="%s"><td></td><td>%s</td><td></td><td>%s</td><td>%s</td></tr>' %
- (error['id'], error['id'], error['severity'], error['msg']))
- elif (error['id'] == 'unmatchedSuppression') and filename.endswith('*'):
- output_file.write(
- '\n <tr class="%s"><td></td><td>%s</td><td></td><td>%s</td><td %s>%s</td></tr>' %
- (error['id'], error['id'], error['severity'], error_class,
- error['msg']))
- else:
- output_file.write(
- '\n <tr class="%s"><td><a href="%s#line-%d">%d</a></td><td>%s</td><td>%s</td><td>%s</td><td %s>%s</td></tr>' %
- (error['id'], data['htmlfile'], error['line'], error['line'],
- error['id'], cwe_url, error['severity'], error_class,
- error['msg']))
-
- output_file.write('\n </table>')
- output_file.write(HTML_FOOTER % contentHandler.versionCppcheck)
-
- if (decode_errors):
- sys.stderr.write("\nGenerating html failed for the following files: " + ' '.join(decode_errors))
- sys.stderr.write("\nConsider changing source-encoding (for example: \"htmlreport ... --source-encoding=\"iso8859-1\"\"\n")
-
- print('Creating style.css file')
- with io.open(os.path.join(options.report_dir, 'style.css'),
- 'w') as css_file:
- css_file.write(STYLE_FILE)
-
- print("Creating stats.html (statistics)\n")
- stats_countlist = {}
-
- for filename, data in sorted(files.items()):
- if (filename == ''):
- continue
- stats_tmplist = []
- for error in sorted(data['errors'], key=lambda k: k['line']):
- stats_tmplist.append(error['severity'])
-
- stats_countlist[filename] = dict(Counter(stats_tmplist))
-
- # get top ten for each severity
- SEVERITIES = "error", "warning", "portability", "performance", "style", "unusedFunction", "information", "missingInclude", "internal"
-
- with io.open(os.path.join(options.report_dir, 'stats.html'), 'w') as stats_file:
-
- stats_file.write(HTML_HEAD.replace('id="menu" dir="rtl"', 'id="menu_index"', 1).replace("Defects:", "Back to summary", 1) % (options.title, '', options.title, 'Statistics', ''))
- stats_file.write(HTML_HEAD_END.replace("content", "content_index", 1))
-
- for sev in SEVERITIES:
- _sum = 0
- stats_templist = {}
-
- # if the we have an style warning but we are checking for
- # portability, we have to skip it to prevent KeyError
- try:
- for filename in stats_countlist:
- try: # also bail out if we have a file with no sev-results
- _sum += stats_countlist[filename][sev]
- stats_templist[filename] = (int)(stats_countlist[filename][sev]) # file : amount,
- except KeyError:
- continue
- # don't print "0 style" etc, if no style warnings were found
- if (_sum == 0):
- break
- except KeyError:
- continue
- stats_file.write("<p>Top 10 files for " + sev + " severity, total findings: " + str(_sum) + "</br>\n")
-
- # sort, so that the file with the most severities per type is first
- stats_list_sorted = sorted(stats_templist.items(), key=operator.itemgetter(1, 0), reverse=True)
- it = 0
- LENGTH = 0
-
- for i in stats_list_sorted: # printing loop
- # for aesthetics: if it's the first iteration of the loop, get
- # the max length of the number string
- if (it == 0):
- LENGTH = len(str(i[1])) # <- length of longest number, now get the difference and try to make other numbers align to it
-
- stats_file.write(" " * 3 + str(i[1]) + " " * (1 + LENGTH - len(str(i[1]))) + "<a href=\"" + files[i[0]]['htmlfile'] + "\"> " + i[0] + "</a></br>\n")
- it += 1
- if (it == 10): # print only the top 10
- break
- stats_file.write("</p>\n")
-
- print("\nOpen '" + options.report_dir + "/index.html' to see the results.")
diff --git a/boot/cypress/cppcheck/cppcheck.sh b/boot/cypress/cppcheck/cppcheck.sh
deleted file mode 100644
index 689e338..0000000
--- a/boot/cypress/cppcheck/cppcheck.sh
+++ /dev/null
@@ -1,162 +0,0 @@
-#!/bin/bash
-#
-# this must be the first non-commented line in this script. It ensures
-# bash doesn't choke on \r on Windows
-(set -o igncr) 2>/dev/null && set -o igncr; # this comment is needed
-
-#
-# This script does static code analysis using Cppcheck tool
-# Copyright (c) 2019 Cypress Semiconductor.
-#
-
-# It performs Cppcheck code analysis with following inputs
-# 1. CypressBootloader/sources - Code analysis is done on all the sources of CypressBootloader.
-# 2. Additional source files to be analyzed are grabbed from config file that is provided as a first argument to the script.
-# 3. Files to be ignored are grabbed from config file that is provided as a first argument to the script.
-# 4. To ignore a file its name need to be added to the config file with word "ignore" as perfix
-# 5. To add any additional files, apart the files from CypressBootloader/sources, those names need
-# to be added in a config file.
-# Example
-# A). add below entries in cpp_check.dat file
-# ignore cy_bootloader_hw.c
-# file1.c
-# file2.c
-# ignore cy_bootloader_services.c
-# B). invoke cpp_check shell script
-# cpp_check.sh cpp_check.dat
-#
-# Above example performs Cppcheck analysis on CypressBootloader/sources, ignore cy_bootloader_hw.c, file1.c, file2.c and ignores cy_bootloader_services.c
-
-
-app_name="$1"
-platform="$2"
-app_defines="$3"
-app_includes="$4"
-CPP_CHECK_FILES="$5"
-scope="$6"
-buildcfg="$7"
-
-if [[ ${scope} != "" ]]; then
- SCOPE="--enable=${scope}"
-else
- SCOPE=""
-fi
-
-#Retrieve list of files need to be ignored
-while IFS= read -r line
-do
- CPP_CHECK_IGNORE_FILES="$CPP_CHECK_IGNORE_FILES -i $line"
-done < "cppcheck/${app_name}/ignore_files.list"
-
-#Retrieve list of cppcheck directives
-while IFS= read -r line
-do
- CPP_CHECK_SUPPRESS="$CPP_CHECK_SUPPRESS --suppress=$line"
-done < "cppcheck/${app_name}/suppress_types.list"
-
-echo "-------------------------------------------"
-echo "Suppress options:" "$CPP_CHECK_SUPPRESS"
-echo "-------------------------------------------"
-echo "Additional files:" "$CPP_CHECK_FILES"
-echo "-------------------------------------------"
-echo "Ignoring files:" "$CPP_CHECK_IGNORE_FILES"
-echo "-------------------------------------------"
-echo "CppCheck scope of messages defined with option " ${SCOPE}
-echo "-------------------------------------------"
-echo "Run CppCheck for platform" ${platform}
-echo "-------------------------------------------"
-echo "Defines passed to CppCheck:"
-echo ${app_defines}
-echo "-------------------------------------------"
-echo "Include dirs passed to CppCheck:"
-echo ${app_includes}
-echo "-------------------------------------------"
-
-mkdir -p cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_html
-
-dos2unix cppcheck/${app_name}/suppress_messages.list
-
-dos2unix cppcheck/${app_name}/ignore_files.list
-
-#Generate file with list of additional files for cppcheck
-CPP_CHECK_FILES_LIST_FILE=cppcheck/${app_name}/cpp-check-files.list
-echo ${CPP_CHECK_FILES} | sed -e "s+ +\n+g" > ${CPP_CHECK_FILES_LIST_FILE}
-
-#Generate xml file
-cppcheck ${SCOPE} ${CPP_CHECK_SUPPRESS} -D__GNUC__ -D${platform} ${app_defines} ${app_includes} --file-list=${CPP_CHECK_FILES_LIST_FILE} ${CPP_CHECK_IGNORE_FILES} \
- --xml 2> cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.xml
-
-#Generate html file
-python cppcheck/cppcheck-htmlreport.py --file=cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.xml --report-dir=cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_html --title=${app_name}
-
-cppcheck ${SCOPE} ${CPP_CHECK_SUPPRESS} -D__GNUC__ -D${platform} ${app_defines} ${app_includes} --file-list=${CPP_CHECK_FILES_LIST_FILE} ${CPP_CHECK_IGNORE_FILES} \
- --template="{severity}\n{id}\n{message}\n{file}\n{line}:{column}\n{code}\n" 2> cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full
-
-#Generate csv file
-echo "severity@id@message@file@line" > cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.csv
-while IFS= read -r line
-do
- read -r line2
- read -r line3
- read -r line4
- read -r line5
- line4=$(echo $line4 | sed 's/.*\\cy_mcuboot\\//' | tr '\\' '/')
- if grep -xq "${line}@${line2}@${line3}@${line4}@${line5}" cppcheck/${app_name}/suppress_messages.list
- then
- :;#suppress current warning
- else
- if grep -xq "${line4}" cppcheck/${app_name}/ignore_files.list
- then
- :;#suppress current warning
- else
- echo ${line}@${line2}@${line3}@${line4}@${line5}
- fi
- fi
- read -r line
- read -r line
- read -r line
-done \
-< cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full \
->>cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.csv
-
-#Generate log file
-while IFS= read -r line
-do
- read -r line2
- read -r line3
- read -r line4
- read -r line5
- line4=$(echo $line4 | sed 's/.*\\cy_mcuboot\\//' | tr '\\' '/')
- if grep -xq "${line}@${line2}@${line3}@${line4}@${line5}" cppcheck/${app_name}/suppress_messages.list
- then
- read -r line
- read -r line
- read -r line
- else
- if grep -xq "${line4}" cppcheck/${app_name}/ignore_files.list
- then
- read -r line
- read -r line
- read -r line
- else
- echo ${line} : ${line2}
- echo ${line3}
- echo "${line4} (${line5})"
- read -r line
- echo ${line}
- read -r line
- echo ${line}
- read -r line
- echo "-------------------------------------------"
- fi
- fi
-done \
-< cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full \
-> cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.log
-
-rm cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full
-cat cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.log
-
-ERRORS=$(( $(wc -l cppcheck/${app_name}/results/${platform}/${buildcfg}/cppcheck_report_${scope}.csv | cut -d' ' -f1) -1 ))
-echo "${app_name} CPPCHECK FOR ${platform} KIT FOUND $ERRORS ERRORS"
-exit $ERRORS
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_multi2_psvp.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_multi2_psvp.json
deleted file mode 100644
index f913ed7..0000000
--- a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_multi2_psvp.json
+++ /dev/null
@@ -1,57 +0,0 @@
-{
- "external_flash": [
- {
- "model": "FM25W04",
- "mode": "XIP"
- }
- ],
- "boot_and_upgrade":
- {
- "bootloader": {
- "address": {
- "description": "Address of the bootloader",
- "value": "0x60000000"
- },
- "size": {
- "description": "Size of the bootloader",
- "value": "0x20000"
- }
- },
- "application_1": {
- "address": {
- "description": "Address of the application primary slot",
- "value": "0x60020000"
- },
- "size": {
- "description": "Size of the application primary slot",
- "value": "0xF000"
- },
- "upgrade_address": {
- "description": "Address of the application secondary slot",
- "value": "0x6003E000"
- },
- "upgrade_size": {
- "description": "Size of the application secondary slot",
- "value": "0xF000"
- }
- },
- "application_2": {
- "address": {
- "description": "Address of the application primary slot",
- "value": "0x6002F000"
- },
- "size": {
- "description": "Size of the application primary slot",
- "value": "0xF000"
- },
- "upgrade_address": {
- "description": "Address of the application secondary slot",
- "value": "0x6004D000"
- },
- "upgrade_size": {
- "description": "Size of the application secondary slot",
- "value": "0xF000"
- }
- }
- }
-}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_single_psvp.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_single_psvp.json
deleted file mode 100644
index 8c98f08..0000000
--- a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_single_psvp.json
+++ /dev/null
@@ -1,39 +0,0 @@
-{
- "external_flash": [
- {
- "model": "FM25W04",
- "mode": "XIP"
- }
- ],
- "boot_and_upgrade":
- {
- "bootloader": {
- "address": {
- "description": "Address of the bootloader",
- "value": "0x60000000"
- },
- "size": {
- "description": "Size of the bootloader",
- "value": "0x20000"
- }
- },
- "application_1": {
- "address": {
- "description": "Address of the application primary slot",
- "value": "0x60020000"
- },
- "size": {
- "description": "Size of the application primary slot",
- "value": "0x20000"
- },
- "upgrade_address": {
- "description": "Address of the application secondary slot",
- "value": "0x60040000"
- },
- "upgrade_size": {
- "description": "Size of the application secondary slot",
- "value": "0x20000"
- }
- }
- }
-}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2_psvp.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2_psvp.json
deleted file mode 100644
index d226156..0000000
--- a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2_psvp.json
+++ /dev/null
@@ -1,83 +0,0 @@
-{
- "external_flash": [
- {
- "model": "FM25W04",
- "mode": "XIP"
- }
- ],
- "boot_and_upgrade":
- {
- "bootloader": {
- "address": {
- "description": "Address of the bootloader",
- "value": "0x60000000"
- },
- "size": {
- "description": "Size of the bootloader",
- "value": "0x20000"
- }
- },
- "service_app": {
- "address": {
- "description": "Address of the service application",
- "value": "0x60070000"
- },
- "size": {
- "description": "Size of the service application",
- "value": "0x8000"
- },
- "params_address": {
- "description": "Address of the service application input parameters",
- "value": "0x60078000"
- },
- "params_size": {
- "description": "Size of the service application input parameters",
- "value": "0x400"
- },
- "desc_address": {
- "description": "Address of the service application descriptor",
- "value": "0x60078400"
- },
- "desc_size": {
- "description": "Size of the service application descriptor",
- "value": "0x20"
- }
- },
- "application_1": {
- "address": {
- "description": "Address of the application primary slot",
- "value": "0x60020000"
- },
- "size": {
- "description": "Size of the application primary slot",
- "value": "0xF000"
- },
- "upgrade_address": {
- "description": "Address of the application secondary slot",
- "value": "0x6003E000"
- },
- "upgrade_size": {
- "description": "Size of the application secondary slot",
- "value": "0xF000"
- }
- },
- "application_2": {
- "address": {
- "description": "Address of the application primary slot",
- "value": "0x6002F000"
- },
- "size": {
- "description": "Size of the application primary slot",
- "value": "0xF000"
- },
- "upgrade_address": {
- "description": "Address of the application secondary slot",
- "value": "0x6004D000"
- },
- "upgrade_size": {
- "description": "Size of the application secondary slot",
- "value": "0xF000"
- }
- }
- }
-}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single_psvp.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single_psvp.json
deleted file mode 100644
index d46066d..0000000
--- a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single_psvp.json
+++ /dev/null
@@ -1,65 +0,0 @@
-{
- "external_flash": [
- {
- "model": "FM25W04",
- "mode": "XIP"
- }
- ],
- "boot_and_upgrade":
- {
- "bootloader": {
- "address": {
- "description": "Address of the bootloader",
- "value": "0x60000000"
- },
- "size": {
- "description": "Size of the bootloader",
- "value": "0x20000"
- }
- },
- "service_app": {
- "address": {
- "description": "Address of the service application",
- "value": "0x60070000"
- },
- "size": {
- "description": "Size of the service application",
- "value": "0x8000"
- },
- "params_address": {
- "description": "Address of the service application input parameters",
- "value": "0x60078000"
- },
- "params_size": {
- "description": "Size of the service application input parameters",
- "value": "0x400"
- },
- "desc_address": {
- "description": "Address of the service application descriptor",
- "value": "0x60078400"
- },
- "desc_size": {
- "description": "Size of the service application descriptor",
- "value": "0x20"
- }
- },
- "application_1": {
- "address": {
- "description": "Address of the application primary slot",
- "value": "0x60020000"
- },
- "size": {
- "description": "Size of the application primary slot",
- "value": "0x20000"
- },
- "upgrade_address": {
- "description": "Address of the application secondary slot",
- "value": "0x60040000"
- },
- "upgrade_size": {
- "description": "Size of the application secondary slot",
- "value": "0x20000"
- }
- }
- }
-}
\ No newline at end of file
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2_psvp.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2_psvp.json
deleted file mode 100644
index 7a64e43..0000000
--- a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2_psvp.json
+++ /dev/null
@@ -1,99 +0,0 @@
-{
- "external_flash": [
- {
- "model": "FM25W04",
- "mode": "XIP"
- }
- ],
- "boot_and_upgrade":
- {
- "bootloader": {
- "address": {
- "description": "Address of the bootloader",
- "value": "0x60000000"
- },
- "size": {
- "description": "Size of the bootloader",
- "value": "0x20000"
- },
- "scratch_address": {
- "description": "Address of the scratch area",
- "value": "0x6007E000"
- },
- "scratch_size": {
- "description": "Size of the scratch area",
- "value": "0x2000"
- },
- "status_address": {
- "description": "Address of the swap status partition",
- "value": "0x60058000"
- },
- "status_size": {
- "description": "Size of the swap status partition",
- "value": "0x14000"
- }
- },
- "service_app": {
- "address": {
- "description": "Address of the service application",
- "value": "0x60070000"
- },
- "size": {
- "description": "Size of the service application",
- "value": "0x8000"
- },
- "params_address": {
- "description": "Address of the service application input parameters",
- "value": "0x60078000"
- },
- "params_size": {
- "description": "Size of the service application input parameters",
- "value": "0x400"
- },
- "desc_address": {
- "description": "Address of the service application descriptor",
- "value": "0x60078400"
- },
- "desc_size": {
- "description": "Size of the service application descriptor",
- "value": "0x20"
- }
- },
- "application_1": {
- "address": {
- "description": "Address of the application primary slot",
- "value": "0x60020000"
- },
- "size": {
- "description": "Size of the application primary slot",
- "value": "0xE000"
- },
- "upgrade_address": {
- "description": "Address of the application secondary slot",
- "value": "0x6003C000"
- },
- "upgrade_size": {
- "description": "Size of the application secondary slot",
- "value": "0xE000"
- }
- },
- "application_2": {
- "address": {
- "description": "Address of the application primary slot",
- "value": "0x6002E000"
- },
- "size": {
- "description": "Size of the application primary slot",
- "value": "0xE000"
- },
- "upgrade_address": {
- "description": "Address of the application secondary slot",
- "value": "0x6004A000"
- },
- "upgrade_size": {
- "description": "Size of the application secondary slot",
- "value": "0xE000"
- }
- }
- }
-}
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single_psvp.json b/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single_psvp.json
deleted file mode 100644
index addeee1..0000000
--- a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single_psvp.json
+++ /dev/null
@@ -1,81 +0,0 @@
-{
- "external_flash": [
- {
- "model": "FM25W04",
- "mode": "XIP"
- }
- ],
- "boot_and_upgrade":
- {
- "bootloader": {
- "address": {
- "description": "Address of the bootloader",
- "value": "0x60000000"
- },
- "size": {
- "description": "Size of the bootloader",
- "value": "0x20000"
- },
- "scratch_address": {
- "description": "Address of the scratch area",
- "value": "0x6007E000"
- },
- "scratch_size": {
- "description": "Size of the scratch area",
- "value": "0x2000"
- },
- "status_address": {
- "description": "Address of the swap status partition",
- "value": "0x60060000"
- },
- "status_size": {
- "description": "Size of the swap status partition",
- "value": "0xC000"
- }
- },
- "service_app": {
- "address": {
- "description": "Address of the service application",
- "value": "0x60070000"
- },
- "size": {
- "description": "Size of the service application",
- "value": "0x8000"
- },
- "params_address": {
- "description": "Address of the service application input parameters",
- "value": "0x60078000"
- },
- "params_size": {
- "description": "Size of the service application input parameters",
- "value": "0x400"
- },
- "desc_address": {
- "description": "Address of the service application descriptor",
- "value": "0x60078400"
- },
- "desc_size": {
- "description": "Size of the service application descriptor",
- "value": "0x20"
- }
- },
- "application_1": {
- "address": {
- "description": "Address of the application primary slot",
- "value": "0x60020000"
- },
- "size": {
- "description": "Size of the application primary slot",
- "value": "0x20000"
- },
- "upgrade_address": {
- "description": "Address of the application secondary slot",
- "value": "0x60040000"
- },
- "upgrade_size": {
- "description": "Size of the application secondary slot",
- "value": "0x20000"
- }
- }
- }
-}
\ No newline at end of file
diff --git a/boot/cypress/libs/cmsis b/boot/cypress/libs/cmsis
new file mode 160000
index 0000000..ce02f64
--- /dev/null
+++ b/boot/cypress/libs/cmsis
@@ -0,0 +1 @@
+Subproject commit ce02f641ebc22103402260f9bb95698fd14086f1
diff --git a/boot/cypress/libs/core-lib b/boot/cypress/libs/core-lib
index 7e6892e..1c1cb8a 160000
--- a/boot/cypress/libs/core-lib
+++ b/boot/cypress/libs/core-lib
@@ -1 +1 @@
-Subproject commit 7e6892ee1eeabc8f6c25fbf02cb00ff43bd3ac73
+Subproject commit 1c1cb8af402ac6c63966d73adbb62cc6ff0ecea5
diff --git a/boot/cypress/libs/cy-mbedtls-acceleration b/boot/cypress/libs/cy-mbedtls-acceleration
index 79a9d8e..b61f07e 160000
--- a/boot/cypress/libs/cy-mbedtls-acceleration
+++ b/boot/cypress/libs/cy-mbedtls-acceleration
@@ -1 +1 @@
-Subproject commit 79a9d8e5e0a98531d8b17f94f3f040359e9cdd9d
+Subproject commit b61f07e62037c00eabf60afbf048ee254bc99a1e
diff --git a/boot/cypress/libs/mtb-hal-cat1 b/boot/cypress/libs/mtb-hal-cat1
index 708a6b2..ac09163 160000
--- a/boot/cypress/libs/mtb-hal-cat1
+++ b/boot/cypress/libs/mtb-hal-cat1
@@ -1 +1 @@
-Subproject commit 708a6b2542f0d8814c129a3141e78fd265826a0b
+Subproject commit ac0916378f819a273a44165784effed839cba95c
diff --git a/boot/cypress/libs/mtb-pdl-cat1 b/boot/cypress/libs/mtb-pdl-cat1
index 3c6aebd..e851dc2 160000
--- a/boot/cypress/libs/mtb-pdl-cat1
+++ b/boot/cypress/libs/mtb-pdl-cat1
@@ -1 +1 @@
-Subproject commit 3c6aebd2f3238b578329bfb8a6c5a0e138bd5c7b
+Subproject commit e851dc2c1a9f7acaf29aad83c7e65ccd48cec453
diff --git a/boot/cypress/platforms.mk b/boot/cypress/platforms.mk
index 281c34c..8122d94 100644
--- a/boot/cypress/platforms.mk
+++ b/boot/cypress/platforms.mk
@@ -26,21 +26,22 @@
include host.mk
# supported platforms
-PLATFORMS := PSOC_062_2M PSOC_062_1M PSOC_062_512K CYW20829
+PSOC_06X := PSOC_061_2M PSOC_061_1M PSOC_061_512K PSOC_062_2M PSOC_062_1M PSOC_062_512K PSOC_063_1M
+PLATFORMS := $(PSOC_06X) CYW20829
ifneq ($(filter $(PLATFORM), $(PLATFORMS)),)
else
$(error Not supported platform: '$(PLATFORM)')
endif
-ifeq ($(PLATFORM), $(filter $(PLATFORM), PSOC_062_2M PSOC_062_1M PSOC_062_512K))
+ifeq ($(PLATFORM), $(filter $(PLATFORM), $(PSOC_06X)))
FAMILY := PSOC6
else ifeq ($(PLATFORM), CYW20829)
FAMILY := CYW20829
endif
# include family related makefile into build
-include platforms/$(FAMILY)/$(FAMILY).mk
+include platforms/$(FAMILY).mk
DEFINES += $(PLATFORM)
DEFINES += $(FAMILY)
@@ -58,6 +59,6 @@
$(info FAMILY <-> $(FAMILY))
$(info PLATFORM <-- $(PLATFORM))
$(info PLATFORMS <-> $(PLATFORMS))
-$(info PLATFORM_DEFINES <-> $(PLATFORM_DEFINES))
-$(info PLATFORM_SUFFIX <-- $(PLATFORM_SUFFIX))
+$(info PLATFORM_DEFINES --> $(PLATFORM_DEFINES))
+$(info PSOC_06X <-> $(PSOC_06X))
endif
diff --git a/boot/cypress/platforms/CYW20829/cybsp.c b/boot/cypress/platforms/BSP/CYW20829/cybsp.c
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cybsp.c
rename to boot/cypress/platforms/BSP/CYW20829/cybsp.c
diff --git a/boot/cypress/platforms/CYW20829/cybsp.h b/boot/cypress/platforms/BSP/CYW20829/cybsp.h
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cybsp.h
rename to boot/cypress/platforms/BSP/CYW20829/cybsp.h
diff --git a/boot/cypress/platforms/CYW20829/cybsp_doc.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cybsp_doc.h
rename to boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h
diff --git a/boot/cypress/platforms/CYW20829/cybsp_types.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_types.h
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cybsp_types.h
rename to boot/cypress/platforms/BSP/CYW20829/cybsp_types.h
diff --git a/boot/cypress/platforms/CYW20829/cycfg.c b/boot/cypress/platforms/BSP/CYW20829/cycfg.c
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg.c
rename to boot/cypress/platforms/BSP/CYW20829/cycfg.c
diff --git a/boot/cypress/platforms/CYW20829/cycfg.h b/boot/cypress/platforms/BSP/CYW20829/cycfg.h
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg.h
rename to boot/cypress/platforms/BSP/CYW20829/cycfg.h
diff --git a/boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.c
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.c
rename to boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.c
diff --git a/boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.h
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg_connectivity_bt.h
rename to boot/cypress/platforms/BSP/CYW20829/cycfg_connectivity_bt.h
diff --git a/boot/cypress/platforms/CYW20829/cycfg_notices.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg_notices.h
rename to boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h
diff --git a/boot/cypress/platforms/CYW20829/cycfg_pins.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg_pins.c
rename to boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c
diff --git a/boot/cypress/platforms/CYW20829/cycfg_pins.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg_pins.h
rename to boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h
diff --git a/boot/cypress/platforms/CYW20829/cycfg_routing.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.c
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg_routing.c
rename to boot/cypress/platforms/BSP/CYW20829/cycfg_routing.c
diff --git a/boot/cypress/platforms/CYW20829/cycfg_routing.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg_routing.h
rename to boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h
diff --git a/boot/cypress/platforms/CYW20829/cycfg_system.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.c
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg_system.c
rename to boot/cypress/platforms/BSP/CYW20829/cycfg_system.c
diff --git a/boot/cypress/platforms/CYW20829/cycfg_system.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.h
similarity index 100%
rename from boot/cypress/platforms/CYW20829/cycfg_system.h
rename to boot/cypress/platforms/BSP/CYW20829/cycfg_system.h
diff --git a/boot/cypress/platforms/CYW20829/qspi_config.cfg b/boot/cypress/platforms/BSP/CYW20829/qspi_config.cfg
similarity index 100%
rename from boot/cypress/platforms/CYW20829/qspi_config.cfg
rename to boot/cypress/platforms/BSP/CYW20829/qspi_config.cfg
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c
new file mode 100644
index 0000000..77d11a3
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c
@@ -0,0 +1,485 @@
+/***************************************************************************//**
+* \file ns_start_cyw20829.c
+* \version 1.1
+*
+* The cyw20829 startup source.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_device.h"
+#if defined (CY_DEVICE_CYW20829)
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stddef.h>
+
+#include "startup_cat1b.h"
+#include "cy_sysint.h"
+#include "cy_syspm.h"
+#include "cy_syslib.h"
+#include "cmsis_compiler.h"
+
+CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.6', 3, \
+'Checked manually. The definition is a part of linker script or application.');
+CY_MISRA_DEVIATE_BLOCK_START('ARRAY_VS_SINGLETON', 1, \
+'Checked manually. Using pointer as an array will not corrupt or misinterpret adjacent memory locations.');
+CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 18.1', 3, \
+'Checked manually. Dereferencing a pointer to one beyond the end of an array will not result in undefined behaviour.');
+CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 18.3', 1, \
+'Checked manually. Attempting to make comparisons between pointers will not result in undefined behaviour.');
+
+#if defined (__ARMCC_VERSION)
+extern uint32_t Region$$Table$$Base;
+extern uint32_t Region$$Table$$Limit;
+typedef void(*pGenericFunction)(uint8_t *pSrc, uint8_t* pDst, uint32_t len); /* typedef for the generic function pointers */
+#endif
+
+__WEAK interrupt_type void Reset_Handler(void);
+interrupt_type void MemManage_Handler(void);
+interrupt_type void BusFault_Handler(void);
+interrupt_type void UsageFault_Handler(void);
+__WEAK interrupt_type void SVC_Handler(void);
+interrupt_type void DebugMon_Handler(void);
+__WEAK interrupt_type void PendSV_Handler(void);
+__WEAK interrupt_type void SysTick_Handler(void);
+interrupt_type void InterruptHandler(void);
+interrupt_type void NMIException_Handler(void);
+interrupt_type void HardFault_Handler(void);
+void delay_infinite(void);
+void SysLib_FaultHandler(uint32_t const *faultStackAddr);
+__WEAK void cy_toolchain_init(void);
+
+extern int main(void);
+
+#if defined (__ARMCC_VERSION)
+void __attribute__((optnone)) Cy_RuntimeInit(void);
+#else
+void Cy_RuntimeInit(void);
+#endif
+
+#if defined(__ARMCC_VERSION)
+extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for (default) One Region model */
+interrupt_type extern void __main(void);
+typedef void(* ExecFuncPtrRw)(void) interrupt_type;
+ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#elif defined (__GNUC__)
+extern unsigned int __StackTop;
+extern uint32_t __StackLimit;
+typedef void(* interrupt_type ExecFuncPtrRw)(void);
+ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#elif defined (__ICCARM__)
+extern unsigned int CSTACK$$Limit; /* for (default) One Region model */
+interrupt_type extern void __cmain();
+ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN)));
+#else
+ #error "An unsupported toolchain"
+#endif /* (__ARMCC_VERSION) */
+
+void SysLib_FaultHandler(uint32_t const *faultStackAddr)
+{
+ Cy_SysLib_FaultHandler(faultStackAddr);
+}
+
+// Exception Vector Table & Handlers
+//----------------------------------------------------------------
+interrupt_type void NMIException_Handler(void)
+{
+ __asm volatile(
+ "bkpt #10\n"
+ "B .\n"
+ );
+}
+
+interrupt_type void HardFault_Handler(void)
+{
+ __asm (
+ "MRS R0, CONTROL\n"
+ "TST R0, #2\n"
+ "ITE EQ\n"
+ "MRSEQ R0, MSP\n"
+ "MRSNE R0, PSP\n"
+ "B SysLib_FaultHandler\n"
+ );
+}
+
+interrupt_type void MemManage_Handler(void) {while(true){}}
+interrupt_type void BusFault_Handler(void) {while(true){}}
+interrupt_type void UsageFault_Handler(void) {while(true){}}
+__WEAK interrupt_type void SVC_Handler(void) {while(true){}}
+interrupt_type void DebugMon_Handler(void) {while(true){}}
+__WEAK interrupt_type void PendSV_Handler(void) {while(true){}}
+__WEAK interrupt_type void SysTick_Handler(void) {while(true){}}
+
+interrupt_type void InterruptHandler(void)
+{
+ __asm volatile(
+ "bkpt #1\n"
+ "B .\n"
+ );
+}
+
+ExecFuncPtr __ns_vector_table[] __VECTOR_TABLE_ATTRIBUTE = {
+ (ExecFuncPtr)&__INITIAL_SP,
+ (ExecFuncPtr)Reset_Handler, // initial PC/Reset
+ (ExecFuncPtr)NMIException_Handler,
+ (ExecFuncPtr)HardFault_Handler,
+ (ExecFuncPtr)MemManage_Handler, // Memory Manage Fault
+ (ExecFuncPtr)BusFault_Handler, // Bus Fault
+ (ExecFuncPtr)UsageFault_Handler, // Usage Fault
+ 0, // Secire Fault
+ 0, // RESERVED
+ 0, // RESERVED
+ 0, // RESERVED
+ (ExecFuncPtr)SVC_Handler, // SVC
+ 0, // debug
+ 0, // RESERVED
+ (ExecFuncPtr)PendSV_Handler, // Pend SV
+ (ExecFuncPtr)SysTick_Handler, // Secure systick
+ /* External interrupts */
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler,
+ (ExecFuncPtr)InterruptHandler
+};
+
+
+/* Provide empty __WEAK implementation for the low-level initialization
+ routine required by the RTOS-enabled applications.
+ clib-support library provides FreeRTOS-specific implementation:
+ https://github.com/Infineon/clib-support */
+void cy_toolchain_init(void);
+__WEAK void cy_toolchain_init(void)
+{
+}
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+/* GCC: newlib crt0 _start executes software_init_hook.
+ The cy_toolchain_init hook provided by clib-support library must execute
+ after static data initialization and before static constructors. */
+void software_init_hook();
+void software_init_hook()
+{
+ cy_toolchain_init();
+}
+#elif defined(__ICCARM__)
+/* Initialize data section */
+void __iar_data_init3(void);
+
+/* Call the constructors of all global objects */
+void __iar_dynamic_initialization(void);
+
+/* Define strong version to return zero for __iar_program_start
+ to skip data sections initialization (__iar_data_init3). */
+int __low_level_init(void);
+int __low_level_init(void)
+{
+ return 0;
+}
+#else
+/**/
+#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */
+
+
+// Reset Handler
+__WEAK interrupt_type void Reset_Handler(void)
+{
+ /* Disable I cache */
+ ICACHE0->CTL = ICACHE0->CTL & (~ICACHE_CTL_CA_EN_Msk);
+
+ /* Enable ECC */
+ //ICACHE0->CTL = ICACHE0->CTL | ICACHE_CTL_ECC_EN_Msk;
+
+ /* Enable I cache */
+ ICACHE0->CTL = ICACHE0->CTL | ICACHE_CTL_CA_EN_Msk;
+
+ __disable_irq();
+
+ for (uint32_t count = 0; count < VECTORTABLE_SIZE; count++)
+ {
+ __ns_vector_table_rw[count] =__ns_vector_table[count];
+ }
+
+ SCB->VTOR = (uint32_t)__ns_vector_table_rw;
+ __DMB();
+
+#ifdef CY_PDL_FLASH_BOOT
+#if !defined (__ARMCC_VERSION)
+ bootstrapInit();
+#endif
+#endif
+ SystemInit();
+
+#if defined(__ICCARM__)
+ /* Initialize data section */
+ __iar_data_init3();
+
+ /* Initialization hook for RTOS environment */
+ cy_toolchain_init();
+
+ /* Call the constructors of all global objects */
+ __iar_dynamic_initialization();
+#endif
+
+ __PROGRAM_START();
+}
+
+CY_MISRA_BLOCK_END('MISRA C-2012 Rule 18.3');
+CY_MISRA_BLOCK_END('MISRA C-2012 Rule 18.1');
+CY_MISRA_BLOCK_END('ARRAY_VS_SINGLETON');
+CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6');
+
+#endif /* defined (CY_DEVICE_CYW20829) */
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c
new file mode 100644
index 0000000..2594560
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c
@@ -0,0 +1,212 @@
+/***************************************************************************//**
+* \file ns_system_cyw20829.c
+* \version 1.1
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cy_device.h"
+
+#if defined (CY_DEVICE_CYW20829)
+#include <stdbool.h>
+#include "system_cyw20829.h"
+#include "cy_syslib.h"
+#include "cy_wdt.h"
+#include "cy_sysclk.h"
+#include "cy_syspm.h"
+
+CY_MISRA_DEVIATE_BLOCK_START('ARRAY_VS_SINGLETON', 1, \
+'Checked manually. Using pointer as an array will not corrupt or misinterpret adjacent memory locations.');
+CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 18.1', 1, \
+'Checked manually. Dereferencing a pointer to one beyond the end of an array will not result in undefined behaviour.');
+CY_MISRA_DEVIATE_BLOCK_START('MISRA C-2012 Rule 18.3', 1, \
+'Checked manually. Attempting to make comparisons between pointers will not result in undefined behaviour.');
+CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.6', 2, \
+'Checked manually. The definition is a part of linker script or application.');
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (48000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (48000000UL)
+
+/** Default system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (48000000UL)
+
+/** Holds the CLK_HF0 system core clock. */
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_AhbFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
+uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) /
+ CY_DELAY_1K_THRESHOLD;
+
+uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) /
+ CY_DELAY_1M_THRESHOLD);
+
+
+#if defined (CY_PDL_FLASH_BOOT)
+
+#if !defined (__ARMCC_VERSION)
+void bootstrapInit(void)
+{
+ typedef struct
+ {
+ uint32_t* dest;
+ uint32_t wlen;
+ } __bootstrap_zero_table_t;
+
+ extern const __bootstrap_zero_table_t __bootstrapzero_table_start__;
+ extern const __bootstrap_zero_table_t __bootstrapzero_table_end__;
+
+ /* Initialize .cy_l1bss section to zero */
+ for (__bootstrap_zero_table_t const* pTable = &__bootstrapzero_table_start__; pTable < &__bootstrapzero_table_end__; ++pTable)
+ {
+ for(uint32_t i=0u; i<pTable->wlen; ++i)
+ {
+ pTable->dest[i] = 0u;
+ }
+ }
+}
+#endif
+#endif /* CY_PDL_FLASH_BOOT */
+
+void SystemInit_CAT1B_CM33(void)
+{
+ /* Release reset for all groups IP except group 0 */
+ (void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U); /* typecast void to suppress a compiler warning about unused return value */
+ (void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U); /* typecast void to suppress a compiler warning about unused return value */
+
+ (void)Cy_SysClk_PeriGroupSetSlaveCtl(1, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU); /* typecast void to suppress a compiler warning about unused return value */
+ (void)Cy_SysClk_PeriGroupSetSlaveCtl(2, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU); /* typecast void to suppress a compiler warning about unused return value */
+ (void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL, 0xFFFFFFFFU); /* typecast void to suppress a compiler warning about unused return value */
+
+ Cy_PDL_Init(CY_DEVICE_CFG);
+ (void)Cy_SystemInit(); /* typecast void to suppress a compiler warning about unused return value */
+
+ if(CY_SYSPM_WARM_BOOT_MODE == Cy_SysPm_GetBootMode())
+ {
+ /* Unfreeze the IO's which are frozen during DEEPSLEEP-RAM and DEEPSLEEP-OFF Entry */
+ if(Cy_SysPm_DeepSleepIoIsFrozen())
+ {
+ Cy_SysPm_DeepSleepIoUnfreeze();
+ }
+ }
+ else
+ {
+ /* Reset BT IP only during cold boot */
+ (void)Cy_SysClk_PeriGroupSetSlaveCtl(3, CY_SYSCLK_PERI_GROUP_SL_CTL2, 0x0U); /* typecast void to suppress a compiler warning about unused return value */
+ }
+
+ /* Unlock and disable WDT */
+ Cy_WDT_Unlock();
+ Cy_WDT_Disable();
+
+ SystemCoreClockUpdate();
+}
+
+void SystemInit(void)
+{
+ SystemInit_CAT1B_CM33();
+};
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function.
+ */
+ __NOP(); /* No operation */
+}
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pathFreqHz;
+ uint32_t clkHfPath;
+
+ /* Get frequency for the high-frequency clock # 0 */
+ clkHfPath = CY_SYSCLK_CLK_CORE_HF_PATH_NUM;
+
+ pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+ SystemCoreClock = pathFreqHz;
+
+ cy_Hfclk0FreqHz = SystemCoreClock;
+
+ /* Get frequency for the high-frequency clock # 2 , whcih is used for PERI PCLK*/
+ clkHfPath = CY_SYSCLK_CLK_PERI_HF_PATH_NUM;
+
+ pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+ cy_PeriClkFreqHz = pathFreqHz;
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqHz = SystemCoreClock;
+ cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+
+ /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
+ cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
+}
+
+CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6');
+CY_MISRA_BLOCK_END('MISRA C-2012 Rule 18.3');
+CY_MISRA_BLOCK_END('MISRA C-2012 Rule 18.1');
+CY_MISRA_BLOCK_END('ARRAY_VS_SINGLETON');
+
+#endif /* defined (CY_DEVICE_CYW20829) */
+/* [] END OF FILE */
+
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h b/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h
new file mode 100644
index 0000000..9bd6e46
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h
@@ -0,0 +1,60 @@
+/***************************************************************************//**
+* \file startup_cat1b.h
+* \version 1.1
+*
+* \brief Common startup header file for CAT1B devices. This file provides
+* declarations for secure and non-secure vector table.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+#ifndef STARTUP_CAT1B_H_
+#define STARTUP_CAT1B_H_
+
+#if defined (CY_DEVICE_CYW20829) /* Declarations for CYW20829 */
+
+#include "cyw20829_config.h"
+
+#define CM33_FIXED_EXP_NR (15u)
+#define VECTORTABLE_SIZE (MXCM33_SYSTEM_INT_NR + CM33_FIXED_EXP_NR + 1u) /* +1 is for Stack pointer */
+#define VECTORTABLE_ALIGN (512) /* alignment for 85 entries (85x4=340) is 512 bytes */
+
+#if defined(__ARMCC_VERSION)
+ #define interrupt_type __attribute__((interrupt))
+ typedef void(* ExecFuncPtrRw)(void) interrupt_type;
+ typedef void(* const ExecFuncPtr)(void) interrupt_type; /* typedef for the function pointers in the vector table */
+ extern ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".bss.noinit.RESET_RAM"))) __attribute__((aligned(VECTORTABLE_ALIGN))); /**< Non-secure vector table in flash/ROM */
+#elif defined (__GNUC__)
+ #define interrupt_type __attribute__((interrupt))
+ typedef void(* interrupt_type ExecFuncPtrRw)(void);
+ typedef void(* interrupt_type ExecFuncPtr)(void) ; /* typedef for the function pointers in the vector table */
+ extern ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".ram_vectors"))) __attribute__((aligned(VECTORTABLE_ALIGN))); /**< Non-secure vector table in flash/ROM */
+#elif defined (__ICCARM__)
+ #define interrupt_type __irq
+ typedef interrupt_type void(* ExecFuncPtrRw)(void) ;
+ typedef interrupt_type void(* const ExecFuncPtr)(void) ; /* typedef for the function pointers in the vector table */
+ extern ExecFuncPtrRw __ns_vector_table_rw[VECTORTABLE_SIZE] __attribute__( ( section(".intvec_ram"))) __attribute__((aligned(VECTORTABLE_ALIGN))); /**< Non-secure vector table in flash/ROM */
+#else
+ #error "An unsupported toolchain"
+#endif /* (__ARMCC_VERSION) */
+extern ExecFuncPtr __ns_vector_table[]; /**< Non-secure vector table in non-secure SRAM */
+#endif /* CY_DEVICE_CYW20829 */
+
+#endif /* STARTUP_CAT1B_H_ */
+
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h b/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h
new file mode 100644
index 0000000..0c4ec1d
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h
@@ -0,0 +1,45 @@
+/***************************************************************************//**
+* \file system_cat1b.h
+* \version 1.1
+*
+* \brief CAT1B Device system header file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+#ifndef _SYSTEM_CAT1B_H_
+#define _SYSTEM_CAT1B_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "system_cyw20829.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_CAT1B_H_ */
+
+
+/* [] END OF FILE */
+
+
+
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/system_cyw20829.h b/boot/cypress/platforms/BSP/CYW20829/system/system_cyw20829.h
new file mode 100644
index 0000000..b422865
--- /dev/null
+++ b/boot/cypress/platforms/BSP/CYW20829/system/system_cyw20829.h
@@ -0,0 +1,301 @@
+/***************************************************************************//**
+* \file system_cyw20829.h
+* \version 1.1
+*
+* \brief Device system header file.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#ifndef _SYSTEM_CYW20829_H_
+#define _SYSTEM_CYW20829_H_
+
+/**
+* \addtogroup group_system_config_cm33
+* \{
+* Provides device startup, system configuration, and linker script files.
+* The system startup provides the followings features:
+* - \ref group_system_config_device_memory_definition_cm33
+* - \ref group_system_config_device_initialization_cm33
+* - \ref group_system_config_heap_stack_config_cm33
+* - \ref group_system_config_default_handlers_cm33
+* - \ref group_system_config_device_vector_table_cm33
+*
+* \section group_system_config_configuration_cm33 Configuration Considerations
+*
+* \subsection group_system_config_device_memory_definition_cm33 Device Memory Definition
+* Allocation of different types of memory such as the ROM, flash and RAM etc. for the CPU is defined by the linker scripts.
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see warnings during the build process. To eliminate build
+* warnings in your project, you can simply comment out or remove the relevant
+* code in the linker file.
+*
+* <b>For CYW20829</b>
+*
+* <b>ARM GCC</b>\n
+* The ROM, flash and RAM sections for the CPU are defined in the linker file:
+* 'cyw20829_ns_flash_cbus.ld', where 'ns' indicates that the
+* linker script file is for non-secure image.
+* For devices without security extension, there will be only one linker file and it
+* is always non-secure.
+*
+* Memory sections are for the GNU GCC ARM tool set is defined in the linker file
+* cyw20829_ns_flash_cbus.ld. Following are the important memory sections for the User/Application image.
+*
+* Memory sections are for the GNU GCC ARM tool set is defined in the linker file
+* \<device\>_ns.sct. Following are the important memory sections for the User/Application image.
+* \code
+* code (rx) : ORIGIN = CODE_VMA, LENGTH = CODE_BS_SIZE Starting address and the size of Non-secure bootstrap code
+* bsData (rwx) : ORIGIN = DATA_BS_VMA, LENGTH = DATA_BS_SIZE Starting address and the size of Non-secure bootstrap data
+* appCodeRam (rx) : ORIGIN = DATA_CBUS_VMA, LENGTH = DATA_SIZE Starting address and the size of Non-secure application ram functions
+* data (rwx) : ORIGIN = DATA_VMA, LENGTH = DATA_SIZE Starting address and the size of Non-secure application data
+* xip (rx) : ORIGIN = XIP_VMA, LENGTH = XIP_SIZE Starting address and the size of Non-secure application code
+* \endcode
+*
+* \note In CYW20829, the Bootstrap memory is used to place the startup code along with SMIF driver in the ram area. The size requirement for Bootstrap may vary
+* depending on the number of functions that are linked from SMIF driver. When more functions are linked, you may see linker error.
+* In order to fix this you need to increase Bootstarp memory size in the ram by modifying the value of BOOTSTRAP_OFFSET_RAM.\n
+* E.g. if linker error suggests to increase by 8192 bytes, then you need to move the starting address of the bootstrap memory up by 8192 bytes as shown below \n
+* BOOTSTRAP_OFFSET_RAM = 0x0001E000; Old value\n
+* BOOTSTRAP_OFFSET_RAM = 0x0001C000; New value\n
+* Because of the change in the bootstrap size, you may also need to move the application start address in the flash. If you see a linker error after above change,
+* then you need to modify the application code offset APPCODE_OFFSET_FLASH in the flash.\n
+* E.g. if linker error suggests 256 bytes overlap of .appText LMA with .bootstrapText LMA, you need to move the application start offset in the flash
+* down by 256 bytes as shown below\n
+* APPCODE_OFFSET_FLASH = 0x00002200; Old value\n
+* APPCODE_OFFSET_FLASH = 0x00002300; New value
+*
+* <b>ARM Compiler</b>\n
+* The ROM, flash and RAM sections for the CPU are defined in the linker file:
+* 'cyw20829_ns_flash_cbus.sct', where 'ns' indicates that the
+* linker script file is for non-secure image.
+* For devices without security extension, there will be only one linker file and it
+* is always non-secure.
+*
+* Memory sections are for the GNU GCC ARM tool set is defined in the linker file
+* cyw20829_ns_flash_cbus.sct. Following are the important memory sections for the User/Application image.
+* \code
+* bootstrapText_vma Starting address of bootstrap code
+* bootstrapText_size Size of memory reserved for Bootstrap code
+* bootstrapData_vma Starting address of Bootstrap data
+* appText_vma Stating address of application code
+* appData_vma Stating address of application data
+* \endcode
+*
+* <b>IAR</b>\n
+* The ROM, flash and RAM sections for the CPU are defined in the linker file:
+* 'cyw20829_ns_flash_cbus.icf', where 'ns' indicates that the
+* linker script file is for non-secure image.
+* For devices without security extension, there will be only one linker file and it
+* is always non-secure.
+*
+* Memory sections are for the GNU GCC ARM tool set is defined in the linker file
+* cyw20829_ns_flash_cbus.icf. Following are the important memory sections for the User/Application image.
+* \code
+* define region CODE_region = mem:[from CODE_VMA size CODE_BS_SIZE]; Bootstrap code region and size
+* define region DATA_BS_region = mem:[from DATA_BS_VMA size DATA_BS_SIZE]; Bootstrap data region and size
+* define region DATA_region = mem:[from DATA_VMA size DATA_SIZE]; Application data region and size
+* define region XIP_region = mem:[from XIP_VMA size XIP_SIZE]; Application code (xip) region and size
+* \endcode
+*
+* \subsection group_system_config_device_initialization_cm33 Device Initialization
+* <b>CM33 Without ARM TrustZone Support:</b><br/>
+* Below MSC describes the simplified startup sequence starting from reset release of the core. As soon as the reset
+* is released, the execution starts form the ROM interrupt vector table reset vector. The ROM code initializes the basic
+* clock needed to access and configure MMIO registers and then sets up debug port so that the debugger can be attached.
+* After it finishes all the necessary initialization, it reads the bootstrap (part of non secure application image)
+* location, size from TOC2 header and loads the bootstrap code into SRAM.
+*
+* Before switching execution to the non-secure application code, the ROM code needs to initialize the stack pointer
+* MSP_NS for the non-secure code. This value is picked form the first entry in the non-secure bootstrap's vector
+* table __ns_vector_table. Once the non-secure stack is initialized, the ROM code will call the non-secure code entry
+* point which is nothing but the Reset_Handler. Address of this function is picked form the second entry in the non-secure
+* vector table __ns_vector_table and type casting it to function pointer.
+*
+* In the non-secure Reset_Handler, the vector table is copied to RAM area and then the address of the vector table is set
+* to VTOR register. This calls SystemInit function which internally calls Cy_PDL_Init, Cy_SystemInit and SystemCoreClockUpdate
+* functions. Then it calls C runtime initialization function which calls main function of the application code.
+*
+* Below sequence diagram captures the initialization process in the startup code.
+* 
+*
+* \subsection group_system_config_heap_stack_config_cm33 Heap and Stack Configuration
+* By default, the stack size is set to 0x00001000 and the entire remaining ram is used for the heap
+*
+* \subsubsection group_system_config_heap_stack_config_gcc_cm33 ARM GCC
+* - <b>Editing source code files for non-secure image</b>\n
+* The stack and heap sizes are defined in the linker script file: 'cyw20829_ns_flash_cbus.ld'.
+* Change the stack size by modifying the following line:\n
+* \code STACK_SIZE = 0x00001000; \endcode
+* Remaining free RAM is used as heap.
+*
+* \subsubsection group_system_config_heap_stack_config_arm_cm33 ARM Compiler
+* - <b>Editing source code files for non-secure image</b>\n
+* The stack sizes are defined in the linker script file: 'cyw20829_ns_flash_cbus.sct'.
+* Change the stack by modifying the following lines:\n
+* \code #define STACK_SIZE 0x00001000 \endcode
+* Remaining free RAM is used as heap.
+*
+* \subsubsection group_system_config_heap_stack_config_iar_cm33 IAR
+* - <b>Editing source code files for non-secure image</b>\n
+* The stack and heap sizes are defined in the linker script file: 'cyw20829_ns_flash_cbus.icf'.
+* Change the stack size by modifying the following line:\n
+* \code define symbol STACK_SIZE = 0x00001000; \endcode
+* Remaining free RAM is used as heap.
+*
+* \subsection group_system_config_default_handlers_cm33 Default Interrupt Handlers Definition
+* The default interrupt handler functions are dummy handler in the startup file.\n
+* Below is the default handler for the non-secure interrupts:\n
+* \code interrupt_type void InterruptHandler(void) {
+* while(1);
+* } \endcode
+*
+* \subsection group_system_config_device_vector_table_cm33 Vectors Table Copy from ROM/Flash to RAM
+* This process uses memory sections defined in the linker script. The startup code copies the
+* default vector table contents to the non-secure SRAM region specified by the linker script.
+* APIs are provided in the sysint driver to hook user implemented handler replacing the default
+* handler for the corresponding interrupt.
+*
+* Following tables provide the address of the default and non-secure SRAM interrupt vector
+* table for different supported compilers.
+* \subsubsection group_system_config_device_vector_table_gcc_cm33 ARM GCC
+* The linker script file is 'cyw20829_ns_flash_cbus.ld'.
+* For non-secure world, it uses the following variable.\n
+* Copy interrupt vectors from ROM/flash to RAM: \n
+* From: \code __ns_vector_table \endcode
+* To: \code __ns_vector_table_rw \endcode
+* The vector table address (and the vector table itself) are defined in the
+* ns_start_<device>.c startup file corresponding to non-secure world.
+* The code in these files copies the vector table from ROM/Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_mdk_cm33 ARM Compiler
+* The linker script file is 'cyw20829_ns_flash_cbus.sct'.
+* For non-secure world, it uses the following variable.\n
+* Copy interrupt vectors from ROM/flash to RAM: \n
+* From: \code __ns_vector_table \endcode
+* To: \code __ns_vector_table_rw \endcode
+* The vector table address (and the vector table itself) are defined in the
+* ns_start_<device>.c startup file corresponding to non-secure world.
+* The code in these files copies the vector table from ROM/Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_iar_cm33 IAR
+* The linker script file is 'cyw20829_ns_flash_cbus.icf'.
+* For non-secure world, it uses the following variable.\n
+* Copy interrupt vectors from ROM/flash to RAM: \n
+* From: \code __ns_vector_table \endcode
+* To: \code __ns_vector_table_rw \endcode
+* The vector table address (and the vector table itself) are defined in the
+* ns_start_<device>.c startup file corresponding to non-secure worlds.
+* The code in these files copies the vector table from ROM/Flash to RAM.
+*
+* \section group_system_config_changelog_cm33 Changelog
+* <table class="doxtable">
+* <tr>
+* <th>Version</th>
+* <th>Changes</th>
+* <th>Reason for Change</th>
+* </tr>
+* <tr>
+* <td>1.1</td>
+* <td>Restructured documentation and internal function behaviour.</td>
+* <td>User experience enhancement.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+*
+* \defgroup group_system_config_macro_cm33 Macros
+* \{
+* \defgroup group_system_config_system_macro_cm33 System Macros
+* \}
+*
+* \}
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Include files
+*******************************************************************************/
+#include <stdint.h>
+
+#define CY_SYSTEM_CPU_CM33 1UL
+
+/*******************************************************************************
+* Global preprocessor symbols/macros ('define')
+*******************************************************************************/
+
+/*******************************************************************************
+*
+* START OF USER SETTINGS HERE
+* ===========================
+*
+* All lines with '<<<' can be set by user.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_system_config_system_macro_cm33
+* \{
+*/
+#if (CY_SYSTEM_CPU_CM33 == 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M33 startup driver identifier */
+ #define CY_STARTUP_M33_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
+#endif /* (CY_SYSTEM_CPU_CM33 == 1UL) */
+/** \} group_system_config_system_macro_cm33 */
+
+
+/** \cond */
+void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+extern void Cy_SystemInit(void);
+extern void bootstrapInit(void);
+
+extern uint32_t cy_delayFreqHz;
+extern uint32_t cy_delayFreqKhz;
+extern uint8_t cy_delayFreqMhz;
+
+extern uint32_t SystemCoreClock;
+extern uint32_t cy_Hfclk0FreqHz;
+extern uint32_t cy_PeriClkFreqHz;
+extern uint32_t cy_AhbFreqHz;
+
+/** \endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_CYW20829_H_ */
+
+
+/* [] END OF FILE */
+
+
+
diff --git a/boot/cypress/platforms/PSOC6/bsp.h b/boot/cypress/platforms/BSP/PSOC6/bsp.h
similarity index 100%
rename from boot/cypress/platforms/PSOC6/bsp.h
rename to boot/cypress/platforms/BSP/PSOC6/bsp.h
diff --git a/boot/cypress/platforms/PSOC6/cycfg.c b/boot/cypress/platforms/BSP/PSOC6/cycfg.c
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg.c
rename to boot/cypress/platforms/BSP/PSOC6/cycfg.c
diff --git a/boot/cypress/platforms/PSOC6/cycfg.h b/boot/cypress/platforms/BSP/PSOC6/cycfg.h
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg.h
rename to boot/cypress/platforms/BSP/PSOC6/cycfg.h
diff --git a/boot/cypress/platforms/PSOC6/cycfg_clocks.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.c
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg_clocks.c
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.c
diff --git a/boot/cypress/platforms/PSOC6/cycfg_clocks.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.h
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg_clocks.h
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.h
diff --git a/boot/cypress/platforms/PSOC6/cycfg_peripherals.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.c
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg_peripherals.c
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.c
diff --git a/boot/cypress/platforms/PSOC6/cycfg_peripherals.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.h
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg_peripherals.h
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.h
diff --git a/boot/cypress/platforms/PSOC6/cycfg_pins.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.c
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg_pins.c
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_pins.c
diff --git a/boot/cypress/platforms/PSOC6/cycfg_pins.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.h
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg_pins.h
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_pins.h
diff --git a/boot/cypress/platforms/PSOC6/cycfg_routing.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_routing.c
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg_routing.c
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_routing.c
diff --git a/boot/cypress/platforms/PSOC6/cycfg_routing.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_routing.h
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg_routing.h
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_routing.h
diff --git a/boot/cypress/platforms/PSOC6/cycfg_system.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_system.c
similarity index 99%
rename from boot/cypress/platforms/PSOC6/cycfg_system.c
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_system.c
index cf3f4e7..fac7a2b 100644
--- a/boot/cypress/platforms/PSOC6/cycfg_system.c
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg_system.c
@@ -25,6 +25,7 @@
********************************************************************************/
#include "cycfg_system.h"
+#include "cy_ble_clk.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
diff --git a/boot/cypress/platforms/PSOC6/cycfg_system.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_system.h
similarity index 100%
rename from boot/cypress/platforms/PSOC6/cycfg_system.h
rename to boot/cypress/platforms/BSP/PSOC6/cycfg_system.h
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S
new file mode 100644
index 0000000..c3427af
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S
@@ -0,0 +1,404 @@
+/**************************************************************************//**
+ * @file startup_psoc6_01_cm0plus.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0plus Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
+ .long NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
+ .long NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
+ .long NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
+ .long NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
+ .long NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
+ .long NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
+ .long NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
+ .long NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
+ .long NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
+ .long NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
+ .long NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
+ .long NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
+ .long NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
+ .long NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
+ .long NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
+ .long NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
+ .long NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
+ .long NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
+ .long NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
+ .long NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
+ .long NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
+ .long NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
+ .long NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
+ .long NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
+ .long NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
+ .long NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
+ .long NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
+ .long NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
+ .long NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
+ .long NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
+ .long NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /*
+ * Device startup customization
+ *
+ * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+ * because this function is executed as the first instruction in the ResetHandler.
+ * The PDL is also not initialized to use the proper register offsets.
+ * The user of this function is responsible for initializing the PDL and resources before using them.
+ */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ bl main
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+.L_API_call:
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CM0+ NVIC Mux input 0 */
+ def_irq_handler NvicMux1_IRQHandler /* CM0+ NVIC Mux input 1 */
+ def_irq_handler NvicMux2_IRQHandler /* CM0+ NVIC Mux input 2 */
+ def_irq_handler NvicMux3_IRQHandler /* CM0+ NVIC Mux input 3 */
+ def_irq_handler NvicMux4_IRQHandler /* CM0+ NVIC Mux input 4 */
+ def_irq_handler NvicMux5_IRQHandler /* CM0+ NVIC Mux input 5 */
+ def_irq_handler NvicMux6_IRQHandler /* CM0+ NVIC Mux input 6 */
+ def_irq_handler NvicMux7_IRQHandler /* CM0+ NVIC Mux input 7 */
+ def_irq_handler NvicMux8_IRQHandler /* CM0+ NVIC Mux input 8 */
+ def_irq_handler NvicMux9_IRQHandler /* CM0+ NVIC Mux input 9 */
+ def_irq_handler NvicMux10_IRQHandler /* CM0+ NVIC Mux input 10 */
+ def_irq_handler NvicMux11_IRQHandler /* CM0+ NVIC Mux input 11 */
+ def_irq_handler NvicMux12_IRQHandler /* CM0+ NVIC Mux input 12 */
+ def_irq_handler NvicMux13_IRQHandler /* CM0+ NVIC Mux input 13 */
+ def_irq_handler NvicMux14_IRQHandler /* CM0+ NVIC Mux input 14 */
+ def_irq_handler NvicMux15_IRQHandler /* CM0+ NVIC Mux input 15 */
+ def_irq_handler NvicMux16_IRQHandler /* CM0+ NVIC Mux input 16 */
+ def_irq_handler NvicMux17_IRQHandler /* CM0+ NVIC Mux input 17 */
+ def_irq_handler NvicMux18_IRQHandler /* CM0+ NVIC Mux input 18 */
+ def_irq_handler NvicMux19_IRQHandler /* CM0+ NVIC Mux input 19 */
+ def_irq_handler NvicMux20_IRQHandler /* CM0+ NVIC Mux input 20 */
+ def_irq_handler NvicMux21_IRQHandler /* CM0+ NVIC Mux input 21 */
+ def_irq_handler NvicMux22_IRQHandler /* CM0+ NVIC Mux input 22 */
+ def_irq_handler NvicMux23_IRQHandler /* CM0+ NVIC Mux input 23 */
+ def_irq_handler NvicMux24_IRQHandler /* CM0+ NVIC Mux input 24 */
+ def_irq_handler NvicMux25_IRQHandler /* CM0+ NVIC Mux input 25 */
+ def_irq_handler NvicMux26_IRQHandler /* CM0+ NVIC Mux input 26 */
+ def_irq_handler NvicMux27_IRQHandler /* CM0+ NVIC Mux input 27 */
+ def_irq_handler NvicMux28_IRQHandler /* CM0+ NVIC Mux input 28 */
+ def_irq_handler NvicMux29_IRQHandler /* CM0+ NVIC Mux input 29 */
+ def_irq_handler NvicMux30_IRQHandler /* CM0+ NVIC Mux input 30 */
+ def_irq_handler NvicMux31_IRQHandler /* CM0+ NVIC Mux input 31 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S
new file mode 100644
index 0000000..93f2361
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S
@@ -0,0 +1,372 @@
+/**************************************************************************//**
+ * @file startup_psoc6_02_cm0plus.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0plus Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */
+ .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */
+ .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */
+ .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */
+ .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */
+ .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */
+ .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */
+ .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */
+ .long Internal0_IRQHandler /* Internal SW Interrupt #0 */
+ .long Internal1_IRQHandler /* Internal SW Interrupt #1 */
+ .long Internal2_IRQHandler /* Internal SW Interrupt #2 */
+ .long Internal3_IRQHandler /* Internal SW Interrupt #3 */
+ .long Internal4_IRQHandler /* Internal SW Interrupt #4 */
+ .long Internal5_IRQHandler /* Internal SW Interrupt #5 */
+ .long Internal6_IRQHandler /* Internal SW Interrupt #6 */
+ .long Internal7_IRQHandler /* Internal SW Interrupt #7 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /*
+ * Device startup customization
+ *
+ * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+ * because this function is executed as the first instruction in the ResetHandler.
+ * The PDL is also not initialized to use the proper register offsets.
+ * The user of this function is responsible for initializing the PDL and resources before using them.
+ */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ bl main
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+.L_API_call:
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */
+ def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */
+ def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */
+ def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */
+ def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */
+ def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */
+ def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */
+ def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */
+ def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */
+ def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */
+ def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */
+ def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */
+ def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */
+ def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */
+ def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */
+ def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S
new file mode 100644
index 0000000..61badbc
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S
@@ -0,0 +1,372 @@
+/**************************************************************************//**
+ * @file startup_psoc6_03_cm0plus.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0plus Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long NvicMux0_IRQHandler /* CPU User Interrupt #0 */
+ .long NvicMux1_IRQHandler /* CPU User Interrupt #1 */
+ .long NvicMux2_IRQHandler /* CPU User Interrupt #2 */
+ .long NvicMux3_IRQHandler /* CPU User Interrupt #3 */
+ .long NvicMux4_IRQHandler /* CPU User Interrupt #4 */
+ .long NvicMux5_IRQHandler /* CPU User Interrupt #5 */
+ .long NvicMux6_IRQHandler /* CPU User Interrupt #6 */
+ .long NvicMux7_IRQHandler /* CPU User Interrupt #7 */
+ .long Internal0_IRQHandler /* Internal SW Interrupt #0 */
+ .long Internal1_IRQHandler /* Internal SW Interrupt #1 */
+ .long Internal2_IRQHandler /* Internal SW Interrupt #2 */
+ .long Internal3_IRQHandler /* Internal SW Interrupt #3 */
+ .long Internal4_IRQHandler /* Internal SW Interrupt #4 */
+ .long Internal5_IRQHandler /* Internal SW Interrupt #5 */
+ .long Internal6_IRQHandler /* Internal SW Interrupt #6 */
+ .long Internal7_IRQHandler /* Internal SW Interrupt #7 */
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /*
+ * Device startup customization
+ *
+ * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+ * because this function is executed as the first instruction in the ResetHandler.
+ * The PDL is also not initialized to use the proper register offsets.
+ * The user of this function is responsible for initializing the PDL and resources before using them.
+ */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ bl main
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+.L_API_call:
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NvicMux0_IRQHandler /* CPU User Interrupt #0 */
+ def_irq_handler NvicMux1_IRQHandler /* CPU User Interrupt #1 */
+ def_irq_handler NvicMux2_IRQHandler /* CPU User Interrupt #2 */
+ def_irq_handler NvicMux3_IRQHandler /* CPU User Interrupt #3 */
+ def_irq_handler NvicMux4_IRQHandler /* CPU User Interrupt #4 */
+ def_irq_handler NvicMux5_IRQHandler /* CPU User Interrupt #5 */
+ def_irq_handler NvicMux6_IRQHandler /* CPU User Interrupt #6 */
+ def_irq_handler NvicMux7_IRQHandler /* CPU User Interrupt #7 */
+ def_irq_handler Internal0_IRQHandler /* Internal SW Interrupt #0 */
+ def_irq_handler Internal1_IRQHandler /* Internal SW Interrupt #1 */
+ def_irq_handler Internal2_IRQHandler /* Internal SW Interrupt #2 */
+ def_irq_handler Internal3_IRQHandler /* Internal SW Interrupt #3 */
+ def_irq_handler Internal4_IRQHandler /* Internal SW Interrupt #4 */
+ def_irq_handler Internal5_IRQHandler /* Internal SW Interrupt #5 */
+ def_irq_handler Internal6_IRQHandler /* Internal SW Interrupt #6 */
+ def_irq_handler Internal7_IRQHandler /* Internal SW Interrupt #7 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/system_psoc6_cm0plus.c b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/system_psoc6_cm0plus.c
new file mode 100644
index 0000000..52927b3
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -0,0 +1,517 @@
+/***************************************************************************//**
+* \file system_psoc6_cm0plus.c
+* \version 2.95.1
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdbool.h>
+#include "system_psoc6.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_sysclk.h"
+#include "cy_wdt.h"
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ #include "cy_ipc_sema.h"
+ #include "cy_ipc_pipe.h"
+ #include "cy_ipc_drv.h"
+
+ #if defined(CY_DEVICE_PSOC6ABLE2)
+ #include "cy_flash.h"
+ #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+ #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
+
+/** Default SlowClk system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (4000000UL)
+
+
+/** \cond */
+/**
+* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
+* which is the system clock frequency supplied to the SysTick timer and the
+* processor core clock.
+* This variable implements CMSIS Core global variable.
+* Refer to the [CMSIS documentation]
+* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
+* for more details.
+* This variable can be used by debuggers to query the frequency
+* of the debug timer or to configure the trace clock speed.
+*
+* \attention Compilers must be configured to avoid removing this variable in case
+* the application program is not using it. Debugging systems require the variable
+* to be physically present in memory so that it can be examined to configure the debugger. */
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
+uint32_t cy_BleEcoClockFreqHz = 0UL;
+
+/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_AhbFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+/** \endcond */
+
+
+/*******************************************************************************
+* SystemInit()
+*******************************************************************************/
+
+/* CLK_FLL_CONFIG default values */
+#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
+#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
+#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
+#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+
+uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
+
+uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
+
+
+/*******************************************************************************
+* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
+*******************************************************************************/
+#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL)
+#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
+#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
+
+
+void SystemInit(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+ /* Restore FLL registers to the default state as they are not restored by the ROM code */
+ uint32_t copy = SRSS->CLK_FLL_CONFIG;
+ copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ SRSS->CLK_FLL_CONFIG = copy;
+
+ copy = SRSS->CLK_ROOT_SELECT[0u];
+ copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
+ SRSS->CLK_ROOT_SELECT[0u] = copy;
+
+ SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
+ SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
+ SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
+ SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
+
+ /* Unlock and disable WDT */
+ Cy_WDT_Unlock();
+ Cy_WDT_Disable();
+
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+
+ /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
+ REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
+
+ /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
+ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ /* Allocate and initialize semaphores for the system operations. */
+ CY_SECTION_SHAREDMEM
+ static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
+
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
+
+
+ /********************************************************************************
+ *
+ * Initializes the system pipes. The system pipes are used by BLE and Flash.
+ *
+ * If the default startup file is not used, or SystemInit() is not called in your
+ * project, call the following three functions prior to executing any flash or
+ * EmEEPROM write or erase operation:
+ * -# Cy_IPC_Sema_Init()
+ * -# Cy_IPC_Pipe_Config()
+ * -# Cy_IPC_Pipe_Init()
+ * -# Cy_Flash_Init()
+ *
+ *******************************************************************************/
+
+ /* Create an array of endpoint structures */
+ static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
+
+ Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
+
+ static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
+
+ static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
+ {
+ /* .ep0ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
+ /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
+ },
+ /* .ep1ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
+ /* .ipcNotifierMuxNumber */ 0u,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
+ },
+ /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
+ /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
+ /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm0
+ };
+
+ Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ Cy_Flash_Init();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+ #if defined(CY_DEVICE_SECURE)
+ /* Initialize Protected Regsiter Access driver. */
+ Cy_PRA_Init();
+ #endif /* defined(CY_DEVICE_SECURE) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup. Once project compiled as part of
+* the PSoC Creator project, the Cy_SystemInit() function is generated by the
+* PSoC Creator.
+*
+* The function generated by PSoC Creator performs all of the necessary device
+* configuration based on the design settings. This includes settings from the
+* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
+* configuration that is necessary.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the PSoC Creator
+ * generated strong function.
+ */
+}
+
+
+void SystemCoreClockUpdate (void)
+{
+ uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
+
+ if (0UL != locHf0Clock)
+ {
+ cy_Hfclk0FreqHz = locHf0Clock;
+ cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
+ SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
+
+ /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
+ cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
+ }
+}
+
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+/*******************************************************************************
+* Function Name: Cy_SysGetCM4Status
+****************************************************************************//**
+*
+* Returns the Cortex-M4 core power mode.
+*
+* \return \ref group_system_config_cm4_status_macro
+*
+*******************************************************************************/
+uint32_t Cy_SysGetCM4Status(void)
+{
+ uint32_t regValue;
+
+ /* Get current power mode */
+ regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
+
+ return (regValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysEnableCM4
+****************************************************************************//**
+*
+* Sets vector table base address and enables the Cortex-M4 core.
+*
+* \note If the CPU is already enabled, it is reset and then enabled.
+*
+* \param vectorTableOffset The offset of the vector table base address from
+* memory address 0x00000000. The offset should be multiple to 1024 bytes.
+*
+*******************************************************************************/
+void Cy_SysEnableCM4(uint32_t vectorTableOffset)
+{
+ uint32_t regValue;
+ uint32_t interruptState;
+ uint32_t cpuState;
+
+ CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ cpuState = Cy_SysGetCM4Status();
+ if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
+ {
+ Cy_SysResetCM4();
+ }
+
+ CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_ENABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysDisableCM4
+****************************************************************************//**
+*
+* Disables the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
+* CPU.
+*
+*******************************************************************************/
+void Cy_SysDisableCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_DISABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysRetainCM4
+****************************************************************************//**
+*
+* Retains the Cortex-M4 core and exists without waiting for the mode to take
+* effect.
+*
+* \note The retained mode can be entered only from the enabled mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysRetainCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RETAINED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysResetCM4
+****************************************************************************//**
+*
+* Resets the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \note The reset mode can not be entered from the retained mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysResetCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RESET;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+/*******************************************************************************
+* Function Name: Cy_SysIpcPipeIsrCm0
+****************************************************************************//**
+*
+* This is the interrupt service routine for the system pipe.
+*
+*******************************************************************************/
+void Cy_SysIpcPipeIsrCm0(void)
+{
+ Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
+}
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_MemorySymbols
+****************************************************************************//**
+*
+* The intention of the function is to declare boundaries of the memories for the
+* MDK compilers. For the rest of the supported compilers, this is done using
+* linker configuration files. The following symbols used by the cymcuelftool.
+*
+*******************************************************************************/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+__asm void Cy_MemorySymbols(void)
+{
+ /* Flash */
+ EXPORT __cy_memory_0_start
+ EXPORT __cy_memory_0_length
+ EXPORT __cy_memory_0_row_size
+
+ /* Working Flash */
+ EXPORT __cy_memory_1_start
+ EXPORT __cy_memory_1_length
+ EXPORT __cy_memory_1_row_size
+
+ /* Supervisory Flash */
+ EXPORT __cy_memory_2_start
+ EXPORT __cy_memory_2_length
+ EXPORT __cy_memory_2_row_size
+
+ /* XIP */
+ EXPORT __cy_memory_3_start
+ EXPORT __cy_memory_3_length
+ EXPORT __cy_memory_3_row_size
+
+ /* eFuse */
+ EXPORT __cy_memory_4_start
+ EXPORT __cy_memory_4_length
+ EXPORT __cy_memory_4_row_size
+
+ /* Flash */
+__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
+__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
+__cy_memory_0_row_size EQU 0x200
+
+ /* Flash region for EEPROM emulation */
+__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
+__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
+__cy_memory_1_row_size EQU 0x200
+
+ /* Supervisory Flash */
+__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
+__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
+__cy_memory_2_row_size EQU 0x200
+
+ /* XIP */
+__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
+__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
+__cy_memory_3_row_size EQU 0x200
+
+ /* eFuse */
+__cy_memory_4_start EQU __cpp(0x90700000)
+__cy_memory_4_length EQU __cpp(0x100000)
+__cy_memory_4_row_size EQU __cpp(1)
+}
+#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S
new file mode 100644
index 0000000..7a9308a
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S
@@ -0,0 +1,655 @@
+/**************************************************************************//**
+ * @file startup_psoc6_01_cm4.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ .long pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
+ .long bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
+ .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ .long udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
+ .long udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
+ .long udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
+ .long udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
+ .long udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
+ .long udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
+ .long udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
+ .long udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
+ .long udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
+ .long udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
+ .long udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
+ .long udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
+ .long udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
+ .long udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
+ .long udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
+ .long udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
+ .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ .long audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
+ .long audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
+ .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ .long usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_med_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ .long pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
+
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /*
+ * Device startup customization
+ *
+ * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+ * because this function is executed as the first instruction in the ResetHandler.
+ * The PDL is also not initialized to use the proper register offsets.
+ * The user of this function is responsible for initializing the PDL and resources before using them.
+ */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* OS-specific low-level initialization */
+ .weak cy_toolchain_init
+ .func cy_toolchain_init, cy_toolchain_init
+ .type cy_toolchain_init, %function
+
+cy_toolchain_init:
+ bx lr
+ .size cy_toolchain_init, . - cy_toolchain_init
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+ /* Enable the FPU if used */
+ bl Cy_SystemInitFpuEnable
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ /* OS-specific low-level initialization */
+ bl cy_toolchain_init
+
+ /* Call C/C++ static constructors */
+ bl __libc_init_array
+
+ /* Execute main application */
+ bl main
+
+ /* Call C/C++ static destructors */
+ bl __libc_fini_array
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+.L_API_call:
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+ def_fault_Handler MemManage_Handler
+ def_fault_Handler BusFault_Handler
+ def_fault_Handler UsageFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ def_irq_handler pass_interrupt_ctbs_IRQHandler /* CTBm Interrupt (all CTBms) */
+ def_irq_handler bless_interrupt_IRQHandler /* Bluetooth Radio interrupt */
+ def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ def_irq_handler udb_interrupts_0_IRQHandler /* UDB Interrupt #0 */
+ def_irq_handler udb_interrupts_1_IRQHandler /* UDB Interrupt #1 */
+ def_irq_handler udb_interrupts_2_IRQHandler /* UDB Interrupt #2 */
+ def_irq_handler udb_interrupts_3_IRQHandler /* UDB Interrupt #3 */
+ def_irq_handler udb_interrupts_4_IRQHandler /* UDB Interrupt #4 */
+ def_irq_handler udb_interrupts_5_IRQHandler /* UDB Interrupt #5 */
+ def_irq_handler udb_interrupts_6_IRQHandler /* UDB Interrupt #6 */
+ def_irq_handler udb_interrupts_7_IRQHandler /* UDB Interrupt #7 */
+ def_irq_handler udb_interrupts_8_IRQHandler /* UDB Interrupt #8 */
+ def_irq_handler udb_interrupts_9_IRQHandler /* UDB Interrupt #9 */
+ def_irq_handler udb_interrupts_10_IRQHandler /* UDB Interrupt #10 */
+ def_irq_handler udb_interrupts_11_IRQHandler /* UDB Interrupt #11 */
+ def_irq_handler udb_interrupts_12_IRQHandler /* UDB Interrupt #12 */
+ def_irq_handler udb_interrupts_13_IRQHandler /* UDB Interrupt #13 */
+ def_irq_handler udb_interrupts_14_IRQHandler /* UDB Interrupt #14 */
+ def_irq_handler udb_interrupts_15_IRQHandler /* UDB Interrupt #15 */
+ def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ def_irq_handler audioss_interrupt_i2s_IRQHandler /* I2S Audio interrupt */
+ def_irq_handler audioss_interrupt_pdm_IRQHandler /* PDM/PCM Audio interrupt */
+ def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ def_irq_handler pass_interrupt_dacs_IRQHandler /* Consolidated interrrupt for all DACs */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S
new file mode 100644
index 0000000..c0fd18d
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file startup_psoc6_02_cm4.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
+ .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
+ .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
+ .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
+ .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
+ .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
+ .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
+ .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
+ .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
+ .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
+ .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
+ .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
+ .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
+ .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
+ .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
+ .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
+ .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
+ .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
+ .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
+ .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
+ .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
+ .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
+ .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
+ .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
+ .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
+ .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
+ .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
+ .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
+ .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
+ .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
+ .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
+ .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
+ .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
+ .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
+ .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
+ .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
+ .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
+ .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
+ .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ .long usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_med_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
+ .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+ .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
+ .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /*
+ * Device startup customization
+ *
+ * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+ * because this function is executed as the first instruction in the ResetHandler.
+ * The PDL is also not initialized to use the proper register offsets.
+ * The user of this function is responsible for initializing the PDL and resources before using them.
+ */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* OS-specific low-level initialization */
+ .weak cy_toolchain_init
+ .func cy_toolchain_init, cy_toolchain_init
+ .type cy_toolchain_init, %function
+
+cy_toolchain_init:
+ bx lr
+ .size cy_toolchain_init, . - cy_toolchain_init
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+ /* Enable the FPU if used */
+ bl Cy_SystemInitFpuEnable
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ /* OS-specific low-level initialization */
+ bl cy_toolchain_init
+
+ /* Call C/C++ static constructors */
+ bl __libc_init_array
+
+ /* Execute main application */
+ bl main
+
+ /* Call C/C++ static destructors */
+ bl __libc_fini_array
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+.L_API_call:
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+ def_fault_Handler MemManage_Handler
+ def_fault_Handler BusFault_Handler
+ def_fault_Handler UsageFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */
+ def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */
+ def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */
+ def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */
+ def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */
+ def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */
+ def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */
+ def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */
+ def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */
+ def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */
+ def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
+ def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
+ def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */
+ def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
+ def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
+ def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
+ def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
+ def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
+ def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
+ def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
+ def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
+ def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
+ def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
+ def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
+ def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
+ def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
+ def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
+ def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
+ def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
+ def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
+ def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
+ def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
+ def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
+ def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
+ def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
+ def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
+ def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
+ def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
+ def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
+ def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
+ def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */
+ def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */
+ def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */
+ def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */
+ def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */
+ def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */
+ def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */
+ def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */
+ def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */
+ def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */
+ def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */
+ def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */
+ def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */
+ def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */
+ def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */
+ def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */
+ def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */
+ def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */
+ def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */
+ def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */
+ def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */
+ def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */
+ def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */
+ def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
+ def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+ def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */
+ def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S
new file mode 100644
index 0000000..99c922c
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S
@@ -0,0 +1,672 @@
+/**************************************************************************//**
+ * @file startup_psoc6_03_cm4.S
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device Series
+ * @version V5.00
+ * @date 02. March 2016
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /* Address of the NMI handler */
+ #define CY_NMI_HANLDER_ADDR 0x0000000D
+
+ /* The CPU VTOR register */
+ #define CY_CPU_VTOR_ADDR 0xE000ED08
+
+ /* Copy flash vectors and data section to RAM */
+ #define __STARTUP_COPY_MULTIPLE
+
+ /* Clear single BSS section */
+ #define __STARTUP_CLEAR_BSS
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00001000
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long CY_NMI_HANLDER_ADDR /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts Description */
+ .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ .long 0 /* Reserved */
+ .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ .long 0 /* Reserved */
+ .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ .long 0 /* Reserved */
+ .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */
+ .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
+ .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
+ .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
+ .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
+ .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
+ .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
+ .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
+ .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
+ .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
+ .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
+ .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
+ .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
+ .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
+ .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
+ .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
+ .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
+ .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
+ .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
+ .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
+ .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
+ .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
+ .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
+ .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
+ .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
+ .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
+ .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
+ .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
+ .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
+ .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ .long usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_med_IRQHandler /* USB Interrupt */
+ .long usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
+ .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */
+ .long canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */
+ .long canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */
+ .long cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */
+ .long cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */
+ .long cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */
+
+
+ .size __Vectors, . - __Vectors
+ .equ __VectorsSize, . - __Vectors
+
+ .section .ram_vectors
+ .align 2
+ .globl __ramVectors
+__ramVectors:
+ .space __VectorsSize
+ .size __ramVectors, . - __ramVectors
+
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+
+ /*
+ * Device startup customization
+ *
+ * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
+ * because this function is executed as the first instruction in the ResetHandler.
+ * The PDL is also not initialized to use the proper register offsets.
+ * The user of this function is responsible for initializing the PDL and resources before using them.
+ */
+ .weak Cy_OnResetUser
+ .func Cy_OnResetUser, Cy_OnResetUser
+ .type Cy_OnResetUser, %function
+
+Cy_OnResetUser:
+ bx lr
+ .size Cy_OnResetUser, . - Cy_OnResetUser
+ .endfunc
+
+ /* OS-specific low-level initialization */
+ .weak cy_toolchain_init
+ .func cy_toolchain_init, cy_toolchain_init
+ .type cy_toolchain_init, %function
+
+cy_toolchain_init:
+ bx lr
+ .size cy_toolchain_init, . - cy_toolchain_init
+ .endfunc
+
+ /* Reset handler */
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+
+Reset_Handler:
+ bl Cy_OnResetUser
+ cpsid i
+
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ /* Update Vector Table Offset Register. */
+ ldr r0, =__ramVectors
+ ldr r1, =CY_CPU_VTOR_ADDR
+ str r0, [r1]
+ dsb 0xF
+
+ /* Enable the FPU if used */
+ bl Cy_SystemInitFpuEnable
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+ /* OS-specific low-level initialization */
+ bl cy_toolchain_init
+
+ /* Call C/C++ static constructors */
+ bl __libc_init_array
+
+ /* Execute main application */
+ bl main
+
+ /* Call C/C++ static destructors */
+ bl __libc_fini_array
+
+ /* Should never get here */
+ b .
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+
+ .weak Cy_SysLib_FaultHandler
+ .type Cy_SysLib_FaultHandler, %function
+
+Cy_SysLib_FaultHandler:
+ b .
+ .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
+ .type Fault_Handler, %function
+
+Fault_Handler:
+ /* Storing LR content for Creator call stack trace */
+ push {LR}
+ movs r0, #4
+ mov r1, LR
+ tst r0, r1
+ beq .L_MSP
+ mrs r0, PSP
+ b .L_API_call
+.L_MSP:
+ mrs r0, MSP
+ /* Compensation of stack pointer address due to pushing 4 bytes of LR */
+ adds r0, r0, #4
+.L_API_call:
+ bl Cy_SysLib_FaultHandler
+ b .
+ .size Fault_Handler, . - Fault_Handler
+
+.macro def_fault_Handler fault_handler_name
+ .weak \fault_handler_name
+ .set \fault_handler_name, Fault_Handler
+ .endm
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+
+ def_fault_Handler HardFault_Handler
+ def_fault_Handler MemManage_Handler
+ def_fault_Handler BusFault_Handler
+ def_fault_Handler UsageFault_Handler
+
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */
+ def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */
+ def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */
+ def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */
+ def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */
+ def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */
+ def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */
+ def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */
+ def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */
+ def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */
+ def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */
+ def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */
+ def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */
+ def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */
+ def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */
+ def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 (DeepSleep capable) */
+ def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */
+ def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */
+ def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
+ def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */
+ def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */
+ def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */
+ def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */
+ def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */
+ def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */
+ def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */
+ def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */
+ def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */
+ def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */
+ def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */
+ def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */
+ def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */
+ def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */
+ def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */
+ def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */
+ def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */
+ def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */
+ def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */
+ def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */
+ def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */
+ def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */
+ def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */
+ def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */
+ def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */
+ def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */
+ def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */
+ def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */
+ def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */
+ def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */
+ def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */
+ def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */
+ def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */
+ def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */
+ def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */
+ def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */
+ def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */
+ def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */
+ def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */
+ def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */
+ def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */
+ def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */
+ def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */
+ def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */
+ def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */
+ def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */
+ def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */
+ def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */
+ def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */
+ def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */
+ def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */
+ def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */
+ def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */
+ def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */
+ def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */
+ def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */
+ def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */
+ def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */
+ def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */
+ def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */
+ def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */
+ def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */
+ def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */
+ def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */
+ def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */
+ def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */
+ def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */
+ def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */
+ def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */
+ def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */
+ def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */
+ def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */
+ def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */
+ def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */
+ def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */
+ def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */
+ def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */
+ def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */
+ def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */
+ def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */
+ def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */
+ def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */
+ def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */
+ def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */
+ def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */
+ def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */
+ def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */
+ def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */
+ def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */
+ def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */
+ def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */
+ def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */
+ def_irq_handler canfd_0_interrupt0_IRQHandler /* Can #0, Consolidated interrupt #0 */
+ def_irq_handler canfd_0_interrupts0_0_IRQHandler /* CAN #0, Interrupt #0, Channel #0 */
+ def_irq_handler canfd_0_interrupts1_0_IRQHandler /* CAN #0, Interrupt #1, Channel #0 */
+ def_irq_handler cpuss_interrupts_dw1_29_IRQHandler /* CPUSS DataWire #1, Channel #29 */
+ def_irq_handler cpuss_interrupts_dw1_30_IRQHandler /* CPUSS DataWire #1, Channel #30 */
+ def_irq_handler cpuss_interrupts_dw1_31_IRQHandler /* CPUSS DataWire #1, Channel #31 */
+
+ .end
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/system_psoc6_cm4.c b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/system_psoc6_cm4.c
new file mode 100644
index 0000000..2c766c1
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/system_psoc6_cm4.c
@@ -0,0 +1,361 @@
+/***************************************************************************//**
+* \file system_psoc6_cm4.c
+* \version 2.95.1
+*
+* The device system-source file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <stdbool.h>
+#include "system_psoc6.h"
+#include "cy_device.h"
+#include "cy_device_headers.h"
+#include "cy_syslib.h"
+#include "cy_sysclk.h"
+#include "cy_wdt.h"
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+ #include "cy_ipc_sema.h"
+ #include "cy_ipc_pipe.h"
+ #include "cy_ipc_drv.h"
+
+ #if defined(CY_DEVICE_PSOC6ABLE2)
+ #include "cy_flash.h"
+ #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+ #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL)
+
+/** Default FastClk system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
+
+uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
+
+uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
+
+/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
+uint32_t cy_BleEcoClockFreqHz = 0UL;
+
+/* SCB->CPACR */
+#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
+
+/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
+uint32_t cy_AhbFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
+
+/*******************************************************************************
+* SystemInit()
+*******************************************************************************/
+
+/* CLK_FLL_CONFIG default values */
+#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u)
+#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u)
+#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u)
+#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu)
+
+/* IPC_STRUCT7->DATA configuration */
+#define CY_STARTUP_CM0_DP_STATE (0x2uL)
+#define CY_STARTUP_IPC7_DP_OFFSET (28u)
+
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+
+uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
+
+uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
+
+
+void SystemInit(void)
+{
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+#ifdef __CM0P_PRESENT
+ #if (__CM0P_PRESENT == 0)
+ /* Restore FLL registers to the default state as they are not restored by the ROM code */
+ uint32_t copy = SRSS->CLK_FLL_CONFIG;
+ copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
+ SRSS->CLK_FLL_CONFIG = copy;
+
+ copy = SRSS->CLK_ROOT_SELECT[0u];
+ copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
+ SRSS->CLK_ROOT_SELECT[0u] = copy;
+
+ SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE;
+ SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
+ SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
+ SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
+
+ /* Unlock and disable WDT */
+ Cy_WDT_Unlock();
+ Cy_WDT_Disable();
+ #endif /* (__CM0P_PRESENT == 0) */
+#endif /* __CM0P_PRESENT */
+
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+
+#ifdef __CM0P_PRESENT
+ #if (__CM0P_PRESENT == 0)
+ /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
+ REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
+ CY_STARTUP_IPC7_DP_OFFSET);
+
+ /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
+ REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
+ #endif /* (__CM0P_PRESENT == 0) */
+#endif /* __CM0P_PRESENT */
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+
+#ifdef __CM0P_PRESENT
+ #if (__CM0P_PRESENT == 0)
+ /* Allocate and initialize semaphores for the system operations. */
+ static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
+ #else
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
+ #endif /* (__CM0P_PRESENT) */
+#else
+ (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
+#endif /* __CM0P_PRESENT */
+
+
+ /********************************************************************************
+ *
+ * Initializes the system pipes. The system pipes are used by BLE and Flash.
+ *
+ * If the default startup file is not used, or SystemInit() is not called in your
+ * project, call the following three functions prior to executing any flash or
+ * EmEEPROM write or erase operation:
+ * -# Cy_IPC_Sema_Init()
+ * -# Cy_IPC_Pipe_Config()
+ * -# Cy_IPC_Pipe_Init()
+ * -# Cy_Flash_Init()
+ *
+ *******************************************************************************/
+ /* Create an array of endpoint structures */
+ static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
+
+ Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
+
+ static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
+
+ static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
+ {
+ /* .ep0ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0,
+ /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0
+ },
+ /* .ep1ConfigData */
+ {
+ /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1,
+ /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1,
+ /* .ipcNotifierMuxNumber */ 0u,
+ /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR,
+ /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1
+ },
+ /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT,
+ /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray,
+ /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4
+ };
+
+ Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
+
+#if defined(CY_DEVICE_PSOC6ABLE2)
+ Cy_Flash_Init();
+#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
+
+#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+ /* Initialize Protected Register Access driver */
+ Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup. Once project compiled as part of
+* the PSoC Creator project, the Cy_SystemInit() function is generated by the
+* PSoC Creator.
+*
+* The function generated by PSoC Creator performs all of the necessary device
+* configuration based on the design settings. This includes settings from the
+* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
+* configuration that is necessary.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the PSoC Creator
+ * generated strong function.
+ */
+}
+
+
+void SystemCoreClockUpdate (void)
+{
+ uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
+
+ if (0UL != locHf0Clock)
+ {
+ cy_Hfclk0FreqHz = locHf0Clock;
+ cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
+ SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
+
+ /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
+ cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SystemInitFpuEnable
+****************************************************************************//**
+*
+* Enables the FPU if it is used. The function is called from the startup file.
+*
+*******************************************************************************/
+void Cy_SystemInitFpuEnable(void)
+{
+ #if defined (__FPU_USED) && (__FPU_USED == 1U)
+ uint32_t interruptState;
+ interruptState = __get_PRIMASK();
+ __disable_irq();
+ SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
+ __DSB();
+ __ISB();
+ __set_PRIMASK(interruptState);
+ #endif /* (__FPU_USED) && (__FPU_USED == 1U) */
+}
+
+
+#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
+/*******************************************************************************
+* Function Name: Cy_SysIpcPipeIsrCm4
+****************************************************************************//**
+*
+* This is the interrupt service routine for the system pipe.
+*
+*******************************************************************************/
+void Cy_SysIpcPipeIsrCm4(void)
+{
+ Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
+}
+#endif
+
+
+/*******************************************************************************
+* Function Name: Cy_MemorySymbols
+****************************************************************************//**
+*
+* The intention of the function is to declare boundaries of the memories for the
+* MDK compilers. For the rest of the supported compilers, this is done using
+* linker configuration files. The following symbols used by the cymcuelftool.
+*
+*******************************************************************************/
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+__asm void Cy_MemorySymbols(void)
+{
+ /* Flash */
+ EXPORT __cy_memory_0_start
+ EXPORT __cy_memory_0_length
+ EXPORT __cy_memory_0_row_size
+
+ /* Working Flash */
+ EXPORT __cy_memory_1_start
+ EXPORT __cy_memory_1_length
+ EXPORT __cy_memory_1_row_size
+
+ /* Supervisory Flash */
+ EXPORT __cy_memory_2_start
+ EXPORT __cy_memory_2_length
+ EXPORT __cy_memory_2_row_size
+
+ /* XIP */
+ EXPORT __cy_memory_3_start
+ EXPORT __cy_memory_3_length
+ EXPORT __cy_memory_3_row_size
+
+ /* eFuse */
+ EXPORT __cy_memory_4_start
+ EXPORT __cy_memory_4_length
+ EXPORT __cy_memory_4_row_size
+
+ /* Flash */
+__cy_memory_0_start EQU __cpp(CY_FLASH_BASE)
+__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE)
+__cy_memory_0_row_size EQU 0x200
+
+ /* Flash region for EEPROM emulation */
+__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE)
+__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE)
+__cy_memory_1_row_size EQU 0x200
+
+ /* Supervisory Flash */
+__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE)
+__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE)
+__cy_memory_2_row_size EQU 0x200
+
+ /* XIP */
+__cy_memory_3_start EQU __cpp(CY_XIP_BASE)
+__cy_memory_3_length EQU __cpp(CY_XIP_SIZE)
+__cy_memory_3_row_size EQU 0x200
+
+ /* eFuse */
+__cy_memory_4_start EQU __cpp(0x90700000)
+__cy_memory_4_length EQU __cpp(0x100000)
+__cy_memory_4_row_size EQU __cpp(1)
+}
+#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/system_psoc6.h b/boot/cypress/platforms/BSP/PSOC6/system/system_psoc6.h
new file mode 100644
index 0000000..eb65a16
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/system/system_psoc6.h
@@ -0,0 +1,730 @@
+/***************************************************************************//**
+* \file system_psoc6.h
+* \version 2.95.1
+*
+* \brief Device system header file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+
+#ifndef _SYSTEM_PSOC6_H_
+#define _SYSTEM_PSOC6_H_
+
+/**
+* \addtogroup group_system_config_cm4
+* \{
+* Provides device startup, system configuration, and linker script files.
+* The system startup provides the followings features:
+* - See \ref group_system_config_device_initialization for the:
+* * \ref group_system_config_dual_core_device_initialization
+* * \ref group_system_config_single_core_device_initialization
+* - \ref group_system_config_device_memory_definition
+* - \ref group_system_config_heap_stack_config
+* - \ref group_system_config_default_handlers
+* - \ref group_system_config_device_vector_table
+* - \ref group_system_config_cm4_functions
+*
+* \section group_system_config_configuration Configuration Considerations
+*
+* \subsection group_system_config_device_memory_definition Device Memory Definition
+* The flash and RAM allocation for each CPU is defined by the linker scripts.
+* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
+* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
+* For Single-Core devices the system reserves additional 80 bytes of RAM.
+* Using the reserved memory area for other purposes will lead to unexpected behavior.
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see warnings during the build process. To eliminate build
+* warnings in your project, you can simply comment out or remove the relevant
+* code in the linker file.
+*
+* \note For the PSoC 64 Secure MCUs devices, refer to the following page:
+* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide
+*
+*
+* <b>ARM GCC</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
+* Cy_SysEnableCM4() function call.
+* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+* More about CM0+ prebuilt images, see here:
+* https://github.com/cypresssemiconductorco/psoc6cm0p
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.ld', where 'xx' is the device group:
+* \code
+* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x2000
+* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000
+* \endcode
+* - 'xx_cm4_dual.ld', where 'xx' is the device group:
+* \code
+* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x100000
+* ram (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the flash LENGTH in
+* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group.
+* Do this by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
+* or
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
+* 'xx' is the device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
+*
+* <b>ARM Compiler</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for
+* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
+* Cy_SysEnableCM4() function call.
+* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+* More about CM0+ prebuilt images, see here:
+* https://github.com/cypresssemiconductorco/psoc6cm0p
+*
+* \note The linker files provided with the PDL are generic and handle all common
+* use cases. Your project may not use every section defined in the linker files.
+* In that case you may see the warnings during the build process:
+* L6314W (no section matches pattern) and/or L6329W
+* (pattern only matches removed unused sections). In your project, you can
+* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+* the linker. You can also comment out or remove the relevant code in the linker
+* file.
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.sct', where 'xx' is the device group:
+* \code
+* #define FLASH_START 0x10000000
+* #define FLASH_SIZE 0x00002000
+* #define RAM_START 0x08000000
+* #define RAM_SIZE 0x00002000
+* \endcode
+* - 'xx_cm4_dual.sct', where 'xx' is the device group:
+* \code
+* #define FLASH_START 0x10000000
+* #define FLASH_SIZE 0x00100000
+* #define RAM_START 0x08002000
+* #define RAM_SIZE 0x00045800
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
+* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image
+* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the
+* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group.
+* Do this by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
+* or
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
+* 'xx' is the device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
+*
+* <b>IAR</b>\n
+* The flash and RAM sections for the CPU are defined in the linker files:
+* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
+* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
+* \note If the start of the Cortex-M4 application image is changed, the value
+* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
+* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
+* Cy_SysEnableCM4() function call.
+* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+* More about CM0+ prebuilt images, see here:
+* https://github.com/cypresssemiconductorco/psoc6cm0p
+*
+* Change the flash and RAM sizes by editing the macros value in the
+* linker files for both CPUs:
+* - 'xx_cm0plus.icf', where 'xx' is the device group:
+* \code
+* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+* define symbol __ICFEDIT_region_IROM1_end__ = 0x10001FFF;
+* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
+* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08001FFF;
+* \endcode
+* - 'xx_cm4_dual.icf', where 'xx' is the device group:
+* \code
+* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+* define symbol __ICFEDIT_region_IROM1_end__ = 0x100FFFFF;
+* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+* define symbol __ICFEDIT_region_IRAM1_end__ = 0x080477FF;
+* \endcode
+*
+* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
+* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value
+* (0x2000, the size of a flash image of the Cortex-M0+ application) in the
+* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
+* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the
+* 'xx_cm0plus.icf'. Do this by either:
+* - Passing the following commands to the compiler:\n
+* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
+* or
+* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
+* 'xx' is the device family:\n
+* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
+*
+* \subsection group_system_config_device_initialization Device Initialization
+* After a power-on-reset (POR), the boot process is handled by the boot code
+* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
+* code passes the control to the Cortex-M0+ startup code located in flash.
+*
+* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
+* The Cortex-M0+ startup code performs the device initialization by a call to
+* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
+* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
+* See \ref group_system_config_cm4_functions for more details.
+* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
+* The function has a separate implementation on each core.
+* Both function implementations unlock and disable the WDT.
+* Therefore enable the WDT after both cores have been initialized.
+*
+* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
+* The Cortex-M0+ core is not user-accessible on these devices. In this case the
+* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
+*
+* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
+* There are two ways to adjust heap and stack configurations:
+* -# Editing source code files
+* -# Specifying via command line
+*
+* By default, the stack size is set to 0x00001000 and the heap size is allocated
+* dynamically to the whole available free memory up to stack memory and it
+* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
+*
+* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the assembler startup files
+* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code .equ Stack_Size, 0x00001000 \endcode
+* \code .equ Heap_Size, 0x00000400 \endcode
+* Also, the stack size is defined in the linker script files: 'xx_yy.ld',
+* where 'xx' is the device family, and 'yy' is the target CPU; for example,
+* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
+* Change the stack size by modifying the following line:\n
+* \code STACK_SIZE = 0x1000; \endcode
+*
+* \note Correct operation of malloc and related functions depends on the working
+* implementation of the 'sbrk' function. Newlib-nano (default C runtime library
+* used by the GNU Arm Embedded toolchain) provides weak 'sbrk' implementation that
+* doesn't check for heap and stack collisions during excessive memory allocations.
+* To ensure the heap always remains within the range defined by __HeapBase and
+* __HeapLimit linker symbols, provide a strong override for the 'sbrk' function:
+* \snippet startup/snippet/main.c snippet_sbrk
+* For FreeRTOS-enabled multi-threaded applications, it is sufficient to include
+* clib-support library that provides newlib-compatible implementations of
+* 'sbrk', '__malloc_lock' and '__malloc_unlock':
+* <br>
+* https://github.com/cypresssemiconductorco/clib-support.
+*
+* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler
+* - <b>Editing source code files</b>\n
+* The stack size is defined in the linker script files: 'xx_yy.sct',
+* where 'xx' is the device family, and 'yy' is the target CPU; for example,
+* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct.
+* Change the stack size by modifying the following line:\n
+* \code STACK_SIZE = 0x1000; \endcode
+*
+* \subsubsection group_system_config_heap_stack_config_iar IAR
+* - <b>Editing source code files</b>\n
+* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf',
+* where 'xx' is the device family, and 'yy' is the target CPU; for example,
+* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
+* Change the heap and stack sizes by modifying the following lines:\n
+* \code Stack_Size EQU 0x00001000 \endcode
+* \code Heap_Size EQU 0x00000400 \endcode
+*
+* - <b>Specifying via command line</b>\n
+* Change the heap and stack sizes passing the following commands to the
+* linker (including quotation marks):\n
+* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
+* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
+*
+* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
+* The default interrupt handler functions are defined as weak functions to a dummy
+* handler in the startup file. The naming convention for the interrupt handler names
+* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
+* user code by defining the handler function using the same name. For example:
+* \code
+* void scb_0_interrupt_IRQHandler(void)
+*{
+* ...
+*}
+* \endcode
+*
+* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
+* This process uses memory sections defined in the linker script. The startup
+* code actually defines the contents of the vector table and performs the copy.
+* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
+* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
+* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
+* It defines sections and locations in memory.\n
+* Copy interrupt vectors from flash to RAM: \n
+* From: \code LONG (__Vectors) \endcode
+* To: \code LONG (__ram_vectors_start__) \endcode
+* Size: \code LONG (__Vectors_End - __Vectors) \endcode
+* The vector table address (and the vector table itself) are defined in the
+* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
+* The code in these files copies the vector table from Flash to RAM.
+* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler
+* The linker script file is 'xx_yy.sct', where 'xx' is the device family,
+* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and
+* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table
+* (RESET_RAM) shall be first in the RAM section.\n
+* RESET_RAM represents the vector table. It is defined in the assembler startup
+* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \subsubsection group_system_config_device_vector_table_iar IAR
+* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
+* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
+* This file defines the .intvec_ram section and its location.
+* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
+* The vector table address (and the vector table itself) are defined in the
+* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
+* The code in these files copies the vector table from Flash to RAM.
+*
+* \section group_system_config_MISRA MISRA Compliance
+*
+* <table class="doxtable">
+* <tr>
+* <th>MISRA Rule</th>
+* <th>Rule Class (Required/Advisory)</th>
+* <th>Rule Description</th>
+* <th>Description of Deviation(s)</th>
+* </tr>
+* <tr>
+* <td>2.3</td>
+* <td>R</td>
+* <td>The character sequence // shall not be used within a comment.</td>
+* <td>The comments provide a useful WEB link to the documentation.</td>
+* </tr>
+* </table>
+*
+* \section group_system_config_changelog Changelog
+* <table class="doxtable">
+* <tr>
+* <th>Version</th>
+* <th>Changes</th>
+* <th>Reason for Change</th>
+* </tr>
+* <tr>
+* <td rowspan="1">2.95.1</td>
+* <td>Restructured documentation.</td>
+* <td>Documentation update.</td>
+* </tr>
+* <tr>
+* <td rowspan="1">2.95</td>
+* <td>Update FPU enable function with CMSIS macros to disable/enable interrupts</td>
+* <td>Move to stadnard inline CMSIS ARM macros</td>
+* </tr>
+* <tr>
+* <td rowspan="2">2.91</td>
+* <td>Updated memory configuration for PSoC 64 devices.</td>
+* <td>Flash and RAM memory allocation updated.</td>
+* </tr>
+* <tr>
+* <td>Added cys06xxa_cm4 linker scripts.</td>
+* <td>New device support.</td>
+* </tr>
+* <tr>
+* <td rowspan="4">2.90.1</td>
+* <td>Updated \ref group_system_config_heap_stack_config_gcc section with the note
+* on the dynamic memory allocation for ARM GCC.</td>
+* <td>Documentation update.</td>
+* </tr>
+* <tr>
+* <td>Updated system_psoc6.h to include custom CY_SYSTEM_PSOC6_CONFIG passed as compiler macro.</td>
+* <td>Improve configuration flexibility.</td>
+* </tr>
+* <tr>
+* <td>Updated attribute usage for the linker section placement in CM0+ startup code</td>
+* <td>Enhancement based on usability feedback.</td>
+* </tr>
+* <tr>
+* <td>Renamed the '.cy_xip' linker script region as 'cy_xip'</td>
+* <td>Enable access to the XIP region start/end addresses from the C code.</td>
+* </tr>
+* <tr>
+* <td>2.90</td>
+* <td>Updated linker scripts for PSoC 64 Secure MCU cyb06xx7 devices.</td>
+* <td>Flash allocation adjustment.</td>
+* </tr>
+* <tr>
+* <td rowspan="2">2.80</td>
+* <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
+* <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+* in accordance with the PSoC 64 Secure Boot SDK policies.</td>
+* </tr>
+* <tr>
+* <td>Added \ref Cy_PRA_Init() call to \ref SystemInit() Cortex-M0+ and Cortex-M4 functions for PSoC 64 Secure MCU.</td>
+* <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
+* </tr>
+* <tr>
+* <td>2.70.1</td>
+* <td>Updated documentation for the better description of the existing startup implementation.</td>
+* <td>User experience enhancement.</td>
+* </tr>
+* <tr>
+* <td rowspan="5">2.70</td>
+* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
+* <td>Code optimization.</td>
+* </tr>
+* <tr>
+* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
+* <td>Provided support for SysPM driver updates.</td>
+* </tr>
+* <tr>
+* <td>Updated the linker scripts.</td>
+* <td>Reserved FLASH area for the MCU boot headers.</td>
+* </tr>
+* <tr>
+* <td>Added System Pipe initialization for all devices. </td>
+* <td>Improved PDL usability according to user experience.</td>
+* </tr>
+* <tr>
+* <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
+* Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
+* <td>Defect fixing.</td>
+* </tr>
+* <tr>
+* <td>2.60</td>
+* <td>Updated linker scripts.</td>
+* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
+* </tr>
+* <tr>
+* <td>2.50</td>
+* <td>Updated assembler files, C files, linker scripts.</td>
+* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>
+* </tr>
+* <tr>
+* <td>2.40</td>
+* <td>Updated assembler files, C files, linker scripts.</td>
+* <td>Added Arm Compiler 6 support.</td>
+* </tr>
+* <tr>
+* <td rowspan="2">2.30</td>
+* <td>Added assembler files, linker scripts for Mbed OS.</td>
+* <td>Added Arm Mbed OS embedded operating system support.</td>
+* </tr>
+* <tr>
+* <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
+* <td>Enhanced PDL usability.</td>
+* </tr>
+* <tr>
+* <td>2.20</td>
+* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
+* <td>Changed the IPC driver configuration method from compile time to run time.</td>
+* </tr>
+* <tr>
+* <td rowspan="2"> 2.10</td>
+* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
+* Removed $Sub$$main symbol for ARM MDK compiler.
+* </td>
+* <td>uVision Debugger support.</td>
+* </tr>
+* <tr>
+* <td>Updated description of the Startup behavior for Single-Core Devices. \n
+* Added note about WDT disabling by SystemInit() function.
+* </td>
+* <td>Documentation improvement.</td>
+* </tr>
+* <tr>
+* <td rowspan="4"> 2.0</td>
+* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
+* Single core device support.
+* </td>
+* <td></td>
+* </tr>
+* <tr>
+* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
+* Renamed 'wflash' memory region to 'em_eeprom'.
+* </td>
+* <td>Linker scripts usability improvement.</td>
+* </tr>
+* <tr>
+* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
+* <td>Reserved system resources for internal operations.</td>
+* </tr>
+* <tr>
+* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
+* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
+* </tr>
+* <tr>
+* <td>1.0</td>
+* <td>Initial version</td>
+* <td></td>
+* </tr>
+* </table>
+*
+*
+* \defgroup group_system_config_macro Macros
+* \{
+* \defgroup group_system_config_system_macro System Macros
+* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status Macros
+* \defgroup group_system_config_user_settings_macro User Settings Macros
+* \}
+* \defgroup group_system_config_functions Functions
+* \{
+* \defgroup group_system_config_cm4_functions Cortex-M4 Control Functions
+* \}
+* \defgroup group_system_config_globals Global Variables
+*
+* \}
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*******************************************************************************
+* Include files
+*******************************************************************************/
+#include <stdint.h>
+
+
+/*******************************************************************************
+* Global preprocessor symbols/macros ('define')
+*******************************************************************************/
+#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
+ (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
+ (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
+ #define CY_SYSTEM_CPU_CM0P 1UL
+#else
+ #define CY_SYSTEM_CPU_CM0P 0UL
+#endif
+
+
+/*******************************************************************************
+*
+* START OF USER SETTINGS HERE
+* ===========================
+*
+* All lines with '<<<' can be set by user.
+*
+*******************************************************************************/
+
+/**
+* \addtogroup group_system_config_user_settings_macro
+* \{
+*/
+
+/*
+ * Include optional application-specific configuration header.
+ *
+ * For example, custom system_psoc6_config.h can be included here
+ * by adding the below macro definition to the build system:
+ * DEFINES+=CY_SYSTEM_PSOC6_CONFIG='"system_psoc6_config.h"'
+ */
+#if defined(CY_SYSTEM_PSOC6_CONFIG)
+#include CY_SYSTEM_PSOC6_CONFIG
+#endif
+
+
+/***************************************************************************//**
+* \brief Start address of the Cortex-M4 application ([address]UL)
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#if !defined (CY_CORTEX_M4_APPL_ADDR)
+ #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
+#endif /* (CY_CORTEX_M4_APPL_ADDR) */
+
+
+/***************************************************************************//**
+* \brief IPC Semaphores allocation ([value]UL).
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
+
+
+/***************************************************************************//**
+* \brief IPC Pipe definitions ([value]UL).
+* <i>(USER SETTING)</i>
+*******************************************************************************/
+#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
+
+
+/*******************************************************************************
+*
+* END OF USER SETTINGS HERE
+* =========================
+*
+*******************************************************************************/
+
+/** \} group_system_config_user_settings_macro */
+
+
+/**
+* \addtogroup group_system_config_system_macro
+* \{
+*/
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M0+ startup driver identifier */
+ #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
+#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
+
+#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
+ /** The Cortex-M4 startup driver identifier */
+ #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
+#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
+
+/** \} group_system_config_system_macro */
+
+
+/** \cond */
+#if defined(__ARMCC_VERSION)
+ extern void SystemInit(void) __attribute__((constructor));
+#else
+ extern void SystemInit(void);
+#endif /* (__ARMCC_VERSION) */
+
+extern void SystemCoreClockUpdate(void);
+/** \endcond */
+
+
+/**
+* \addtogroup group_system_config_cm4_functions
+* \{
+*/
+extern uint32_t Cy_SysGetCM4Status(void);
+extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
+extern void Cy_SysDisableCM4(void);
+extern void Cy_SysRetainCM4(void);
+extern void Cy_SysResetCM4(void);
+/** \} group_system_config_cm4_functions */
+
+
+/** \cond */
+extern void Default_Handler (void);
+
+void Cy_SysIpcPipeIsrCm0(void);
+void Cy_SysIpcPipeIsrCm4(void);
+
+extern void Cy_SystemInit(void);
+extern void Cy_SystemInitFpuEnable(void);
+
+extern uint32_t cy_delayFreqKhz;
+extern uint8_t cy_delayFreqMhz;
+/** \endcond */
+
+
+#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
+/**
+* \addtogroup group_system_config_cm4_status_macro
+* \{
+*/
+#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
+#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
+#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
+#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
+/** \} group_system_config_cm4_status_macro */
+
+#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
+
+
+/*******************************************************************************
+* IPC Configuration
+* =========================
+*******************************************************************************/
+/* IPC CY_PIPE default configuration */
+#define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
+
+#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
+#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
+#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
+
+#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
+#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
+
+
+/******************************************************************************/
+/*
+ * The System pipe configuration defines the IPC channel number, interrupt
+ * number, and the pipe interrupt mask for the endpoint.
+ *
+ * The format of the endPoint configuration
+ * Bits[31:16] Interrupt Mask
+ * Bits[15:8 ] IPC interrupt
+ * Bits[ 7:0 ] IPC channel
+ */
+
+/* System Pipe addresses */
+/* CyPipe defines */
+
+#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
+
+#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_CYPIPE_EP0)
+#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
+ | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
+ | CY_IPC_CHAN_CYPIPE_EP1)
+
+/******************************************************************************/
+
+
+
+/** \addtogroup group_system_config_globals
+* \{
+*/
+extern uint32_t cy_BleEcoClockFreqHz;
+/** \} group_system_config_globals */
+
+/** \cond INTERNAL */
+extern uint32_t cy_Hfclk0FreqHz;
+extern uint32_t cy_PeriClkFreqHz;
+extern uint32_t SystemCoreClock;
+extern uint32_t cy_AhbFreqHz;
+
+
+
+
+/*******************************************************************************
+* Backward compatibility macros. The following code is DEPRECATED and must
+* not be used in new projects
+*******************************************************************************/
+
+/* BWC defines for functions related to enter/exit critical section */
+#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
+#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
+#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
+#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
+#define cy_delayFreqHz (SystemCoreClock)
+
+/** \endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_PSOC6_H_ */
+
+
+/* [] END OF FILE */
diff --git a/boot/cypress/platforms/CYW20829.md b/boot/cypress/platforms/CYW20829.md
new file mode 100644
index 0000000..420d337
--- /dev/null
+++ b/boot/cypress/platforms/CYW20829.md
@@ -0,0 +1,249 @@
+## CYW20829 platform description
+
+### Prerequisites
+
+#### Cysecuretools
+
+The CYW20829 chip has a set of security features. A special tool called `cysecuretools` is required to use most of them.
+
+`Cysecuretools` is a Python3 package, which can be installed using the conventional `python pip` packet manager:
+
+ python -m pip install cysecuretools
+
+`Cysecuretools` is used for reprovisioning of the chip, revocation of keys, security counter updates, image encryption, and more. For more details on functionality, go to [https://pypi.org/project/cysecuretools](https://pypi.org/project/cysecuretools) or [https://github.com/Infineon/cysecuretools#provision-device](https://github.com/Infineon/cysecuretools#provision-device)
+
+Invocation of cysecuretools is build-in post-build jobs for `MCUBootApp` and `BlinkyApp`, so the user gets ready to use images after build.
+
+### MCUBootApp specifics
+The PSoC CYW20829 can work in two modes - Non-Secure and Secure. In the Non-Secure (NORMAL_NO_SECURE) mode the CYW20829 works as a 'usual' Infineon chip. In the SECURE mode the following functionality becomes available:
+ - signing of images;
+ - rollback protection (hardware secure counter).
+
+The work with the CYW20829 chip begins from the initialization of the project with the following device provisioning in the desired lifecycle - Non-Secure on Secure.
+
+### Device and environment initialization
+For the cysecuretools environment setup, the MCUboot `boot/cypress` folder is used.
+
+To create a common CYW20829 configuration, use:
+
+ cysecuretools -t cyw20829 init
+
+To configure an OpenOCD package patch (via ModusToolbox™ by default):
+
+ cysecuretools set-ocd --name openocd --path C:/Users/%USERNAME%/ModusToolbox/tools_2.4/openocd
+
+This is enough for a NORMAL_NO_SECURE lifecycle. But for SECURE `LCS`, a few more steps are necessary.
+
+You will need to generate an RSA key pair (or copy it to the keys folder, if it was generated previously), to provision a chip in Secure mode:
+
+ cysecuretools -t cyw20829 -p policy/policy_secure.json create-key -k N
+
+where N is the key number, zero or one.
+
+To get access to the chip after provisioning, a debug certificate is required:
+
+ cysecuretools -t cyw20829 -p policy/policy_secure.json debug-certificate -t packets/debug_cert.json -o packets/debug_cert.bin -k N
+
+where N is the key number, zero or one.
+
+### CYW20829 provisioning and reprovisioning
+
+For the first provision of the CYW20829 chip, use:
+
+ cysecuretools -t cyw20829 -p policy/policy_%LCS%.json provision-device
+
+or
+
+ cysecuretools -t cyw20829 -p policy/policy_reprovisioning_%LCS%.json reprovision-device [--key-id N]
+
+for the following reprovision procedure.
+
+More details about provisioning and reprovisioning processes you can find in [README_CYW20829.md](https://github.com/Infineon/cysecuretools/blob/master/docs/README_CYW20829.md#command-provision-device)
+
+### Default memory map
+
+The repository provides a set of predefined memory maps in JSON files. They are located in `platforms/cy_flash_pal/flash_CYW20829/flashmap`. One can use the predefined flash map or define your own using the predefined file as a template.
+
+### Encrypted image support
+
+CYW20829 does not have internal flash memory, so both primary and secondary images are located in external memory.
+
+To protect the firmware from reading, place it in external memory in the encrypted form.
+
+CYW20829 can execute encrypted firmware directly using the onboard hardware interface (SMIF) with special mode XIP (eXecute-In-Place). In this mode, all code is decrypted transparently by the AES algorithm.
+
+MCUboot has its own Encrypted image mode to encrypt the firmware and transfer it with the AES session key included in the HKDF data block.
+
+**MCUboot image validation flow**
+
+- Decrypt the AES key / initial vector (IV) from HKDF
+- Set up AES IV + CTR nonce (Image addr = base_addr + header_size)
+- Read slot data by MMIO
+- Decrypt the image in the slot using MCUboot internal functionality
+- Calculate and verify hash from decrypted data
+- Validate the slot image by hash and sign it
+
+**MCUboot image upgrade flow**
+
+- Read slot 1 sector data using MMIO
+- Skip data decryption
+- Write data to the primary slot using MMIO
+
+**MCUboot Application Run**
+- Set up SMIF registers
+- Set the AES key
+- Set AES IV
+- Set SMIF mode to XIP
+- Go to the application entry point
+
+MCUBootApp and BlinkyApp can be built with an encrypted image plus encrypted XIP support using special build flags `ENC_IMG=1`. That flag will automatically enable XIP mode.
+
+Example build command for MCUBootApp:
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
+
+Example build command for BlinkyApp:
+
+ make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
+
+### Rollback protection Support
+
+As mentioned above, to use the rollback protection feature the device must be transferred to the SECURE lifecycle. The CYW20829 platform has a hardware-supported feature - a non-volatile counter (NV-counter). This feature is used by the MCUboot library to implement the rollback protection counter (security counter). NV-counter on CYW20829 is implemented as an Efuse-type region that can only be incremented. This means, that each time a new counter value is updated - a corresponding number of Efuse is burned.
+
+The initial value of the rollback counter is programmed into the chip at the provisioning stage. The provisioning policy for Secure mode contains a corresponding field (file `policy/policy_secure.json`):
+
+
+ "reprovisioning":
+ {
+ "nv_counter": {
+ "description": "Anti-rollback counter (supports up to 32 updates)",
+ "value": 0
+ },
+
+If the `nv_counter` value is left untouched, any image with counters higher than 0 and less than (or equal to) 32 can be programmed into the chip.
+If the `nv_counter` value is encreased in `policy/policy_secure.json` at the provisioning stage, the `nv_counter` value in `policy/policy_reprovisioning_secure.json` must start from the value not less than the value in `policy/policy_secure.json` file.
+More details about provisioning and reprovisioning processes you can find in [README_CYW20829.md](https://github.com/Infineon/cysecuretools/blob/master/docs/README_CYW20829.md#command-provision-device)
+
+When preparing an image for MCUBootApp with the rollback counter support, the `cysecuretools` sign it with `policy/policy_secure.json` in the post-build stage of 'make'. The `nv_counter` value remains the same as one in the chip or sets higher. When `cysecuretools` signs an image, it places the `nv-counter` value and the reprovisioning packet in TLVs with tags 0x50 (plain value of the counter) and 0x51 (reprovisioning packet). MCUBootApp then parses these tags and compares the value supplied with the image against the one stored in the Efuse counter.
+
+### Building MCUBootApp and BlinkyApp with rollback protection
+
+Examples of the build command with the rollback counter support for a single image and 'Overwride' mode:
+for MCUBootApp:
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 APP_DEFAULT_POLICY=./policy/policy_secure.json BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json LCS=SECURE
+
+for BlinkyApp with TLVs containing rollback counter data:
+ - BOOT slot:
+
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
+
+ - UPGRADE slot:
+
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
+
+#### NV-counter update
+
+To update NV-counter for an appropriate image you have to increase NV-counter in the reprovisioning policy `/policy/policy_reprovisioning_secure.json`, after that re-build the `BlinkyApp` and re-program your device.
+
+The CYW20829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of Efuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `cysecuretools` under `targets/cyw20829/packets/apps`. The `reprovisioning` application is used for NV-counter updates.
+
+To enable the rollback counter feaure, one have to use a JSON flash map with the `"service_app"` section. Sample flash maps are located in `boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot`.
+
+The service application is supplied as a precompiled binary executed from RAM by BootROM. User should program either `cyapp_reprovisioning_signed.hex` (located at `./MCUBootApp/out/CYW20829/Debug/cyapp_reprovisioning_signed.hex`) or similar binary `./packets/apps/reprovisioning/cyapp_reprovisioning_signed.bin` (with the `"address"` specified in the `"service_app"` section of JSON flash map). Some other data is required for BootROM to execute the service app - this data is prepared by MCUBootApp.
+
+When MCUBootApp detects that the rollback counter must be updated on CYW20829, it executes the function, which prepares input data and service application descriptor data and places it in flash at addresses `"params_address"` and `"desc_address"`, respectively (see the `"service_app"` section in JSON flash map). Then, it sets the special flag in the service register, which signalizes BootROM to launch the service application and calls a system reset. BootROM then detects the service app with its data, copies it to the corresponding addresses in RAM, and executes it. Reprovisioning app then updates the `nv-counter` value in Efuse. An automatic reset can (and for convenience should) be initiated after that. To allow this value, `sys_reset_req` is set to `true` (`false` by default).
+
+ "sys_reset_req": {
+ "description": "Resets a device after RAM application finishes execution.",
+ "value": true
+ }
+
+For more details on BootROM service applications, refer to the CYW20829 documentation.
+
+#### Rollback counter behavior
+
+**Case 1**
+
+An image is singed using the `policy_reprovisioning_secure.json` policy with the `nv-counter` field value set to 1; the current value of NV-counter in the chip is `0` and programmed to the primary slot of MCUBootApp.
+
+MCUBootApp validates the image in the primary slot and initiates a rollback counter update. The image in the primary slot is started after that.
+
+**Case 2**
+
+An image is signed using the `policy_reprovisioning_secure.json` policy with `nv-counter`, the field value is set to 2; the current value of NV-counter in the chip is `1` and programmed into the secondary slot of MCUBootApp. The upgrade type is 'swap'.
+
+MCUBootApp validates the image in the secondary slot and initiates a firmware upgrade. After swapping the primary and
+secondary images, the firmware from the primary slot is executed immediately after the upgrade.
+
+- If the upgraded firmware operates correctly - starts its execution and sets the confirmation flag (read more in the design.md file), then, after the next reset, MCUBootApp updates the rollback counter value as in Case 1.
+
+- If the upgraded firmware operates incorrectly - does not start or does not set the confirmation flag, the watchdog initiates a system reset and MCUBootApp performs the `revert` operation - copies back the previous firmware from the secondary to the primary slot, marks the image in the secondary slot as invalid and executes the original firmware from the primary slot. **The rollback counter is not updated in this case.**
+
+**Case 3**
+
+An image is signed with the `policy_reprovisioning_secure.json` policy with `nv-counter`, the field value is set to 3; the current value of NV-counter in the chip is `4` and programmed to the secondary or primary slot of MCUBootApp. The upgrade type is 'swap'.
+
+MCUBootApp tries to validate the image, detects that the value of the rollback counter stored in the chip is greater than the one provided with the image, and rejects such an image. The firmware in the primary slot will not start and an upgrade will not be initiated.
+
+When the reprovisioning packet TLV is absent in the primary or secondary image TLVs, MCUBootApp marks such an image as invalid.
+
+**Multi-image case**
+
+Since there is only one physical security counter available on `CYW20829` in a multi-image use case, all images in the system should have the same value of security counter.
+
+For example, two images are programmed to their corresponding BOOT slots with a security counter value of 2. The value of the security counter stored in the chip is also 2. In case one of the images requires an update and its value of the security counter is increased to 3 - the second image should also be updated with a counter value of 3. This is required because `BootROM` will update the security image counter stored in the chip to 3 per first upgrade image. After that - the second image would become invalid since it still contains a security counter of 2. These restrictions will be removed in the release of MCUBoot version 1.8.3.
+
+Examples of the build command with the rollback counter support for the multi-image case, swap mode:
+
+for MCUBootApp:
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 APP_DEFAULT_POLICY=./policy/policy_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json LCS=SECURE USE_HW_ROLLBACK_PROT=1
+
+for BlinkyApp with TLVs containing rollback counter data:
+ - BOOT slot, IMG_ID=1:
+
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=1
+ - UPGRADE slot, IMG_ID=1:
+
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=1
+
+ - BOOT slot, IMG_ID=2:
+
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=2
+
+ - UPGRADE slot, IMG_ID=2:
+
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=2
+
+**Attention!** Don't omit `clean_boot` and `clean_upgrade` to avoid any issues!
+
+### Programming applications
+The HEXes for device programming you can find:
+
+for MCUBootApp: `MCUBootApp.hex` in the directory 'MCUBootApp/out/CYW20829/*{BUILDCFG}*/
+
+for BlinkyApp:
+ - for IMG_ID=1, BOOT slot select `BlinkyApp.hex` inside of 'BlinkyApp/**out**/CYW20829/*{BUILDCFG}*/**boot**/'
+ - for IMG_ID=1, UPGRADE slot select `BlinkyApp_upgrade.hex` inside of 'BlinkyApp/**out**/CYW20829/*{BUILDCFG}*/**upgrade**/
+ - for IMG_ID=2, BOOT slot select `BlinkyApp.hex` inside of 'BlinkyApp/**out.id2**/CYW20829/*{BUILDCFG}*/**boot**/'
+ - for IMG_ID=1, UPGRADE slot select `BlinkyApp_upgrade.hex` inside of 'BlinkyApp/**out.id2**/CYW20829/*{BUILDCFG}*/**upgrade**/
+
+Default **{BUILDCFG}** is 'Debug', so all previous commands for the 'multi-image' case will build a 'Debug' configuration.
+
+#### Using OpenOCD from command line
+
+The following instruction assumes the usage of one of Cypress KitProg3 devices and a development board.
+
+Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
+
+Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION` and `OPENOCD` variables:
+
+ export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
+
+ $OPENOCD_PATH/bin/openocd -s $OPENOCD_PATH/scripts -c "set ENABLE_ACQUIRE 0" -f $OPENOCD_PATH/scripts/interface/kitprog3.cfg -c "set SMIF_BANKS { 0 {addr 0x60000000 size 0x4000000 psize 0x1000 esize 0x40000} }" -f $OPENOCD_PATH/scripts/target/cyw20829.cfg -c "init; reset init; cmsis_flash init; flash write_image %PATH_TO_APPLICATION%/BlinkyApp.hex; shutdown"
+
+**Warning**
+
+The application slot is erased by `flash erase_address` before executing the `flash write_image` command.
+
diff --git a/boot/cypress/platforms/CYW20829/CYW20829.mk b/boot/cypress/platforms/CYW20829.mk
similarity index 85%
rename from boot/cypress/platforms/CYW20829/CYW20829.mk
rename to boot/cypress/platforms/CYW20829.mk
index 902ede3..727a83b 100644
--- a/boot/cypress/platforms/CYW20829/CYW20829.mk
+++ b/boot/cypress/platforms/CYW20829.mk
@@ -31,6 +31,7 @@
# PDL category suffix to resolve common path in pdl
PDL_CAT_SUFFIX := 1B
+CRYPTO_ACC_TYPE := MXCRYPTOLITE
# MCU device selection, based on target device.
# Default chips are used for supported platforms
@@ -38,10 +39,17 @@
DEVICE ?= CYW20829A0LKML
# If PSVP build is required
ifeq ($(CYW20829_PSVP), 1)
-DEVICE := CYW20829_PSVP
SERVICE_APP_PLATFORM_SUFFIX := _psvp
endif
+#Led pin default config
+LED_PORT_DEFAULT ?= GPIO_PRT0
+LED_PIN_DEFAULT ?= 0U
+
+#UART default config
+UART_TX_DEFAULT ?= CYBSP_DEBUG_UART_TX
+UART_RX_DEFAULT ?= CYBSP_DEBUG_UART_RX
+
PLATFORM_SUFFIX ?= cyw20829
# Add device name to defines
@@ -54,9 +62,6 @@
FLASH_START := 0x60000000
FLASH_XIP_START := 0x08000000
-# Bootloader size
-PLATFORM_BOOTLOADER_SIZE ?= 0x20000
-
###############################################################################
# Application specific libraries
###############################################################################
@@ -66,23 +71,22 @@
ifeq ($(APP_NAME), MCUBootApp)
-PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/cy_flash_pal
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/flash_qspi
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/include
-# INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/include/flash_map_backend)
-PLATFORM_SOURCES_FLASH := $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/*.c)
-PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/flash_qspi/*.c)
+PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/platforms/cy_flash_pal
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/flash_qspi
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/include
+PLATFORM_SOURCES_FLASH := $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/*.c)
+PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/*.c)
# Platform dependend utils files
-PLATFORM_APP_SOURCES := $(PRJ_DIR)/platforms/$(FAMILY)/utils/cyw_20829_utils.c
-PLATFORM_INCLUDE_DIRS_UTILS := $(PRJ_DIR)/platforms/$(FAMILY)/utils
+PLATFORM_APP_SOURCES := $(PRJ_DIR)/platforms/utils/$(FAMILY)/cyw_platform_utils.c
+PLATFORM_INCLUDE_DIRS_UTILS := $(PRJ_DIR)/platforms/utils/$(FAMILY)
# mbedTLS hardware acceleration settings
ifeq ($(USE_CRYPTO_HW), 1)
# cy-mbedtls-acceleration related include directories
-INCLUDE_DIRS_MBEDTLS_CRYPTOLITE := $(PRJ_DIR)/platforms/$(FAMILY)/mbedtls_Cryptolite
+INCLUDE_DIRS_MBEDTLS_CRYPTOLITE := $(PRJ_DIR)/platforms/crypto/$(FAMILY)/mbedtls_Cryptolite
# Collect source files for MbedTLS acceleration
-SOURCES_MBEDTLS_CRYPTOLITE := $(wildcard $(PRJ_DIR)/platforms/$(FAMILY)/mbedtls_Cryptolite/*.c)
+SOURCES_MBEDTLS_CRYPTOLITE := $(wildcard $(PRJ_DIR)/platforms/crypto/$(FAMILY)/mbedtls_Cryptolite/*.c)
#
INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS_CRYPTOLITE))
# Collected source files for libraries
@@ -91,8 +95,9 @@
###############################################################################
# Application dependent definitions
-# MCUBootApp
-# Default settings
+# MCUBootApp default settings
+USE_CRYPTO_HW ?= 1
+
USE_EXTERNAL_FLASH := 1
PROVISION_PATH ?= $(PRJ_DIR)
LCS ?= NORMAL_NO_SECURE
@@ -141,8 +146,8 @@
post_build: $(OUT_CFG)/$(APP_NAME).elf
ifeq ($(POST_BUILD_ENABLE), 1)
$(info [TOC2_Generate] - Execute toc2 generator script for $(APP_NAME))
- @echo $(SHELL) $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(PLATFORM_BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM_SERVICE_APP_DESC_OFFSET)
- $(shell $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(PLATFORM_BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM_SERVICE_APP_DESC_OFFSET))
+ @echo $(SHELL) $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM_SERVICE_APP_DESC_OFFSET)
+ $(shell $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PROVISION_PATH) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH) $(APP_DEFAULT_POLICY) $(BOOTLOADER_SIZE) $(ENC_IMG) $(PLATFORM_SERVICE_APP_DESC_OFFSET))
# Convert binary to hex and rename
$(shell mv -f $(OUT_CFG)/$(APP_NAME).final.bin $(OUT_CFG)/$(APP_NAME).bin || rm -f $(OUT_CFG)/$(APP_NAME).bin)
@@ -184,12 +189,12 @@
PLATFORM_DEFINES_APP += -DUSER_APP_START_OFF=0x20000
-PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/cy_flash_pal
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/flash_qspi
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/include
-PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_cyw208xx/flash_qspi/*.c)
+PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/platforms/cy_flash_pal
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/flash_qspi
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/include
+PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/*.c)
-PLATFORM_DEFAULT_IMG_VER_ARG ?=
+PLATFORM_DEFAULT_IMG_VER_ARG ?= 1.0.0
PLATFORM_SIGN_ARGS := --image-format $(SIGN_TYPE) -i $(OUT_CFG)/$(APP_NAME).final.bin -o $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).bin --key-path $(PRJ_DIR)/keys/cypress-test-ec-p256.pem --update-key-path $(PRJ_DIR)/keys/priv_oem_0.pem --slot-size $(SLOT_SIZE) --align 1
@@ -224,9 +229,8 @@
###############################################################################
# Common libraries
###############################################################################
-PLATFORM_SYSTEM_FILE_NAME := non-secure/ns_system_$(PLATFORM_SUFFIX).c
-PLATFORM_SOURCES_PDL_STARTUP := non-secure/ns_start_$(PLATFORM_SUFFIX).c
-PLATFORM_SOURCES_PDL_RUNTIME := non-secure/ns_runtime_$(PLATFORM_SUFFIX).c
+PLATFORM_SYSTEM_FILE_NAME := ns_system_$(PLATFORM_SUFFIX).c
+PLATFORM_SOURCES_PDL_STARTUP := ns_start_$(PLATFORM_SUFFIX).c
PLATFORM_SOURCES_RETARGET_IO := $(wildcard $(PRJ_DIR)/libs/retarget-io/*.c)
@@ -234,7 +238,7 @@
PLATFORM_SOURCES_HAL += $(PRJ_DIR)/libs/mtb-hal-cat1/COMPONENT_CAT$(PDL_CAT_SUFFIX)/source/triggers/cyhal_triggers_cyw20829.c
PLATFORM_SOURCES_HAL += $(wildcard $(PRJ_DIR)/libs/mtb-hal-cat1/source/*.c)
-PLATFORM_INCLUDE_DIRS_PDL_STARTUP := $(PRJ_DIR)/libs/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/templates/COMPONENT_MTB/COMPONENT_$(CORE)/$(HEADER_FILES)
+PLATFORM_INCLUDE_DIRS_PDL_STARTUP := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system
PLATFORM_INCLUDE_DIRS_RETARGET_IO := $(PRJ_DIR)/libs/retarget-io
@@ -258,6 +262,7 @@
$(info APPTYPE <-> $(APPTYPE))
$(info APP_DEFAULT_POLICY <-> $(APP_DEFAULT_POLICY))
$(info APP_NAME <-- $(APP_NAME))
+$(info BOOTLOADER_SIZE <-- $(BOOTLOADER_SIZE))
$(info CFLAGS_PLATFORM --> $(CFLAGS_PLATFORM))
$(info CORE <-> $(CORE))
$(info CORE_SUFFIX --> $(CORE_SUFFIX))
@@ -275,10 +280,11 @@
$(info INCLUDE_DIRS_LIBS --> $(INCLUDE_DIRS_LIBS))
$(info INCLUDE_DIRS_MBEDTLS_CRYPTOLITE <-> $(INCLUDE_DIRS_MBEDTLS_CRYPTOLITE))
$(info LCS <-> $(LCS))
+$(info LED_PIN_DEFAULT --> $(LED_PIN_DEFAULT))
+$(info LED_PORT_DEFAULT --> $(LED_PORT_DEFAULT))
$(info OUT_CFG <-- $(OUT_CFG))
$(info PDL_CAT_SUFFIX <-> $(PDL_CAT_SUFFIX))
$(info PLATFORM_APP_SOURCES --> $(PLATFORM_APP_SOURCES))
-$(info PLATFORM_BOOTLOADER_SIZE <-> $(PLATFORM_BOOTLOADER_SIZE))
$(info PLATFORM_CHUNK_SIZE --> $(PLATFORM_CHUNK_SIZE))
$(info PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE --> $(PLATFORM_CY_MAX_EXT_FLASH_ERASE_SIZE))
$(info PLATFORM_DEFAULT_ERASED_VALUE --> $(PLATFORM_DEFAULT_ERASED_VALUE))
@@ -310,7 +316,6 @@
$(info PRJ_DIR <-- $(PRJ_DIR))
$(info PROVISION_PATH <-> $(PROVISION_PATH))
$(info SERVICE_APP_NAME <-> $(SERVICE_APP_NAME))
-$(info SERVICE_APP_OFFSET <-- $(SERVICE_APP_OFFSET))
$(info SERVICE_APP_PATH <-> $(SERVICE_APP_PATH))
$(info SERVICE_APP_PLATFORM_SUFFIX <-> $(SERVICE_APP_PLATFORM_SUFFIX))
$(info SHELL <-- $(SHELL))
@@ -321,8 +326,10 @@
$(info SOURCES_LIBS --> $(SOURCES_LIBS))
$(info SOURCES_MBEDTLS_CRYPTOLITE <-> $(SOURCES_MBEDTLS_CRYPTOLITE))
$(info TOOLCHAIN_PATH <-- $(TOOLCHAIN_PATH))
+$(info UART_RX_DEFAULT --> $(UART_RX_DEFAULT))
+$(info UART_TX_DEFAULT --> $(UART_TX_DEFAULT))
$(info UPGRADE_SUFFIX <-- $(UPGRADE_SUFFIX))
-$(info USE_CRYPTO_HW <-- $(USE_CRYPTO_HW))
+$(info USE_CRYPTO_HW <-> $(USE_CRYPTO_HW))
$(info USE_CUSTOM_MEMORY_MAP --> $(USE_CUSTOM_MEMORY_MAP))
$(info USE_EXTERNAL_FLASH --> $(USE_EXTERNAL_FLASH))
$(info USE_HW_ROLLBACK_PROT <-- $(USE_HW_ROLLBACK_PROT))
diff --git a/boot/cypress/platforms/CYW20829/CYW20829.md b/boot/cypress/platforms/CYW20829/CYW20829.md
deleted file mode 100644
index 4d591c6..0000000
--- a/boot/cypress/platforms/CYW20829/CYW20829.md
+++ /dev/null
@@ -1,198 +0,0 @@
-## CYW20829 platform description
-
-### Prerequisites
-
-#### Cysecuretools
-
-The CYW20829 chip has a set of security features. The special tool called `cysecuretools` is required to use most of them.
-
-Cysecuretools is a Python3 package, which can be installed using the conventional `python pip` packet manager:
-
- python -m pip install cysecuretools
-
-Cysecuretools is used for reprovisioning of the chip, revocation of keys, security counter updates, image encryption and more. For more details on functionality, go to https://pypi.org/project/cysecuretools/
-
-Invocation of cysecuretools is build-in post build jobs for `MCUBootApp` and `BlinkyApp`, so the user gets ready to use images after build.
-
-### MCUBootApp specifics
-
-### Default memory map
-
-This repository provides a set of predefined memory maps in JSON files. They are located in `cy_flash_pal/flash_%platform_name%/flashmap`. One can use the predefined flash map or define its own using the predefined file as a template.
-
-### Encrypted image support
-
-CYW20829 does not have internal flash memory, so both primary and secondary images are located in external memory.
-
-To protect the firmware from read, place it in external memory in the encrypted form.
-
-CYW20829 can execute encrypted firmware directly using the onboard hardware interface (SMIF) with special mode XIP (eXecute-In-Place). In this mode all code is decrypted transparently by AES algorithm.
-
-MCUboot has its own Encrypted image mode to encrypt the firmware and transfer it with the AES session key included in the HKDF data block.
-
-**MCUboot image validation flow**
-
-- Decrypt the AES key / initial vector (IV) from HKDF
-- Set up AES IV + CTR nonce (Image addr = base_addr + header_size)
-- Read slot data by MMIO
-- Decrypt the image in the slot using MCUboot internal functionality
-- Calculate and verify hash from decrypted data
-- Validate the slot image by hash and sign it
-
-**MCUboot image upgrade flow**
-
-- Read slot 1 sector data using MMIO
-- Skip data decryption
-- Write data to the primary slot using MMIO
-
-**MCUboot Application Run**
-- Set up SMIF registers
-- Set the AES key
-- Set AES IV
-- Set SMIF mode to XIP
-- Go to the application entry point
-
-MCUBootApp and BlinkyApp can be built with an encrypted image plus encrypted XIP support using special build flags `ENC_IMG=1`. That flag will automatically enable XIP mode.
-
-Example build command for MCUBootApp:
-
- make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
-
-Example build command for BlinkyApp:
-
- make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
-
-### Rollback protection Support
-
-The CYW20829 platform has a hardware-supported feature - a non-volatile counter (NV-counter). This feature is used by the MCUboot library to implement the rollback counter (security counter) protection. NV-counter on CYW20829 is implemented as an Efuse-type region that can only be incremented. This means, that each time a new counter value is updated - a corresponding number of Efuse is burned.
-
-The initial value of the rollback counter is programmed into the chip at the provisioning stage. The provisioning policy for Secure mode contains a corresponding field:
-
-
- "reprovisioning":
- {
- "nv_counter": {
- "description": "Anti-rollback counter (supports up to 32 updates)",
- "value": 0
- },
-
-If the `nv_counter` value is left untouched, any image with counters higher than 0 and less than (or equal to) 32 can be programmed into the chip.
-
-When preparing an image for MCUBootApp with the rollback counter support, sign it with `cysecuretools` using `policy/policy_reprovisioning_secure.json` supplied with it. The `nv_counter` value remains the same as one in the chip or set higher. When signing image `cysecuretools` places the `nv-counter` value and the reprovisioning packet in TLVs with tags 0x50 (plain value of counter) and 0x51 (reprovisioning packet). MCUBootApp then parses these tags and compares the value supplied with the image against the one stored in the Efuse counter.
-
-#### NV-counter update
-
-The CYW20829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of Efuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `cysecuretools` under `targets/cyw20829/packets/apps`. The `reprovisioning` application is used for NV-counter update.
-
-To enable the rollback counter feaure, one have to use a JSON flash map with the `"service_app"` section. Sample flash maps are located in `boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot`.
-
-The service application is supplied as a precompiled binary executed from RAM by BootROM. User should program either `cyapp_reprovisioning_signed.hex` (located at `./MCUBootApp/out/CYW20829/Debug/cyapp_reprovisioning_signed.hex`) or similar binary `./packets/apps/reprovisioning/cyapp_reprovisioning_signed.bin` (with the `"address"` specified in the `"service_app"` section of JSON flash map). Some other data is required for BootROM to execute the service app - this data is prepared by MCUBootApp.
-
-When MCUBootApp detects that the rollback counter must be updated on CYW20829, it executes the function, which prepares input data and service application descriptor data and places it in flash at addresses `"params_address"` and `"desc_address"`, respectively (see the `"service_app"` section in JSON flash map). Then, it sets the special flag in the service register, which signalizes BootROM to launch the service application and calls a system reset. BootROM is then detects the service app with its data, copies it to the corresponding addresses in RAM and executes it. Reprovisioning app then updates the `nv-counter` value in Efuse. An automatic reset can (and for convenience should) be initiated after that. To allow this value, `sys_reset_req` is set to `true` (`false` by default).
-
- "sys_reset_req": {
- "description": "Resets a device after RAM application finishes execution.",
- "value": true
- }
-
-For more details on BootROM service applications, refer to the CYW20829 documentation.
-
-#### Rollback counter behavior
-
-**Case 1**
-
-An image is singed using the `policy_reprovisioning_secure.json` policy with `nv-counter` field value set to 1; the current value of NV-counter in chip is `0` and programmed to the primary slot of MCUBootApp.
-
-MCUBootApp validates the image in the primary slot and initiates a rollback counter update. The image in the primary slot is started after that.
-
-**Case 2**
-
-An image is signed using the `policy_reprovisioning_secure.json` policy with `nv-counter`, the field value is set to 2; the current value of NV-counter in the chip is `1` and programmed into the secondary slot of MCUBootApp. The ugrade type is swap using the status partition.
-
-MCUBootApp validates the image in the secondary slot and initiates a firmware upgrade. After swapping the primary and
-secondary images, the firmware from the primary slot is executed immediately after upgrade.
-
-- If upgraded firmware operates correctly - starts its execution and sets the confirmation flag (read more in the design.md file), then, after a next reset, MCUBootApp updates the rollback counter value as in Case 1.
-
-- If upgraded firmware operates incorrectly - does not start or does not set the confirmation flag, the watchdog initiates a system reset and MCUBootApp performs the `revert` operation - copies back the previous firmware from the secondary to the primary slot, marks the image in the secondary slot as invalid and executes the original firmware from the primary slot. **The rollback counter is not updated in this case.**
-
-**Case 3**
-
-An image is signed with the `policy_reprovisioning_secure.json` policy with `nv-counter`, the field value is set to 3; the current value of NV-counter in chip is `4` and programmed to the secondary or primary slot of MCUBootApp. The upgrade type is swap using the status partition.
-
-MCUBootApp tries to validate the image, detects that the value of the rollback counter stored in the chip is greater than the one provided with the image, and rejects such an image. The firmware in the primary slot will not start and upgrade will not be initiated.
-
-When the reprovisioning packet TLV is absent in the primary or secondary image TLVs, MCUBootApp marks such an image as invalid.
-
-**Multi image case**
-
-Since there is only one physical security counter available on `CYW20829` in multi image use case, all images in system should have the same value of security counter.
-
-For example two images are programmed to their corresponding BOOT slots with security counter value of 2. Value of security counter stored in chip is also 2. In case one of images requires update and its value of security counter is increased to 3 - second image should also be updated with counter value of 3. This is required because `BootROM` will update security image counter stored in chip to 3 per first upgrade image. After that - second image would become invalid sice it still contains security counter of 2.
-
-An example of the build command for MCUBootApp with the rollback counter support:
-
- make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
-
-An example of the build command for BlinkyApp with TLVs containing rollback counter data:
-
- make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
-
-### Build environment preparation
-
-For cysecuretools environment setup, the MCUboot `boot/cypress` folder is used.
-
-To create common CYW20829 configuration, use:
-
- cysecuretools -t cyw20829 init
-
-To configure an OpenOCD package patch (via ModusToolbox™ by default):
-
- cysecuretools set-ocd --name openocd --path C:/Users/%USERNAME%/ModusToolbox/tools_2.4/openocd
-
-This is enough for a NORMAL_NO_SECURE lifecycle. But for SECURE `LCS`, a few more steps are necessary.
-
-You will need to generate an RSA key pair (or copy it to keys folder, if it was generated previously), in order to provision a silicon in Secure mode:
-
- cysecuretools -t cyw20829 -p policy/policy_secure.json create-key -k N
-
-where N is the key number, zero or one.
-
-To get access to the chip after provisioning, a debug certificate is required:
-
- cysecuretools -t cyw20829 -p policy/policy_secure.json debug-certificate -t packets/debug_cert.json -o packets/debug_cert.bin -k N
-
-where N is the key number, zero or one.
-
-### CYW20829 provisioning
-
-For the first provision of CYW20829 chip, use:
-
- cysecuretools -t cyw20829 -p policy/policy_%LCS%.json provision-device
-
-or
-
- cysecuretools -t cyw20829 -p policy/policy_reprovisioning_%LCS%.json reprovision-device [--key-id N]
-
-for the following reprovision procedure.
-
-For more details on the CYW20829 environment setup and provisioning, go to the cysecuretools `README_CYW20829.md` file.
-
-### Programming applications
-
-#### Using OpenOCD from command line
-
-The following instruction assume the usage of one of Cypress KitProg3 devices and a development board.
-
-Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
-
-Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION` and `OPENOCD` variables:
-
- export OPENOCD=/Applications/ModusToolbox/tools_2.4/openocd
-
- $OPENOCD_PATH/bin/openocd -s $OPENOCD_PATH/scripts -c "set ENABLE_ACQUIRE 0" -f $OPENOCD_PATH/scripts/interface/kitprog3.cfg -c "set SMIF_BANKS { 0 {addr 0x60000000 size 0x4000000 psize 0x1000 esize 0x40000} }" -f $OPENOCD_PATH/scripts/target/cyw20829.cfg -c "init; reset init; cmsis_flash init; flash write_image %PATH_TO_APPLICATION%/BlinkyApp.hex; shutdown"
-
-**Warning**
-
-The application slot is erased by `flash erase_address` before executing the `flash write_image` command.
-
diff --git a/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.c b/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.c
deleted file mode 100644
index 6adee83..0000000
--- a/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * mbed Microcontroller Library
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * Copyright (c) 2021 Infineon Technologies AG
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if defined(MBEDTLS_CONFIG_FILE)
-#include MBEDTLS_CONFIG_FILE
-#else
-#include "config.h"
-#endif
-
-#if defined(MBEDTLS_SHA256_C)
-
-#include "mbedtls/sha256.h"
-#include "mbedtls/platform_util.h"
-
-#if defined(MBEDTLS_SHA256_ALT)
-
-/* Uncomment for distinct error codes */
-/* #define MAP_SPECIFIC_ERROR_CODES */
-
-/* Cy_Cryptolite_Sha256_Update() fails with CY_CRYPTOLITE_BUS_ERROR for data
- * from Flash, if length is 64 bytes or more.
- */
-#define CYW20829_SHA256_FLASH_WORKAROUND
-
-/* Parameter validation macros based on platform_util.h */
-#define SHA256_VALIDATE_RET(cond) \
- MBEDTLS_INTERNAL_VALIDATE_RET((cond), MBEDTLS_ERR_SHA256_BAD_INPUT_DATA)
-
-#define SHA256_VALIDATE(cond) MBEDTLS_INTERNAL_VALIDATE(cond)
-
-#ifdef CYW20829_SHA256_FLASH_WORKAROUND
-
-#ifndef CYW20829
-#error Workaround is only for CYW20829!
-#endif /* CYW20829 */
-
-#include "cyw20829_partition.h"
-
-/* Largest safe length for Cy_Cryptolite_Sha256_Update() */
-#define CYW20829_SHA256_SAFE_CHUNK_SIZE 63u
-
-#endif /* CYW20829_SHA256_FLASH_WORKAROUND */
-
-/**
- * \brief Map Cryptolite status to mbed TLS error code.
- *
- * \param status The \c CY_CRYPTOLITE_??? function status.
- * \return \c 0 on success.
- * \return A negative error code on failure.
- */
-static
-#ifndef MAP_SPECIFIC_ERROR_CODES
-inline __attribute__((always_inline))
-#endif /* MAP_SPECIFIC_ERROR_CODES */
-int cryptolite_to_mbedtls(cy_en_cryptolite_status_t status)
-{
- int rc = -1;
-
- switch (status) {
- case CY_CRYPTOLITE_SUCCESS:
- rc = 0;
- break;
-
-#ifdef MAP_SPECIFIC_ERROR_CODES
- case CY_CRYPTOLITE_BAD_PARAMS:
- rc = MBEDTLS_ERR_SHA256_BAD_INPUT_DATA;
- break;
-
- case CY_CRYPTOLITE_HW_BUSY:
- case CY_CRYPTOLITE_BUS_ERROR:
- rc = MBEDTLS_ERR_SHA256_HW_ACCEL_FAILED;
- break;
-#endif /* MAP_SPECIFIC_ERROR_CODES */
-
- default:
- break;
- }
-
- return rc;
-}
-
-/**
- * \brief Zeroize memory block. There is no Cy_Crypto_Core_MemSet() in
- * Cryptolite, and no memset_s() in newlib-nano.
- *
- * \param buf The buffer to zeroize.
- * \param len The length of the buffer in Bytes.
- */
-static inline __attribute__((always_inline))
-void zeroize(void *buf, size_t len)
-{
- volatile uint8_t *p = (volatile uint8_t *)buf;
-
- while (len > 0u) {
- *p++ = 0u;
- len--;
- }
-}
-
-/**
- * \brief This function initializes a SHA-256 context.
- *
- * \param ctx The SHA-256 context to initialize. This must not be \c NULL.
- */
-void mbedtls_sha256_init(mbedtls_sha256_context *ctx)
-{
- cy_en_cryptolite_status_t status;
-
- SHA256_VALIDATE(ctx != NULL);
- zeroize(ctx, sizeof(*ctx));
-
- /* There is some chance crypto HW might be busy here */
- do {
- status = Cy_Cryptolite_Sha256_Init(CRYPTO, ctx);
- } while (CY_CRYPTOLITE_HW_BUSY == status);
-
- SHA256_VALIDATE(CY_CRYPTOLITE_SUCCESS == status);
-}
-
-/**
- * \brief This function clears a SHA-256 context.
- *
- * \param ctx The SHA-256 context to clear. This may be \c NULL, in which
- * case this function returns immediately. If it is not \c NULL,
- * it must point to an initialized SHA-256 context.
- */
-void mbedtls_sha256_free(mbedtls_sha256_context *ctx)
-{
- if (ctx != NULL) {
- (void)Cy_Cryptolite_Sha256_Free(CRYPTO, ctx);
- zeroize(ctx, sizeof(*ctx));
- }
-}
-
-/**
- * \brief This function clones the state of a SHA-256 context.
- *
- * \param dst The destination context. This must be initialized.
- * \param src The context to clone. This must be initialized.
- */
-void mbedtls_sha256_clone(mbedtls_sha256_context *dst,
- const mbedtls_sha256_context *src)
-{
- SHA256_VALIDATE(dst != NULL);
- SHA256_VALIDATE(src != NULL);
-
- *dst = *src;
-}
-
-/**
- * \brief This function starts a SHA-224 or SHA-256 checksum
- * calculation.
- * WARNING: SHA-224 is NOT supported by Cryptolite!
- *
- * \param ctx The context to use. This must be initialized.
- * \param is224 This determines which function to use. This must be
- * either \c 0 for SHA-256, or \c 1 for SHA-224.
- *
- * \return \c 0 on success.
- * \return A negative error code on failure.
- */
-int mbedtls_sha256_starts_ret(mbedtls_sha256_context *ctx, int is224)
-{
- SHA256_VALIDATE_RET(ctx != NULL);
- SHA256_VALIDATE_RET(0u == is224);
-
- (void)is224;
-
- return cryptolite_to_mbedtls(
- Cy_Cryptolite_Sha256_Start(CRYPTO, ctx));
-}
-
-/**
- * \brief This function feeds an input buffer into an ongoing
- * SHA-256 checksum calculation.
- *
- * \param ctx The SHA-256 context. This must be initialized
- * and have a hash operation started.
- * \param input The buffer holding the data. This must be a readable
- * buffer of length \p ilen Bytes.
- * \param ilen The length of the input data in Bytes.
- *
- * \return \c 0 on success.
- * \return A negative error code on failure.
- */
-int mbedtls_sha256_update_ret(mbedtls_sha256_context *ctx,
- const unsigned char *input,
- size_t ilen)
-{
- size_t offs = 0;
- SHA256_VALIDATE_RET(ctx != NULL);
- SHA256_VALIDATE_RET(0u == ilen || input != NULL);
-
-#ifdef CYW20829_SHA256_FLASH_WORKAROUND
- /* Apply workaround only for data from Flash */
- if ((uintptr_t)input >= XIP_NS_CBUS &&
- (uintptr_t)(input + ilen) <= XIP_NS_CBUS + XIP_SIZE) {
-
- while (ilen > CYW20829_SHA256_SAFE_CHUNK_SIZE) {
- cy_en_cryptolite_status_t status =
- Cy_Cryptolite_Sha256_Update(CRYPTO,
- (uint8_t const *)input + offs,
- CYW20829_SHA256_SAFE_CHUNK_SIZE,
- ctx);
-
- if (CY_CRYPTOLITE_SUCCESS != status) {
- return cryptolite_to_mbedtls(status);
- }
-
- offs += CYW20829_SHA256_SAFE_CHUNK_SIZE;
- ilen -= CYW20829_SHA256_SAFE_CHUNK_SIZE;
- }
- }
-#endif /* CYW20829_SHA256_FLASH_WORKAROUND */
-
- return cryptolite_to_mbedtls(
- Cy_Cryptolite_Sha256_Update(CRYPTO, (uint8_t const *)input + offs,
- (uint32_t)ilen, ctx));
-}
-
-/**
- * \brief This function finishes the SHA-256 operation, and writes
- * the result to the output buffer.
- *
- * \param ctx The SHA-256 context. This must be initialized
- * and have a hash operation started.
- * \param output The SHA-224 or SHA-256 checksum result.
- * This must be a writable buffer of length \c 32 Bytes.
- *
- * \return \c 0 on success.
- * \return A negative error code on failure.
- */
-int mbedtls_sha256_finish_ret(mbedtls_sha256_context *ctx,
- unsigned char output[32])
-{
- SHA256_VALIDATE_RET(ctx != NULL);
- SHA256_VALIDATE_RET((unsigned char *)output != NULL);
-
- return cryptolite_to_mbedtls(
- Cy_Cryptolite_Sha256_Finish(CRYPTO, (uint8_t *)output, ctx));
-}
-
-/**
- * \brief This function processes a single data block within
- * the ongoing SHA-256 computation. This function is for
- * internal use only.
- *
- * \param ctx The SHA-256 context. This must be initialized.
- * \param data The buffer holding one block of data. This must
- * be a readable buffer of length \c 64 Bytes.
- *
- * \return \c 0 on success.
- * \return A negative error code on failure.
- */
-int mbedtls_internal_sha256_process(mbedtls_sha256_context *ctx,
- const unsigned char data[64])
-{
- return mbedtls_sha256_update_ret(ctx,
- data,
- CY_CRYPTOLITE_SHA256_BLOCK_SIZE);
-}
-
-#endif /* MBEDTLS_SHA256_ALT */
-
-#endif /* MBEDTLS_SHA256_C */
diff --git a/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.h b/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.h
deleted file mode 100644
index f919246..0000000
--- a/boot/cypress/platforms/CYW20829/crypto/mbedtls_Cryptolite/sha256_alt.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * mbed Microcontroller Library
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * Copyright (c) 2021 Infineon Technologies AG
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if !defined(SHA256_ALT_H)
-#define SHA256_ALT_H
-
-#if defined(MBEDTLS_CONFIG_FILE)
-#include MBEDTLS_CONFIG_FILE
-#else
-#include "config.h"
-#endif
-
-#if defined(MBEDTLS_SHA256_ALT)
-
-#include "cy_cryptolite.h"
-
-typedef cy_stc_cryptolite_context_sha_t mbedtls_sha256_context;
-
-#endif /* MBEDTLS_SHA256_ALT */
-
-#endif /* (SHA256_ALT_H) */
diff --git a/boot/cypress/platforms/CYW20829/cyw20829_psvp.h b/boot/cypress/platforms/CYW20829/cyw20829_psvp.h
deleted file mode 100644
index 65868c0..0000000
--- a/boot/cypress/platforms/CYW20829/cyw20829_psvp.h
+++ /dev/null
@@ -1,916 +0,0 @@
-/***************************************************************************//**
-* \file cyw20829_psvp.h
-*
-* \brief
-* CYW20829_PSVP device header
-*
-********************************************************************************
-* \copyright
-* (c) (2016-2021), Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-*
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#ifndef _CYW20829_PSVP_H_
-#define _CYW20829_PSVP_H_
-
-/**
-* \addtogroup group_device CYW20829_PSVP
-* \{
-*/
-
-/**
-* \addtogroup Configuration_of_CMSIS
-* \{
-*/
-
-/*******************************************************************************
-* Interrupt Number Definition
-*******************************************************************************/
-
-typedef enum {
- /* ARM Cortex-M33 Core Interrupt Numbers */
- Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
- NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
- HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
- MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
- BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
- UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
- SecureFault_IRQn = -9, /*!< -9 Secure Fault Interrupt */
- SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
- DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
- PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
- SysTick_IRQn = -1, /*!< -1 System Tick Timer */
- /* CYW20829_PSVP Peripheral Interrupt Numbers */
- ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
- ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
- ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
- ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
- ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
- ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
- ioss_interrupt_vdd_IRQn = 6, /*!< 6 [DeepSleep] GPIO Supply Detect Interrupt */
- ioss_interrupt_gpio_IRQn = 7, /*!< 7 [DeepSleep] GPIO All Ports */
- scb_0_interrupt_IRQn = 8, /*!< 8 [DeepSleep] Serial Communication Block #0 (DeepSleep capable) */
- srss_interrupt_mcwdt_0_IRQn = 9, /*!< 9 [DeepSleep] Multi Counter Watchdog Timer interrupt */
- srss_interrupt_backup_IRQn = 10, /*!< 10 [DeepSleep] Backup domain interrupt */
- srss_interrupt_IRQn = 11, /*!< 11 [DeepSleep] Other combined Interrupts for srss (LVD and CLKCAL, CLKCAL only supported in Active mode) */
- cpuss_interrupts_ipc_dpslp_0_IRQn = 12, /*!< 12 [DeepSleep] cpuss Inter Process Communication Interrupt #0 */
- cpuss_interrupts_ipc_dpslp_1_IRQn = 13, /*!< 13 [DeepSleep] cpuss Inter Process Communication Interrupt #1 */
- keyscan_interrupt_IRQn = 14, /*!< 14 [DeepSleep] mxkeyscan interrupt for keyscan edge or fifo thresh to WIC in M33 */
- srss_interrupt_wdt_IRQn = 15, /*!< 15 [DeepSleep] Interrupt from WDT */
- btss_interrupt_btss_ipc_IRQn = 16, /*!< 16 [DeepSleep] interrupt from BTSS IPC */
- scb_1_interrupt_IRQn = 17, /*!< 17 [Active] Serial Communication Block #1 */
- scb_2_interrupt_IRQn = 18, /*!< 18 [Active] Serial Communication Block #2 */
- cpuss_interrupts_dw0_0_IRQn = 19, /*!< 19 [Active] cpuss DataWire #0, Channel #0 */
- cpuss_interrupts_dw0_1_IRQn = 20, /*!< 20 [Active] cpuss DataWire #0, Channel #1 */
- cpuss_interrupts_dw0_2_IRQn = 21, /*!< 21 [Active] cpuss DataWire #0, Channel #2 */
- cpuss_interrupts_dw0_3_IRQn = 22, /*!< 22 [Active] cpuss DataWire #0, Channel #3 */
- cpuss_interrupts_dw0_4_IRQn = 23, /*!< 23 [Active] cpuss DataWire #0, Channel #4 */
- cpuss_interrupts_dw0_5_IRQn = 24, /*!< 24 [Active] cpuss DataWire #0, Channel #5 */
- cpuss_interrupts_dw0_6_IRQn = 25, /*!< 25 [Active] cpuss DataWire #0, Channel #6 */
- cpuss_interrupts_dw0_7_IRQn = 26, /*!< 26 [Active] cpuss DataWire #0, Channel #7 */
- cpuss_interrupts_dw0_8_IRQn = 27, /*!< 27 [Active] cpuss DataWire #0, Channel #8 */
- cpuss_interrupts_dw0_9_IRQn = 28, /*!< 28 [Active] cpuss DataWire #0, Channel #9 */
- cpuss_interrupts_dw0_10_IRQn = 29, /*!< 29 [Active] cpuss DataWire #0, Channel #10 */
- cpuss_interrupts_dw0_11_IRQn = 30, /*!< 30 [Active] cpuss DataWire #0, Channel #11 */
- cpuss_interrupts_dw0_12_IRQn = 31, /*!< 31 [Active] cpuss DataWire #0, Channel #12 */
- cpuss_interrupts_dw0_13_IRQn = 32, /*!< 32 [Active] cpuss DataWire #0, Channel #13 */
- cpuss_interrupts_dw0_14_IRQn = 33, /*!< 33 [Active] cpuss DataWire #0, Channel #14 */
- cpuss_interrupts_dw0_15_IRQn = 34, /*!< 34 [Active] cpuss DataWire #0, Channel #15 */
- cpuss_interrupt_mpc_promc_IRQn = 35, /*!< 35 [Active] PROMC Int */
- cpuss_interrupt_ppu_sramc0_IRQn = 36, /*!< 36 [Active] PPU SRAM0 */
- cpuss_interrupt_mpc_sramc0_IRQn = 37, /*!< 37 [Active] MPC SRAM0 */
- cpuss_interrupt_cm33_0_fp_IRQn = 38, /*!< 38 [Active] CM33 0 Floating Point Interrupt */
- cpuss_interrupts_cm33_0_cti_0_IRQn = 39, /*!< 39 [Active] CM33-0 CTI interrupt outputs */
- cpuss_interrupts_cm33_0_cti_1_IRQn = 40, /*!< 40 [Active] CM33-1 CTI interrupt outputs */
- cpuss_interrupt_exp_br_ahb_error_IRQn = 41, /*!< 41 [Active] EXPANSION BRIDGE AHB Error interrupt */
- tcpwm_0_interrupts_0_IRQn = 42, /*!< 42 [Active] TCPWM #0, Counter #0 */
- tcpwm_0_interrupts_1_IRQn = 43, /*!< 43 [Active] TCPWM #0, Counter #1 */
- tcpwm_0_interrupts_256_IRQn = 44, /*!< 44 [Active] TCPWM #0, Counter #256 */
- tcpwm_0_interrupts_257_IRQn = 45, /*!< 45 [Active] TCPWM #0, Counter #257 */
- tcpwm_0_interrupts_258_IRQn = 46, /*!< 46 [Active] TCPWM #0, Counter #258 */
- tcpwm_0_interrupts_259_IRQn = 47, /*!< 47 [Active] TCPWM #0, Counter #259 */
- tcpwm_0_interrupts_260_IRQn = 48, /*!< 48 [Active] TCPWM #0, Counter #260 */
- tcpwm_0_interrupts_261_IRQn = 49, /*!< 49 [Active] TCPWM #0, Counter #261 */
- tcpwm_0_interrupts_262_IRQn = 50, /*!< 50 [Active] TCPWM #0, Counter #262 */
- smif_interrupt_normal_IRQn = 51, /*!< 51 [Active] Serial Memory Interface interrupt */
- smif_interrupt_mpc_IRQn = 52, /*!< 52 [Active] Serial Memory Interface interrupt */
- tdm_0_interrupts_rx_0_IRQn = 53, /*!< 53 [Active] TDM0 Audio interrupt RX */
- tdm_0_interrupts_tx_0_IRQn = 54, /*!< 54 [Active] TDM0 Audio interrupt TX */
- pdm_0_interrupts_0_IRQn = 55, /*!< 55 [Active] PDM0/PCM0 Audio interrupt */
- pdm_0_interrupts_1_IRQn = 56, /*!< 56 [Active] PDM0/PCM0 Audio interrupt */
- srss_interrupt_main_ppu_IRQn = 57, /*!< 57 [Active] SRSS Main PPU Interrupt */
- peri_interrupt_ppc_IRQn = 58, /*!< 58 [Active] PERI PPC Interrupt */
- peri_interrupt_ahb_error_IRQn = 59, /*!< 59 [Active] PERI AHB Interrupt */
- lin_0_interrupts_0_IRQn = 60, /*!< 60 [Active] LIN Interrupt, Channel #0 */
- lin_0_interrupts_1_IRQn = 61, /*!< 61 [Active] LIN Interrupt, Channel #1 */
- crypto_interrupt_error_IRQn = 62, /*!< 62 [Active] Crypto Interrupt */
- cpuss_interrupt_ppu_cpuss_IRQn = 63, /*!< 63 [Active] CPUSS PPU Interrupt */
- canfd_0_interrupts0_0_IRQn = 64, /*!< 64 [Active] CAN #0, Interrupt #0, Channel #0 */
- canfd_0_interrupts1_0_IRQn = 65, /*!< 65 [Active] CAN #0, Interrupt #1, Channel #0 */
- canfd_0_interrupt0_IRQn = 66, /*!< 66 [Active] Can #0, Consolidated interrupt #0 */
- adcmic_interrupt_adcmic_IRQn = 67, /*!< 67 [Active] ADCMIC interrupt */
- btss_interrupt_btss_exception_IRQn = 68, /*!< 68 [Active] interrupt indicating BTSS has encountered exception */
- unconnected_IRQn = 240 /*!< 240 Unconnected */
-} IRQn_Type;
-
-
-/*******************************************************************************
-* Processor and Core Peripheral Section
-*******************************************************************************/
-
-/* Configuration of the ARM Cortex-M33 Processor and Core Peripherals */
-#define __CM33_REV 0x0001U /*!< CM33 Core Revision */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __FPU_PRESENT 1 /*!< FPU present or not */
-#define __CM0P_PRESENT 0 /*!< CM0P present or not */
-#define __DTCM_PRESENT 0 /*!< DTCM present or not */
-#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */
-#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */
-
-/** \} Configuration_of_CMSIS */
-
-#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
-
-
-/* Memory Blocks */
-#define CY_ROM_BASE 0x00000000UL
-#define CY_ROM_SIZE 0x00010000UL
-#define CY_ROM_SECURE_OFFSET 0x10000000UL
-#define CY_ROM_REMAP_OFFSET 0x00000000UL
-#define CY_ROM_REMAP_SECURE_OFFSET 0x10000000UL
-#define CY_CAN0MRAM_BASE 0x40450000UL
-#define CY_CAN0MRAM_SIZE 0x00010000UL
-#define CY_EFUSE_BASE 0x40810800UL
-#define CY_EFUSE_SIZE 0x00000200UL
-#define CY_XIP_BASE 0x60000000UL
-#define CY_XIP_SIZE 0x08000000UL
-#define CY_XIP_SECURE_OFFSET 0x70000000UL
-#define CY_XIP_REMAP_OFFSET 0x08000000UL
-#define CY_XIP_REMAP_SECURE_OFFSET 0x18000000UL
-#define CY_SRAM0_BASE 0x20000000UL
-#define CY_SRAM0_SIZE 0x00020000UL
-#define CY_SRAM0_SECURE_OFFSET 0x30000000UL
-#define CY_SRAM0_REMAP_OFFSET 0x04000000UL
-#define CY_SRAM0_REMAP_SECURE_OFFSET 0x14000000UL
-
-#include "system_cat1b.h" /*!< Category 1B System */
-
-/* IP List */
-#define CY_IP_MXS40ADCMIC 1u
-#define CY_IP_MXS40ADCMIC_INSTANCES 1u
-#define CY_IP_MXS40ADCMIC_VERSION 1u
-#define CY_IP_MXS40BLE52SS 1u
-#define CY_IP_MXS40BLE52SS_INSTANCES 1u
-#define CY_IP_MXS40BLE52SS_VERSION 1u
-#define CY_IP_MXTTCANFD 1u
-#define CY_IP_MXTTCANFD_INSTANCES 1u
-#define CY_IP_MXTTCANFD_VERSION 1u
-#define CY_IP_M33SYSCPUSS 1u
-#define CY_IP_M33SYSCPUSS_INSTANCES 1u
-#define CY_IP_M33SYSCPUSS_VERSION 1u
-#define CY_IP_MXCRYPTOLITE 1u
-#define CY_IP_MXCRYPTOLITE_INSTANCES 1u
-#define CY_IP_MXCRYPTOLITE_VERSION 1u
-#define CY_IP_MXDFT 1u
-#define CY_IP_MXDFT_INSTANCES 1u
-#define CY_IP_MXDFT_VERSION 2u
-#define CY_IP_MXEFUSE 1u
-#define CY_IP_MXEFUSE_INSTANCES 1u
-#define CY_IP_MXEFUSE_VERSION 3u
-#define CY_IP_MXS40SIOSS 1u
-#define CY_IP_MXS40SIOSS_INSTANCES 1u
-#define CY_IP_MXS40SIOSS_VERSION 1u
-#define CY_IP_MXKEYSCAN 1u
-#define CY_IP_MXKEYSCAN_INSTANCES 1u
-#define CY_IP_MXKEYSCAN_VERSION 1u
-#define CY_IP_MXLIN 1u
-#define CY_IP_MXLIN_INSTANCES 1u
-#define CY_IP_MXLIN_VERSION 1u
-#define CY_IP_MXCM33 1u
-#define CY_IP_MXCM33_INSTANCES 1u
-#define CY_IP_MXCM33_VERSION 1u
-#define CY_IP_MXDW 1u
-#define CY_IP_MXDW_INSTANCES 1u
-#define CY_IP_MXDW_VERSION 1u
-#define CY_IP_MXIPC 1u
-#define CY_IP_MXIPC_INSTANCES 1u
-#define CY_IP_MXIPC_VERSION 1u
-#define CY_IP_MXPROMC 1u
-#define CY_IP_MXPROMC_INSTANCES 1u
-#define CY_IP_MXPROMC_VERSION 1u
-#define CY_IP_MXSRAMC 1u
-#define CY_IP_MXSRAMC_INSTANCES 1u
-#define CY_IP_MXSRAMC_VERSION 1u
-#define CY_IP_MXPDM 1u
-#define CY_IP_MXPDM_INSTANCES 1u
-#define CY_IP_MXPDM_VERSION 1u
-#define CY_IP_MXSPERI 1u
-#define CY_IP_MXSPERI_INSTANCES 1u
-#define CY_IP_MXSPERI_VERSION 1u
-#define CY_IP_MXSPERI_TR 1u
-#define CY_IP_MXSPERI_TR_INSTANCES 1u
-#define CY_IP_MXSPERI_TR_VERSION 1u
-#define CY_IP_MXSCB 1u
-#define CY_IP_MXSCB_INSTANCES 3u
-#define CY_IP_MXSCB_VERSION 4u
-#define CY_IP_MXSMIF 1u
-#define CY_IP_MXSMIF_INSTANCES 1u
-#define CY_IP_MXSMIF_VERSION 3u
-#define CY_IP_MXS40SSRSS 1u
-#define CY_IP_MXS40SSRSS_INSTANCES 1u
-#define CY_IP_MXS40SSRSS_VERSION 1u
-#define CY_IP_MXTCPWM 1u
-#define CY_IP_MXTCPWM_INSTANCES 1u
-#define CY_IP_MXTCPWM_VERSION 2u
-#define CY_IP_MXTDM 1u
-#define CY_IP_MXTDM_INSTANCES 1u
-#define CY_IP_MXTDM_VERSION 1u
-
-#include "cyw20829_config.h"
-#include "gpio_cyw20829_56_qfn.h"
-
-#define CY_DEVICE_CYW20829
-#define CY_SILICON_ID 0xFFFFFFFFUL
-#define CY_HF_CLK_MAX_FREQ 150000000UL
-
-
-/*******************************************************************************
-* PERI
-*******************************************************************************/
-
-#define PERI_BASE 0x40000000UL
-#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */
-#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */
-#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004040 */
-#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004080 */
-#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400040C0 */
-#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */
-#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */
-#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */
-#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */
-#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */
-#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */
-#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */
-#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */
-#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */
-#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */
-#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */
-#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */
-#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */
-#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */
-#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */
-
-/*******************************************************************************
-* PPC
-*******************************************************************************/
-
-#define PPC_BASE 0x40020000UL
-#define PPC ((PPC_Type*) PPC_BASE) /* 0x40020000 */
-#define PPC_R_ADDR0 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[0]) /* 0x40025000 */
-#define PPC_R_ADDR1 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[1]) /* 0x40025004 */
-#define PPC_R_ADDR2 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[2]) /* 0x40025008 */
-#define PPC_R_ADDR3 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[3]) /* 0x4002500C */
-#define PPC_R_ADDR4 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[4]) /* 0x40025010 */
-#define PPC_R_ADDR5 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[5]) /* 0x40025014 */
-#define PPC_R_ADDR6 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[6]) /* 0x40025018 */
-#define PPC_R_ADDR7 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[7]) /* 0x4002501C */
-#define PPC_R_ADDR8 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[8]) /* 0x40025020 */
-#define PPC_R_ADDR9 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[9]) /* 0x40025024 */
-#define PPC_R_ADDR10 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[10]) /* 0x40025028 */
-#define PPC_R_ADDR11 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[11]) /* 0x4002502C */
-#define PPC_R_ADDR12 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[12]) /* 0x40025030 */
-#define PPC_R_ADDR13 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[13]) /* 0x40025034 */
-#define PPC_R_ADDR14 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[14]) /* 0x40025038 */
-#define PPC_R_ADDR15 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[15]) /* 0x4002503C */
-#define PPC_R_ADDR16 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[16]) /* 0x40025040 */
-#define PPC_R_ADDR17 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[17]) /* 0x40025044 */
-#define PPC_R_ADDR18 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[18]) /* 0x40025048 */
-#define PPC_R_ADDR19 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[19]) /* 0x4002504C */
-#define PPC_R_ADDR20 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[20]) /* 0x40025050 */
-#define PPC_R_ADDR21 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[21]) /* 0x40025054 */
-#define PPC_R_ADDR22 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[22]) /* 0x40025058 */
-#define PPC_R_ADDR23 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[23]) /* 0x4002505C */
-#define PPC_R_ADDR24 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[24]) /* 0x40025060 */
-#define PPC_R_ADDR25 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[25]) /* 0x40025064 */
-#define PPC_R_ADDR26 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[26]) /* 0x40025068 */
-#define PPC_R_ADDR27 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[27]) /* 0x4002506C */
-#define PPC_R_ADDR28 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[28]) /* 0x40025070 */
-#define PPC_R_ADDR29 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[29]) /* 0x40025074 */
-#define PPC_R_ADDR30 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[30]) /* 0x40025078 */
-#define PPC_R_ADDR31 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[31]) /* 0x4002507C */
-#define PPC_R_ADDR32 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[32]) /* 0x40025080 */
-#define PPC_R_ADDR33 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[33]) /* 0x40025084 */
-#define PPC_R_ADDR34 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[34]) /* 0x40025088 */
-#define PPC_R_ADDR35 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[35]) /* 0x4002508C */
-#define PPC_R_ADDR36 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[36]) /* 0x40025090 */
-#define PPC_R_ADDR37 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[37]) /* 0x40025094 */
-#define PPC_R_ADDR38 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[38]) /* 0x40025098 */
-#define PPC_R_ADDR39 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[39]) /* 0x4002509C */
-#define PPC_R_ADDR40 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[40]) /* 0x400250A0 */
-#define PPC_R_ADDR41 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[41]) /* 0x400250A4 */
-#define PPC_R_ADDR42 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[42]) /* 0x400250A8 */
-#define PPC_R_ADDR43 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[43]) /* 0x400250AC */
-#define PPC_R_ADDR44 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[44]) /* 0x400250B0 */
-#define PPC_R_ADDR45 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[45]) /* 0x400250B4 */
-#define PPC_R_ADDR46 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[46]) /* 0x400250B8 */
-#define PPC_R_ADDR47 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[47]) /* 0x400250BC */
-#define PPC_R_ADDR48 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[48]) /* 0x400250C0 */
-#define PPC_R_ADDR49 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[49]) /* 0x400250C4 */
-#define PPC_R_ADDR50 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[50]) /* 0x400250C8 */
-#define PPC_R_ADDR51 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[51]) /* 0x400250CC */
-#define PPC_R_ADDR52 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[52]) /* 0x400250D0 */
-#define PPC_R_ADDR53 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[53]) /* 0x400250D4 */
-#define PPC_R_ADDR54 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[54]) /* 0x400250D8 */
-#define PPC_R_ADDR55 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[55]) /* 0x400250DC */
-#define PPC_R_ADDR56 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[56]) /* 0x400250E0 */
-#define PPC_R_ADDR57 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[57]) /* 0x400250E4 */
-#define PPC_R_ADDR58 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[58]) /* 0x400250E8 */
-#define PPC_R_ADDR59 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[59]) /* 0x400250EC */
-#define PPC_R_ADDR60 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[60]) /* 0x400250F0 */
-#define PPC_R_ADDR61 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[61]) /* 0x400250F4 */
-#define PPC_R_ADDR62 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[62]) /* 0x400250F8 */
-#define PPC_R_ADDR63 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[63]) /* 0x400250FC */
-#define PPC_R_ADDR64 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[64]) /* 0x40025100 */
-#define PPC_R_ADDR65 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[65]) /* 0x40025104 */
-#define PPC_R_ADDR66 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[66]) /* 0x40025108 */
-#define PPC_R_ADDR67 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[67]) /* 0x4002510C */
-#define PPC_R_ADDR68 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[68]) /* 0x40025110 */
-#define PPC_R_ADDR69 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[69]) /* 0x40025114 */
-#define PPC_R_ADDR70 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[70]) /* 0x40025118 */
-#define PPC_R_ADDR71 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[71]) /* 0x4002511C */
-#define PPC_R_ADDR72 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[72]) /* 0x40025120 */
-#define PPC_R_ADDR73 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[73]) /* 0x40025124 */
-#define PPC_R_ADDR74 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[74]) /* 0x40025128 */
-#define PPC_R_ADDR75 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[75]) /* 0x4002512C */
-#define PPC_R_ADDR76 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[76]) /* 0x40025130 */
-#define PPC_R_ADDR77 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[77]) /* 0x40025134 */
-#define PPC_R_ADDR78 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[78]) /* 0x40025138 */
-#define PPC_R_ADDR79 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[79]) /* 0x4002513C */
-#define PPC_R_ADDR80 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[80]) /* 0x40025140 */
-#define PPC_R_ADDR81 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[81]) /* 0x40025144 */
-#define PPC_R_ADDR82 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[82]) /* 0x40025148 */
-#define PPC_R_ADDR83 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[83]) /* 0x4002514C */
-#define PPC_R_ADDR84 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[84]) /* 0x40025150 */
-#define PPC_R_ADDR85 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[85]) /* 0x40025154 */
-#define PPC_R_ADDR86 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[86]) /* 0x40025158 */
-#define PPC_R_ADDR87 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[87]) /* 0x4002515C */
-#define PPC_R_ADDR88 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[88]) /* 0x40025160 */
-#define PPC_R_ADDR89 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[89]) /* 0x40025164 */
-#define PPC_R_ADDR90 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[90]) /* 0x40025168 */
-#define PPC_R_ADDR91 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[91]) /* 0x4002516C */
-#define PPC_R_ADDR92 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[92]) /* 0x40025170 */
-#define PPC_R_ADDR93 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[93]) /* 0x40025174 */
-#define PPC_R_ADDR94 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[94]) /* 0x40025178 */
-#define PPC_R_ADDR95 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[95]) /* 0x4002517C */
-#define PPC_R_ADDR96 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[96]) /* 0x40025180 */
-#define PPC_R_ADDR97 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[97]) /* 0x40025184 */
-#define PPC_R_ADDR98 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[98]) /* 0x40025188 */
-#define PPC_R_ADDR99 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[99]) /* 0x4002518C */
-#define PPC_R_ADDR100 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[100]) /* 0x40025190 */
-#define PPC_R_ADDR101 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[101]) /* 0x40025194 */
-#define PPC_R_ADDR102 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[102]) /* 0x40025198 */
-#define PPC_R_ADDR103 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[103]) /* 0x4002519C */
-#define PPC_R_ADDR104 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[104]) /* 0x400251A0 */
-#define PPC_R_ADDR105 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[105]) /* 0x400251A4 */
-#define PPC_R_ADDR106 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[106]) /* 0x400251A8 */
-#define PPC_R_ADDR107 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[107]) /* 0x400251AC */
-#define PPC_R_ADDR108 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[108]) /* 0x400251B0 */
-#define PPC_R_ADDR109 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[109]) /* 0x400251B4 */
-#define PPC_R_ADDR110 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[110]) /* 0x400251B8 */
-#define PPC_R_ADDR111 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[111]) /* 0x400251BC */
-#define PPC_R_ADDR112 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[112]) /* 0x400251C0 */
-#define PPC_R_ADDR113 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[113]) /* 0x400251C4 */
-#define PPC_R_ADDR114 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[114]) /* 0x400251C8 */
-#define PPC_R_ADDR115 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[115]) /* 0x400251CC */
-#define PPC_R_ADDR116 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[116]) /* 0x400251D0 */
-#define PPC_R_ADDR117 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[117]) /* 0x400251D4 */
-#define PPC_R_ADDR118 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[118]) /* 0x400251D8 */
-#define PPC_R_ADDR119 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[119]) /* 0x400251DC */
-#define PPC_R_ADDR120 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[120]) /* 0x400251E0 */
-#define PPC_R_ADDR121 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[121]) /* 0x400251E4 */
-#define PPC_R_ADDR122 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[122]) /* 0x400251E8 */
-#define PPC_R_ADDR123 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[123]) /* 0x400251EC */
-#define PPC_R_ADDR124 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[124]) /* 0x400251F0 */
-#define PPC_R_ADDR125 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[125]) /* 0x400251F4 */
-#define PPC_R_ADDR126 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[126]) /* 0x400251F8 */
-#define PPC_R_ADDR127 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[127]) /* 0x400251FC */
-#define PPC_R_ADDR128 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[128]) /* 0x40025200 */
-#define PPC_R_ADDR129 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[129]) /* 0x40025204 */
-#define PPC_R_ADDR130 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[130]) /* 0x40025208 */
-#define PPC_R_ADDR131 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[131]) /* 0x4002520C */
-#define PPC_R_ADDR132 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[132]) /* 0x40025210 */
-#define PPC_R_ADDR133 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[133]) /* 0x40025214 */
-#define PPC_R_ADDR134 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[134]) /* 0x40025218 */
-#define PPC_R_ADDR135 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[135]) /* 0x4002521C */
-#define PPC_R_ADDR136 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[136]) /* 0x40025220 */
-#define PPC_R_ADDR137 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[137]) /* 0x40025224 */
-#define PPC_R_ADDR138 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[138]) /* 0x40025228 */
-#define PPC_R_ADDR139 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[139]) /* 0x4002522C */
-#define PPC_R_ADDR140 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[140]) /* 0x40025230 */
-#define PPC_R_ADDR141 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[141]) /* 0x40025234 */
-#define PPC_R_ADDR142 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[142]) /* 0x40025238 */
-#define PPC_R_ADDR143 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[143]) /* 0x4002523C */
-#define PPC_R_ADDR144 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[144]) /* 0x40025240 */
-#define PPC_R_ADDR145 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[145]) /* 0x40025244 */
-#define PPC_R_ADDR146 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[146]) /* 0x40025248 */
-#define PPC_R_ADDR147 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[147]) /* 0x4002524C */
-#define PPC_R_ADDR148 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[148]) /* 0x40025250 */
-#define PPC_R_ADDR149 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[149]) /* 0x40025254 */
-#define PPC_R_ADDR150 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[150]) /* 0x40025258 */
-#define PPC_R_ADDR151 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[151]) /* 0x4002525C */
-#define PPC_R_ADDR152 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[152]) /* 0x40025260 */
-#define PPC_R_ADDR153 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[153]) /* 0x40025264 */
-#define PPC_R_ADDR154 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[154]) /* 0x40025268 */
-#define PPC_R_ADDR155 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[155]) /* 0x4002526C */
-#define PPC_R_ADDR156 ((PPC_R_ADDR_Type*) &PPC->R_ADDR[156]) /* 0x40025270 */
-#define PPC_R_ATT0 ((PPC_R_ATT_Type*) &PPC->R_ATT[0]) /* 0x40026000 */
-#define PPC_R_ATT1 ((PPC_R_ATT_Type*) &PPC->R_ATT[1]) /* 0x40026004 */
-#define PPC_R_ATT2 ((PPC_R_ATT_Type*) &PPC->R_ATT[2]) /* 0x40026008 */
-#define PPC_R_ATT3 ((PPC_R_ATT_Type*) &PPC->R_ATT[3]) /* 0x4002600C */
-#define PPC_R_ATT4 ((PPC_R_ATT_Type*) &PPC->R_ATT[4]) /* 0x40026010 */
-#define PPC_R_ATT5 ((PPC_R_ATT_Type*) &PPC->R_ATT[5]) /* 0x40026014 */
-#define PPC_R_ATT6 ((PPC_R_ATT_Type*) &PPC->R_ATT[6]) /* 0x40026018 */
-#define PPC_R_ATT7 ((PPC_R_ATT_Type*) &PPC->R_ATT[7]) /* 0x4002601C */
-#define PPC_R_ATT8 ((PPC_R_ATT_Type*) &PPC->R_ATT[8]) /* 0x40026020 */
-#define PPC_R_ATT9 ((PPC_R_ATT_Type*) &PPC->R_ATT[9]) /* 0x40026024 */
-#define PPC_R_ATT10 ((PPC_R_ATT_Type*) &PPC->R_ATT[10]) /* 0x40026028 */
-#define PPC_R_ATT11 ((PPC_R_ATT_Type*) &PPC->R_ATT[11]) /* 0x4002602C */
-#define PPC_R_ATT12 ((PPC_R_ATT_Type*) &PPC->R_ATT[12]) /* 0x40026030 */
-#define PPC_R_ATT13 ((PPC_R_ATT_Type*) &PPC->R_ATT[13]) /* 0x40026034 */
-#define PPC_R_ATT14 ((PPC_R_ATT_Type*) &PPC->R_ATT[14]) /* 0x40026038 */
-#define PPC_R_ATT15 ((PPC_R_ATT_Type*) &PPC->R_ATT[15]) /* 0x4002603C */
-#define PPC_R_ATT16 ((PPC_R_ATT_Type*) &PPC->R_ATT[16]) /* 0x40026040 */
-#define PPC_R_ATT17 ((PPC_R_ATT_Type*) &PPC->R_ATT[17]) /* 0x40026044 */
-#define PPC_R_ATT18 ((PPC_R_ATT_Type*) &PPC->R_ATT[18]) /* 0x40026048 */
-#define PPC_R_ATT19 ((PPC_R_ATT_Type*) &PPC->R_ATT[19]) /* 0x4002604C */
-#define PPC_R_ATT20 ((PPC_R_ATT_Type*) &PPC->R_ATT[20]) /* 0x40026050 */
-#define PPC_R_ATT21 ((PPC_R_ATT_Type*) &PPC->R_ATT[21]) /* 0x40026054 */
-#define PPC_R_ATT22 ((PPC_R_ATT_Type*) &PPC->R_ATT[22]) /* 0x40026058 */
-#define PPC_R_ATT23 ((PPC_R_ATT_Type*) &PPC->R_ATT[23]) /* 0x4002605C */
-#define PPC_R_ATT24 ((PPC_R_ATT_Type*) &PPC->R_ATT[24]) /* 0x40026060 */
-#define PPC_R_ATT25 ((PPC_R_ATT_Type*) &PPC->R_ATT[25]) /* 0x40026064 */
-#define PPC_R_ATT26 ((PPC_R_ATT_Type*) &PPC->R_ATT[26]) /* 0x40026068 */
-#define PPC_R_ATT27 ((PPC_R_ATT_Type*) &PPC->R_ATT[27]) /* 0x4002606C */
-#define PPC_R_ATT28 ((PPC_R_ATT_Type*) &PPC->R_ATT[28]) /* 0x40026070 */
-#define PPC_R_ATT29 ((PPC_R_ATT_Type*) &PPC->R_ATT[29]) /* 0x40026074 */
-#define PPC_R_ATT30 ((PPC_R_ATT_Type*) &PPC->R_ATT[30]) /* 0x40026078 */
-#define PPC_R_ATT31 ((PPC_R_ATT_Type*) &PPC->R_ATT[31]) /* 0x4002607C */
-#define PPC_R_ATT32 ((PPC_R_ATT_Type*) &PPC->R_ATT[32]) /* 0x40026080 */
-#define PPC_R_ATT33 ((PPC_R_ATT_Type*) &PPC->R_ATT[33]) /* 0x40026084 */
-#define PPC_R_ATT34 ((PPC_R_ATT_Type*) &PPC->R_ATT[34]) /* 0x40026088 */
-#define PPC_R_ATT35 ((PPC_R_ATT_Type*) &PPC->R_ATT[35]) /* 0x4002608C */
-#define PPC_R_ATT36 ((PPC_R_ATT_Type*) &PPC->R_ATT[36]) /* 0x40026090 */
-#define PPC_R_ATT37 ((PPC_R_ATT_Type*) &PPC->R_ATT[37]) /* 0x40026094 */
-#define PPC_R_ATT38 ((PPC_R_ATT_Type*) &PPC->R_ATT[38]) /* 0x40026098 */
-#define PPC_R_ATT39 ((PPC_R_ATT_Type*) &PPC->R_ATT[39]) /* 0x4002609C */
-#define PPC_R_ATT40 ((PPC_R_ATT_Type*) &PPC->R_ATT[40]) /* 0x400260A0 */
-#define PPC_R_ATT41 ((PPC_R_ATT_Type*) &PPC->R_ATT[41]) /* 0x400260A4 */
-#define PPC_R_ATT42 ((PPC_R_ATT_Type*) &PPC->R_ATT[42]) /* 0x400260A8 */
-#define PPC_R_ATT43 ((PPC_R_ATT_Type*) &PPC->R_ATT[43]) /* 0x400260AC */
-#define PPC_R_ATT44 ((PPC_R_ATT_Type*) &PPC->R_ATT[44]) /* 0x400260B0 */
-#define PPC_R_ATT45 ((PPC_R_ATT_Type*) &PPC->R_ATT[45]) /* 0x400260B4 */
-#define PPC_R_ATT46 ((PPC_R_ATT_Type*) &PPC->R_ATT[46]) /* 0x400260B8 */
-#define PPC_R_ATT47 ((PPC_R_ATT_Type*) &PPC->R_ATT[47]) /* 0x400260BC */
-#define PPC_R_ATT48 ((PPC_R_ATT_Type*) &PPC->R_ATT[48]) /* 0x400260C0 */
-#define PPC_R_ATT49 ((PPC_R_ATT_Type*) &PPC->R_ATT[49]) /* 0x400260C4 */
-#define PPC_R_ATT50 ((PPC_R_ATT_Type*) &PPC->R_ATT[50]) /* 0x400260C8 */
-#define PPC_R_ATT51 ((PPC_R_ATT_Type*) &PPC->R_ATT[51]) /* 0x400260CC */
-#define PPC_R_ATT52 ((PPC_R_ATT_Type*) &PPC->R_ATT[52]) /* 0x400260D0 */
-#define PPC_R_ATT53 ((PPC_R_ATT_Type*) &PPC->R_ATT[53]) /* 0x400260D4 */
-#define PPC_R_ATT54 ((PPC_R_ATT_Type*) &PPC->R_ATT[54]) /* 0x400260D8 */
-#define PPC_R_ATT55 ((PPC_R_ATT_Type*) &PPC->R_ATT[55]) /* 0x400260DC */
-#define PPC_R_ATT56 ((PPC_R_ATT_Type*) &PPC->R_ATT[56]) /* 0x400260E0 */
-#define PPC_R_ATT57 ((PPC_R_ATT_Type*) &PPC->R_ATT[57]) /* 0x400260E4 */
-#define PPC_R_ATT58 ((PPC_R_ATT_Type*) &PPC->R_ATT[58]) /* 0x400260E8 */
-#define PPC_R_ATT59 ((PPC_R_ATT_Type*) &PPC->R_ATT[59]) /* 0x400260EC */
-#define PPC_R_ATT60 ((PPC_R_ATT_Type*) &PPC->R_ATT[60]) /* 0x400260F0 */
-#define PPC_R_ATT61 ((PPC_R_ATT_Type*) &PPC->R_ATT[61]) /* 0x400260F4 */
-#define PPC_R_ATT62 ((PPC_R_ATT_Type*) &PPC->R_ATT[62]) /* 0x400260F8 */
-#define PPC_R_ATT63 ((PPC_R_ATT_Type*) &PPC->R_ATT[63]) /* 0x400260FC */
-#define PPC_R_ATT64 ((PPC_R_ATT_Type*) &PPC->R_ATT[64]) /* 0x40026100 */
-#define PPC_R_ATT65 ((PPC_R_ATT_Type*) &PPC->R_ATT[65]) /* 0x40026104 */
-#define PPC_R_ATT66 ((PPC_R_ATT_Type*) &PPC->R_ATT[66]) /* 0x40026108 */
-#define PPC_R_ATT67 ((PPC_R_ATT_Type*) &PPC->R_ATT[67]) /* 0x4002610C */
-#define PPC_R_ATT68 ((PPC_R_ATT_Type*) &PPC->R_ATT[68]) /* 0x40026110 */
-#define PPC_R_ATT69 ((PPC_R_ATT_Type*) &PPC->R_ATT[69]) /* 0x40026114 */
-#define PPC_R_ATT70 ((PPC_R_ATT_Type*) &PPC->R_ATT[70]) /* 0x40026118 */
-#define PPC_R_ATT71 ((PPC_R_ATT_Type*) &PPC->R_ATT[71]) /* 0x4002611C */
-#define PPC_R_ATT72 ((PPC_R_ATT_Type*) &PPC->R_ATT[72]) /* 0x40026120 */
-#define PPC_R_ATT73 ((PPC_R_ATT_Type*) &PPC->R_ATT[73]) /* 0x40026124 */
-#define PPC_R_ATT74 ((PPC_R_ATT_Type*) &PPC->R_ATT[74]) /* 0x40026128 */
-#define PPC_R_ATT75 ((PPC_R_ATT_Type*) &PPC->R_ATT[75]) /* 0x4002612C */
-#define PPC_R_ATT76 ((PPC_R_ATT_Type*) &PPC->R_ATT[76]) /* 0x40026130 */
-#define PPC_R_ATT77 ((PPC_R_ATT_Type*) &PPC->R_ATT[77]) /* 0x40026134 */
-#define PPC_R_ATT78 ((PPC_R_ATT_Type*) &PPC->R_ATT[78]) /* 0x40026138 */
-#define PPC_R_ATT79 ((PPC_R_ATT_Type*) &PPC->R_ATT[79]) /* 0x4002613C */
-#define PPC_R_ATT80 ((PPC_R_ATT_Type*) &PPC->R_ATT[80]) /* 0x40026140 */
-#define PPC_R_ATT81 ((PPC_R_ATT_Type*) &PPC->R_ATT[81]) /* 0x40026144 */
-#define PPC_R_ATT82 ((PPC_R_ATT_Type*) &PPC->R_ATT[82]) /* 0x40026148 */
-#define PPC_R_ATT83 ((PPC_R_ATT_Type*) &PPC->R_ATT[83]) /* 0x4002614C */
-#define PPC_R_ATT84 ((PPC_R_ATT_Type*) &PPC->R_ATT[84]) /* 0x40026150 */
-#define PPC_R_ATT85 ((PPC_R_ATT_Type*) &PPC->R_ATT[85]) /* 0x40026154 */
-#define PPC_R_ATT86 ((PPC_R_ATT_Type*) &PPC->R_ATT[86]) /* 0x40026158 */
-#define PPC_R_ATT87 ((PPC_R_ATT_Type*) &PPC->R_ATT[87]) /* 0x4002615C */
-#define PPC_R_ATT88 ((PPC_R_ATT_Type*) &PPC->R_ATT[88]) /* 0x40026160 */
-#define PPC_R_ATT89 ((PPC_R_ATT_Type*) &PPC->R_ATT[89]) /* 0x40026164 */
-#define PPC_R_ATT90 ((PPC_R_ATT_Type*) &PPC->R_ATT[90]) /* 0x40026168 */
-#define PPC_R_ATT91 ((PPC_R_ATT_Type*) &PPC->R_ATT[91]) /* 0x4002616C */
-#define PPC_R_ATT92 ((PPC_R_ATT_Type*) &PPC->R_ATT[92]) /* 0x40026170 */
-#define PPC_R_ATT93 ((PPC_R_ATT_Type*) &PPC->R_ATT[93]) /* 0x40026174 */
-#define PPC_R_ATT94 ((PPC_R_ATT_Type*) &PPC->R_ATT[94]) /* 0x40026178 */
-#define PPC_R_ATT95 ((PPC_R_ATT_Type*) &PPC->R_ATT[95]) /* 0x4002617C */
-#define PPC_R_ATT96 ((PPC_R_ATT_Type*) &PPC->R_ATT[96]) /* 0x40026180 */
-#define PPC_R_ATT97 ((PPC_R_ATT_Type*) &PPC->R_ATT[97]) /* 0x40026184 */
-#define PPC_R_ATT98 ((PPC_R_ATT_Type*) &PPC->R_ATT[98]) /* 0x40026188 */
-#define PPC_R_ATT99 ((PPC_R_ATT_Type*) &PPC->R_ATT[99]) /* 0x4002618C */
-#define PPC_R_ATT100 ((PPC_R_ATT_Type*) &PPC->R_ATT[100]) /* 0x40026190 */
-#define PPC_R_ATT101 ((PPC_R_ATT_Type*) &PPC->R_ATT[101]) /* 0x40026194 */
-#define PPC_R_ATT102 ((PPC_R_ATT_Type*) &PPC->R_ATT[102]) /* 0x40026198 */
-#define PPC_R_ATT103 ((PPC_R_ATT_Type*) &PPC->R_ATT[103]) /* 0x4002619C */
-#define PPC_R_ATT104 ((PPC_R_ATT_Type*) &PPC->R_ATT[104]) /* 0x400261A0 */
-#define PPC_R_ATT105 ((PPC_R_ATT_Type*) &PPC->R_ATT[105]) /* 0x400261A4 */
-#define PPC_R_ATT106 ((PPC_R_ATT_Type*) &PPC->R_ATT[106]) /* 0x400261A8 */
-#define PPC_R_ATT107 ((PPC_R_ATT_Type*) &PPC->R_ATT[107]) /* 0x400261AC */
-#define PPC_R_ATT108 ((PPC_R_ATT_Type*) &PPC->R_ATT[108]) /* 0x400261B0 */
-#define PPC_R_ATT109 ((PPC_R_ATT_Type*) &PPC->R_ATT[109]) /* 0x400261B4 */
-#define PPC_R_ATT110 ((PPC_R_ATT_Type*) &PPC->R_ATT[110]) /* 0x400261B8 */
-#define PPC_R_ATT111 ((PPC_R_ATT_Type*) &PPC->R_ATT[111]) /* 0x400261BC */
-#define PPC_R_ATT112 ((PPC_R_ATT_Type*) &PPC->R_ATT[112]) /* 0x400261C0 */
-#define PPC_R_ATT113 ((PPC_R_ATT_Type*) &PPC->R_ATT[113]) /* 0x400261C4 */
-#define PPC_R_ATT114 ((PPC_R_ATT_Type*) &PPC->R_ATT[114]) /* 0x400261C8 */
-#define PPC_R_ATT115 ((PPC_R_ATT_Type*) &PPC->R_ATT[115]) /* 0x400261CC */
-#define PPC_R_ATT116 ((PPC_R_ATT_Type*) &PPC->R_ATT[116]) /* 0x400261D0 */
-#define PPC_R_ATT117 ((PPC_R_ATT_Type*) &PPC->R_ATT[117]) /* 0x400261D4 */
-#define PPC_R_ATT118 ((PPC_R_ATT_Type*) &PPC->R_ATT[118]) /* 0x400261D8 */
-#define PPC_R_ATT119 ((PPC_R_ATT_Type*) &PPC->R_ATT[119]) /* 0x400261DC */
-#define PPC_R_ATT120 ((PPC_R_ATT_Type*) &PPC->R_ATT[120]) /* 0x400261E0 */
-#define PPC_R_ATT121 ((PPC_R_ATT_Type*) &PPC->R_ATT[121]) /* 0x400261E4 */
-#define PPC_R_ATT122 ((PPC_R_ATT_Type*) &PPC->R_ATT[122]) /* 0x400261E8 */
-#define PPC_R_ATT123 ((PPC_R_ATT_Type*) &PPC->R_ATT[123]) /* 0x400261EC */
-#define PPC_R_ATT124 ((PPC_R_ATT_Type*) &PPC->R_ATT[124]) /* 0x400261F0 */
-#define PPC_R_ATT125 ((PPC_R_ATT_Type*) &PPC->R_ATT[125]) /* 0x400261F4 */
-#define PPC_R_ATT126 ((PPC_R_ATT_Type*) &PPC->R_ATT[126]) /* 0x400261F8 */
-#define PPC_R_ATT127 ((PPC_R_ATT_Type*) &PPC->R_ATT[127]) /* 0x400261FC */
-#define PPC_R_ATT128 ((PPC_R_ATT_Type*) &PPC->R_ATT[128]) /* 0x40026200 */
-#define PPC_R_ATT129 ((PPC_R_ATT_Type*) &PPC->R_ATT[129]) /* 0x40026204 */
-#define PPC_R_ATT130 ((PPC_R_ATT_Type*) &PPC->R_ATT[130]) /* 0x40026208 */
-#define PPC_R_ATT131 ((PPC_R_ATT_Type*) &PPC->R_ATT[131]) /* 0x4002620C */
-#define PPC_R_ATT132 ((PPC_R_ATT_Type*) &PPC->R_ATT[132]) /* 0x40026210 */
-#define PPC_R_ATT133 ((PPC_R_ATT_Type*) &PPC->R_ATT[133]) /* 0x40026214 */
-#define PPC_R_ATT134 ((PPC_R_ATT_Type*) &PPC->R_ATT[134]) /* 0x40026218 */
-#define PPC_R_ATT135 ((PPC_R_ATT_Type*) &PPC->R_ATT[135]) /* 0x4002621C */
-#define PPC_R_ATT136 ((PPC_R_ATT_Type*) &PPC->R_ATT[136]) /* 0x40026220 */
-#define PPC_R_ATT137 ((PPC_R_ATT_Type*) &PPC->R_ATT[137]) /* 0x40026224 */
-#define PPC_R_ATT138 ((PPC_R_ATT_Type*) &PPC->R_ATT[138]) /* 0x40026228 */
-#define PPC_R_ATT139 ((PPC_R_ATT_Type*) &PPC->R_ATT[139]) /* 0x4002622C */
-#define PPC_R_ATT140 ((PPC_R_ATT_Type*) &PPC->R_ATT[140]) /* 0x40026230 */
-#define PPC_R_ATT141 ((PPC_R_ATT_Type*) &PPC->R_ATT[141]) /* 0x40026234 */
-#define PPC_R_ATT142 ((PPC_R_ATT_Type*) &PPC->R_ATT[142]) /* 0x40026238 */
-#define PPC_R_ATT143 ((PPC_R_ATT_Type*) &PPC->R_ATT[143]) /* 0x4002623C */
-#define PPC_R_ATT144 ((PPC_R_ATT_Type*) &PPC->R_ATT[144]) /* 0x40026240 */
-#define PPC_R_ATT145 ((PPC_R_ATT_Type*) &PPC->R_ATT[145]) /* 0x40026244 */
-#define PPC_R_ATT146 ((PPC_R_ATT_Type*) &PPC->R_ATT[146]) /* 0x40026248 */
-#define PPC_R_ATT147 ((PPC_R_ATT_Type*) &PPC->R_ATT[147]) /* 0x4002624C */
-#define PPC_R_ATT148 ((PPC_R_ATT_Type*) &PPC->R_ATT[148]) /* 0x40026250 */
-#define PPC_R_ATT149 ((PPC_R_ATT_Type*) &PPC->R_ATT[149]) /* 0x40026254 */
-#define PPC_R_ATT150 ((PPC_R_ATT_Type*) &PPC->R_ATT[150]) /* 0x40026258 */
-#define PPC_R_ATT151 ((PPC_R_ATT_Type*) &PPC->R_ATT[151]) /* 0x4002625C */
-#define PPC_R_ATT152 ((PPC_R_ATT_Type*) &PPC->R_ATT[152]) /* 0x40026260 */
-#define PPC_R_ATT153 ((PPC_R_ATT_Type*) &PPC->R_ATT[153]) /* 0x40026264 */
-#define PPC_R_ATT154 ((PPC_R_ATT_Type*) &PPC->R_ATT[154]) /* 0x40026268 */
-#define PPC_R_ATT155 ((PPC_R_ATT_Type*) &PPC->R_ATT[155]) /* 0x4002626C */
-#define PPC_R_ATT156 ((PPC_R_ATT_Type*) &PPC->R_ATT[156]) /* 0x40026270 */
-
-/*******************************************************************************
-* PERI_PCLK
-*******************************************************************************/
-
-#define PERI_PCLK_BASE 0x40040000UL
-#define PERI_PCLK ((PERI_PCLK_Type*) PERI_PCLK_BASE) /* 0x40040000 */
-#define PERI_PCLK_GR0 ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[0]) /* 0x40040000 */
-#define PERI_PCLK_GR1 ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[1]) /* 0x40042000 */
-#define PERI_PCLK_GR2 ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[2]) /* 0x40044000 */
-#define PERI_PCLK_GR3 ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[3]) /* 0x40046000 */
-#define PERI_PCLK_GR4 ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[4]) /* 0x40048000 */
-#define PERI_PCLK_GR5 ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[5]) /* 0x4004A000 */
-#define PERI_PCLK_GR6 ((PERI_PCLK_GR_Type*) &PERI_PCLK->GR[6]) /* 0x4004C000 */
-
-/*******************************************************************************
-* RAMC_PPU
-*******************************************************************************/
-
-#define RAMC_PPU0_BASE 0x40100000UL
-#define RAMC_PPU1_BASE 0x40101000UL
-#define RAMC_PPU2_BASE 0x40102000UL
-#define RAMC_PPU0 ((RAMC_PPU_Type*) RAMC_PPU0_BASE) /* 0x40100000 */
-#define RAMC_PPU1 ((RAMC_PPU_Type*) RAMC_PPU1_BASE) /* 0x40101000 */
-#define RAMC_PPU2 ((RAMC_PPU_Type*) RAMC_PPU2_BASE) /* 0x40102000 */
-
-/*******************************************************************************
-* ICACHE
-*******************************************************************************/
-
-#define ICACHE0_BASE 0x40103000UL
-#define ICACHE1_BASE 0x40104000UL
-#define ICACHE0 ((ICACHE_Type*) ICACHE0_BASE) /* 0x40103000 */
-#define ICACHE1 ((ICACHE_Type*) ICACHE1_BASE) /* 0x40104000 */
-
-/*******************************************************************************
-* CPUSS_PPU
-*******************************************************************************/
-
-#define CPUSS_PPU_BASE 0x40105000UL
-#define CPUSS_PPU ((CPUSS_PPU_Type*) CPUSS_PPU_BASE) /* 0x40105000 */
-
-/*******************************************************************************
-* RAMC
-*******************************************************************************/
-
-#define RAMC0_BASE 0x40110000UL
-#define RAMC0 ((RAMC_Type*) RAMC0_BASE) /* 0x40110000 */
-#define RAMC0_MPC0 ((RAMC_MPC_Type*) &RAMC0->MPC[0]) /* 0x40114000 */
-
-/*******************************************************************************
-* PROMC
-*******************************************************************************/
-
-#define PROMC_BASE 0x40140000UL
-#define PROMC ((PROMC_Type*) PROMC_BASE) /* 0x40140000 */
-#define PROMC_MPC0 ((PROMC_MPC_Type*) &PROMC->MPC[0]) /* 0x40141000 */
-
-/*******************************************************************************
-* MXCM33
-*******************************************************************************/
-
-#define MXCM33_BASE 0x40160000UL
-#define MXCM33 ((MXCM33_Type*) MXCM33_BASE) /* 0x40160000 */
-
-/*******************************************************************************
-* DW
-*******************************************************************************/
-
-#define DW0_BASE 0x40180000UL
-#define DW0 ((DW_Type*) DW0_BASE) /* 0x40180000 */
-#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40188000 */
-#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40188040 */
-#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40188080 */
-#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x401880C0 */
-#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40188100 */
-#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40188140 */
-#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40188180 */
-#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x401881C0 */
-#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40188200 */
-#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40188240 */
-#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40188280 */
-#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x401882C0 */
-#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40188300 */
-#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40188340 */
-#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40188380 */
-#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x401883C0 */
-
-/*******************************************************************************
-* CPUSS
-*******************************************************************************/
-
-#define CPUSS_BASE 0x401C0000UL
-#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x401C0000 */
-
-/*******************************************************************************
-* MS_CTL_1_2
-*******************************************************************************/
-
-#define MS_CTL_1_2_BASE 0x401C4000UL
-#define MS_CTL_1_2 ((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE) /* 0x401C4000 */
-#define MS5 ((MS_Type*) &MS_CTL_1_2->MS[5]) /* 0x401C4050 */
-#define MS_PC5 ((MS_PC_Type*) &MS_CTL_1_2->MS_PC[5]) /* 0x401C5050 */
-
-/*******************************************************************************
-* CPUSS_SL_CTL
-*******************************************************************************/
-
-#define CPUSS_SL_CTL_BASE 0x401C8000UL
-#define CPUSS_SL_CTL ((CPUSS_SL_CTL_Type*) CPUSS_SL_CTL_BASE) /* 0x401C8000 */
-
-/*******************************************************************************
-* IPC
-*******************************************************************************/
-
-#define IPC_BASE 0x401D0000UL
-#define IPC ((IPC_Type*) IPC_BASE) /* 0x401D0000 */
-#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x401D0000 */
-#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x401D0020 */
-#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x401D0040 */
-#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x401D0060 */
-#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x401D1000 */
-#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x401D1020 */
-
-/*******************************************************************************
-* SRSS
-*******************************************************************************/
-
-#define SRSS_BASE 0x40200000UL
-#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40200000 */
-#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x4020D000 */
-
-/*******************************************************************************
-* PWRMODE
-*******************************************************************************/
-
-#define PWRMODE_BASE 0x40210000UL
-#define PWRMODE ((PWRMODE_Type*) PWRMODE_BASE) /* 0x40210000 */
-#define PWRMODE_PD0 ((PWRMODE_PD_Type*) &PWRMODE->PD[0]) /* 0x40210000 */
-#define PWRMODE_PD1 ((PWRMODE_PD_Type*) &PWRMODE->PD[1]) /* 0x40210010 */
-#define PWRMODE_PD2 ((PWRMODE_PD_Type*) &PWRMODE->PD[2]) /* 0x40210020 */
-#define PWRMODE_PD3 ((PWRMODE_PD_Type*) &PWRMODE->PD[3]) /* 0x40210030 */
-#define PWRMODE_PD4 ((PWRMODE_PD_Type*) &PWRMODE->PD[4]) /* 0x40210040 */
-#define PWRMODE_PD5 ((PWRMODE_PD_Type*) &PWRMODE->PD[5]) /* 0x40210050 */
-#define PWRMODE_PD6 ((PWRMODE_PD_Type*) &PWRMODE->PD[6]) /* 0x40210060 */
-#define PWRMODE_PD7 ((PWRMODE_PD_Type*) &PWRMODE->PD[7]) /* 0x40210070 */
-#define PWRMODE_PD8 ((PWRMODE_PD_Type*) &PWRMODE->PD[8]) /* 0x40210080 */
-#define PWRMODE_PD9 ((PWRMODE_PD_Type*) &PWRMODE->PD[9]) /* 0x40210090 */
-#define PWRMODE_PD10 ((PWRMODE_PD_Type*) &PWRMODE->PD[10]) /* 0x402100A0 */
-#define PWRMODE_PD11 ((PWRMODE_PD_Type*) &PWRMODE->PD[11]) /* 0x402100B0 */
-#define PWRMODE_PD12 ((PWRMODE_PD_Type*) &PWRMODE->PD[12]) /* 0x402100C0 */
-#define PWRMODE_PD13 ((PWRMODE_PD_Type*) &PWRMODE->PD[13]) /* 0x402100D0 */
-#define PWRMODE_PD14 ((PWRMODE_PD_Type*) &PWRMODE->PD[14]) /* 0x402100E0 */
-#define PWRMODE_PD15 ((PWRMODE_PD_Type*) &PWRMODE->PD[15]) /* 0x402100F0 */
-#define PWRMODE_PPU_MAIN ((PWRMODE_PPU_MAIN_Type*) &PWRMODE->PPU_MAIN) /* 0x40211000 */
-#define PWRMODE_PPU_MAIN_PPU_MAIN ((PWRMODE_PPU_MAIN_PPU_MAIN_Type*) &PWRMODE->PPU_MAIN.PPU_MAIN) /* 0x40211000 */
-
-/*******************************************************************************
-* BACKUP
-*******************************************************************************/
-
-#define BACKUP_BASE 0x40220000UL
-#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40220000 */
-
-/*******************************************************************************
-* CRYPTO
-*******************************************************************************/
-
-#define CRYPTO_BASE 0x40230000UL
-#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40230000 */
-
-/*******************************************************************************
-* HSIOM
-*******************************************************************************/
-
-#define HSIOM_BASE 0x40400000UL
-#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40400000 */
-#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40400000 */
-#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40400010 */
-#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40400020 */
-#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40400030 */
-#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40400040 */
-#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40400050 */
-
-/*******************************************************************************
-* GPIO
-*******************************************************************************/
-
-#define GPIO_BASE 0x40410000UL
-#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40410000 */
-#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40410000 */
-#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40410080 */
-#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40410100 */
-#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40410180 */
-#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40410200 */
-#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40410280 */
-
-/*******************************************************************************
-* SMARTIO
-*******************************************************************************/
-
-#define SMARTIO_BASE 0x40420000UL
-#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40420000 */
-#define SMARTIO_PRT3 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[3]) /* 0x40420300 */
-
-/*******************************************************************************
-* LIN
-*******************************************************************************/
-
-#define LIN0_BASE 0x40430000UL
-#define LIN0 ((LIN_Type*) LIN0_BASE) /* 0x40430000 */
-#define LIN0_CH0 ((LIN_CH_Type*) &LIN0->CH[0]) /* 0x40438000 */
-#define LIN0_CH1 ((LIN_CH_Type*) &LIN0->CH[1]) /* 0x40438100 */
-
-/*******************************************************************************
-* CANFD
-*******************************************************************************/
-
-#define CANFD0_BASE 0x40440000UL
-#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40440000 */
-#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40440000 */
-#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40440000 */
-
-/*******************************************************************************
-* TCPWM
-*******************************************************************************/
-
-#define TCPWM0_BASE 0x404A0000UL
-#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x404A0000 */
-#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x404A0000 */
-#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x404A8000 */
-#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x404A0000 */
-#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x404A0080 */
-#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x404A8000 */
-#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x404A8080 */
-#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x404A8100 */
-#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x404A8180 */
-#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x404A8200 */
-#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x404A8280 */
-#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x404A8300 */
-
-/*******************************************************************************
-* MXS40ADCMIC
-*******************************************************************************/
-
-#define MXS40ADCMIC0_BASE 0x40520000UL
-#define MXS40ADCMIC0 ((MXS40ADCMIC_Type*) MXS40ADCMIC0_BASE) /* 0x40520000 */
-
-/*******************************************************************************
-* SCB
-*******************************************************************************/
-
-#define SCB0_BASE 0x40590000UL
-#define SCB1_BASE 0x405A0000UL
-#define SCB2_BASE 0x405B0000UL
-#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40590000 */
-#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x405A0000 */
-#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x405B0000 */
-
-/*******************************************************************************
-* EFUSE
-*******************************************************************************/
-
-#define EFUSE_BASE 0x40810000UL
-#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x40810000 */
-
-/*******************************************************************************
-* SMIF
-*******************************************************************************/
-
-#define SMIF0_BASE 0x40890000UL
-#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40890000 */
-#define SMIF0_SMIF_CRYPTO0 ((SMIF_SMIF_CRYPTO_Type*) &SMIF0->SMIF_CRYPTO_BLOCK[0]) /* 0x40890200 */
-#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40890800 */
-#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40890880 */
-#define SMIF0_MPC0 ((SMIF_MPC_Type*) &SMIF0->MPC[0]) /* 0x40891000 */
-
-/*******************************************************************************
-* TDM
-*******************************************************************************/
-
-#define TDM0_BASE 0x408C0000UL
-#define TDM0 ((TDM_Type*) TDM0_BASE) /* 0x408C0000 */
-#define TDM0_TDM_STRUCT0 ((TDM_TDM_STRUCT_Type*) &TDM0->TDM_STRUCT[0]) /* 0x408C8000 */
-#define TDM0_TDM_STRUCT0_TDM_TX_STRUCT ((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type*) &TDM0->TDM_STRUCT[0].TDM_TX_STRUCT) /* 0x408C8000 */
-#define TDM0_TDM_STRUCT0_TDM_RX_STRUCT ((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type*) &TDM0->TDM_STRUCT[0].TDM_RX_STRUCT) /* 0x408C8100 */
-
-/*******************************************************************************
-* PDM
-*******************************************************************************/
-
-#define PDM0_BASE 0x408D0000UL
-#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x408D0000 */
-#define PDM0_CH0 ((PDM_CH_Type*) &PDM0->CH[0]) /* 0x408D8000 */
-#define PDM0_CH1 ((PDM_CH_Type*) &PDM0->CH[1]) /* 0x408D8100 */
-
-/*******************************************************************************
-* MXKEYSCAN
-*******************************************************************************/
-
-#define MXKEYSCAN_BASE 0x40920000UL
-#define MXKEYSCAN ((MXKEYSCAN_Type*) MXKEYSCAN_BASE) /* 0x40920000 */
-
-/*******************************************************************************
-* BTSS
-*******************************************************************************/
-
-#define BTSS_BASE 0x42000000UL
-#define BTSS ((BTSS_Type*) BTSS_BASE) /* 0x42000000 */
-#define BTSS_DATA_RAM_IPC ((BTSS_DATA_RAM_IPC_Type*) &BTSS->DATA_RAM_IPC) /* 0x42600000 */
-
-/** \} CYW20829_PSVP */
-
-#endif /* _CYW20829_PSVP_H_ */
-
-
-/* [] END OF FILE */
diff --git a/boot/cypress/platforms/PSOC6/PSOC6.md b/boot/cypress/platforms/PSOC6.md
similarity index 94%
rename from boot/cypress/platforms/PSOC6/PSOC6.md
rename to boot/cypress/platforms/PSOC6.md
index 8cbe47f..22798c7 100644
--- a/boot/cypress/platforms/PSOC6/PSOC6.md
+++ b/boot/cypress/platforms/PSOC6.md
@@ -4,7 +4,7 @@
### Default memory map
-This repository provides a set of predefined memory maps in JSON files. They are located in `cy_flash_pal/flash_psoc6/flashmap`. One can use the predefined flash map or define its own using the predefined file as a template.
+This repository provides a set of predefined memory maps in JSON files. They are located in `platforms/cy_flash_pal/flash_psoc6/flashmap`. One can use the predefined flash map or define its own using the predefined file as a template.
### JSON flash map
As absolute addresses are used in JSON flash maps, the placement of flash area in internal or external memory is derived from its address. For instance:
@@ -75,7 +75,7 @@
An example of the command:
- make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json ENC_IMG=1
+ make app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json ENC_IMG=1
NOTE: Debug configuration of MCUBootApp with Multi-image encrypted upgrades in external flash (built with flags `BUILDCFG=Debug` `MCUBOOT_IMG_NUMBER=2 USE_EXTERNAL_FLASH=1 ENC_IMG=1`) is set to use optimization level `-O2 -g3` to fit into `0x18000` allocated for `MCUBootApp`.
diff --git a/boot/cypress/platforms/PSOC6.mk b/boot/cypress/platforms/PSOC6.mk
new file mode 100644
index 0000000..991ec3f
--- /dev/null
+++ b/boot/cypress/platforms/PSOC6.mk
@@ -0,0 +1,357 @@
+################################################################################
+# \file PSOC6.mk
+# \version 1.0
+#
+# \brief
+# Makefile to describe supported boards and platforms for Cypress MCUBoot based applications.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2019 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+include host.mk
+
+# PDL category suffix to resolve common path in pdl
+PDL_CAT_SUFFIX := 1A
+CRYPTO_ACC_TYPE := MXCRYPTO
+
+# MCU device selection, based on target device.
+# Default chips are used for supported platforms
+# This can be redefined in case of other chip usage
+ifeq ($(PLATFORM), PSOC_062_2M)
+# base kit CY8CPROTO-062-4343W
+DEVICE ?= CY8C624ABZI_S2D44
+PLATFORM_SUFFIX := 02
+else ifeq ($(PLATFORM), PSOC_062_1M)
+# base kit CY8CKIT-062-WIFI-BT
+DEVICE ?= CY8C6247BZI-D54
+PLATFORM_SUFFIX := 01
+else ifeq ($(PLATFORM), PSOC_062_512K)
+# base kit CY8CPROTO-062S3-4343W
+DEVICE ?= CY8C6245LQI-S3D72
+PLATFORM_SUFFIX := 03
+else ifeq ($(PLATFORM), PSOC_063_1M)
+# base kit CY8CPROTO-063-BLE
+DEVICE ?= CYBLE-416045-02-device
+PLATFORM_SUFFIX := 01
+else ifeq ($(PLATFORM), PSOC_061_2M)
+# FIXME!
+DEVICE ?= CY8C614ABZI-S2F44
+PLATFORM_SUFFIX := 02
+else ifeq ($(PLATFORM), PSOC_061_512K)
+DEVICE ?= CY8C6136BZI-F34
+PLATFORM_SUFFIX := 03
+USE_CRYPTO_HW := 0
+endif
+
+# Led default config
+ifeq ($(PLATFORM), PSOC_062_512K)
+LED_PORT_DEFAULT ?= GPIO_PRT11
+LED_PIN_DEFAULT ?= 1U
+else ifeq ($(PLATFORM), PSOC_062_1M)
+LED_PORT_DEFAULT ?= GPIO_PRT13
+LED_PIN_DEFAULT ?= 7U
+else ifeq ($(PLATFORM), PSOC_062_2M)
+LED_PORT_DEFAULT ?= GPIO_PRT13
+LED_PIN_DEFAULT ?= 7U
+else ifeq ($(PLATFORM), PSOC_063_1M)
+LED_PORT_DEFAULT ?= GPIO_PRT6
+LED_PIN_DEFAULT ?= 3U
+else ifeq ($(PLATFORM), PSOC_061_2M)
+LED_PORT_DEFAULT ?= GPIO_PRT13
+LED_PIN_DEFAULT ?= 7U
+else ifeq ($(PLATFORM), PSOC_061_512K)
+LED_PORT_DEFAULT ?= GPIO_PRT13
+LED_PIN_DEFAULT ?= 7U
+endif
+
+#UART default config
+ifeq ($(PLATFORM), PSOC_062_512K)
+UART_TX_DEFAULT ?= P10_1
+UART_RX_DEFAULT ?= P10_0
+else ifeq ($(PLATFORM), PSOC_061_512K)
+# INFO: Since 061 platform development
+# is happening on processor module (PM),
+# not dedicated kit, use port 10 for UART,
+# since it is present on PM headers
+# USE_CUSTOM_DEBUG_UART would use
+# custom_debug_uart_cfg.h config in MCUBootApp
+USE_CUSTOM_DEBUG_UART := 1
+# Definitions for BlinkyApp
+UART_TX_DEFAULT ?= P10_1
+UART_RX_DEFAULT ?= P10_0
+else
+UART_TX_DEFAULT ?= P5_1
+UART_RX_DEFAULT ?= P5_0
+endif
+
+# Add device name to defines
+DEFINES += $(DEVICE)
+
+# Default upgrade method
+PLATFORM_DEFAULT_USE_OVERWRITE ?= 0
+
+###############################################################################
+# Application specific libraries
+###############################################################################
+# MCUBootApp
+###############################################################################
+THIS_APP_PATH = $(PRJ_DIR)/libs
+
+ifeq ($(APP_NAME), MCUBootApp)
+
+CORE ?= CM0P
+ifeq ($(CORE), CM0P)
+CORE_SUFFIX = m0plus
+else
+CORE_SUFFIX = m4
+endif
+
+# Add retartget IO implementation using pdl
+PLATFORM_SOURCES_RETARGET_IO_PDL := $(wildcard $(THIS_APP_PATH)/retarget_io_pdl/*.c)
+
+# Collect dirrectories containing headers for PLATFORM
+PLATFORM_INCLUDE_RETARGET_IO_PDL := $(THIS_APP_PATH)/retarget_io_pdl
+
+# PSOC6HAL source files
+PLATFORM_SOURCES_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_crypto_common.c
+PLATFORM_SOURCES_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_hwmgr.c
+
+# needed for Crypto HW Acceleration and headers inclusion, do not use for peripherals
+# peripherals should be accessed
+PLATFORM_INCLUDE_DIRS_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include
+PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include
+PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include_pvt
+PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages
+
+###############################################################################
+# Application dependent definitions
+# MCUBootApp default settings
+
+USE_CRYPTO_HW ?= 1
+###############################################################################
+
+PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/platforms/cy_flash_pal
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/include
+PLATFORM_SOURCES_FLASH := $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/*.c)
+
+ifneq ($(USE_EXTERNAL_FLASH), 1)
+PLATFORM_SOURCES_FLASH := $(filter-out $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c, $(PLATFORM_SOURCES_FLASH))
+endif
+
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/flash_qspi
+PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/flash_qspi/*.c)
+ifeq ($(BUILDCFG), Debug)
+# Include files with statically defined SMIF configuration to enable
+# OpenOCD debugging of external memory
+PLATFORM_SOURCES_FLASH += cy_serial_flash_prog.c
+PLATFORM_SOURCES_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg
+endif
+endif
+
+# Platform dependend utils files
+PLATFORM_APP_SOURCES := $(PRJ_DIR)/platforms/utils/$(FAMILY)/cyw_platform_utils.c
+ifeq ($(PLATFORM), $(filter $(PLATFORM), PSOC_061_2M PSOC_061_1M PSOC_061_512K))
+# FIXME: not needed for real PSoC 61!
+PLATFORM_APP_SOURCES += $(PRJ_DIR)/platforms/utils/$(FAMILY)/psoc6_02_cm0p_sleep.c
+endif
+PLATFORM_INCLUDE_DIRS_UTILS := $(PRJ_DIR)/platforms/utils/$(FAMILY)
+
+# Post build job to execute for platform
+post_build: $(OUT_CFG)/$(APP_NAME)_unsigned.hex
+ifeq ($(POST_BUILD_ENABLE), 1)
+ $(info [POST BUILD] - Executing post build script for $(APP_NAME))
+ $(shell cp -f $(OUT_CFG)/$(APP_NAME)_unsigned.hex $(OUT_CFG)/$(APP_NAME).hex)
+ $(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME).hex > $(OUT_CFG)/$(APP_NAME).objdump
+else
+ $(info Post build is disabled by POST_BUILD_ENABLE parameter)
+endif # POST_BUILD_ENABLE
+endif ## MCUBootApp
+
+###############################################################################
+# BlinkyApp
+###############################################################################
+ifeq ($(APP_NAME), BlinkyApp)
+
+CORE := $(APP_CORE)
+ifeq ($(CORE), CM0P)
+CORE_SUFFIX = m0plus
+else
+CORE_SUFFIX = m4
+endif
+
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+PLATFORM_DEFAULT_ERASED_VALUE := 0xff
+else
+PLATFORM_DEFAULT_ERASED_VALUE := 0
+endif
+
+# Define start of application, RAM start and size, slot size
+ifeq ($(PLATFORM), $(filter $(PLATFORM), PSOC_061_2M PSOC_062_2M))
+ifeq ($(USE_XIP), 1)
+ PLATFORM_DEFAULT_RAM_START ?= 0x08020000
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0xE0000
+else
+ PLATFORM_DEFAULT_RAM_START ?= 0x08040000
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
+endif
+else ifeq ($(PLATFORM), $(filter $(PLATFORM), PSOC_061_1M PSOC_062_1M))
+ifeq ($(USE_XIP), 1)
+ PLATFORM_DEFAULT_RAM_START ?= 0x08000800
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x47800
+else
+ PLATFORM_DEFAULT_RAM_START ?= 0x08020000
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
+endif
+else ifeq ($(PLATFORM), $(filter $(PLATFORM), PSOC_061_512K PSOC_062_512K))
+ifeq ($(USE_XIP), 1)
+ PLATFORM_DEFAULT_RAM_START ?= 0x08000800
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x3F800
+else
+ PLATFORM_DEFAULT_RAM_START ?= 0x08020000
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
+endif
+else ifeq ($(PLATFORM), PSOC_063_1M)
+ PLATFORM_DEFAULT_RAM_START ?= 0x08020000
+ PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
+endif
+# Default start address of application (boot)
+PLATFORM_USER_APP_START ?= $(PRIMARY_IMG_START)
+# For PSOC6 platform PRIMARY_IMG_START start is the same as USER_APP_START
+# This parameter can be different in cases when code is resided in
+# flash mapped to one address range, but executed using different bus
+# for access with another address range. For example, execution of code
+# from external memory in XIP mode.
+PLATFORM_DEFAULT_PRIMARY_IMG_START ?= $(PLATFORM_DEFAULT_USER_APP_START)
+
+PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/platforms/cy_flash_pal
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/include
+
+ifeq ($(USE_EXTERNAL_FLASH), 1)
+PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/flash_qspi
+PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/platforms/cy_flash_pal/flash_psoc6/flash_qspi/*.c)
+endif
+
+# We still need this for MCUBoot apps signing
+IMGTOOL_PATH ?= ../../scripts/imgtool.py
+
+PLATFORM_DEFAULT_IMG_VER_ARG ?= 1.0.0
+
+PLATFORM_SIGN_ARGS := sign --header-size 1024 --pad-header --align 8 -M 512
+
+# Set parameters needed for signing
+ifeq ($(IMG_TYPE), UPGRADE)
+ # Use encryption and random initial vector for image
+ ifeq ($(ENC_IMG), 1)
+ PLATFORM_SIGN_ARGS += --encrypt ../../$(ENC_KEY_FILE).pem
+ PLATFORM_SIGN_ARGS += --use-random-iv
+ endif
+endif
+
+# Post build action to execute after main build job
+post_build: $(OUT_CFG)/$(APP_NAME).bin
+ifeq ($(POST_BUILD_ENABLE), 1)
+ $(info [POST BUILD] - Executing post build script for $(APP_NAME))
+ $(shell mv -f $(OUT_CFG)/$(APP_NAME).bin $(OUT_CFG)/$(APP_NAME)_unsigned.bin)
+ $(PYTHON_PATH) $(IMGTOOL_PATH) $(SIGN_ARGS) $(BOOT_RECORD) -S $(SLOT_SIZE) -R $(ERASED_VALUE) $(UPGRADE_TYPE) -k keys/$(SIGN_KEY_FILE).pem $(OUT_CFG)/$(APP_NAME)_unsigned.bin $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex --hex-addr=$(HEADER_OFFSET)
+ $(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex > $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).objdump
+else
+ $(info Post build is disabled by POST_BUILD_ENABLE parameter)
+endif # POST_BUILD_ENABLE
+endif ## BlinkyApp
+
+
+###############################################################################
+# Toolchain
+###############################################################################
+# Define build flags specific to a certain platform
+CFLAGS_PLATFORM := -mcpu=cortex-$(CORE_SUFFIX) -mfloat-abi=soft -fno-stack-protector -fstrict-aliasing
+
+###############################################################################
+# Common libraries
+###############################################################################
+PLATFORM_SYSTEM_FILE_NAME := system_psoc6_c$(CORE_SUFFIX).c
+PLATFORM_STARTUP_FILE := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/startup_psoc6_$(PLATFORM_SUFFIX)_c$(CORE_SUFFIX).S
+
+PLATFORM_INCLUDE_DIRS_PDL_STARTUP := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system
+
+###############################################################################
+# Print debug information about all settings used and/or set in this file
+ifeq ($(VERBOSE), 1)
+$(info #### PSOC6.mk ####)
+$(info APP_CORE <-- $(APP_CORE))
+$(info APP_NAME <-- $(APP_NAME))
+$(info BOOT_RECORD <-- $(BOOT_RECORD))
+$(info BUILDCFG <-- $(BUILDCFG))
+$(info CFLAGS_PLATFORM --> $(CFLAGS_PLATFORM))
+$(info COMPILER <-- $(COMPILER))
+$(info CORE <-> $(CORE))
+$(info CORE_SUFFIX <-- $(CORE_SUFFIX))
+$(info DEFINES --> $(DEFINES))
+$(info DEVICE <-> $(DEVICE))
+$(info ENC_IMG <-- $(ENC_IMG))
+$(info ENC_KEY_FILE <-- $(ENC_KEY_FILE))
+$(info ERASED_VALUE <-- $(ERASED_VALUE))
+$(info FAMILY <-- $(FAMILY))
+$(info GCC_PATH <-- $(GCC_PATH))
+$(info HEADER_OFFSET <-- $(HEADER_OFFSET))
+$(info IMGTOOL_PATH <-> $(IMGTOOL_PATH))
+$(info IMG_TYPE <-- $(IMG_TYPE))
+$(info LED_PIN_DEFAULT --> $(LED_PIN_DEFAULT))
+$(info LED_PORT_DEFAULT --> $(LED_PORT_DEFAULT))
+$(info OUT_CFG <-- $(OUT_CFG))
+$(info PDL_CAT_SUFFIX <-> $(PDL_CAT_SUFFIX))
+$(info PLATFORM <-- $(PLATFORM))
+$(info PLATFORM_APP_SOURCES --> $(PLATFORM_APP_SOURCES))
+$(info PLATFORM_DEFAULT_ERASED_VALUE --> $(PLATFORM_DEFAULT_ERASED_VALUE))
+$(info PLATFORM_DEFAULT_IMG_VER_ARG --> $(PLATFORM_DEFAULT_IMG_VER_ARG))
+$(info PLATFORM_DEFAULT_PRIMARY_IMG_START --> $(PLATFORM_DEFAULT_PRIMARY_IMG_START))
+$(info PLATFORM_DEFAULT_RAM_SIZE --> $(PLATFORM_DEFAULT_RAM_SIZE))
+$(info PLATFORM_DEFAULT_RAM_START --> $(PLATFORM_DEFAULT_RAM_START))
+$(info PLATFORM_DEFAULT_USER_APP_START <-- $(PLATFORM_DEFAULT_USER_APP_START))
+$(info PLATFORM_DEFAULT_USE_OVERWRITE --> $(PLATFORM_DEFAULT_USE_OVERWRITE))
+$(info PLATFORM_INCLUDE_DIRS_FLASH --> $(PLATFORM_INCLUDE_DIRS_FLASH))
+$(info PLATFORM_INCLUDE_DIRS_HAL_MCUB --> $(PLATFORM_INCLUDE_DIRS_HAL_MCUB))
+$(info PLATFORM_INCLUDE_DIRS_PDL_STARTUP --> $(PLATFORM_INCLUDE_DIRS_PDL_STARTUP))
+$(info PLATFORM_INCLUDE_DIRS_UTILS --> $(PLATFORM_INCLUDE_DIRS_UTILS))
+$(info PLATFORM_INCLUDE_RETARGET_IO_PDL --> $(PLATFORM_INCLUDE_RETARGET_IO_PDL))
+$(info PLATFORM_SIGN_ARGS --> $(PLATFORM_SIGN_ARGS))
+$(info PLATFORM_SOURCES_FLASH <-> $(PLATFORM_SOURCES_FLASH))
+$(info PLATFORM_SOURCES_HAL_MCUB --> $(PLATFORM_SOURCES_HAL_MCUB))
+$(info PLATFORM_SOURCES_RETARGET_IO_PDL --> $(PLATFORM_SOURCES_RETARGET_IO_PDL))
+$(info PLATFORM_STARTUP_FILE --> $(PLATFORM_STARTUP_FILE))
+$(info PLATFORM_SUFFIX <-> $(PLATFORM_SUFFIX))
+$(info PLATFORM_SYSTEM_FILE_NAME --> $(PLATFORM_SYSTEM_FILE_NAME))
+$(info PLATFORM_USER_APP_START --> $(PLATFORM_USER_APP_START))
+$(info POST_BUILD_ENABLE <-- $(POST_BUILD_ENABLE))
+$(info PRIMARY_IMG_START <-- $(PRIMARY_IMG_START))
+$(info PRJ_DIR <-- $(PRJ_DIR))
+$(info PYTHON_PATH <-- $(PYTHON_PATH))
+$(info SIGN_ARGS <-- $(SIGN_ARGS))
+$(info SIGN_KEY_FILE <-- $(SIGN_KEY_FILE))
+$(info SLOT_SIZE <-- $(SLOT_SIZE))
+$(info THIS_APP_PATH <-- $(THIS_APP_PATH))
+$(info UART_RX_DEFAULT --> $(UART_RX_DEFAULT))
+$(info UART_TX_DEFAULT --> $(UART_TX_DEFAULT))
+$(info UPGRADE_SUFFIX <-- $(UPGRADE_SUFFIX))
+$(info UPGRADE_TYPE <-- $(UPGRADE_TYPE))
+$(info USE_CRYPTO_HW --> $(USE_CRYPTO_HW))
+$(info USE_EXTERNAL_FLASH <-- $(USE_EXTERNAL_FLASH))
+$(info USE_XIP <-- $(USE_XIP))
+endif
diff --git a/boot/cypress/platforms/PSOC6/PSOC6.mk b/boot/cypress/platforms/PSOC6/PSOC6.mk
deleted file mode 100644
index b4b0c20..0000000
--- a/boot/cypress/platforms/PSOC6/PSOC6.mk
+++ /dev/null
@@ -1,300 +0,0 @@
-################################################################################
-# \file PSOC6.mk
-# \version 1.0
-#
-# \brief
-# Makefile to describe supported boards and platforms for Cypress MCUBoot based applications.
-#
-################################################################################
-# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
-# SPDX-License-Identifier: Apache-2.0
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-################################################################################
-
-include host.mk
-
-# PDL category suffix to resolve common path in pdl
-PDL_CAT_SUFFIX := 1A
-
-# MCU device selection, based on target device.
-# Default chips are used for supported platforms
-# This can be redefined in case of other chip usage
-ifeq ($(PLATFORM), PSOC_062_2M)
-# base kit CY8CPROTO-062-4343W
-DEVICE ?= CY8C624ABZI_S2D44
-PLATFORM_SUFFIX := 02
-else ifeq ($(PLATFORM), PSOC_062_1M)
-# base kit CY8CKIT-062-WIFI-BT
-DEVICE ?= CY8C6247BZI-D54
-PLATFORM_SUFFIX := 01
-else ifeq ($(PLATFORM), PSOC_062_512K)
-# base kit CY8CPROTO-062S3-4343W
-DEVICE ?= CY8C6245LQI-S3D72
-PLATFORM_SUFFIX := 03
-endif
-
-# Add device name to defines
-DEFINES += $(DEVICE)
-
-# Default upgrade method
-PLATFORM_DEFAULT_USE_OVERWRITE ?= 0
-
-###############################################################################
-# Application specific libraries
-###############################################################################
-# MCUBootApp
-###############################################################################
-THIS_APP_PATH = $(PRJ_DIR)/libs
-
-ifeq ($(APP_NAME), MCUBootApp)
-
-CORE := CM0P
-CORE_SUFFIX = m0plus
-
-# Add retartget IO implementation using pdl
-PLATFORM_SOURCES_RETARGET_IO_PDL := $(wildcard $(THIS_APP_PATH)/retarget_io_pdl/*.c)
-
-# Collect dirrectories containing headers for PLATFORM
-PLATFORM_INCLUDE_RETARGET_IO_PDL := $(THIS_APP_PATH)/retarget_io_pdl
-
-# PSOC6HAL source files
-PLATFORM_SOURCES_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_crypto_common.c
-PLATFORM_SOURCES_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/source/cyhal_hwmgr.c
-
-# needed for Crypto HW Acceleration and headers inclusion, do not use for peripherals
-# peripherals should be accessed
-PLATFORM_INCLUDE_DIRS_HAL_MCUB := $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include
-PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include
-PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/include_pvt
-PLATFORM_INCLUDE_DIRS_HAL_MCUB += $(THIS_APP_PATH)/mtb-hal-cat1/COMPONENT_CAT1A/include/pin_packages
-
-# mbedTLS hardware acceleration settings
-ifeq ($(USE_CRYPTO_HW), 1)
-# cy-mbedtls-acceleration related include directories
-INCLUDE_DIRS_MBEDTLS_MXCRYPTO := $(THIS_APP_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO
-# Collect source files for MbedTLS acceleration
-SOURCES_MBEDTLS_MXCRYPTO := $(wildcard $(THIS_APP_PATH)/cy-mbedtls-acceleration/mbedtls_MXCRYPTO/*.c)
-#
-INCLUDE_DIRS_LIBS += $(addprefix -I,$(INCLUDE_DIRS_MBEDTLS_MXCRYPTO))
-# Collected source files for libraries
-SOURCES_LIBS += $(SOURCES_MBEDTLS_MXCRYPTO)
-endif
-
-###############################################################################
-# Application dependent definitions
-# MCUBootApp default settings
-# 0 by default until mbedtls.3.0 support
-USE_CRYPTO_HW ?= 0
-
-# Bootloader size
-PLATFORM_BOOTLOADER_SIZE ?= 0x18000
-###############################################################################
-
-PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/cy_flash_pal
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/flash_qspi
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/include
-# INCLUDE_DIRS_APP += $(addprefix -I, $(PRJ_DIR)/cy_flash_pal/flash_psoc/include/flash_map_backend)
-PLATFORM_SOURCES_FLASH := $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_psoc6/*.c)
-PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_psoc6/flash_qspi/*.c)
-
-ifeq ($(USE_EXTERNAL_FLASH), 1)
-ifeq ($(BUILDCFG), Debug)
-# Include files with statically defined SMIF configuration to enable
-# OpenOCD debugging of external memory
-PLATFORM_SOURCES_FLASH += cy_serial_flash_prog.c
-PLATFORM_SOURCES_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/smif_cfg_dbg
-endif
-endif
-
-# Post build job to execute for platform
-post_build: $(OUT_CFG)/$(APP_NAME)_unsigned.hex
-ifeq ($(POST_BUILD_ENABLE), 1)
- $(info [POST BUILD] - Executing post build script for $(APP_NAME))
- $(shell cp -f $(OUT_CFG)/$(APP_NAME)_unsigned.hex $(OUT_CFG)/$(APP_NAME).hex)
- $(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME).hex > $(OUT_CFG)/$(APP_NAME).objdump
-else
- $(info Post build is disabled by POST_BUILD_ENABLE parameter)
-endif # POST_BUILD_ENABLE
-endif ## MCUBootApp
-
-###############################################################################
-# BlinkyApp
-###############################################################################
-ifeq ($(APP_NAME), BlinkyApp)
-
-CORE := CM4
-CORE_SUFFIX = m4
-
-ifeq ($(USE_EXTERNAL_FLASH), 1)
-PLATFORM_DEFAULT_ERASED_VALUE := 0xff
-else
-PLATFORM_DEFAULT_ERASED_VALUE := 0
-endif
-
-# Define start of application, RAM start and size, slot size
-ifeq ($(PLATFORM), PSOC_062_2M)
-ifeq ($(USE_XIP), 1)
- PLATFORM_DEFAULT_RAM_START ?= 0x08020000
- PLATFORM_DEFAULT_RAM_SIZE ?= 0xE0000
-else
- PLATFORM_DEFAULT_RAM_START ?= 0x08040000
- PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
-endif
-else ifeq ($(PLATFORM), PSOC_062_1M)
-ifeq ($(USE_XIP), 1)
- PLATFORM_DEFAULT_RAM_START ?= 0x08000800
- PLATFORM_DEFAULT_RAM_SIZE ?= 0x47800
-else
- PLATFORM_DEFAULT_RAM_START ?= 0x08020000
- PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
-endif
-else ifeq ($(PLATFORM), PSOC_062_512K)
-ifeq ($(USE_XIP), 1)
- PLATFORM_DEFAULT_RAM_START ?= 0x08000800
- PLATFORM_DEFAULT_RAM_SIZE ?= 0x3F800
-else
- PLATFORM_DEFAULT_RAM_START ?= 0x08020000
- PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
-endif
-endif
-# Default start address of application (boot)
-PLATFORM_USER_APP_START ?= $(PRIMARY_IMG_START)
-# For PSOC6 platform PRIMARY_IMG_START start is the same as USER_APP_START
-# This parameter can be different in cases when code is resided in
-# flash mapped to one address range, but executed using different bus
-# for access with another address range. For example, execution of code
-# from external memory in XIP mode.
-PLATFORM_DEFAULT_PRIMARY_IMG_START ?= $(PLATFORM_DEFAULT_USER_APP_START)
-
-PLATFORM_INCLUDE_DIRS_FLASH := $(PRJ_DIR)/cy_flash_pal
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/flash_qspi
-PLATFORM_INCLUDE_DIRS_FLASH += $(PRJ_DIR)/cy_flash_pal/flash_psoc6/include
-PLATFORM_SOURCES_FLASH += $(wildcard $(PRJ_DIR)/cy_flash_pal/flash_psoc6/flash_qspi/*.c)
-
-# We still need this for MCUBoot apps signing
-IMGTOOL_PATH ?= ../../scripts/imgtool.py
-
-PLATFORM_DEFAULT_IMG_VER_ARG ?= -v "1.0.0"
-
-PLATFORM_SIGN_ARGS := sign --header-size 1024 --pad-header --align 8 -M 512
-
-# Set parameters needed for signing
-ifeq ($(IMG_TYPE), UPGRADE)
- # Use encryption and random initial vector for image
- ifeq ($(ENC_IMG), 1)
- PLATFORM_SIGN_ARGS += --encrypt ../../$(ENC_KEY_FILE).pem
- PLATFORM_SIGN_ARGS += --use-random-iv
- endif
-endif
-
-# Post build action to execute after main build job
-post_build: $(OUT_CFG)/$(APP_NAME).bin
-ifeq ($(POST_BUILD_ENABLE), 1)
- $(info [POST BUILD] - Executing post build script for $(APP_NAME))
- $(shell mv -f $(OUT_CFG)/$(APP_NAME).bin $(OUT_CFG)/$(APP_NAME)_unsigned.bin)
- $(PYTHON_PATH) $(IMGTOOL_PATH) $(SIGN_ARGS) -S $(SLOT_SIZE) -R $(ERASED_VALUE) $(UPGRADE_TYPE) -k keys/$(SIGN_KEY_FILE).pem $(OUT_CFG)/$(APP_NAME)_unsigned.bin $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex --hex-addr=$(HEADER_OFFSET)
- $(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex > $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).objdump
-else
- $(info Post build is disabled by POST_BUILD_ENABLE parameter)
-endif # POST_BUILD_ENABLE
-endif ## BlinkyApp
-
-
-###############################################################################
-# Toolchain
-###############################################################################
-# Define build flags specific to a certain platform
-CFLAGS_PLATFORM := -mcpu=cortex-$(CORE_SUFFIX) -mfloat-abi=soft -fno-stack-protector -fstrict-aliasing
-
-###############################################################################
-# Common libraries
-###############################################################################
-PLATFORM_SYSTEM_FILE_NAME := system_psoc6_c$(CORE_SUFFIX).c
-PLATFORM_STARTUP_FILE := $(PRJ_DIR)/libs/mtb-pdl-cat1/devices/COMPONENT_CAT1A/templates/COMPONENT_MTB/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/startup_psoc6_$(PLATFORM_SUFFIX)_c$(CORE_SUFFIX).S
-
-PLATFORM_INCLUDE_DIRS_PDL_STARTUP := $(PRJ_DIR)/libs/mtb-pdl-cat1/devices/COMPONENT_CAT$(PDL_CAT_SUFFIX)/templates/COMPONENT_MTB
-
-###############################################################################
-# Print debug information about all settings used and/or set in this file
-ifeq ($(VERBOSE), 1)
-$(info #### PSOC6.mk ####)
-$(info APP_NAME <-- $(APP_NAME))
-$(info CFLAGS_PLATFORM <-> $(CFLAGS_PLATFORM))
-$(info COMPILER <-- $(COMPILER))
-$(info CORE <-> $(CORE))
-$(info CORE_SUFFIX <-- $(CORE_SUFFIX))
-$(info DEFINES <-> $(DEFINES))
-$(info DEVICE <-> $(DEVICE))
-$(info ENC_IMG <-- $(ENC_IMG))
-$(info ENC_KEY_FILE <-- $(ENC_KEY_FILE))
-$(info ERASED_VALUE <-- $(ERASED_VALUE))
-$(info FAMILY <-- $(FAMILY))
-$(info GCC_PATH <-- $(GCC_PATH))
-$(info HEADER_OFFSET <-- $(HEADER_OFFSET))
-$(info IMGTOOL_PATH <-> $(IMGTOOL_PATH))
-$(info IMG_TYPE <-- $(IMG_TYPE))
-$(info INCLUDE_DIRS_LIBS <-> $(INCLUDE_DIRS_LIBS))
-$(info INCLUDE_DIRS_MBEDTLS_MXCRYPTO <-> $(INCLUDE_DIRS_MBEDTLS_MXCRYPTO))
-$(info MCUBOOT_IMAGE_NUMBER <-- $(MCUBOOT_IMAGE_NUMBER))
-$(info OUT_CFG <-- $(OUT_CFG))
-$(info PDL_CAT_SUFFIX <-> $(PDL_CAT_SUFFIX))
-$(info PLATFORM <-- $(PLATFORM))
-$(info PLATFORM_APP_SOURCES <-> $(PLATFORM_APP_SOURCES))
-$(info PLATFORM_BOOTLOADER_SIZE <-> $(PLATFORM_BOOTLOADER_SIZE))
-$(info PLATFORM_DEFAULT_ERASED_VALUE <-> $(PLATFORM_DEFAULT_ERASED_VALUE))
-$(info PLATFORM_DEFAULT_RAM_SIZE <-> $(PLATFORM_DEFAULT_RAM_SIZE))
-$(info PLATFORM_DEFAULT_RAM_START <-> $(PLATFORM_DEFAULT_RAM_START))
-$(info PLATFORM_DEFAULT_SLOT_SIZE <-> $(PLATFORM_DEFAULT_SLOT_SIZE))
-$(info PLATFORM_DEFAULT_USER_APP_START <-> $(PLATFORM_DEFAULT_USER_APP_START))
-$(info PLATFORM_DEFAULT_PRIMARY_IMG_START <-> $(PLATFORM_DEFAULT_PRIMARY_IMG_START))
-$(info PLATFORM_DEFAULT_USE_OVERWRITE <-> $(PLATFORM_DEFAULT_USE_OVERWRITE))
-$(info PLATFORM_DEFINES <-- $(PLATFORM_DEFINES))
-$(info PLATFORM_EXTERNAL_FLASH_SCRATCH_OFFSET <-> $(PLATFORM_EXTERNAL_FLASH_SCRATCH_OFFSET))
-$(info PLATFORM_EXTERNAL_FLASH_SECONDARY_1_OFFSET <-> $(PLATFORM_EXTERNAL_FLASH_SECONDARY_1_OFFSET))
-$(info PLATFORM_EXTERNAL_FLASH_SECONDARY_2_OFFSET <-> $(PLATFORM_EXTERNAL_FLASH_SECONDARY_2_OFFSET))
-$(info PLATFORM_IMAGE_1_SLOT_SIZE <-> $(PLATFORM_IMAGE_1_SLOT_SIZE))
-$(info PLATFORM_IMAGE_2_SLOT_SIZE <-> $(PLATFORM_IMAGE_2_SLOT_SIZE))
-$(info PLATFORM_INCLUDE_DIRS_FLASH <-> $(PLATFORM_INCLUDE_DIRS_FLASH))
-$(info PLATFORM_INCLUDE_DIRS_HAL_MCUB <-> $(PLATFORM_INCLUDE_DIRS_HAL_MCUB))
-$(info PLATFORM_INCLUDE_DIRS_PDL_STARTUP <-> $(PLATFORM_INCLUDE_DIRS_PDL_STARTUP))
-$(info PLATFORM_INCLUDE_RETARGET_IO_PDL <-> $(PLATFORM_INCLUDE_RETARGET_IO_PDL))
-$(info PLATFORM_SCRATCH_SIZE <-> $(PLATFORM_SCRATCH_SIZE))
-$(info PLATFORM_DEFAULT_IMG_VER_ARG <-> $(PLATFORM_DEFAULT_IMG_VER_ARG))
-$(info PLATFORM_SIGN_ARGS <-> $(PLATFORM_SIGN_ARGS))
-$(info PLATFORM_SOURCES_FLASH <-> $(PLATFORM_SOURCES_FLASH))
-$(info PLATFORM_SOURCES_HAL_MCUB <-> $(PLATFORM_SOURCES_HAL_MCUB))
-$(info PLATFORM_SOURCES_RETARGET_IO_PDL <-> $(PLATFORM_SOURCES_RETARGET_IO_PDL))
-$(info PLATFORM_STARTUP_FILE <-> $(PLATFORM_STARTUP_FILE))
-$(info PLATFORM_SUFFIX <-> $(PLATFORM_SUFFIX))
-$(info PLATFORM_SYSTEM_FILE_NAME <-> $(PLATFORM_SYSTEM_FILE_NAME))
-$(info POST_BUILD_ENABLE <-- $(POST_BUILD_ENABLE))
-$(info PRJ_DIR <-- $(PRJ_DIR))
-$(info PYTHON_PATH <-- $(PYTHON_PATH))
-$(info SIGN_ARGS <-- $(SIGN_ARGS))
-$(info SIGN_KEY_FILE <-- $(SIGN_KEY_FILE))
-$(info SLOT_SIZE <-- $(SLOT_SIZE))
-$(info SOURCES_LIBS <-> $(SOURCES_LIBS))
-$(info SOURCES_MBEDTLS_MXCRYPTO <-> $(SOURCES_MBEDTLS_MXCRYPTO))
-$(info THIS_APP_PATH <-- $(THIS_APP_PATH))
-$(info UPGRADE_SUFFIX <-- $(UPGRADE_SUFFIX))
-$(info UPGRADE_TYPE <-- $(UPGRADE_TYPE))
-$(info USER_APP_START <-- $(USER_APP_START))
-$(info USE_CRYPTO_HW <-> $(USE_CRYPTO_HW))
-$(info USE_CUSTOM_MEMORY_MAP <-> $(USE_CUSTOM_MEMORY_MAP))
-$(info USE_EXTERNAL_FLASH <-> $(USE_EXTERNAL_FLASH))
-$(info USE_OVERWRITE <-- $(USE_OVERWRITE))
-$(info USE_XIP <-- $(USE_XIP))
-endif
diff --git a/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h b/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h
new file mode 100644
index 0000000..e4497fd
--- /dev/null
+++ b/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h
@@ -0,0 +1,68 @@
+/********************************************************************************
+* Copyright 2022 Infineon Technologies AG
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(MBEDTLS_COMPAT2X_H)
+#define MBEDTLS_COMPAT2X_H
+
+#include <string.h>
+
+#define mbedtls_sha256_starts_ret mbedtls_sha256_starts
+#define mbedtls_sha256_finish_ret mbedtls_sha256_finish
+
+static inline int mbedtls_sha256_update_ret(struct mbedtls_sha256_context *ctx,
+ const unsigned char *input,
+ size_t ilen)
+{
+ /* Cryptolite accelerator does not work on CBUS! */
+ if (input >= (const unsigned char *)CY_XIP_REMAP_OFFSET &&
+ input < (const unsigned char *)(CY_XIP_REMAP_OFFSET + CY_XIP_SIZE)) {
+
+ if (input + ilen > (const unsigned char *)(CY_XIP_REMAP_OFFSET + CY_XIP_SIZE)) {
+ return -MBEDTLS_ERR_SHA256_BAD_INPUT_DATA;
+ }
+ else {
+#ifdef MCUBOOT_ENC_IMAGES_XIP
+ /* Process chunks copied to SRAM */
+ uint8_t tmp_buf[0x400];
+ size_t offs = 0;
+ int rc = 0;
+
+ while (rc == 0 && offs < ilen) {
+ size_t len = ilen - offs;
+
+ if (len > sizeof(tmp_buf)) {
+ len = sizeof(tmp_buf);
+ }
+
+ (void)memcpy(tmp_buf, input + offs, len);
+ rc = mbedtls_sha256_update(ctx, tmp_buf, len);
+ offs += len;
+ }
+
+ (void)memset(tmp_buf, 0, sizeof(tmp_buf));
+ return rc;
+#else
+ /* Remap to SAHB */
+ input += CY_XIP_BASE - CY_XIP_SIZE;
+#endif /* MCUBOOT_ENC_IMAGES_XIP */
+ }
+ }
+
+ return mbedtls_sha256_update(ctx, input, ilen);
+}
+
+#endif /* MBEDTLS_COMPAT2X_H */
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/cy_flash_map.c b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_flash_map.c
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/cy_flash_map.c
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_flash_map.c
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/cy_smif_cyw20829.c b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_smif_cyw20829.c
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/cy_smif_cyw20829.c
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/cy_smif_cyw20829.c
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.c b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/cy_smif_hybrid_sect.c
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.c
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/cy_smif_hybrid_sect.c
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.h b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/cy_smif_hybrid_sect.h
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/cy_smif_hybrid_sect.h
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/cy_smif_hybrid_sect.h
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.c b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.c
similarity index 90%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.c
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.c
index 4bb8391..9933ff6 100644
--- a/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.c
+++ b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.c
@@ -73,10 +73,11 @@
#include "flash_qspi.h"
#include "cy_smif_hybrid_sect.h"
-#define CY_SMIF_SYSCLK_HFCLK_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_4
+#define CY_SMIF_SYSCLK_HFCLK_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
#define CY_SMIF_INIT_TRY_COUNT (10U)
#define CY_SMIF_INIT_TRY_DELAY (500U)
+#define CY_CHECK_MEMORY_AVAILABILITY_DELAY_US (1000U)
/* This is the board specific stuff that should align with your board.
*
@@ -131,74 +132,11 @@
en_hsiom_sel_t SS_Mux;
};
-#if (defined(PSOC_064_2M) || \
- defined(PSOC_064_1M) || \
- defined(PSOC_062_2M))
- #define CY_BOOTLOADER_SMIF_SS_CFG_NUM 4
-#elif defined(PSOC_064_512K)
- #define CY_BOOTLOADER_SMIF_SS_CFG_NUM 3
-#elif defined(CYW20829)
- #define CY_BOOTLOADER_SMIF_SS_CFG_NUM 2
-#else
-#error "Platform device name is unsupported."
-#endif
-
static cy_stc_smif_context_t QSPI_context;
static cy_stc_smif_block_config_t *smif_blk_config;
-#ifndef CYW20829
-static struct qspi_ss_config qspi_SS_Configuration[CY_BOOTLOADER_SMIF_SS_CFG_NUM] =
-{
- {
- .SS_Port = GPIO_PRT11,
- .SS_Pin = 2U,
- .SS_Mux = P11_2_SMIF_SPI_SELECT0
- },
- {
- .SS_Port = GPIO_PRT11,
- .SS_Pin = 1U,
- .SS_Mux = P11_1_SMIF_SPI_SELECT1
- },
-#if(CY_BOOTLOADER_SMIF_SS_CFG_NUM > 2)
- {
- .SS_Port = GPIO_PRT11,
- .SS_Pin = 0U,
- .SS_Mux = P11_0_SMIF_SPI_SELECT2
- },
-#endif
-#if(CY_BOOTLOADER_SMIF_SS_CFG_NUM > 3)
- {
- .SS_Port = GPIO_PRT12,
- .SS_Pin = 4U,
- .SS_Mux = P12_4_SMIF_SPI_SELECT3
- }
-#endif
-};
-
-static GPIO_PRT_Type *D3Port = GPIO_PRT11;
-static uint32_t D3Pin = 3U;
-static en_hsiom_sel_t D3MuxPort = P11_3_SMIF_SPI_DATA3;
-
-static GPIO_PRT_Type *D2Port = GPIO_PRT11;
-static uint32_t D2Pin = 4U;
-static en_hsiom_sel_t D2MuxPort = P11_4_SMIF_SPI_DATA2;
-
-static GPIO_PRT_Type *D1Port = GPIO_PRT11;
-static uint32_t D1Pin = 5U;
-static en_hsiom_sel_t D1MuxPort = P11_5_SMIF_SPI_DATA1;
-
-static GPIO_PRT_Type *D0Port = GPIO_PRT11;
-static uint32_t D0Pin = 6U;
-static en_hsiom_sel_t D0MuxPort = P11_6_SMIF_SPI_DATA0;
-
-static GPIO_PRT_Type *SCKPort = GPIO_PRT11;
-static uint32_t SCKPin = 7U;
-static en_hsiom_sel_t SCKMuxPort = P11_7_SMIF_SPI_CLK;
-
-#else
-
-static struct qspi_ss_config qspi_SS_Configuration[CY_BOOTLOADER_SMIF_SS_CFG_NUM] =
+static struct qspi_ss_config qspi_SS_Configuration[SMIF_CHIP_TOP_SPI_SEL_NR] =
{
{
.SS_Port = GPIO_PRT2,
@@ -231,7 +169,6 @@
static GPIO_PRT_Type *SCKPort = GPIO_PRT2;
static uint32_t SCKPin = 5U;
static en_hsiom_sel_t SCKMuxPort = P2_5_SMIF_SPIHB_CLK;
-#endif
static GPIO_PRT_Type *SS_Port;
static uint32_t SS_Pin;
@@ -303,11 +240,9 @@
{
.mode = (uint32_t)CY_SMIF_NORMAL,
.deselectDelay = 1,
-#ifdef CYW20829
+
.rxClockSel = (uint32_t)CY_SMIF_SEL_INVERTED_FEEDBACK_CLK,
-#else
- .rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
-#endif
+
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR
};
@@ -456,6 +391,9 @@
return st;
}
}
+
+ /* Set the polling delay in micro seconds to check memory device availability */
+ Cy_SMIF_SetReadyPollingDelay(CY_CHECK_MEMORY_AVAILABILITY_DELAY_US, &QSPI_context);
qspiReservations = EXT_FLASH_DEV_DISABLED;
return CY_SMIF_SUCCESS;
@@ -631,4 +569,3 @@
{
return qspiReservations;
}
-
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.h b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.h
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flash_qspi/flash_qspi.h
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flash_qspi/flash_qspi.h
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_multi2.json b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_multi2.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_multi2.json
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_multi2.json
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_single.json b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_single.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_single.json
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_single.json
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_multi2.json b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_multi2.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_multi2.json
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_multi2.json
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_multi2_psvp.json b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_shared_psvp.json
similarity index 79%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_multi2_psvp.json
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_shared_psvp.json
index 42151c1..40593c3 100644
--- a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_multi2_psvp.json
+++ b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_shared_psvp.json
@@ -40,33 +40,41 @@
},
"size": {
"description": "Size of the application primary slot",
- "value": "0xF000"
+ "value": "0x10000"
+ },
+ "shared_slot": {
+ "description": "Using shared secondary slot",
+ "value": true
},
"upgrade_address": {
"description": "Address of the application secondary slot",
- "value": "0x6003E000"
+ "value": "0x60040000"
},
"upgrade_size": {
"description": "Size of the application secondary slot",
- "value": "0xF000"
+ "value": "0x10000"
}
},
"application_2": {
"address": {
"description": "Address of the application primary slot",
- "value": "0x6002F000"
+ "value": "0x60030000"
},
"size": {
"description": "Size of the application primary slot",
- "value": "0xF000"
+ "value": "0x10000"
+ },
+ "shared_slot": {
+ "description": "Using shared secondary slot",
+ "value": true
},
"upgrade_address": {
"description": "Address of the application secondary slot",
- "value": "0x6004D000"
+ "value": "0x60041000"
},
"upgrade_size": {
"description": "Size of the application secondary slot",
- "value": "0xF000"
+ "value": "0x10000"
}
}
}
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single.json b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_single.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single.json
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_single.json
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2.json
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single.json
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_single.json
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/include/cy_smif_cyw20829.h b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/cy_smif_cyw20829.h
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/include/cy_smif_cyw20829.h
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/cy_smif_cyw20829.h
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/include/flash_map_backend/flash_map_backend.h b/boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/flash_map_backend/flash_map_backend.h
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/include/flash_map_backend/flash_map_backend.h
rename to boot/cypress/platforms/cy_flash_pal/flash_cyw20829/include/flash_map_backend/flash_map_backend.h
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/cy_flash_map.c b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_flash_map.c
similarity index 79%
rename from boot/cypress/cy_flash_pal/flash_psoc6/cy_flash_map.c
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_flash_map.c
index af17b0b..a3f23b8 100644
--- a/boot/cypress/cy_flash_pal/flash_psoc6/cy_flash_map.c
+++ b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_flash_map.c
@@ -65,20 +65,22 @@
{
int rc = -1;
- if (FLASH_DEVICE_INTERNAL_FLASH == fd_id) {
- *ret = CY_FLASH_BASE;
- rc = 0;
- }
-#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if ((fd_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
- *ret = CY_SMIF_BASE_MEM_OFFSET;
- rc = 0;
- }
-#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
- else {
- BOOT_LOG_ERR("invalid flash ID %u; expected %u or %u",
- (unsigned)fd_id, FLASH_DEVICE_INTERNAL_FLASH,
- FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX));
+ if (ret != NULL) {
+ if (FLASH_DEVICE_INTERNAL_FLASH == fd_id) {
+ *ret = CY_FLASH_BASE;
+ rc = 0;
+ }
+ #ifdef CY_BOOT_USE_EXTERNAL_FLASH
+ else if ((fd_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ *ret = CY_SMIF_BASE_MEM_OFFSET;
+ rc = 0;
+ }
+ #endif /* CY_BOOT_USE_EXTERNAL_FLASH */
+ else {
+ BOOT_LOG_ERR("invalid flash ID %u; expected %u or %u",
+ (unsigned)fd_id, FLASH_DEVICE_INTERNAL_FLASH,
+ FLASH_DEVICE_EXTERNAL_FLASH(CY_BOOT_EXTERNAL_DEVICE_INDEX));
+ }
}
return rc;
@@ -92,14 +94,16 @@
int rc = -1;
uint32_t i = 0u;
- while (NULL != boot_area_descs[i]) {
+ if (fa != NULL) {
+ while (boot_area_descs[i] != NULL) {
- if (id == boot_area_descs[i]->fa_id) {
- *fa = boot_area_descs[i];
- rc = 0;
- break;
+ if (id == boot_area_descs[i]->fa_id) {
+ *fa = boot_area_descs[i];
+ rc = 0;
+ break;
+ }
+ i++;
}
- i++;
}
return rc;
@@ -120,10 +124,11 @@
uint32_t len)
{
int rc = -1;
- size_t addr = 0u;
+ uintptr_t addr = 0u;
uintptr_t flash_base = 0u;
+ void* src;
- if ((NULL != dst) && (NULL != fa)) {
+ if ((dst != NULL) && (fa != NULL)) {
if (off > fa->fa_size ||
len > fa->fa_size ||
@@ -138,9 +143,11 @@
addr = flash_base + fa->fa_off + off;
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
+ /* Convert from uintptr_t to void*, MISRA C 11.6 */
+ (void)memcpy((void *)&src, (void const *)&addr, sizeof(void*));
/* flash read by simple memory copying */
- (void)memcpy((void *)dst, (const void *)((uint8_t *)addr), (size_t)len);
+ (void)memcpy(dst, src, (size_t)len);
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
else {
@@ -160,12 +167,12 @@
const void *src, uint32_t len)
{
int rc = BOOT_EFLASH;
- size_t write_start_addr = 0u;
- size_t write_end_addr = 0u;
+ uintptr_t write_start_addr = 0u;
+ uintptr_t write_end_addr = 0u;
const uint32_t * row_ptr = NULL;
uintptr_t flash_base = 0u;
- if ( (NULL != src) && (NULL != fa) ) {
+ if ((src != NULL) && (fa != NULL)) {
if (off > fa->fa_size ||
len > fa->fa_size ||
@@ -181,7 +188,7 @@
write_start_addr = flash_base + fa->fa_off + off;
write_end_addr = flash_base + fa->fa_off + off + len;
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
uint32_t row_number = 0u;
uint32_t row_addr = 0u;
@@ -227,12 +234,11 @@
int flash_area_erase(const struct flash_area *fa, uint32_t off, uint32_t len)
{
int rc = -1;
- size_t erase_start_addr = 0u;
- size_t erase_end_addr = 0u;
+ uintptr_t erase_start_addr = 0u;
+ uintptr_t erase_end_addr = 0u;
uintptr_t flash_base = 0u;
- if (NULL != fa) {
-
+ if (fa != NULL) {
if (off > fa->fa_size ||
len > fa->fa_size ||
off + len > fa->fa_size) {
@@ -243,11 +249,10 @@
rc = flash_device_base(fa->fa_device_id, &flash_base);
if (0 == rc) {
-
erase_start_addr = flash_base + fa->fa_off + off;
erase_end_addr = flash_base + fa->fa_off + off + len;
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
uint32_t row_number = 0u;
uint32_t row_addr = 0u;
uint32_t row_start_addr = (erase_start_addr / CY_FLASH_SIZEOF_ROW) * CY_FLASH_SIZEOF_ROW;
@@ -260,10 +265,9 @@
}
}
else {
-
row_number = (row_end_addr - row_start_addr) / CY_FLASH_SIZEOF_ROW;
- while (0u != row_number) {
+ while (row_number != 0u) {
row_number--;
row_addr = row_start_addr + row_number * (uint32_t) CY_FLASH_SIZEOF_ROW;
if (Cy_Flash_EraseRow(row_addr) != CY_FLASH_DRV_SUCCESS) {
@@ -289,8 +293,8 @@
{
size_t rc = 0u; /* error code (alignment cannot be zero) */
- if (NULL != fa) {
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ if (fa != NULL) {
+ if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
rc = CY_FLASH_ALIGN;
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
@@ -310,25 +314,27 @@
/*< Initializes an array of flash_area elements for the slot's sectors */
int flash_area_to_sectors(int idx, int *cnt, struct flash_area *fa)
{
- int rc = 0;
+ int rc = -1;
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
- (void)idx;
- (void)cnt;
- rc = 0;
- }
+ if (cnt != NULL && fa != NULL) {
+ if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
+ (void)idx;
+ (void)cnt;
+ rc = 0;
+ }
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
- (void)idx;
- (void)cnt;
- rc = 0;
- }
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ (void)idx;
+ (void)cnt;
+ rc = 0;
+ }
#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
- else
- {
- /* incorrect/non-existing flash device id */
- rc = -1;
+ else {
+ /* incorrect/non-existing flash device id */
+ rc = -1;
+ }
}
+
return rc;
}
#endif /* MCUBOOT_USE_FLASH_AREA_GET_SECTORS */
@@ -340,7 +346,7 @@
*/
int flash_area_id_from_multi_image_slot(int image_index, int slot)
{
- int rc;
+ int rc = -1;
if ((image_index < 0) || (image_index >= MCUBOOT_IMAGE_NUMBER)) {
return -1;
}
@@ -373,10 +379,10 @@
return -1;
}
- if (area_id == (int) FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index)) {
+ if ((int) FLASH_AREA_IMAGE_PRIMARY((uint32_t)image_index) == area_id) {
return 0;
}
- if (area_id == (int) FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index)) {
+ if ((int) FLASH_AREA_IMAGE_SECONDARY((uint32_t)image_index) == area_id) {
return 1;
}
@@ -392,7 +398,7 @@
{
uint8_t ret = 0u;
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
ret = (uint8_t) CY_BOOT_INTERNAL_FLASH_ERASE_VALUE;
}
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
@@ -418,7 +424,7 @@
uint32_t my_sector_addr = 0u;
uint32_t my_sector_size = 0u;
- while (NULL != boot_area_descs[i]) {
+ while (boot_area_descs[i] != NULL) {
if (idx == (int) boot_area_descs[i]->fa_id) {
fa = boot_area_descs[i];
break;
@@ -426,31 +432,31 @@
i++;
}
- if ( (NULL != fa) && (NULL != cnt) && (NULL != ret) ) {
+ if ((fa != NULL) && (cnt != NULL) && (ret != NULL)) {
size_t sector_size = 0;
size_t area_size = fa->fa_size;
- if (fa->fa_device_id == FLASH_DEVICE_INTERNAL_FLASH) {
+ if (FLASH_DEVICE_INTERNAL_FLASH == fa->fa_device_id) {
+ sector_size = CY_FLASH_SIZEOF_ROW;
#if defined(CY_BOOT_USE_EXTERNAL_FLASH) && defined(MCUBOOT_SWAP_USING_STATUS) && !defined(MCUBOOT_SWAP_USING_SCRATCH)
- if (idx == (int) FLASH_AREA_IMAGE_SWAP_STATUS) {
+ if ((int) FLASH_AREA_IMAGE_SWAP_STATUS == idx) {
sector_size = CY_FLASH_SIZEOF_ROW;
}
else {
sector_size = qspi_get_erase_size();
-#else
- sector_size = CY_FLASH_SIZEOF_ROW;
+ }
#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) && defined(MCUBOOT_SWAP_USING_STATUS) && !defined(MCUBOOT_SWAP_USING_SCRATCH) */
- }
+ }
#ifdef CY_BOOT_USE_EXTERNAL_FLASH
- else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
- /* implement for SMIF */
- /* lets assume they are equal */
+ else if ((fa->fa_device_id & FLASH_DEVICE_EXTERNAL_FLAG) == FLASH_DEVICE_EXTERNAL_FLAG) {
+ /* implement for SMIF */
+ /* lets assume they are equal */
#if defined(MCUBOOT_SWAP_USING_STATUS) || defined(USE_XIP)
- sector_size = qspi_get_erase_size();
+ sector_size = qspi_get_erase_size();
#else
- sector_size = CY_FLASH_SIZEOF_ROW;
+ sector_size = CY_FLASH_SIZEOF_ROW;
#endif /* MCUBOOT_SWAP_USING_STATUS */
- }
+ }
#endif /* CY_BOOT_USE_EXTERNAL_FLASH */
else {
/* fa->fa_device_id = FLASH_DEVICE_UNDEFINED,
@@ -484,8 +490,13 @@
ret[sectors_n].fs_off = my_sector_addr;
my_sector_addr += my_sector_size;
- area_size -= my_sector_size;
- sectors_n++;
+ if (area_size >= my_sector_size) {
+ area_size -= my_sector_size;
+ sectors_n++;
+ }
+ else {
+ area_size = 0;
+ }
}
if (sectors_n <= *cnt) {
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/cy_smif_psoc6.c
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
similarity index 95%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
index f62c3eb..5718bf5 100644
--- a/boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
+++ b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.c
@@ -67,9 +67,10 @@
#include <stdio.h>
#include "flash_qspi.h"
-#define CY_SMIF_SYSCLK_HFCLK_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_4
+#define CY_SMIF_SYSCLK_HFCLK_DIVIDER CY_SYSCLK_CLKHF_DIVIDE_BY_2
#define CY_SMIF_INIT_TRY_COUNT (10U)
+#define CY_CHECK_MEMORY_AVAILABILITY_DELAY_US (1000U)
/* This is the board specific stuff that should align with your board.
*
@@ -99,17 +100,8 @@
en_hsiom_sel_t SS_Mux;
};
-#if (defined(PSOC_064_2M) || \
- defined(PSOC_064_1M) || \
- defined(PSOC_062_2M) || \
- defined(PSOC_062_1M))
- #define CY_BOOTLOADER_SMIF_SS_CFG_NUM 4
-#elif defined(PSOC_064_512K) || defined(PSOC_062_512K) || defined(CYW20829)
- #define CY_BOOTLOADER_SMIF_SS_CFG_NUM 3
-#else
-#error "Platform device name is unsupported."
-#endif
-static struct qspi_ss_config qspi_SS_Configuration[CY_BOOTLOADER_SMIF_SS_CFG_NUM] =
+
+static struct qspi_ss_config qspi_SS_Configuration[SMIF_CHIP_TOP_SPI_SEL_NR] =
{
{
.SS_Port = GPIO_PRT11,
@@ -126,7 +118,7 @@
.SS_Pin = 0u,
.SS_Mux = P11_0_SMIF_SPI_SELECT2
},
-#if(CY_BOOTLOADER_SMIF_SS_CFG_NUM > 3)
+#if(SMIF_CHIP_TOP_SPI_SEL_NR > 3)
{
.SS_Port = GPIO_PRT12,
.SS_Pin = 4u,
@@ -177,7 +169,7 @@
static cy_stc_smif_mem_cmd_t readstsqecmd0;
static cy_stc_smif_mem_cmd_t writestseqcmd0;
-static cy_stc_smif_mem_device_cfg_t dev_sfdp_0 =
+cy_stc_smif_mem_device_cfg_t dev_sfdp_0 =
{
.numOfAddrBytes = 4,
.readSfdpCmd = &sfdpcmd,
@@ -192,7 +184,7 @@
.writeStsRegQeCmd = &writestseqcmd0,
};
-static cy_stc_smif_mem_config_t mem_sfdp_0 =
+cy_stc_smif_mem_config_t mem_sfdp_0 =
{
/* The base address the memory slave is mapped to in the PSoC memory map.
Valid when the memory-mapped mode is enabled. */
@@ -207,12 +199,12 @@
};
-static cy_stc_smif_mem_config_t *mems_sfdp[1] =
+cy_stc_smif_mem_config_t *mems_sfdp[1] =
{
&mem_sfdp_0
};
-static cy_stc_smif_block_config_t smifBlockConfig_sfdp =
+cy_stc_smif_block_config_t smifBlockConfig_sfdp =
{
.memCount = 1,
.memConfig = mems_sfdp,
@@ -233,8 +225,12 @@
#ifdef CM0P
static cy_stc_sysint_t smifIntConfig =
{/* ATTENTION: make sure proper Interrupts configured for CM0p or M4 cores */
+#if (CY_CPU_CORTEX_M0P)
.intrSrc = NvicMux7_IRQn,
.cm0pSrc = smif_interrupt_IRQn,
+#else
+ .intrSrc = smif_interrupt_IRQn,
+#endif
.intrPriority = 1
};
#endif
@@ -382,6 +378,9 @@
return st;
}
+ /* Set the polling delay in micro seconds to check memory device availability */
+ Cy_SMIF_SetReadyPollingDelay(CY_CHECK_MEMORY_AVAILABILITY_DELAY_US, &QSPI_context);
+
#ifdef CM0P
NVIC_EnableIRQ(smifIntConfig.intrSrc); /* Finally, Enable the SMIF interrupt */
#endif
@@ -440,13 +439,13 @@
case 3:
(*memCfg)->slaveSelect = CY_SMIF_SLAVE_SELECT_2;
break;
-#if(CY_BOOTLOADER_SMIF_SS_CFG_NUM > 3)
+#if(SMIF_CHIP_TOP_SPI_SEL_NR > 3)
case 4:
(*memCfg)->slaveSelect = CY_SMIF_SLAVE_SELECT_3;
break;
#endif
default:
- stat = -1;
+ stat = CY_SMIF_BAD_PARAM;
break;
}
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
similarity index 93%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
index 1458091..ff42980 100644
--- a/boot/cypress/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
+++ b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flash_qspi/flash_qspi.h
@@ -50,6 +50,11 @@
#include <stdint.h>
#include "cy_pdl.h"
+extern cy_stc_smif_block_config_t smifBlockConfig_sfdp;
+extern cy_stc_smif_mem_config_t *mems_sfdp[1];
+extern cy_stc_smif_mem_config_t mem_sfdp_0;
+extern cy_stc_smif_mem_device_cfg_t dev_sfdp_0;
+
cy_en_smif_status_t qspi_init_sfdp(uint32_t smif_id);
cy_en_smif_status_t qspi_init(cy_stc_smif_block_config_t *blk_config);
cy_en_smif_status_t qspi_init_hardware(void);
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi.json
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi_smif.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi_smif.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_multi_smif.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_multi_smif.json
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single.json
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single_smif.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single_smif.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_overwrite_single_smif.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_overwrite_single_smif.json
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_multi.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_multi.json
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi_smif.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_multi_smif.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_multi_smif.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_multi_smif.json
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_shared.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_shared.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_shared.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_shared.json
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single.json
diff --git a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single_psvp.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_cm0p.json
similarity index 71%
rename from boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single_psvp.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_cm0p.json
index 3fb2ac2..8cb90e1 100644
--- a/boot/cypress/cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single_psvp.json
+++ b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_cm0p.json
@@ -1,24 +1,18 @@
{
- "external_flash": [
- {
- "model": "FM25W04",
- "mode": "XIP"
- }
- ],
"boot_and_upgrade":
{
"bootloader": {
"address": {
"description": "Address of the bootloader",
- "value": "0x60000000"
+ "value": "0x10000000"
},
"size": {
"description": "Size of the bootloader",
- "value": "0x20000"
+ "value": "0x18000"
},
"scratch_address": {
"description": "Address of the scratch area",
- "value": "0x6007E000"
+ "value": "0x10040000"
},
"scratch_size": {
"description": "Size of the scratch area",
@@ -26,29 +20,33 @@
},
"status_address": {
"description": "Address of the swap status partition",
- "value": "0x60060000"
+ "value": "0x10038000"
},
"status_size": {
"description": "Size of the swap status partition",
- "value": "0xC000"
+ "value": "0x1800"
}
},
"application_1": {
+ "core": {
+ "description": "Run app on the specific core. PSoC6: CM0P or CM4",
+ "value": "CM0P"
+ },
"address": {
"description": "Address of the application primary slot",
- "value": "0x60020000"
+ "value": "0x10018000"
},
"size": {
"description": "Size of the application primary slot",
- "value": "0x20000"
+ "value": "0x10000"
},
"upgrade_address": {
"description": "Address of the application secondary slot",
- "value": "0x60040000"
+ "value": "0x10028000"
},
"upgrade_size": {
"description": "Size of the application secondary slot",
- "value": "0x20000"
+ "value": "0x10000"
}
}
}
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single_smif.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_swap_single_smif.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_swap_single_smif.json
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_overwrite.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_overwrite.json
similarity index 93%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_overwrite.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_overwrite.json
index 92e26e2..b54a07d 100644
--- a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_overwrite.json
+++ b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_overwrite.json
@@ -24,7 +24,7 @@
},
"size": {
"description": "Size of the application primary slot",
- "value": "0x80000"
+ "value": "0x40200"
},
"upgrade_address": {
"description": "Address of the application secondary slot",
@@ -32,7 +32,7 @@
},
"upgrade_size": {
"description": "Size of the application secondary slot",
- "value": "0x80000"
+ "value": "0x40200"
}
}
}
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_swap.json b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_swap.json
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/flashmap/psoc62_xip_swap.json
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/flashmap/psoc6_xip_swap.json
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/cy_smif_psoc6.h
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/include/flash_map_backend/flash_map_backend.h
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.c
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.h b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.h
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.h
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/cycfg_qspi_memslot.h
diff --git a/boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/qspi_config.cfg b/boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/qspi_config.cfg
similarity index 100%
rename from boot/cypress/cy_flash_pal/flash_psoc6/smif_cfg_dbg/qspi_config.cfg
rename to boot/cypress/platforms/cy_flash_pal/flash_psoc6/smif_cfg_dbg/qspi_config.cfg
diff --git a/boot/cypress/cy_flash_pal/sysflash/sysflash.h b/boot/cypress/platforms/cy_flash_pal/sysflash/sysflash.h
similarity index 100%
rename from boot/cypress/cy_flash_pal/sysflash/sysflash.h
rename to boot/cypress/platforms/cy_flash_pal/sysflash/sysflash.h
diff --git a/boot/cypress/platforms/CYW20829/img_confirm/set_img_ok.c b/boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c
similarity index 100%
rename from boot/cypress/platforms/CYW20829/img_confirm/set_img_ok.c
rename to boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c
diff --git a/boot/cypress/platforms/PSOC6/img_confirm/set_img_ok.c b/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c
similarity index 97%
rename from boot/cypress/platforms/PSOC6/img_confirm/set_img_ok.c
rename to boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c
index 220f86c..83c0581 100644
--- a/boot/cypress/platforms/PSOC6/img_confirm/set_img_ok.c
+++ b/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c
@@ -71,11 +71,6 @@
#else
-extern cy_stc_smif_block_config_t smifBlockConfig_sfdp;
-extern cy_stc_smif_mem_config_t *mems_sfdp[1];
-extern cy_stc_smif_mem_config_t mem_sfdp_0;
-extern cy_stc_smif_mem_device_cfg_t dev_sfdp_0;
-
/**
* @brief Function sets img_ok value to primary slot trailer
* when application is executed from external memory
diff --git a/boot/cypress/BlinkyApp/set_img_ok.h b/boot/cypress/platforms/img_confirm/set_img_ok.h
similarity index 91%
rename from boot/cypress/BlinkyApp/set_img_ok.h
rename to boot/cypress/platforms/img_confirm/set_img_ok.h
index 68d4ac2..60f98e8 100644
--- a/boot/cypress/BlinkyApp/set_img_ok.h
+++ b/boot/cypress/platforms/img_confirm/set_img_ok.h
@@ -19,7 +19,9 @@
#define SET_IMG_OK_H
#include "cy_flash.h"
+#if defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829)
#include "flash_qspi.h"
+#endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829) */
#include "sysflash/sysflash.h"
#include <string.h>
diff --git a/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.c b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c
similarity index 97%
rename from boot/cypress/platforms/CYW20829/cy_security_cnt_platform.c
rename to boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c
index cd39f2d..d0a86a9 100644
--- a/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.c
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c
@@ -14,15 +14,15 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-#include <stdint.h>
-#include "sysflash/sysflash.h"
-#include "cy_efuse.h"
+#include <stdint.h>
#include "cy_security_cnt_platform.h"
#include "cy_service_app.h"
+#include "sysflash/sysflash.h"
+#include "cy_efuse.h"
-#if defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT
+#if defined MCUBOOT_HW_ROLLBACK_PROT
#define TEST_BIT(var, pos) (0U != ((var) & (1UL << (pos))))
@@ -145,4 +145,4 @@
return rc;
}
-#endif /* defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT */
+#endif /* defined MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.h b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h
similarity index 97%
rename from boot/cypress/platforms/CYW20829/cy_security_cnt_platform.h
rename to boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h
index d2e0e3c..578e689 100644
--- a/boot/cypress/platforms/CYW20829/cy_security_cnt_platform.h
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h
@@ -18,8 +18,6 @@
#ifndef CY_SECURITY_CNT_PLATFORM_H
#define CY_SECURITY_CNT_PLATFORM_H
-#ifdef CYW20829
-
#include "bootutil/fault_injection_hardening.h"
#define MAX_SEC_COUNTER_VAL (32U)
@@ -45,6 +43,5 @@
* @return 0 on success; nonzero on failure.
*/
int32_t platform_security_counter_update(uint32_t img_security_cnt, uint8_t * reprov_packet);
-#endif /* CYW20829 */
#endif /* CY_SECURITY_CNT_PLATFORM_H */
diff --git a/boot/cypress/platforms/CYW20829/cy_service_app.c b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c
similarity index 98%
rename from boot/cypress/platforms/CYW20829/cy_service_app.c
rename to boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c
index 2d2f2fb..eb1615a 100644
--- a/boot/cypress/platforms/CYW20829/cy_service_app.c
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c
@@ -21,13 +21,11 @@
#include "bootutil/image.h"
#include "bootutil_priv.h"
#include "sysflash/sysflash.h"
-
+#include "cy_service_app.h"
#include "flash_qspi.h"
#include "cy_smif_cyw20829.h"
-#include "cy_service_app.h"
-
-#if defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT
+#if defined MCUBOOT_HW_ROLLBACK_PROT
#ifndef CY_BOOT_EXTERNAL_FLASH_ERASE_VALUE
/* This is the value of external flash bytes after an erase */
@@ -198,4 +196,4 @@
return rc;
}
-#endif /* MCUBootApp && MCUBOOT_HW_ROLLBACK_PROT */
+#endif /* MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/CYW20829/cy_service_app.h b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.h
similarity index 96%
rename from boot/cypress/platforms/CYW20829/cy_service_app.h
rename to boot/cypress/platforms/security_counter/CYW20829/cy_service_app.h
index c306bfa..2f76386 100644
--- a/boot/cypress/platforms/CYW20829/cy_service_app.h
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.h
@@ -21,7 +21,7 @@
extern "C" {
#endif
-#if defined(MCUBootApp) && defined(MCUBOOT_HW_ROLLBACK_PROT)
+#if defined(MCUBOOT_HW_ROLLBACK_PROT)
#include <stdint.h>
@@ -106,4 +106,4 @@
}
#endif
-#endif /* CY_SERVICE_APP && MCUBOOT_HW_ROLLBACK_PROT */
+#endif /* MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.c b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c
similarity index 93%
rename from boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.c
rename to boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c
index c918656..17a4e08 100644
--- a/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.c
+++ b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c
@@ -14,14 +14,13 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-#include <stdint.h>
+#include <stdint.h>
+#include "cy_security_cnt_platform.h"
#include "sysflash/sysflash.h"
#include "bootutil/bootutil_log.h"
-#include "cy_security_cnt_platform.h"
-
-#if defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT
+#if defined MCUBOOT_HW_ROLLBACK_PROT
/*
* Reads a data corresponding to security counter which is stored in
@@ -60,4 +59,4 @@
return -1;
}
-#endif /* defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT */
+#endif /* defined MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.h b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h
similarity index 97%
rename from boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.h
rename to boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h
index b7cca56..69874c9 100644
--- a/boot/cypress/platforms/PSOC6/secure/cy_security_cnt_platform.h
+++ b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h
@@ -18,8 +18,6 @@
#ifndef CY_SECURITY_CNT_PLATFORM_H
#define CY_SECURITY_CNT_PLATFORM_H
-#ifdef PSOC6
-
#include "bootutil/fault_injection_hardening.h"
/**
@@ -43,6 +41,5 @@
* @return 0 on success; nonzero on failure.
*/
int32_t platform_security_counter_update(uint32_t img_security_cnt, void * custom_data);
-#endif /* PSOC6 */
-#endif /* CY_SECURITY_CNT_PLATFORM_H */
\ No newline at end of file
+#endif /* CY_SECURITY_CNT_PLATFORM_H */
diff --git a/boot/cypress/MCUBootApp/cy_security_cnt.c b/boot/cypress/platforms/security_counter/cy_security_cnt.c
similarity index 90%
rename from boot/cypress/MCUBootApp/cy_security_cnt.c
rename to boot/cypress/platforms/security_counter/cy_security_cnt.c
index d658345..56b92a4 100644
--- a/boot/cypress/MCUBootApp/cy_security_cnt.c
+++ b/boot/cypress/platforms/security_counter/cy_security_cnt.c
@@ -14,7 +14,7 @@
* limitations under the License.
*/
-#if defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT
+#if defined MCUBOOT_HW_ROLLBACK_PROT
#include <stdint.h>
#include <string.h>
@@ -52,4 +52,4 @@
return rc;
}
-#endif /* defined MCUBootApp && defined MCUBOOT_HW_ROLLBACK_PROT */
+#endif /* defined MCUBOOT_HW_ROLLBACK_PROT */
diff --git a/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.c b/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c
similarity index 95%
rename from boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.c
rename to boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c
index 5778fc1..92953f4 100644
--- a/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.c
+++ b/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.c
@@ -14,7 +14,7 @@
* limitations under the License.
*/
-#include "cyw_20829_utils.h"
+#include "cyw_platform_utils.h"
/* Cypress pdl headers */
#include "cy_pdl.h"
@@ -207,21 +207,21 @@
FIH_PANIC;
}
-/* End of cyw20829_RunAppFinish() */
+/* End of platform_RunNextAppFinish() */
extern uint8_t hsiniFppAnuR_92802wyc[];
CY_RAMFUNC_BEGIN
static __NO_RETURN __attribute__((naked))
-void cyw20829_RunAppFinish(uintptr_t bootstrap_dst,
+void platform_RunNextAppFinish(uintptr_t bootstrap_dst,
uintptr_t bootstrap_src,
uint32_t bootstrap_size)
{
/* MCUBoot is over! The code below depends on the linker script. Assuming
* stack is located at the very beginning, followed by code and data, and
- * heap is located at the end. cyw20829_RunAppFinish is located as low as
+ * heap is located at the end. platform_RunNextAppFinish is located as low as
* possible, ideally following the MCUBoot's Vector Table in RAM, to save
* max space for the application (the goal is to fit below 0x20004000).
- * First we wipe SRAM from the end of cyw20829_RunAppFinish to the end of
+ * First we wipe SRAM from the end of platform_RunNextAppFinish to the end of
* heap. Then bootstrap is copied to its place. Then, after the necessary
* setup, we wipe SRAM from the stack limit to the wiping loop itself. So
* only 6 launcher's instructions are left. Note that the app's bootstrap
@@ -296,7 +296,7 @@
CY_RAMFUNC_END
CY_RAMFUNC_BEGIN
-__NO_RETURN void cyw20829_RunApp(fih_uint toc2_addr, uint32_t *key, uint32_t *iv)
+__NO_RETURN void platform_RunNextApp(fih_uint toc2_addr, uint32_t *key, uint32_t *iv)
{
fih_uint l1_app_descr_addr = (fih_uint)FIH_FAILURE;
fih_uint ns_vect_tbl_addr = (fih_uint)FIH_FAILURE;
@@ -362,11 +362,11 @@
* the linker script, the runtime check is below (BOOTSTRAP_SRAM0_ADDR).
*/
if (fits_into((uintptr_t)bootstrap_dst_addr, 0,
- (uintptr_t)cyw20829_RunAppFinish,
- (uintptr_t)hsiniFppAnuR_92802wyc - (uintptr_t)cyw20829_RunAppFinish) ||
+ (uintptr_t)platform_RunNextAppFinish,
+ (uintptr_t)hsiniFppAnuR_92802wyc - (uintptr_t)platform_RunNextAppFinish) ||
fits_into((uintptr_t)bootstrap_dst_addr + bootstrap_size, 0,
- (uintptr_t)cyw20829_RunAppFinish,
- (uintptr_t)hsiniFppAnuR_92802wyc - (uintptr_t)cyw20829_RunAppFinish)) {
+ (uintptr_t)platform_RunNextAppFinish,
+ (uintptr_t)hsiniFppAnuR_92802wyc - (uintptr_t)platform_RunNextAppFinish)) {
FIH_PANIC;
}
@@ -413,7 +413,7 @@
}
/* MCUBoot is over */
- cyw20829_RunAppFinish((uintptr_t)bootstrap_dst_addr,
+ platform_RunNextAppFinish((uintptr_t)bootstrap_dst_addr,
(uintptr_t)fih_uint_decode(ns_vect_tbl_addr),
bootstrap_size);
}
diff --git a/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.h b/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.h
similarity index 86%
rename from boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.h
rename to boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.h
index ecaf9d1..3adc51a 100644
--- a/boot/cypress/platforms/CYW20829/utils/cyw_20829_utils.h
+++ b/boot/cypress/platforms/utils/CYW20829/cyw_platform_utils.h
@@ -14,8 +14,8 @@
* limitations under the License.
*/
-#ifndef CYW_20829_UTILS_H
-#define CYW_20829_UTILS_H
+#ifndef CYW_PLATFORMS_UTILS_H
+#define CYW_PLATFORMS_UTILS_H
#include <stddef.h>
#include <stdint.h>
@@ -40,8 +40,8 @@
extern const volatile uint32_t __StackLimit[];
extern const volatile uint32_t __StackTop[];
-__NO_RETURN void cyw20829_RunApp(fih_uint toc2_addr, uint32_t *key, uint32_t *iv);
+__NO_RETURN void platform_RunNextApp(fih_uint toc2_addr, uint32_t *key, uint32_t *iv);
#endif
-#endif /* CYW_20829_UTILS_H */
+#endif /* CYW_PLATFORMS_UTILS_H */
diff --git a/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.c b/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.c
new file mode 100644
index 0000000..2329670
--- /dev/null
+++ b/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.c
@@ -0,0 +1,142 @@
+/***************************************************************************//**
+* \file cyw_platform_utils.h
+*
+* \brief
+* PSoC6 platform utilities
+*
+********************************************************************************
+* \copyright
+* (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include <string.h>
+#include "cyw_platform_utils.h"
+
+#define IVT_ALIGNMENT (0x3FFu) /* IVT alignment requires to have these bits as zeros in IVT */
+#define STACK_ALIGNMENT (7u) /* Per ARM AABI, a stack should be aligned to 64 bits, thus should have these bits as zeros */
+#define THUMB_CALL_MASK (1u) /* THUMB ISA requires the LSB of a function call address to be 1 */
+
+/* Symbols below are provided by the linker script: */
+extern uint8_t __data_start__[];
+extern uint8_t __data_end__[];
+
+extern uint8_t __bss_start__[];
+extern uint8_t __bss_end__[];
+
+extern uint8_t __HeapBase[];
+extern uint8_t __HeapLimit[];
+
+extern uint8_t __StackLimit[];
+extern uint8_t __StackTop[];
+
+/* An app begins with vector table that starts with: */
+typedef struct
+{
+ uint32_t stack_pointer;
+ void (*reset_handler)(void);
+} vect_tbl_start_t;
+
+/**
+ * Should never get to this function.
+ */
+static __NO_RETURN void hang(void)
+{
+ while (true) {
+ CY_ASSERT((bool)0);
+ }
+}
+
+/**
+ * Starts the application on the current core. MCUBoot is also running on
+ * this core, so we just clean up memory, set up the vector table and stack,
+ * and transfer control to the app's reset handler.
+ *
+ * @param app_addr FIH-protected address of the app's vector table.
+ */
+#ifdef CM0P
+__NO_RETURN void psoc6_launch_cm0p_app(fih_uint app_addr)
+#else
+__NO_RETURN void psoc6_launch_cm4_app(fih_uint app_addr)
+#endif /* CM0P */
+{
+ register vect_tbl_start_t* const vect_tbl1 = (vect_tbl_start_t*)fih_uint_decode(app_addr);
+ register vect_tbl_start_t* const vect_tbl2 = (vect_tbl_start_t*)fih_uint_decode(app_addr);
+
+ do
+ {
+ if ( (vect_tbl1 != vect_tbl2) || /* validate app_addr */
+ (0u != ((uint32_t)vect_tbl1 & IVT_ALIGNMENT)) || /* validate IVT alignment */
+ (0u != ((uint32_t)vect_tbl1->stack_pointer & STACK_ALIGNMENT)) || /* validate stack alignment in IVT*/
+ (0u == ((uint32_t)vect_tbl1->reset_handler & THUMB_CALL_MASK)) ) /* validate reset handler address is TUHMB compliant */
+ {
+ break;
+ }
+
+ /* Data, Heap, Stack and BSS section in RAM can contain sensitive data, used by bootloader.
+ * Set these sections to the default of 0 before next application start so no data left in
+ * RAM after bootloader completed execution.
+ */
+ (void)memset(__data_start__, 0, (size_t)((uintptr_t)__data_end__ - (uintptr_t)__data_start__));
+ (void)memset(__HeapBase, 0, (size_t)((uintptr_t)__HeapLimit - (uintptr_t)__HeapBase));
+ (void)memset(__StackLimit, 0, (size_t)((uintptr_t)__StackTop - (uintptr_t)__StackLimit));
+ (void)memset(__bss_start__, 0, (size_t)((uintptr_t)__bss_end__ - (uintptr_t)__bss_start__));
+
+ /* Relocate Vector Table */
+ #ifdef CM0P
+ CPUSS->CM0_VECTOR_TABLE_BASE = (uintptr_t)vect_tbl1;
+ if((uintptr_t)CPUSS->CM0_VECTOR_TABLE_BASE != (uintptr_t)vect_tbl2)
+ {
+ break;
+ }
+ #else
+ CPUSS->CM4_VECTOR_TABLE_BASE = (uintptr_t)vect_tbl1;
+ if((uintptr_t)CPUSS->CM4_VECTOR_TABLE_BASE != (uintptr_t)vect_tbl2)
+ {
+ break;
+ }
+ #endif /* CM0P */
+ SCB->VTOR = (uintptr_t)vect_tbl1;
+ if((uintptr_t)SCB->VTOR != (uintptr_t)vect_tbl2)
+ {
+ break;
+ }
+
+ __DSB();
+ __ISB();
+
+ __set_MSP(vect_tbl1->stack_pointer);
+ if ((uintptr_t)__get_MSP() != (uintptr_t)vect_tbl2->stack_pointer)
+ {
+ break;
+ }
+
+ if ((uintptr_t)vect_tbl1->reset_handler != (uintptr_t)vect_tbl2->reset_handler)
+ {
+ break;
+ }
+
+ /* Transfer control to the application */
+ __DSB();
+ __ISB();
+ vect_tbl1->reset_handler(); /* Never returns */
+
+ } while(false);
+
+ /* Should never get here */
+ hang();
+}
diff --git a/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.h b/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.h
new file mode 100644
index 0000000..3e514e0
--- /dev/null
+++ b/boot/cypress/platforms/utils/PSOC6/cyw_platform_utils.h
@@ -0,0 +1,54 @@
+/***************************************************************************//**
+* \file cyw_platform_utils.h
+*
+* \brief
+* PSoC6 platform utilities
+*
+********************************************************************************
+* \copyright
+* (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+#ifndef CYW_PLATFORMS_UTILS_H
+#define CYW_PLATFORMS_UTILS_H
+
+#include "cy_pdl.h"
+#include "bootutil/fault_injection_hardening.h"
+
+#if defined CM0P
+/**
+ * Starts the application on the Cortex-M0+ core. MCUBoot is also running on
+ * this core, so we just clean up memory, set up the vector table and stack,
+ * and transfer control to the app's reset handler.
+ *
+ * @param app_addr FIH-protected address of the app's vector table.
+ */
+__NO_RETURN void psoc6_launch_cm0p_app(fih_uint app_addr);
+#elif defined CM4
+/**
+ * Starts the application on the Cortex-M4 core. MCUBoot is also running on
+ * this core, so we just clean up memory, set up the vector table and stack,
+ * and transfer control to the app's reset handler.
+ *
+ * @param app_addr FIH-protected address of the app's vector table.
+ */
+__NO_RETURN void psoc6_launch_cm4_app(fih_uint app_addr);
+#else
+#error "MCUBoot should be compiled for either Cortex-M0+ or Cortex-M4"
+#endif /* defined CM... */
+
+#endif /* CYW_PLATFORMS_UTILS_H */
diff --git a/boot/cypress/platforms/utils/PSOC6/psoc6_02_cm0p_sleep.c b/boot/cypress/platforms/utils/PSOC6/psoc6_02_cm0p_sleep.c
new file mode 100644
index 0000000..e5af3e6
--- /dev/null
+++ b/boot/cypress/platforms/utils/PSOC6/psoc6_02_cm0p_sleep.c
@@ -0,0 +1,421 @@
+/***************************************************************************//**
+* \file psoc6_02_cm0p_sleep.c
+*
+* \brief
+* Cortex-M0+ prebuilt application image.
+*
+********************************************************************************
+* \copyright
+* Copyright (c) 2018-2021 Cypress Semiconductor Corporation (an Infineon
+* company) or an affiliate of Cypress Semiconductor Corporation
+* SPDX-License-Identifier: LicenseRef-PBL
+*
+* Licensed under the Permissive Binary License
+*******************************************************************************/
+
+#include <stdint.h>
+#include "cy_device_headers.h"
+
+#if defined(CY_DEVICE_PSOC6A2M)
+
+#if defined(__APPLE__) && defined(__clang__)
+__attribute__ ((__section__("__CY_M0P_IMAGE,__cy_m0p_image"), used))
+#elif defined(__GNUC__) || defined(__ARMCC_VERSION)
+__attribute__ ((__section__(".cy_m0p_image"), used))
+#elif defined(__ICCARM__)
+#pragma location=".cy_m0p_image"
+#else
+#error "An unsupported toolchain"
+#endif
+const uint8_t cy_m0p_image[] = {
+ 0x00u, 0x20u, 0x00u, 0x08u, 0xebu, 0x00u, 0x00u, 0x10u, 0x0du, 0x00u, 0x00u, 0x00u, 0x4du, 0x01u, 0x00u, 0x10u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x49u, 0x01u, 0x00u, 0x10u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
+ 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
+ 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
+ 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
+ 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u,
+ 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u,
+ 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x0cu, 0x15u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u,
+ 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0xb4u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x15u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u,
+ 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u,
+ 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u,
+ 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu,
+ 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au,
+ 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u,
+ 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0xf9u, 0xfeu, 0x00u, 0xf0u, 0xa9u, 0xfeu, 0xfeu, 0xe7u,
+ 0x18u, 0x15u, 0x00u, 0x10u, 0x30u, 0x15u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u,
+ 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u,
+ 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x02u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u,
+ 0x04u, 0x30u, 0x00u, 0xf0u, 0x8du, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u,
+ 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xbau, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au,
+ 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u,
+ 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u,
+ 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u,
+ 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u,
+ 0x1bu, 0x06u, 0x98u, 0x42u, 0x1cu, 0xd0u, 0x12u, 0x4bu, 0x98u, 0x42u, 0xeau, 0xd1u, 0xa0u, 0x20u, 0x0bu, 0xe0u,
+ 0x10u, 0x4bu, 0x98u, 0x42u, 0x0au, 0xd0u, 0x10u, 0x4bu, 0x98u, 0x42u, 0x09u, 0xd0u, 0x0fu, 0x4bu, 0x98u, 0x42u,
+ 0xdfu, 0xd1u, 0x0fu, 0x48u, 0x70u, 0x47u, 0xa4u, 0x20u, 0xc0u, 0x03u, 0xfbu, 0xe7u, 0x0du, 0x48u, 0xf9u, 0xe7u,
+ 0x0du, 0x48u, 0xf7u, 0xe7u, 0x0du, 0x48u, 0xf5u, 0xe7u, 0x0du, 0x48u, 0xf3u, 0xe7u, 0x0du, 0x48u, 0xf1u, 0xe7u,
+ 0x00u, 0x20u, 0xefu, 0xe7u, 0x06u, 0x00u, 0x52u, 0x00u, 0xffu, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x00u, 0xf0u,
+ 0x09u, 0x00u, 0x00u, 0xa0u, 0x04u, 0x00u, 0x00u, 0xf0u, 0x05u, 0x00u, 0x00u, 0xf0u, 0x03u, 0x00u, 0x00u, 0xf0u,
+ 0x01u, 0x00u, 0x52u, 0x00u, 0x02u, 0x00u, 0x52u, 0x00u, 0x03u, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u,
+ 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu,
+ 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xbcu, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu,
+ 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u,
+ 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u,
+ 0xccu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xbcu, 0x33u, 0x1bu, 0x68u,
+ 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u,
+ 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu,
+ 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u,
+ 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xbcu, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u,
+ 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u,
+ 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u,
+ 0x18u, 0x60u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu,
+ 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu,
+ 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xbau, 0x36u, 0x36u, 0x88u,
+ 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u,
+ 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u,
+ 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u,
+ 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u,
+ 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x03u, 0x68u, 0x06u, 0x6au, 0x17u, 0x33u,
+ 0x6bu, 0x80u, 0x43u, 0x68u, 0x47u, 0x6au, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u,
+ 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb8u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u,
+ 0x30u, 0x00u, 0xffu, 0xf7u, 0xb1u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0x2du, 0xfbu, 0x00u, 0x22u,
+ 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u,
+ 0x01u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u,
+ 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u,
+ 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau,
+ 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u,
+ 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu,
+ 0xa4u, 0xb2u, 0x4bu, 0x62u, 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u,
+ 0xe0u, 0x03u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u,
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+ 0xd3u, 0x58u, 0x00u, 0x2bu, 0x3eu, 0xdau, 0x36u, 0x4au, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, 0xf0u, 0xf8u,
+ 0x00u, 0x28u, 0x37u, 0xd1u, 0x01u, 0x98u, 0xffu, 0xf7u, 0x8fu, 0xffu, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x3eu, 0xd0u,
+ 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0xbbu, 0xf8u, 0x04u, 0x00u, 0x2bu, 0xe0u, 0x06u, 0x20u,
+ 0x00u, 0xf0u, 0xc6u, 0xf8u, 0x2bu, 0x68u, 0xbcu, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu,
+ 0x02u, 0xdau, 0x28u, 0x4cu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x00u, 0x20u, 0x00u, 0xf0u, 0xa1u, 0xf8u, 0x26u, 0x4bu,
+ 0x98u, 0x42u, 0xf6u, 0xd0u, 0x00u, 0x23u, 0x25u, 0x4au, 0x19u, 0x00u, 0x12u, 0x68u, 0x01u, 0x20u, 0x00u, 0xf0u,
+ 0xa7u, 0xf8u, 0x00u, 0x25u, 0xa8u, 0x42u, 0xecu, 0xd1u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x91u, 0xf8u, 0x1eu, 0x4au,
+ 0x1fu, 0x4bu, 0x90u, 0x42u, 0x03u, 0xd0u, 0x9du, 0x42u, 0xe3u, 0xd0u, 0x01u, 0x35u, 0xf4u, 0xe7u, 0x9du, 0x42u,
+ 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, 0x05u, 0xd1u, 0x01u, 0x21u, 0x00u, 0x20u, 0x00u, 0xf0u,
+ 0xb7u, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x72u, 0xf8u, 0xd2u, 0xe7u, 0x15u, 0x4cu,
+ 0xf1u, 0xe7u, 0x00u, 0xf0u, 0x9du, 0xf8u, 0x0eu, 0x4au, 0x05u, 0x00u, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u,
+ 0x9fu, 0xf8u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x08u, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu,
+ 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x6du, 0xf8u, 0x04u, 0x00u, 0xe5u, 0xe7u, 0x06u, 0x4cu, 0xe3u, 0xe7u, 0x09u, 0x4cu,
+ 0xe1u, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u,
+ 0xccu, 0x03u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0xdcu, 0x03u, 0x00u, 0x08u,
+ 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au,
+ 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu,
+ 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u,
+ 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u,
+ 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u,
+ 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u,
+ 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u,
+ 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u,
+ 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xe3u, 0x00u, 0x00u, 0x10u,
+ 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xddu, 0x05u, 0x00u, 0x10u,
+ 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x39u, 0x02u, 0x00u, 0x10u,
+ 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xadu, 0x03u, 0x00u, 0x10u,
+ 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x75u, 0x01u, 0x00u, 0x10u,
+ 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xc5u, 0x0fu, 0x00u, 0x10u,
+ 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xdbu, 0x00u, 0x00u, 0x10u,
+ 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x9du, 0x02u, 0x00u, 0x10u,
+ 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x69u, 0x05u, 0x00u, 0x10u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+};
+#endif /* defined(CY_DEVICE_PSOC6A2M) */
diff --git a/boot/cypress/scripts/cppcheck-htmlreport.py b/boot/cypress/scripts/cppcheck-htmlreport.py
deleted file mode 100644
index afc7380..0000000
--- a/boot/cypress/scripts/cppcheck-htmlreport.py
+++ /dev/null
@@ -1,696 +0,0 @@
-#! /usr/bin/python3
-
-from __future__ import unicode_literals
-
-import io
-import sys
-import optparse
-import os
-import operator
-
-from collections import Counter
-from pygments import highlight
-from pygments.lexers import guess_lexer_for_filename
-from pygments.formatters import HtmlFormatter
-from xml.sax import parse as xml_parse
-from xml.sax import SAXParseException as XmlParseException
-from xml.sax.handler import ContentHandler as XmlContentHandler
-from xml.sax.saxutils import escape
-"""
-Turns a cppcheck xml file into a browsable html report along
-with syntax highlighted source code.
-"""
-
-STYLE_FILE = """
-body {
- font: 13px Arial, Verdana, Sans-Serif;
- margin: 0;
- width: auto;
-}
-
-h1 {
- margin: 10px;
-}
-
-#footer > p {
- margin: 4px;
-}
-
-.error {
- background-color: #ffb7b7;
-}
-
-.error2 {
- background-color: #faa;
- border: 1px dotted black;
- display: inline-block;
- margin-left: 4px;
-}
-
-.inconclusive {
- background-color: #B6B6B4;
-}
-
-.inconclusive2 {
- background-color: #B6B6B4;
- border: 1px dotted black;
- display: inline-block;
- margin-left: 4px;
-}
-
-div.verbose {
- display: inline-block;
- vertical-align: top;
- cursor: help;
-}
-
-div.verbose div.content {
- display: none;
- position: absolute;
- padding: 10px;
- margin: 4px;
- max-width: 40%;
- white-space: pre-wrap;
- border: 1px solid black;
- background-color: #FFFFCC;
- cursor: auto;
-}
-
-.highlight .hll {
- padding: 1px;
-}
-
-#header {
- border-bottom: thin solid #aaa;
-}
-
-#menu {
- float: left;
- margin-top: 5px;
- text-align: left;
- width: 150px;
- height: 75%;
- position: fixed;
- overflow: auto;
- z-index: 1;
-}
-
-#menu_index {
- float: left;
- margin-top: 5px;
- padding-left: 5px;
- text-align: left;
- width: 200px;
- height: 75%;
- position: fixed;
- overflow: auto;
- z-index: 1;
-}
-
-#menu > a {
- display: block;
- margin-left: 10px;
- font: 12px;
- z-index: 1;
-}
-
-#filename {
- margin-left: 10px;
- font: 12px;
- z-index: 1;
-}
-
-.highlighttable {
- background-color:white;
- z-index: 10;
- position: relative;
- margin: -10 px;
-}
-
-#content {
- background-color: white;
- -webkit-box-sizing: content-box;
- -moz-box-sizing: content-box;
- box-sizing: content-box;
- float: left;
- margin: 5px;
- margin-left: 10px;
- padding: 0 10px 10px 10px;
- width: 80%;
- padding-left: 150px;
-}
-
-#content_index {
- background-color: white;
- -webkit-box-sizing: content-box;
- -moz-box-sizing: content-box;
- box-sizing: content-box;
- float: left;
- margin: 5px;
- margin-left: 10px;
- padding: 0 10px 10px 10px;
- width: 80%;
- padding-left: 200px;
-}
-
-.linenos {
- border-right: thin solid #aaa;
- color: lightgray;
- padding-right: 6px;
-}
-
-#footer {
- border-top: thin solid #aaa;
- clear: both;
- font-size: 90%;
- margin-top: 5px;
-}
-
-#footer ul {
- list-style-type: none;
- padding-left: 0;
-}
-"""
-
-HTML_HEAD = """
-<!DOCTYPE html>
-<html lang="en">
- <head>
- <meta charset="utf-8">
- <title>Cppcheck - HTML report - %s</title>
- <link rel="stylesheet" href="style.css">
- <style>
-%s
- </style>
- <script language="javascript">
- function getStyle(el,styleProp) {
- if (el.currentStyle)
- var y = el.currentStyle[styleProp];
- else if (window.getComputedStyle)
- var y = document.defaultView.getComputedStyle(el,null).getPropertyValue(styleProp);
- return y;
- }
- function toggle() {
- var el = this.expandable_content;
- var mark = this.expandable_marker;
- if (el.style.display == "block") {
- el.style.display = "none";
- mark.innerHTML = "[+]";
- } else {
- el.style.display = "block";
- mark.innerHTML = "[-]";
- }
- }
- function init_expandables() {
- var elts = document.getElementsByClassName("expandable");
- for (var i = 0; i < elts.length; i++) {
- var el = elts[i];
- var clickable = el.getElementsByTagName("span")[0];
- var marker = clickable.getElementsByClassName("marker")[0];
- var content = el.getElementsByClassName("content")[0];
- var width = clickable.clientWidth - parseInt(getStyle(content, "padding-left")) - parseInt(getStyle(content, "padding-right"));
- content.style.width = width + "px";
- clickable.expandable_content = content;
- clickable.expandable_marker = marker;
- clickable.onclick = toggle;
- }
- }
- function set_class_display(c, st) {
- var elements = document.querySelectorAll('.' + c),
- len = elements.length;
- for (i = 0; i < len; i++) {
- elements[i].style.display = st;
- }
- }
- function toggle_class_visibility(id) {
- var box = document.getElementById(id);
- set_class_display(id, box.checked ? '' : 'none');
- }
- </script>
- </head>
- <body onload="init_expandables()">
- <div id="header">
- <h1>Cppcheck report - %s: %s </h1>
- </div>
- <div id="menu" dir="rtl">
- <p id="filename"><a href="index.html">Defects:</a> %s</p>
-"""
-
-HTML_HEAD_END = """
- </div>
- <div id="content">
-"""
-
-HTML_FOOTER = """
- </div>
- <div id="footer">
- <p>
- Cppcheck %s - a tool for static C/C++ code analysis</br>
- </br>
- Internet: <a href="http://cppcheck.net">http://cppcheck.net</a></br>
- IRC: <a href="irc://irc.freenode.net/cppcheck">irc://irc.freenode.net/cppcheck</a></br>
- <p>
- </div>
- </body>
-</html>
-"""
-
-HTML_ERROR = "<span class='error2'><--- %s</span>\n"
-HTML_INCONCLUSIVE = "<span class='inconclusive2'><--- %s</span>\n"
-
-HTML_EXPANDABLE_ERROR = "<div class='verbose expandable'><span class='error2'><--- %s <span class='marker'>[+]</span></span><div class='content'>%s</div></div>\n"""
-HTML_EXPANDABLE_INCONCLUSIVE = "<div class='verbose expandable'><span class='inconclusive2'><--- %s <span class='marker'>[+]</span></span><div class='content'>%s</div></div>\n"""
-
-# escape() and unescape() takes care of &, < and >.
-html_escape_table = {
- '"': """,
- "'": "'"
-}
-html_unescape_table = {v: k for k, v in html_escape_table.items()}
-
-
-def html_escape(text):
- return escape(text, html_escape_table)
-
-
-class AnnotateCodeFormatter(HtmlFormatter):
- errors = []
-
- def wrap(self, source, outfile):
- line_no = 1
- for i, t in HtmlFormatter.wrap(self, source, outfile):
- # If this is a source code line we want to add a span tag at the
- # end.
- if i == 1:
- for error in self.errors:
- if error['line'] == line_no:
- try:
- if error['inconclusive'] == 'true':
- # only print verbose msg if it really differs
- # from actual message
- if error.get('verbose') and (error['verbose'] != error['msg']):
- index = t.rfind('\n')
- t = t[:index] + HTML_EXPANDABLE_INCONCLUSIVE % (error['msg'], html_escape(error['verbose'].replace("\\012", '\n'))) + t[index + 1:]
- else:
- t = t.replace('\n', HTML_INCONCLUSIVE % error['msg'])
- except KeyError:
- if error.get('verbose') and (error['verbose'] != error['msg']):
- index = t.rfind('\n')
- t = t[:index] + HTML_EXPANDABLE_ERROR % (error['msg'], html_escape(error['verbose'].replace("\\012", '\n'))) + t[index + 1:]
- else:
- t = t.replace('\n', HTML_ERROR % error['msg'])
-
- line_no = line_no + 1
- yield i, t
-
-
-class CppCheckHandler(XmlContentHandler):
-
- """Parses the cppcheck xml file and produces a list of all its errors."""
-
- def __init__(self):
- XmlContentHandler.__init__(self)
- self.errors = []
- self.version = '1'
- self.versionCppcheck = ''
-
- def startElement(self, name, attributes):
- if name == 'results':
- self.version = attributes.get('version', self.version)
-
- if self.version == '1':
- self.handleVersion1(name, attributes)
- else:
- self.handleVersion2(name, attributes)
-
- def handleVersion1(self, name, attributes):
- if name != 'error':
- return
-
- self.errors.append({
- 'file': attributes.get('file', ''),
- 'line': int(attributes.get('line', 0)),
- 'locations': [{
- 'file': attributes.get('file', ''),
- 'line': int(attributes.get('line', 0)),
- }],
- 'id': attributes['id'],
- 'severity': attributes['severity'],
- 'msg': attributes['msg']
- })
-
- def handleVersion2(self, name, attributes):
- if name == 'cppcheck':
- self.versionCppcheck = attributes['version']
- if name == 'error':
- error = {
- 'locations': [],
- 'file': '',
- 'line': 0,
- 'id': attributes['id'],
- 'severity': attributes['severity'],
- 'msg': attributes['msg'],
- 'verbose': attributes.get('verbose')
- }
-
- if 'inconclusive' in attributes:
- error['inconclusive'] = attributes['inconclusive']
- if 'cwe' in attributes:
- error['cwe'] = attributes['cwe']
-
- self.errors.append(error)
- elif name == 'location':
- assert self.errors
- error = self.errors[-1]
- locations = error['locations']
- file = attributes['file']
- line = int(attributes['line'])
- if not locations:
- error['file'] = file
- error['line'] = line
- locations.append({
- 'file': file,
- 'line': line,
- 'info': attributes.get('info')
- })
-
-if __name__ == '__main__':
- # Configure all the options this little utility is using.
- parser = optparse.OptionParser()
- parser.add_option('--title', dest='title',
- help='The title of the project.',
- default='[project name]')
- parser.add_option('--file', dest='file',
- help='The cppcheck xml output file to read defects '
- 'from. Default is reading from stdin.')
- parser.add_option('--report-dir', dest='report_dir',
- help='The directory where the HTML report content is '
- 'written.')
- parser.add_option('--source-dir', dest='source_dir',
- help='Base directory where source code files can be '
- 'found.')
- parser.add_option('--source-encoding', dest='source_encoding',
- help='Encoding of source code.', default='utf-8')
-
- # Parse options and make sure that we have an output directory set.
- options, args = parser.parse_args()
-
- try:
- sys.argv[1]
- except IndexError: # no arguments give, print --help
- parser.print_help()
- quit()
-
- if not options.report_dir:
- parser.error('No report directory set.')
-
- # Get the directory where source code files are located.
- source_dir = os.getcwd()
- if options.source_dir:
- source_dir = options.source_dir
-
- # Get the stream that we read cppcheck errors from.
- input_file = sys.stdin
- if options.file:
- if not os.path.exists(options.file):
- parser.error('cppcheck xml file: %s not found.' % options.file)
- input_file = io.open(options.file, 'r')
- else:
- parser.error('No cppcheck xml file specified. (--file=)')
-
- # Parse the xml file and produce a simple list of errors.
- print('Parsing xml report.')
- try:
- contentHandler = CppCheckHandler()
- xml_parse(input_file, contentHandler)
- except XmlParseException as msg:
- print('Failed to parse cppcheck xml file: %s' % msg)
- sys.exit(1)
-
- # We have a list of errors. But now we want to group them on
- # each source code file. Lets create a files dictionary that
- # will contain a list of all the errors in that file. For each
- # file we will also generate a HTML filename to use.
- files = {}
- file_no = 0
- for error in contentHandler.errors:
- filename = error['file']
- if filename not in files.keys():
- files[filename] = {
- 'errors': [], 'htmlfile': str(file_no) + '.html'}
- file_no = file_no + 1
- files[filename]['errors'].append(error)
-
- # Make sure that the report directory is created if it doesn't exist.
- print('Creating %s directory' % options.report_dir)
- if not os.path.exists(options.report_dir):
- os.mkdir(options.report_dir)
-
- # Generate a HTML file with syntax highlighted source code for each
- # file that contains one or more errors.
- print('Processing errors')
-
- decode_errors = []
- for filename, data in sorted(files.items()):
- htmlfile = data['htmlfile']
- errors = []
-
- for error in data['errors']:
- for location in error['locations']:
- if filename == location['file']:
- newError = dict(error)
-
- del newError['locations']
- newError['line'] = location['line']
- if location.get('info'):
- newError['msg'] = location['info']
- newError['severity'] = 'information'
- del newError['verbose']
-
- errors.append(newError)
-
- lines = []
- for error in errors:
- lines.append(error['line'])
-
- if filename == '':
- continue
-
- source_filename = os.path.join(source_dir, filename)
- try:
- with io.open(source_filename, 'r', encoding=options.source_encoding) as input_file:
- content = input_file.read()
- except IOError:
- if (error['id'] == 'unmatchedSuppression'):
- continue # file not found, bail out
- else:
- sys.stderr.write("ERROR: Source file '%s' not found.\n" %
- source_filename)
- continue
- except UnicodeDecodeError:
- sys.stderr.write("WARNING: Unicode decode error in '%s'.\n" %
- source_filename)
- decode_errors.append(source_filename[2:]) # "[2:]" gets rid of "./" at beginning
- continue
-
- htmlFormatter = AnnotateCodeFormatter(linenos=True,
- style='colorful',
- hl_lines=lines,
- lineanchors='line',
- encoding=options.source_encoding)
- htmlFormatter.errors = errors
-
- with io.open(os.path.join(options.report_dir, htmlfile), 'w', encoding='utf-8') as output_file:
- output_file.write(HTML_HEAD %
- (options.title,
- htmlFormatter.get_style_defs('.highlight'),
- options.title,
- filename,
- filename.split('/')[-1]))
-
- for error in sorted(errors, key=lambda k: k['line']):
- output_file.write("<a href='%s#line-%d'> %s %s</a>" % (data['htmlfile'], error['line'], error['id'], error['line']))
-
- output_file.write(HTML_HEAD_END)
- try:
- lexer = guess_lexer_for_filename(source_filename, '')
- except:
- sys.stderr.write("ERROR: Couldn't determine lexer for the file' " + source_filename + " '. Won't be able to syntax highlight this file.")
- output_file.write("\n <tr><td colspan='4'> Could not generated content because pygments failed to retrieve the determine code type.</td></tr>")
- output_file.write("\n <tr><td colspan='4'> Sorry about this.</td></tr>")
- continue
-
- if options.source_encoding:
- lexer.encoding = options.source_encoding
-
- output_file.write(
- highlight(content, lexer, htmlFormatter).decode(
- options.source_encoding))
-
- output_file.write(HTML_FOOTER % contentHandler.versionCppcheck)
-
- print(' ' + filename)
-
- # Generate a master index.html file that will contain a list of
- # all the errors created.
- print('Creating index.html')
-
- with io.open(os.path.join(options.report_dir, 'index.html'),
- 'w') as output_file:
-
- stats_count = 0
- stats = []
- for filename, data in sorted(files.items()):
- for error in data['errors']:
- stats.append(error['id']) # get the stats
- stats_count += 1
-
- counter = Counter(stats)
-
- stat_html = []
- # the following lines sort the stat primary by value (occurrences),
- # but if two IDs occur equally often, then we sort them alphabetically by warning ID
- try:
- cnt_max = counter.most_common()[0][1]
- except IndexError:
- cnt_max = 0
-
- try:
- cnt_min = counter.most_common()[-1][1]
- except IndexError:
- cnt_min = 0
-
- stat_fmt = " <tr><td><input type='checkbox' onclick='toggle_class_visibility(this.id)' id='{}' name='{}' checked></td><td>{}</td><td>{}</td></tr>"
- for occurrences in reversed(range(cnt_min, cnt_max + 1)):
- for _id in [k for k, v in sorted(counter.items()) if v == occurrences]:
- stat_html.append(stat_fmt.format(_id, _id, dict(counter.most_common())[_id], _id))
-
- output_file.write(HTML_HEAD.replace('id="menu" dir="rtl"', 'id="menu_index"', 1).replace("Defects:", "Defect summary;", 1) % (options.title, '', options.title, '', ''))
- output_file.write(' <table>')
- output_file.write(' <tr><th>Show</th><th>#</th><th>Defect ID</th></tr>')
- output_file.write(''.join(stat_html))
- output_file.write(' <tr><td></td><td>' + str(stats_count) + '</td><td>total</td></tr>')
- output_file.write(' </table>')
- output_file.write(' <a href="stats.html">Statistics</a></p>')
- output_file.write(HTML_HEAD_END.replace("content", "content_index", 1))
- output_file.write(' <table>\n')
-
- output_file.write(
- ' <tr><th>Line</th><th>Id</th><th>CWE</th><th>Severity</th><th>Message</th></tr>')
- for filename, data in sorted(files.items()):
- if filename in decode_errors: # don't print a link but a note
- output_file.write("\n <tr><td colspan='4'>%s</td></tr>" % (filename))
- output_file.write("\n <tr><td colspan='4'> Could not generated due to UnicodeDecodeError</td></tr>")
- else:
- if filename.endswith('*'): # assume unmatched suppression
- output_file.write(
- "\n <tr><td colspan='4'>%s</td></tr>" %
- (filename))
- else:
- output_file.write(
- "\n <tr><td colspan='4'><a href='%s'>%s</a></td></tr>" %
- (data['htmlfile'], filename))
-
- for error in sorted(data['errors'], key=lambda k: k['line']):
- error_class = ''
- try:
- if error['inconclusive'] == 'true':
- error_class = 'class="inconclusive"'
- error['severity'] += ", inconcl."
- except KeyError:
- pass
-
- try:
- if error['cwe']:
- cwe_url = "<a href='https://cwe.mitre.org/data/definitions/" + error['cwe'] + ".html'>" + error['cwe'] + "</a>"
- except KeyError:
- cwe_url = ""
-
- if error['severity'] == 'error':
- error_class = 'class="error"'
- if error['id'] == 'missingInclude':
- output_file.write(
- '\n <tr class="%s"><td></td><td>%s</td><td></td><td>%s</td><td>%s</td></tr>' %
- (error['id'], error['id'], error['severity'], error['msg']))
- elif (error['id'] == 'unmatchedSuppression') and filename.endswith('*'):
- output_file.write(
- '\n <tr class="%s"><td></td><td>%s</td><td></td><td>%s</td><td %s>%s</td></tr>' %
- (error['id'], error['id'], error['severity'], error_class,
- error['msg']))
- else:
- output_file.write(
- '\n <tr class="%s"><td><a href="%s#line-%d">%d</a></td><td>%s</td><td>%s</td><td>%s</td><td %s>%s</td></tr>' %
- (error['id'], data['htmlfile'], error['line'], error['line'],
- error['id'], cwe_url, error['severity'], error_class,
- error['msg']))
-
- output_file.write('\n </table>')
- output_file.write(HTML_FOOTER % contentHandler.versionCppcheck)
-
- if (decode_errors):
- sys.stderr.write("\nGenerating html failed for the following files: " + ' '.join(decode_errors))
- sys.stderr.write("\nConsider changing source-encoding (for example: \"htmlreport ... --source-encoding=\"iso8859-1\"\"\n")
-
- print('Creating style.css file')
- with io.open(os.path.join(options.report_dir, 'style.css'),
- 'w') as css_file:
- css_file.write(STYLE_FILE)
-
- print("Creating stats.html (statistics)\n")
- stats_countlist = {}
-
- for filename, data in sorted(files.items()):
- if (filename == ''):
- continue
- stats_tmplist = []
- for error in sorted(data['errors'], key=lambda k: k['line']):
- stats_tmplist.append(error['severity'])
-
- stats_countlist[filename] = dict(Counter(stats_tmplist))
-
- # get top ten for each severity
- SEVERITIES = "error", "warning", "portability", "performance", "style", "unusedFunction", "information", "missingInclude", "internal"
-
- with io.open(os.path.join(options.report_dir, 'stats.html'), 'w') as stats_file:
-
- stats_file.write(HTML_HEAD.replace('id="menu" dir="rtl"', 'id="menu_index"', 1).replace("Defects:", "Back to summary", 1) % (options.title, '', options.title, 'Statistics', ''))
- stats_file.write(HTML_HEAD_END.replace("content", "content_index", 1))
-
- for sev in SEVERITIES:
- _sum = 0
- stats_templist = {}
-
- # if the we have an style warning but we are checking for
- # portability, we have to skip it to prevent KeyError
- try:
- for filename in stats_countlist:
- try: # also bail out if we have a file with no sev-results
- _sum += stats_countlist[filename][sev]
- stats_templist[filename] = (int)(stats_countlist[filename][sev]) # file : amount,
- except KeyError:
- continue
- # don't print "0 style" etc, if no style warnings were found
- if (_sum == 0):
- break
- except KeyError:
- continue
- stats_file.write("<p>Top 10 files for " + sev + " severity, total findings: " + str(_sum) + "</br>\n")
-
- # sort, so that the file with the most severities per type is first
- stats_list_sorted = sorted(stats_templist.items(), key=operator.itemgetter(1, 0), reverse=True)
- it = 0
- LENGTH = 0
-
- for i in stats_list_sorted: # printing loop
- # for aesthetics: if it's the first iteration of the loop, get
- # the max length of the number string
- if (it == 0):
- LENGTH = len(str(i[1])) # <- length of longest number, now get the difference and try to make other numbers align to it
-
- stats_file.write(" " * 3 + str(i[1]) + " " * (1 + LENGTH - len(str(i[1]))) + "<a href=\"" + files[i[0]]['htmlfile'] + "\"> " + i[0] + "</a></br>\n")
- it += 1
- if (it == 10): # print only the top 10
- break
- stats_file.write("</p>\n")
-
- print("\nOpen '" + options.report_dir + "/index.html' to see the results.")
diff --git a/boot/cypress/scripts/cppcheck.sh b/boot/cypress/scripts/cppcheck.sh
deleted file mode 100644
index 862b926..0000000
--- a/boot/cypress/scripts/cppcheck.sh
+++ /dev/null
@@ -1,145 +0,0 @@
-#!/bin/bash
-#
-# this must be the first non-commented line in this script. It ensures
-# bash doesn't choke on \r on Windows
-(set -o igncr) 2>/dev/null && set -o igncr; # this comment is needed
-
-#
-# This script does static code analysis using Cppcheck tool
-# Copyright (c) 2019 Cypress Semiconductor.
-#
-
-# It performs Cppcheck code analysis with following inputs
-# 1. CypressBootloader/sources - Code analysis is done on all the sources of CypressBootloader.
-# 2. Additional source files to be analyzed are grabbed from config file that is provided as a first argument to the script.
-# 3. Files to be ignored are grabbed from config file that is provided as a first argument to the script.
-# 4. To ignore a file its name need to be added to the config file with word "ignore" as perfix
-# 5. To add any additional files, apart the files from CypressBootloader/sources, those names need
-# to be added in a config file.
-# Example
-# A). add below entries in cpp_check.dat file
-# ignore cy_bootloader_hw.c
-# file1.c
-# file2.c
-# ignore cy_bootloader_services.c
-# B). invoke cpp_check shell script
-# cpp_check.sh cpp_check.dat
-#
-# Above example performs Cppcheck analysis on CypressBootloader/sources, ignore cy_bootloader_hw.c, file1.c, file2.c and ignores cy_bootloader_services.c
-
-
-app_name="$1"
-platform="$2"
-app_defines="$3"
-app_includes="$4"
-CPP_CHECK_FILES="$5"
-scope="$6"
-buildcfg="$7"
-
-if [[ ${scope} != "" ]]; then
- SCOPE="--enable=${scope}"
-else
- SCOPE=""
-fi
-
-#Retrieve list of files need to be ignored
-while IFS= read -r line
-do
- CPP_CHECK_IGNORE_FILES="$CPP_CHECK_IGNORE_FILES -i $line"
-done < "${app_name}/cppcheck/ignore_files.list"
-
-#Retrieve list of cppcheck directives
-while IFS= read -r line
-do
- CPP_CHECK_SUPPRESS="$CPP_CHECK_SUPPRESS --suppress=$line"
-done < "${app_name}/cppcheck/suppress_types.list"
-
-echo "-------------------------------------------"
-echo "Suppress options:" "$CPP_CHECK_SUPPRESS"
-echo "-------------------------------------------"
-echo "Additional files:" "$CPP_CHECK_FILES"
-echo "-------------------------------------------"
-echo "Ignoring files:" "$CPP_CHECK_IGNORE_FILES"
-echo "-------------------------------------------"
-echo "CppCheck scope of messages defined with option " ${SCOPE}
-echo "-------------------------------------------"
-echo "Run CppCheck for platform" ${platform}
-echo "-------------------------------------------"
-echo "Defines passed to CppCheck:"
-echo ${app_defines}
-echo "-------------------------------------------"
-echo "Include dirs passed to CppCheck:"
-echo ${app_includes}
-echo "-------------------------------------------"
-
-mkdir -p ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_html
-
-dos2unix ${app_name}/cppcheck/suppress_messages.list
-
-#Generate xml file
-cppcheck ${SCOPE} ${CPP_CHECK_SUPPRESS} -D__GNUC__ -D${platform} ${app_defines} ${app_includes} ${CPP_CHECK_FILES} ${CPP_CHECK_IGNORE_FILES} \
- --xml 2> ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.xml
-
-#Generate html file
-python scripts/cppcheck-htmlreport.py --file=${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.xml --report-dir=${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_html --title=${app_name}
-
-cppcheck ${SCOPE} ${CPP_CHECK_SUPPRESS} -D__GNUC__ -D${platform} ${app_defines} ${app_includes} ${CPP_CHECK_FILES} ${CPP_CHECK_IGNORE_FILES} \
- --template="{severity}\n{id}\n{message}\n{file}\n{line}:{column}\n{code}\n" 2> ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full
-
-#Generate csv file
-echo "severity@id@message@file@line" > ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.csv
-while IFS= read -r line
-do
- read -r line2
- read -r line3
- read -r line4
- read -r line5
- line4=$(echo $line4 | sed 's/.*\\cy_mcuboot\\//' | tr '\\' '/')
- if grep -xq "${line}@${line2}@${line3}@${line4}@${line5}" ${app_name}/cppcheck/suppress_messages.list
- then
- :;#suppress current warning
- else
- echo ${line}@${line2}@${line3}@${line4}@${line5}
- fi
- read -r line
- read -r line
- read -r line
-done \
-< ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full \
->>${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.csv
-
-#Generate log file
-while IFS= read -r line
-do
- read -r line2
- read -r line3
- read -r line4
- read -r line5
- line4=$(echo $line4 | sed 's/.*\\cy_mcuboot\\//' | tr '\\' '/')
- if grep -xq "${line}@${line2}@${line3}@${line4}@${line5}" ${app_name}/cppcheck/suppress_messages.list
- then
- read -r line
- read -r line
- read -r line
- else
- echo ${line} : ${line2}
- echo ${line3}
- echo "${line4} (${line5})"
- read -r line
- echo ${line}
- read -r line
- echo ${line}
- read -r line
- echo "-------------------------------------------"
- fi
-done \
-< ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full \
-> ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.log
-
-rm ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.full
-cat ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.log
-
-RC=$(( $(wc -l ${app_name}/cppcheck/results/${platform}/${buildcfg}/cppcheck_report_${scope}.csv | cut -d' ' -f1) -1 ))
-echo "${app_name} CPPCHECK FOR ${platform} KIT FOUND $RC ERRORS"
-
-exit $RC
\ No newline at end of file
diff --git a/boot/cypress/scripts/flashmap.py b/boot/cypress/scripts/flashmap.py
index 339e4c5..0cb0805 100644
--- a/boot/cypress/scripts/flashmap.py
+++ b/boot/cypress/scripts/flashmap.py
@@ -7,33 +7,98 @@
import json
# Supported Platforms
+cm0pCore = {
+ 'cortex-m0+': 'CM0P',
+ 'cm0+': 'CM0P',
+ 'm0+': 'CM0P',
+ 'cortex-m0p': 'CM0P',
+ 'cm0p': 'CM0P',
+ 'm0p': 'CM0P',
+ 'cortex-m0plus': 'CM0P',
+ 'cm0plus': 'CM0P',
+ 'm0plus': 'CM0P'
+}
+
+cm4Core = {
+ 'cortex-m4': 'CM4',
+ 'cm4': 'CM4',
+ 'm4': 'CM4'
+}
+
+cm33Core = {
+ 'cortex-m33': 'CM33',
+ 'cm33': 'CM33',
+ 'm33': 'CM33'
+}
+
+allCores_PSOC_06x = {**cm0pCore, **cm4Core}
+
+common_PSOC_061 = {
+ 'flashAddr': 0x10000000,
+ 'eraseSize': 0x200, # 512 bytes
+ 'smifAddr': 0x18000000,
+ 'smifSize': 0x8000000, # i.e., window size
+ 'VTAlign': 0x400, # Vector Table alignment
+ 'allCores': cm4Core,
+ 'bootCore': 'Cortex-M4',
+ 'appCore': 'Cortex-M4'
+}
+
+common_PSOC_06x = {
+ 'flashAddr': 0x10000000,
+ 'eraseSize': 0x200, # 512 bytes
+ 'smifAddr': 0x18000000,
+ 'smifSize': 0x8000000, # i.e., window size
+ 'VTAlign': 0x400, # Vector Table alignment
+ 'allCores': allCores_PSOC_06x,
+ 'bootCore': 'Cortex-M0+',
+ 'appCore': 'Cortex-M4'
+}
+
platDict = {
- 'PSOC_062_2M': {
- 'flashAddr': 0x10000000,
+ 'PSOC_061_2M': {
'flashSize': 0x200000, # 2 MBytes
- 'eraseSize': 0x200, # 512 bytes
- 'smifAddr': 0x18000000,
- 'smifSize': 0x8000000 # i.e., window size
+ **common_PSOC_061
+ },
+ 'PSOC_061_1M': {
+ 'flashSize': 0x100000, # 1 MByte
+ **common_PSOC_061
+ },
+ 'PSOC_061_512K': {
+ 'flashSize': 0x80000, # 512 KBytes
+ **common_PSOC_061
+ },
+
+ 'PSOC_062_2M': {
+ 'flashSize': 0x200000, # 2 MBytes
+ **common_PSOC_06x
},
'PSOC_062_1M': {
- 'flashAddr': 0x10000000,
'flashSize': 0x100000, # 1 MByte
- 'eraseSize': 0x200, # 512 bytes
- 'smifAddr': 0x18000000,
- 'smifSize': 0x8000000 # i.e., window size
+ **common_PSOC_06x
},
'PSOC_062_512K': {
- 'flashAddr': 0x10000000,
'flashSize': 0x80000, # 512 KBytes
- 'eraseSize': 0x200, # 512 bytes
- 'smifAddr': 0x18000000,
- 'smifSize': 0x8000000 # i.e., window size
+ **common_PSOC_06x
},
+
+ 'PSOC_063_1M': {
+ 'flashSize': 0x100000, # 1 MByte
+ **common_PSOC_06x
+ },
+
'CYW20829': {
'flashSize': 0, # n/a
'smifAddr': 0x60000000,
- 'smifSize': 0x8000000 # i.e., window size
- }
+ 'smifSize': 0x8000000, # i.e., window size
+ 'VTAlign': 0x200, # Vector Table alignment
+ 'allCores': cm33Core,
+ 'bootCore': 'Cortex-M33',
+ 'appCore': 'Cortex-M33',
+ 'bitsPerCnt': False
+ },
+
+
}
# Supported SPI Flash ICs
@@ -115,6 +180,8 @@
self.in_file = ''
self.out_file = ''
self.img_id = None
+ self.policy = None
+ self.set_core = False
usage = 'USAGE:\n' + sys.argv[0] + \
''' -p <platform> -i <flash_map.json> -o <flash_map.h> -d <img_id>
@@ -124,12 +191,15 @@
-p --platform= Target (e.g., PSOC_062_512K)
-i --ifile= JSON flash map file
-o --ofile= C header file to be generated
--d --img_id ID of application to build'''
+-d --img_id ID of application to build
+-c --policy Policy file in JSON format
+-m --core Detect and set Cortex-M CORE
+'''
try:
opts, unused = getopt.getopt(
- sys.argv[1:], 'hi:o:p:d:',
- ['help', 'platform=', 'ifile=', 'ofile=', 'img_id='])
+ sys.argv[1:], 'hi:o:p:d:c:m',
+ ['help', 'platform=', 'ifile=', 'ofile=', 'img_id=', 'policy=', 'core'])
if len(unused) > 0:
print(usage, file=sys.stderr)
sys.exit(1)
@@ -149,6 +219,10 @@
self.out_file = arg
elif opt in ('-d', '--img_id'):
self.img_id = arg
+ elif opt in ('-c', '--policy'):
+ self.policy = arg
+ elif opt in ('-m', '--core'):
+ self.set_core = True
if len(self.in_file) == 0 or len(self.out_file) == 0:
print(usage, file=sys.stderr)
@@ -361,8 +435,9 @@
try:
with open(params.out_file, "w", encoding='UTF-8') as out_f:
out_f.write('/* AUTO-GENERATED FILE, DO NOT EDIT.'
- ' ALL CHANGES WILL BE LOST! */\n')
- out_f.write(f'/* Platform: {params.plat_id} */\n')
+ ' ALL CHANGES WILL BE LOST! */\n\n'
+ '#ifndef CY_FLASH_MAP_H\n#define CY_FLASH_MAP_H\n')
+ out_f.write(f'\n/* Platform: {params.plat_id} */\n')
out_f.write(f'\nstatic struct flash_area {c_array}[] = {{\n')
comma = len(self.areas)
area_count = 0
@@ -383,7 +458,7 @@
'struct flash_area *boot_area_descs[] = {\n')
for area_index in range(area_count):
out_f.write(f' &{c_array}[{area_index}U],\n')
- out_f.write(' NULL\n};\n')
+ out_f.write(' NULL\n};\n\n#endif /* CY_FLASH_MAP_H */\n')
except (FileNotFoundError, OSError):
print('Cannot create', params.out_file, file=sys.stderr)
sys.exit(4)
@@ -411,7 +486,7 @@
def get_bool(obj, attr, def_val=False):
- """Get JSON boolean value (returns def_val if it missing)"""
+ """Get JSON boolean value (returns def_val if it is missing)"""
ret_val = def_val
obj = obj.get(attr)
if obj is not None:
@@ -433,6 +508,21 @@
return ret_val
+def get_str(obj, attr, def_val=None):
+ """Get JSON string value (returns def_val if it is missing)"""
+ ret_val = def_val
+ obj = obj.get(attr)
+ if obj is not None:
+ try:
+ ret_val = str(obj['value'])
+ except KeyError as key:
+ print('Malformed JSON:', key,
+ 'is missing in', "'" + attr + "'",
+ file=sys.stderr)
+ sys.exit(5)
+ return ret_val
+
+
class AddrSize:
"""Bootloader area"""
@@ -514,7 +604,7 @@
slot_sectors_max = 0
all_shared = get_bool(boot_and_upgrade['bootloader'], 'shared_slot')
any_shared = all_shared
-
+ app_core = None
apps_flash_map = [None, ]
for stage in range(2):
@@ -543,6 +633,21 @@
area_list.chk_area(primary_addr, primary_size)
area_list.chk_area(secondary_addr, secondary_size,
primary_addr)
+ if application.get('core') is None:
+ if app_index == 1:
+ app_core = area_list.plat['appCore']
+ elif app_index > 1:
+ print('"core" makes sense only for the 1st app',
+ file=sys.stderr)
+ sys.exit(6)
+ else:
+ app_core = get_str(application, 'core',
+ area_list.plat['appCore'])
+ if app_index == 1:
+ app_core = area_list.plat['allCores'].get(app_core.lower())
+ if app_core is None:
+ print('Unknown "core"', file=sys.stderr)
+ sys.exit(6)
else:
slot_sectors_max = max(
slot_sectors_max,
@@ -577,7 +682,7 @@
file=sys.stderr)
sys.exit(5)
- return app_count, slot_sectors_max, apps_flash_map, any_shared
+ return app_core, app_count, slot_sectors_max, apps_flash_map, any_shared
def main():
@@ -642,9 +747,19 @@
sys.exit(5)
# Fill flash areas
- app_count, slot_sectors_max, apps_flash_map, shared_slot = \
+ app_core, app_count, slot_sectors_max, apps_flash_map, shared_slot = \
process_images(area_list, boot_and_upgrade)
+ cy_img_hdr_size = 0x400
+ app_start = int(apps_flash_map[1].get("primary").get("address"), 0) + cy_img_hdr_size
+
+ if app_start % plat['VTAlign'] != 0:
+ print('Starting address', apps_flash_map[1].get("primary").get("address"),
+ '+', hex(cy_img_hdr_size),
+ 'must be aligned to', hex(plat['VTAlign']),
+ file=sys.stderr)
+ sys.exit(7)
+
slot_sectors_max = max(slot_sectors_max, 32)
if swap_status is not None:
@@ -673,17 +788,19 @@
# Report necessary values back to make
print('# AUTO-GENERATED FILE, DO NOT EDIT. ALL CHANGES WILL BE LOST!')
+ print('BOOTLOADER_SIZE :=', hex(boot.fa_size))
+ if params.set_core:
+ print('CORE :=', plat['allCores'][plat['bootCore'].lower()])
+ print('APP_CORE :=', app_core)
if params.img_id is not None:
- primary_img_start = (apps_flash_map[int(params.img_id)].get("primary")).get("address")
- secondary_img_start = (apps_flash_map[int(params.img_id)].get("secondary")).get("address")
- bootloader_size = (bootloader.get("size")).get("value")
- slot_size = (apps_flash_map[int(params.img_id)].get("primary")).get("size")
+ primary_img_start = apps_flash_map[int(params.img_id)].get("primary").get("address")
+ secondary_img_start = apps_flash_map[int(params.img_id)].get("secondary").get("address")
+ slot_size = apps_flash_map[int(params.img_id)].get("primary").get("size")
print('PRIMARY_IMG_START := ' + primary_img_start)
print('SECONDARY_IMG_START := ' + secondary_img_start)
print('SLOT_SIZE := ' + slot_size)
- print('BOOTLOADER_SIZE := ' + bootloader_size)
else:
print('MCUBOOT_IMAGE_NUMBER :=', app_count)
print('MAX_IMG_SECTORS :=', slot_sectors_max)
diff --git a/boot/cypress/scripts/github_pr_cleaner.py b/boot/cypress/scripts/github_pr_cleaner.py
index be26c07..df221f0 100644
--- a/boot/cypress/scripts/github_pr_cleaner.py
+++ b/boot/cypress/scripts/github_pr_cleaner.py
@@ -6,17 +6,23 @@
shutil.rmtree('../cppcheck')
shutil.rmtree('../coverity')
+shutil.rmtree('../manifests')
remove('../../../.gitlab-ci.yml')
remove('../BlinkyApp/BlinkyApp_CM4_Debug.launch')
remove('../MCUBootApp/MCUBootApp_CM0P_Debug.launch')
remove('../MCUBootApp/MCUBootApp_CYW20829_Debug.launch')
-remove('../cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_single_psvp.json')
-remove('../cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_swap_multi2_psvp.json')
-remove('../cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_single_psvp.json')
-remove('../cy_flash_pal/flash_cyw208xx/flashmap/cyw20829_xip_overwrite_multi2_psvp.json')
+remove('./cppcheck.sh')
remove('./cppcheck-htmlreport.py')
remove('./rbc_policy_and_cert_revision_modify.py')
-remove('../platforms/CYW20829/cyw20829_psvp.h')
+remove('../platforms/BSP/CYW20829/cyw20829_psvp.h')
+remove('../platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_single_psvp.json')
+remove('../platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_swap_multi2_psvp.json')
+remove('../platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_single_psvp.json')
+remove('../platforms/cy_flash_pal/flash_cyw20829/flashmap/cyw20829_xip_overwrite_multi2_psvp.json')
+remove('../platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_single_psvp.json')
+remove('../platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2_psvp.json')
+remove('../platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_single_psvp.json')
+remove('../platforms/cy_flash_pal/flash_cyw20829/flashmap/hw_rollback_prot/cyw20829_xip_overwrite_multi2_psvp.json')
remove(argv[0])
print('Cleanup complete')
diff --git a/boot/cypress/scripts/rbc_policy_and_cert_revision_modify.py b/boot/cypress/scripts/rbc_policy_and_cert_revision_modify.py
deleted file mode 100644
index 7b47634..0000000
--- a/boot/cypress/scripts/rbc_policy_and_cert_revision_modify.py
+++ /dev/null
@@ -1,19 +0,0 @@
-#!/usr/bin/env python
-
-import json
-
-with open("./policy/policy_reprovisioning_secure.json", "r+") as f:
- data = json.load(f)
- data["device_policy"]["flow_control"]["sys_reset_req"]["value"] = True
- f.seek(0)
- json.dump(data, f)
- f.truncate()
- f.close()
-
-with open("./packets/debug_cert.json", "r+") as f:
- data = json.load(f)
- data["device_id"]["revision_id"] = "0x00"
- f.seek(0)
- json.dump(data, f)
- f.truncate()
- f.close()
diff --git a/boot/cypress/toolchains.mk b/boot/cypress/toolchains.mk
index 2e20404..71a8348 100644
--- a/boot/cypress/toolchains.mk
+++ b/boot/cypress/toolchains.mk
@@ -39,7 +39,7 @@
# NOTE: Absolute pathes for now for the sake of development
ifeq ($(HOST_OS), win)
ifeq ($(COMPILER), GCC_ARM)
- TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/ModusToolbox/tools_2.3/gcc
+ TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/ModusToolbox/tools_2.4/gcc
MY_TOOLCHAIN_PATH := $(call get_os_path, $(TOOLCHAIN_PATH))
TOOLCHAIN_PATH := $(MY_TOOLCHAIN_PATH)
GCC_PATH := $(TOOLCHAIN_PATH)