Infineon: Add Direct-XIP feature for CYW20829 devices
diff --git a/.gitignore b/.gitignore
index 0ed0a12..fcb2574 100644
--- a/.gitignore
+++ b/.gitignore
@@ -13,8 +13,10 @@
**/build/**/*
#Eclipse project files
-.cproject
-.project
+*.project
+*.cproject
+.pydevproject
+.settings/
# Compiled python modules.
*.pyc
@@ -30,3 +32,6 @@
/target/
boot/cypress/platforms/memory/memorymap.c
boot/cypress/platforms/memory/memorymap.h
+
+# Visual Studio Code
+.vscode/
\ No newline at end of file
diff --git a/boot/bootutil/include/bootutil/bootutil.h b/boot/bootutil/include/bootutil/bootutil.h
index 4e9fc38..51ec64e 100644
--- a/boot/bootutil/include/bootutil/bootutil.h
+++ b/boot/bootutil/include/bootutil/bootutil.h
@@ -31,6 +31,7 @@
#include <inttypes.h>
#include "bootutil/fault_injection_hardening.h"
#include "bootutil/bootutil_public.h"
+#include "bootutil/image.h"
#ifdef MCUBOOT_ENC_IMAGES_XIP
#include "bootutil/enc_key.h"
@@ -74,6 +75,10 @@
* when attempting to read/write a trailer.
*/
struct image_trailer {
+#if defined(MCUBOOT_DIRECT_XIP)
+ uint8_t image_inactive;
+ uint8_t pad0[BOOT_MAX_ALIGN - 1];
+#endif
uint8_t swap_type;
uint8_t pad1[BOOT_MAX_ALIGN - 1];
uint8_t copy_done;
@@ -86,15 +91,184 @@
uint8_t magic[BOOT_MAGIC_SZ];
};
+typedef enum
+{
+ MCUBOOT_SLOT_STATE_NO_IMAGE = 0,
+ MCUBOOT_SLOT_STATE_ACTIVE,
+ MCUBOOT_SLOT_STATE_PENDING,
+ MCUBOOT_SLOT_STATE_VERIFYING,
+ MCUBOOT_SLOT_STATE_INACTIVE
+} boot_slot_state_t;
+
/* you must have pre-allocated all the entries within this structure */
fih_int boot_go(struct boot_rsp *rsp);
fih_int boot_go_for_image_id(struct boot_rsp *rsp, uint32_t image_id);
+/**
+ * @brief Performs slot validation without performing boot
+ *
+ * @param image_id - Image number, starting from 0
+ *
+ * @param slot_id - Slot index: 0 - primary slot, 1 - secondary slot
+ *
+ * @retval FIH_SUCCESS on success
+ */
+fih_int
+boot_validate_slot_for_image_id(uint32_t image_id, uint32_t slot_id);
+
+/**
+ * @brief Reads image version fields from the image header area
+ *
+ * @param image_id - Image number, starting from 0
+ *
+ * @param slot_id - Slot index: 0 - primary slot, 1 - secondary slot
+ *
+ * @param ver - Version structure output
+ *
+ * @retval 0 on success
+ */
+int
+boot_get_image_version(uint32_t image_id, uint32_t slot_id, struct image_version* ver);
+
+#if defined(MCUBOOT_DIRECT_XIP)
+/**
+ * @brief Marks the slot as inactive.
+ *
+ * @param image_id - Image number, starting from 0.
+ *
+ * @param slot_id - Slot index: 0 - primary slot, 1 - secondary slot.
+ *
+ * @retval 0 on success
+ */
+int
+boot_set_inactive_slot(uint32_t image_id, uint32_t slot_id);
+
+/**
+ * @brief Checks if the slot is inactive.
+ *
+ * @param image_id - Image number, starting from 0.
+ *
+ * @param slot_id - Slot index: 0 - primary slot, 1 - secondary slot.
+ *
+ * @retval 1 The slot is set as inactive
+ * 0 The slot is not set as inactive
+ * -1 On error
+ */
+int
+boot_is_slot_inactive(uint32_t image_id, uint32_t slot_id);
+
+/**
+ * @brief Restores slot from inactive state to make it able to boot.
+ *
+ * @param image_id - Image number, starting from 0
+ *
+ * @param slot_id - Slot index: 0 - primary slot, 1 - secondary slot
+ *
+ * @retval 0 on success
+ *
+ */
+int
+boot_set_pending_slot(uint32_t image_id, uint32_t slot_id);
+
+
+/**
+ * @brief Sets the revert state to the slot. Image will be erased on next reboot
+ *
+ * @param image_id - Image number, starting from 0
+ *
+ * @param slot_id - Slot index: 0 - primary slot, 1 - secondary slot
+ *
+ * @retval 0 on success
+ *
+ */
+int
+boot_set_revert_slot(uint32_t image_id, uint32_t slot_id);
+
+/**
+ * @brief Finds the TLV (Type-Length-Value) metadata information for a specific image and slot.
+ *
+ * Retrieves offset and length information for the requested TLV entry.
+ *
+ * @param image_id Image identifier (starting from 0).
+ *
+ * @param slot_id Slot index (0 for primary slot, 1 for secondary slot).
+ *
+ * @param type TLV type identifier.
+ *
+ * @param len Output pointer for storing TLV length.
+ *
+ * @param off Output pointer for storing TLV offset.
+ *
+ * @retval 0 Success.
+ * @retval Non-zero Error occurred or TLV not found.
+ */
+int
+boot_find_image_tlv_info(uint32_t image_id, uint32_t slot_id, uint16_t type, uint16_t* len, uint32_t* off);
+
+/**
+ * @brief Reads the TLV metadata value from a specified image slot.
+ *
+ * Fetches the actual data associated with the specified TLV type.
+ *
+ * @param image_id Image identifier (starting from 0).
+ *
+ * @param slot_id Slot index (0 for primary slot, 1 for secondary slot).
+ *
+ * @param type TLV type identifier.
+ *
+ * @param buf Buffer pointer to store the retrieved TLV value.
+ *
+ * @param buf_len Length of provided buffer.
+ *
+ * @param read_len Output pointer for storing the actual number of bytes read.
+ *
+ * @retval 0 Success.
+ * @retval Non-zero Error occurred or insufficient buffer length.
+ */
+int
+boot_read_image_tlv_value(uint32_t image_id, uint32_t slot_id, uint16_t type, uint8_t* buf, uint32_t buf_len, uint32_t* read_len);
+
+/**
+ * @brief Retrieves the current state of the specified slot.
+ *
+ * Provides details about the current slot status without image verification.
+ *
+ * @param image_id Image identifier (starting from 0).
+ *
+ * @param slot_id Slot index (0 for primary slot, 1 for secondary slot).
+ *
+ * @param state Output pointer to store the slot state information.
+ *
+ * @retval 0 Success.
+ * @retval Non-zero Error occurred.
+ */
+int
+boot_get_slot_state(uint32_t image_id, uint32_t slot_id, boot_slot_state_t* state);
+
+/**
+ * @brief Retrieves the current state of the specified image slot.
+ *
+ * Provides details about the current status (active, inactive, pending, etc.) of the specified slot.
+ *
+ * @param image_id Image identifier (starting from 0).
+ *
+ * @param slot_id Slot index (0 for primary slot, 1 for secondary slot).
+ *
+ * @param state Output pointer to store the slot state information.
+ *
+ * @retval 0 Success.
+ * @retval Non-zero Error occurred.
+ */
+int
+boot_get_image_state(uint32_t image_id, uint32_t slot_id, boot_slot_state_t* state);
+
+#endif
+
struct boot_loader_state;
void boot_state_clear(struct boot_loader_state *state);
fih_int context_boot_go_flash(struct boot_loader_state *state, struct boot_rsp *rsp);
-#if defined(MCUBOOT_RAM_LOAD)
+#if defined(MCUBOOT_RAM_LOAD) || defined(MCUBOOT_DIRECT_XIP)
fih_int context_boot_go_ram(struct boot_loader_state *state, struct boot_rsp *rsp);
fih_int boot_go_for_image_id_ram(struct boot_rsp *rsp, uint32_t image_id);
#endif
diff --git a/boot/bootutil/include/bootutil/bootutil_public.h b/boot/bootutil/include/bootutil/bootutil_public.h
index 2c303d8..e8e1fb5 100644
--- a/boot/bootutil/include/bootutil/bootutil_public.h
+++ b/boot/bootutil/include/bootutil/bootutil_public.h
@@ -147,6 +147,9 @@
uint8_t copy_done; /* One of the BOOT_FLAG_[...] values. */
uint8_t image_ok; /* One of the BOOT_FLAG_[...] values. */
uint8_t image_num; /* Boot status belongs to this image */
+#if defined(MCUBOOT_DIRECT_XIP)
+ uint8_t image_inactive; /* One of the BOOT_FLAG_[...] values. */
+#endif
};
/**
@@ -230,6 +233,18 @@
*/
uint32_t boot_swap_info_off(const struct flash_area *fap);
+#if defined(MCUBOOT_DIRECT_XIP)
+/**
+ * @brief Get offset of the image invalidation field in the image trailer.
+ *
+ * @param fap Flash are for which offset is determined.
+ *
+ * @retval offset of the image invalidation field.
+ */
+uint32_t
+boot_image_inactive_off(const struct flash_area *fap);
+#endif
+
/**
* @brief Get value of image-ok flag of the image.
*
diff --git a/boot/bootutil/include/bootutil/crypto/aes_ctr.h b/boot/bootutil/include/bootutil/crypto/aes_ctr.h
index 90727f1..5c0796a 100644
--- a/boot/bootutil/include/bootutil/crypto/aes_ctr.h
+++ b/boot/bootutil/include/bootutil/crypto/aes_ctr.h
@@ -137,7 +137,7 @@
}
if (status == PSA_SUCCESS) {
- status = psa_cipher_finish(&ctx->operation, c + out_sz, sizeof(mlen) - out_sz, &f_sz);
+ status = psa_cipher_finish(&ctx->operation, c + out_sz, mlen - out_sz, &f_sz);
}
if ((status != PSA_SUCCESS) || ((out_sz + f_sz) != mlen)) {
@@ -168,7 +168,7 @@
}
if (status == PSA_SUCCESS) {
- status = psa_cipher_finish(&ctx->operation, m + out_sz, sizeof(clen) - out_sz, &f_sz);
+ status = psa_cipher_finish(&ctx->operation, m + out_sz, clen - out_sz, &f_sz);
}
if ((status != PSA_SUCCESS) || ((out_sz + f_sz) != clen)) {
diff --git a/boot/bootutil/include/bootutil/security_cnt.h b/boot/bootutil/include/bootutil/security_cnt.h
index 515041e..d66c296 100644
--- a/boot/bootutil/include/bootutil/security_cnt.h
+++ b/boot/bootutil/include/bootutil/security_cnt.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2020, Arm Limited. All rights reserved.
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/bootutil/src/bootutil_priv.h b/boot/bootutil/src/bootutil_priv.h
index 04c61f9..97841c3 100644
--- a/boot/bootutil/src/bootutil_priv.h
+++ b/boot/bootutil/src/bootutil_priv.h
@@ -266,6 +266,7 @@
#elif defined(MCUBOOT_DIRECT_XIP_REVERT)
/* Swap status for the active slot */
struct boot_swap_state swap_state;
+ bool slot_validated[BOOT_NUM_SLOTS];
#endif
} slot_usage[BOOT_IMAGE_NUMBER];
#endif /* MCUBOOT_DIRECT_XIP || MCUBOOT_RAM_LOAD */
@@ -290,6 +291,9 @@
int boot_write_swap_info(const struct flash_area *fap, uint8_t swap_type,
uint8_t image_num);
int boot_write_swap_size(const struct flash_area *fap, uint32_t swap_size);
+int boot_write_image_inv(const struct flash_area *fap);
+int boot_read_copy_done(const struct flash_area *fap, uint8_t *copy_done);
+int boot_read_image_inactive(const struct flash_area *fap, uint8_t *image_inactive);
int boot_write_trailer(const struct flash_area *fap, uint32_t off,
const uint8_t *inbuf, uint8_t inlen);
int boot_write_trailer_flag(const struct flash_area *fap, uint32_t off,
diff --git a/boot/bootutil/src/bootutil_public.c b/boot/bootutil/src/bootutil_public.c
index 38b2bd1..c1af9a5 100644
--- a/boot/bootutil/src/bootutil_public.c
+++ b/boot/bootutil/src/bootutil_public.c
@@ -143,7 +143,7 @@
}
#endif /* !MCUBOOT_SWAP_USING_STATUS */
-static int
+int
boot_flag_decode(uint8_t flag)
{
if (flag != BOOT_FLAG_SET) {
@@ -160,7 +160,7 @@
return ALIGN_DOWN(boot_magic_off(fap) - BOOT_MAX_ALIGN, BOOT_MAX_ALIGN);
}
-static inline uint32_t
+uint32_t
boot_copy_done_off(const struct flash_area *fap)
{
return boot_image_ok_off(fap) - BOOT_MAX_ALIGN;
@@ -171,6 +171,13 @@
{
return boot_copy_done_off(fap) - BOOT_MAX_ALIGN;
}
+
+uint32_t
+boot_image_inactive_off(const struct flash_area *fap)
+{
+ return boot_swap_info_off(fap) - BOOT_MAX_ALIGN;
+}
+
#endif /* !MCUBOOT_SWAP_USING_STATUS */
/**
@@ -232,16 +239,35 @@
static int
boot_read_flag(const struct flash_area *fap, uint8_t *flag, uint32_t off)
{
+ uint8_t buf[BOOT_MAX_ALIGN];
int rc;
- rc = flash_area_read(fap, off, flag, sizeof *flag);
+ rc = flash_area_read(fap, off, buf, BOOT_MAX_ALIGN);
+
if (rc != 0) {
return BOOT_EFLASH;
}
- if (*flag == flash_area_erased_val(fap)) {
+
+ if (bootutil_buffer_is_erased(fap, buf, BOOT_MAX_ALIGN))
+ {
*flag = BOOT_FLAG_UNSET;
- } else {
- *flag = boot_flag_decode(*flag);
+ }
+ else
+ {
+ bool erased = bootutil_buffer_is_erased(fap, buf+1U, BOOT_MAX_ALIGN-1U);
+
+ if ((*buf == BOOT_FLAG_SET) && erased)
+ {
+ *flag = BOOT_FLAG_SET;
+ }
+ else if ((*buf != BOOT_FLAG_SET) && erased)
+ {
+ *flag = BOOT_FLAG_BAD;
+ }
+ else
+ {
+ *flag = BOOT_FLAG_UNSET;
+ }
}
return 0;
@@ -249,12 +275,27 @@
#ifndef MCUBOOT_SWAP_USING_STATUS
-static inline int
+int
boot_read_copy_done(const struct flash_area *fap, uint8_t *copy_done)
{
return boot_read_flag(fap, copy_done, boot_copy_done_off(fap));
}
+int
+boot_read_image_inactive(const struct flash_area *fap, uint8_t *image_inactive)
+{
+ return boot_read_flag(fap, image_inactive, boot_image_inactive_off(fap));
+}
+
+int
+boot_write_image_inv(const struct flash_area *fap)
+{
+ uint32_t off;
+
+ off = boot_image_inactive_off(fap);
+
+ return boot_write_trailer_flag(fap, off, BOOT_FLAG_SET);
+}
int
boot_read_swap_state(const struct flash_area *fap,
@@ -297,6 +338,13 @@
return BOOT_EFLASH;
}
+#if defined(MCUBOOT_DIRECT_XIP)
+ rc = boot_read_image_inactive(fap, &state->image_inactive);
+ if (rc != 0) {
+ return BOOT_EFLASH;
+ }
+#endif
+
return boot_read_image_ok(fap, &state->image_ok);
}
@@ -406,14 +454,8 @@
uint8_t erased_val;
uint32_t align;
int rc;
-
- align = flash_area_align(fap);
-
- if (align == 0u) {
- return BOOT_EFLASH;
- }
- align = ALIGN_UP(inlen, align);
+ align = ALIGN_UP(inlen, BOOT_MAX_ALIGN);
if (align > BOOT_MAX_ALIGN) {
return -1;
}
diff --git a/boot/bootutil/src/crc32c.c b/boot/bootutil/src/crc32c.c
index d298a1f..dd0ccb2 100644
--- a/boot/bootutil/src/crc32c.c
+++ b/boot/bootutil/src/crc32c.c
@@ -1,7 +1,7 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
- * Copyright (c) 2020 Cypress Semiconductors
+ * Copyright (c) 2025 Cypress Semiconductors
*
* Original license:
*
diff --git a/boot/bootutil/src/crc32c.h b/boot/bootutil/src/crc32c.h
index 3a45663..ca48dd7 100644
--- a/boot/bootutil/src/crc32c.h
+++ b/boot/bootutil/src/crc32c.h
@@ -1,7 +1,7 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
- * Copyright (c) 2020 Cypress Semiconductors
+ * Copyright (c) 2025 Cypress Semiconductors
*
* Original license:
*
diff --git a/boot/bootutil/src/encrypted.c b/boot/bootutil/src/encrypted.c
index 6d37ecb..322d71b 100644
--- a/boot/bootutil/src/encrypted.c
+++ b/boot/bootutil/src/encrypted.c
@@ -202,12 +202,12 @@
}
#if !defined(MCUBOOT_USE_PSA_CRYPTO)
- if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
- memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
+ if (alg.len != sizeof(ec_pubkey_oid) - 1 ||
+ memcmp(alg.p, ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
return -6;
}
- if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
- memcmp(param.MBEDTLS_CONTEXT_MEMBER(p), ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
+ if (param.len != sizeof(ec_secp256r1_oid) - 1 ||
+ memcmp(param.p, ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
return -7;
}
#endif
@@ -283,8 +283,8 @@
}
#if !defined(MCUBOOT_USE_PSA_CRYPTO)
- if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
- memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
+ if (alg.len != sizeof(ec_pubkey_oid) - 1 ||
+ memcmp(alg.p, ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
return -5;
}
#endif
diff --git a/boot/bootutil/src/image_ec256.c b/boot/bootutil/src/image_ec256.c
index 4d67063..07172e6 100644
--- a/boot/bootutil/src/image_ec256.c
+++ b/boot/bootutil/src/image_ec256.c
@@ -70,33 +70,35 @@
if (mbedtls_asn1_get_alg(p, end, &alg, ¶m)) {
return -2;
}
- if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
- memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
+
+ else if (alg.len != sizeof(ec_pubkey_oid) - 1 ||
+ memcmp(alg.p, ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
return -3;
}
- if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
- memcmp(param.MBEDTLS_CONTEXT_MEMBER(p), ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
+
+ else if (param.len != sizeof(ec_secp256r1_oid) - 1 ||
+ memcmp(param.p, ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
return -4;
}
- if (mbedtls_ecp_group_load(&ctx->MBEDTLS_CONTEXT_MEMBER(grp), MBEDTLS_ECP_DP_SECP256R1)) {
+ else if (mbedtls_ecp_group_load(&ctx->MBEDTLS_CONTEXT_MEMBER(grp), MBEDTLS_ECP_DP_SECP256R1)) {
return -5;
}
- if (mbedtls_asn1_get_bitstring_null(p, end, &len)) {
+ else if (mbedtls_asn1_get_bitstring_null(p, end, &len)) {
return -6;
}
- if (*p + len != end) {
+ else if (*p + len != end) {
return -7;
}
- if (mbedtls_ecp_point_read_binary(&ctx->MBEDTLS_CONTEXT_MEMBER(grp),
+ else if (mbedtls_ecp_point_read_binary(&ctx->MBEDTLS_CONTEXT_MEMBER(grp),
&ctx->MBEDTLS_CONTEXT_MEMBER(Q),
*p, end - *p)) {
return -8;
}
- if (mbedtls_ecp_check_pubkey(&ctx->MBEDTLS_CONTEXT_MEMBER(grp),
+ else if (mbedtls_ecp_check_pubkey(&ctx->MBEDTLS_CONTEXT_MEMBER(grp),
&ctx->MBEDTLS_CONTEXT_MEMBER(Q))) {
return -9;
}
@@ -120,17 +122,28 @@
if (mbedtls_asn1_get_alg(cp, end, &alg, ¶m)) {
return -2;
}
-
- if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
- memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
+#ifdef PSE84
+ /* id-ecPublicKey (RFC5480) */
+ if (alg.len != sizeof(ec_pubkey_oid) - 1 ||
+ memcmp(alg.p, ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
return -3;
}
/* namedCurve (RFC5480) */
- if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
- memcmp(param.MBEDTLS_CONTEXT_MEMBER(p), ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
+ if (param.len != sizeof(ec_secp256r1_oid) - 1 ||
+ memcmp(param.p, ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
return -4;
}
-
+#else
+ if (alg.len != sizeof(ec_pubkey_oid) - 1 ||
+ memcmp(alg.p, ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
+ return -3;
+ }
+ /* namedCurve (RFC5480) */
+ if (param.len != sizeof(ec_secp256r1_oid) - 1 ||
+ memcmp(param.p, ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
+ return -4;
+ }
+#endif
/* ECPoint (RFC5480) */
if (mbedtls_asn1_get_bitstring_null(cp, end, &len)) {
return -6;
diff --git a/boot/bootutil/src/image_ed25519.c b/boot/bootutil/src/image_ed25519.c
index 47fd5ba..2eb2774 100644
--- a/boot/bootutil/src/image_ed25519.c
+++ b/boot/bootutil/src/image_ed25519.c
@@ -45,8 +45,8 @@
return -2;
}
- if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ed25519_pubkey_oid) - 1 ||
- memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ed25519_pubkey_oid, sizeof(ed25519_pubkey_oid) - 1)) {
+ if (alg.len != sizeof(ed25519_pubkey_oid) - 1 ||
+ memcmp(alg.p, ed25519_pubkey_oid, sizeof(ed25519_pubkey_oid) - 1)) {
return -3;
}
diff --git a/boot/bootutil/src/image_validate.c b/boot/bootutil/src/image_validate.c
index 79dc2fd..e95ce61 100644
--- a/boot/bootutil/src/image_validate.c
+++ b/boot/bootutil/src/image_validate.c
@@ -4,7 +4,7 @@
* Copyright (c) 2017-2019 Linaro LTD
* Copyright (c) 2016-2019 JUUL Labs
* Copyright (c) 2019-2020 Arm Limited
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Original license:
*
diff --git a/boot/bootutil/src/loader.c b/boot/bootutil/src/loader.c
index ba5350e..e441b56 100644
--- a/boot/bootutil/src/loader.c
+++ b/boot/bootutil/src/loader.c
@@ -4,6 +4,7 @@
* Copyright (c) 2016-2020 Linaro LTD
* Copyright (c) 2016-2019 JUUL Labs
* Copyright (c) 2019-2021 Arm Limited
+ * Copyright (c) 2021-2025 Cypress Semiconductor Corporation (an Infineon company)
*
* Original license:
*
@@ -241,12 +242,11 @@
}
}
-#if !defined(MCUBOOT_DIRECT_XIP)
/*
* Compute the total size of the given image. Includes the size of
* the TLVs.
*/
-#if !defined(MCUBOOT_OVERWRITE_ONLY) || defined(MCUBOOT_OVERWRITE_ONLY_FAST) || defined(MCUBOOT_RAM_LOAD)
+#if defined(MCUBOOT_DIRECT_XIP) || !defined(MCUBOOT_OVERWRITE_ONLY) || defined(MCUBOOT_OVERWRITE_ONLY_FAST) || defined(MCUBOOT_RAM_LOAD)
static int
boot_read_image_size(struct boot_loader_state *state, int slot, uint32_t *size)
{
@@ -526,7 +526,7 @@
#endif /* MCUBOOT_SWAP_USING_STATUS */
-#endif /* !MCUBOOT_DIRECT_XIP */
+
/*
* Validate image hash/signature and optionally the security counter in a slot.
@@ -558,7 +558,11 @@
/* In the case of ram loading the image has already been decrypted as it is
* decrypted when copied in ram */
#if defined(MCUBOOT_ENC_IMAGES)
+#if defined(MCUBOOT_ENC_IMAGES_XIP_MULTI)
+ if (MUST_DECRYPT(fap, image_index, hdr)) {
+#else
if (MUST_DECRYPT(fap, image_index, hdr) && !IS_RAM_BOOTABLE(hdr)) {
+#endif /* MCUBOOT_ENC_IMAGES_XIP_MULTI */
int rc = flash_area_id_to_multi_image_slot(image_index, fap->fa_id);
if (rc < 0) {
FIH_RET(fih_rc);
@@ -796,7 +800,7 @@
f_off = boot_img_slot_off(state, active_slot);
if (hdr->ih_flags & IMAGE_F_ROM_FIXED && hdr->ih_load_addr != f_off) {
- BOOT_LOG_WRN("Image in %s slot at 0x%" PRIx32
+ BOOT_LOG_DBG("Image in %s slot at 0x%" PRIx32
" has been built for offset 0x%" PRIx32 ", skipping",
active_slot == 0 ? "primary" : "secondary", f_off,
hdr->ih_load_addr);
@@ -839,7 +843,7 @@
hdr = boot_img_hdr(state, slot);
#ifdef MCUBOOT_ENC_IMAGES_XIP_MULTI
-/* In the XIP encryption multi image case if XIP encryption is turned on then
+/* In the XIP encryption multi image case if XIP encryption is turned on then
* the boot_check_header_erased() can't detect erased header correctly for the second and next images
* because erased value is not read as 0xFF.
* So, the bootloader has one option only to detect correctness of image header: it is
@@ -956,6 +960,102 @@
FIH_RET(fih_rc);
}
+/*
+ * Check that there is a valid image in a slot
+ *
+ * @returns
+ * FIH_SUCCESS if image was successfully validated
+ * 1 (or its fih_int encoded form) if no bootloable image was found
+ * FIH_FAILURE on any errors
+ */
+static fih_int
+boot_soft_validate_slot(struct boot_loader_state *state, int slot,
+ struct boot_status *bs)
+{
+ const struct flash_area *fap = NULL;
+ struct image_header *hdr;
+ int area_id;
+ fih_int fih_rc = FIH_FAILURE;
+ int rc;
+
+ area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
+ rc = flash_area_open(area_id, &fap);
+ if (rc != 0) {
+ FIH_RET(fih_rc);
+ }
+
+ BOOT_LOG_DBG("> boot_validate_slot: fa_id = %u", (unsigned)fap->fa_id);
+
+ hdr = boot_img_hdr(state, slot);
+
+ if (hdr->ih_magic != IMAGE_MAGIC) {
+ FIH_RET(fih_rc);
+ }
+
+#if defined(MCUBOOT_OVERWRITE_ONLY) && defined(MCUBOOT_DOWNGRADE_PREVENTION)
+ if (slot != BOOT_PRIMARY_SLOT) {
+ /* Check if version of secondary slot is sufficient */
+ rc = boot_version_cmp(
+ &boot_img_hdr(state, BOOT_SECONDARY_SLOT)->ih_ver,
+ &boot_img_hdr(state, BOOT_PRIMARY_SLOT)->ih_ver);
+ if (rc < 0 && boot_check_header_erased(state, BOOT_PRIMARY_SLOT)) {
+ BOOT_LOG_ERR("insufficient version in secondary slot");
+ fih_rc = FIH_SWAP_TYPE_NONE;
+ goto out;
+ }
+ }
+#endif
+ BOOT_HOOK_CALL_FIH(boot_image_check_hook, FIH_INT_INIT(BOOT_HOOK_REGULAR),
+ fih_rc, BOOT_CURR_IMG(state), slot);
+ if (fih_eq(fih_rc, FIH_INT_INIT(BOOT_HOOK_REGULAR)))
+ {
+ FIH_CALL(boot_image_check, fih_rc, state, hdr, fap, bs);
+ }
+ if (!boot_is_header_valid(hdr, fap) || !fih_eq(fih_rc, FIH_SUCCESS)) {
+ if ((slot != BOOT_PRIMARY_SLOT) || ARE_SLOTS_EQUIVALENT()) {
+ BOOT_LOG_DBG(" * Image in the secondary slot is invalid.");
+ }
+#if !defined(__BOOTSIM__)
+ BOOT_LOG_DBG("Image in the %s slot is not valid!",
+ (slot == BOOT_PRIMARY_SLOT) ? "primary" : "secondary");
+#endif
+ fih_rc = FIH_SWAP_TYPE_NONE;
+ goto out;
+ }
+
+#if MCUBOOT_IMAGE_NUMBER > 1 && !defined(MCUBOOT_ENC_IMAGES) && defined(MCUBOOT_VERIFY_IMG_ADDRESS)
+ /* Verify that the image in the secondary slot has a reset address
+ * located in the primary slot. This is done to avoid users incorrectly
+ * overwriting an application written to the incorrect slot.
+ * This feature is only supported by ARM platforms.
+ */
+ if (area_id == FLASH_AREA_IMAGE_SECONDARY(BOOT_CURR_IMG(state))) {
+ const struct flash_area *pri_fa = BOOT_IMG_AREA(state, BOOT_PRIMARY_SLOT);
+ struct image_header *secondary_hdr = boot_img_hdr(state, slot);
+ uint32_t reset_value = 0;
+ uint32_t reset_addr = secondary_hdr->ih_hdr_size + sizeof(reset_value);
+
+ rc = flash_area_read(fap, reset_addr, &reset_value, sizeof(reset_value));
+ if (rc != 0) {
+ fih_rc = FIH_INT_INIT(1);
+ goto out;
+ }
+
+ if (reset_value < pri_fa->fa_off || reset_value> (pri_fa->fa_off + pri_fa->fa_size)) {
+ BOOT_LOG_ERR("Reset address of image in secondary slot is not in the primary slot");
+
+ fih_rc = FIH_INT_INIT(1);
+ goto out;
+ }
+ }
+#endif
+
+out:
+ flash_area_close(fap);
+ BOOT_LOG_DBG("< boot_validate_slot: fa_id = %u", (unsigned)fap->fa_id);
+ FIH_RET(fih_rc);
+}
+
#ifdef MCUBOOT_HW_ROLLBACK_PROT
/**
* Updates the stored security counter value with the image's security counter
@@ -1579,7 +1679,7 @@
switch (BOOT_SWAP_TYPE(state)) {
case BOOT_SWAP_TYPE_TEST:
case BOOT_SWAP_TYPE_PERM:
- /* BOOT_SWAP_TYPE_NONE has been changed to BOOT_SWAP_TYPE_FAIL to avoid
+ /* BOOT_SWAP_TYPE_NONE has been changed to BOOT_SWAP_TYPE_FAIL to avoid
* reversion again after device reset */
BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_FAIL;
break;
@@ -1713,9 +1813,9 @@
*/
for (int idx = 0; idx < BOOT_IMAGE_NUMBER; idx++) {
BOOT_CURR_IMG(state) = idx;
- /*When dependency is not satisfied, the boot_verify_slot_dependencies_flash
+ /*When dependency is not satisfied, the boot_verify_slot_dependencies_flash
changes swap type to BOOT_SWAP_TYPE_REVERT to have ability of reversion of a
- dependent image. That's why BOOT_SWAP_TYPE_REVERT must not be changed to
+ dependent image. That's why BOOT_SWAP_TYPE_REVERT must not be changed to
BOOT_SWAP_TYPE_NONE */
if (BOOT_SWAP_TYPE(state) != BOOT_SWAP_TYPE_REVERT) {
BOOT_SWAP_TYPE(state) = BOOT_SWAP_TYPE_NONE;
@@ -2249,7 +2349,19 @@
continue;
}
#endif
+#else
+ /* Dependency is set and encryption is enabled. In this case we cannot
+ * reread the first image header because it is encrypted
+ */
+#if defined(MCUBOOT_ENC_IMAGES_XIP_MULTI)
+#if BOOT_IMAGE_NUMBER > 1
+ if ((BOOT_CURR_IMG(state) == 0) && (state->img_mask[BOOT_CURR_IMG(state)] == true)) {
+ continue;
+ }
#endif
+#endif /* MCUBOOT_ENC_IMAGES_XIP_MULTI */
+#endif /* !defined(MCUBOOT_DEPENDENCY_CHECK) */
+
#if defined(MCUBOOT_ENC_IMAGES) && (BOOT_IMAGE_NUMBER > 1)
/* The keys used for encryption may no longer be valid (could belong to
* another images). Therefore, mark them as invalid to force their reload
@@ -2410,7 +2522,11 @@
#ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
#if defined(MCUBOOT_RAM_LOAD) /* to fix Rule 14.3 violation */
+#if defined(MCUBOOT_ENC_IMAGES_XIP_MULTI)
+ if (true) {
+#else
if(IS_RAM_BOOTABLE(boot_img_hdr(state, BOOT_PRIMARY_SLOT)) == false) {
+#endif /* MCUBOOT_ENC_IMAGES_XIP_MULTI */
#endif /* defined(MCUBOOT_RAM_LOAD) */
FIH_CALL(boot_validate_slot, fih_rc, state, BOOT_PRIMARY_SLOT, &bs);
if (!fih_eq(fih_rc, FIH_SUCCESS)) {
@@ -2598,8 +2714,18 @@
assert(rc == 0);
}
+#if defined(MCUBOOT_ENC_IMAGES_XIP_MULTI)
+ if (BOOT_CURR_IMG(state) == 0) {
+ SMIF_SET_CRYPTO_MODE(Disable);
+ }
+#endif /* MCUBOOT_ENC_IMAGES_XIP_MULTI */
/* Attempt to read an image header from each slot. */
rc = boot_read_image_headers(state, false, NULL);
+#if defined(MCUBOOT_ENC_IMAGES_XIP_MULTI)
+ if (BOOT_CURR_IMG(state) == 0) {
+ SMIF_SET_CRYPTO_MODE(Enable);
+ }
+#endif /* MCUBOOT_ENC_IMAGES_XIP_MULTI */
if (rc != 0) {
BOOT_LOG_WRN("Failed reading image headers.");
return rc;
@@ -2698,6 +2824,28 @@
#endif
#if defined(MCUBOOT_DIRECT_XIP) && defined(MCUBOOT_DIRECT_XIP_REVERT)
+static int
+boot_get_swap_state(struct boot_loader_state *state, uint32_t active_slot, struct boot_swap_state* active_swap_state)
+{
+ (void)state;
+ int rc = -1;
+
+ const struct flash_area *fap;
+ int fa_id;
+
+ fa_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), active_slot);
+ rc = flash_area_open(fa_id, &fap);
+
+ if (rc == 0)
+ {
+ (void)memset(active_swap_state, 0, sizeof(struct boot_swap_state));
+
+ rc = boot_read_swap_state(fap, active_swap_state);
+ }
+
+ return rc;
+}
+
/**
* Checks whether the active slot of the current image was previously selected
* to run. Erases the image if it was selected but its execution failed,
@@ -2720,52 +2868,67 @@
fa_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), active_slot);
rc = flash_area_open(fa_id, &fap);
- assert(rc == 0);
active_swap_state = &(state->slot_usage[BOOT_CURR_IMG(state)].swap_state);
(void)memset(active_swap_state, 0, sizeof(struct boot_swap_state));
rc = boot_read_swap_state(fap, active_swap_state);
- assert(rc == 0);
- if (active_swap_state->magic != BOOT_MAGIC_GOOD ||
- (active_swap_state->copy_done == BOOT_FLAG_SET &&
- active_swap_state->image_ok != BOOT_FLAG_SET)) {
+ if ((active_swap_state->copy_done == BOOT_FLAG_SET &&
+ active_swap_state->image_ok != BOOT_FLAG_SET)) {
/*
- * A reboot happened without the image being confirmed at
- * runtime or its trailer is corrupted/invalid. Erase the image
- * to prevent it from being selected again on the next reboot.
- */
+ * A reboot happened without the image being confirmed at
+ * runtime or its trailer is corrupted/invalid. Erase the image
+ * to prevent it from being selected again on the next reboot.
+ */
BOOT_LOG_DBG("Erasing faulty image in the %s slot.",
- (active_slot == BOOT_PRIMARY_SLOT) ? "primary" : "secondary");
+ (active_slot == BOOT_PRIMARY_SLOT) ? "primary" : "secondary");
rc = flash_area_erase(fap, 0, flash_area_get_size(fap));
assert(rc == 0);
- flash_area_close(fap);
rc = -1;
} else {
- if (active_swap_state->copy_done != BOOT_FLAG_SET) {
- if (active_swap_state->copy_done == BOOT_FLAG_BAD) {
- BOOT_LOG_DBG("The copy_done flag had an unexpected value. Its "
- "value was neither 'set' nor 'unset', but 'bad'.");
- }
- /*
- * Set the copy_done flag, indicating that the image has been
- * selected to boot. It can be set in advance, before even
- * validating the image, because in case the validation fails, the
- * entire image slot will be erased (including the trailer).
- */
- rc = boot_write_copy_done(fap);
- if (rc != 0) {
- BOOT_LOG_WRN("Failed to set copy_done flag of the image in "
- "the %s slot.", (active_slot == BOOT_PRIMARY_SLOT) ?
- "primary" : "secondary");
- rc = 0;
+ struct image_header *hdr = boot_img_hdr(state, active_slot);
+
+ if (boot_is_header_valid(hdr, fap))
+ {
+ if (active_swap_state->copy_done != BOOT_FLAG_SET) {
+ if (active_swap_state->copy_done == BOOT_FLAG_BAD) {
+ BOOT_LOG_DBG("The copy_done flag had an unexpected value. Its "
+ "value was neither 'set' nor 'unset', but 'bad'.");
+ }
+
+ bool img_ok = (active_swap_state->image_ok == BOOT_FLAG_SET);
+
+ uint32_t off = flash_area_get_size(fap) - BOOT_MAX_ALIGN;
+
+ flash_area_erase(fap, off, BOOT_MAX_ALIGN);
+
+ /*
+ * Set the copy_done flag, indicating that the image has been
+ * selected to boot. It can be set in advance, before even
+ * validating the image, because in case the validation fails, the
+ * entire image slot will be erased (including the trailer).
+ */
+ rc = boot_write_copy_done(fap);
+
+ rc |= boot_write_magic(fap);
+
+ if (img_ok) {
+ rc |= boot_write_image_ok(fap);
+ }
+
+ if (rc != 0) {
+ BOOT_LOG_WRN("Failed to set copy_done flag of the image in "
+ "the %s slot.", (active_slot == BOOT_PRIMARY_SLOT) ?
+ "primary" : "secondary");
+ rc = 0;
+ }
}
}
- flash_area_close(fap);
}
-
+
+ flash_area_close(fap);
return rc;
}
#endif /* MCUBOOT_DIRECT_XIP && MCUBOOT_DIRECT_XIP_REVERT */
@@ -2855,19 +3018,21 @@
* 4. The image is authenticated in RAM.
*/
const struct flash_area *fap_src = NULL;
+ uint32_t tlv_off;
+ int area_id;
+ int rc;
+ uint8_t image_index;
+ uint8_t * ram_dst = (void *)(IMAGE_RAM_BASE + img_dst);
+#if !defined(MCUBOOT_ENC_IMAGES_XIP_MULTI)
struct boot_status bs;
uint32_t blk_off;
- uint32_t tlv_off;
uint32_t blk_sz;
uint32_t bytes_copied = hdr->ih_hdr_size;
uint32_t chunk_sz;
uint32_t max_sz = 1024;
uint16_t idx;
- uint8_t image_index;
uint8_t * cur_dst;
- int area_id;
- int rc;
- uint8_t * ram_dst = (void *)(IMAGE_RAM_BASE + img_dst);
+#endif /* MCUBOOT_ENC_IMAGES_XIP_MULTI */
image_index = BOOT_CURR_IMG(state);
area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
@@ -2883,7 +3048,7 @@
if (rc != 0) {
goto done;
}
-
+#if !defined(MCUBOOT_ENC_IMAGES_XIP_MULTI)
rc = boot_enc_load(BOOT_CURR_ENC(state), image_index, hdr, fap_src, &bs);
if (rc < 0) {
goto done;
@@ -2923,6 +3088,25 @@
bytes_copied += chunk_sz;
}
+#else
+ (void)image_index;
+ /* Special case for the first image because header and TLV are not encrypted */
+ SMIF_CRYPTO_SECTION(Disable) {
+ /* Copy header to RAM */
+ rc = flash_area_read(fap_src, 0, ram_dst, hdr->ih_hdr_size);
+ }
+ if (0 != rc) {
+ goto done;
+ }
+
+ SMIF_CRYPTO_SECTION(Disable) {
+ /* Copy TLV ro RAM */
+ rc = flash_area_read(fap_src, tlv_off, ram_dst + tlv_off, src_sz - tlv_off);
+ }
+ if (0 != rc) {
+ goto done;
+ }
+#endif /* !defined(MCUBOOT_ENC_IMAGES_XIP_MULTI) */
rc = 0;
done:
@@ -3067,7 +3251,17 @@
img_dst = hdr->ih_load_addr;
+#if defined(MCUBOOT_ENC_IMAGES_XIP_MULTI)
+ if (BOOT_CURR_IMG(state) == 0) {
+ SMIF_SET_CRYPTO_MODE(Disable);
+ }
+#endif /* MCUBOOT_ENC_IMAGES_XIP_MULTI */
rc = boot_read_image_size(state, active_slot, &img_sz);
+#if defined(MCUBOOT_ENC_IMAGES_XIP_MULTI)
+ if (BOOT_CURR_IMG(state) == 0) {
+ SMIF_SET_CRYPTO_MODE(Enable);
+ }
+#endif /* MCUBOOT_ENC_IMAGES_XIP_MULTI */
if (rc != 0) {
return rc;
}
@@ -3174,6 +3368,51 @@
return rc;
}
+
+/**
+ * Switch to image in SRAM
+ *
+ * @param state Boot loader status information.
+ * @param slot The flash slot of the image to be erased.
+ *
+ * @return 0 on success; nonzero on failure.
+ */
+static inline int
+boot_switch_to_sram_image(struct boot_loader_state *state, uint32_t slot)
+{
+ int area_id = -1;
+ int rc = -1;
+ struct flash_area *fap = NULL;
+ struct image_header *hdr = NULL;
+
+ (void)state;
+
+ hdr = boot_img_hdr(state, slot);
+ BOOT_LOG_INF("Image %u slot %" PRIu32 " switch to SRAM",
+ (unsigned)BOOT_CURR_IMG(state), slot);
+ area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
+ rc = flash_area_open(area_id, (const struct flash_area **)&fap);
+
+ if (rc == 0) {
+ /* Switch to image SRAM */
+
+ if (IS_RAM_BOOTABLE_SECURE(hdr)) {
+ fap->fa_device_id = INTERNAL_S_SRAM;
+ }
+ else {
+ fap->fa_device_id = INTERNAL_NS_SRAM;
+ }
+
+ if (hdr->ih_load_addr < flash_devices[fap->fa_device_id].address) {
+ return -1;
+ }
+ fap->fa_off = hdr->ih_load_addr - flash_devices[fap->fa_device_id].address;
+ /* Image is already decrepted, so clear encrypted flags in the header */
+ CLEAR_ENCRYPT_FLAGS(hdr);
+ }
+
+ return rc;
+}
#endif /* MCUBOOT_RAM_LOAD */
#if (BOOT_IMAGE_NUMBER > 1)
@@ -3323,6 +3562,141 @@
#endif /* (MCUBOOT_DEPENDENCY_CHECK) */
#endif /* (BOOT_IMAGE_NUMBER > 1) */
+static const uint8_t slot_table[] = {BOOT_PRIMARY_SLOT, BOOT_SECONDARY_SLOT};
+
+/**
+ * Tries to load a slot for all the images with validation.
+ *
+ * @param state Boot loader status information.
+ *
+ * @return 0 on success; nonzero on failure.
+ */
+fih_int
+boot_load_and_validate_images_xip(struct boot_loader_state *state)
+{
+ uint32_t active_slot = NO_ACTIVE_SLOT;
+ int rc = -1;
+ fih_int fih_rc = FIH_FAILURE;
+
+ struct boot_swap_state swap_state[BOOT_NUM_SLOTS];
+
+ /* Go over all the images and try to load one */
+ IMAGES_ITER(BOOT_CURR_IMG(state))
+ {
+#if BOOT_IMAGE_NUMBER > 1
+ if (state->img_mask[BOOT_CURR_IMG(state)]) {
+ continue;
+ }
+#endif
+
+ for (uint32_t i = 0; i < BOOT_NUM_SLOTS; i++) {
+ active_slot = slot_table[i];
+
+ /* Save the number of the active slot. */
+ state->slot_usage[BOOT_CURR_IMG(state)].active_slot = active_slot;
+
+ rc = boot_rom_address_check(state);
+ if (rc != 0) {
+ /* The image is placed in an unsuitable slot. */
+ state->slot_usage[BOOT_CURR_IMG(state)].slot_available[active_slot] = false;
+ state->slot_usage[BOOT_CURR_IMG(state)].active_slot = NO_ACTIVE_SLOT;
+ continue;
+ }
+
+
+ rc = boot_get_swap_state(state, active_slot, &swap_state[i]);
+
+ if (rc == 0) {
+ /* Proceed with inactive state */
+ if (swap_state[i].image_inactive == BOOT_FLAG_SET) {
+ state->slot_usage[BOOT_CURR_IMG(state)].slot_available[active_slot] = false;
+ state->slot_usage[BOOT_CURR_IMG(state)].active_slot = NO_ACTIVE_SLOT;
+
+
+ if (swap_state[i].copy_done == BOOT_FLAG_SET && swap_state[i].image_ok == BOOT_FLAG_SET)
+ {
+ state->slot_usage[BOOT_CURR_IMG(state)].slot_validated[active_slot] = true;
+ }
+ else
+ {
+ FIH_CALL(boot_validate_slot, fih_rc, state, active_slot, NULL);
+ if (fih_eq(fih_rc, FIH_SUCCESS)) {
+ state->slot_usage[BOOT_CURR_IMG(state)].slot_validated[active_slot] = true;
+ }
+ }
+ continue;
+
+ } else {
+ /* Proceed with revert state */
+ if (boot_select_or_erase(state) != 0) {
+ /* The selected image slot has been erased. */
+ state->slot_usage[BOOT_CURR_IMG(state)].slot_available[active_slot] = false;
+ state->slot_usage[BOOT_CURR_IMG(state)].active_slot = NO_ACTIVE_SLOT;
+ continue;
+ }
+ }
+ }
+ }
+
+ active_slot = NO_ACTIVE_SLOT;
+
+ for (int i = 0; i < BOOT_NUM_SLOTS; i++) {
+ if (state->slot_usage[BOOT_CURR_IMG(state)].slot_available[i] == true) {
+ if (swap_state[i].copy_done == BOOT_FLAG_UNSET)
+ {
+ active_slot = i;
+ break;
+ }
+ }
+ }
+
+ if (active_slot == NO_ACTIVE_SLOT)
+ {
+ active_slot = find_slot_with_highest_version(state);
+ }
+
+ if (active_slot != NO_ACTIVE_SLOT)
+ {
+ #ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
+ FIH_CALL(boot_validate_slot, fih_rc, state, active_slot, NULL);
+ #else
+ fih_rc = FIH_SUCCESS;
+ #endif
+
+ if (fih_eq(fih_rc, FIH_SUCCESS)) {
+ state->slot_usage[BOOT_CURR_IMG(state)].slot_validated[active_slot] = true;
+ state->slot_usage[BOOT_CURR_IMG(state)].active_slot = active_slot;
+ }
+ }
+ else
+ {
+ bool dead_state = true;
+ for (int i = 0; i < BOOT_NUM_SLOTS; i++) {
+ if (state->slot_usage[BOOT_CURR_IMG(state)].slot_available[i] == false) {
+ dead_state = false;
+ break;
+ }
+ }
+
+ if (dead_state == false) {
+ for (int i = 0; i < BOOT_NUM_SLOTS; i++) {
+ if (state->slot_usage[BOOT_CURR_IMG(state)].slot_validated[i] == true) {
+ state->slot_usage[BOOT_CURR_IMG(state)].slot_available[i] = true;
+ state->slot_usage[BOOT_CURR_IMG(state)].active_slot = i;
+
+ fih_rc = FIH_SUCCESS;
+
+ break;
+ }
+ }
+ }
+ }
+ }
+
+
+ FIH_RET(fih_rc);
+}
+
/**
* Tries to load a slot for all the images with validation.
*
@@ -3335,9 +3709,7 @@
{
uint32_t active_slot;
int rc;
-#ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
fih_int fih_rc = FIH_FAILURE;
-#endif
/* Go over all the images and try to load one */
IMAGES_ITER(BOOT_CURR_IMG(state)) {
@@ -3351,7 +3723,7 @@
/* A slot is already active, go to next image. */
break;
}
-
+
/* Ram load assumes to find the highest version of available slots
* and load it. Also dependency check feature verifies version
* of first slot of dependent image and assumes to load from the
@@ -3400,6 +3772,12 @@
/* The selected image slot has been erased. */
state->slot_usage[BOOT_CURR_IMG(state)].slot_available[active_slot] = false;
state->slot_usage[BOOT_CURR_IMG(state)].active_slot = NO_ACTIVE_SLOT;
+
+ FIH_CALL(boot_validate_slot, fih_rc, state, active_slot, NULL);
+ if (fih_eq(fih_rc, FIH_SUCCESS)) {
+ state->slot_usage[BOOT_CURR_IMG(state)].slot_validated[active_slot] = true;
+ }
+
continue;
}
#endif /* MCUBOOT_DIRECT_XIP_REVERT */
@@ -3423,9 +3801,14 @@
(unsigned)BOOT_CURR_IMG(state));
FIH_RET(FIH_FAILURE);
}
+
+ if (boot_switch_to_sram_image(state, active_slot) != 0) {
+ FIH_RET(FIH_FAILURE);
+ }
#endif /* MCUBOOT_RAM_LOAD */
#ifdef MCUBOOT_VALIDATE_PRIMARY_SLOT
FIH_CALL(boot_validate_slot, fih_rc, state, active_slot, NULL);
+
if (!fih_eq(fih_rc, FIH_SUCCESS)) {
/* Image is invalid. */
#ifdef MCUBOOT_RAM_LOAD
@@ -3436,10 +3819,10 @@
/* Since active_slot is set BOOT_PRIMARY_SLOT only, then after its deletion
* no sense to check BOOT_SECONDARY_SLOT. So go outside with an error */
BOOT_LOG_ERR("BOOT slot of image %u has been removed from SRAM",
- (unsigned)BOOT_CURR_IMG(state));
+ (unsigned)BOOT_CURR_IMG(state));
FIH_RET(FIH_FAILURE);
}
-#endif
+#endif /* MCUBOOT_VALIDATE_PRIMARY_SLOT */
/* Valid image loaded from a slot, go to next image. */
break;
}
@@ -3508,7 +3891,12 @@
#if (BOOT_IMAGE_NUMBER > 1)
while (true) {
#endif
+
+#if defined(MCUBOOT_DIRECT_XIP)
+ FIH_CALL(boot_load_and_validate_images_xip, fih_rc, state);
+#else
FIH_CALL(boot_load_and_validate_images, fih_rc, state);
+#endif
if (!fih_eq(fih_rc, FIH_SUCCESS)) {
goto out;
}
@@ -3580,7 +3968,11 @@
boot_state_clear(NULL);
+#if defined(MCUBOOT_DIRECT_XIP) || defined(MCUBOOT_RAM_LOAD)
+ FIH_CALL(context_boot_go_ram, fih_rc, &boot_data, rsp);
+#else
FIH_CALL(context_boot_go_flash, fih_rc, &boot_data, rsp);
+#endif
FIH_RET(fih_rc);
}
@@ -3613,7 +4005,7 @@
FIH_RET(fih_rc);
}
-#if defined(MCUBOOT_RAM_LOAD)
+#if defined(MCUBOOT_RAM_LOAD) || defined(MCUBOOT_DIRECT_XIP)
/**
* Prepares the booting process, considering only a single image. This function
* moves images around in flash as appropriate, and tells you what address to
@@ -3661,3 +4053,343 @@
(void)memset(&boot_data, 0, sizeof(struct boot_loader_state));
}
}
+
+fih_int
+context_validate_slot_flash(struct boot_loader_state *state, int image_slot)
+{
+ fih_int fih_rc = FIH_FAILURE;
+
+ struct boot_status bs = {0};
+ int rc = boot_read_image_headers(state, false, &bs);
+
+ if (rc == 0) {
+ FIH_CALL(boot_soft_validate_slot, fih_rc, state, image_slot, &bs);
+ }
+
+ FIH_RET(fih_rc);
+}
+
+/**
+ * Prepares the booting process, considering only a single image. This function
+ * moves images around in flash as appropriate, and tells you what address to
+ * boot from.
+ *
+ * @param rsp On success, indicates how booting should occur.
+ *
+ * @param image_id The image ID to prepare the boot process for.
+ *
+ * @return FIH_SUCCESS on success; nonzero on failure.
+ */
+fih_int
+boot_validate_slot_for_image_id(uint32_t image_id, uint32_t slot_id)
+{
+ fih_int fih_rc = FIH_FAILURE;
+
+ if (image_id >= BOOT_IMAGE_NUMBER) {
+ FIH_RET(FIH_FAILURE);
+ }
+
+#if BOOT_IMAGE_NUMBER > 1
+ (void)memset(&boot_data.img_mask, 1, BOOT_IMAGE_NUMBER);
+ boot_data.img_mask[image_id] = 0;
+#endif
+
+ FIH_CALL(context_validate_slot_flash, fih_rc, &boot_data, slot_id);
+ FIH_RET(fih_rc);
+}
+
+int boot_get_image_version(uint32_t image_id, uint32_t slot_id, struct image_version *image_version)
+{
+ int rc = -1;
+ struct boot_status bs = {0};
+
+ if (image_id < BOOT_IMAGE_NUMBER) {
+#if BOOT_IMAGE_NUMBER > 1
+ (void)memset(&boot_data.img_mask, 1, BOOT_IMAGE_NUMBER);
+ boot_data.img_mask[image_id] = 0;
+#endif
+
+ if (boot_read_image_headers(&boot_data, false, &bs) == 0) {
+ struct image_header *hdr = boot_img_hdr(&boot_data, slot_id);
+
+ if (hdr->ih_magic == IMAGE_MAGIC) {
+ *image_version = hdr->ih_ver;
+ rc = 0;
+ } else {
+ /* Image magic is not valid - fill with flash area erase value */
+ const struct flash_area *fa = BOOT_IMG_AREA(&boot_data, slot_id);
+ memset(image_version, flash_area_erased_val(fa), sizeof(struct image_version));
+ }
+ }
+ }
+ return rc;
+}
+
+#if defined(MCUBOOT_DIRECT_XIP)
+
+int boot_read_image_header(struct boot_loader_state *state, int slot,
+ struct image_header *out_hdr, struct boot_status *bs)
+{
+ (void) bs;
+ (void) state;
+ const struct flash_area *fap = NULL;
+ int rc = -1;
+ int area_id = flash_area_id_from_multi_image_slot(BOOT_CURR_IMG(state), slot);
+
+ do {
+ rc = flash_area_open(area_id, &fap);
+ if (rc != 0) {
+ rc = BOOT_EFLASH;
+ break;
+ }
+
+ rc = flash_area_read(fap, 0, out_hdr, sizeof *out_hdr);
+ if (rc < 0) {
+ rc = BOOT_EFLASH;
+ break;
+ }
+
+ flash_area_close(fap);
+ } while (false);
+
+ return rc;
+}
+
+int
+boot_set_inactive_slot(uint32_t image_id, uint32_t slot_id)
+{
+ const struct flash_area *fap = NULL;
+ int fa_id = flash_area_id_from_multi_image_slot(image_id, slot_id);
+ int rc = flash_area_open(fa_id, &fap);
+
+ if (rc == 0)
+ {
+ rc = boot_write_image_inv(fap);
+ }
+ flash_area_close(fap);
+
+ return rc;
+}
+
+static
+int boot_read_slot_flag(uint32_t image_id, uint32_t slot_id, int (* fn)(const struct flash_area *, uint8_t *))
+{
+ uint8_t flag = 0U;
+ const struct flash_area *fap = NULL;
+ int fa_id = flash_area_id_from_multi_image_slot(image_id, slot_id);
+ int rc = flash_area_open(fa_id, &fap);
+
+ if (rc == 0)
+ {
+ rc = fn(fap, &flag);
+ }
+
+ if (rc == 0)
+ {
+ rc = -1;
+
+ if (flag == BOOT_FLAG_SET)
+ {
+ rc = 1;
+ }
+ else
+ {
+ rc = 0;
+ }
+ }
+
+ flash_area_close(fap);
+
+ return rc;
+}
+
+int
+boot_is_slot_inactive(uint32_t image_id, uint32_t slot_id)
+{
+ int rc = boot_read_slot_flag(image_id, slot_id, &boot_read_image_inactive);
+
+ return rc;
+}
+
+int
+boot_is_slot_booted(uint32_t image_id, uint32_t slot_id)
+{
+ int rc = boot_read_slot_flag(image_id, slot_id, &boot_read_copy_done);
+
+ return rc;
+}
+
+int
+boot_is_slot_confirmed(uint32_t image_id, uint32_t slot_id)
+{
+ int rc = boot_read_slot_flag(image_id, slot_id, &boot_read_image_ok);
+
+ return rc;
+}
+
+int
+boot_set_pending_slot(uint32_t image_id, uint32_t slot_id)
+{
+ const struct flash_area *fap = NULL;
+ int fa_id = flash_area_id_from_multi_image_slot(image_id, slot_id);
+ int rc = flash_area_open(fa_id, &fap);
+
+ uint32_t off;
+
+ off = boot_image_inactive_off(fap);
+
+ if (rc == 0)
+ {
+ rc = flash_area_erase(fap, off, BOOT_MAX_ALIGN);
+ }
+ flash_area_close(fap);
+
+ return rc;
+}
+
+int
+boot_set_revert_slot(uint32_t image_id, uint32_t slot_id)
+{
+ int rc = boot_set_pending_slot(image_id, slot_id);
+
+ if (rc == 0)
+ {
+ const struct flash_area *fap = NULL;
+ int fa_id = flash_area_id_from_multi_image_slot(image_id, slot_id);
+
+ rc = flash_area_open(fa_id, &fap);
+
+ if (rc == 0)
+ {
+ rc = boot_write_copy_done(fap);
+ }
+
+ flash_area_close(fap);
+ }
+
+ return rc;
+}
+
+int
+boot_find_image_tlv_info(uint32_t image_id, uint32_t slot_id, uint16_t type, uint16_t* len, uint32_t* off)
+{
+ struct boot_loader_state *state = &boot_data;
+ struct boot_status bs = {0};
+ struct image_tlv_iter it = {0};
+ int rc = -1;
+
+ if (image_id < BOOT_IMAGE_NUMBER) {
+#if BOOT_IMAGE_NUMBER > 1
+ (void)memset(state->img_mask, 1, BOOT_IMAGE_NUMBER);
+ state->img_mask[image_id] = 0;
+#endif
+ if (boot_read_image_headers(state, false, &bs) == 0) {
+ int area_id = flash_area_id_from_multi_image_slot(image_id, slot_id);
+ struct image_header* hdr = boot_img_hdr(state, slot_id);
+ const struct flash_area *fap = NULL;
+
+ rc = flash_area_open(area_id, &fap);
+
+ if (rc == 0)
+ {
+ rc = bootutil_tlv_iter_begin(&it, hdr, fap, type, false);
+ }
+
+ if (rc == 0)
+ {
+ rc = bootutil_tlv_iter_next(&it, off, len, NULL);
+ }
+
+ flash_area_close(fap);
+ }
+ }
+
+ return rc;
+}
+
+int boot_read_image_tlv_value(uint32_t image_id, uint32_t slot_id, uint16_t type, uint8_t *buf, uint32_t buf_len, uint32_t *read_len)
+{
+ int rc = -1;
+
+ uint16_t tlv_len = 0;
+ uint32_t tlv_off = 0;
+ uint32_t tmp_len = 0;
+
+ if (buf != NULL && buf_len > 0U) {
+ rc = boot_find_image_tlv_info(image_id, slot_id, type, &tlv_len, &tlv_off);
+
+ if (rc == 0) {
+ int area_id = flash_area_id_from_multi_image_slot(image_id, slot_id);
+ const struct flash_area *fap = NULL;
+
+ tmp_len = tlv_len;
+
+ if (tlv_len > buf_len) {
+ tmp_len = buf_len;
+ }
+
+ rc = flash_area_open(area_id, &fap);
+
+ if (rc == 0) {
+ rc = flash_area_read(fap, tlv_off, buf, tmp_len);
+ }
+
+ if (rc == 0) {
+ if (read_len != NULL) {
+ *read_len = tmp_len;
+ }
+ }
+
+ flash_area_close(fap);
+ }
+ }
+
+ return rc;
+}
+
+int
+boot_get_slot_state(uint32_t image_id, uint32_t slot_id, boot_slot_state_t* state)
+{
+ int rc = 0;
+
+ if (boot_is_slot_inactive(image_id, slot_id) == 1)
+ {
+ *state = MCUBOOT_SLOT_STATE_INACTIVE;
+ }
+ else if ((boot_is_slot_booted(image_id, slot_id) == 1) && (boot_is_slot_confirmed(image_id, slot_id) == 0))
+ {
+ *state = MCUBOOT_SLOT_STATE_VERIFYING;
+ }
+ else if (boot_is_slot_booted(image_id, slot_id) == 0)
+ {
+ *state = MCUBOOT_SLOT_STATE_PENDING;
+ }
+ else if ((boot_is_slot_booted(image_id, slot_id) == 1) && (boot_is_slot_confirmed(image_id, slot_id) == 1))
+ {
+ *state = MCUBOOT_SLOT_STATE_ACTIVE;
+ }
+
+ return rc;
+}
+
+int
+boot_get_image_state(uint32_t image_id, uint32_t slot_id, boot_slot_state_t* state)
+{
+ int rc = -1;
+ fih_int fih_rc;
+
+ FIH_CALL(boot_validate_slot_for_image_id, fih_rc, image_id, slot_id);
+
+ if (fih_eq(fih_rc, FIH_SUCCESS)) {
+ rc = boot_get_slot_state(image_id, slot_id, state);
+ }
+ else
+ {
+ rc = 0;
+ *state = MCUBOOT_SLOT_STATE_NO_IMAGE;
+ }
+
+ return rc;
+}
+
+#endif
diff --git a/boot/bootutil/src/swap_scratch.c b/boot/bootutil/src/swap_scratch.c
index 8b55d2a..000f4df 100644
--- a/boot/bootutil/src/swap_scratch.c
+++ b/boot/bootutil/src/swap_scratch.c
@@ -33,7 +33,7 @@
BOOT_LOG_MODULE_DECLARE(mcuboot);
-#ifndef MCUBOOT_SWAP_USING_MOVE
+#if !defined(MCUBOOT_SWAP_USING_MOVE) && !defined(MCUBOOT_DIRECT_XIP)
#if defined(MCUBOOT_VALIDATE_PRIMARY_SLOT)
/*
diff --git a/boot/bootutil/src/swap_status.c b/boot/bootutil/src/swap_status.c
index d5be7c4..5c40754 100644
--- a/boot/bootutil/src/swap_status.c
+++ b/boot/bootutil/src/swap_status.c
@@ -4,7 +4,7 @@
* Copyright (c) 2017-2019 Linaro LTD
* Copyright (c) 2016-2019 JUUL Labs
* Copyright (c) 2019-2020 Arm Limited
- * Copyright (c) 2020 Cypress Semiconductors
+ * Copyright (c) 2025 Cypress Semiconductors
*
* Original license:
*
diff --git a/boot/bootutil/src/swap_status.h b/boot/bootutil/src/swap_status.h
index 9cc8362..ee8ce9b 100644
--- a/boot/bootutil/src/swap_status.h
+++ b/boot/bootutil/src/swap_status.h
@@ -4,7 +4,7 @@
* Copyright (c) 2017-2019 Linaro LTD
* Copyright (c) 2016-2019 JUUL Labs
* Copyright (c) 2019-2020 Arm Limited
- * Copyright (c) 2020 Cypress Semiconductors
+ * Copyright (c) 2025 Cypress Semiconductors
*
* Original license:
*
diff --git a/boot/bootutil/src/swap_status_misc.c b/boot/bootutil/src/swap_status_misc.c
index 2794a6f..aecd353 100644
--- a/boot/bootutil/src/swap_status_misc.c
+++ b/boot/bootutil/src/swap_status_misc.c
@@ -4,7 +4,7 @@
* Copyright (c) 2017-2019 Linaro LTD
* Copyright (c) 2016-2019 JUUL Labs
* Copyright (c) 2019-2020 Arm Limited
- * Copyright (c) 2020 Cypress Semiconductors
+ * Copyright (c) 2025 Cypress Semiconductors
*
* Original license:
*
diff --git a/boot/bootutil/src/swap_status_part.c b/boot/bootutil/src/swap_status_part.c
index 6498787..da516a6 100644
--- a/boot/bootutil/src/swap_status_part.c
+++ b/boot/bootutil/src/swap_status_part.c
@@ -4,7 +4,7 @@
* Copyright (c) 2017-2019 Linaro LTD
* Copyright (c) 2016-2019 JUUL Labs
* Copyright (c) 2019-2020 Arm Limited
- * Copyright (c) 2020 Cypress Semiconductors
+ * Copyright (c) 2025 Cypress Semiconductors
*
* Original license:
*
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.md b/boot/cypress/BlinkyApp/BlinkyApp.md
index 7c7100b..7fec277 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.md
+++ b/boot/cypress/BlinkyApp/BlinkyApp.md
@@ -4,7 +4,7 @@
Implements a simple Blinky LED application to demonstrate the MCUBootApp bootloader application operation for the boot and upgrade processes.
-It is validated and started by MCUBootApp, which is running on the CM0p core of PSoC™ 6 devices, or CM33 core for the CYW20829/CYW89829 devices.
+It is validated and started by MCUBootApp, which is running on the CM0p core of PSoC™ 6 devices, CM7 core for the XMC7100/XMC7200 devices, or CM33 core for the CYW20829/CYW89829 devices.
Functionality:
@@ -57,9 +57,9 @@
Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE**:
- make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.2/gcc
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
- make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 APP_CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1 TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.2/gcc
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=XMC7200 BUILDCFG=Debug FLASH_MAP=platforms/memory/XMC7000/flashmap/xmc7000_overwrite_single.json PLATFORM_CONFIG=platforms/memory/XMC7000/flashmap/xmc7200_platform.json CORE=CM7 APP_CORE=CM7 CORE_ID=0 IMG_TYPE=BOOT IMG_ID=1 TOOLCHAIN_PATH=c:/Users/${USERNAME}/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
The supported platforms:
@@ -173,8 +173,8 @@
- `0x0` - Internal memory.
- `0xff` - External memory.
- `TOOLCHAIN_PATH` - The path to the GCC compiler to use for the build.
- - Example: TOOLCHAIN_PATH=/home/user/ModusToolbox/tools_3.2/gcc
- - Example: TOOLCHAIN_PATH=C:/ModusToolbox/tools_3.2/gcc
+ - Example: TOOLCHAIN_PATH=/opt/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
+ - Example: TOOLCHAIN_PATH=C:/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
Flags are set by pre-build action. Result of pre-build can be found in autogenerated file `BlinkyApp/memorymap.mk`.
@@ -194,7 +194,7 @@
Flags passed to `imgtool` for a signature are defined in the `SIGN_ARGS` variable in BlinkyApp.mk.
-For `CYWxx829` and `XMC7x00` platforms, `cysecuretools` is used for the image signing.
+For `CYWxx829` and `XMC7x00` platforms, `edgeprotecttools` is used for the image signing.
### How to program an application
@@ -204,11 +204,11 @@
Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
-The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in the ModusToolbox™ installation folder `ModusToolbox/tools_3.2/openocd`.
+The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.4\openocd` folder.
-Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION.hex` and `OPENOCD_PATH` paths:
+Open the terminal application and execute the following commands:
- export OPENOCD_PATH=/Applications/ModusToolbox/tools_3.2/openocd
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
-f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
diff --git a/boot/cypress/BlinkyApp/BlinkyApp.mk b/boot/cypress/BlinkyApp/BlinkyApp.mk
index 735989b..27fe673 100644
--- a/boot/cypress/BlinkyApp/BlinkyApp.mk
+++ b/boot/cypress/BlinkyApp/BlinkyApp.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -57,10 +57,19 @@
OUT_CFG := $(OUT_TARGET)/$(BUILDCFG)
# Set build directory for BOOT and UPGRADE images
-ifeq ($(IMG_TYPE), UPGRADE)
- OUT_CFG := $(OUT_CFG)/upgrade
+
+ifeq ($(USE_DIRECT_XIP), 1)
+ ifeq ($(APP_SLOT), 1)
+ OUT_CFG := $(OUT_CFG)/primary
+ else ifeq ($(APP_SLOT), 2)
+ OUT_CFG := $(OUT_CFG)/secondary
+ endif
else
- OUT_CFG := $(OUT_CFG)/boot
+ ifeq ($(IMG_TYPE), UPGRADE)
+ OUT_CFG := $(OUT_CFG)/upgrade
+ else
+ OUT_CFG := $(OUT_CFG)/boot
+ endif
endif
# Set parameters needed for signing
@@ -73,10 +82,10 @@
ifneq ($(FLASH_MAP), )
ifeq ($(FAMILY), CYW20829)
$(CUR_APP_PATH)/memorymap.mk:
- $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -c $(PRJ_DIR)/policy/policy_secure.json -d $(IMG_ID) -c $(PRJ_DIR)/policy/policy_reprovisioning_secure.json > $(CUR_APP_PATH)/memorymap.mk
+ $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -d $(IMG_ID) -k $(CUR_APP_PATH)/memorymap.mk -c $(PRJ_DIR)/policy/policy_reprovisioning_secure.json
else ifeq ($(FAMILY), PSOC6)
$(CUR_APP_PATH)/memorymap.mk:
- $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -d $(IMG_ID) > $(CUR_APP_PATH)/memorymap.mk
+ $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -d $(IMG_ID) -k $(CUR_APP_PATH)/memorymap.mk -m
else
$(CUR_APP_PATH)/memorymap.mk:
$(PYTHON_PATH) scripts/memorymap_rework.py run -p $(PLATFORM_CONFIG) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory -n memorymap -d $(IMG_ID) > $(CUR_APP_PATH)/memorymap.mk
@@ -138,7 +147,9 @@
DEFINES += -DUSER_APP_RAM_SIZE=$(USER_APP_RAM_SIZE)
DEFINES += -DUSER_APP_START=$(USER_APP_START)
DEFINES += -DPRIMARY_IMG_START=$(PRIMARY_IMG_START)
+DEFINES += -DSECONDARY_IMG_START=$(SECONDARY_IMG_START)
DEFINES += -DUSER_APP_SIZE=$(SLOT_SIZE)
+DEFINES += -DAPP_SLOT=$(APP_SLOT)
DEFINES += -DAPP_$(APP_CORE)
DEFINES += -DBOOT_$(APP_CORE)
@@ -203,11 +214,21 @@
# Collect Test Application sources
C_FILES += $(wildcard $(CUR_APP_PATH)/*.c)
-# Set offset for secondary image
-ifeq ($(IMG_TYPE), UPGRADE)
- HEADER_OFFSET := $(SECONDARY_IMG_START)
+
+ifeq ($(USE_DIRECT_XIP), 1)
+ # Set offset for secondary image
+ ifeq ($(APP_SLOT), 2)
+ HEADER_OFFSET := $(SECONDARY_IMG_START)
+ else
+ HEADER_OFFSET := $(PRIMARY_IMG_START)
+ endif
else
- HEADER_OFFSET := $(PRIMARY_IMG_START)
+ # Set offset for secondary image
+ ifeq ($(IMG_TYPE), UPGRADE)
+ HEADER_OFFSET := $(SECONDARY_IMG_START)
+ else
+ HEADER_OFFSET := $(PRIMARY_IMG_START)
+ endif
endif
# Collect all the sources
@@ -233,6 +254,11 @@
endif
endif
+ifeq ($(USE_DIRECT_XIP), 1)
+ C_FILES += $(PRJ_DIR)/platforms/img_confirm/$(FAMILY)/set_img_ok.c
+ INCLUDE_DIRS += $(PRJ_DIR)/platforms/img_confirm
+endif
+
# Overwite path to linker script if custom is required, otherwise default from BSP is used
LINKER_SCRIPT := $(CUR_APP_PATH)/linker/$(APP_NAME).ld
diff --git a/boot/cypress/BlinkyApp/Readme.md b/boot/cypress/BlinkyApp/Readme.md
index 08de778..cc8707e 100644
--- a/boot/cypress/BlinkyApp/Readme.md
+++ b/boot/cypress/BlinkyApp/Readme.md
@@ -44,7 +44,7 @@
The following command will build regular HEX file of a BlinkyApp for BOOT slot. Substitute `PLATFORM=` to a platform name you use in all following commands.
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M BUILDCFG=Debug IMG_TYPE=BOOT FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_single.json
This have following defaults suggested:
@@ -53,59 +53,23 @@
To build UPGRADE image use following command:
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x10000
-
- Note: HEADER_OFFSET=%SLOT_SIZE%
-
-Example command-line for single-image:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT
-
-**Building Multi-Image**
-
-`BlinkyApp` can be built to use in multi-image bootloader configuration.
-
-To get appropriate artifacts to use with multi image MCUBootApp, makefile flag `HEADER_OFFSET=` can be used.
-
-Example usage:
-
-Considering default config:
-
-* first image BOOT (PRIMARY) slot start `0x10018000`
-* slot size `0x10000`
-* second image BOOT (PRIMARY) slot start `0x10038000`
-
-To get appropriate artifact for second image PRIMARY slot run this command:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=BOOT HEADER_OFFSET=0x20000
-
-*Note:* only 2 images are supported at the moment.
+ make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_single.json
**How to build upgrade image for external memory:**
To prepare MCUBootApp for work with external memory please refer to `MCUBootApp/ExternalMemory.md`.
-For build BlinkyApp upgrade image for external memory use command:
+For build BlinkyApp upgrade image for external memory use flashmap with `_smif.json` configuration :
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x7FE8000 ERASED_VALUE=0xff
-
-`HEADER_OFFSET` defines the offset from original boot image address. This one in line above suggests secondary slot will start from `0x18000000`.
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M BUILDCFG=Debug IMG_TYPE=BOOT FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_overwrite_multi_smif.json
`ERASED_VALUE` defines the memory cell contents in erased state. It is `0x00` for PSoC6's internal Flash and `0xff` for S25FL512S.
-In case of using muti-image configuration, upgrade image for second application can be built using next command:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x8028000 ERASED_VALUE=0xff
-
- Note: for S25FL512S block address should be multiple by 0x40000
-
**How to build encrypted upgrade image :**
-To prepare MCUBootApp for work with encrypted upgrade image please refer to `MCUBootApp/Readme.md`.
+To prepare MCUBootApp for work with encrypted upgrade image please refer to `MCUBootApp/README.md`.
-To obtain encrypted upgrade image of BlinkyApp extra flag `ENC_IMG=1` should be passed in command line, for example:
-
- make app APP_NAME=BlinkyApp PLATFORM=PSOC_062_2M IMG_TYPE=UPGRADE HEADER_OFFSET=0x20000 ENC_IMG=1
+To obtain encrypted upgrade image of BlinkyApp extra flag `ENC_IMG=1` should be passed in command line.
This also suggests user already placed corresponding `*.pem` key in `\keys` folder. The key variables are defined in root `Makefile` as `SIGN_KEY_FILE` and `ENC_KEY_FILE`
@@ -146,20 +110,25 @@
When user application programmed in BOOT slot:
===========================
- [BlinkyApp] BlinkyApp v1.0 [CM4]
+ [BlinkyApp] Version: 1.0.0
===========================
- [BlinkyApp] GPIO initialized
- [BlinkyApp] UART initialized
- [BlinkyApp] Retarget I/O set to 115200 baudrate
+ [BlinkyApp] GPIO initialized
+ [BlinkyApp] UART initialized
+ [BlinkyApp] Retarget I/O set to 115200 baudrate
[BlinkyApp] Red led blinks with 1 sec period
+ [BlinkyApp] Image type: BOOT on CM4 core
+ [BlinkyApp] Turn off watchdog timer
When user application programmed in UPRADE slot and upgrade procedure was successful:
===========================
- [BlinkyApp] BlinkyApp v2.0 [+]
+ [BlinkyApp] Version: 1.0.0
===========================
-
- [BlinkyApp] GPIO initialized
- [BlinkyApp] UART initialized
- [BlinkyApp] Retarget I/O set to 115200 baudrate
+ [BlinkyApp] GPIO initialized
+ [BlinkyApp] UART initialized
+ [BlinkyApp] Retarget I/O set to 115200 baudrate
[BlinkyApp] Red led blinks with 0.25 sec period
+ [BlinkyApp] Try to set img_ok to confirm upgrade image
+ [BlinkyApp] SWAP Status : Image OK was set at 0x10027fe8.
+ [BlinkyApp] Image type: UPGRADE on CM4 core
+ [BlinkyApp] Turn off watchdog timer
diff --git a/boot/cypress/BlinkyApp/libs.mk b/boot/cypress/BlinkyApp/libs.mk
index 54bc8d8..c930531 100644
--- a/boot/cypress/BlinkyApp/libs.mk
+++ b/boot/cypress/BlinkyApp/libs.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template.ld
index b7044a7..a423014 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2016-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld
index dea9ce6..dcee795 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM0P_template_xip.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2016-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
@@ -133,7 +133,7 @@
EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o
*cy_sysclk.o *cy_smif_hybrid_sect.o *flash_qspi.o
- *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm0plus.o, *libgcc.a) *(.text)
+ *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm0plus.o, *libgcc.a, *libc.a, *libc_a-memset.o, *libc_a-memcpy-stub.o, *libc.a:memcpy.o, *cyhal_system.o) *(.text)
KEEP(*(.init))
KEEP(*(.fini))
@@ -252,6 +252,10 @@
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
+ *libc.a(.text*)
+ *libc_a-memset.o(.text*)
+ *libc_a-memcpy-stub.o(.text*)
+ *cyhal_system.o(.text*)
*libgcc.a(.text*)
*cy_smif.o(.text*)
*cy_smif_memslot.o(.text*)
@@ -262,6 +266,9 @@
*cy_syslib.o(.text*)
*cy_syslib_ext.o(.text*)
+ KEEP(*libc.a:memset.o(.text*))
+ KEEP(*libc.a:memcpy.o(.text*))
+
__data_end__ = .;
} > ram AT>flash
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld
index 704c3b4..b5e8f70 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM33_template_xip.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright (c) (2020-2025), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template.ld
index 4324012..9c602d0 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
+* Copyright 2016-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
index c99131c..29c99b2 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM4_template_xip.ld
@@ -19,8 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
-* Copyright 2022 Infineon Technologies AG
+* Copyright 2025 Infineon Technologies AG
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -43,7 +42,7 @@
ENTRY(Reset_Handler)
/* Size of the stack section at the end of CM4 SRAM */
-STACK_SIZE = 0x1000;
+STACK_SIZE = 0x2000;
/* The size of the MCU boot header area at the start of FLASH */
BOOT_HEADER_SIZE = 0x400;
@@ -132,7 +131,7 @@
EXCLUDE_FILE(*cy_smif.o *cy_smif_memslot.o *cy_smif_sfdp.o
*cy_sysclk.o *cy_smif_hybrid_sect.o *flash_qspi.o
- *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm4.o *libgcc.a) *(.text)
+ *cy_syslib.o *cy_syslib_ext.o *system_psoc6_cm4.o *libgcc.a, *libc.a, *libc_a-memset.o, *libc_a-memcpy-stub.o, *libc.a:memcpy.o, *cyhal_system.o) *(.text)
KEEP(*(.init))
KEEP(*(.fini))
@@ -251,6 +250,10 @@
KEEP(*(.cy_ramfunc*))
. = ALIGN(4);
+ *libc.a(.text*)
+ *libc_a-memset.o(.text*)
+ *libc_a-memcpy-stub.o(.text*)
+ *cyhal_system.o(.text*)
*libgcc.a(.text*)
*cy_smif.o(.text*)
*cy_smif_memslot.o(.text*)
@@ -261,6 +264,9 @@
*cy_syslib.o(.text*)
*cy_syslib_ext.o(.text*)
+ KEEP(*libc.a:memset.o(.text*))
+ KEEP(*libc.a:memcpy.o(.text*))
+
__data_end__ = .;
} > ram AT>flash
diff --git a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld
index 3767ba8..2a450fa 100644
--- a/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld
+++ b/boot/cypress/BlinkyApp/linker/BlinkyApp_CM7_template.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/BlinkyApp/main.c b/boot/cypress/BlinkyApp/main.c
index 22abb36..8f1a872 100644
--- a/boot/cypress/BlinkyApp/main.c
+++ b/boot/cypress/BlinkyApp/main.c
@@ -1,6 +1,5 @@
/*
- * Copyright (c) 2020 Cypress Semiconductor Corporation
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -25,7 +24,7 @@
#include "platform.h"
-#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
+#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE) || defined(MCUBOOT_DIRECT_XIP)
#include "set_img_ok.h"
#endif
@@ -35,10 +34,10 @@
printf(GREETING_MESSAGE_INFO);
-#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
+#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE) || defined(MCUBOOT_DIRECT_XIP)
int rc = -1;
- printf("[BlinkyApp] Try to set img_ok to confirm upgrade image\r\n");
+ printf("[BlinkyApp] Try to set img_ok to confirm that the image is valid\r\n");
/* Write Image OK flag to the slot trailer, so MCUBoot-loader
* will not revert new image
@@ -51,6 +50,7 @@
printf("[BlinkyApp] SWAP Status : Image OK was set at 0x%08x.\r\n", IMG_OK_ADDR);
} else {
printf("[BlinkyApp] SWAP Status : Failed to set Image OK.\r\n");
+ for (;;);
}
#endif /* !(SWAP_DISABLED) && defined(UPGRADE_IMAGE) */
diff --git a/boot/cypress/BlinkyApp/main.h b/boot/cypress/BlinkyApp/main.h
index 4fafb4e..a9e084c 100644
--- a/boot/cypress/BlinkyApp/main.h
+++ b/boot/cypress/BlinkyApp/main.h
@@ -1,6 +1,6 @@
/*
\copyright
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2017-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/BlinkyApp/platform.h b/boot/cypress/BlinkyApp/platform.h
index b2a0a50..5435d97 100644
--- a/boot/cypress/BlinkyApp/platform.h
+++ b/boot/cypress/BlinkyApp/platform.h
@@ -1,3 +1,23 @@
+/********************************************************************************
+* \copyright
+* (c) 2025, Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
#ifndef PLATFORM_H
#define PLATFORM_H
@@ -28,6 +48,15 @@
#error "[BlinkyApp] Please specify type of image: -DBOOT_IMAGE or -DUPGRADE_IMAGE\r\n"
#endif /* BOOT_IMAGE */
+#if defined(MCUBOOT_DIRECT_XIP)
+ #undef IMAGE_TYPE
+ #if APP_SLOT == 1
+ #define IMAGE_TYPE "Primary slot"
+ #else
+ #define IMAGE_TYPE "Secondary slot"
+ #endif
+#endif
+
#define GREETING_MESSAGE_VER "[BlinkyApp] Version:"
#define WATCHDOG_FREE_MESSAGE "[BlinkyApp] Turn off watchdog timer\r\n"
diff --git a/boot/cypress/CC.mk b/boot/cypress/CC.mk
index 75e97a3..050b12b 100644
--- a/boot/cypress/CC.mk
+++ b/boot/cypress/CC.mk
@@ -1,3 +1,21 @@
+################################################################################
+# \copyright
+# Copyright 2025 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
ASM_FILES :=
C_FILES :=
diff --git a/boot/cypress/MCUBootApp/ExternalMemory.md b/boot/cypress/MCUBootApp/ExternalMemory.md
index 07598cb..72e435f 100644
--- a/boot/cypress/MCUBootApp/ExternalMemory.md
+++ b/boot/cypress/MCUBootApp/ExternalMemory.md
@@ -74,7 +74,7 @@
When XIP mode is used primary slot of an image can be placed in external memory.
-This repository provides default flash map files with suffix _xip_ to be used for XIP mode in `platforms/memory/flash_%platform_name%/flashmap`.
+This repository provides default flash map files with suffix _xip_ to be used for XIP mode in `platforms/memory/<PLATFORM_NAME>/flashmap`.
#### How to enable external memory support
@@ -100,11 +100,11 @@
The MCUBootApp can be programmed similarly to described in the [MCUBootApp.md](MCUBootApp.md) file:
- export OPENOCD=/Applications/ModusToolbox/tools_3.2/openocd
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
- ${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
- -f ${OPENOCD}/scripts/interface/kitprog3.cfg \
- -f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
+ ${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
+ -f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
+ -f ${OPENOCD_PATH}/scripts/target/psoc6_2m.cfg \
-c "init; psoc6 sflash_restrictions 1" \
-c "init; reset init; program PATH_TO_APPLICATION.hex" \
-c "resume; reset; exit"
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.md b/boot/cypress/MCUBootApp/MCUBootApp.md
index 2bdcbaf..883b8a3 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.md
+++ b/boot/cypress/MCUBootApp/MCUBootApp.md
@@ -33,7 +33,7 @@
The flash map of the bootloader is defined at compile-time and cannot be changed dynamically. Flash map is prepared in the industry-accepted JSON (JavaScript Object Notation) format. It should follow the rules described in section **How to modify the flash map**.
-`MCUBootApp` contains JSON templates for flash maps with commonly used configurations. They can be found in `platforms/memory/flash_%platform_name%/flashmap` The slots' sizes are defined per platform to be compatible with all supported device families.
+`MCUBootApp` contains JSON templates for flash maps with commonly used configurations. They can be found in `platforms/memory/<PLATFORM_NAME>/flashmap` The slots' sizes are defined per platform to be compatible with all supported device families.
The actual addresses are provided in corresponding platform doc files:
@@ -641,9 +641,9 @@
Folder `boot/cypress` contains make-files infrastructure for building MCUBootApp bootloader applications. Example build commands are provided later in this document for different build configurations.
-Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ IDE**:
+Toolchain is set by default in `toolchains.mk` file, depending on `COMPILER` makefile variable. MCUBoot is currently support only `GCC_ARM` as compiler. Toolchain path can be redefined, by setting `TOOLCHAIN_PATH` build flag to desired toolchain path. Below is an example on how to set toolchain path from **ModusToolbox™ Programming Tools**:
- make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.2/gcc
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
* Build MCUBootApp in the `Debug` configuration for Single-image mode with swap upgrade.
@@ -741,9 +741,7 @@
1. The direct usage of OpenOCD.
-The OpenOCD package is supplied with ModusToolbox™ IDE and can be found in the installation folder `ModusToolbox/tools_3.2/openocd`.
-
-Set environment variable `OPENOCD` to the path to the openocd folder in ModusToolbox™. Exact commands for programming images are provided in the corresponding platform readme files.
+The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.4\openocd` folder. Commands for programming images are provided in the corresponding platform readme files.
2. Using the GUI tool `Cypress Programmer`
@@ -773,4 +771,4 @@
*Python/Python3* - ensure that you have the correct path referenced in `PATH`.
-*Msys2* - To use the systems path, navigate to the msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, and restart the MSYS2 shell. This will inherit the system's path and find `python` installed in the regular way as well as `imgtool` and its dependencies.
+*Msys2* - To use the systems path, navigate to the msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, and restart the MSYS2 shell. This will inherit the system's path and find `Python` installed in the regular way as well as `imgtool` and its dependencies.
diff --git a/boot/cypress/MCUBootApp/MCUBootApp.mk b/boot/cypress/MCUBootApp/MCUBootApp.mk
index d1c93d1..f8f7ede 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp.mk
+++ b/boot/cypress/MCUBootApp/MCUBootApp.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -43,6 +43,7 @@
FIH_PROFILE_LEVEL_LIST := OFF LOW MEDIUM HIGH
FIH_PROFILE_LEVEL ?= MEDIUM
MCUBOOT_SWAP_STATUS_FAST_BOOT ?= 0
+USE_LOG_TIMESTAMP ?= 1
ifeq ($(BUILDCFG), Release)
MCUBOOT_LOG_LEVEL ?= MCUBOOT_LOG_LEVEL_INFO
@@ -77,10 +78,10 @@
ifeq ($(FAMILY), CYW20829)
$(CUR_APP_PATH)/memorymap.mk:
- $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -c $(PRJ_DIR)/policy/policy_secure.json > $(CUR_APP_PATH)/memorymap.mk
+ $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -c $(APP_DEFAULT_POLICY) -k $(CUR_APP_PATH)/memorymap.mk -n $(OUT_CFG)/$(APP_NAME).signed_nonce.bin
else ifeq ($(FAMILY), PSOC6)
$(CUR_APP_PATH)/memorymap.mk:
- $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h > $(CUR_APP_PATH)/memorymap.mk
+ $(PYTHON_PATH) scripts/memorymap.py -p $(PLATFORM) -m -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory/memorymap.c -a $(PRJ_DIR)/platforms/memory/memorymap.h -k $(CUR_APP_PATH)/memorymap.mk
else
$(CUR_APP_PATH)/memorymap.mk:
$(PYTHON_PATH) scripts/memorymap_rework.py run -p $(PLATFORM_CONFIG) -i $(FLASH_MAP) -o $(PRJ_DIR)/platforms/memory -n memorymap > $(CUR_APP_PATH)/memorymap.mk
@@ -170,6 +171,15 @@
endif
+ifeq ($(MCUBOOT_SKIP_VALIDATE_PRIMARY_SLOT), 1)
+ DEFINES += -DMCUBOOT_SKIP_VALIDATE_PRIMARY_SLOT
+endif
+
+ifeq ($(MCUBOOT_SKIP_VALIDATE), 1)
+ DEFINES += -DMCUBOOT_SKIP_VALIDATE_PRIMARY_SLOT
+ DEFINES += -DMCUBOOT_SKIP_VALIDATE_SECONDARY_SLOT
+endif
+
ifneq ($(MCUBOOT_IMAGE_NUMBER), 1)
ifeq ($(MCUBOOT_DEPENDENCY_CHECK), 1)
DEFINES += -DMCUBOOT_DEPENDENCY_CHECK
@@ -197,15 +207,6 @@
ifeq ($(FAMILY), CYW20829)
DEFINES += -DMCUBOOT_ENC_IMAGES_XIP
endif
-# Use maximum optimization level for PSOC6 encrypted image with
-# external flash so it would fit into 0x18000 size of MCUBootApp
- ifneq ($(FAMILY), CYW20829)
- ifeq ($(BUILDCFG), Debug)
- ifeq ($(USE_EXTERNAL_FLASH), 1)
- CFLAGS_OPTIMIZATION := -Os -g3
- endif
- endif
- endif
endif
ifeq ($(USE_MEASURED_BOOT), 1)
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
index f80e9da..0ecd0b1 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM0P.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
+* Copyright 2016-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld
index 83be8e4..1c2478d 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM33.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
+* Copyright 2016-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld
index 06a074b..e37b4ae 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM4.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
+* Copyright 2016-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/MCUBootApp/MCUBootApp_CM7.ld b/boot/cypress/MCUBootApp/MCUBootApp_CM7.ld
index 6b6de37..b2aa608 100644
--- a/boot/cypress/MCUBootApp/MCUBootApp_CM7.ld
+++ b/boot/cypress/MCUBootApp/MCUBootApp_CM7.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/MCUBootApp/README.md b/boot/cypress/MCUBootApp/README.md
index b58f87e..59e6e87 100644
--- a/boot/cypress/MCUBootApp/README.md
+++ b/boot/cypress/MCUBootApp/README.md
@@ -172,16 +172,18 @@
There are couple ways of programming hex of MCUBootApp and BlinkyApp. Following instructions assume one of Cypress development kits, for example `CY8CPROTO_062_4343W`.
1. Direct usage of OpenOCD.
-OpenOCD package is supplied with ModuToolbox IDE and can be found in installation folder under `./tools_3.2/openocd`.
-Open terminal application - and execute following command after substitution `PATH_TO_APPLICATION.hex` and `OPENOCD` paths.
Connect a board to your computer. Switch Kitprog3 to DAP-BULK mode by pressing `SW3 MODE` button until `LED2 STATUS` constantly shines.
- export OPENOCD=/Applications/ModusToolbox/tools_3.2/openocd
+The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.4\openocd` folder.
- ${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
- -f ${OPENOCD}/scripts/interface/kitprog3.cfg \
- -f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
+Open the terminal application and execute the following commands:
+
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
+
+ ${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
+ -f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
+ -f ${OPENOCD_PATH}/scripts/target/psoc6_2m.cfg \
-c "init; reset init; program PATH_TO_APPLICATION.hex" \
-c "resume; reset; exit"
@@ -209,7 +211,7 @@
* Msys2
Also IDE may be used:
-* Eclipse / ModusToolbox ("makefile project from existing source")
+* Eclipse / ModusToolbox™ ("makefile project from existing source")
*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
@@ -217,5 +219,5 @@
*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
-This will inherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.
+This will inherit system's PATH so should find `Python` installed in regular way as well as imgtool and its dependencies.
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_assert.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_assert.h
index 5c07711..2e55eef 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_assert.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_assert.h
@@ -4,6 +4,25 @@
* Cypress-specific assert() macro redefinition
*
*/
+/********************************************************************************
+* \copyright
+* (c) 2025, Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
#ifndef MCUBOOT_ASSERT_H
#define MCUBOOT_ASSERT_H
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
index 819cd20..59f573e 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_config.h
@@ -1,4 +1,4 @@
-/* Copyright 2019 Cypress Semiconductor Corporation
+/* Copyright 2025 Cypress Semiconductor Corporation
*
* Copyright (c) 2018 Open Source Foundries Limited
*
@@ -48,18 +48,20 @@
* simpler code path, which only supports overwriting the
* existing image with the update image, is also available.
*/
-#ifdef MCUBOOT_OVERWRITE_ONLY
+#if !defined (MCUBOOT_DIRECT_XIP)
+# ifdef MCUBOOT_OVERWRITE_ONLY
/* Uncomment to only erase and overwrite those slot 0 sectors needed
* to install the new image, rather than the entire image slot. */
/* #define MCUBOOT_OVERWRITE_ONLY_FAST */
-#else
+# else
/* Using SWAP w Scratch by default.
* Uncomment which is needed. */
-#define MCUBOOT_SWAP_USING_SCRATCH 1
+# define MCUBOOT_SWAP_USING_SCRATCH 1
/* #define MCUBOOT_SWAP_USING_MOVE 1 */
-#ifdef USE_SWAP_STATUS
-#define MCUBOOT_SWAP_USING_STATUS 1
-#endif
+# ifdef USE_SWAP_STATUS
+# define MCUBOOT_SWAP_USING_STATUS 1
+# endif
+# endif
#endif
/* This definition is used in boot_copy_region function to define
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
index c2d97d8..0389a4a 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_config/mcuboot_logging.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2015 Runtime Inc
- * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h b/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h
index 307c6be..f1217fa 100644
--- a/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h
+++ b/boot/cypress/MCUBootApp/config/mcuboot_crypto_acc_config.h
@@ -1,6 +1,6 @@
/*
* mbed Microcontroller Library
- * Copyright (c) 2019 Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Cypress Semiconductor Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/MCUBootApp/cy_serial_flash_prog.c b/boot/cypress/MCUBootApp/cy_serial_flash_prog.c
index 84197e1..14da828 100644
--- a/boot/cypress/MCUBootApp/cy_serial_flash_prog.c
+++ b/boot/cypress/MCUBootApp/cy_serial_flash_prog.c
@@ -10,7 +10,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2019 Cypress Semiconductor Corporation
+* Copyright 2018-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/MCUBootApp/libs.mk b/boot/cypress/MCUBootApp/libs.mk
index 4be1c07..bbfa77d 100644
--- a/boot/cypress/MCUBootApp/libs.mk
+++ b/boot/cypress/MCUBootApp/libs.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/MCUBootApp/misc/exec_time_check.h b/boot/cypress/MCUBootApp/misc/exec_time_check.h
index 55d71f2..d0f595c 100644
--- a/boot/cypress/MCUBootApp/misc/exec_time_check.h
+++ b/boot/cypress/MCUBootApp/misc/exec_time_check.h
@@ -1,4 +1,4 @@
-/* Copyright 2022, Infineon Technologies AG. All rights reserved.
+/* Copyright 2025, Infineon Technologies AG. All rights reserved.
*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
diff --git a/boot/cypress/MCUBootApp/misc/timebase_us.c b/boot/cypress/MCUBootApp/misc/timebase_us.c
index dfe2ffd..5d4efdc 100644
--- a/boot/cypress/MCUBootApp/misc/timebase_us.c
+++ b/boot/cypress/MCUBootApp/misc/timebase_us.c
@@ -1,4 +1,4 @@
-/* Copyright 2022, Infineon Technologies AG. All rights reserved.
+/* Copyright 2025, Infineon Technologies AG. All rights reserved.
*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
diff --git a/boot/cypress/MCUBootApp/misc/timebase_us.h b/boot/cypress/MCUBootApp/misc/timebase_us.h
index 79d1482..9689aba 100644
--- a/boot/cypress/MCUBootApp/misc/timebase_us.h
+++ b/boot/cypress/MCUBootApp/misc/timebase_us.h
@@ -1,4 +1,4 @@
-/* Copyright 2022, Infineon Technologies AG. All rights reserved.
+/* Copyright 2025, Infineon Technologies AG. All rights reserved.
*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
diff --git a/boot/cypress/MCUBootApp/os/os.h b/boot/cypress/MCUBootApp/os/os.h
index 8d581ca..d6067e4 100644
--- a/boot/cypress/MCUBootApp/os/os.h
+++ b/boot/cypress/MCUBootApp/os/os.h
@@ -8,7 +8,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2017-2025, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
diff --git a/boot/cypress/MCUBootApp/timestamp.h b/boot/cypress/MCUBootApp/timestamp.h
index afd6460..6a6b4df 100644
--- a/boot/cypress/MCUBootApp/timestamp.h
+++ b/boot/cypress/MCUBootApp/timestamp.h
@@ -1,4 +1,4 @@
-/* Copyright 2022, Infineon Technologies AG. All rights reserved.
+/* Copyright 2025, Infineon Technologies AG. All rights reserved.
*
* Licensed to the Apache Software Foundation (ASF) under one
* or more contributor license agreements. See the NOTICE file
diff --git a/boot/cypress/Makefile b/boot/cypress/Makefile
index 1e32ec8..3efa1ad 100644
--- a/boot/cypress/Makefile
+++ b/boot/cypress/Makefile
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2021 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/README.md b/boot/cypress/README.md
index a659281..9c78f6b 100644
--- a/boot/cypress/README.md
+++ b/boot/cypress/README.md
@@ -1,12 +1,12 @@
-### Port of MCUBoot library for evaluation with Cypress PSoC 6 chips
+### Port of MCUBoot library for evaluation with Cypress (Infineon) chips
### Disclaimer
-Given solution is included in `MCUboot` repository with purpose to demonstrate basic concepts and features of MCUboot library on Cypress PSoC 6 device. Applications are created per MCUboot library maintainers requirements. Implementation differs from conventional and recommended by Cypress Semiconductors development flow for PSoC 6 devices. These applications are not recommended as a starting point for development and should not be considered as supported examples for PSoC 6 devices.
+Given solution is included in `MCUboot` repository with purpose to demonstrate basic concepts and features of MCUboot library on Cypress (Infineon) devices. Applications are created per MCUboot library maintainers requirements. Implementation differs from conventional and recommended by Cypress Semiconductors development flow. These applications are not recommended as a starting point for development and should not be considered as supported examples.
-Examples provided to use with **ModusToolbox® Software Environment** are a recommended reference point to start development of MCUboot based bootloaders for PSoC 6 devices.
+Examples provided to use with **ModusToolbox™ Software Environment** are a recommended reference point to start development of MCUboot based bootloaders for Cypress (Infineon) devices.
-Refer to **Cypress Semiconductors** [github](https://github.com/cypresssemiconductorco) page to find examples.
+Refer to **Cypress (Infineon)** [github](https://github.com/Infineon) page to find examples.
1. MCUboot-Based Basic Bootloader [mtb-example-psoc6-mcuboot-basic](https://github.com/cypresssemiconductorco/mtb-example-psoc6-mcuboot-basic)
2. MCUboot-Based Bootloader with Rollback to Factory App in External Flash [mtb-example-anycloud-mcuboot-rollback](https://github.com/cypresssemiconductorco/mtb-example-anycloud-mcuboot-rollback)
@@ -14,20 +14,20 @@
### Solution description
There are two applications implemented:
-* MCUBootApp - PSoC6 MCUboot-based bootloading application;
-* BlinkyApp - simple PSoC6 blinking LED application which is a target of BOOT/UPGRADE;
+* MCUBootApp - MCUboot-based bootloading application;
+* BlinkyApp - simple blinking LED application which is a target for primary or secondary slot;
-The default flash map for MCUBootApp implemented is next:
+The default flash map for PSOC6 MCUBootApp implemented is next:
* [0x10000000, 0x10018000] - MCUBootApp (bootloader) area;
* [0x10018000, 0x10028000] - primary slot for BlinkyApp;
* [0x10028000, 0x10038000] - secondary slot for BlinkyApp;
* [0x10038000, 0x10039000] - scratch area;
-The flash map is defined through sysflash.h and memory.c.
+The flash map can be defined in boot/cypress/platforms/memory/<PLATFORM>/flashmap/<CONFIGURATION>.json
It is also possible to place secondary (upgrade) slots in external memory module. In this case primary slot can be doubled in size.
-For more details about External Memory usage, please refer to separate guiding document `MCUBootApp/ExternalMemory.md`.
+For more details about External Memory usage, please refer to separate guiding document [ExternalMemory.md](MCUBootApp/ExternalMemory.md).
MCUBootApp checks image integrity with SHA256, image authenticity with EC256 digital signature verification and uses either completely software implementation of cryptographic functions or accelerated by hardware - both based on Mbed TLS Library.
@@ -54,25 +54,19 @@
### Building solution
-Root directory for build is **boot/cypress.**
+Root directory for build is **boot/cypress**
This folder contains make files infrastructure for building both MCUboot Bootloader and sample BlinkyApp application used for Bootloader demo functionality.
-Instructions on how to build and upload MCUBootApp bootloader application and sample user application are located in `Readme.md` files in corresponding folders.
+Instructions on how to build and upload MCUBootApp bootloader application and sample user application are located in corresponding `Readme` files of the `platforms` folder.
-Supported platforms for `MCUboot`, `BlinkyApp`:
+**GCC_ARM** is only supported GCC compiler. It is included with [ModusToolbox™ Programming Tools](https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolboxprogtools). The recommended version of the GCC_ARM compiler is 11.3.1.
-**GCC_ARM** is only supported (built and verified on GCC 9.3.1).
+The default installation folder is expected by the makefile build system.To use another installation folder, version of **ModusToolbox™ Programming Tools** or another GCC Compiler, specify the path to a toolchain using the **TOOLCHAIN_PATH** parameter.
-It is included with [ModusToolbox™ Software Environment](https://www.cypress.com/products/modustoolbox).
+Below is an example on how to set toolchain path:
-The default installation folder is expected by the makefile build system.
-
-To use another installation folder, version of **ModusToolbox™ IDE** or another GCC Compiler, specify the path to a toolchain using the **TOOLCHAIN_PATH** parameter.
-
-Below is an example on how to set toolchain path to the latest include with **ModusToolbox™ IDE 3.2**:
-
- make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/ModusToolbox/tools_3.2/gcc
+ make clean app APP_NAME=MCUBootApp PLATFORM=PSOC_062_2M BUILDCFG=Debug FLASH_MAP=platforms/memory/PSOC6/flashmap/psoc6_swap_single.json TOOLCHAIN_PATH=c:/Users/${USERNAME}/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
### Build environment troubleshooting
@@ -80,7 +74,7 @@
* Cygwin on Windows systems
* unix style shells on *nix systems
-* Eclipse / ModusToolbox ("makefile project from existing source")
+* Eclipse / ModusToolbox™ ("makefile project from existing source")
*Make* - make sure it is added to system's `PATH` variable and correct path is first in the list;
@@ -88,5 +82,5 @@
*Msys2* - to use systems PATH navigate to msys2 folder, open `msys2_shell.cmd`, uncomment set `MSYS2_PATH_TYPE=inherit`, restart MSYS2 shell.
-This will inherit system's PATH so should find `python3.7` installed in regular way as well as imgtool and its dependencies.
+This will inherit system's PATH so should find `Python` installed in regular way as well as imgtool and its dependencies.
diff --git a/boot/cypress/build_config.mk b/boot/cypress/build_config.mk
index 966bd3f..b6f86b5 100644
--- a/boot/cypress/build_config.mk
+++ b/boot/cypress/build_config.mk
@@ -1,3 +1,21 @@
+################################################################################
+# \copyright
+# Copyright 2025 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
# Defines whether or not show verbose build output
VERBOSE ?= 0
diff --git a/boot/cypress/common_libs.mk b/boot/cypress/common_libs.mk
index 240ce8c..5abd167 100644
--- a/boot/cypress/common_libs.mk
+++ b/boot/cypress/common_libs.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2021 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/host.mk b/boot/cypress/host.mk
index 6b6851e..660801c 100644
--- a/boot/cypress/host.mk
+++ b/boot/cypress/host.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2021 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/libs/cy-mbedtls-acceleration b/boot/cypress/libs/cy-mbedtls-acceleration
index f4f9de4..4ff35d0 160000
--- a/boot/cypress/libs/cy-mbedtls-acceleration
+++ b/boot/cypress/libs/cy-mbedtls-acceleration
@@ -1 +1 @@
-Subproject commit f4f9de4be6ebd2effc30f2b82eb6b4327555d89e
+Subproject commit 4ff35d09e3339d2d476e5972daa4576bdf2588e1
diff --git a/boot/cypress/libs/mtb-pdl-cat1 b/boot/cypress/libs/mtb-pdl-cat1
index baab436..6e1d7a3 160000
--- a/boot/cypress/libs/mtb-pdl-cat1
+++ b/boot/cypress/libs/mtb-pdl-cat1
@@ -1 +1 @@
-Subproject commit baab4365d2afc0df4c852ecc4df885775b15479f
+Subproject commit 6e1d7a397f61702aa1a56cb18750927e6a839528
diff --git a/boot/cypress/libs/retarget-io/cy_retarget_io.c b/boot/cypress/libs/retarget-io/cy_retarget_io.c
index c508666..4f2f8ff 100644
--- a/boot/cypress/libs/retarget-io/cy_retarget_io.c
+++ b/boot/cypress/libs/retarget-io/cy_retarget_io.c
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/libs/retarget-io/cy_retarget_io.h b/boot/cypress/libs/retarget-io/cy_retarget_io.h
index fe2330d..7316ea9 100644
--- a/boot/cypress/libs/retarget-io/cy_retarget_io.h
+++ b/boot/cypress/libs/retarget-io/cy_retarget_io.h
@@ -14,7 +14,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms.mk b/boot/cypress/platforms.mk
index cab13d0..8e45bf1 100644
--- a/boot/cypress/platforms.mk
+++ b/boot/cypress/platforms.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.c b/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.c
index f5e92f9..6726fb2 100644
--- a/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.c
+++ b/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.c
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2020-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2020-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.h b/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.h
index 75c8a49..ad26e70 100644
--- a/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.h
+++ b/boot/cypress/platforms/BSP/CYW20829/bluetooth/cybsp_bt_config.h
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2020-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2020-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp.c b/boot/cypress/platforms/BSP/CYW20829/cybsp.c
index e8407b7..bc97940 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp.c
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2021 Cypress Semiconductor Corporation
+* Copyright 2018-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp.h b/boot/cypress/platforms/BSP/CYW20829/cybsp.h
index 6d5d663..7449625 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp.h
@@ -8,7 +8,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2021 Cypress Semiconductor Corporation
+ * Copyright 2018-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h
index 02bc2f0..cd6c8a0 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_doc.h
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.c b/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.c
index b20862f..89b0fe5 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.h
index a3e5137..f3012a6 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_dsram.h
@@ -6,7 +6,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_hw_config.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_hw_config.h
index f4ff295..6aabdb3 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_hw_config.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_hw_config.h
@@ -7,7 +7,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.c b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.c
index 254dc51..f35523b 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.c
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.h
index 27b12f3..5fe6182 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm.h
@@ -6,7 +6,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.c b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.c
index ed5f0af..3ce8145 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.c
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.h
index 4a41792..c5f6243 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_pm_callbacks.h
@@ -6,7 +6,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.c b/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.c
index 410be64..5885431 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.h
index f4968c4..74be1f5 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_smif_init.h
@@ -6,7 +6,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cybsp_types.h b/boot/cypress/platforms/BSP/CYW20829/cybsp_types.h
index aeb7023..c20d555 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cybsp_types.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cybsp_types.h
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg.c b/boot/cypress/platforms/BSP/CYW20829/cycfg.c
index 86c7e6a..8798d50 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg.c
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg.h b/boot/cypress/platforms/BSP/CYW20829/cycfg.h
index d2cf33f..3831527 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h
index fc94cf2..218aeed 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_notices.h
@@ -10,7 +10,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.c
index 0d1a34a..4679211 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.c
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.h
index f625a9a..a1a38c9 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_peripherals.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c
index 4ba698b..7727a1a 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.c
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h
index 60a717d..f220fcf 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_pins.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.c
index c1d6c4c..a74c843 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.c
@@ -7,7 +7,7 @@
* QSPI Configurator 4.10.0.1343
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.h
index 422fb49..d2e7be3 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_qspi_memslot.h
@@ -7,7 +7,7 @@
* QSPI Configurator 4.10.0.1343
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h
index 1ced646..0340c87 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_routing.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_system.c b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.c
index f04cde5..65b0a71 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_system.c
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.c
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/cycfg_system.h b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.h
index 6395d20..7a31a13 100644
--- a/boot/cypress/platforms/BSP/CYW20829/cycfg_system.h
+++ b/boot/cypress/platforms/BSP/CYW20829/cycfg_system.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.9.0.29592
*
********************************************************************************
-* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c
index c77911d..1c9abe1 100644
--- a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c
+++ b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_start_cyw20829.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright (c) (2020-2025), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c
index 9adf3d7..b2f2a3a 100644
--- a/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c
+++ b/boot/cypress/platforms/BSP/CYW20829/system/COMPONENT_CM33/ns_system_cyw20829.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright (c) (2020-2025), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
@@ -128,7 +128,7 @@
(void)Cy_SystemInit(); /* typecast void to suppress a compiler warning about unused return value */
/* Unlock and disable WDT */
-#if !defined(DISABLE_WDT_FREE)
+#if defined(BSP_DISABLE_WDT)
Cy_WDT_Unlock();
Cy_WDT_Disable();
#endif
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h b/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h
index 862b5b5..f2d0c49 100644
--- a/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h
+++ b/boot/cypress/platforms/BSP/CYW20829/system/startup_cat1b.h
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
+* Copyright 2016-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h b/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h
index 81c48fd..b9a1b26 100644
--- a/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h
+++ b/boot/cypress/platforms/BSP/CYW20829/system/system_cat1b.h
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
+* Copyright 2016-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/CYW20829/system/system_cyw20829.h b/boot/cypress/platforms/BSP/CYW20829/system/system_cyw20829.h
index f136e81..9421a66 100644
--- a/boot/cypress/platforms/BSP/CYW20829/system/system_cyw20829.h
+++ b/boot/cypress/platforms/BSP/CYW20829/system/system_cyw20829.h
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright (c) (2020-2025), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp.c b/boot/cypress/platforms/BSP/PSOC6/cybsp.c
index d20fa97..d5f13c2 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cybsp.c
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp.c
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
@@ -117,11 +117,11 @@
// the CM4 if necessary.
#if defined(CORE_NAME_CM0P_0) || !(__CM0P_PRESENT) || (defined(CORE_NAME_CM4_0) && \
defined(CY_USING_PREBUILT_CM0P_IMAGE))
- //cycfg_config_init();
+ cycfg_config_init();
#endif
// Do any additional configuration reservations that are needed on all cores.
- //cycfg_config_reservations();
+ cycfg_config_reservations();
if (CY_RSLT_SUCCESS == result)
{
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp.h b/boot/cypress/platforms/BSP/PSOC6/cybsp.h
index cd27cf6..7ba085f 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cybsp.h
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp.h
@@ -6,7 +6,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp_doc.h b/boot/cypress/platforms/BSP/PSOC6/cybsp_doc.h
index 1f9f0d6..cd6c8a0 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cybsp_doc.h
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp_doc.h
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
@@ -24,7 +24,7 @@
#include "cyhal_pin_package.h"
#endif
/* CAT4 and CAT5 do not have configurators so the BSP defines pins in a non-generated header */
-#if defined(COMPONENT_CAT4) || defined(COMPONENT_CAT5)
+#if defined(COMPONENT_CAT4)
#include "cybsp_pins.h"
#else
#include "cycfg.h"
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp_hw_config.h b/boot/cypress/platforms/BSP/PSOC6/cybsp_hw_config.h
index 580d49c..b8f3546 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cybsp_hw_config.h
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp_hw_config.h
@@ -7,7 +7,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
@@ -28,6 +28,7 @@
#include "cy_result.h"
#include "cybsp_types.h"
+#include "cycfg_pins.h"
#if defined(__cplusplus)
extern "C" {
@@ -37,6 +38,13 @@
#define CYBSP_USER_BTN_DRIVE (CYHAL_GPIO_DRIVE_PULLUP)
#endif
+#ifndef CYBSP_DEBUG_UART_CTS
+#define CYBSP_DEBUG_UART_CTS (NC)
+#endif
+#ifndef CYBSP_DEBUG_UART_RTS
+#define CYBSP_DEBUG_UART_RTS (NC)
+#endif
+
#if defined(__cplusplus)
}
#endif
diff --git a/boot/cypress/platforms/BSP/PSOC6/cybsp_types.h b/boot/cypress/platforms/BSP/PSOC6/cybsp_types.h
index aeb7023..c20d555 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cybsp_types.h
+++ b/boot/cypress/platforms/BSP/PSOC6/cybsp_types.h
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg.c b/boot/cypress/platforms/BSP/PSOC6/cycfg.c
index ede3da0..12ba07f 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg.c
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg.c
@@ -1,33 +1,47 @@
/*******************************************************************************
-* File Name: cycfg.c
-*
-* Description:
-* Wrapper function to initialize all generated code.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg.c
+ *
+ * Description:
+ * Simple wrapper containing all generated files and function to initialize
+ * all generated code.
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
#include "cycfg.h"
+/* This function is provided for compatibility with older 2.X style projects. */
void init_cycfg_all(void)
{
- init_cycfg_system();
- init_cycfg_clocks();
+ cycfg_config_init();
+ cycfg_config_reservations();
+}
+void cycfg_config_init(void)
+{
+ init_cycfg_system();
+ init_cycfg_routing();
+ init_cycfg_pins();
+}
+void cycfg_config_reservations(void)
+{
+ reserve_cycfg_pins();
}
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg.h b/boot/cypress/platforms/BSP/PSOC6/cycfg.h
index 9b74187..bb1d9c6 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg.h
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg.h
@@ -1,45 +1,52 @@
/*******************************************************************************
-* File Name: cycfg.h
-*
-* Description:
-* Simple wrapper header containing all generated files.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg.h
+ *
+ * Description:
+ * Simple wrapper containing all generated files and function to initialize
+ * all generated code.
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
#if !defined(CYCFG_H)
#define CYCFG_H
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+#include "cycfg_security.h"
+
#if defined(__cplusplus)
extern "C" {
-#endif
-
-#include "cycfg_system.h"
-#include "cycfg_clocks.h"
+#endif /* defined(__cplusplus) */
void init_cycfg_all(void);
-
+void cycfg_config_init(void);
+void cycfg_config_reservations(void);
#if defined(__cplusplus)
}
-#endif
-
+#endif /* defined(__cplusplus) */
#endif /* CYCFG_H */
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.c
deleted file mode 100644
index 48c1497..0000000
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_clocks.c
-*
-* Description:
-* Clock configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_clocks.h"
-
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
- {
- .type = CYHAL_RSC_CLOCK,
- .block_num = CYBSP_CSD_CLK_DIV_HW,
- .channel_num = CYBSP_CSD_CLK_DIV_NUM,
- };
-#endif //defined (CY_USING_HAL)
-
-
-void init_cycfg_clocks(void)
-{
- (void)Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
- (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
- (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
-#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
-#endif //defined (CY_USING_HAL)
-}
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.h
deleted file mode 100644
index 5766ab5..0000000
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_clocks.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_clocks.h
-*
-* Description:
-* Clock configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_CLOCKS_H)
-#define CYCFG_CLOCKS_H
-
-#include "cy_sysclk.h"
-#if defined (CY_USING_HAL)
- #include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_CSD_CLK_DIV_ENABLED 1U
-#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_CSD_CLK_DIV_NUM 0U
-
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_clocks(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_CLOCKS_H */
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_notices.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_notices.h
new file mode 100644
index 0000000..6b5ba8b
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg_notices.h
@@ -0,0 +1,53 @@
+/*******************************************************************************
+ * File Name: cycfg_notices.h
+ *
+ * Description:
+ * Contains warnings and errors that occurred while generating code for the
+ * design.
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
+
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* defined(__cplusplus) */
+
+#if defined(CY_SUPPORTS_DEVICE_VALIDATION)
+#if !defined(CYBLE_416045_02_device)
+#error "Unexpected MPN; expected DEVICE:=CYBLE-416045-02-device. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif /* !defined(CYBLE_416045_02_device) */
+#endif /* defined(CY_SUPPORTS_DEVICE_VALIDATION) */
+
+#if defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION)
+#if !defined(CYBLE_416045_02_device)
+#error "Unexpected MPN; expected DEVICE:=CYBLE-416045-02-device. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif /* !defined(CYBLE_416045_02_device) */
+#endif /* defined(CY_SUPPORTS_COMPLETE_DEVICE_VALIDATION) */
+
+#if defined(__cplusplus)
+}
+#endif /* defined(__cplusplus) */
+
+#endif /* CYCFG_NOTICES_H */
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.c
deleted file mode 100644
index a694256..0000000
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_peripherals.c
-*
-* Description:
-* Peripheral Hardware Block configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.3.1.1499
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_peripherals.h"
-
-void init_cycfg_peripherals(void)
-{
-
-}
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.h
index f4133a8..7da72e7 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.h
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg_peripherals.h
@@ -1,48 +1,42 @@
/*******************************************************************************
-* File Name: cycfg_peripherals.h
-*
-* Description:
-* Peripheral Hardware Block configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.3.1.1499
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_peripherals.h
+ *
+ * Description:
+ * Peripheral Hardware Block configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
#if !defined(CYCFG_PERIPHERALS_H)
#define CYCFG_PERIPHERALS_H
-// #include "cycfg_notices.h"
-#include "cy_scb_uart.h"
-#include "cy_sysclk.h"
-#if defined (CY_USING_HAL)
- #include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
+#include "cycfg_notices.h"
#if defined(__cplusplus)
extern "C" {
-#endif
-
-void init_cycfg_peripherals(void);
+#endif /* defined(__cplusplus) */
#if defined(__cplusplus)
}
-#endif
-
+#endif /* defined(__cplusplus) */
#endif /* CYCFG_PERIPHERALS_H */
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.c
index 0ba461d..4752cdd 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.c
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.c
@@ -1,32 +1,148 @@
/*******************************************************************************
-* File Name: cycfg_pins.c
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.3.1.1499
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_pins.c
+ *
+ * Description:
+ * Pin configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
#include "cycfg_pins.h"
+const cy_stc_gpio_pin_config_t WCO_IN_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = WCO_IN_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t WCO_IN_obj =
+{
+ .type = CYHAL_RSC_GPIO,
+ .block_num = WCO_IN_PORT_NUM,
+ .channel_num = WCO_IN_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+const cy_stc_gpio_pin_config_t WCO_OUT_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_ANALOG,
+ .hsiom = WCO_OUT_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t WCO_OUT_obj =
+{
+ .type = CYHAL_RSC_GPIO,
+ .block_num = WCO_OUT_PORT_NUM,
+ .channel_num = WCO_OUT_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+const cy_stc_gpio_pin_config_t SWDIO_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_PULLUP,
+ .hsiom = SWDIO_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t SWDIO_obj =
+{
+ .type = CYHAL_RSC_GPIO,
+ .block_num = SWDIO_PORT_NUM,
+ .channel_num = SWDIO_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+const cy_stc_gpio_pin_config_t SWCLK_config =
+{
+ .outVal = 1,
+ .driveMode = CY_GPIO_DM_PULLDOWN,
+ .hsiom = SWCLK_HSIOM,
+ .intEdge = CY_GPIO_INTR_DISABLE,
+ .intMask = 0UL,
+ .vtrip = CY_GPIO_VTRIP_CMOS,
+ .slewRate = CY_GPIO_SLEW_FAST,
+ .driveSel = CY_GPIO_DRIVE_1_2,
+ .vregEn = 0UL,
+ .ibufMode = 0UL,
+ .vtripSel = 0UL,
+ .vrefSel = 0UL,
+ .vohSel = 0UL,
+};
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+const cyhal_resource_inst_t SWCLK_obj =
+{
+ .type = CYHAL_RSC_GPIO,
+ .block_num = SWCLK_PORT_NUM,
+ .channel_num = SWCLK_PIN,
+};
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
void init_cycfg_pins(void)
{
-
+ Cy_GPIO_Pin_Init(SWDIO_PORT, SWDIO_PIN, &SWDIO_config);
+ Cy_GPIO_Pin_Init(SWCLK_PORT, SWCLK_PIN, &SWCLK_config);
+}
+void reserve_cycfg_pins(void)
+{
+#if defined (CY_USING_HAL)
+ cyhal_hwmgr_reserve(&WCO_IN_obj);
+ cyhal_hwmgr_reserve(&WCO_OUT_obj);
+ cyhal_hwmgr_reserve(&SWDIO_obj);
+ cyhal_hwmgr_reserve(&SWCLK_obj);
+#endif /* defined (CY_USING_HAL) */
}
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.h
index 9adea11..a0111fc 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.h
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg_pins.h
@@ -1,47 +1,197 @@
/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.3.1.1499
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_pins.h
+ *
+ * Description:
+ * Pin configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
#if !defined(CYCFG_PINS_H)
#define CYCFG_PINS_H
+#include "cycfg_notices.h"
#include "cy_gpio.h"
-#if defined (CY_USING_HAL)
- #include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
#include "cycfg_routing.h"
+#if defined (CY_USING_HAL)
+#include "cyhal_hwmgr.h"
+#endif /* defined (CY_USING_HAL) */
+
+#if defined (CY_USING_HAL_LITE)
+#include "cyhal_hw_types.h"
+#endif /* defined (CY_USING_HAL_LITE) */
+
#if defined(__cplusplus)
extern "C" {
+#endif /* defined(__cplusplus) */
+
+#define WCO_IN_ENABLED 1U
+#define WCO_IN_PORT GPIO_PRT0
+#define WCO_IN_PORT_NUM 0U
+#define WCO_IN_PIN 0U
+#define WCO_IN_NUM 0U
+#define WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+ #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
+#define WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define WCO_IN_HAL_PORT_PIN P0_0
+#define WCO_IN P0_0
+#define WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#define WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+#define WCO_OUT_ENABLED 1U
+#define WCO_OUT_PORT GPIO_PRT0
+#define WCO_OUT_PORT_NUM 0U
+#define WCO_OUT_PIN 1U
+#define WCO_OUT_NUM 1U
+#define WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+ #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define WCO_OUT_HAL_PORT_PIN P0_1
+#define WCO_OUT P0_1
+#define WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#define WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+#define SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_ENABLED SWDIO_ENABLED
+#define SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT SWDIO_PORT
+#define SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PORT_NUM SWDIO_PORT_NUM
+#define SWDIO_PIN 6U
+#define CYBSP_SWDIO_PIN SWDIO_PIN
+#define SWDIO_NUM 6U
+#define CYBSP_SWDIO_NUM SWDIO_NUM
+#define SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_DRIVEMODE SWDIO_DRIVEMODE
+#define SWDIO_INIT_DRIVESTATE 1
+#define CYBSP_SWDIO_INIT_DRIVESTATE SWDIO_INIT_DRIVESTATE
+#ifndef ioss_0_port_6_pin_6_HSIOM
+ #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_HSIOM SWDIO_HSIOM
+#define SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDIO_IRQ SWDIO_IRQ
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define SWDIO_HAL_PORT_PIN P6_6
+#define CYBSP_SWDIO_HAL_PORT_PIN SWDIO_HAL_PORT_PIN
+#define SWDIO P6_6
+#define CYBSP_SWDIO SWDIO
+#define SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define CYBSP_SWDIO_HAL_IRQ SWDIO_HAL_IRQ
+#define SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
+#define CYBSP_SWDIO_HAL_DIR SWDIO_HAL_DIR
+#define SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#define CYBSP_SWDIO_HAL_DRIVEMODE SWDIO_HAL_DRIVEMODE
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+#define SWCLK_ENABLED 1U
+#define CYBSP_SWDCK_ENABLED SWCLK_ENABLED
+#define SWCLK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT SWCLK_PORT
+#define SWCLK_PORT_NUM 6U
+#define CYBSP_SWDCK_PORT_NUM SWCLK_PORT_NUM
+#define SWCLK_PIN 7U
+#define CYBSP_SWDCK_PIN SWCLK_PIN
+#define SWCLK_NUM 7U
+#define CYBSP_SWDCK_NUM SWCLK_NUM
+#define SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_DRIVEMODE SWCLK_DRIVEMODE
+#define SWCLK_INIT_DRIVESTATE 1
+#define CYBSP_SWDCK_INIT_DRIVESTATE SWCLK_INIT_DRIVESTATE
+#ifndef ioss_0_port_6_pin_7_HSIOM
+ #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_HSIOM SWCLK_HSIOM
+#define SWCLK_IRQ ioss_interrupts_gpio_6_IRQn
+#define CYBSP_SWDCK_IRQ SWCLK_IRQ
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+#define SWCLK_HAL_PORT_PIN P6_7
+#define CYBSP_SWDCK_HAL_PORT_PIN SWCLK_HAL_PORT_PIN
+#define SWCLK P6_7
+#define CYBSP_SWDCK SWCLK
+#define SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#define CYBSP_SWDCK_HAL_IRQ SWCLK_HAL_IRQ
+#define SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
+#define CYBSP_SWDCK_HAL_DIR SWCLK_HAL_DIR
+#define SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#define CYBSP_SWDCK_HAL_DRIVEMODE SWCLK_HAL_DRIVEMODE
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+extern const cy_stc_gpio_pin_config_t WCO_IN_config;
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t WCO_IN_obj;
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+extern const cy_stc_gpio_pin_config_t WCO_OUT_config;
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t WCO_OUT_obj;
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+extern const cy_stc_gpio_pin_config_t SWDIO_config;
+
+#define CYBSP_SWDIO_config SWDIO_config
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t SWDIO_obj;
+#define CYBSP_SWDIO_obj SWDIO_obj
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
+
+extern const cy_stc_gpio_pin_config_t SWCLK_config;
+
+#define CYBSP_SWDCK_config SWCLK_config
+
+#if defined (CY_USING_HAL) || (CY_USING_HAL_LITE)
+extern const cyhal_resource_inst_t SWCLK_obj;
+#define CYBSP_SWDCK_obj SWCLK_obj
+#endif /* defined (CY_USING_HAL) || (CY_USING_HAL_LITE) */
void init_cycfg_pins(void);
+void reserve_cycfg_pins(void);
#if defined(__cplusplus)
}
-#endif
-
+#endif /* defined(__cplusplus) */
#endif /* CYCFG_PINS_H */
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_routing.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_routing.c
deleted file mode 100644
index 063e736..0000000
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_routing.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_routing.c
-*
-* Description:
-* Establishes all necessary connections between hardware elements.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.0.1889
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_routing.h"
-
-void init_cycfg_routing(void)
-{
-}
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_routing.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_routing.h
index dbedb11..8daeebd 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_routing.h
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg_routing.h
@@ -1,43 +1,49 @@
/*******************************************************************************
-* File Name: cycfg_routing.h
-*
-* Description:
-* Establishes all necessary connections between hardware elements.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.0.1889
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_routing.h
+ *
+ * Description:
+ * Establishes all necessary connections between hardware elements.
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
#if !defined(CYCFG_ROUTING_H)
#define CYCFG_ROUTING_H
+#include "cycfg_notices.h"
+
#if defined(__cplusplus)
extern "C" {
-#endif
+#endif /* defined(__cplusplus) */
-void init_cycfg_routing(void);
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
+#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
+#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-#define init_cycfg_connectivity() init_cycfg_routing()
+static inline void init_cycfg_routing(void) {}
#if defined(__cplusplus)
}
-#endif
-
+#endif /* defined(__cplusplus) */
#endif /* CYCFG_ROUTING_H */
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_security.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_security.h
new file mode 100644
index 0000000..40c251a
--- /dev/null
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg_security.h
@@ -0,0 +1,42 @@
+/*******************************************************************************
+ * File Name: cycfg_security.h
+ *
+ * Description:
+ * Memory configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
+
+#if !defined(CYCFG_SECURITY_H)
+#define CYCFG_SECURITY_H
+
+#include "cycfg_notices.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* defined(__cplusplus) */
+
+#if defined(__cplusplus)
+}
+#endif /* defined(__cplusplus) */
+
+#endif /* CYCFG_SECURITY_H */
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_system.c b/boot/cypress/platforms/BSP/PSOC6/cycfg_system.c
index fac7a2b..21471b8 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_system.c
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg_system.c
@@ -1,72 +1,107 @@
/*******************************************************************************
-* File Name: cycfg_system.c
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_system.c
+ *
+ * Description:
+ * System configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
#include "cycfg_system.h"
-#include "cy_ble_clk.h"
#define CY_CFG_SYSCLK_ECO_ERROR 1
#define CY_CFG_SYSCLK_ALTHF_ERROR 2
#define CY_CFG_SYSCLK_PLL_ERROR 3
#define CY_CFG_SYSCLK_FLL_ERROR 4
#define CY_CFG_SYSCLK_WCO_ERROR 5
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_WCO
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0
#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_MULT 500U
+#define CY_CFG_SYSCLK_FLL_REFDIV 20U
+#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4
+#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true
+#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U
+#define CY_CFG_SYSCLK_FLL_IGAIN 9U
+#define CY_CFG_SYSCLK_FLL_PGAIN 5U
+#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U
+#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
+#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U
+#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000
#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
-#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
#define CY_CFG_SYSCLK_ILO_ENABLED 1
+#define CY_CFG_SYSCLK_ILO_HIBERNATE true
#define CY_CFG_SYSCLK_IMO_ENABLED 1
#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL
#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL
#define CY_CFG_SYSCLK_PLL0_ENABLED 1
-#define CY_CFG_SYSCLK_PLL1_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 30
+#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 5
+#define CY_CFG_SYSCLK_PLL0_LF_MODE false
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 48000000
#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
-#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
+#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0
#define CY_CFG_SYSCLK_WCO_ENABLED 1
+#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0
+#define CY_CFG_SYSCLK_WCO_IN_PIN 0U
+#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0
+#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U
+#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED
+#define CY_CFG_PWR_ENABLED 1
+#define CY_CFG_PWR_INIT 1
+#define CY_CFG_PWR_USING_PMIC 0
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
+#define CY_CFG_PWR_USING_ULP 0
+#define CY_CFG_PWR_REGULATOR_MODE_MIN 0
+#define CY_CFG_PWR_BKP_ERROR 6
-void cycfg_ClockStartupError(uint32_t error);
+#if defined (CY_DEVICE_SECURE)
+static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig;
+#endif /* defined (CY_DEVICE_SECURE) */
-static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
+#if (!defined(CY_DEVICE_SECURE))
+static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
{
.fllMult = 500U,
.refDiv = 20U,
@@ -79,39 +114,43 @@
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
+#endif /* (!defined(CY_DEVICE_SECURE)) */
+
#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 0U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 1U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
- {
- .type = CYHAL_RSC_CLKPATH,
- .block_num = 2U,
- .channel_num = 0U,
- };
-#endif //defined (CY_USING_HAL)
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
- .feedbackDiv = 36,
- .referenceDiv = 1,
- .outputDiv = 2,
- .lfMode = false,
- .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 0U,
+ .channel_num = 0U,
};
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig =
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
+{
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 1U,
+ .channel_num = 0U,
+};
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
+{
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 2U,
+ .channel_num = 0U,
+};
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
+{
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 3U,
+ .channel_num = 0U,
+};
+const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
+{
+ .type = CYHAL_RSC_CLKPATH,
+ .block_num = 4U,
+ .channel_num = 0U,
+};
+#endif /* defined (CY_USING_HAL) */
+
+#if (!defined(CY_DEVICE_SECURE))
+static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 30,
.referenceDiv = 1,
@@ -119,19 +158,498 @@
.lfMode = false,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
};
+#endif /* (!defined(CY_DEVICE_SECURE)) */
-__WEAK void cycfg_ClockStartupError(uint32_t error)
+__WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
{
(void)error; /* Suppress the compiler warning */
- while (true) {}
+ while(1);
}
-__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit(void)
+
+#if ((!defined(CY_DEVICE_SECURE)) && (defined(CY_CFG_SYSCLK_FLL_ENABLED)))
+__STATIC_INLINE void Cy_SysClk_FllDeInit(void)
{
- Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
+ Cy_SysClk_FllDisable();
}
+#endif /* ((!defined(CY_DEVICE_SECURE)) && (defined(CY_CFG_SYSCLK_FLL_ENABLED))) */
+
+#if defined (CY_DEVICE_SECURE)
+void init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config)
+{
+ #ifdef CY_CFG_PWR_ENABLED
+ secure_config->powerEnable = CY_CFG_PWR_ENABLED;
+ #endif /* CY_CFG_PWR_ENABLED */
+
+ #ifdef CY_CFG_PWR_USING_LDO
+ secure_config->ldoEnable = CY_CFG_PWR_USING_LDO;
+ #endif /* CY_CFG_PWR_USING_LDO */
+
+ #ifdef CY_CFG_PWR_USING_PMIC
+ secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC;
+ #endif /* CY_CFG_PWR_USING_PMIC */
+
+ #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD
+ secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD;
+ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+ #ifdef CY_CFG_PWR_USING_ULP
+ secure_config->ulpEnable = CY_CFG_PWR_USING_ULP;
+ #endif /* CY_CFG_PWR_USING_ULP */
+
+ #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+ secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED;
+ #endif /* CY_CFG_SYSCLK_ECO_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+ secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED;
+ #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+ secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED;
+ #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+ secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED;
+ #endif /* CY_CFG_SYSCLK_WCO_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+ secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED;
+ #endif /* CY_CFG_SYSCLK_FLL_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+ secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED;
+ #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+ secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED;
+ #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+ secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+ secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+ secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+ secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+ secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+ secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+ secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+ secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED
+ secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+ secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+ secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+ secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+ secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+ secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+ secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+ secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+ secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+ secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED;
+ #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+ #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices.
+ #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+ secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED;
+ #endif /* CY_CFG_SYSCLK_PILO_ENABLED */
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+ secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED;
+ #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */
+
+ #ifdef CY_CFG_PWR_LDO_VOLTAGE
+ secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE;
+ #endif /* CY_CFG_PWR_LDO_VOLTAGE */
+
+ #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN
+ secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN;
+ #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
+
+ #ifdef CY_CFG_PWR_BUCK_VOLTAGE
+ secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE;
+ #endif /* CY_CFG_PWR_BUCK_VOLTAGE */
+
+ #ifdef CY_CFG_SYSCLK_ECO_FREQ
+ secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ;
+ #endif /* CY_CFG_SYSCLK_ECO_FREQ */
+
+ #ifdef CY_CFG_SYSCLK_ECO_CLOAD
+ secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD;
+ #endif /* CY_CFG_SYSCLK_ECO_CLOAD */
+
+ #ifdef CY_CFG_SYSCLK_ECO_ESR
+ secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR;
+ #endif /* CY_CFG_SYSCLK_ECO_ESR */
+
+ #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL
+ secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL;
+ #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */
+
+ #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT
+ secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT;
+ #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */
+
+ #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT
+ secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT;
+ #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */
+
+ #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN
+ secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN;
+ #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */
+
+ #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN
+ secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN;
+ #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ
+ secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ;
+ #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT
+ secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT;
+ #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN
+ secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN;
+ #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM
+ secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM;
+ #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */
+
+ #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE
+ secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE;
+ #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */
+
+ #ifdef CY_CFG_SYSCLK_WCO_BYPASS
+ secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS;
+ #endif /* CY_CFG_SYSCLK_WCO_BYPASS */
+
+ #ifdef CY_CFG_SYSCLK_WCO_IN_PRT
+ secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT;
+ #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */
+
+ #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT
+ secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT;
+ #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */
+
+ #ifdef CY_CFG_SYSCLK_WCO_IN_PIN
+ secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN;
+ #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */
+
+ #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN
+ secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN;
+ #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */
+
+ #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ
+ secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ;
+ #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */
+
+ #ifdef CY_CFG_SYSCLK_FLL_MULT
+ secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT;
+ #endif /* CY_CFG_SYSCLK_FLL_MULT */
+
+ #ifdef CY_CFG_SYSCLK_FLL_REFDIV
+ secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV;
+ #endif /* CY_CFG_SYSCLK_FLL_REFDIV */
+
+ #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE
+ secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE;
+ #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */
+
+ #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV
+ secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV;
+ #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */
+
+ #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE
+ secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE;
+ #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */
+
+ #ifdef CY_CFG_SYSCLK_FLL_IGAIN
+ secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN;
+ #endif /* CY_CFG_SYSCLK_FLL_IGAIN */
+
+ #ifdef CY_CFG_SYSCLK_FLL_PGAIN
+ secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN;
+ #endif /* CY_CFG_SYSCLK_FLL_PGAIN */
+
+ #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT
+ secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT;
+ #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */
+
+ #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE
+ secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE;
+ #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */
+
+ #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ
+ secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ;
+ #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */
+
+ #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV
+ secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV;
+ #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */
+
+ #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV
+ secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV;
+ #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */
+
+ #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV
+ secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV;
+ #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */
+
+ #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE
+ secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE;
+ #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */
+
+ #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE
+ secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE;
+ #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */
+
+ #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ
+ secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ;
+ #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */
+
+ #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV
+ secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV;
+ #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */
+
+ #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV
+ secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV;
+ #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */
+
+ #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV
+ secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV;
+ #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */
+
+ #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE
+ secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE;
+ #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */
+
+ #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE
+ secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE;
+ #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */
+
+ #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ
+ secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ;
+ #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE
+ secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE
+ secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE
+ secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE
+ secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE
+ secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE
+ secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER
+ secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER
+ secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER
+ secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH
+ secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH;
+ #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER
+ secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ
+ secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ;
+ #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH
+ secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH;
+ #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER
+ secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ
+ secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ;
+ #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH
+ secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH;
+ #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER
+ secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ
+ secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ;
+ #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH
+ secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH;
+ #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER
+ secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ
+ secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ;
+ #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH
+ secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH;
+ #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER
+ secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ
+ secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ;
+ #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH
+ secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH;
+ #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER
+ secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ
+ secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ;
+ #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */
+
+ #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE
+ secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER
+ secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE
+ secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE
+ secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE
+ secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER
+ secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER;
+ #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */
+
+ #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE
+ secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE;
+ #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD
+ secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD;
+ #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME
+ secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME;
+ #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ
+ secure_config->altHFclkFreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ;
+ #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV
+ secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV;
+ #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */
+
+ #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR
+ secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR;
+ #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */
+}
+#endif /* defined (CY_DEVICE_SECURE) */
+
+#if (!defined(CY_DEVICE_SECURE))
__STATIC_INLINE void Cy_SysClk_ClkBakInit(void)
{
- Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+ Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
}
__STATIC_INLINE void Cy_SysClk_ClkFastInit(void)
{
@@ -150,26 +668,8 @@
}
__STATIC_INLINE void Cy_SysClk_ClkHf0Init(void)
{
- (void)Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
- (void)Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf2Init(void)
-{
- (void)Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
- (void)Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
- (void)Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf3Init(void)
-{
- (void)Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
- (void)Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
- (void)Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf4Init(void)
-{
- (void)Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
- (void)Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
- (void)Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
+ Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
}
__STATIC_INLINE void Cy_SysClk_IloInit(void)
{
@@ -184,19 +684,27 @@
}
__STATIC_INLINE void Cy_SysClk_ClkPath0Init(void)
{
- (void)Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+ Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath1Init(void)
{
- (void)Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+ Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPath2Init(void)
{
- (void)Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+ Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath3Init(void)
+{
+ Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
+}
+__STATIC_INLINE void Cy_SysClk_ClkPath4Init(void)
+{
+ Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
}
__STATIC_INLINE void Cy_SysClk_ClkPeriInit(void)
{
- Cy_SysClk_ClkPeriSetDivider(1U);
+ Cy_SysClk_ClkPeriSetDivider(0U);
}
__STATIC_INLINE void Cy_SysClk_Pll0Init(void)
{
@@ -209,28 +717,10 @@
cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
}
}
-__STATIC_INLINE void Cy_SysClk_Pll1Init(void)
-{
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
- {
- cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
- }
- if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
- {
- cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
- }
-}
__STATIC_INLINE void Cy_SysClk_ClkSlowInit(void)
{
Cy_SysClk_ClkSlowSetDivider(0U);
}
-__STATIC_INLINE void Cy_SysClk_ClkTimerInit(void)
-{
- Cy_SysClk_ClkTimerDisable();
- Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
- Cy_SysClk_ClkTimerSetDivider(0U);
- Cy_SysClk_ClkTimerEnable();
-}
__STATIC_INLINE void Cy_SysClk_WcoInit(void)
{
(void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
@@ -240,302 +730,479 @@
cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
}
}
+__STATIC_INLINE void init_cycfg_power(void)
+{
+ /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
+ #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+ #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+ if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+ {
+ #if CY_CFG_SYSCLK_WCO_ENABLED
+ uint32_t wcoTrim = Cy_SysLib_GetWcoTrim();
+ if (CY_SYSLIB_SUCCESS != Cy_SysLib_ResetBackupDomain())
+ {
+ Cy_SysLib_DelayUs(1U);
+ if (CY_SYSLIB_SUCCESS != Cy_SysLib_GetResetStatus())
+ {
+ cycfg_ClockStartupError(CY_CFG_PWR_BKP_ERROR);
+ }
+ }
+ Cy_SysLib_SetWcoTrim(wcoTrim);
+ #else /* CY_CFG_SYSCLK_WCO_ENABLED */
+ (void) Cy_SysLib_ResetBackupDomain();
+ #endif /* CY_CFG_SYSCLK_WCO_ENABLED */
+ Cy_SysClk_IloDisable();
+ Cy_SysClk_IloInit();
+ }
+ #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
+ #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+ /* Configure core regulator */
+ #if !(defined(CY_DEVICE_SECURE))
+ #if defined (CY_IP_M4CPUSS)
+ #if CY_CFG_PWR_USING_LDO
+ Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+ #else
+ Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+ #endif /* CY_CFG_PWR_USING_LDO */
+ #endif /* defined (CY_IP_M4CPUSS) */
+ #if CY_CFG_PWR_REGULATOR_MODE_MIN
+ Cy_SysPm_SystemSetMinRegulatorCurrent();
+ #else
+ Cy_SysPm_SystemSetNormalRegulatorCurrent();
+ #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
+ #endif /* !(defined(CY_DEVICE_SECURE)) */
+ /* Configure PMIC */
+ Cy_SysPm_UnlockPmic();
+ #if CY_CFG_PWR_USING_PMIC
+ Cy_SysPm_PmicEnableOutput();
+ #else
+ Cy_SysPm_PmicDisableOutput();
+ #endif /* CY_CFG_PWR_USING_PMIC */
+}
+#endif /* (!defined(CY_DEVICE_SECURE)) */
void init_cycfg_system(void)
{
- /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
- Cy_SysLib_SetWaitStates(false, 150UL);
+ #if defined(CY_DEVICE_SECURE)
+ cy_en_pra_status_t configStatus;
+ init_cycfg_secure_struct(&srss_0_clock_0_secureConfig);
+ #if (((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0UL))
+ #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+ #endif
+ #if (((CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 1UL))
+ #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+ #endif
+ #if (((CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 2UL))
+ #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+ #endif
+ #if (((CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 3UL))
+ #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+ #endif
+ #if (((CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 4UL))
+ #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+ #endif
+ #if (((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL))
+ #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+ #endif
+
+ configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC,
+ CY_PRA_FUNC_INIT_CYCFG_DEVICE,
+ &srss_0_clock_0_secureConfig);
+ if ( configStatus != CY_PRA_STATUS_SUCCESS )
+ {
+ cycfg_ClockStartupError(configStatus);
+ }
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ
+ Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ);
+ #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
+ #else /* defined(CY_DEVICE_SECURE) */
+
+ /* Set worst case memory wait states (! ultra low power, 180 MHz), will update at the end */
+ Cy_SysLib_SetWaitStates(false, 180UL);
#ifdef CY_CFG_PWR_ENABLED
#ifdef CY_CFG_PWR_INIT
- init_cycfg_power();
+ init_cycfg_power();
#else
- #warning Power system will not be configured. Update power personality to v1.20 or later.
+ #warning Power system will not be configured. Update power personality to v1.20 or later.
#endif /* CY_CFG_PWR_INIT */
#endif /* CY_CFG_PWR_ENABLED */
-
- /* Reset the core clock path to default and disable all the FLLs/PLLs */
- (void)Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
- Cy_SysClk_ClkFastSetDivider(0U);
- Cy_SysClk_ClkPeriSetDivider(1U);
- Cy_SysClk_ClkSlowSetDivider(0U);
- for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
- {
- (void)Cy_SysClk_PllDisable(pll);
- }
- (void)Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
-
- if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
- (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
- {
- (void)Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
- }
-
- (void)Cy_SysClk_FllDisable();
- (void)Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
- (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
- #ifdef CY_IP_MXBLESS
- (void)Cy_BLE_EcoReset();
+
+ /* Disable FLL */
+ #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+ Cy_SysClk_FllDeInit();
#endif
-
-
+
+ /* Reset the core clock path to default and disable all the FLLs/PLLs */
+ Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+ Cy_SysClk_ClkFastSetDivider(0U);
+ Cy_SysClk_ClkPeriSetDivider(1U);
+ Cy_SysClk_ClkSlowSetDivider(0U);
+ for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+ {
+ (void)Cy_SysClk_PllDisable(pll);
+ }
+ Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
+
+ if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
+ (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
+ {
+ Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ }
+
+ Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
+ Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+ #ifdef CY_IP_MXBLESS
+ (void)Cy_BLE_EcoReset();
+ #endif
+
+
/* Enable all source clocks */
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
- Cy_SysClk_PiloInit();
+ Cy_SysClk_PiloInit();
#endif
-
+
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
- Cy_SysClk_WcoInit();
+ Cy_SysClk_WcoInit();
#endif
-
+
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
- Cy_SysClk_ClkLfInit();
+ Cy_SysClk_ClkLfInit();
#endif
+
+ #if (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED)
- #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
- Cy_SysClk_AltHfInit();
- #endif
+ Cy_SysClk_AltHfInit();
+ #endif /* (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED */
- #ifdef CY_CFG_SYSCLK_ECO_ENABLED
- Cy_SysClk_EcoInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
- Cy_SysClk_ExtClkInit();
- #endif
-
- /* Configure CPU clock dividers */
- #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
- Cy_SysClk_ClkFastInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
- Cy_SysClk_ClkPeriInit();
- #endif
-
- #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
- Cy_SysClk_ClkSlowInit();
- #endif
-
- #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
- /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
- (void)Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
- (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
- #else
- #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
- Cy_SysClk_ClkPath1Init();
+
+ #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+ Cy_SysClk_EcoInit();
#endif
+
+ #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+ Cy_SysClk_ExtClkInit();
#endif
-
- /* Configure Path Clocks */
- #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
- Cy_SysClk_ClkPath0Init();
+
+ /* Configure CPU clock dividers */
+ #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+ Cy_SysClk_ClkFastInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+ Cy_SysClk_ClkPeriInit();
+ #endif
+
+ #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+ Cy_SysClk_ClkSlowInit();
+ #endif
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
+ /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
+ Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
+ Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+ #else
+ #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+ Cy_SysClk_ClkPath1Init();
+ #endif
+ #endif
+
+ /* Configure Path Clocks */
+ #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+ Cy_SysClk_ClkPath0Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
- Cy_SysClk_ClkPath2Init();
+ Cy_SysClk_ClkPath2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
- Cy_SysClk_ClkPath3Init();
+ Cy_SysClk_ClkPath3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
- Cy_SysClk_ClkPath4Init();
+ Cy_SysClk_ClkPath4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
- Cy_SysClk_ClkPath5Init();
+ Cy_SysClk_ClkPath5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
- Cy_SysClk_ClkPath6Init();
+ Cy_SysClk_ClkPath6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
- Cy_SysClk_ClkPath7Init();
+ Cy_SysClk_ClkPath7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
- Cy_SysClk_ClkPath8Init();
+ Cy_SysClk_ClkPath8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
- Cy_SysClk_ClkPath9Init();
+ Cy_SysClk_ClkPath9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
- Cy_SysClk_ClkPath10Init();
+ Cy_SysClk_ClkPath10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
- Cy_SysClk_ClkPath11Init();
+ Cy_SysClk_ClkPath11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
- Cy_SysClk_ClkPath12Init();
+ Cy_SysClk_ClkPath12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
- Cy_SysClk_ClkPath13Init();
+ Cy_SysClk_ClkPath13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
- Cy_SysClk_ClkPath14Init();
+ Cy_SysClk_ClkPath14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
- Cy_SysClk_ClkPath15Init();
+ Cy_SysClk_ClkPath15Init();
#endif
-
+
/* Configure and enable FLL */
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
- Cy_SysClk_FllInit();
+ Cy_SysClk_FllInit();
#endif
-
- Cy_SysClk_ClkHf0Init();
-
- #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
+
+ #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED
+ Cy_SysClk_ClkHf0Init();
+ #endif
+
+ #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
/* Apply the ClkPath1 user setting */
Cy_SysClk_ClkPath1Init();
#endif
#endif
-
-
+
/* Configure and enable PLLs */
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
- Cy_SysClk_Pll0Init();
+ Cy_SysClk_Pll0Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
- Cy_SysClk_Pll1Init();
+ Cy_SysClk_Pll1Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
- Cy_SysClk_Pll2Init();
+ Cy_SysClk_Pll2Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
- Cy_SysClk_Pll3Init();
+ Cy_SysClk_Pll3Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
- Cy_SysClk_Pll4Init();
+ Cy_SysClk_Pll4Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
- Cy_SysClk_Pll5Init();
+ Cy_SysClk_Pll5Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
- Cy_SysClk_Pll6Init();
+ Cy_SysClk_Pll6Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
- Cy_SysClk_Pll7Init();
+ Cy_SysClk_Pll7Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
- Cy_SysClk_Pll8Init();
+ Cy_SysClk_Pll8Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
- Cy_SysClk_Pll9Init();
+ Cy_SysClk_Pll9Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
- Cy_SysClk_Pll10Init();
+ Cy_SysClk_Pll10Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
- Cy_SysClk_Pll11Init();
+ Cy_SysClk_Pll11Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
- Cy_SysClk_Pll12Init();
+ Cy_SysClk_Pll12Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
- Cy_SysClk_Pll13Init();
+ Cy_SysClk_Pll13Init();
#endif
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
- Cy_SysClk_Pll14Init();
+ Cy_SysClk_Pll14Init();
#endif
-
+
/* Configure HF clocks */
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
- Cy_SysClk_ClkHf1Init();
+ Cy_SysClk_ClkHf1Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
- Cy_SysClk_ClkHf2Init();
+ Cy_SysClk_ClkHf2Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
- Cy_SysClk_ClkHf3Init();
+ Cy_SysClk_ClkHf3Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
- Cy_SysClk_ClkHf4Init();
+ Cy_SysClk_ClkHf4Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
- Cy_SysClk_ClkHf5Init();
+ Cy_SysClk_ClkHf5Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
- Cy_SysClk_ClkHf6Init();
+ Cy_SysClk_ClkHf6Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
- Cy_SysClk_ClkHf7Init();
+ Cy_SysClk_ClkHf7Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
- Cy_SysClk_ClkHf8Init();
+ Cy_SysClk_ClkHf8Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
- Cy_SysClk_ClkHf9Init();
+ Cy_SysClk_ClkHf9Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
- Cy_SysClk_ClkHf10Init();
+ Cy_SysClk_ClkHf10Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
- Cy_SysClk_ClkHf11Init();
+ Cy_SysClk_ClkHf11Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
- Cy_SysClk_ClkHf12Init();
+ Cy_SysClk_ClkHf12Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
- Cy_SysClk_ClkHf13Init();
+ Cy_SysClk_ClkHf13Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
- Cy_SysClk_ClkHf14Init();
+ Cy_SysClk_ClkHf14Init();
#endif
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
- Cy_SysClk_ClkHf15Init();
+ Cy_SysClk_ClkHf15Init();
#endif
-
+
/* Configure miscellaneous clocks */
- #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
- Cy_SysClk_ClkTimerInit();
- #endif
-
+ #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+ Cy_SysClk_ClkTimerInit();
+ #endif
+
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
- Cy_SysClk_ClkAltSysTickInit();
+ Cy_SysClk_ClkAltSysTickInit();
#endif
-
+
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
- Cy_SysClk_ClkPumpInit();
+ Cy_SysClk_ClkPumpInit();
#endif
-
+
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
- Cy_SysClk_ClkBakInit();
+ Cy_SysClk_ClkBakInit();
#endif
-
+
/* Configure default enabled clocks */
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
- Cy_SysClk_IloInit();
- #else
- Cy_SysClk_IloDisable();
+ Cy_SysClk_IloInit();
#endif
-
+
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
- #error the IMO must be enabled for proper chip operation
- #endif
-
+ #error the IMO must be enabled for proper chip operation
+ #endif
+
+ #ifndef CY_CFG_SYSCLK_CLKHF0_ENABLED
+ #error the CLKHF0 must be enabled for proper chip operation
+ #endif
+
+ #endif /* defined(CY_DEVICE_SECURE) */
+
#ifdef CY_CFG_SYSCLK_MFO_ENABLED
- Cy_SysClk_MfoInit();
+ Cy_SysClk_MfoInit();
#endif
-
+
#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
- Cy_SysClk_ClkMfInit();
+ Cy_SysClk_ClkMfInit();
#endif
-
- /* Set accurate flash wait states */
- #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
- Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+
+ #ifdef CY_CFG_SYSCLK_CLKPWR_ENABLED
+ Cy_SysClk_ClkPwrInit();
#endif
-
- /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
- SystemCoreClockUpdate();
-
+
+ #if (!defined(CY_DEVICE_SECURE))
+ /* Set accurate flash wait states */
+ #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
+ Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+ #endif
+
+ /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+ SystemCoreClockUpdate();
+ #ifndef CY_CFG_SYSCLK_ILO_ENABLED
+ #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+ /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */
+ Cy_SysLib_DelayUs(200U);
+ #endif
+ Cy_SysClk_IloDisable();
+ Cy_SysClk_IloHibernateOn(false);
+ #endif
+
+ #endif /* (!defined(CY_DEVICE_SECURE)) */
+
+#if defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED)
+ Cy_SysClk_EcoPrescalerInit();
+#endif /* defined(CY_CFG_SYSCLK_ECO_PRESCALER_ENABLED) */
+ #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+ Cy_SysClk_ClkAltSysTickInit();
+ #endif
+
+ /* Configure HF clocks CSV */
+ #ifdef CY_CFG_SYSCLK_CLKHF0_CSV_ENABLED
+ Cy_SysClk_ClkHf0CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF1_CSV_ENABLED
+ Cy_SysClk_ClkHf1CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF2_CSV_ENABLED
+ Cy_SysClk_ClkHf2CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF3_CSV_ENABLED
+ Cy_SysClk_ClkHf3CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF4_CSV_ENABLED
+ Cy_SysClk_ClkHf4CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF5_CSV_ENABLED
+ Cy_SysClk_ClkHf5CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF6_CSV_ENABLED
+ Cy_SysClk_ClkHf6CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF7_CSV_ENABLED
+ Cy_SysClk_ClkHf7CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF8_CSV_ENABLED
+ Cy_SysClk_ClkHf8CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF9_CSV_ENABLED
+ Cy_SysClk_ClkHf9CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF10CSV_ENABLED
+ Cy_SysClk_ClkHf10CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF11_CSV_ENABLED
+ Cy_SysClk_ClkHf11CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF12_CSV_ENABLED
+ Cy_SysClk_ClkHf12CsvInit();
+ #endif
+ #ifdef CY_CFG_SYSCLK_CLKHF13_CSV_ENABLED
+ Cy_SysClk_ClkHf13CsvInit();
+ #endif
+
+ /* Configure LF clocks CSV */
+ #ifdef CY_CFG_SYSCLK_CLKLF_CSV_ENABLED
+ Cy_SysClk_ClkLfCsvInit();
+ #endif
#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
- cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
-#endif //defined (CY_USING_HAL)
+ if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj)))
+ {
+ CY_HALT();
+ }
+ if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj)))
+ {
+ CY_HALT();
+ }
+ if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj)))
+ {
+ CY_HALT();
+ }
+ if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj)))
+ {
+ CY_HALT();
+ }
+ if(CY_RSLT_SUCCESS != (cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj)))
+ {
+ CY_HALT();
+ }
+#endif /* defined (CY_USING_HAL) */
}
diff --git a/boot/cypress/platforms/BSP/PSOC6/cycfg_system.h b/boot/cypress/platforms/BSP/PSOC6/cycfg_system.h
index 581aeda..4872e19 100644
--- a/boot/cypress/platforms/BSP/PSOC6/cycfg_system.h
+++ b/boot/cypress/platforms/BSP/PSOC6/cycfg_system.h
@@ -1,86 +1,103 @@
/*******************************************************************************
-* File Name: cycfg_system.h
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * File Name: cycfg_system.h
+ *
+ * Description:
+ * System configuration
+ * This file was automatically generated and should not be modified.
+ * Configurator Backend 3.30.0
+ * device-db 4.5.20.7163
+ * mtb-pdl-cat1 3.100.0.38033
+ *
+ *******************************************************************************
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ******************************************************************************/
#if !defined(CYCFG_SYSTEM_H)
#define CYCFG_SYSTEM_H
+#include "cycfg_notices.h"
#include "cy_sysclk.h"
-#include "cy_systick.h"
-#if defined (CY_USING_HAL)
- #include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
+#include "cy_pra.h"
+#include "cy_pra_cfg.h"
+#include "cy_ble_clk.h"
#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined (CY_USING_HAL)
+#include "cyhal_hwmgr.h"
+#endif /* defined (CY_USING_HAL) */
#if defined(__cplusplus)
extern "C" {
-#endif
+#endif /* defined(__cplusplus) */
#define cpuss_0_dap_0_ENABLED 1U
#define srss_0_clock_0_ENABLED 1U
-#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
#define srss_0_clock_0_bakclk_0_ENABLED 1U
#define srss_0_clock_0_fastclk_0_ENABLED 1U
#define srss_0_clock_0_fll_0_ENABLED 1U
#define srss_0_clock_0_hfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKHF0 0UL
-#define srss_0_clock_0_hfclk_2_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF2 2UL
-#define srss_0_clock_0_hfclk_3_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF3 3UL
-#define srss_0_clock_0_hfclk_4_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF4 4UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
#define srss_0_clock_0_ilo_0_ENABLED 1U
#define srss_0_clock_0_imo_0_ENABLED 1U
#define srss_0_clock_0_lfclk_0_ENABLED 1U
#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
#define srss_0_clock_0_pathmux_0_ENABLED 1U
#define srss_0_clock_0_pathmux_1_ENABLED 1U
#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0
#define srss_0_clock_0_pll_0_ENABLED 1U
-#define srss_0_clock_0_pll_1_ENABLED 1U
#define srss_0_clock_0_slowclk_0_ENABLED 1U
-#define srss_0_clock_0_timerclk_0_ENABLED 1U
#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
- extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
-#endif //defined (CY_USING_HAL)
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif /* defined (CY_USING_HAL) */
void init_cycfg_system(void);
#if defined(__cplusplus)
}
-#endif
-
+#endif /* defined(__cplusplus) */
#endif /* CYCFG_SYSTEM_H */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/system_psoc6_cm0plus.c b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/system_psoc6_cm0plus.c
index 52927b3..dc25a4f 100644
--- a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/system_psoc6_cm0plus.c
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM0P/system_psoc6_cm0plus.c
@@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6_cm0plus.c
-* \version 2.95.1
+* \version 2.100
*
* The device system-source file.
*
********************************************************************************
* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
+* Copyright 2016-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,6 +30,597 @@
#include "cy_sysclk.h"
#include "cy_wdt.h"
+#if (defined(CY_DEVICE_TVIIBE))
+#include "cmsis_compiler.h"
+
+#include "tviibe_partition.h"
+
+#define CY_SYS_CM4_PWR_CTL_KEY_OPEN (0x05FAUL)
+#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
+#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR (0x000003FFUL)
+
+static void EnableEcc(void);
+static void PrepareSystemCallInfrastructure(void);
+
+extern uint32_t Cy_u32StartupStackStartAddress;
+extern uint32_t Cy_u32StartupStackEndAddress;
+extern cy_israddress __ramVectors[];
+
+/* Interrupt Logic */
+
+static void SystemIrqInit(void);
+void Cy_DefaultUserHandler(void);
+
+#define DEFAULT_HANDLER_NAME Cy_DefaultUserHandler
+
+CY_NOINIT cy_israddress Cy_SystemIrqUserTable[CPUSS_SYSTEM_INT_NR] ;
+CY_NOINIT cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer ;
+__STATIC_FORCEINLINE void CM0_CpuIntr_Handler(uint8_t intrNum);
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (100000000UL)
+
+/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M7_0) or CLK_FAST(Cortex-M7_1) system core clock */
+CY_NOINIT uint32_t SystemCoreClock ;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_Hfclk0FreqHz ;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_PeriClkFreqHz ;
+
+/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_AhbFreqHz ;
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
+
+CY_NOINIT uint32_t cy_delayFreqKhz ;
+CY_NOINIT uint8_t cy_delayFreqMhz ;
+
+
+/*****************************************************************************
+* Global variable definitions (declared in header file with 'extern')
+*****************************************************************************/
+// CAUTION: Static or global initialized and non-const variables will not have their init value yet!
+
+
+#define SRAM_BEGIN_ADDR (BASE_SRAM_CM0P)
+#define SRAM_END_ADDR (CY_SRAM_BASE + CY_SRAM_SIZE)
+#define STARTUP_STACK_OFFSEST (0x100) /* 32 2-words are cleaned by startup */
+
+#define ECC_INIT_WIDTH_BYTES 8
+#define SROM_VECTOR_TABLE_BASE_ADDRESS 0x00000000
+#define VECTOR_TABLE_OFFSET_IRQ0 0x40
+#define VECTOR_TABLE_OFFSET_IRQ1 0x44
+
+#if defined(__ARMCC_VERSION)
+extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit; /* for (default) One Region model */
+extern void __main(void);
+#elif defined (__GNUC__)
+extern unsigned int __StackTop;
+#elif defined (__ICCARM__)
+extern unsigned int CSTACK$$Limit; /* for (default) One Region model */
+#endif
+
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name: Cy_DefaultUserHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU attempts to call IRQ that has not been mapped to user functions.
+*
+*******************************************************************************/
+void Cy_DefaultUserHandler(void)
+{
+ // This IRQ occurred because CPU attempted to call IRQ that has not been mapped to user function
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux0_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt0 occurs.
+*
+*******************************************************************************/
+void NvicMux0_IRQHandler(void)
+{
+ CM0_CpuIntr_Handler(0);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux1_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt0 occurs.
+*
+*******************************************************************************/
+void NvicMux1_IRQHandler(void)
+{
+ CM0_CpuIntr_Handler(1);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux2_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt2 occurs.
+*
+*******************************************************************************/
+void NvicMux2_IRQHandler(void)
+{
+ CM0_CpuIntr_Handler(2);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux3_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt3 occurs.
+*
+*******************************************************************************/
+void NvicMux3_IRQHandler(void)
+{
+ CM0_CpuIntr_Handler(3);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux4_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt4 occurs.
+*
+*******************************************************************************/
+void NvicMux4_IRQHandler(void)
+{
+ CM0_CpuIntr_Handler(4);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux5_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt5 occurs.
+*
+*******************************************************************************/
+void NvicMux5_IRQHandler(void)
+{
+ CM0_CpuIntr_Handler(5);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux6_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt6 occurs.
+*
+*******************************************************************************/
+void NvicMux6_IRQHandler(void)
+{
+ CM0_CpuIntr_Handler(6);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux7_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt7 occurs.
+*
+*******************************************************************************/
+void NvicMux7_IRQHandler(void)
+{
+ CM0_CpuIntr_Handler(7);
+}
+
+/*******************************************************************************
+* Function Name: CM0_CpuIntr_Handler
+****************************************************************************//**
+*
+* The Inline handler for CPU interrupt.
+* The system interrupt mapped to CPU interrupt will be fetched and executed
+*
+*******************************************************************************/
+__STATIC_FORCEINLINE void CM0_CpuIntr_Handler(uint8_t intrNum)
+{
+ uint32_t system_int_idx;
+ cy_israddress handler;
+
+ if((_FLD2VAL(CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM0_INT_STATUS[intrNum])))
+ {
+ system_int_idx = _FLD2VAL(CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM0_INT_STATUS[intrNum]);
+ handler = Cy_SystemIrqUserTable[system_int_idx];
+ if(handler != NULL)
+ {
+ handler(); // jump to system interrupt handler
+ }
+ }
+ else
+ {
+ // Triggered by software or because software cleared a peripheral interrupt flag but did not clear the pending flag at NVIC
+ }
+ NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
+}
+
+/*******************************************************************************
+* Function Name: SystemIrqInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+static void SystemIrqInit(void)
+{
+ for (int i=0; i<(int)CPUSS_SYSTEM_INT_NR; i++)
+ {
+ Cy_SystemIrqUserTable[i] = DEFAULT_HANDLER_NAME;
+ }
+
+ Cy_SysInt_SystemIrqUserTableRamPointer = Cy_SystemIrqUserTable;
+}
+
+/** Define an abstract type for the chosen ECC initialization granularity */
+typedef uint64_t ecc_init_width_t;
+
+/* Provide empty __WEAK implementation for the low-level initialization
+ routine required by the RTOS-enabled applications.
+ clib-support library provides FreeRTOS-specific implementation:
+ https://github.com/Infineon/clib-support */
+void cy_toolchain_init(void);
+__WEAK void cy_toolchain_init(void)
+{
+}
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+/* GCC: newlib crt0 _start executes software_init_hook.
+ The cy_toolchain_init hook provided by clib-support library must execute
+ after static data initialization and before static constructors. */
+void software_init_hook();
+void software_init_hook()
+{
+ cy_toolchain_init();
+}
+#elif defined(__ICCARM__)
+/* Initialize data section */
+void __iar_data_init3(void);
+
+/* Call the constructors of all global objects */
+void __iar_dynamic_initialization(void);
+
+#else
+/**/
+#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */
+
+
+void CyMain(void)
+{
+#if defined(__ICCARM__)
+ /* Initialize data section */
+ __iar_data_init3();
+
+ /* Initialization hook for RTOS environment */
+ cy_toolchain_init();
+
+ /* Call the constructors of all global objects */
+ __iar_dynamic_initialization();
+#endif
+
+ __PROGRAM_START();
+}
+
+
+/******************************************************************************/
+// TVIIBE SystemInit
+void SystemInit(void)
+{
+ /* Startup Init */
+ EnableEcc();
+ PrepareSystemCallInfrastructure();
+ /* Startup Init Done */
+
+ Cy_PDL_Init(CY_DEVICE_CFG);
+ Cy_WDT_Unlock();
+ Cy_WDT_Disable();
+
+ // Call custom user system init function (assuming weak ref was overridden by user)
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+
+ SystemIrqInit();
+}
+
+
+/*******************************************************************************
+* Function Name: EnableEcc
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+static void EnableEcc(void)
+{
+ /* Enable ECC checking in SRAM controllers again (had been switched off by assembly startup code) */
+ CPUSS->RAM0_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
+#if (CPUSS_RAMC1_PRESENT == 1u)
+ CPUSS->RAM1_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
+#endif
+#if (CPUSS_RAMC2_PRESENT == 1u)
+ CPUSS->RAM2_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
+#endif
+}
+
+
+/**
+ *****************************************************************************
+ ** Prepares necessary settings to get SROM system calls working
+ **
+ ** \return none
+ *****************************************************************************/
+static void PrepareSystemCallInfrastructure(void)
+{
+ const uint8_t u8Irq0Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ0 / 4);
+ const uint8_t u8Irq1Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ1 / 4);
+ uint32_t * const pu32RamTable = (uint32_t *) __ramVectors;
+ uint32_t * const pu32SromTable = (uint32_t *) SROM_VECTOR_TABLE_BASE_ADDRESS;
+
+ // Use IRQ0 and IRQ1 handlers from SROM vector table
+ pu32RamTable[u8Irq0Index] = pu32SromTable[u8Irq0Index];
+ pu32RamTable[u8Irq1Index] = pu32SromTable[u8Irq1Index];
+
+ NVIC_SetPriority(NvicMux0_IRQn, 1);
+ NVIC_SetPriority(NvicMux1_IRQn, 0);
+ NVIC_EnableIRQ(NvicMux0_IRQn);
+ NVIC_EnableIRQ(NvicMux1_IRQn);
+
+ // Only item left is clearing of PRIMASK:
+ // This should be done by the application at a later point in time (e.g. in main())
+}
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the app
+ * generated strong function.
+ */
+}
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pathFreqHz;
+ uint32_t clkHfPath;
+
+ /* Get frequency for the high-frequency clock*/
+ clkHfPath = CY_SYSCLK_CLK_CORE_HF_PATH_NUM;
+
+ pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+ SystemCoreClock = pathFreqHz;
+
+ cy_Hfclk0FreqHz = SystemCoreClock;
+
+ /* Get Peripheral clock Frequency*/
+ clkHfPath = CY_SYSCLK_CLK_PERI_HF_PATH_NUM;
+
+ pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+ cy_PeriClkFreqHz = pathFreqHz;
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqMhz = (uint32_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+
+ /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
+ cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysGetCM4Status
+****************************************************************************//**
+*
+* Returns the Cortex-M4 core power mode.
+*
+* \return \ref group_system_config_cm4_status_macro
+*
+*******************************************************************************/
+uint32_t Cy_SysGetCM4Status(void)
+{
+ uint32_t regValue;
+
+ /* Get current power mode */
+ regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
+
+ return (regValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysEnableCM4
+****************************************************************************//**
+*
+* Sets vector table base address and enables the Cortex-M4 core.
+*
+* \note If the CPU is already enabled, it is reset and then enabled.
+*
+* \param vectorTableOffset The offset of the vector table base address from
+* memory address 0x00000000. The offset should be multiple to 1024 bytes.
+*
+*******************************************************************************/
+void Cy_SysEnableCM4(uint32_t vectorTableOffset)
+{
+ uint32_t regValue;
+ uint32_t interruptState;
+ uint32_t cpuState;
+
+ CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ cpuState = Cy_SysGetCM4Status();
+ if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
+ {
+ Cy_SysResetCM4();
+ }
+
+ CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_ENABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysDisableCM4
+****************************************************************************//**
+*
+* Disables the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
+* CPU.
+*
+*******************************************************************************/
+void Cy_SysDisableCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_DISABLED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysRetainCM4
+****************************************************************************//**
+*
+* Retains the Cortex-M4 core and exists without waiting for the mode to take
+* effect.
+*
+* \note The retained mode can be entered only from the enabled mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysRetainCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RETAINED;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysResetCM4
+****************************************************************************//**
+*
+* Resets the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \note The reset mode can not be entered from the retained mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysResetCM4(void)
+{
+ uint32_t interruptState;
+ uint32_t regValue;
+
+ interruptState = Cy_SysLib_EnterCriticalSection();
+
+ regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+ regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+ regValue |= CY_SYS_CM4_STATUS_RESET;
+ CPUSS->CM4_PWR_CTL = regValue;
+
+ while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+ {
+ /* Wait for the power mode to take effect */
+ }
+
+ Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+#else /* End of TVIIBE section, start of PSoC 6 section */
+
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
#include "cy_ipc_pipe.h"
@@ -215,7 +806,7 @@
#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
#if defined(CY_DEVICE_SECURE)
- /* Initialize Protected Regsiter Access driver. */
+ /* Initialize Protected Register Access driver. */
Cy_PRA_Init();
#endif /* defined(CY_DEVICE_SECURE) */
}
@@ -513,5 +1104,6 @@
}
#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+#endif /* (defined(CY_DEVICE_TVIIBE)) */
/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/system_psoc6_cm4.c b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/system_psoc6_cm4.c
index 2c766c1..b5dada0 100644
--- a/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/system_psoc6_cm4.c
+++ b/boot/cypress/platforms/BSP/PSOC6/system/COMPONENT_CM4/system_psoc6_cm4.c
@@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
-* \version 2.95.1
+* \version 2.100
*
* The device system-source file.
*
********************************************************************************
* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
+* Copyright 2016-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -30,6 +30,309 @@
#include "cy_sysclk.h"
#include "cy_wdt.h"
+#if (defined(CY_DEVICE_TVIIBE))
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (8000000UL)
+
+/** Default system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL)
+
+/* SCB->CPACR */
+#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u)
+
+/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M4_0) system core clock */
+CY_NOINIT uint32_t SystemCoreClock ;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_Hfclk0FreqHz ;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_PeriClkFreqHz ;
+
+/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_AhbFreqHz ;
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u)
+#define CY_DELAY_1K_THRESHOLD (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u)
+
+CY_NOINIT uint32_t cy_delayFreqKhz ;
+
+CY_NOINIT uint8_t cy_delayFreqMhz ;
+
+/* Interrupt Logic */
+
+void Cy_DefaultUserHandler(void);
+
+#define DEFAULT_HANDLER_NAME Cy_DefaultUserHandler
+
+CY_NOINIT cy_israddress Cy_SystemIrqUserTable[CPUSS_SYSTEM_INT_NR] ;
+
+CY_NOINIT cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer ;
+
+void CM4_CpuIntr_Handler(uint8_t intrNum);
+
+/*******************************************************************************
+* Function Name: Cy_DefaultUserHandler
+****************************************************************************//**
+*
+*The Handler is called when the CPU attempts to call IRQ that has not been mapped to user functions.
+*
+*
+*******************************************************************************/
+void Cy_DefaultUserHandler(void)
+{
+ // This IRQ occurred because CPU attempted to call IRQ that has not been mapped to user function
+ while(1);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux0_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt0 occurs.
+*
+*******************************************************************************/
+void NvicMux0_IRQHandler(void)
+{
+ CM4_CpuIntr_Handler(0);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux1_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt0 occurs.
+*
+*******************************************************************************/
+void NvicMux1_IRQHandler(void)
+{
+ CM4_CpuIntr_Handler(1);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux2_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt2 occurs.
+*
+*******************************************************************************/
+void NvicMux2_IRQHandler(void)
+{
+ CM4_CpuIntr_Handler(2);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux3_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt3 occurs.
+*
+*******************************************************************************/
+void NvicMux3_IRQHandler(void)
+{
+ CM4_CpuIntr_Handler(3);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux4_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt4 occurs.
+*
+*******************************************************************************/
+void NvicMux4_IRQHandler(void)
+{
+ CM4_CpuIntr_Handler(4);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux5_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt5 occurs.
+*
+*******************************************************************************/
+void NvicMux5_IRQHandler(void)
+{
+ CM4_CpuIntr_Handler(5);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux6_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt6 occurs.
+*
+*******************************************************************************/
+void NvicMux6_IRQHandler(void)
+{
+ CM4_CpuIntr_Handler(6);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux7_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt7 occurs.
+*
+*******************************************************************************/
+void NvicMux7_IRQHandler(void)
+{
+ CM4_CpuIntr_Handler(7);
+}
+
+/*******************************************************************************
+* Function Name: CM4_CpuIntr_Handler
+****************************************************************************//**
+*
+* The Inline handler for CPU interrupt.
+* The system interrupt mapped to CPU interrupt will be fetched and executed
+*
+*******************************************************************************/
+void CM4_CpuIntr_Handler(uint8_t intrNum)
+{
+ uint32_t system_int_idx;
+ cy_israddress handler;
+
+ if((_FLD2VAL(CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM4_INT_STATUS[intrNum])))
+ {
+ system_int_idx = _FLD2VAL(CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM4_INT_STATUS[intrNum]);
+ handler = Cy_SystemIrqUserTable[system_int_idx];
+ handler(); // jump to system interrupt handler
+ }
+ NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
+}
+
+/*******************************************************************************
+* Function Name: SystemIrqInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+void SystemIrqInit(void)
+{
+ for (int i=0; i<(int)CPUSS_SYSTEM_INT_NR; i++)
+ {
+ Cy_SystemIrqUserTable[i] = DEFAULT_HANDLER_NAME;
+ }
+
+ Cy_SysInt_SystemIrqUserTableRamPointer = Cy_SystemIrqUserTable;
+}
+
+/*******************************************************************************
+* Function Name: SystemInit
+****************************************************************************//**
+* \cond
+* Initializes the system:
+* - Unlocks and disables WDT.
+* - Calls the Cy_SystemInit() function.
+* - Calls \ref SystemCoreClockUpdate().
+* \endcond
+*******************************************************************************/
+void SystemInit(void)
+{
+ // TVIIBE SystemInit
+ Cy_PDL_Init(CY_DEVICE_CFG);
+
+ Cy_SystemInit();
+ SystemCoreClockUpdate();
+
+ SystemIrqInit();
+}
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+ /* Empty weak function. The actual implementation to be in the user application
+ * as strong function.
+ */
+}
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock, \ref
+* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+ uint32_t pathFreqHz;
+ uint32_t clkHfPath;
+
+ /* Get frequency for the high-frequency clock # 0 */
+ clkHfPath = CY_SYSCLK_CLK_CORE_HF_PATH_NUM;
+
+ pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+ SystemCoreClock = pathFreqHz;
+
+ cy_Hfclk0FreqHz = SystemCoreClock;
+
+ /* Get frequency for the high-frequency clock # 2 , which is used for PERI PCLK*/
+ clkHfPath = CY_SYSCLK_CLK_PERI_HF_PATH_NUM;
+
+ pathFreqHz = Cy_SysClk_ClkHfGetFrequency(clkHfPath);
+
+ cy_PeriClkFreqHz = pathFreqHz;
+
+ /* Sets clock frequency for Delay API */
+ cy_delayFreqMhz = (uint32_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+ cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+
+ /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
+ cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
+}
+
+/*******************************************************************************
+* Function Name: Cy_SystemInitFpuEnable
+****************************************************************************//**
+*
+* Enables the FPU if it is used. The function is called from the startup file.
+*
+*******************************************************************************/
+void Cy_SystemInitFpuEnable(void)
+{
+ #if defined (__FPU_USED) && (__FPU_USED == 1U)
+ uint32_t interruptState;
+ interruptState = __get_PRIMASK();
+ __disable_irq();
+ SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
+ __DSB();
+ __ISB();
+ __set_PRIMASK(interruptState);
+ #endif /* (__FPU_USED) && (__FPU_USED == 1U) */
+}
+
+#else /* PSoC 6 */
+
#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
#include "cy_ipc_sema.h"
#include "cy_ipc_pipe.h"
@@ -357,5 +660,6 @@
}
#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
+#endif /* (defined(CY_DEVICE_TVIIBE)) */
/* [] END OF FILE */
diff --git a/boot/cypress/platforms/BSP/PSOC6/system/system_psoc6.h b/boot/cypress/platforms/BSP/PSOC6/system/system_psoc6.h
index eb65a16..c4b2645 100644
--- a/boot/cypress/platforms/BSP/PSOC6/system/system_psoc6.h
+++ b/boot/cypress/platforms/BSP/PSOC6/system/system_psoc6.h
@@ -1,12 +1,12 @@
/***************************************************************************//**
* \file system_psoc6.h
-* \version 2.95.1
+* \version 2.100
*
* \brief Device system header file.
*
********************************************************************************
* \copyright
-* Copyright 2016-2021 Cypress Semiconductor Corporation
+* Copyright 2016-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -69,7 +69,7 @@
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
-* https://github.com/cypresssemiconductorco/psoc6cm0p
+* https://github.com/Infineon/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
@@ -106,7 +106,7 @@
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
-* https://github.com/cypresssemiconductorco/psoc6cm0p
+* https://github.com/Infineon/psoc6cm0p
*
* \note The linker files provided with the PDL are generic and handle all common
* use cases. Your project may not use every section defined in the linker files.
@@ -156,7 +156,7 @@
* Cy_SysEnableCM4() function call.
* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
* More about CM0+ prebuilt images, see here:
-* https://github.com/cypresssemiconductorco/psoc6cm0p
+* https://github.com/Infineon/psoc6cm0p
*
* Change the flash and RAM sizes by editing the macros value in the
* linker files for both CPUs:
@@ -240,7 +240,7 @@
* clib-support library that provides newlib-compatible implementations of
* 'sbrk', '__malloc_lock' and '__malloc_unlock':
* <br>
-* https://github.com/cypresssemiconductorco/clib-support.
+* https://github.com/Infineon/clib-support.
*
* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler
* - <b>Editing source code files</b>\n
@@ -334,6 +334,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
+* <td rowspan="1">2.100</td>
+* <td>Added support for TRAVEO™ II Body Entry devices.</td>
+* <td>Code enhancement and support for new devices.</td>
+* </tr>
+* <tr>
* <td rowspan="1">2.95.1</td>
* <td>Restructured documentation.</td>
* <td>Documentation update.</td>
@@ -341,7 +346,7 @@
* <tr>
* <td rowspan="1">2.95</td>
* <td>Update FPU enable function with CMSIS macros to disable/enable interrupts</td>
-* <td>Move to stadnard inline CMSIS ARM macros</td>
+* <td>Move to standard inline CMSIS ARM macros</td>
* </tr>
* <tr>
* <td rowspan="2">2.91</td>
@@ -552,7 +557,13 @@
* <i>(USER SETTING)</i>
*******************************************************************************/
#if !defined (CY_CORTEX_M4_APPL_ADDR)
- #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
+ // Include a partition file for Traveo II BE devices
+ #if (defined (CY_DEVICE_SERIES_CYT2B6) || defined (CY_DEVICE_SERIES_CYT2B7) || defined (CY_DEVICE_SERIES_CYT2B9) || defined (CY_DEVICE_SERIES_CYT2BL))
+ #include "tviibe_partition.h"
+ #define CY_CORTEX_M4_APPL_ADDR BASE_CODE_FLASH_CM4_0
+ #else
+ #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
+ #endif
#endif /* (CY_CORTEX_M4_APPL_ADDR) */
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp.c b/boot/cypress/platforms/BSP/XMC7000/cybsp.c
index 00c25fd..6f08f7a 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp.c
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp.h b/boot/cypress/platforms/BSP/XMC7000/cybsp.h
index cd27cf6..7ba085f 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp.h
@@ -6,7 +6,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h b/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
index 30363dc..5378efd 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp_doc.h
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h b/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
index a6c9bad..b8f3546 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp_hw_config.h
@@ -7,7 +7,7 @@
*
***************************************************************************************************
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/XMC7000/cybsp_types.h b/boot/cypress/platforms/BSP/XMC7000/cybsp_types.h
index aeb7023..c20d555 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cybsp_types.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cybsp_types.h
@@ -1,6 +1,6 @@
/***********************************************************************************************//**
* \copyright
- * Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.c b/boot/cypress/platforms/BSP/XMC7000/cycfg.c
index 734470f..18ad9eb 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.c
@@ -10,7 +10,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg.h b/boot/cypress/platforms/BSP/XMC7000/cycfg.h
index 9528ebe..c65929a 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg.h
@@ -10,7 +10,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
index 4b16b75..90d5a10 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.c
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
index 0bb0ba4..1c8e274 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_clocks.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
index 318279d..958f2a3 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_notices.h
@@ -10,7 +10,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
index 3701533..42ffcbb 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.c
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
index cb08758..decbc73 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_peripherals.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
index 9724f7d..1787b68 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.c
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
index 29b5cd9..f27f86d 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_pins.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
index 9ab1bcf..c2d6e16 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.c
@@ -7,7 +7,7 @@
* QSPI Configurator 4.30.0.1865
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
index 7507b44..b834288 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_qspi_memslot.h
@@ -7,7 +7,7 @@
* QSPI Configurator 4.30.0.1865
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
index 0932043..6a568a0 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_routing.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
index 5debda7..7922f27 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.c
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
index e214cda..93575ee 100644
--- a/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
+++ b/boot/cypress/platforms/BSP/XMC7000/cycfg_system.h
@@ -9,7 +9,7 @@
* mtb-pdl-cat1 3.600.0.33254
*
*******************************************************************************
- * Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld
index 96d2f68..fa98705 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/linker.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
index f110bef..7a4e9fd 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM0P/system_cm0plus.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h
index 3540379..cd13ca8 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cat1c.h
@@ -1,3 +1,21 @@
+/*******************************************************************************
+* \copyright
+* Copyright 2025 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
#ifndef __STARTUP_CAT1C_H__
#define __STARTUP_CAT1C_H__
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
index 0415a87..ccdfec2 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/startup_cm7.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h
index 8c67ae9..e6b7373 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cat1c.h
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
index 488f191..80058f3 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
+++ b/boot/cypress/platforms/BSP/XMC7000/system/COMPONENT_CM7/system_cm7.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h
index 3540379..cd13ca8 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/startup_cat1c.h
@@ -1,3 +1,21 @@
+/*******************************************************************************
+* \copyright
+* Copyright 2025 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
#ifndef __STARTUP_CAT1C_H__
#define __STARTUP_CAT1C_H__
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h b/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
index 3fe0771..6f64626 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/system_cat1c.h
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2021 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h b/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
index b6a3f2d..9c76d22 100644
--- a/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
+++ b/boot/cypress/platforms/BSP/XMC7000/system/xmc7xxx_partition.h
@@ -1,3 +1,21 @@
+/*******************************************************************************
+* \copyright
+* Copyright 2025 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
#if !defined(LAYOUT_CAT1C_H)
#define LAYOUT_CAT1C_H
diff --git a/boot/cypress/platforms/CYW20829.md b/boot/cypress/platforms/CYW20829.md
index 08a985e..d6e546b 100644
--- a/boot/cypress/platforms/CYW20829.md
+++ b/boot/cypress/platforms/CYW20829.md
@@ -2,47 +2,45 @@
### Prerequisites
-#### Cysecuretools
+#### Edgeprotecttools
-The CYW20829/CYW89829 devices have a set of security features. A special tool called `cysecuretools` is required to use most of them.
+The CYW20829/CYW89829 devices have a set of security features. A special tool called `edgeprotecttools` is required to use most of them.
-`Cysecuretools` is a Python3 package, which can be installed using the conventional `python pip` packet manager:
+`Edgeprotecttools` is a Python package, which can be installed using the conventional `python pip` packet manager:
- python -m pip install cysecuretools
+ python -m pip install edgeprotecttools
-`Cysecuretools` is used for reprovisioning of the chip, revocation of keys, security counter updates, image encryption, and more. For more details on functionality, go to [https://pypi.org/project/cysecuretools](https://pypi.org/project/cysecuretools) or [https://github.com/Infineon/cysecuretools#provision-device](https://github.com/Infineon/cysecuretools#provision-device)
+`Edgeprotecttools` is used for reprovisioning of the chip, revocation of keys, security counter updates, image encryption, and more. For more details on functionality, go to [https://pypi.org/project/edgeprotecttools](https://pypi.org/project/edgeprotecttools) or [https://github.com/Infineon/edgeprotecttools#provision-device](https://github.com/Infineon/edgeprotecttools#provision-device)
-Invocation of cysecuretools is build-in post-build jobs for `MCUBootApp` and `BlinkyApp`, so the user gets ready to use images after build.
+Invocation of edgeprotecttools is build-in post-build jobs for `MCUBootApp` and `BlinkyApp`, so the user gets ready to use images after build.
+
+Requirements for `Edgeprotecttools` installation can be found [here](https://github.com/Infineon/edgeprotecttools?tab=readme-ov-file#prerequisites).
### MCUBootApp specifics
-The PSoC CYW20829/CYW89829 can work in two modes - Non-Secure and Secure. In the Non-Secure (NORMAL_NO_SECURE) mode the CYW20829/CYW89829 works as a 'usual' Infineon chip. In the SECURE mode the following functionality becomes available:
+The CYW20829/CYW89829 silicons can be provisioned in two modes - Non-Secure and Secure. In the Non-Secure (NORMAL_NO_SECURE) mode the CYW20829/CYW89829 works as a 'usual' Infineon chip. In the SECURE mode the following functionality becomes available:
- signing of images;
- rollback protection (hardware secure counter).
The work with the CYW20829/CYW89829 chips begin from the initialization of the project with the following device provisioning in the desired lifecycle - Non-Secure on Secure.
### Device and environment initialization
-For the cysecuretools environment setup, the MCUboot `boot/cypress` folder is used.
+For the edgeprotecttools environment setup, the MCUboot `boot/cypress` folder is used.
To create a common configuration, use:
- cysecuretools -t cyw20829 init
+ edgeprotecttools -t cyw20829 init
-To configure an OpenOCD package patch (via ModusToolbox™ by default):
+To configure an OpenOCD package path (via ModusToolbox™ Programming Tools by default):
- cysecuretools set-ocd --name openocd --path C:/Users/%USERNAME%/ModusToolbox/tools_3.2/openocd
+ edgeprotecttools set-ocd --name openocd --path C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
-This is enough for a NORMAL_NO_SECURE lifecycle. But for SECURE `LCS`, a few more steps are necessary.
+For SECURE `LCS`, a few more steps are necessary. You will need to generate an RSA key pair (or copy it to the keys folder, if it was generated previously), to provision a chip in Secure mode:
-You will need to generate an RSA key pair (or copy it to the keys folder, if it was generated previously), to provision a chip in Secure mode:
-
- cysecuretools -t cyw20829 -p policy/policy_secure.json create-key -k N
-
-where N is the key number, zero or one.
+ edgeprotecttools -t cyw20829 -p policy/policy_secure.json create-key -k 0
To get access to the chip after provisioning, a debug certificate is required:
- cysecuretools -t cyw20829 -p policy/policy_secure.json debug-certificate -t packets/debug_cert.json -o packets/debug_cert.bin -k N
+ edgeprotecttools -t cyw20829 -p policy/policy_secure.json debug-certificate -t packets/debug_cert.json -o packets/debug_cert.bin -k N
where N is the key number, zero or one.
@@ -50,20 +48,152 @@
For the first provision of the CYW20829 chip, use:
- cysecuretools -t cyw20829 -p policy/policy_%LCS%.json provision-device
+ edgeprotecttools -t cyw20829 -p policy/policy_%LCS%.json provision-device
or
- cysecuretools -t cyw20829 -p policy/policy_reprovisioning_%LCS%.json reprovision-device [--key-id N]
+ edgeprotecttools -t cyw20829 -p policy/policy_reprovisioning_%LCS%.json reprovision-device [--key-id N]
for the following reprovision procedure.
-More details about provisioning and reprovisioning processes you can find in [README_CYW20829.md](https://github.com/Infineon/cysecuretools/blob/master/docs/README_CYW20829.md#command-provision-device)
+More details about provisioning and reprovisioning processes you can find in [README_CYW20829.md](https://github.com/Infineon/edgeprotecttools/blob/master/docs/README_CYW20829.md#command-provision-device)
### Default memory map
The repository provides a set of predefined memory maps in JSON files. They are located in `platforms/memory/CYW20829/flashmap`. One can use the predefined flash map or define your own using the predefined file as a template.
+### Direct-XIP mode support
+
+Additionally to the classic mode with `BOOT` and `UPGRADE` slots, MCUBoot for CYW20829/CYW89829 platform supports the `Direct-XIP` mode. The main difference is that both slots, named `Primary` and `Secondary`, are equal, and the image in one slot has no effect on the other image. In this mode, MCUBoot checks the version of the images and launches the application with the higher version number. The version number can be set via the `IMG_VER` command-line parameter. If both version numbers are equal, the image in the primary slot will be launched. The build number is not taken into account during version comparison; only the major, minor, and patch version numbers are considered.
+In the `Direct-XIP` mode, both images are treated like `UPGRADE` images. This implies that each image must set the `IMG_OK` flag during its first startup. If the `IMG_OK` flag is not set, the corresponding application will be erased, and the application from the other slot will be launched. If neither application sets the `IMG_OK` flag, MCUBoot will erase both applications. The `Direct-XIP` mode supports encrypted images. In this mode, the MCUBootApp and all images are encrypted using the same `AES-CTR` encryption key. For more information, refer to the `Encrypted image support` section.
+Another change is that the `APP_SLOT` command line parameter should be used for application compilation instead of the `IMG_TYPE` parameter. Use `APP_SLOT=1` for the `Primary` slot and `APP_SLOT=2` for the `Secondary`.
+
+To enable the `Direct-XIP` mode, use the appropriate flash map, such as `cyw20829_direct_xip_single.json`
+
+ make clean app APP_NAME=MCUBootApp PLATFORM=CYW20829 FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_direct_xip_single.json
+ make app APP_NAME=BlinkyApp PLATFORM=CYW20829 FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_direct_xip_single.json APP_SLOT=1 IMG_VER=1.0.0+100
+ make app APP_NAME=BlinkyApp PLATFORM=CYW20829 FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_direct_xip_single.json APP_SLOT=2 IMG_VER=2.0.0+200
+
+NOTE: Currently, support for the `Direct-XIP` mode is limited to the `NORMAL_NO_SECURE` lifecycle.
+
+### Skip image validation
+
+To decrease the boot time of MCUBoot, image validation can be skipped before launching the application. This flow is recommended in cases where boot time is more important than reliability. To disable image validation for a selected slot, use the `MCUBOOT_SKIP_VALIDATE_PRIMARY_SLOT=1` or `MCUBOOT_SKIP_VALIDATE_SECONDARY_SLOT=1` command-line parameter.
+To skip image validation entirely, the `MCUBOOT_SKIP_VALIDATE=1` option can be used.
+
+### Direct-XIP APIs
+
+The Direct-XIP API provides a comprehensive set of functions for managing firmware images and their associated metadata in boot slots. This API is designed to facilitate secure and reliable firmware updates in embedded systems and supports operations such as slot validation, image state management, and metadata handling. Below is a summary of the key API functions and their purposes.
+
+- Image Validation:
+Use `boot_validate_slot_for_image_id` to ensure that the firmware image in a slot is valid before executing it. This API is useful when MCUBoot startup validation is disabled.
+
+- Slot Management:
+Use `boot_set_inactive_slot`, `boot_is_slot_inactive`, or `boot_set_pending_slot` to manage the activation and deactivation of firmware slots.
+
+- Metadata Handling:
+Use `boot_find_image_tlv_info` and `boot_read_image_tlv_value` to retrieve and parse metadata associated with firmware images.
+
+- State Inspection:
+Use `boot_get_slot_state` or `boot_get_image_state` to monitor and debug the current state of firmware images in the system.
+
+- Revert Mechanism:
+ Use `boot_set_revert_slot` to mark a slot for erasure on the next reboot if its firmware fails validation.
+
+
+#### Slot Validation and Image Management APIs
+
+ boot_validate_slot_for_image_id
+ Description: Validates the image in a specified slot without performing a boot.
+ Parameters:
+ image_id: Image identifier (starting from 0).
+ slot_id: Slot index (0 for primary, 1 for secondary).
+ Returns: FIH_SUCCESS on success.
+
+ boot_get_image_version
+ Description: Reads the version information (major, minor, patch, and build) from the image header in the specified slot.
+ Parameters:
+ image_id: Image identifier.
+ slot_id: Slot index.
+ ver: Pointer to the structure where version information will be stored.
+ Returns: 0 on success.
+
+ boot_set_inactive_slot
+ Description: Marks the specified slot as inactive.
+ Parameters:
+ image_id: Image identifier.
+ slot_id: Slot index.
+ Returns: 0 on success.
+
+ boot_is_slot_inactive
+ Description: Checks if the specified slot is inactive.
+ Parameters:
+ image_id: Image identifier.
+ slot_id: Slot index.
+ Returns:
+ 1: Slot is inactive.
+ 0: Slot is active.
+ -1: Error occurred.
+
+ boot_set_pending_slot
+ Description: Restores an inactive slot to a pending state, making it bootable in the next cycle.
+ Parameters:
+ image_id: Image identifier.
+ slot_id: Slot index.
+ Returns: 0 on success.
+
+ boot_set_revert_slot
+ Description: Sets the revert state for a slot, indicating that the image will be erased on the next boot if not validated.
+ Parameters:
+ image_id: Image identifier.
+ slot_id: Slot index.
+ Returns: 0 on success.
+
+
+#### Metadata (TLV) Handling APIs
+
+ boot_find_image_tlv_info
+ Description: Finds metadata information (Type-Length-Value) for a specific image and slot, returning the offset and length of the requested TLV entry.
+ Parameters:
+ image_id: Image identifier.
+ slot_id: Slot index.
+ type: TLV type identifier.
+ len: Pointer to store the length of the TLV entry.
+ off: Pointer to store the offset of the TLV entry.
+ Returns: 0 on success, non-zero on error or if the TLV is not found.
+
+ boot_read_image_tlv_value
+ Description: Reads the actual value of a TLV entry from the specified image slot.
+ Parameters:
+ image_id: Image identifier.
+ slot_id: Slot index.
+ type: TLV type identifier.
+ buf: Buffer to store the retrieved TLV value.
+ buf_len: Length of the provided buffer.
+ read_len: Pointer to store the actual number of bytes read.
+ Returns: 0 on success, non-zero on error or insufficient buffer length.
+
+
+#### Slot and Image State Management APIs
+
+ boot_get_slot_state
+ Description: Retrieves the current state of a specified slot without performing image validation.
+ Parameters:
+ image_id: Image identifier.
+ slot_id: Slot index.
+ state: Pointer to store the slot's state information.
+ Returns: 0 on success, non-zero on error.
+
+ boot_get_image_state
+ Description: Retrieves the detailed state of a slot, such as active, inactive, pending, etc.
+ Parameters:
+ image_id: Image identifier.
+ slot_id: Slot index.
+ state: Pointer to store the state information of the slot.
+ Returns: 0 on success, non-zero on error.
+
+A detailed description of the API interfaces can be found in the `boot/bootutil/include/bootutil/bootutil.h` header file.
+
### Encrypted image support
CYW20829/CYW89829 does not have internal flash memory, so both primary and secondary images are located in external memory.
@@ -106,10 +236,15 @@
make clean app APP_NAME=BlinkyApp PLATFORM=CYW20829 BUILDCFG=Debug FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_xip_swap_single.json ENC_IMG=1
+NOTE: In the case where a common AES-CTR key is used to encrypt both the MCUBoot and BlinkyApp applications, MCUBoot should be compiled first. This is because the common NONCE file for the AES-CTR algorithm is generated during the MCUBoot compilation. Since BlinkyApp will use the same NONCE file, it should be compiled after MCUBoot. This also applies to cases where MCUBoot is recompiled and a new NONCE file is generated.
#### Encrypted image support using secured encryption key
-The CYW20829 MCU supports on-the-fly XIP (eXecute In Place) encryption utilizing a provisioned AES-128 key when the device is in a secure lifecycle state (LCS=SECURE)
+The CYW20829 MCU supports on-the-fly XIP (eXecute In Place) encryption utilizing a provisioned AES-128 key in both `SECURE` and `NORMAL_NO_SECURE` lifecycles. SMIF encryption can be enabled only once, during the first device provisioning, and cannot be changed in the future.
+Information about key generation for image encryption and device provisioning can be found in the documentation for the `Edge Protect Tools` utility:
+https://github.com/Infineon/edgeprotecttools/blob/master/docs/README_CYW20829.md#encrypt-the-user-application
+
+NOTE: To enable SMIF encryption in the `NORMAL_NO_SECURE` LCS, you will need at least EdgeProtectTools version 1.5.0, and B0 revision of the silicon (or later).
##### Enabling XIP Encryption
@@ -126,13 +261,13 @@
```
##### Preparing and Encrypting Application Images
-Users must prepare non-encrypted signed images for their applications and perform manual encryption using cysecuretools with the "encrypt" command. This command requires specifying the encryption key, nonce, and image address as the initial vector (IV).
+Users must prepare non-encrypted signed images for their applications and perform manual encryption using edgeprotecttools with the "encrypt" command. This command requires specifying the encryption key, nonce, and image address as the initial vector (IV).
##### Encryption Example
To encrypt your application binary, use the following command:
```sh
-cysecuretools -t cyw20829 encrypt --input BlinkyApp.bin --output BlinkyApp_encrypted.bin --iv 0x08020000 --enckey keys/encrypt_key.bin --nonce ./MCUBootApp/out/CYW20829/Debug/MCUBootApp.signed_nonce.bin
+edgeprotecttools -t cyw20829 encrypt --input BlinkyApp.bin --output BlinkyApp_encrypted.bin --iv 0x08020000 --enckey keys/encrypt_key.bin --nonce ./MCUBootApp/out/CYW20829/Debug/MCUBootApp.signed_nonce.bin
```
**Parameters:**
@@ -144,6 +279,17 @@
By following these steps, you can ensure that your application binaries are securely encrypted and ready for execution on the CYW20829 MCU with on-the-fly XIP encryption enabled.
+##### USE_IMG_TRAILER Parameter Description
+The `USE_IMG_TRAILER` parameter provides developers with the ability to disable the generation of the image trailer and padding between the image body and the trailer, reducing the image size. This feature is useful for encrypted images. Padding bytes in encrypted images are transformed into random data, making the image size non-compressible. Disabling the trailer and padding reduces unnecessary overhead in such cases. By default, this parameter is enabled `USE_IMG_TRAILER=1`.
+
+**Warning:** Disabling the image trailer and padding is supported for Direct-XIP mode only.
+
+To disable the trailer and padding, set `USE_IMG_TRAILER=0` during the build process:
+```sh
+ make app APP_NAME=BlinkyApp PLATFORM=CYW20829 FLASH_MAP=platforms/memory/CYW20829/flashmap/cyw20829_direct_xip_single.json APP_SLOT=1 IMG_VER=1.0.0+100 USE_IMG_TRAILER=0
+```
+NOTE: The application slot must be erased before writing the image when USE_IMG_TRAILER parameter is zero.
+
### Rollback protection Support
As mentioned above, to use the rollback protection feature the device must be transferred to the SECURE lifecycle. The CYW20829/CYW89829 platform has a hardware-supported feature - a non-volatile counter (NV-counter). This feature is used by the MCUboot library to implement the rollback protection counter (security counter). NV-counter on CYW20829/CYW89829 is implemented as an Efuse-type region that can only be incremented. This means, that each time a new counter value is updated - a corresponding number of Efuse is burned.
@@ -182,9 +328,9 @@
`"value": [2, 3]` filed sets corresponding value for image ids. Here `4` would be assigned to image id `1` and `5` to image id `2`.
If the `nv_counter` value is increased in `policy/policy_secure.json` at the provisioning stage, the `nv_counter` value in `policy/policy_reprovisioning_secure.json` must start from the value not less than the value in `policy/policy_secure.json` file.
-More details about provisioning and reprovisioning processes you can find in [README_CYW20829.md](https://github.com/Infineon/cysecuretools/blob/master/docs/README_CYW20829.md#command-provision-device)
+More details about provisioning and reprovisioning processes you can find in [README_CYW20829.md](https://github.com/Infineon/edgeprotecttools/blob/master/docs/README_CYW20829.md#command-provision-device)
-When preparing an image for MCUBootApp with the rollback counter support, the `cysecuretools` signs it with `policy/policy_secure.json` in the post-build stage of `make`. The `nv_counter` value remains the same as one in the chip or sets higher. When `cysecuretools` signs an image, it places the `nv-counter` value and the reprovisioning packet in TLVs with tags 0x50 (bit mask representation of the counter) and 0x51 (reprovisioning packet). MCUBootApp then parses these tags and compares the value supplied with the image against the one stored in the Efuse counter.
+When preparing an image for MCUBootApp with the rollback counter support, the `edgeprotecttools` signs it with `policy/policy_secure.json` in the post-build stage of `make`. The `nv_counter` value remains the same as one in the chip or sets higher. When `edgeprotecttools` signs an image, it places the `nv-counter` value and the reprovisioning packet in TLVs with tags 0x50 (bit mask representation of the counter) and 0x51 (reprovisioning packet). MCUBootApp then parses these tags and compares the value supplied with the image against the one stored in the Efuse counter.
If image counter value is set to higher then defined for this image by `bits_per_cnt` filed in policy, for example, image id 1 is provisioned to have 16 bits for its counter, but image programmed has nv counter value of 20 embedded in TLVs - MCUBootApp would discard it as invalid.
@@ -208,7 +354,7 @@
To update NV-counter for an appropriate image you have to increase NV-counter in the reprovisioning policy `/policy/policy_reprovisioning_secure.json`, after that re-build the `BlinkyApp` and re-program your device.
-The CYW20829/CYW89829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of Efuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `cysecuretools` under `targets/cyw20829/packets/apps`. The `reprovisioning` application is used for NV-counter updates.
+The CYW20829/CYW89829 chip is designed so that the first stage bootloader called `BootROM` has most of the rights to modify the system - it is executed in the privileged protection context. Only BootROM can modify the content of Efuse where the NV counter is stored. BootROM supports the special type of service applications used when the user needs to modify the system. These apps are also provided with `edgeprotecttools` under `targets/cyw20829/packets/apps`. The `reprovisioning` application is used for NV-counter updates.
To enable the rollback counter feature, one have to use a JSON flash map with the `"service_app"` section. Sample flash maps are located in `boot/cypress/platforms/memory/CYW20829/flashmap/hw_rollback_prot`.
@@ -263,14 +409,14 @@
for BlinkyApp with TLVs containing rollback counter data:
- BOOT slot, IMG_ID=1:
- make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=1
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=1
- UPGRADE slot, IMG_ID=1:
make clean_upgrade app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=UPGRADE APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=1
- BOOT slot, IMG_ID=2:
- make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=2
+ make clean_boot app APP_NAME=BlinkyApp PLATFORM=CYW20829 IMG_TYPE=BOOT APP_DEFAULT_POLICY=./policy/policy_reprovisioning_secure.json FLASH_MAP=platforms/memory/CYW20829/flashmap/hw_rollback_prot/cyw20829_xip_swap_multi2.json IMG_ID=2
- UPGRADE slot, IMG_ID=2:
@@ -279,15 +425,15 @@
**Attention!** Don't omit `clean_boot` and `clean_upgrade` to avoid any issues!
### Programming applications
-The HEXes for device programming you can find:
+The HEXes for device programming you can find:
-for MCUBootApp: `MCUBootApp.hex` in the directory 'MCUBootApp/out/CYW20829/*{BUILDCFG}*/
+for MCUBootApp: `MCUBootApp.hex` in the directory 'MCUBootApp/out/CYW20829/*{BUILDCFG}*/'
for BlinkyApp:
- for IMG_ID=1, BOOT slot select `BlinkyApp.hex` inside of 'BlinkyApp/**out**/CYW20829/*{BUILDCFG}*/**boot**/'
- - for IMG_ID=1, UPGRADE slot select `BlinkyApp_upgrade.hex` inside of 'BlinkyApp/**out**/CYW20829/*{BUILDCFG}*/**upgrade**/
+ - for IMG_ID=1, UPGRADE slot select `BlinkyApp_upgrade.hex` inside of 'BlinkyApp/**out**/CYW20829/*{BUILDCFG}*/**upgrade**/'
- for IMG_ID=2, BOOT slot select `BlinkyApp.hex` inside of 'BlinkyApp/**out.id2**/CYW20829/*{BUILDCFG}*/**boot**/'
- - for IMG_ID=1, UPGRADE slot select `BlinkyApp_upgrade.hex` inside of 'BlinkyApp/**out.id2**/CYW20829/*{BUILDCFG}*/**upgrade**/
+ - for IMG_ID=1, UPGRADE slot select `BlinkyApp_upgrade.hex` inside of 'BlinkyApp/**out.id2**/CYW20829/*{BUILDCFG}*/**upgrade**/'
Default **{BUILDCFG}** is 'Debug', so all previous commands for the 'multi-image' case will build a 'Debug' configuration.
@@ -297,13 +443,13 @@
Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
-Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION` and `OPENOCD` variables:
+Open the terminal application and execute the following commands:
- export OPENOCD=/Applications/ModusToolbox/tools_3.2/openocd
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
- $OPENOCD_PATH/bin/openocd -s $OPENOCD_PATH/scripts -c "set ENABLE_ACQUIRE 0" -f $OPENOCD_PATH/scripts/interface/kitprog3.cfg -c "set SMIF_BANKS { 0 {addr 0x60000000 size 0x4000000 psize 0x1000 esize 0x40000} }" -f $OPENOCD_PATH/scripts/target/cyw20829.cfg -c "init; reset init; cmsis_flash init; flash write_image %PATH_TO_APPLICATION%/BlinkyApp.hex; shutdown"
+ $OPENOCD_PATH/bin/openocd -s $OPENOCD_PATH/scripts -f $OPENOCD_PATH/scripts/interface/kitprog3.cfg -c "set SMIF_BANKS { 0 {addr 0x60000000 size 0x100000 psize 0x1000 esize 0x40000} }; set DEBUG_CERTIFICATE ./packets/debug_cert.bin" -f $OPENOCD_PATH/scripts/target/infineon/cyw20829.cfg -c "init; reset init; cmsis_flash init; program ./BlinkyApp/out/CYW20829/Release/upgrade/BlinkyApp.hex; shutdown"
**Warning**
-The application slot is erased by `flash erase_address` before executing the `flash write_image` command.
+The application slot is automatically erased by `flash erase_address` before executing the `program` command.
diff --git a/boot/cypress/platforms/CYW20829.mk b/boot/cypress/platforms/CYW20829.mk
index 02ce47e..ac10910 100644
--- a/boot/cypress/platforms/CYW20829.mk
+++ b/boot/cypress/platforms/CYW20829.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -42,11 +42,6 @@
DEVICE ?= CYW89829B0232
endif
-# If PSVP build is required
-ifeq ($(CYW20829_PSVP), 1)
-SERVICE_APP_PLATFORM_SUFFIX := _psvp
-endif
-
#Led pin default config
LED_PORT_DEFAULT ?= GPIO_PRT0
LED_PIN_DEFAULT ?= 0U
@@ -60,7 +55,12 @@
# Add device name to defines
DEFINES += -D$(DEVICE)
-USE_SWAP_STATUS ?= 1
+USE_SWAP_STATUS ?= 0
+
+ifeq ($(USE_DIRECT_XIP), 1)
+DEFINES += -DMCUBOOT_DIRECT_XIP=1
+DEFINES += -DMCUBOOT_DIRECT_XIP_REVERT=1
+endif
ifeq ($(USE_SWAP_STATUS), 1)
DEFINES += -DUSE_SWAP_STATUS=1
@@ -90,6 +90,8 @@
ifeq ($(APP_NAME), MCUBootApp)
+DEFINES += -DBSP_DISABLE_WDT
+
SMIF_ENC ?= 0
ifeq ($(CYW20829_PSVP), )
@@ -145,6 +147,10 @@
SIGN_ENC := 0
+ifeq ($(SMIF_ENC), 1)
+ SIGN_ENC := 1
+endif
+
###############################################################################
# MCUBootApp service app definitions
###############################################################################
@@ -154,10 +160,6 @@
SERVICE_APP_PATH := $(PRJ_DIR)/packets/apps/reprovisioning$(SERVICE_APP_PLATFORM_SUFFIX)
SERVICE_APP_NAME := cyapp_reprovisioning_signed_icv0
-ifeq ($(SMIF_ENC), 1)
- SIGN_ENC := 1
-endif
-
ifeq ($(ENC_IMG), 1)
SIGN_ENC := 1
endif
@@ -196,11 +198,18 @@
###############################################################################
ifeq ($(APP_NAME), BlinkyApp)
+APP_SLOT ?= 1
+
+ifeq ($(shell [ $(APP_SLOT) -gt 2 ] && echo true), true)
+ $(error APP_SLOT must be 1 or 2)
+endif
+
# Basic settings
LCS ?= NORMAL_NO_SECURE
APPTYPE ?= flash
SIGN_TYPE ?= mcuboot_user_app
SMIF_CRYPTO_CONFIG ?= NONE
+USE_IMG_TRAILER ?= 1
ifeq ($(LCS), NORMAL_NO_SECURE)
APP_DEFAULT_POLICY ?= $(PRJ_DIR)/policy/policy_no_secure.json
@@ -211,12 +220,26 @@
PLATFORM_DEFAULT_ERASED_VALUE := 0xff
# Define start of application
-PLATFORM_USER_APP_START ?= $(shell echo $$(($(PRIMARY_IMG_START)-$(FLASH_START)+$(FLASH_XIP_START))))
+PLATFORM_USER_APP_START ?= $(shell printf "0x%X" $$(($(PRIMARY_IMG_START)-$(FLASH_START)+$(FLASH_XIP_START))))
+PLATFORM_USER_APP_LOCATION ?= $(shell printf "0x%X" $$(($(PRIMARY_IMG_START)-$(FLASH_START)+$(FLASH_XIP_START))))
+
+ifeq ($(IMG_TYPE), UPGRADE)
+ PLATFORM_USER_APP_LOCATION := $(shell printf "0x%X" $$(($(SECONDARY_IMG_START)-$(FLASH_START)+$(FLASH_XIP_START))))
+endif
+
+ifeq ($(APP_SLOT), 2)
+ PLATFORM_USER_APP_LOCATION := $(shell printf "0x%X" $$(($(SECONDARY_IMG_START)-$(FLASH_START)+$(FLASH_XIP_START))))
+endif
+
# Define RAM start and size, slot size
PLATFORM_DEFAULT_RAM_START ?= 0x2000C000
PLATFORM_DEFAULT_RAM_SIZE ?= 0x10000
-DEFINES += -DUSER_APP_START_OFF=0x20000
+ifeq ($(APP_SLOT), 1)
+DEFINES += -DUSER_APP_START_OFF=$(shell echo $$(($(PRIMARY_IMG_START)-$(FLASH_START))))
+else
+DEFINES += -DUSER_APP_START_OFF=$(shell echo $$(($(SECONDARY_IMG_START)-$(FLASH_START))))
+endif
PLATFORM_DEFAULT_IMG_VER_ARG ?= 1.0.0
@@ -229,6 +252,10 @@
PLATFORM_SIGN_ARGS += --app-addr=$(PLATFORM_USER_APP_START)
endif
+ifeq ($(USE_IMG_TRAILER), 1)
+ PLATFORM_SIGN_ARGS += --pad
+endif
+
pre_build:
$(info [PRE_BUILD] - Generating linker script for application $(CUR_APP_PATH)/linker/$(APP_NAME).ld)
@$(CC) -E -x c $(CFLAGS) $(INCLUDE_DIRS) $(CUR_APP_PATH)/linker/$(APP_NAME)_$(CORE)_template$(LD_SUFFIX).ld | grep -v '^#' >$(CUR_APP_PATH)/linker/$(APP_NAME).ld
@@ -240,8 +267,14 @@
$(shell $(PRJ_DIR)/run_toc2_generator.sh $(LCS) $(OUT_CFG) $(APP_NAME) $(APPTYPE) $(PRJ_DIR) $(SMIF_CRYPTO_CONFIG) $(TOOLCHAIN_PATH))
$(info SIGN_ARGS <-> $(SIGN_ARGS))
+ $(info cysecuretools -q -t cyw20829 -p $(APP_DEFAULT_POLICY) sign-image $(SIGN_ARGS))
$(shell cysecuretools -q -t cyw20829 -p $(APP_DEFAULT_POLICY) sign-image $(SIGN_ARGS))
+ifeq ($(SMIF_ENC), 1)
+ $(info edgeprotecttools -t cyw20829 encrypt --input $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).bin --output $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).bin --iv $(PLATFORM_USER_APP_LOCATION) --enckey keys/encrypt_key.bin --nonce ./MCUBootApp/out/CYW20829/$(BUILDCFG)/MCUBootApp.signed_nonce.bin)
+ $(shell edgeprotecttools -t cyw20829 encrypt --input $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).bin --output $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).bin --iv $(PLATFORM_USER_APP_LOCATION) --enckey keys/encrypt_key.bin --nonce ./MCUBootApp/out/CYW20829/$(BUILDCFG)/MCUBootApp.signed_nonce.bin)
+endif
+
$(GCC_PATH)/bin/arm-none-eabi-objcopy --change-address=$(HEADER_OFFSET) -I binary -O ihex $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).bin $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex
$(GCC_PATH)/bin/arm-none-eabi-objdump -s $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).hex > $(OUT_CFG)/$(APP_NAME)$(UPGRADE_SUFFIX).objdump
else
diff --git a/boot/cypress/platforms/PSC3.md b/boot/cypress/platforms/PSC3.md
index a1eb402..8c72b0d 100644
--- a/boot/cypress/platforms/PSC3.md
+++ b/boot/cypress/platforms/PSC3.md
@@ -1,3 +1,3 @@
## PSOC™ C3 platform description
-PSOC™ C3 support added for ModusToolbox Code Example - [mtb-example-psoc-control-edge-protect-bootloader](https://github.com/Infineon/mtb-example-psoc-control-edge-protect-bootloader). Please use ModusToolbox 3.3 or higher to create and run the project.
+PSOC™ C3 support added for ModusToolbox™ Code Example - [mtb-example-psoc-control-edge-protect-bootloader](https://github.com/Infineon/mtb-example-psoc-control-edge-protect-bootloader). Please use ModusToolbox™ 3.5 or higher to create and run the project.
diff --git a/boot/cypress/platforms/PSOC6.md b/boot/cypress/platforms/PSOC6.md
index 88d3f24..6c9b7f7 100644
--- a/boot/cypress/platforms/PSOC6.md
+++ b/boot/cypress/platforms/PSOC6.md
@@ -71,7 +71,7 @@
To enable the image encryption support, use the `ENC_IMG=1` build flag (BlinkyApp should also be built with this flash set 1).
-The user is also responsible for providing corresponding binary key data in `enc_priv_key[]` (file `\MCUBootApp\keys.c`). The public part will be used by `imgtool` when signing and encrypting upgrade image. Signing image with encryption is described in [BlinkyApp.md](../../BlinkyApp/BlinkyApp.md).
+The user is also responsible for providing corresponding binary key data in `enc_priv_key[]` (file `\MCUBootApp\keys.c`). The public part will be used by `imgtool` when signing and encrypting upgrade image. Signing image with encryption is described in [BlinkyApp.md](../BlinkyApp/BlinkyApp.md).
After MCUBootApp is built with these settings, unencrypted and encrypted images will be accepted in the secondary (upgrade) slot.
@@ -89,12 +89,14 @@
Connect the board to your computer. Switch Kitprog3 to DAP-BULK mode by clicking the `SW3 MODE` button until `LED2 STATUS` constantly shines.
-Open the terminal application and execute the following command after substitution of the `PATH_TO_APPLICATION.hex` and `OPENOCD` paths:
+The OpenOCD package is supplied with `ModusToolbox™ Programming Tools` and can be found in the `C:\Infineon\Tools\ModusToolboxProgtools-1.4\openocd` folder.
- export OPENOCD=/Applications/ModusToolbox/tools_3.2/openocd
+Open the terminal application and execute the following commands:
- ${OPENOCD}/bin/openocd -s ${OPENOCD}/scripts \
- -f ${OPENOCD}/scripts/interface/kitprog3.cfg \
- -f ${OPENOCD}/scripts/target/psoc6_2m.cfg \
+ export OPENOCD_PATH=C:/Infineon/Tools/ModusToolboxProgtools-1.4/openocd
+
+ ${OPENOCD_PATH}/bin/openocd -s ${OPENOCD_PATH}/scripts \
+ -f ${OPENOCD_PATH}/scripts/interface/kitprog3.cfg \
+ -f ${OPENOCD_PATH}/scripts/target/psoc6_2m.cfg \
-c "init; reset init; program PATH_TO_APPLICATION.hex" \
-c "resume; reset; exit"
diff --git a/boot/cypress/platforms/PSOC6.mk b/boot/cypress/platforms/PSOC6.mk
index 6747b4e..0ae2b29 100644
--- a/boot/cypress/platforms/PSOC6.mk
+++ b/boot/cypress/platforms/PSOC6.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -106,14 +106,6 @@
DEFINES += -DCYBSP_DEBUG_UART_TX=$(UART_TX_DEFAULT)
DEFINES += -DCYBSP_DEBUG_UART_RX=$(UART_RX_DEFAULT)
-# Add device name to defines
-DEFINES += -D$(DEVICE)
-DEFINES += -DCY_USING_HAL
-DEFINES += -DCORE_NAME_$(CORE)_0=1
-DEFINES += -DCOMPONENT_CAT1
-DEFINES += -DCOMPONENT_CAT1A
-DEFINES += -DCOMPONENT_$(CORE)
-
# Minimum erase size of underlying memory hardware
PLATFORM_MEMORY_ALIGN := 0x200
PLATFORM_MAX_TRAILER_PAGE_SIZE := 0x200
@@ -133,6 +125,8 @@
ifeq ($(APP_NAME), MCUBootApp)
+CFLAGS_OPTIMIZATION := -Os -g3
+
CORE ?= CM0P
ifeq ($(CORE), CM0P)
CORE_SUFFIX = m0plus
@@ -276,3 +270,11 @@
PLATFORM_STARTUP_FILE := $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system/COMPONENT_$(CORE)/TOOLCHAIN_$(COMPILER)/startup_psoc6_$(PLATFORM_SUFFIX)_c$(CORE_SUFFIX).S
INCLUDE_DIRS += $(PRJ_DIR)/platforms/BSP/$(FAMILY)/system
+
+# Add device name to defines
+DEFINES += -D$(DEVICE)
+DEFINES += -DCY_USING_HAL
+DEFINES += -DCORE_NAME_$(CORE)_0=1
+DEFINES += -DCOMPONENT_CAT1
+DEFINES += -DCOMPONENT_CAT1A
+DEFINES += -DCOMPONENT_$(CORE)
diff --git a/boot/cypress/platforms/XMC7000.md b/boot/cypress/platforms/XMC7000.md
index 5566859..b91b846 100644
--- a/boot/cypress/platforms/XMC7000.md
+++ b/boot/cypress/platforms/XMC7000.md
@@ -31,10 +31,10 @@
To prepare a secure MCUBoot image, the user must configure the public key and specify the appropriate parameters for the TOC2 structure in the `cy_si_config.c`, `cy_si_key.c` files and execute the make command with the additional variables `USE_SECURE_MODE=1`, `SECURE_MODE_KEY_NAME=<name>`.
- Step to generate custom RSA2048 keys:
- cysecuretools -t xmc7200 create-key --key-type RSA2048 -o ./keys/cypress-test-rsa2k.pem ./keys/cypress-test-rsa2k.pub --format PEM
+ edgeprotecttools -t xmc7200 create-key --key-type RSA2048 -o ./keys/cypress-test-rsa2k.pem ./keys/cypress-test-rsa2k.pub --format PEM
- Step to generate `cy_si_key.c` file:
- cysecuretools convert-key -k ./keys/cypress-test-rsa2k.pub -o ./platforms/utils/XMC7000/cy_si_key.c --fmt secure_boot --endian little
+ edgeprotecttools convert-key -k ./keys/cypress-test-rsa2k.pub -o ./platforms/utils/XMC7000/cy_si_key.c --fmt secure_boot --endian little
Previous two steps can be executed with single Makefile command.
make gen_secure_cfgs PLATFORM=XMC7200 SECURE_MODE_KEY_TYPE=RSA2048 KEY_NAME=cypress-test-rsa2k
@@ -61,7 +61,7 @@
flash erase_address 0x17006400 0x00000C00
flash fillb 0x14030000 0xFF 0x00002800
- program `./MCUBootApp/out/XMC7200/Debug/MCUBootApp.hex`
+ program './MCUBootApp/out/XMC7200/Debug/MCUBootApp.hex'
resume;
reset;
diff --git a/boot/cypress/platforms/XMC7000.mk b/boot/cypress/platforms/XMC7000.mk
index 509a41d..510841d 100644
--- a/boot/cypress/platforms/XMC7000.mk
+++ b/boot/cypress/platforms/XMC7000.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/boot_rng/boot_rng.c b/boot/cypress/platforms/boot_rng/boot_rng.c
index 9a658cd..44301d7 100644
--- a/boot/cypress/platforms/boot_rng/boot_rng.c
+++ b/boot/cypress/platforms/boot_rng/boot_rng.c
@@ -2,7 +2,7 @@
* File Name: boot_rng.c
*
*******************************************************************************
-* Copyright 2024, Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation. All rights reserved.
*
* This software, including source code, documentation and related
diff --git a/boot/cypress/platforms/boot_rng/boot_rng.h b/boot/cypress/platforms/boot_rng/boot_rng.h
index 68c5646..033e1cd 100644
--- a/boot/cypress/platforms/boot_rng/boot_rng.h
+++ b/boot/cypress/platforms/boot_rng/boot_rng.h
@@ -2,7 +2,7 @@
* File Name: boot_rng.h
*
******************************************************************************
-* Copyright 2024, Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation. All rights reserved.
*
* This software, including source code, documentation and related
diff --git a/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h b/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h
index 2ed6c81..fffa145 100644
--- a/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h
+++ b/boot/cypress/platforms/crypto/CYW20829/mbedtls/compat-2.x.h
@@ -1,5 +1,5 @@
/********************************************************************************
-* Copyright 2022 Infineon Technologies AG
+* Copyright 2025 Infineon Technologies AG
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/crypto/PSC3/cyboot_crypto_list.h b/boot/cypress/platforms/crypto/PSC3/cyboot_crypto_list.h
index f86cb2a..beb27bb 100644
--- a/boot/cypress/platforms/crypto/PSC3/cyboot_crypto_list.h
+++ b/boot/cypress/platforms/crypto/PSC3/cyboot_crypto_list.h
@@ -4,7 +4,7 @@
* Provides header file for crypto API.
********************************************************************************
* \copyright
-* (c) 2023, Cypress Semiconductor Corporation (an Infineon company) or an
+* (c) 2025, Cypress Semiconductor Corporation (an Infineon company) or an
* affiliate of Cypress Semiconductor Corporation. All rights reserved.
* This software, associated documentation and materials ("Software") is owned
* by Cypress Semiconductor Corporation or one of its affiliates ("Cypress") and
diff --git a/boot/cypress/platforms/crypto/PSC3/image_ec256_port.c b/boot/cypress/platforms/crypto/PSC3/image_ec256_port.c
index 0232b8d..45f2462 100644
--- a/boot/cypress/platforms/crypto/PSC3/image_ec256_port.c
+++ b/boot/cypress/platforms/crypto/PSC3/image_ec256_port.c
@@ -69,13 +69,13 @@
}
#if !defined(MCUBOOT_USE_PSA_CRYPTO)
/* id-ecPublicKey (RFC5480) */
- if (alg.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_pubkey_oid) - 1 ||
- memcmp(alg.MBEDTLS_CONTEXT_MEMBER(p), ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
+ if (alg.len != sizeof(ec_pubkey_oid) - 1 ||
+ memcmp(alg.p, ec_pubkey_oid, sizeof(ec_pubkey_oid) - 1)) {
return -3;
}
/* namedCurve (RFC5480) */
- if (param.MBEDTLS_CONTEXT_MEMBER(len) != sizeof(ec_secp256r1_oid) - 1 ||
- memcmp(param.MBEDTLS_CONTEXT_MEMBER(p), ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
+ if (param.len != sizeof(ec_secp256r1_oid) - 1 ||
+ memcmp(param.p, ec_secp256r1_oid, sizeof(ec_secp256r1_oid) - 1)) {
return -4;
}
#endif
diff --git a/boot/cypress/platforms/crypto/PSC3/sha256_port.h b/boot/cypress/platforms/crypto/PSC3/sha256_port.h
index f74fd8b..f26105b 100644
--- a/boot/cypress/platforms/crypto/PSC3/sha256_port.h
+++ b/boot/cypress/platforms/crypto/PSC3/sha256_port.h
@@ -4,7 +4,7 @@
* Provides port layer for SHA256 MCUBoot functions
********************************************************************************
* \copyright
- * (c) 2023, Cypress Semiconductor Corporation (an Infineon company) or an
+ * (c) 2025, Cypress Semiconductor Corporation (an Infineon company) or an
* affiliate of Cypress Semiconductor Corporation. All rights reserved.
* This software, associated documentation and materials ("Software") is owned
* by Cypress Semiconductor Corporation or one of its affiliates ("Cypress") and
diff --git a/boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c b/boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c
index f3a8f1b..a6f9f1f 100644
--- a/boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c
+++ b/boot/cypress/platforms/img_confirm/CYW20829/set_img_ok.c
@@ -1,5 +1,5 @@
/********************************************************************************
- * Copyright 2018-2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2018-2025 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
@@ -17,11 +17,13 @@
* limitations under the License.
********************************************************************************/
-#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
+#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE) || defined(MCUBOOT_DIRECT_XIP)
#include "set_img_ok.h"
#include <flash_map_backend/flash_map_backend.h>
+#include <string.h>
+
#define EXT_MEM_INTERFACE_ID 0
extern const struct flash_area_interface external_mem_interface;
@@ -59,11 +61,15 @@
int rc = 0;
/* Accepting an arbitrary address */
uint32_t row_mask = external_mem_interface.get_erase_size(0) - 1U;
+ uint32_t erase_val = external_mem_interface.get_erase_val(0);
+ uint32_t index = address & row_mask;
rc |= external_mem_interface.read(EXT_MEM_INTERFACE_ID, address & ~row_mask, row_buff, FLASH_ROW_BUF_SZ);
/* Modifying the target byte */
- row_buff[address & row_mask] = src;
+ memset(&row_buff[index], erase_val, sizeof(uint64_t));
+ row_buff[index] = src;
+
rc |= external_mem_interface.erase(EXT_MEM_INTERFACE_ID, address & ~row_mask, FLASH_ROW_BUF_SZ);
diff --git a/boot/cypress/platforms/img_confirm/PSC3/set_img_ok.c b/boot/cypress/platforms/img_confirm/PSC3/set_img_ok.c
index cb580a9..4a0de1c 100644
--- a/boot/cypress/platforms/img_confirm/PSC3/set_img_ok.c
+++ b/boot/cypress/platforms/img_confirm/PSC3/set_img_ok.c
@@ -1,5 +1,5 @@
/********************************************************************************
-* Copyright 2021 Infineon Technologies AG
+* Copyright 2025 Infineon Technologies AG
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c b/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c
index c8901c0..25e95b6 100644
--- a/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c
+++ b/boot/cypress/platforms/img_confirm/PSOC6/set_img_ok.c
@@ -1,25 +1,26 @@
/********************************************************************************
-* Copyright 2021 Infineon Technologies AG
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-* http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
+ * Copyright 2025 Infineon Technologies AG
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ ********************************************************************************/
#if !(SWAP_DISABLED) && defined(UPGRADE_IMAGE)
-#include "string.h"
#include "set_img_ok.h"
+
#include "cy_flash.h"
+#include "string.h"
#if defined(CY_BOOT_USE_EXTERNAL_FLASH)
#include "flash_qspi.h"
@@ -27,11 +28,9 @@
static uint8_t row_buff[FLASH_ROW_BUF_SZ];
-#ifndef USE_XIP
-
/**
* @brief Function reads value of img_ok flag from address.
- *
+ *
* @param address - address of img_ok flag in primary img trailer
* @return int - value at address
*/
@@ -40,14 +39,16 @@
return *(volatile uint8_t *)address;
}
+#ifndef USE_XIP
/**
* @brief Function sets img_ok flag value to primary image trailer.
- *
+ *
* @param address - address of img_ok flag in primary img trailer
* @param value - value corresponding to img_ok set
- *
+ *
* @return - operation status. 0 - set succesfully, -1 - failed to set.
*/
+CY_RAMFUNC_BEGIN
static int write_img_ok_value(uint32_t address, uint8_t value)
{
int rc = -1;
@@ -74,19 +75,20 @@
return rc;
}
+CY_RAMFUNC_END
#else
/**
* @brief Function sets img_ok value to primary slot trailer
- * when application is executed from external memory
+ * when application is executed from external memory
* in XIP mode. This function is executed from RAM since
* it reconfigures SMIF block from XIP to MMIO mode, then
* writes img_ok set value and switches back to XIP mode.
*
* @param address - address of img_ok flag in primary img trailer
* @param value - value corresponding to img_ok set
- *
+ *
* @return - operation status. 1 - already set, 0 - set succesfully,
* -1 - failed to set.
*/
@@ -94,98 +96,35 @@
static int set_img_ok_ram(uint32_t address, uint8_t value)
{
int32_t rc = IMG_OK_SET_FAILED;
- uint32_t try_count = 10U;
- cy_en_smif_status_t stat = CY_SMIF_BUSY;
SMIF_Type *QSPIPort = SMIF0;
- cy_stc_smif_context_t QSPI_context;
- cy_en_smif_mode_t mode = CY_SMIF_NORMAL;
+ cy_stc_smif_context_t QSPI_context = {0};
+ cy_stc_smif_mem_config_t *cfg = smifBlockConfig_sfdp.memConfig[0];
+
+ const uint32_t trailer_row_abs_addr = address & ~(MEMORY_ALIGN - 1);
+ const uint32_t trailer_row_addr = (address - CY_XIP_BASE) & ~(MEMORY_ALIGN - 1);
+
+ memcpy(row_buff, (void *)trailer_row_abs_addr, MEMORY_ALIGN);
Cy_SMIF_SetMode(SMIF0, CY_SMIF_NORMAL);
- mode = Cy_SMIF_GetMode(QSPIPort);
- if (mode != CY_SMIF_NORMAL) {
- CY_HALT();
- }
+ Cy_SMIF_MemDeInit(QSPIPort);
- for (try_count = 0U; try_count < 10U; try_count++) {
+ cy_en_smif_status_t status = Cy_SMIF_MemInit(QSPIPort, &smifBlockConfig_sfdp, &QSPI_context);
- stat = Cy_SMIF_MemInit(QSPIPort, &smifBlockConfig_sfdp, &QSPI_context);
+ if (status == CY_SMIF_SUCCESS) {
+ row_buff[address & (MEMORY_ALIGN - 1)] = value;
- if (CY_SMIF_SUCCESS == stat) {
- break;
- }
-
- Cy_SysLib_Delay(500U);
- }
-
- if (stat == CY_SMIF_SUCCESS) {
-
- cy_stc_smif_mem_config_t *cfg = smifBlockConfig_sfdp.memConfig[0];
- /* Determine row start address, where image trailer is allocated */
- uint32_t erase_len = cfg->deviceCfg->eraseSize;
- uint32_t row_mask = erase_len /* is a power of two */ - 1u;
- uint32_t row_addr = (address - CY_XIP_BASE) & ~row_mask;
- /* Determine start address of image trailer
- * The minimum erase size area is allocated
- * for trailer, but reading the whole area is
- * not nessesary since data is only located at
- * first 0x200 bytes. Trailer size is taken as 0x200
- * to keep consistency with internal memory
- * implementation, where min_erase_size is 0x200
- */
- uint32_t img_trailer_addr = address - CY_XIP_BASE + USER_SWAP_IMAGE_OK_OFFS - IMG_TRAILER_SZ;
- uint32_t img_ok_mask = FLASH_ROW_BUF_SZ /* is a power of 2 */ - 1u;
-
- cy_en_smif_status_t st = Cy_SMIF_MemRead(QSPIPort, cfg,
- img_trailer_addr, row_buff, FLASH_ROW_BUF_SZ,
- &QSPI_context);
-
- if (CY_SMIF_SUCCESS == st) {
-
- if (row_buff[address & img_ok_mask] != value) {
-
- row_buff[address & img_ok_mask] = value;
-
- /* Programming the updated block back */
- st = Cy_SMIF_MemEraseSector(QSPIPort, cfg,
- row_addr, erase_len,
- &QSPI_context);
-
- if (CY_SMIF_SUCCESS == st) {
- st = Cy_SMIF_MemWrite(QSPIPort, cfg,
- img_trailer_addr, row_buff, FLASH_ROW_BUF_SZ,
- &QSPI_context);
- if (CY_SMIF_SUCCESS == st) {
- rc = IMG_OK_SET_SUCCESS;
- }
- }
- else {
- rc = IMG_OK_SET_FAILED;
- }
- }
- else {
- rc = IMG_OK_ALREADY_SET;
- }
- }
- else {
- rc = IMG_OK_SET_FAILED;
- }
-
- stat = Cy_SMIF_CacheEnable(QSPIPort, CY_SMIF_CACHE_FAST);
-
- if (CY_SMIF_SUCCESS == stat) {
- Cy_SMIF_SetMode(QSPIPort, CY_SMIF_MEMORY);
- mode = Cy_SMIF_GetMode(QSPIPort);
-
- if (mode != CY_SMIF_MEMORY) {
- CY_HALT();
+ if (CY_SMIF_SUCCESS == Cy_SMIF_MemEraseSector(QSPIPort, cfg,
+ trailer_row_addr, MEMORY_ALIGN, &QSPI_context)) {
+ if (CY_SMIF_SUCCESS == Cy_SMIF_MemWrite(QSPIPort, cfg, trailer_row_addr,
+ row_buff, MEMORY_ALIGN, &QSPI_context)) {
+ rc = IMG_OK_SET_SUCCESS;
}
}
}
- else {
- /* do nothing */
- }
+
+ Cy_SMIF_SetMode(SMIF0, CY_SMIF_MEMORY);
return rc;
}
@@ -195,14 +134,14 @@
/**
* @brief Public function to confirm that upgraded application is operable
- * after swap. Should be called from main code of user application.
+ * after swap. Should be called from main code of user application.
* It sets mcuboot flag img_ok in primary (boot) image trailer.
* MCUBootApp checks img_ok flag at first reset after upgrade and
* validates successful swap.
- *
+ *
* @param address - address of img_ok flag in primary img trailer
* @param value - value corresponding to img_ok set
- *
+ *
* @return - operation status. 1 - already set, 0 - set succesfully,
* -1 - failed to set.
*/
@@ -213,26 +152,15 @@
/* Write Image OK flag to the slot trailer, so MCUBoot-loader
* will not revert new image
*/
-#ifdef USE_XIP
- /*
- * When switching from XIP execution mode to RAM function
- * it is required to clear and disable SMIF cache. set_img_ok_ram
- * is then turns cache on before return. If it is not done - return
- * to execution from RAM to XIP hangs indefinitely.
- */
- Cy_SMIF_CacheDisable(SMIF0, CY_SMIF_CACHE_FAST);
- Cy_SMIF_CacheInvalidate(SMIF0, CY_SMIF_CACHE_FAST);
- rc = set_img_ok_ram(address, value);
-
-#else
-
if (read_img_ok_value(address) != value) {
+#ifdef USE_XIP
+ rc = set_img_ok_ram(address, value);
+#else
rc = write_img_ok_value(address, value);
- }
- else {
+#endif /* USE_XIP */
+ } else {
rc = IMG_OK_ALREADY_SET;
}
-#endif /* USE_XIP */
return rc;
}
diff --git a/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c b/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c
index b95cf32..edb9132 100644
--- a/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c
+++ b/boot/cypress/platforms/img_confirm/XMC7000/set_img_ok.c
@@ -1,5 +1,5 @@
/********************************************************************************
-* Copyright 2021 Infineon Technologies AG
+* Copyright 2025 Infineon Technologies AG
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/img_confirm/set_img_ok.h b/boot/cypress/platforms/img_confirm/set_img_ok.h
index 08ecb04..c5beed8 100644
--- a/boot/cypress/platforms/img_confirm/set_img_ok.h
+++ b/boot/cypress/platforms/img_confirm/set_img_ok.h
@@ -1,5 +1,5 @@
/********************************************************************************
-* Copyright 2021 Infineon Technologies AG
+* Copyright 2025 Infineon Technologies AG
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -25,7 +25,16 @@
#define USER_SWAP_IMAGE_OK_OFFS (24)
#define USER_SWAP_IMAGE_OK (1)
-#define IMG_OK_ADDR (PRIMARY_IMG_START + USER_APP_SIZE - USER_SWAP_IMAGE_OK_OFFS)
+
+#if defined(MCUBOOT_DIRECT_XIP)
+ #if APP_SLOT == 1
+ #define IMG_OK_ADDR (PRIMARY_IMG_START + USER_APP_SIZE - USER_SWAP_IMAGE_OK_OFFS)
+ #else
+ #define IMG_OK_ADDR (SECONDARY_IMG_START + USER_APP_SIZE - USER_SWAP_IMAGE_OK_OFFS)
+ #endif
+#else
+ #define IMG_OK_ADDR (PRIMARY_IMG_START + USER_APP_SIZE - USER_SWAP_IMAGE_OK_OFFS)
+#endif
#define IMG_OK_SET_UNDEFINED 0x55
diff --git a/boot/cypress/platforms/memory/CYW20829/flash_map_backend_platform.h b/boot/cypress/platforms/memory/CYW20829/flash_map_backend_platform.h
index dc6010e..81b3dbd 100644
--- a/boot/cypress/platforms/memory/CYW20829/flash_map_backend_platform.h
+++ b/boot/cypress/platforms/memory/CYW20829/flash_map_backend_platform.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2015 Runtime Inc
- * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.c b/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.c
index 0643ea1..468a9d3 100644
--- a/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.c
+++ b/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.c
@@ -27,7 +27,7 @@
********************************************************************************
* \copyright
*
-* (c) 2020, Cypress Semiconductor Corporation
+* (c) 2025, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
diff --git a/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.h b/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.h
index 7e44118..4b95845 100644
--- a/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.h
+++ b/boot/cypress/platforms/memory/CYW20829/flash_qspi/cy_smif_hybrid_sect.h
@@ -8,7 +8,7 @@
********************************************************************************
* \copyright
*
-* © 2020, Cypress Semiconductor Corporation
+* © 2025, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
diff --git a/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.c b/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.c
index 76ee0e7..6d22381 100644
--- a/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.c
+++ b/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.c
@@ -27,7 +27,7 @@
********************************************************************************
* \copyright
*
-* (c) 2020, Cypress Semiconductor Corporation
+* (c) 2025, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
diff --git a/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.h b/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.h
index 5ce3fd0..2381323 100644
--- a/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.h
+++ b/boot/cypress/platforms/memory/CYW20829/flash_qspi/flash_qspi.h
@@ -8,7 +8,7 @@
********************************************************************************
* \copyright
*
-* © 2020, Cypress Semiconductor Corporation
+* © 2025, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
diff --git a/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_direct_xip_single.json b/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_direct_xip_single.json
new file mode 100644
index 0000000..22791c5
--- /dev/null
+++ b/boot/cypress/platforms/memory/CYW20829/flashmap/cyw20829_direct_xip_single.json
@@ -0,0 +1,39 @@
+{
+ "external_flash": [
+ {
+ "model": "FM25W04",
+ "mode": "XIP"
+ }
+ ],
+ "boot_and_upgrade":
+ {
+ "bootloader": {
+ "address": {
+ "description": "Address of the bootloader",
+ "value": "0x60000000"
+ },
+ "size": {
+ "description": "Size of the bootloader",
+ "value": "0x20000"
+ }
+ },
+ "application_1": {
+ "primary_slot": {
+ "description": "Address of the application primary slot",
+ "value": "0x60020000"
+ },
+ "primary_slot_size": {
+ "description": "Size of the application primary slot",
+ "value": "0x20000"
+ },
+ "secondary_slot": {
+ "description": "Address of the application secondary slot",
+ "value": "0x60040000"
+ },
+ "secondary_slot_size": {
+ "description": "Size of the application secondary slot",
+ "value": "0x20000"
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/boot/cypress/platforms/memory/PSC3/flash_map_backend_platform.h b/boot/cypress/platforms/memory/PSC3/flash_map_backend_platform.h
index 2160e73..f04fc8b 100644
--- a/boot/cypress/platforms/memory/PSC3/flash_map_backend_platform.h
+++ b/boot/cypress/platforms/memory/PSC3/flash_map_backend_platform.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2015 Runtime Inc
- * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/platforms/memory/PSC3/internal_memory.c b/boot/cypress/platforms/memory/PSC3/internal_memory.c
index 320bcd3..3ee2f85 100644
--- a/boot/cypress/platforms/memory/PSC3/internal_memory.c
+++ b/boot/cypress/platforms/memory/PSC3/internal_memory.c
@@ -1,6 +1,6 @@
/********************************************************************************
* \copyright
- * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+ * (c) (2016-2025), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/memory/PSC3/linker.ld b/boot/cypress/platforms/memory/PSC3/linker.ld
index 9588295..c4a5119 100644
--- a/boot/cypress/platforms/memory/PSC3/linker.ld
+++ b/boot/cypress/platforms/memory/PSC3/linker.ld
@@ -19,7 +19,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2024, Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
diff --git a/boot/cypress/platforms/memory/PSOC6/flash_map_backend_platform.h b/boot/cypress/platforms/memory/PSOC6/flash_map_backend_platform.h
index bdfedbd..77a969e 100644
--- a/boot/cypress/platforms/memory/PSOC6/flash_map_backend_platform.h
+++ b/boot/cypress/platforms/memory/PSOC6/flash_map_backend_platform.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2015 Runtime Inc
- * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c
index 222ad66..7216a75 100644
--- a/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c
+++ b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.c
@@ -27,7 +27,7 @@
********************************************************************************
* \copyright
*
-* (c) 2020, Cypress Semiconductor Corporation
+* (c) 2025, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
diff --git a/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.h b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.h
index 26ffd72..09e982a 100644
--- a/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.h
+++ b/boot/cypress/platforms/memory/PSOC6/flash_qspi/flash_qspi.h
@@ -8,7 +8,7 @@
********************************************************************************
* \copyright
*
-* © 2020, Cypress Semiconductor Corporation
+* © 2025, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
diff --git a/boot/cypress/platforms/memory/PSOC6/internal_memory.c b/boot/cypress/platforms/memory/PSOC6/internal_memory.c
index c0d2d0e..568eccd 100644
--- a/boot/cypress/platforms/memory/PSOC6/internal_memory.c
+++ b/boot/cypress/platforms/memory/PSOC6/internal_memory.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2020 Cypress Semiconductor Corporation
- * Copyright (c) 2022 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.c b/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.c
index bcf6841..4131724 100644
--- a/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.c
+++ b/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.c
@@ -7,7 +7,7 @@
* QSPI Configurator 3.0.0.5613
*
********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.h b/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.h
index 884be8f..6952854 100644
--- a/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.h
+++ b/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/cycfg_qspi_memslot.h
@@ -7,7 +7,7 @@
* QSPI Configurator 3.0.0.5613
*
********************************************************************************
-* Copyright 2022 Cypress Semiconductor Corporation
+* Copyright 2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/qspi_config.cfg b/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/qspi_config.cfg
index 96ff76a..a7aaf45 100644
--- a/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/qspi_config.cfg
+++ b/boot/cypress/platforms/memory/PSOC6/smif_cfg_dbg/qspi_config.cfg
@@ -7,7 +7,7 @@
# QSPI Configurator: 3.0.0.5613
#
################################################################################
-# Copyright 2022 Cypress Semiconductor Corporation
+# Copyright 2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/memory/XMC7000/flash_map_backend_platform.h b/boot/cypress/platforms/memory/XMC7000/flash_map_backend_platform.h
index 614ce37..b717744 100644
--- a/boot/cypress/platforms/memory/XMC7000/flash_map_backend_platform.h
+++ b/boot/cypress/platforms/memory/XMC7000/flash_map_backend_platform.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2015 Runtime Inc
- * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c b/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c
index 52070c0..5aab23b 100644
--- a/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c
+++ b/boot/cypress/platforms/memory/XMC7000/internal_memory_code.c
@@ -1,6 +1,6 @@
/********************************************************************************
* \copyright
-* (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or
+* (c) (2016-2025), Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/memory/XMC7000/internal_memory_work.c b/boot/cypress/platforms/memory/XMC7000/internal_memory_work.c
index 998c975..4ef77df 100644
--- a/boot/cypress/platforms/memory/XMC7000/internal_memory_work.c
+++ b/boot/cypress/platforms/memory/XMC7000/internal_memory_work.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2020 Cypress Semiconductor Corporation
- * Copyright (c) 2022 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/platforms/memory/cy_flash_map.c b/boot/cypress/platforms/memory/cy_flash_map.c
index 52e69cb..26158e7 100644
--- a/boot/cypress/platforms/memory/cy_flash_map.c
+++ b/boot/cypress/platforms/memory/cy_flash_map.c
@@ -1,7 +1,6 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
- * Copyright (c) 2020 Cypress Semiconductor Corporation
- * Copyright (c) 2022 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/platforms/memory/external_memory/external_memory.c b/boot/cypress/platforms/memory/external_memory/external_memory.c
index 5fe2b93..58e0c35 100644
--- a/boot/cypress/platforms/memory/external_memory/external_memory.c
+++ b/boot/cypress/platforms/memory/external_memory/external_memory.c
@@ -9,7 +9,7 @@
********************************************************************************
* \copyright
*
- * (c) 2020, Cypress Semiconductor Corporation
+ * (c) 2025, Cypress Semiconductor Corporation
* or a subsidiary of Cypress Semiconductor Corporation. All rights
* reserved.
*
@@ -160,7 +160,7 @@
#if defined(MCUBOOT_ENC_IMAGES_SMIF)
CY_RAMFUNC_BEGIN
-static cy_en_smif_status_t smif_encrypt(const void *data, uint32_t len, uintptr_t addr)
+static cy_en_smif_status_t smif_encrypt(void *data, uint32_t len, uintptr_t addr)
{
cy_en_smif_status_t status = CY_SMIF_SUCCESS;
SMIF_Type *device = qspi_get_device();
diff --git a/boot/cypress/platforms/memory/flash_map_backend/flash_map_backend.h b/boot/cypress/platforms/memory/flash_map_backend/flash_map_backend.h
index c882a97..37e7068 100644
--- a/boot/cypress/platforms/memory/flash_map_backend/flash_map_backend.h
+++ b/boot/cypress/platforms/memory/flash_map_backend/flash_map_backend.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2018 Nordic Semiconductor ASA
* Copyright (c) 2015 Runtime Inc
- * Copyright (c) 2020 Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/platforms/memory/sysflash/sysflash.h b/boot/cypress/platforms/memory/sysflash/sysflash.h
index 544a8c6..32b1c55 100644
--- a/boot/cypress/platforms/memory/sysflash/sysflash.h
+++ b/boot/cypress/platforms/memory/sysflash/sysflash.h
@@ -1,6 +1,5 @@
/*
- * Copyright (c) 2020 Cypress Semiconductor Corporation
- * Copyright (c) 2022 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* SPDX-License-Identifier: Apache-2.0
*/
diff --git a/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c
index 4612904..dfebd2f 100644
--- a/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2020 Arm Limited.
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h
index f712a8d..0c6f75e 100644
--- a/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_security_cnt_platform.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2020 Arm Limited.
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c
index 5afd417..4c0ed92 100644
--- a/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.h b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.h
index 2f76386..34f433b 100644
--- a/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.h
+++ b/boot/cypress/platforms/security_counter/CYW20829/cy_service_app.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/platforms/security_counter/PSC3/cy_security_cnt_platform.c b/boot/cypress/platforms/security_counter/PSC3/cy_security_cnt_platform.c
index a786702..b2c9eb2 100644
--- a/boot/cypress/platforms/security_counter/PSC3/cy_security_cnt_platform.c
+++ b/boot/cypress/platforms/security_counter/PSC3/cy_security_cnt_platform.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2020 Arm Limited.
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/platforms/security_counter/PSC3/cy_security_cnt_platform.h b/boot/cypress/platforms/security_counter/PSC3/cy_security_cnt_platform.h
index 75f17cf..7946a3b 100644
--- a/boot/cypress/platforms/security_counter/PSC3/cy_security_cnt_platform.h
+++ b/boot/cypress/platforms/security_counter/PSC3/cy_security_cnt_platform.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2020 Arm Limited.
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/platforms/security_counter/PSC3/rollback_counter.h b/boot/cypress/platforms/security_counter/PSC3/rollback_counter.h
index a764cb4..a6dc154 100644
--- a/boot/cypress/platforms/security_counter/PSC3/rollback_counter.h
+++ b/boot/cypress/platforms/security_counter/PSC3/rollback_counter.h
@@ -7,7 +7,7 @@
*
*********************************************************************************
* \copyright
-* Copyright 2019-2024, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2019-2025 Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
diff --git a/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c
index 4218fe8..01e6dfb 100644
--- a/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c
+++ b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2020 Arm Limited.
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h
index b1fad71..bc47b27 100644
--- a/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h
+++ b/boot/cypress/platforms/security_counter/PSOC6/cy_security_cnt_platform.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2020 Arm Limited.
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/platforms/utils/CYW20829/platform_utils.c b/boot/cypress/platforms/utils/CYW20829/platform_utils.c
index d405caa..d6c7299 100644
--- a/boot/cypress/platforms/utils/CYW20829/platform_utils.c
+++ b/boot/cypress/platforms/utils/CYW20829/platform_utils.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
diff --git a/boot/cypress/platforms/utils/CYW20829/platform_utils.h b/boot/cypress/platforms/utils/CYW20829/platform_utils.h
index 3adc51a..4c5f895 100644
--- a/boot/cypress/platforms/utils/CYW20829/platform_utils.h
+++ b/boot/cypress/platforms/utils/CYW20829/platform_utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Infineon Technologies AG
+ * Copyright (c) 2025 Infineon Technologies AG
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -26,22 +26,7 @@
#include "bootutil/enc_key.h"
#include "bootutil/fault_injection_hardening.h"
-#ifdef CYW20829
-
-extern const volatile uint32_t __data_start__[];
-extern const volatile uint32_t __data_end__[];
-
-extern const volatile uint32_t __bss_start__[];
-extern const volatile uint32_t __bss_end__[];
-
-extern const volatile uint32_t __HeapBase[];
-extern const volatile uint32_t __HeapLimit[];
-
-extern const volatile uint32_t __StackLimit[];
-extern const volatile uint32_t __StackTop[];
-
__NO_RETURN void platform_RunNextApp(fih_uint toc2_addr, uint32_t *key, uint32_t *iv);
-#endif
#endif /* CYW_PLATFORMS_UTILS_H */
diff --git a/boot/cypress/platforms/utils/PSC3/cyw_platform_utils.h b/boot/cypress/platforms/utils/PSC3/cyw_platform_utils.h
index 1213bf8..d23da98 100644
--- a/boot/cypress/platforms/utils/PSC3/cyw_platform_utils.h
+++ b/boot/cypress/platforms/utils/PSC3/cyw_platform_utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2024, Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/utils/PSC3/platform_utils.h b/boot/cypress/platforms/utils/PSC3/platform_utils.h
index de18aba..6771f3a 100644
--- a/boot/cypress/platforms/utils/PSC3/platform_utils.h
+++ b/boot/cypress/platforms/utils/PSC3/platform_utils.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2024, Cypress Semiconductor Corporation (an Infineon company) or
+ * Copyright 2025, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/utils/PSOC6/platform_utils.c b/boot/cypress/platforms/utils/PSOC6/platform_utils.c
index db18b8c..9e91e9d 100644
--- a/boot/cypress/platforms/utils/PSOC6/platform_utils.c
+++ b/boot/cypress/platforms/utils/PSOC6/platform_utils.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or
+* (c) 2025, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/utils/PSOC6/platform_utils.h b/boot/cypress/platforms/utils/PSOC6/platform_utils.h
index af85c6c..51c82b2 100644
--- a/boot/cypress/platforms/utils/PSOC6/platform_utils.h
+++ b/boot/cypress/platforms/utils/PSOC6/platform_utils.h
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or
+* (c) 2025, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/utils/PSOC6/psoc6_02_cm0p_sleep.c b/boot/cypress/platforms/utils/PSOC6/psoc6_02_cm0p_sleep.c
index e5af3e6..15b818d 100644
--- a/boot/cypress/platforms/utils/PSOC6/psoc6_02_cm0p_sleep.c
+++ b/boot/cypress/platforms/utils/PSOC6/psoc6_02_cm0p_sleep.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* Copyright (c) 2018-2021 Cypress Semiconductor Corporation (an Infineon
+* Copyright (c) 2018-2025 Cypress Semiconductor Corporation (an Infineon
* company) or an affiliate of Cypress Semiconductor Corporation
* SPDX-License-Identifier: LicenseRef-PBL
*
diff --git a/boot/cypress/platforms/utils/XMC7000/cy_si_config.c b/boot/cypress/platforms/utils/XMC7000/cy_si_config.c
index 4a2d076..fce8494 100644
--- a/boot/cypress/platforms/utils/XMC7000/cy_si_config.c
+++ b/boot/cypress/platforms/utils/XMC7000/cy_si_config.c
@@ -1,5 +1,5 @@
/********************************************************************************
-* Copyright 2023 Infineon Technologies AG
+* Copyright 2025 Infineon Technologies AG
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/platforms/utils/XMC7000/cy_si_config.h b/boot/cypress/platforms/utils/XMC7000/cy_si_config.h
index 90d071a..1008ee5 100644
--- a/boot/cypress/platforms/utils/XMC7000/cy_si_config.h
+++ b/boot/cypress/platforms/utils/XMC7000/cy_si_config.h
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2023, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2025, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
diff --git a/boot/cypress/platforms/utils/XMC7000/cy_si_keystorage.h b/boot/cypress/platforms/utils/XMC7000/cy_si_keystorage.h
index 647f66e..3062bc5 100644
--- a/boot/cypress/platforms/utils/XMC7000/cy_si_keystorage.h
+++ b/boot/cypress/platforms/utils/XMC7000/cy_si_keystorage.h
@@ -7,7 +7,7 @@
*
********************************************************************************
* \copyright
-* Copyright 2017-2018, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2017-2025 Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
diff --git a/boot/cypress/platforms/utils/XMC7000/platform_utils.c b/boot/cypress/platforms/utils/XMC7000/platform_utils.c
index df140d3..6c7c7ee 100644
--- a/boot/cypress/platforms/utils/XMC7000/platform_utils.c
+++ b/boot/cypress/platforms/utils/XMC7000/platform_utils.c
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or
+* (c) 2025, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/platforms/utils/XMC7000/platform_utils.h b/boot/cypress/platforms/utils/XMC7000/platform_utils.h
index b82e8af..8741cb2 100644
--- a/boot/cypress/platforms/utils/XMC7000/platform_utils.h
+++ b/boot/cypress/platforms/utils/XMC7000/platform_utils.h
@@ -6,7 +6,7 @@
*
********************************************************************************
* \copyright
-* (c) 2022, Cypress Semiconductor Corporation (an Infineon company) or
+* (c) 2025, Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation.
*
* SPDX-License-Identifier: Apache-2.0
diff --git a/boot/cypress/run_toc2_generator.sh b/boot/cypress/run_toc2_generator.sh
index c8f65f3..44de9ec 100755
--- a/boot/cypress/run_toc2_generator.sh
+++ b/boot/cypress/run_toc2_generator.sh
@@ -1,4 +1,21 @@
#!/bin/bash
+################################################################################
+# \copyright
+# Copyright 2025 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
(set -o igncr) 2>/dev/null && set -o igncr; #keep this comment
echo_run() { echo "\$ ${@/eval/}" ; "$@" ; }
@@ -37,6 +54,12 @@
L1_USER_APP_ELF="$2/$3.elf"
: ${L1_USER_APP_ELF:="blinky.elf"}
+PLAIN_APP_BIN="$2/$3.plain_app.bin"
+: ${PLAIN_APP_BIN:="blinky.plain_app.bin"}
+
+PLAIN_APP_ENCRYPTED_BIN="$2/$3.plain_app_enc.bin"
+: ${PLAIN_APP_ENCRYPTED_BIN:="blinky.plain_app_enc.bin"}
+
FINAL_BIN_FILE="$2/$3.final.bin"
: ${FINAL_BIN_FILE:="blinky.final.bin"}
@@ -333,7 +356,20 @@
fi
# Combining all images (toc2+l1_app_desc+l1_user_app_header+l1_user_app) to Final binary file
- `cat $TOC2_FILE $L1_DESC_FILE $L1_USER_APP_HEADER_FILE $L1_USER_APP_BIN > $FINAL_BIN_FILE`
+ if [ "$ENC_OPTION" != "" ]; then
+ dd seek=16 bs=1 count=12 conv=notrunc if=$AES_CTR_NONCE_FILE of=$L1_DESC_FILE >& /dev/null
+
+ cat $L1_USER_APP_HEADER_FILE $L1_USER_APP_BIN > $PLAIN_APP_BIN
+
+ cysecuretools -t cyw20829 encrypt --input $PLAIN_APP_BIN --output $PLAIN_APP_ENCRYPTED_BIN --iv 0x08000030 --enckey ./keys/encrypt_key.bin --nonce $AES_CTR_NONCE_FILE
+
+ `cat $TOC2_FILE $L1_DESC_FILE $PLAIN_APP_ENCRYPTED_BIN > $FINAL_BIN_FILE`
+
+ else
+
+ `cat $TOC2_FILE $L1_DESC_FILE $L1_USER_APP_HEADER_FILE $L1_USER_APP_BIN > $FINAL_BIN_FILE`
+
+ fi
elif [ "$LCS" == "SECURE" ]; then
if [ ! -f "$L1_USER_APP_BIN" ]; then
echo "Error: $L1_USER_APP_BIN does not exist." > /dev/tty
diff --git a/boot/cypress/scripts/bin2c.py b/boot/cypress/scripts/bin2c.py
index 04bc67a..8cdf147 100644
--- a/boot/cypress/scripts/bin2c.py
+++ b/boot/cypress/scripts/bin2c.py
@@ -15,7 +15,7 @@
*
********************************************************************************
* \\copyright
-* Copyright (c) 2018-2019 Cypress Semiconductor Corporation
+* Copyright (c) 2018-2025 Cypress Semiconductor Corporation
* SPDX-License-Identifier: LicenseRef-PBL
*
* Licensed under the Permissive Binary License
diff --git a/boot/cypress/scripts/feature.py b/boot/cypress/scripts/feature.py
index a0a61c4..63d7cb9 100644
--- a/boot/cypress/scripts/feature.py
+++ b/boot/cypress/scripts/feature.py
@@ -1,5 +1,5 @@
"""
-Copyright 2024 Cypress Semiconductor Corporation (an Infineon company)
+Copyright 2025 Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/boot/cypress/scripts/find_cysectools.py b/boot/cypress/scripts/find_cysectools.py
index 8733575..83faaba 100644
--- a/boot/cypress/scripts/find_cysectools.py
+++ b/boot/cypress/scripts/find_cysectools.py
@@ -1,5 +1,5 @@
"""
-Copyright (c) 2019 Cypress Semiconductor Corporation
+Copyright (c) 2025 Cypress Semiconductor Corporation
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/boot/cypress/scripts/memorymap.py b/boot/cypress/scripts/memorymap.py
index d0799d6..3215dc4 100644
--- a/boot/cypress/scripts/memorymap.py
+++ b/boot/cypress/scripts/memorymap.py
@@ -1,14 +1,21 @@
"""MCUBoot Flash Map Converter (JSON to .h)
-Copyright (c) 2022 Infineon Technologies AG
+Copyright (c) 2025 Infineon Technologies AG
"""
import sys
import getopt
import json
+import os
from enum import Enum
-import os.path
+from cryptography.hazmat.primitives.ciphers import Cipher, algorithms, modes
MAX_IMAGE_NUMBERS = 16
+NONCE_GEN_RETRIES = 10
+NONCE_RAND_SIZE = 12
+AES_BLOCK_SIZE = 16
+IMG_OK_OFFSET = 8 + 16 # flag_size + magic_size
+IMG_OK_VALUE = 0x01
+SHAB_ADDR = 0x08000000
class Error(Enum):
''' Application error codes '''
@@ -230,31 +237,36 @@
self.plat_id = ''
self.in_file = ''
self.out_file = ''
+ self.mk_file = ''
self.fa_file = ''
+ self.nonce_file = None
self.img_id = None
self.policy = None
self.set_core = False
self.image_boot_config = False
usage = 'USAGE:\n' + sys.argv[0] + \
- ''' -p <platform> -i <flash_map.json> -o <memorymap.c> -a <memorymap.h> -d <img_id> -c <policy.json>
+ ''' -p <platform> -i <flash_map.json> -o <memorymap.c> -k <memorymap.mk> -a <memorymap.h> -d <img_id> -c <policy.json>
OPTIONS:
--h --help Display the usage information
--p --platform= Target (e.g., PSOC_062_512K)
--i --ifile= JSON flash map file
--o --ofile= C file to be generated
--a --fa_file= path where to create 'memorymap.h'
--d --img_id ID of application to build
--c --policy Policy file in JSON format
--m --core Detect and set Cortex-M CORE
+-h --help Display the usage information
+-p --platform Target (e.g., PSOC_062_512K)
+-i --ifile JSON flash map file
+-o --ofile C file to be generated
+-k --mk_file Path where to create 'memorymap.mk'
+-a --fa_file Path where to create 'memorymap.h'
+-n --nonce_file Path where to create file with NONCE
+-d --img_id ID of application to build
+-c --policy Policy file in JSON format
+-m --core Detect and set Cortex-M CORE
-x --image_boot_config Generate image boot config structure
'''
try:
opts, unused = getopt.getopt(
- sys.argv[1:], 'hi:o:a:p:d:c:x:m',
- ['help', 'platform=', 'ifile=', 'ofile=', "fa_file=", 'img_id=', 'policy=', 'core', 'image_boot_config'])
+ sys.argv[1:], 'h:i:o:k:a:n:p:d:c:x:m',
+ ['help', 'platform=', 'ifile=', 'ofile=', 'mk_file=', 'fa_file=',
+ 'nonce_file=', 'img_id=', 'policy=', 'core', 'image_boot_config'])
except getopt.GetoptError:
print(usage, file=sys.stderr)
sys.exit(Error.ARG)
@@ -269,8 +281,12 @@
self.in_file = arg
elif opt in ('-o', '--ofile'):
self.out_file = arg
+ elif opt in ('-k', '--mk_file'):
+ self.mk_file = arg
elif opt in ('-a', '--fa_file'):
self.fa_file = arg
+ elif opt in ('-n', '--nonce_file'):
+ self.nonce_file = arg
elif opt in ('-d', '--img_id'):
self.img_id = arg
elif opt in ('-c', '--policy'):
@@ -280,7 +296,7 @@
elif opt in ('x', '--image_boot_config'):
self.image_boot_config = True
- if len(self.in_file) == 0 or len(self.out_file) == 0 or len(self.fa_file) == 0:
+ if any(len(x) == 0 for x in (self.in_file, self.out_file, self.mk_file, self.fa_file)):
print(usage, file=sys.stderr)
sys.exit(Error.ARG)
@@ -351,6 +367,7 @@
self.plat = plat
self.flash = flash
self.use_overwrite = use_overwrite
+ self.use_direct_xip = False
self.areas = []
self.peers = {}
self.trailers = {}
@@ -655,7 +672,7 @@
out_f.write(f'#include "{params.fa_file}"\n')
out_f.write(f'#include "flash_map_backend.h"\n\n')
out_f.write(f'#include "flash_map_backend_platform.h"\n\n')
- out_f.write(f'struct flash_area {c_array}[] = {{\n')
+ out_f.write(f'const struct flash_area {c_array}[] = {{\n')
comma = len(self.areas)
area_count = 0
for area in self.areas:
@@ -672,7 +689,7 @@
' },' if comma else ' }', '']))
area_count += 1
out_f.write('};\n\n'
- 'struct flash_area *boot_area_descs[] = {\n')
+ 'const struct flash_area * const boot_area_descs[] = {\n')
for area_index in range(area_count):
out_f.write(f' &{c_array}[{area_index}U],\n')
out_f.write(' NULL\n};\n')
@@ -721,8 +738,8 @@
fa_f.write(f'#include "flash_map_backend.h"\n\n')
fa_f.write('#include "bootutil/bootutil.h"\n')
- fa_f.write(f'extern struct flash_area {c_array}[];\n')
- fa_f.write(f'extern struct flash_area *boot_area_descs[];\n')
+ fa_f.write(f'extern const struct flash_area {c_array}[];\n')
+ fa_f.write(f'extern const struct flash_area * const boot_area_descs[];\n')
#we always have BOOTLOADER and IMG_1_
fa_f.write("#define FLASH_AREA_BOOTLOADER ( 0u)\n\n")
@@ -991,10 +1008,19 @@
ram = None
try:
- primary_addr = get_val(flash, 'address')
- primary_size = get_val(flash, 'size')
- secondary_addr = get_val(flash, 'upgrade_address')
- secondary_size = get_val(flash, 'upgrade_size')
+ try:
+ primary_addr = get_val(flash, 'primary_slot')
+ secondary_addr = get_val(flash, 'secondary_slot')
+ primary_size = get_val(flash, 'primary_slot_size')
+ secondary_size = get_val(flash, 'secondary_slot_size')
+
+ area_list.use_direct_xip = True
+
+ except KeyError:
+ primary_addr = get_val(flash, 'address')
+ secondary_addr = get_val(flash, 'upgrade_address')
+ primary_size = get_val(flash, 'size')
+ secondary_size = get_val(flash, 'upgrade_size')
if ram is not None:
app_ram_addr = get_val(ram, 'address')
@@ -1235,8 +1261,7 @@
app_desc = None
if service_app is not None:
if plat['flashSize'] > 0:
- print('service_app is unsupported on this platform',
- file=sys.stderr)
+ print('service_app is unsupported on this platform', file=sys.stderr)
sys.exit(Error.CONFIG_MISMATCH)
try:
app_binary = AddrSize(service_app, 'address', 'size')
@@ -1250,8 +1275,7 @@
area_list.add_area('service_app', None, app_binary.addr,
app_binary.size + input_params.size + app_desc.size)
except KeyError as key:
- print('Malformed JSON:', key, 'is missing',
- file=sys.stderr)
+ print('Malformed JSON:', key, 'is missing', file=sys.stderr)
sys.exit(Error.JSON)
# Fill flash areas
@@ -1263,8 +1287,7 @@
if app_start % plat['VTAlign'] != 0:
print('Starting address', apps_flash_map[1].get("primary").get("address"),
- '+', hex(cy_img_hdr_size),
- 'must be aligned to', hex(plat['VTAlign']),
+ '+', hex(cy_img_hdr_size), 'must be aligned to', hex(plat['VTAlign']),
file=sys.stderr)
sys.exit(Error.CONFIG_MISMATCH)
@@ -1308,39 +1331,45 @@
area_list.create_flash_area_id(app_count, params)
- # Report necessary values back to make
- print('# AUTO-GENERATED FILE, DO NOT EDIT. ALL CHANGES WILL BE LOST!')
+ # Write necessary values to makefile
+ try:
+ mk_file = open(params.mk_file, "w")
+ except (FileNotFoundError, OSError):
+ print('\nERROR: Cannot create ', params.mk_file, file=sys.stderr)
+ sys.exit(Error.IO)
+
+ print('# AUTO-GENERATED FILE, DO NOT EDIT. ALL CHANGES WILL BE LOST!', file=mk_file)
if params.set_core:
- print('CORE :=', plat['allCores'][plat['bootCore'].lower()])
+ print('CORE :=', plat['allCores'][plat['bootCore'].lower()], file=mk_file)
if ram_app_staging is not None:
- print('USE_STAGE_RAM_APPS := 1')
- print('RAM_APP_STAGING_EXT_MEM_ADDR := ', hex(ram_app_staging_ext_mem_addr))
- print('RAM_APP_STAGING_SRAM_MEM_ADDR :=', hex(ram_app_staging_sram_stage_addr))
- print('RAM_APP_STAGING_SIZE := ', hex(ram_app_staging_size))
+ print('USE_STAGE_RAM_APPS := 1', file=mk_file)
+ print('RAM_APP_STAGING_EXT_MEM_ADDR := ', hex(ram_app_staging_ext_mem_addr), file=mk_file)
+ print('RAM_APP_STAGING_SRAM_MEM_ADDR :=', hex(ram_app_staging_sram_stage_addr), file=mk_file)
+ print('RAM_APP_STAGING_SIZE := ', hex(ram_app_staging_size), file=mk_file)
if ram_app_staging_reset_trigger is True:
- print('RAM_APP_RESET_TRIGGER := 1')
+ print('RAM_APP_RESET_TRIGGER := 1', file=mk_file)
if bootloader_startup is True:
- print('BOOTLOADER_STARTUP := 1')
+ print('BOOTLOADER_STARTUP := 1', file=mk_file)
if ram_app_area is not None:
- print('USE_MCUBOOT_RAM_LOAD := 1')
- print('IMAGE_EXECUTABLE_RAM_START :=', hex(ram_app_area.addr))
- print('IMAGE_EXECUTABLE_RAM_SIZE :=', hex(ram_app_area.size))
+ print('USE_MCUBOOT_RAM_LOAD := 1', file=mk_file)
+ print('IMAGE_EXECUTABLE_RAM_START :=', hex(ram_app_area.addr), file=mk_file)
+ print('IMAGE_EXECUTABLE_RAM_SIZE :=', hex(ram_app_area.size), file=mk_file)
if boot_shared_data_area is not None:
- print('USE_MEASURED_BOOT := 1')
- print('USE_DATA_SHARING := 1')
- print('BOOT_SHARED_DATA_ADDRESS :=', hex(boot_shared_data_area.addr)+'U')
- print('BOOT_SHARED_DATA_SIZE :=', hex(boot_shared_data_area.size)+'U')
- print('BOOT_SHARED_DATA_RECORD_SIZE :=', hex(boot_shared_data_area.size)+'U')
+ print('USE_MEASURED_BOOT := 1', file=mk_file)
+ print('USE_DATA_SHARING := 1', file=mk_file)
+ print('BOOT_SHARED_DATA_ADDRESS :=', hex(boot_shared_data_area.addr)+'U', file=mk_file)
+ print('BOOT_SHARED_DATA_SIZE :=', hex(boot_shared_data_area.size)+'U', file=mk_file)
+ print('BOOT_SHARED_DATA_RECORD_SIZE :=', hex(boot_shared_data_area.size)+'U', file=mk_file)
- print('BOOTLOADER_ORIGIN :=', hex(boot_flash_area.addr))
- print('BOOTLOADER_SIZE :=', hex(boot_flash_area.size))
- print('BOOTLOADER_RAM_ORIGIN :=', hex(boot_ram_area.addr))
- print('BOOTLOADER_RAM_SIZE :=', hex(boot_ram_area.size))
- print('APP_CORE :=', app_core)
+ print('BOOTLOADER_ORIGIN :=', hex(boot_flash_area.addr), file=mk_file)
+ print('BOOTLOADER_SIZE :=', hex(boot_flash_area.size), file=mk_file)
+ print('BOOTLOADER_RAM_ORIGIN :=', hex(boot_ram_area.addr), file=mk_file)
+ print('BOOTLOADER_RAM_SIZE :=', hex(boot_ram_area.size), file=mk_file)
+ print('APP_CORE :=', app_core, file=mk_file)
# for blinky
if params.img_id is not None:
@@ -1353,14 +1382,14 @@
image_ram_size = apps_ram_map[int(params.img_id)].get("size")
image_ram_boot = apps_ram_map[int(params.img_id)].get("ram_boot")
if image_ram_address and image_ram_size:
- print('IMG_RAM_ORIGIN := ' + hex(image_ram_address))
- print('IMG_RAM_SIZE := ' + hex(image_ram_size))
+ print('IMG_RAM_ORIGIN := ' + hex(image_ram_address), file=mk_file)
+ print('IMG_RAM_SIZE := ' + hex(image_ram_size), file=mk_file)
if image_ram_boot is True:
- print('USE_MCUBOOT_RAM_LOAD := 1')
+ print('USE_MCUBOOT_RAM_LOAD := 1', file=mk_file)
- print('PRIMARY_IMG_START := ' + primary_img_start)
- print('SECONDARY_IMG_START := ' + secondary_img_start)
- print('SLOT_SIZE := ' + slot_size)
+ print('PRIMARY_IMG_START := ' + primary_img_start, file=mk_file)
+ print('SECONDARY_IMG_START := ' + secondary_img_start, file=mk_file)
+ print('SLOT_SIZE := ' + slot_size, file=mk_file)
# for bootloader
else:
if apps_ram_map:
@@ -1370,34 +1399,96 @@
ram_load_counter += 1
if ram_load_counter != 0:
- print('USE_MCUBOOT_RAM_LOAD := 1')
+ print('USE_MCUBOOT_RAM_LOAD := 1', file=mk_file)
if ram_load_counter == 1:
- print(f'IMAGE_EXECUTABLE_RAM_START := {hex(apps_ram_map[1].get("address"))}')
- print(f'IMAGE_EXECUTABLE_RAM_SIZE := {hex(apps_ram_map[1].get("size"))}')
+ print(f'IMAGE_EXECUTABLE_RAM_START := {hex(apps_ram_map[1].get("address"))}', file=mk_file)
+ print(f'IMAGE_EXECUTABLE_RAM_SIZE := {hex(apps_ram_map[1].get("size"))}', file=mk_file)
else:
- print('USE_MCUBOOT_MULTI_MEMORY_LOAD := 1')
+ print('USE_MCUBOOT_MULTI_MEMORY_LOAD := 1', file=mk_file)
- print('MAX_IMG_SECTORS :=', slot_sectors_max)
+ print('MAX_IMG_SECTORS :=', slot_sectors_max, file=mk_file)
- print('MCUBOOT_IMAGE_NUMBER :=', app_count)
+ print('MCUBOOT_IMAGE_NUMBER :=', app_count, file=mk_file)
if area_list.external_flash:
- print('USE_EXTERNAL_FLASH := 1')
+ print('USE_EXTERNAL_FLASH := 1', file=mk_file)
if area_list.external_flash_xip:
- print('USE_XIP := 1')
+ print('USE_XIP := 1', file=mk_file)
- if area_list.use_overwrite:
- print('USE_OVERWRITE := 1')
+ if area_list.use_direct_xip:
+ print('USE_DIRECT_XIP := 1', file=mk_file)
+ elif area_list.use_overwrite:
+ print('USE_OVERWRITE := 1', file=mk_file)
+
if shared_slot:
- print('USE_SHARED_SLOT := 1')
+ print('USE_SHARED_SLOT := 1', file=mk_file)
if service_app is not None:
print('PLATFORM_SERVICE_APP_OFFSET :=',
- hex(app_binary.addr - plat['smifAddr']))
+ hex(app_binary.addr - plat['smifAddr']), file=mk_file)
print('PLATFORM_SERVICE_APP_INPUT_PARAMS_OFFSET :=',
- hex(input_params.addr - plat['smifAddr']))
+ hex(input_params.addr - plat['smifAddr']), file=mk_file)
print('PLATFORM_SERVICE_APP_DESC_OFFSET :=',
- hex(app_desc.addr - plat['smifAddr']))
- print('USE_HW_ROLLBACK_PROT := 1')
+ hex(app_desc.addr - plat['smifAddr']), file=mk_file)
+ print('USE_HW_ROLLBACK_PROT := 1', file=mk_file)
+ mk_file.close()
+ if params.nonce_file and not os.path.isfile(params.nonce_file):
+ try:
+ with open(params.policy, encoding='UTF-8') as in_f:
+ try:
+ policy = json.load(in_f)
+ except ValueError:
+ print('\nERROR: Cannot parse', params.policy, '\n', file=sys.stderr)
+ sys.exit(Error.IO)
+ except (FileNotFoundError, OSError):
+ print('\nERROR: Cannot open', params.policy, file=sys.stderr)
+ sys.exit(Error.IO)
+
+ policy_key_path = policy.get('pre_build', {}).get('keys', {}).get('encrypt_key', {}).get('value', {})
+ if policy_key_path:
+ full_key_path = os.path.join(os.path.dirname(params.policy), policy_key_path)
+ try:
+ with open(full_key_path, "rb") as aes_key_file:
+ aes_key = aes_key_file.read()
+ except (FileNotFoundError, OSError):
+ print('Missing encryption key', full_key_path, '\nNonce file generation skipped')
+ sys.exit(0)
+
+ if len(aes_key) != AES_BLOCK_SIZE:
+ print('\nERROR: Wrong AES key size in ', full_key_path, file=sys.stderr)
+ sys.exit(Error.CONFIG_MISMATCH)
+
+ for i in range(NONCE_GEN_RETRIES):
+ random_bytes = os.urandom(NONCE_RAND_SIZE)
+ fa_ids = [entry['fa_off'] + entry['fa_size'] for entry in area_list.areas
+ if entry['fa_id'].startswith('FLASH_AREA_IMG_')]
+ for fa_end_addr in fa_ids:
+ img_ok_addr = SHAB_ADDR + fa_end_addr - IMG_OK_OFFSET
+ img_ok_block_addr = img_ok_addr & ~(AES_BLOCK_SIZE - 1)
+ nonce = img_ok_block_addr.to_bytes(AES_BLOCK_SIZE - NONCE_RAND_SIZE,
+ byteorder='little') + random_bytes
+ cipher = Cipher(algorithms.AES(aes_key), modes.CTR(nonce))
+ encryptor_0 = cipher.encryptor()
+ encryptor_1 = cipher.encryptor()
+ encrypted_block_0 = encryptor_0.update(b'\x00' * AES_BLOCK_SIZE)
+ encrypted_block_1 = encryptor_1.update(b'\xFF' * AES_BLOCK_SIZE)
+
+ if encrypted_block_0[img_ok_addr - img_ok_block_addr] == IMG_OK_VALUE or \
+ encrypted_block_1[img_ok_addr - img_ok_block_addr] == IMG_OK_VALUE:
+ break
+ else:
+ break
+ else:
+ print("\nERROR: Can't generate valid NONCE sequence", file=sys.stderr)
+ sys.exit(Error.VALUE)
+
+ try:
+ if '/' in params.nonce_file or '\\' in params.nonce_file:
+ os.makedirs(os.path.dirname(params.nonce_file), exist_ok=True)
+ with open(params.nonce_file, "wb") as nonce_f:
+ nonce_f.write(random_bytes)
+ except (FileNotFoundError, OSError):
+ print('\nERROR: Cannot create ', params.nonce_file, file=sys.stderr)
+ sys.exit(Error.IO)
if __name__ == '__main__':
main()
diff --git a/boot/cypress/scripts/memorymap_rework.py b/boot/cypress/scripts/memorymap_rework.py
index 01b541f..5167475 100644
--- a/boot/cypress/scripts/memorymap_rework.py
+++ b/boot/cypress/scripts/memorymap_rework.py
@@ -1,5 +1,5 @@
"""
-Copyright 2024 Cypress Semiconductor Corporation (an Infineon company)
+Copyright 2025 Cypress Semiconductor Corporation (an Infineon company)
or an affiliate of Cypress Semiconductor Corporation. All rights reserved.
Licensed under the Apache License, Version 2.0 (the "License");
@@ -57,6 +57,8 @@
, 'secondary_image_start' : 'SECONDARY_IMG_START'
, 'secondary_image_area' : 'SECONDARY_IMG_AREA'
, 'image_size' : 'SLOT_SIZE'
+ , 'erase_size' : 'MIN_ERASE_SIZE'
+ , 'erase_value' : 'ERASE_VALUE'
}
def header_guard_generate(file):
@@ -316,8 +318,7 @@
if region_name_alt:
if "boot" in key:
- if region_name_alt not in self.region_types_alt:
- self.region_types_alt.append(region_name_alt)
+ self.region_types_alt.append(region_name_alt)
offset = area.addr - region.addr
size = area.sz
@@ -409,14 +410,13 @@
f_out.write('struct flash_device flash_devices[] =\n')
f_out.write('{\n')
for region in self.regions:
- if region.mem_type[0] in self.region_types:
- f_out.write('\t{\n')
- f_out.write(f'\t\t.address = {hex(region.addr)}U,\n')
- f_out.write(f'\t\t.size = {hex(region.sz)}U,\n')
- f_out.write(f'\t\t.erase_size = {hex(region.erase_sz)}U,\n')
- f_out.write(f'\t\t.erase_val = {hex(region.erase_val)}U,\n')
- f_out.write(f'\t\t.device_id = {str(region.mem_type[0])},\n')
- f_out.write('\t},\n')
+ f_out.write(f'\t[{region.mem_type[0]}] = ' + '{\n')
+ f_out.write(f'\t\t.address = {hex(region.addr)}U,\n')
+ f_out.write(f'\t\t.size = {hex(region.sz)}U,\n')
+ f_out.write(f'\t\t.erase_size = {hex(region.erase_sz)}U,\n')
+ f_out.write(f'\t\t.erase_val = {hex(region.erase_val)}U,\n')
+ f_out.write(f'\t\t.device_id = {str(region.mem_type[0])},\n')
+ f_out.write('\t},\n')
f_out.write('};\n\n')
f_out.write(f'struct flash_area flash_areas[] =\n')
@@ -450,7 +450,7 @@
f_out.write('\n};\n\n')
f_out.write('image_boot_config_t image_boot_config[BOOT_IMAGE_NUMBER] = {\n')
-
+
for app in self.apps:
f_out.writelines('\n'.join([
'\t{\n'
@@ -484,8 +484,7 @@
# because it fixes the bug when enum {INTERNAL_RRAM, EXTERNAL_FLASH,}
# is generated in incorrect sequence.
for region in self.regions:
- if region.mem_type[0] in self.region_types:
- f_out.write(f'\t{str(region.mem_type[0])},\n')
+ f_out.write(f'\t{str(region.mem_type[0])},\n')
f_out.write('};\n\n')
f_out.write('enum \n{\n')
@@ -539,6 +538,11 @@
print(f'{settings_dict["shared_data_size"]} :=', hex(shared_data.sz))
print(f'{settings_dict["shared_data_record_size"]} :=', hex(shared_data.sz))
+ print('# Bootloader erase area')
+ for region in self.regions:
+ print(f'{region.mem_type[0]}_{settings_dict["erase_size"]} :=', hex(region.erase_sz))
+ print(f'{region.mem_type[0]}_{settings_dict["erase_value"]} :=', hex(region.erase_val))
+
print('# Bootloader app area')
for region in self.regions:
if boot.bootloader_area.fits_with(region):
@@ -552,7 +556,7 @@
print('# Bootloader ram area')
print(f'{settings_dict["bootloader_ram_address"]} :=', hex(boot.ram.addr))
print(f'{settings_dict["bootloader_ram_size"]} :=', hex(boot.ram.sz))
-
+
if boot.ram_boot:
print(f'{settings_dict["bootloader_ram_load"]} := 1')
print(f'{settings_dict["bootloader_ram_address"]} :=', hex(boot.ram_boot.addr))
@@ -628,6 +632,12 @@
print(settings_dict['scratch'], f':= {0 if boot.scratch_area is None else 1}')
print(settings_dict['status'], f':= {0 if boot.status_area is None else 1}')
+ print('# Application erase area')
+ for region in self.regions:
+ print(f'{region.mem_type[0]}_{settings_dict["erase_size"]} :=', hex(region.erase_sz))
+ print(f'{region.mem_type[0]}_{settings_dict["erase_value"]} :=', hex(region.erase_val))
+
+ print('# Application area')
print(settings_dict['application_count'], f'= {len(self.apps)}')
print(settings_dict['boot_image'], ':=', self.app_id)
print(settings_dict['primary_image_start'], ':=', hex(app.boot_area.addr))
diff --git a/boot/cypress/scripts/verbose_make.py b/boot/cypress/scripts/verbose_make.py
index c9cc037..c9d2d34 100644
--- a/boot/cypress/scripts/verbose_make.py
+++ b/boot/cypress/scripts/verbose_make.py
@@ -1,5 +1,5 @@
"""VERBOSE Makefile Generator
-Copyright (c) 2022 Infineon Technologies AG
+Copyright (c) 2025 Infineon Technologies AG
"""
import os
diff --git a/boot/cypress/toolchains.mk b/boot/cypress/toolchains.mk
index 1208def..39876fe 100644
--- a/boot/cypress/toolchains.mk
+++ b/boot/cypress/toolchains.mk
@@ -7,7 +7,7 @@
#
################################################################################
# \copyright
-# Copyright 2018-2019 Cypress Semiconductor Corporation
+# Copyright 2018-2025 Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
#
# Licensed under the Apache License, Version 2.0 (the "License");
@@ -39,7 +39,7 @@
# NOTE: Absolute pathes for now for the sake of development
ifeq ($(HOST_OS), win)
ifeq ($(COMPILER), GCC_ARM)
- TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/ModusToolbox/tools_3.2/gcc
+ TOOLCHAIN_PATH ?= c:/Users/$(USERNAME)/Infineon/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
MY_TOOLCHAIN_PATH := $(call get_os_path, $(TOOLCHAIN_PATH))
TOOLCHAIN_PATH := $(MY_TOOLCHAIN_PATH)
GCC_PATH := $(TOOLCHAIN_PATH)
@@ -49,14 +49,14 @@
endif
else ifeq ($(HOST_OS), osx)
- TOOLCHAIN_PATH ?= /opt/gcc-arm-none-eabi
+ TOOLCHAIN_PATH ?= /Applications/mtb-gcc-arm-eabi/11.3.1/gcc
GCC_PATH := $(TOOLCHAIN_PATH)
-
+ # executables
CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
LD := $(CC)
else ifeq ($(HOST_OS), linux)
- TOOLCHAIN_PATH ?= /opt/gcc-arm-none-eabi
+ TOOLCHAIN_PATH ?= /opt/Tools/mtb-gcc-arm-eabi/11.3.1/gcc
GCC_PATH := $(TOOLCHAIN_PATH)
# executables
CC := "$(GCC_PATH)/bin/arm-none-eabi-gcc"
@@ -90,11 +90,11 @@
$(error BUILDCFG : '$(BUILDCFG)' is not supported)
endif
- CFLAGS := $(CFLAGS_COMMON) $(CFLAGS_PLATFORM) $(INCLUDES)
+ CFLAGS := $(CFLAGS_COMMON) $(CFLAGS_PLATFORM) $(INCLUDES) -ffreestanding -fno-builtin-memset -fno-builtin-memcpy
CC_DEPEND = -MD -MP -MF
- LDFLAGS_COMMON := -mcpu=cortex-$(CORE_SUFFIX) -mthumb -specs=nano.specs -ffunction-sections -fdata-sections -Wl,--gc-sections -ffat-lto-objects -g --enable-objc-gc
+ LDFLAGS_COMMON := -mcpu=cortex-$(CORE_SUFFIX) -mthumb -specs=nano.specs -ffunction-sections -fdata-sections -Wl,--gc-sections -ffat-lto-objects -g --enable-objc-gc -ffreestanding -fno-builtin-memset -fno-builtin-memcpy
ifeq ($(WARN_AS_ERR), 1)
LDFLAGS_COMMON += -Wl,--fatal-warnings
diff --git a/ext/mbedtls b/ext/mbedtls
index 8df2f8e..1873d3b 160000
--- a/ext/mbedtls
+++ b/ext/mbedtls
@@ -1 +1 @@
-Subproject commit 8df2f8e7b9c7bb9390ac74bb7bace27edca81a2b
+Subproject commit 1873d3bfc2da771672bd8e7e8f41f57e0af77f33
diff --git a/sim/mcuboot-sys/build.rs b/sim/mcuboot-sys/build.rs
index 294aea6..c00162b 100644
--- a/sim/mcuboot-sys/build.rs
+++ b/sim/mcuboot-sys/build.rs
@@ -42,7 +42,8 @@
conf.conf.define("MCUBOOT_USE_FLASH_AREA_GET_SECTORS", None);
conf.conf.define("MCUBOOT_HAVE_ASSERT_H", None);
conf.conf.define("MCUBOOT_MAX_IMG_SECTORS", Some("128"));
-
+ conf.conf.define("MCUBOOT_DEPENDENCY_CHECK", None);
+
if max_align_32 {
conf.conf.define("MCUBOOT_BOOT_MAX_ALIGN", Some("32"));
} else {
@@ -100,7 +101,11 @@
conf.file("csupport/keys.c");
conf.file("../../ext/mbedtls/library/rsa.c");
+ conf.file("../../ext/mbedtls/library/hash_info.c");
conf.file("../../ext/mbedtls/library/bignum.c");
+ conf.file("../../ext/mbedtls/library/bignum_core.c");
+ conf.file("../../ext/mbedtls/library/bignum_mod_raw.c");
+ conf.file("../../ext/mbedtls/library/constant_time.c");
conf.file("../../ext/mbedtls/library/platform.c");
conf.file("../../ext/mbedtls/library/platform_util.c");
conf.file("../../ext/mbedtls/library/asn1parse.c");
@@ -132,6 +137,9 @@
conf.file("../../ext/mbedtls/library/asn1parse.c");
conf.file("../../ext/mbedtls/library/bignum.c");
+ conf.file("../../ext/mbedtls/library/bignum_core.c");
+ conf.file("../../ext/mbedtls/library/bignum_mod_raw.c");
+ conf.file("../../ext/mbedtls/library/constant_time.c");
conf.file("../../ext/mbedtls/library/ecdsa.c");
conf.file("../../ext/mbedtls/library/ecp.c");
conf.file("../../ext/mbedtls/library/ecp_curves.c");
@@ -201,10 +209,14 @@
conf.file("../../ext/mbedtls/library/platform.c");
conf.file("../../ext/mbedtls/library/platform_util.c");
conf.file("../../ext/mbedtls/library/rsa.c");
+ conf.file("../../ext/mbedtls/library/hash_info.c");
conf.file("../../ext/mbedtls/library/rsa_alt_helpers.c");
conf.file("../../ext/mbedtls/library/md.c");
conf.file("../../ext/mbedtls/library/aes.c");
conf.file("../../ext/mbedtls/library/bignum.c");
+ conf.file("../../ext/mbedtls/library/bignum_core.c");
+ conf.file("../../ext/mbedtls/library/bignum_mod_raw.c");
+ conf.file("../../ext/mbedtls/library/constant_time.c");
conf.file("../../ext/mbedtls/library/asn1parse.c");
}
@@ -228,6 +240,7 @@
conf.conf.include("../../ext/mbedtls/library");
conf.file("../../ext/mbedtls/library/platform_util.c");
conf.file("../../ext/mbedtls/library/nist_kw.c");
+ conf.file("../../ext/mbedtls/library/constant_time.c");
conf.file("../../ext/mbedtls/library/cipher.c");
conf.file("../../ext/mbedtls/library/cipher_wrap.c");
conf.file("../../ext/mbedtls/library/aes.c");
@@ -292,6 +305,9 @@
conf.file("../../ext/mbedtls/library/sha256.c");
conf.file("../../ext/mbedtls/library/asn1parse.c");
conf.file("../../ext/mbedtls/library/bignum.c");
+ conf.file("../../ext/mbedtls/library/bignum_core.c");
+ conf.file("../../ext/mbedtls/library/bignum_mod_raw.c");
+ conf.file("../../ext/mbedtls/library/constant_time.c");
conf.file("../../ext/mbedtls/library/ecdh.c");
conf.file("../../ext/mbedtls/library/md.c");
conf.file("../../ext/mbedtls/library/aes.c");
@@ -391,8 +407,7 @@
conf.conf.include("../../boot/zephyr/include");
conf.conf.debug(true);
conf.conf.flag("-Wall");
- conf.conf.flag("-Werror");
-
+
// FIXME: travis-ci still uses gcc 4.8.4 which defaults to std=gnu90.
// It has incomplete std=c11 and std=c99 support but std=c99 was checked
// to build correctly so leaving it here to updated in the future...