blob: 5766ab520da1da00f38b094d1f360ed6a7d6a7d8 [file] [log] [blame]
Roman Okhrimenko89ecdac2020-02-28 17:05:55 +02001/*******************************************************************************
2* File Name: cycfg_clocks.h
3*
4* Description:
5* Clock configuration
6* This file was automatically generated and should not be modified.
7* Device Configurator: 2.0.0.1483
8* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
9*
10********************************************************************************
11* Copyright 2017-2019 Cypress Semiconductor Corporation
12* SPDX-License-Identifier: Apache-2.0
13*
14* Licensed under the Apache License, Version 2.0 (the "License");
15* you may not use this file except in compliance with the License.
16* You may obtain a copy of the License at
17*
18* http://www.apache.org/licenses/LICENSE-2.0
19*
20* Unless required by applicable law or agreed to in writing, software
21* distributed under the License is distributed on an "AS IS" BASIS,
22* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23* See the License for the specific language governing permissions and
24* limitations under the License.
25********************************************************************************/
26
27#if !defined(CYCFG_CLOCKS_H)
28#define CYCFG_CLOCKS_H
29
30#include "cy_sysclk.h"
31#if defined (CY_USING_HAL)
32 #include "cyhal_hwmgr.h"
33#endif //defined (CY_USING_HAL)
34
35#if defined(__cplusplus)
36extern "C" {
37#endif
38
39#define CYBSP_CSD_CLK_DIV_ENABLED 1U
40#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
41#define CYBSP_CSD_CLK_DIV_NUM 0U
42
43#if defined (CY_USING_HAL)
44 extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
45#endif //defined (CY_USING_HAL)
46
47void init_cycfg_clocks(void);
48
49#if defined(__cplusplus)
50}
51#endif
52
53
54#endif /* CYCFG_CLOCKS_H */