diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index f3ff0ca..f3c98d8 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -140,6 +140,7 @@
 #define ID_AA64PFR0_AMU_V1P1	U(0x2)
 #define ID_AA64PFR0_ELX_MASK	ULL(0xf)
 #define ID_AA64PFR0_SVE_SHIFT	U(32)
+#define ID_AA64PFR0_SVE_WIDTH	U(4)
 #define ID_AA64PFR0_SVE_MASK	ULL(0xf)
 #define ID_AA64PFR0_SVE_LENGTH	U(4)
 #define ID_AA64PFR0_MPAM_SHIFT	U(40)
@@ -389,6 +390,11 @@
 #define CPACR_EL1_FP_TRAP_ALL	U(0x2)
 #define CPACR_EL1_FP_TRAP_NONE	U(0x3)
 
+#define CPACR_EL1_ZEN(x)	((x) << 16)
+#define CPACR_EL1_ZEN_TRAP_EL0	U(0x1)
+#define CPACR_EL1_ZEN_TRAP_ALL	U(0x2)
+#define CPACR_EL1_ZEN_TRAP_NONE	U(0x3)
+
 /* SCR definitions */
 #define SCR_RES1_BITS		((U(1) << 4) | (U(1) << 5))
 #define SCR_AMVOFFEN_BIT	(UL(1) << 35)
@@ -852,14 +858,17 @@
 /*******************************************************************************
  * Definitions for system register interface to SVE
  ******************************************************************************/
-#define ZCR_EL3			S3_6_C1_C2_0
-#define ZCR_EL2			S3_4_C1_C2_0
-
-/* ZCR_EL3 definitions */
-#define ZCR_EL3_LEN_MASK	U(0xf)
+#define ID_AA64ZFR0_EL1		S3_0_C0_C4_4
 
 /* ZCR_EL2 definitions */
-#define ZCR_EL2_LEN_MASK	U(0xf)
+#define ZCR_EL2			S3_4_C1_C2_0
+#define ZCR_EL2_SVE_VL_SHIFT	UL(0)
+#define ZCR_EL2_SVE_VL_WIDTH	UL(4)
+
+/* ZCR_EL1 definitions */
+#define ZCR_EL1			S3_0_C1_C2_0
+#define ZCR_EL1_SVE_VL_SHIFT	UL(0)
+#define ZCR_EL1_SVE_VL_WIDTH	UL(4)
 
 /*******************************************************************************
  * Definitions for system register interface to SME
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index b7c0418..77dc881 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -509,8 +509,10 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(pmbsr_el1, PMBSR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(pmscr_el2, PMSCR_EL2)
 
-DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
-DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
+/* Definitions for system register interface to SVE */
+DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64zfr0_el1, ID_AA64ZFR0_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(zcr_el2, ZCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(zcr_el1, ZCR_EL1)
 
 DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(svcr, SVCR)
diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h
index 07bd663..994fbfe 100644
--- a/include/lib/extensions/sve.h
+++ b/include/lib/extensions/sve.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,6 +7,8 @@
 #ifndef SVE_H
 #define SVE_H
 
+#include <arch.h>
+
 #define fill_sve_helper(num) "ldr z"#num", [%0, #"#num", MUL VL];"
 #define read_sve_helper(num) "str z"#num", [%0, #"#num", MUL VL];"
 
@@ -17,10 +19,21 @@
 #define SVE_VECTOR_LEN_BYTES		256
 #define SVE_NUM_VECTORS			32
 
+#define SVE_VQ_ARCH_MAX			((1 << ZCR_EL2_SVE_VL_WIDTH) - 1)
+
+/* convert SVE VL in bytes to VQ */
+#define SVE_VL_TO_VQ(vl_bytes)		(((vl_bytes) >> 4U) - 1)
+
+/* convert SVE VQ to bits */
+#define SVE_VQ_TO_BITS(vq)		(((vq) + 1U) << 7U)
+
 #ifndef __ASSEMBLY__
 
 typedef uint8_t sve_vector_t[SVE_VECTOR_LEN_BYTES];
 
+void sve_config_vq(uint8_t sve_vq);
+uint32_t sve_probe_vl(uint8_t sve_max_vq);
+
 #ifdef __aarch64__
 
 /* Returns the SVE implemented VL in bytes (constrained by ZCR_EL3.LEN) */
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 9dcf58d..8a54e60 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -162,7 +162,10 @@
 
 #define COMPILER_BARRIER() __asm__ volatile ("" ::: "memory")
 
-#define MASK(regfield) \
+#define INPLACE(regfield, val)						\
+	(((val) + UL(0)) << (regfield##_SHIFT))
+
+#define MASK(regfield)							\
 	((~0ULL >> (64ULL - (regfield##_WIDTH))) << (regfield##_SHIFT))
 
 #define EXTRACT(regfield, reg) \