diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 77878e6..cfc573c 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -104,7 +104,6 @@
 #define ICC_EOIR0_EL1		S3_0_C12_C8_1
 #define ICC_EOIR1_EL1		S3_0_C12_C12_1
 #define ICC_SGI0R_EL1		S3_0_C12_C11_7
-
 #define ICV_CTRL_EL1		S3_0_C12_C12_4
 #define ICV_IAR1_EL1		S3_0_C12_C12_0
 #define ICV_IGRPEN1_EL1		S3_0_C12_C12_7
@@ -112,6 +111,29 @@
 #define ICV_PMR_EL1		S3_0_C4_C6_0
 
 /*******************************************************************************
+ * Definitions for EL2 system registers.
+ ******************************************************************************/
+#define CNTPOFF_EL2		S3_4_C14_C0_6
+#define HDFGRTR2_EL2		S3_4_C3_C1_0
+#define HDFGWTR2_EL2		S3_4_C3_C1_1
+#define HFGRTR2_EL2		S3_4_C3_C1_2
+#define HFGWTR2_EL2		S3_4_C3_C1_3
+#define HDFGRTR_EL2		S3_4_C3_C1_4
+#define HDFGWTR_EL2		S3_4_C3_C1_5
+#define HAFGRTR_EL2		S3_4_C3_C1_6
+#define HFGITR2_EL2		S3_4_C3_C1_7
+#define HFGITR_EL2		S3_4_C1_C1_6
+#define HFGRTR_EL2		S3_4_C1_C1_4
+#define HFGWTR_EL2		S3_4_C1_C1_5
+#define ICH_HCR_EL2		S3_4_C12_C11_0
+#define ICH_VMCR_EL2		S3_4_C12_C11_7
+#define VNCR_EL2		S3_4_C2_C2_0
+#define PMSCR_EL2		S3_4_C9_C9_0
+#define TFSR_EL2		S3_4_C5_C6_0
+#define CONTEXTIDR_EL2		S3_4_C13_C0_1
+#define TTBR1_EL2		S3_4_C2_C0_1
+
+/*******************************************************************************
  * Generic timer memory mapped registers & offsets
  ******************************************************************************/
 #define CNTCR_OFF			U(0x000)
@@ -384,6 +406,8 @@
 #define ID_AA64MMFR1_EL1_LO_WIDTH		U(4)
 #define ID_AA64MMFR1_EL1_LOR_NOT_SUPPORTED	ULL(0x0)
 #define ID_AA64MMFR1_EL1_LOR_SUPPORTED		ULL(0x1)
+#define ID_AA64MMFR1_EL1_VHE_SHIFT		ULL(8)
+#define ID_AA64MMFR1_EL1_VHE_MASK		ULL(0xf)
 
 /* ID_AA64MMFR2_EL1 definitions */
 #define ID_AA64MMFR2_EL1		S3_0_C0_C7_2
@@ -394,6 +418,10 @@
 #define ID_AA64MMFR2_EL1_CNP_SHIFT	U(0)
 #define ID_AA64MMFR2_EL1_CNP_MASK	ULL(0xf)
 
+#define ID_AA64MMFR2_EL1_NV_SHIFT	U(24)
+#define ID_AA64MMFR2_EL1_NV_MASK	ULL(0xf)
+#define NV2_IMPLEMENTED			ULL(0x2)
+
 /* ID_AA64MMFR3_EL1 definitions */
 #define ID_AA64MMFR3_EL1			S3_0_C0_C7_3
 
@@ -1482,6 +1510,10 @@
 /*******************************************************************************
  * Permission indirection and overlay Registers
  ******************************************************************************/
+#define PIRE0_EL2		S3_4_C10_C2_2
+#define PIR_EL2			S3_4_C10_C2_3
+#define POR_EL2			S3_4_C10_C2_4
+#define S2PIR_EL2		S3_4_C10_C2_5
 #define PIRE0_EL1		S3_0_C10_C2_2
 #define PIR_EL1			S3_0_C10_C2_3
 #define POR_EL1			S3_0_C10_C2_4
@@ -1490,6 +1522,8 @@
 /*******************************************************************************
  * FEAT_GCS - Guarded Control Stack Registers
  ******************************************************************************/
+#define GCSCR_EL2		S3_4_C2_C5_0
+#define GCSPR_EL2		S3_4_C2_C5_1
 #define GCSCR_EL1		S3_0_C2_C5_0
 #define GCSCRE0_EL1		S3_0_C2_C5_2
 #define GCSPR_EL1		S3_0_C2_C5_1
@@ -1498,6 +1532,7 @@
 /*******************************************************************************
  * Realm management extension register definitions
  ******************************************************************************/
+#define SCXTNUM_EL2		S3_4_C13_C0_7
 #define SCXTNUM_EL1		S3_0_C13_C0_7
 #define SCXTNUM_EL0		S3_3_C13_C0_7
 
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 0290e8f..c7d824a 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -28,6 +28,12 @@
 		(id_aa64mmfr1_pan <= ID_AA64MMFR1_EL1_PAN3_SUPPORTED);
 }
 
+static inline bool is_armv8_1_vhe_present(void)
+{
+	return ((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_VHE_SHIFT) &
+		ID_AA64MMFR1_EL1_VHE_MASK) == 1U;
+}
+
 static inline bool is_armv8_2_pan2_present(void)
 {
 	u_register_t id_aa64mmfr1_pan =
@@ -114,12 +120,24 @@
 		(read_id_aa64isar2_el1() & mask_id_aa64isar2)) != 0U;
 }
 
+static inline bool is_armv8_4_amuv1_present(void)
+{
+	return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
+		ID_AA64PFR0_AMU_MASK) == 1U;
+}
+
 static inline bool is_armv8_4_dit_present(void)
 {
 	return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) &
 		ID_AA64PFR0_DIT_MASK) == 1U;
 }
 
+static inline bool is_armv8_4_nv2_present(void)
+{
+	return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_NV_SHIFT) &
+		ID_AA64MMFR2_EL1_NV_MASK) == NV2_IMPLEMENTED;
+}
+
 static inline bool is_armv8_4_ttst_present(void)
 {
 	return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_ST_SHIFT) &
@@ -486,10 +504,25 @@
 		>= ID_AA64MMFR3_EL1_S1PIE_SUPPORTED;
 }
 
+static inline bool is_feat_s2pie_present(void)
+{
+	return EXTRACT(ID_AA64MMFR3_EL1_S2PIE, read_id_aa64mmfr3_el1())
+		>= ID_AA64MMFR3_EL1_S2PIE_SUPPORTED;
+}
+
+static inline bool is_feat_sxpoe_present(void)
+{
+	return is_feat_s1poe_present() || is_feat_s2poe_present();
+}
+
+static inline bool is_feat_sxpie_present(void)
+{
+	return is_feat_s1pie_present() || is_feat_s2pie_present();
+}
+
 static inline bool is_feat_mte2_present(void)
 {
 	return EXTRACT(ID_AA64PFR1_EL1_MTE, read_id_aa64pfr1_el1())
 		>= MTE_IMPLEMENTED_ELX;
 }
-
 #endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 912b0f6..5cb28cb 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -367,6 +367,7 @@
 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
 
 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2)
 
 DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
 
@@ -512,11 +513,13 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
 
+/* Armv8.4 Memory Partitioning and Monitoring Extension Registers */
 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
 
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0)
 
@@ -585,6 +588,7 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2)
 
 /* Armv8.4 Data Independent Timing */
 DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
@@ -595,6 +599,7 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2,  HFGITR_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2)
 
 /* Armv8.9 Fine Grained Virtualization Traps 2 Registers */
 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr2_el2,  HFGRTR2_EL2)
@@ -629,6 +634,21 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el1, TRFCR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
 
+/* Armv8.4 Enhanced Nested Virtualization */
+DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
+
+/* Armv8.9 Stage 1/2 Permission Overlays */
+DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2)
+
+/* Armv8.9 Stage 1/2 Permission Indirections */
+DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2)
+
+/* Armv9.4 Guarded Control Stack Extension */
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
+
 /* Trace System Registers */
 DEFINE_RENAME_SYSREG_RW_FUNCS(trcauxctlr, TRCAUXCTLR)
 DEFINE_RENAME_SYSREG_RW_FUNCS(trcrsr, TRCRSR)
@@ -678,6 +698,29 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
 
+/* CONTEXTIDR_EL2 */
+DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
+
+/* Reliability, Availability, Serviceability (RAS) */
+DEFINE_SYSREG_RW_FUNCS(vdisr_el2)
+DEFINE_SYSREG_RW_FUNCS(vsesr_el2)
+
+DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2)
+DEFINE_SYSREG_RW_FUNCS(hacr_el2)
+DEFINE_SYSREG_RW_FUNCS(hpfar_el2)
+DEFINE_SYSREG_RW_FUNCS(ich_hcr_el2)
+DEFINE_SYSREG_RW_FUNCS(ich_vmcr_el2)
+DEFINE_SYSREG_RW_FUNCS(tpidr_el2)
+DEFINE_SYSREG_RW_FUNCS(vtcr_el2)
+
+static inline u_register_t read_sp(void)
+{
+	u_register_t v;
+	__asm__ volatile ("mov %0, sp" : "=r" (v));
+
+	return v;
+}
+
 #define IS_IN_EL(x) \
 	(GET_EL(read_CurrentEl()) == MODE_EL##x)