diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h
index 230d69a..53ef4ba 100644
--- a/include/lib/aarch32/arch.h
+++ b/include/lib/aarch32/arch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -440,10 +440,11 @@
 
 /* PMCCFILTR definitions */
 #define PMCCFILTR_EL0_P_BIT		(U(1) << 31)
+#define PMCCFILTR_EL0_U_BIT		(U(1) << 30)
 #define PMCCFILTR_EL0_NSK_BIT		(U(1) << 29)
+#define PMCCFILTR_EL0_NSU_BIT		(U(1) << 28)
 #define PMCCFILTR_EL0_NSH_BIT		(U(1) << 27)
 #define PMCCFILTR_EL0_M_BIT		(U(1) << 26)
-#define PMCCFILTR_EL0_MT_BIT		(U(1) << 25)
 #define PMCCFILTR_EL0_SH_BIT		(U(1) << 24)
 
 /* PMU event counter ID definitions */
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index e48e51c..f43bc8a 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -85,15 +85,21 @@
 #define ICC_CTLR_EL3		S3_6_C12_C12_4
 #define ICC_PMR_EL1		S3_0_C4_C6_0
 #define ICC_RPR_EL1		S3_0_C12_C11_3
-#define ICC_IGRPEN1_EL3		S3_6_c12_c12_7
-#define ICC_IGRPEN0_EL1		S3_0_c12_c12_6
-#define ICC_HPPIR0_EL1		S3_0_c12_c8_2
-#define ICC_HPPIR1_EL1		S3_0_c12_c12_2
-#define ICC_IAR0_EL1		S3_0_c12_c8_0
-#define ICC_IAR1_EL1		S3_0_c12_c12_0
-#define ICC_EOIR0_EL1		S3_0_c12_c8_1
-#define ICC_EOIR1_EL1		S3_0_c12_c12_1
-#define ICC_SGI0R_EL1		S3_0_c12_c11_7
+#define ICC_IGRPEN1_EL3		S3_6_C12_C12_7
+#define ICC_IGRPEN0_EL1		S3_0_C12_C12_6
+#define ICC_HPPIR0_EL1		S3_0_C12_C8_2
+#define ICC_HPPIR1_EL1		S3_0_C12_C12_2
+#define ICC_IAR0_EL1		S3_0_C12_C8_0
+#define ICC_IAR1_EL1		S3_0_C12_C12_0
+#define ICC_EOIR0_EL1		S3_0_C12_C8_1
+#define ICC_EOIR1_EL1		S3_0_C12_C12_1
+#define ICC_SGI0R_EL1		S3_0_C12_C11_7
+
+#define ICV_CTRL_EL1		S3_0_C12_C12_4
+#define ICV_IAR1_EL1		S3_0_C12_C12_0
+#define ICV_IGRPEN1_EL1		S3_0_C12_C12_7
+#define ICV_EOIR1_EL1		S3_0_C12_C12_1
+#define ICV_PMR_EL1		S3_0_C4_C6_0
 
 /*******************************************************************************
  * Generic timer memory mapped registers & offsets
@@ -808,20 +814,30 @@
 
 /* PMEVTYPER<n>_EL0 definitions */
 #define PMEVTYPER_EL0_P_BIT		(U(1) << 31)
+#define PMEVTYPER_EL0_U_BIT		(U(1) << 30)
 #define PMEVTYPER_EL0_NSK_BIT		(U(1) << 29)
+#define PMEVTYPER_EL0_NSU_BIT		(U(1) << 28)
 #define PMEVTYPER_EL0_NSH_BIT		(U(1) << 27)
 #define PMEVTYPER_EL0_M_BIT		(U(1) << 26)
 #define PMEVTYPER_EL0_MT_BIT		(U(1) << 25)
 #define PMEVTYPER_EL0_SH_BIT		(U(1) << 24)
+#define PMEVTYPER_EL0_T_BIT		(U(1) << 23)
+#define PMEVTYPER_EL0_RLK_BIT		(U(1) << 22)
+#define PMEVTYPER_EL0_RLU_BIT		(U(1) << 21)
+#define PMEVTYPER_EL0_RLH_BIT		(U(1) << 20)
 #define PMEVTYPER_EL0_EVTCOUNT_BITS	U(0x0000FFFF)
 
 /* PMCCFILTR_EL0 definitions */
 #define PMCCFILTR_EL0_P_BIT		(U(1) << 31)
+#define PMCCFILTR_EL0_U_BIT		(U(1) << 30)
 #define PMCCFILTR_EL0_NSK_BIT		(U(1) << 29)
 #define PMCCFILTR_EL0_NSH_BIT		(U(1) << 27)
 #define PMCCFILTR_EL0_M_BIT		(U(1) << 26)
-#define PMCCFILTR_EL0_MT_BIT		(U(1) << 25)
 #define PMCCFILTR_EL0_SH_BIT		(U(1) << 24)
+#define PMCCFILTR_EL0_T_BIT		(U(1) << 23)
+#define PMCCFILTR_EL0_RLK_BIT		(U(1) << 22)
+#define PMCCFILTR_EL0_RLU_BIT		(U(1) << 21)
+#define PMCCFILTR_EL0_RLH_BIT		(U(1) << 20)
 
 /* PMSELR_EL0 definitions */
 #define PMSELR_EL0_SEL_SHIFT		U(0)
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index f79174e..7c3ffc5 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -409,16 +409,22 @@
 DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
 DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
 DEFINE_SYSREG_RW_FUNCS(hstr_el2)
-DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
-DEFINE_SYSREG_RW_FUNCS(pmcntenset_el0)
-DEFINE_SYSREG_READ_FUNC(pmccntr_el0)
-DEFINE_SYSREG_RW_FUNCS(pmccfiltr_el0)
 
+DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
+DEFINE_SYSREG_RW_FUNCS(pmcntenclr_el0)
+DEFINE_SYSREG_RW_FUNCS(pmcntenset_el0)
+DEFINE_SYSREG_RW_FUNCS(pmccntr_el0)
+DEFINE_SYSREG_RW_FUNCS(pmccfiltr_el0)
 DEFINE_SYSREG_RW_FUNCS(pmevtyper0_el0)
-DEFINE_SYSREG_READ_FUNC(pmevcntr0_el0)
+DEFINE_SYSREG_RW_FUNCS(pmevcntr0_el0)
+DEFINE_SYSREG_RW_FUNCS(pmovsclr_el0)
+DEFINE_SYSREG_RW_FUNCS(pmovsset_el0)
 DEFINE_SYSREG_RW_FUNCS(pmselr_el0)
+DEFINE_SYSREG_RW_FUNCS(pmuserenr_el0);
 DEFINE_SYSREG_RW_FUNCS(pmxevtyper_el0)
 DEFINE_SYSREG_RW_FUNCS(pmxevcntr_el0)
+DEFINE_SYSREG_RW_FUNCS(pmintenclr_el1)
+DEFINE_SYSREG_RW_FUNCS(pmintenset_el1)
 
 /* parameterised event counter accessors */
 static inline u_register_t read_pmevcntrn_el0(int ctr_num)
@@ -450,7 +456,6 @@
 DEFINE_SYSREG_READ_FUNC(rndrrs)
 
 /* GICv3 System Registers */
-
 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
@@ -468,6 +473,12 @@
 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
 
+DEFINE_RENAME_SYSREG_RW_FUNCS(icv_ctrl_el1, ICV_CTRL_EL1)
+DEFINE_RENAME_SYSREG_READ_FUNC(icv_iar1_el1, ICV_IAR1_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icv_igrpen1_el1, ICV_IGRPEN1_EL1)
+DEFINE_RENAME_SYSREG_WRITE_FUNC(icv_eoir1_el1, ICV_EOIR1_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(icv_pmr_el1, ICV_PMR_EL1)
+
 DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0)
 DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0)
 DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)