feat: add register definitions needed for SMCCC_ARCH_FEATURE_AVAILABILITY
Also slightly optimised some redundant feature functions
Co-developed-by: Charlie Bareham <charlie.bareham@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I6dcc11060a2f3697a8aa41443e9cfc665b2b7c74
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index fe29ee5..6f97bb3 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -212,7 +212,7 @@
#define SKIP_TEST_IF_TRBE_NOT_SUPPORTED() \
do { \
- if (!get_armv9_0_trbe_support()) { \
+ if (!is_feat_trbe_present()) { \
tftf_testcase_printf("ARMv9-TRBE not supported\n"); \
return TEST_RESULT_SKIPPED; \
} \
diff --git a/include/lib/aarch32/arch_features.h b/include/lib/aarch32/arch_features.h
index 3c6a338..999f7ec 100644
--- a/include/lib/aarch32/arch_features.h
+++ b/include/lib/aarch32/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -59,4 +59,11 @@
{
return 0;
}
+
+static inline unsigned int amu_get_version(void)
+{
+ return (unsigned int)(read_id_pfr0() >> ID_PFR0_AMU_SHIFT) &
+ ID_PFR0_AMU_MASK;
+}
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index f0c10ef..62cf470 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -218,6 +218,12 @@
#define ID_AA64PFR0_CSV2_SUPPORTED ULL(0x1)
#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
+/* ID_AA64DFR0_EL1.DoubleLock definitions */
+#define ID_AA64DFR0_DOUBLELOCK_SHIFT U(36)
+#define ID_AA64DFR0_DOUBLELOCK_MASK ULL(0xf)
+#define ID_AA64DFR0_DOUBLELOCK_WIDTH U(4)
+#define DOUBLELOCK_IMPLEMENTED ULL(0)
+
/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
#define ID_AA64DFR0_PMS_SHIFT U(32)
#define ID_AA64DFR0_PMS_LENGTH U(4)
@@ -260,6 +266,7 @@
/* ID_DFR0_EL1.Tracefilt definitions */
#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
+#define ID_AA64DFR0_TRACEFILT_WIDTH U(4)
#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
/* ID_AA64DFR0_EL1.PMUVer definitions */
@@ -611,37 +618,109 @@
/* SCR definitions */
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
-#define SCR_AMVOFFEN_BIT (UL(1) << 35)
-#define SCR_ATA_BIT (U(1) << 26)
-#define SCR_FIEN_BIT (U(1) << 21)
-#define SCR_API_BIT (U(1) << 17)
-#define SCR_APK_BIT (U(1) << 16)
-#define SCR_TWE_BIT (U(1) << 13)
-#define SCR_TWI_BIT (U(1) << 12)
-#define SCR_ST_BIT (U(1) << 11)
-#define SCR_RW_BIT (U(1) << 10)
-#define SCR_SIF_BIT (U(1) << 9)
-#define SCR_HCE_BIT (U(1) << 8)
-#define SCR_SMD_BIT (U(1) << 7)
-#define SCR_EA_BIT (U(1) << 3)
-#define SCR_FIQ_BIT (U(1) << 2)
-#define SCR_IRQ_BIT (U(1) << 1)
-#define SCR_NS_BIT (U(1) << 0)
+#define SCR_NSE_SHIFT U(62)
+#define SCR_FGTEN2_BIT (UL(1) << 59)
+#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
+#define SCR_EnIDCP128_BIT (UL(1) << 55)
+#define SCR_PFAREn_BIT (UL(1) << 53)
+#define SCR_TWERR_BIT (UL(1) << 52)
+#define SCR_TMEA_BIT (UL(1) << 51)
+#define SCR_MECEn_BIT (UL(1) << 49)
+#define SCR_GPF_BIT (UL(1) << 48)
+#define SCR_D128En_BIT (UL(1) << 47)
+#define SCR_AIEn_BIT (UL(1) << 46)
+#define SCR_TWEDEL_SHIFT U(30)
+#define SCR_TWEDEL_MASK ULL(0xf)
+#define SCR_PIEN_BIT (UL(1) << 45)
+#define SCR_SCTLR2En_BIT (UL(1) << 44)
+#define SCR_TCR2EN_BIT (UL(1) << 43)
+#define SCR_RCWMASKEn_BIT (UL(1) << 42)
+#define SCR_ENTP2_SHIFT U(41)
+#define SCR_TRNDR_BIT (UL(1) << 40)
+#define SCR_GCSEn_BIT (UL(1) << 39)
+#define SCR_HXEn_BIT (UL(1) << 38)
+#define SCR_ADEn_BIT (UL(1) << 37)
+#define SCR_EnAS0_BIT (UL(1) << 36)
+#define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT)
+#define SCR_AMVOFFEN_SHIFT U(35)
+#define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT)
+#define SCR_TME_BIT (UL(1) << 34)
+#define SCR_TWEDEn_BIT (UL(1) << 29)
+#define SCR_ECVEN_BIT (UL(1) << 28)
+#define SCR_FGTEN_BIT (UL(1) << 27)
+#define SCR_ATA_BIT (UL(1) << 26)
+#define SCR_EnSCXT_BIT (UL(1) << 25)
+#define SCR_FIEN_BIT (UL(1) << 21)
+#define SCR_NMEA_BIT (UL(1) << 20)
+#define SCR_EASE_BIT (UL(1) << 19)
+#define SCR_EEL2_BIT (UL(1) << 18)
+#define SCR_API_BIT (UL(1) << 17)
+#define SCR_APK_BIT (UL(1) << 16)
+#define SCR_TERR_BIT (UL(1) << 15)
+#define SCR_TLOR_BIT (UL(1) << 14)
+#define SCR_TWE_BIT (UL(1) << 13)
+#define SCR_TWI_BIT (UL(1) << 12)
+#define SCR_ST_BIT (UL(1) << 11)
+#define SCR_RW_BIT (UL(1) << 10)
+#define SCR_SIF_BIT (UL(1) << 9)
+#define SCR_HCE_BIT (UL(1) << 8)
+#define SCR_SMD_BIT (UL(1) << 7)
+#define SCR_EA_BIT (UL(1) << 3)
+#define SCR_FIQ_BIT (UL(1) << 2)
+#define SCR_IRQ_BIT (UL(1) << 1)
+#define SCR_NS_BIT (UL(1) << 0)
+#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
#define SCR_VALID_BIT_MASK U(0x2f8f)
#define SCR_RESET_VAL SCR_RES1_BITS
/* MDCR_EL3 definitions */
+#define MDCR_EnSTEPOP_BIT (ULL(1) << 50)
+#define MDCR_ETBAD(x) ((x) << 48)
+#define MDCR_EnITE_BIT (ULL(1) << 47)
+#define MDCR_EPMSSAD(x) (ULL(x) << 45)
+#define MDCR_EnPMSS_BIT (ULL(1) << 44)
+#define MDCR_EBWE_BIT (ULL(1) << 43)
+#define MDCR_EnPMS3_BIT (ULL(1) << 42)
+#define MDCR_PMEE(x) ((x) << 40)
+#define MDCR_EnTB2_BIT (ULL(1) << 39)
+#define MDCR_E3BREC_BIT (ULL(1) << 38)
+#define MDCR_E3BREW_BIT (ULL(1) << 37)
+#define MDCR_EnPMSN_BIT (ULL(1) << 36)
+#define MDCR_MPMX_BIT (ULL(1) << 35)
+#define MDCR_MCCD_BIT (ULL(1) << 34)
+#define MDCR_SBRBE_SHIFT U(32)
+#define MDCR_SBRBE_MASK ULL(0x3)
+#define MDCR_SBRBE(x) (ULL(x) << MDCR_SBRBE_SHIFT)
+#define MDCR_PMSSE(x) ((x) << 30)
+#define MDCR_NSTBE_BIT (ULL(1) << 26)
+#define MDCR_NSTB(x) ((x) << 24)
+#define MDCR_NSTB_EL1 ULL(0x3)
+#define MDCR_NSTBE_BIT (ULL(1) << 26)
+#define MDCR_MTPME_BIT (ULL(1) << 28)
+#define MDCR_TDCC_BIT (ULL(1) << 27)
+#define MDCR_SCCD_BIT (ULL(1) << 23)
+#define MDCR_ETAD_BIT (ULL(1) << 22)
+#define MDCR_EPMAD_BIT (ULL(1) << 21)
+#define MDCR_EDAD_BIT (ULL(1) << 20)
+#define MDCR_TTRF_BIT (ULL(1) << 19)
+#define MDCR_STE_BIT (ULL(1) << 18)
+#define MDCR_SPME_BIT (ULL(1) << 17)
+#define MDCR_SDD_BIT (ULL(1) << 16)
#define MDCR_SPD32(x) ((x) << 14)
#define MDCR_SPD32_LEGACY ULL(0x0)
#define MDCR_SPD32_DISABLE ULL(0x2)
#define MDCR_SPD32_ENABLE ULL(0x3)
-#define MDCR_SDD_BIT (ULL(1) << 16)
#define MDCR_NSPB(x) ((x) << 12)
#define MDCR_NSPB_EL1 ULL(0x3)
+#define MDCR_NSPBE_BIT (ULL(1) << 11)
#define MDCR_TDOSA_BIT (ULL(1) << 10)
#define MDCR_TDA_BIT (ULL(1) << 9)
+#define MDCR_EnPM2_BIT (ULL(1) << 7)
#define MDCR_TPM_BIT (ULL(1) << 6)
-#define MDCR_SCCD_BIT (ULL(1) << 23)
+#define MDCR_EDADE_BIT (ULL(1) << 4)
+#define MDCR_ETADE_BIT (ULL(1) << 3)
+#define MDCR_EPMADE_BIT (ULL(1) << 2)
+#define MDCR_RLTE_BIT (ULL(1) << 0)
#define MDCR_EL3_RESET_VAL ULL(0x0)
/* MDCR_EL2 definitions */
@@ -707,6 +786,14 @@
#define EVNTI_SHIFT U(4)
#define EVNTI_MASK U(0xf)
+/* CPTR_EL3 definitions */
+#define CPTR_EL3_TCPAC_BIT (ULL(1) << 31)
+#define CPTR_EL3_TAM_BIT (ULL(1) << 30)
+#define CPTR_EL3_TTA_BIT (ULL(1) << 20)
+#define CPTR_EL3_ESM_BIT (ULL(1) << 12)
+#define CPTR_EL3_TFP_BIT (ULL(1) << 10)
+#define CPTR_EL3_EZ_BIT (ULL(1) << 8)
+
/* CPTR_EL2 definitions */
#define CPTR_EL2_RES1 ((ULL(1) << 13) | (ULL(1) << 9) | (ULL(0xff)))
#define CPTR_EL2_TCPAC_BIT (ULL(1) << 31)
@@ -1285,6 +1372,7 @@
/* MPAM register definitions */
#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
+#define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62)
#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 27f5c82..f7b3632 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -120,12 +120,6 @@
(read_id_aa64isar2_el1() & mask_id_aa64isar2)) != 0U;
}
-static inline bool is_armv8_4_amuv1_present(void)
-{
- return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
- ID_AA64PFR0_AMU_MASK) == 1U;
-}
-
static inline bool is_armv8_4_dit_present(void)
{
return ((read_id_aa64pfr0_el1() >> ID_AA64PFR0_DIT_SHIFT) &
@@ -186,13 +180,6 @@
ID_AA64DFR0_DEBUG_SHIFT);
}
-static inline bool get_armv9_0_trbe_support(void)
-{
- return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEBUFFER_SHIFT) &
- ID_AA64DFR0_TRACEBUFFER_MASK) ==
- ID_AA64DFR0_TRACEBUFFER_SUPPORTED;
-}
-
static inline bool get_armv8_4_trf_support(void)
{
return ((read_id_aa64dfr0_el1() >> ID_AA64DFR0_TRACEFILT_SHIFT) &
@@ -474,6 +461,22 @@
ID_AA64ISAR1_LS64_MASK);
}
+static inline unsigned int amu_get_version(void)
+{
+ return (unsigned int)(read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
+ ID_AA64PFR0_AMU_MASK;
+}
+
+static inline bool is_feat_amuv1_present(void)
+{
+ return amu_get_version() >= ID_AA64PFR0_AMU_V1;
+}
+
+static inline bool is_feat_amuv1p1_present(void)
+{
+ return amu_get_version() >= ID_AA64PFR0_AMU_V1P1;
+}
+
static inline bool is_feat_trbe_present(void)
{
return EXTRACT(ID_AA64DFR0_TRACEBUFFER, read_id_aa64dfr0_el1())
@@ -555,4 +558,10 @@
return (((read_id_aa64mmfr3_el1() >> ID_AA64MMFR3_EL1_D128_SHIFT) &
ID_AA64MMFR3_EL1_D128_MASK) == ID_AA64MMFR3_EL1_D128_SUPPORTED);
}
+
+static inline bool is_feat_doublelock_present(void)
+{
+ return EXTRACT(ID_AA64DFR0_DOUBLELOCK, read_id_aa64dfr0_el1())
+ >= DOUBLELOCK_IMPLEMENTED;
+}
#endif /* ARCH_FEATURES_H */
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h
index 3ce053d..838e4b9 100644
--- a/include/lib/extensions/amu.h
+++ b/include/lib/extensions/amu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -61,8 +61,6 @@
CASSERT(AMU_GROUP1_COUNTERS_MASK <= 0xffff, invalid_amu_group1_counters_mask);
-unsigned int amu_get_version(void);
-
uint64_t amu_group0_cnt_read(unsigned int idx);
#if __aarch64__
uint64_t amu_group0_voffset_read(unsigned int idx);