commit 589a112c6d96697529eb96cc3452c1a6d3d5af5a
author Manish V Badarkhe <Manish.Badarkhe@arm.com> Fri Dec 31 15:20:08 2021 +0000
committer Manish V Badarkhe <Manish.Badarkhe@arm.com> Thu Jan 27 21:09:57 2022 +0000
tree 66d2ed27cc0e5e451f1d526faa84e0862a15c18b
parent a7ccb402229b3b9419ec17f311576ffdf1e037b7

feat(spe): add simple SPE test

Added simple SPE test that reads static profiling system registers
of available SPE version i.e. FEAT_SPE/FEAT_SPEv1p1/FEAT_SPEv1p2

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I6fe02914b0ad5e8b702654dab27aee449b3b7b9f

include/lib/aarch64/arch.h

diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index d9bc33c..75fdfcf 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -866,7 +866,18 @@
 /*******************************************************************************
  * Definitions for system register interface to SPE
  ******************************************************************************/
+#define PMSCR_EL1		S3_0_C9_C9_0
+#define PMSNEVFR_EL1		S3_0_C9_C9_1
+#define PMSICR_EL1		S3_0_C9_C9_2
+#define PMSIRR_EL1		S3_0_C9_C9_3
+#define PMSFCR_EL1		S3_0_C9_C9_4
+#define PMSEVFR_EL1		S3_0_C9_C9_5
+#define PMSLATFR_EL1		S3_0_C9_C9_6
+#define PMSIDR_EL1		S3_0_C9_C9_7
 #define PMBLIMITR_EL1		S3_0_C9_C10_0
+#define PMBPTR_EL1		S3_0_C9_C10_1
+#define PMBSR_EL1		S3_0_C9_C10_3
+#define PMSCR_EL2		S3_4_C9_C9_0
 
 /*******************************************************************************
  * Definitions for system register interface to MPAM

include/lib/aarch64/arch_helpers.h

diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 05f6779..f42f2f8 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -439,7 +439,19 @@
 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
 
+/* Static profiling control registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmscr_el1, PMSCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmsevfr_el1, PMSEVFR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmsfcr_el1, PMSFCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmsicr_el1, PMSICR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmsidr_el1, PMSIDR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmsirr_el1, PMSIRR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmslatfr_el1, PMSLATFR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmsnevfr_el1, PMSNEVFR_EL1)
 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmbptr_el1, PMBPTR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmbsr_el1, PMBSR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pmscr_el2, PMSCR_EL2)
 
 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)