diff --git a/tftf/tests/extensions/spe/test_spe.c b/tftf/tests/extensions/spe/test_spe.c
new file mode 100644
index 0000000..8b18654
--- /dev/null
+++ b/tftf/tests/extensions/spe/test_spe.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <test_helpers.h>
+
+#ifdef __aarch64__
+/*
+ * Get SPE version value from id_aa64dfr0_el1.
+ * Return values
+ *   ID_AA64DFR0_SPE_NOT_SUPPORTED: not supported
+ *   ID_AA64DFR0_SPE: FEAT_SPE supported (introduced in ARM v8.2)
+ *   ID_AA64DFR0_SPE_V1P1: FEAT_SPEv1p1 supported (introduced in ARM v8.5)
+ *   ID_AA64DFR0_SPE_V1P2: FEAT_SPEv1p2 supported (introduced in ARM v8.7)
+ */
+
+typedef enum {
+	ID_AA64DFR0_SPE_NOT_SUPPORTED = 0,
+	ID_AA64DFR0_SPE,
+	ID_AA64DFR0_SPE_V1P1,
+	ID_AA64DFR0_SPE_V1P2
+} spe_ver_t;
+
+static spe_ver_t spe_get_version(void)
+{
+	return (spe_ver_t)((read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT) &
+		ID_AA64DFR0_PMS_MASK);
+}
+#endif /* __aarch64__ */
+
+test_result_t test_spe_support(void)
+{
+	/* SPE is an AArch64-only feature.*/
+	SKIP_TEST_IF_AARCH32();
+
+#ifdef __aarch64__
+	spe_ver_t spe_ver = spe_get_version();
+
+	assert(spe_ver <= ID_AA64DFR0_SPE_V1P2);
+
+	if (spe_ver == ID_AA64DFR0_SPE_NOT_SUPPORTED) {
+		return TEST_RESULT_SKIPPED;
+	}
+
+	/*
+	 * If runtime-EL3 does not enable access to SPE system
+	 * registers from NS-EL2/NS-EL1 then read of these
+	 * registers traps in EL3
+	 */
+	read_pmscr_el1();
+	read_pmsfcr_el1();
+	read_pmsicr_el1();
+	read_pmsidr_el1();
+	read_pmsirr_el1();
+	read_pmslatfr_el1();
+	read_pmblimitr_el1();
+	read_pmbptr_el1();
+	read_pmbsr_el1();
+	read_pmsevfr_el1();
+	if (IS_IN_EL2()) {
+		read_pmscr_el2();
+	}
+	if (spe_ver == ID_AA64DFR0_SPE_V1P2) {
+		read_pmsnevfr_el1();
+	}
+
+	return TEST_RESULT_SUCCESS;
+#endif /* __aarch64__ */
+}
diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk
index 6563b2a..5845212 100644
--- a/tftf/tests/tests-cpu-extensions.mk
+++ b/tftf/tests/tests-cpu-extensions.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2022, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -11,6 +11,8 @@
 	extensions/mte/test_mte.c					\
 	extensions/pauth/test_pauth.c					\
 	extensions/sve/sve_operations.S					\
+	extensions/sme/test_sme.c					\
+	extensions/spe/test_spe.c                                       \
 	extensions/sve/test_sve.c					\
 	extensions/sys_reg_trace/test_sys_reg_trace.c			\
 	extensions/trbe/test_trbe.c					\
@@ -18,5 +20,4 @@
 	runtime_services/arm_arch_svc/smccc_arch_soc_id.c		\
 	runtime_services/arm_arch_svc/smccc_arch_workaround_1.c		\
 	runtime_services/arm_arch_svc/smccc_arch_workaround_2.c		\
-	extensions/sme/test_sme.c					\
 )
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index 990ab9f..3d18f84 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="utf-8"?>
 
 <!--
-  Copyright (c) 2018-2021, Arm Limited. All rights reserved.
+  Copyright (c) 2018-2022, Arm Limited. All rights reserved.
 
   SPDX-License-Identifier: BSD-3-Clause
 -->
@@ -24,6 +24,7 @@
     <testcase name="Use trace filter control Registers" function="test_trf_enabled" />
     <testcase name="Use trace system Registers" function="test_sys_reg_trace_enabled" />
     <testcase name="SME support" function="test_sme_support" />
+    <testcase name="SPE support" function="test_spe_support" />
   </testsuite>
 
   <testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">