diff --git a/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.c b/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.c
new file mode 100644
index 0000000..6c28c87
--- /dev/null
+++ b/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <test_helpers.h>
+#include <tftf_lib.h>
+#include <tftf.h>
+
+#include "./test_sys_reg_trace.h"
+
+static uint32_t get_trace_arch_ver(void)
+{
+	uint32_t val = read_trcdevarch();
+	val = (val >> TRCDEVARCH_ARCHVER_SHIFT) & TRCDEVARCH_ARCHVER_MASK;
+
+	return val;
+}
+
+/*
+ * EL3 is expected to allow access to trace system registers from EL2.
+ * Reading these register will trap to EL3 and crash when EL3 has not
+ * allowed access.
+ */
+test_result_t test_sys_reg_trace_enabled(void)
+{
+	SKIP_TEST_IF_SYS_REG_TRACE_NOT_SUPPORTED();
+
+	/*
+	 * Read few ETMv4 system trace registers to verify correct access
+	 * been provided from EL3.
+	 */
+	uint32_t trace_arch_ver __unused = get_trace_arch_ver();
+	read_trcauxctlr();
+	read_trcccctlr();
+	read_trcbbctlr();
+	read_trcclaimset();
+	read_trcclaimclr();
+
+	/*
+	 * Read few ETE system trace registers to verify correct access
+	 * been provided from EL3. ETE system trace register access are
+	 * not possible from NS-EL2 in aarch32 state.
+	 */
+#if __aarch64__
+	if (trace_arch_ver == TRCDEVARCH_ARCHVER_ETE) {
+		read_trcrsr();
+		read_trcextinselr0();
+		read_trcextinselr1();
+		read_trcextinselr2();
+		read_trcextinselr3();
+	}
+#endif /* __aarch64__ */
+
+	return TEST_RESULT_SUCCESS;
+}
diff --git a/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.h b/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.h
new file mode 100644
index 0000000..640b82c
--- /dev/null
+++ b/tftf/tests/extensions/sys_reg_trace/test_sys_reg_trace.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TEST_SYS_REG_TRACE_H
+#define TEST_SYS_REG_TRACE_H
+
+/* TRCEDEVARCH definitions */
+#define TRCDEVARCH_ARCHVER_SHIFT	U(12)
+#define TRCDEVARCH_ARCHVER_MASK		U(0xf)
+#define TRCDEVARCH_ARCHVER_ETE		U(0x5)
+
+#endif /* TEST_SYS_REG_TRACE_H */
diff --git a/tftf/tests/tests-cpu-extensions.mk b/tftf/tests/tests-cpu-extensions.mk
index e5f4f79..5ceb340 100644
--- a/tftf/tests/tests-cpu-extensions.mk
+++ b/tftf/tests/tests-cpu-extensions.mk
@@ -12,6 +12,7 @@
 	extensions/pauth/test_pauth.c					\
 	extensions/sve/sve_operations.S					\
 	extensions/sve/test_sve.c					\
+	extensions/sys_reg_trace/test_sys_reg_trace.c			\
 	extensions/trbe/test_trbe.c					\
 	extensions/trf/test_trf.c					\
 	runtime_services/arm_arch_svc/smccc_arch_soc_id.c		\
diff --git a/tftf/tests/tests-cpu-extensions.xml b/tftf/tests/tests-cpu-extensions.xml
index a0d2c9a..a1e3f8f 100644
--- a/tftf/tests/tests-cpu-extensions.xml
+++ b/tftf/tests/tests-cpu-extensions.xml
@@ -22,6 +22,7 @@
     <testcase name="Use ECV Registers" function="test_ecv_enabled" />
     <testcase name="Use trace buffer control Registers" function="test_trbe_enabled" />
     <testcase name="Use trace filter control Registers" function="test_trf_enabled" />
+    <testcase name="Use trace system Registers" function="test_sys_reg_trace_enabled" />
   </testsuite>
 
   <testsuite name="ARM_ARCH_SVC" description="Arm Architecture Service tests">