feat(ls64): add LS64_ACCDATA test

FEAT_LS64_ACCDATA introduces the system register ACCDATA_EL1, its value
replacing the first four bytes of the data provided to an ST64BV0
instruction. As this system register would need context switching
between non-secure and secure worlds, there is an SCR_EL3 bit to allow
trapping accesses from lower ELs into EL3.

Introduce a check to verify that accesses to this system register do not
trap into EL3, if the CPUID registers advertise this feature.
Bits[63:32] of ACCDATA_EL1 are described as RES0, so mask those bits
when comparing the read-back values with the written one.

Change-Id: Ia32bcf7187356c701470a1757708b3d554e88629
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index d6a7ade..28b1d4e 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -355,6 +355,15 @@
 		}								\
 	} while (false)
 
+#define SKIP_TEST_IF_LS64_ACCDATA_NOT_SUPPORTED()			\
+	do {								\
+		if (get_feat_ls64_support() <				\
+		    ID_AA64ISAR1_LS64_ACCDATA_SUPPORTED) {		\
+			tftf_testcase_printf("ARMv8.7-ls64-accdata not supported");	\
+			return TEST_RESULT_SKIPPED;			\
+		}							\
+	} while (false)
+
 /* Helper macro to verify if system suspend API is supported */
 #define is_psci_sys_susp_supported()	\
 		(tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND)		\
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index a1dca21..a641052 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -1323,6 +1323,11 @@
  ******************************************************************************/
 #define CNTPOFF_EL2  S3_4_C14_C0_6
 
+/*******************************************************************************
+ * Armv8.7 - LoadStore64Bytes Registers
+ ******************************************************************************/
+#define SYS_ACCDATA_EL1		S3_0_C13_C0_5
+
 /******************************************************************************
  * Armv8.9 - Breakpoint and Watchpoint Selection Register
  ******************************************************************************/
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 455ae27..744bbe6 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -230,6 +230,8 @@
 DEFINE_SYSOP_PARAM_FUNC(wfit)
 DEFINE_SYSOP_PARAM_FUNC(wfet)
 
+DEFINE_RENAME_SYSREG_RW_FUNCS(sys_accdata_el1, SYS_ACCDATA_EL1)
+
 static inline void enable_irq(void)
 {
 	/*