Merge "fix(printf): increase TESTCASE_OUTPUT_MAX_SIZE"
diff --git a/docs/index.rst b/docs/index.rst
index 4869af1..7e54db2 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -12,6 +12,7 @@
design
implementing-tests
porting/index
+ plat/index
change-log
license
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
new file mode 100644
index 0000000..33c0ab9
--- /dev/null
+++ b/docs/plat/index.rst
@@ -0,0 +1,18 @@
+Platform Ports
+==============
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :hidden:
+
+ xilinx-versal_net
+ xilinx-versal
+ xilinx-zynqmp
+
+This section provides a list of supported upstream *platform ports* and the
+documentation associated with them.
+
+--------------
+
+*Copyright (c) 2024, Arm Limited. All rights reserved.*
diff --git a/docs/plat/xilinx-zynqmp.rst b/docs/plat/xilinx-zynqmp.rst
new file mode 100644
index 0000000..bac6728
--- /dev/null
+++ b/docs/plat/xilinx-zynqmp.rst
@@ -0,0 +1,45 @@
+..
+ Copyright (c) 2024, Advanced Micro Devices, Inc. All rights reserved. !
+ SPDX-License-Identifier: BSD-3-Clause !
+
+Xilinx ZynqMP
+=============
+
+- The TF-A Tests on Xilinx ZynqMP platform runs from DDR.
+- Logs are available only on console and not saved in memory(No NVM support).
+- ZynqMP Platform uses TTC Timer
+
+Build Command
+-------------
+For individual tests/test suite:
+
+.. code-block:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp TESTS=<required tests> tftf
+
+For Versal NET Specific tests (includes AMD-Xilinx Tests cases + Standard Test Suite)
+
+.. code-block:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp TESTS=versal tftf
+
+Execution on Target
+-------------------
+
+- The TF-A Tests uses the memory location of U-boot.
+- To package the tftf.elf in BOOT.BIN, the u-boot entry in bootgen.bif needs to be replaced with following
+
+.. code-block:: shell
+
+ the_ROM_image:
+ {
+ [bootloader, destination_cpu=a53-0] zynqmp_fsbl.elf
+ [pmufw_image] pmufw.elf
+ [destination_device=pl] pre-built/linux/implementation/download.bit
+ [destination_cpu=a53-0, exception_level=el-3, trustzone] bl31.elf
+ [destination_cpu=a53-0, load=0x00100000] system.dtb
+ [destination_cpu=a53-0, exception_level=el-2] tftf.elf
+ }
+
+- The BOOT.BIN with TF-A Tests can now be used to run on the target.
+- The TF-A Tests will be executed after TF-A and the tests report will be available on the console.
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
new file mode 100644
index 0000000..c88990e
--- /dev/null
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+#include <drivers/console.h>
+#include <drivers/cadence/cdns_uart.h>
+#include <platform_def.h>
+
+ /*
+ * "core" functions are low-level implementations that don't require
+ * writable memory and are thus safe to call in BL1 crash context.
+ */
+ .globl console_core_init
+ .globl console_core_putc
+ .globl console_core_getc
+ .globl console_core_flush
+
+ .globl console_init
+ .globl console_putc
+ .globl console_getc
+ .globl console_flush
+
+ /*
+ * The console base is in the data section and not in .bss
+ * even though it is zero-init. In particular, this allows
+ * the console functions to start using this variable before
+ * the runtime memory is initialized for images which do not
+ * need to copy the .data section from ROM to RAM.
+ */
+ .section .data.console_base
+ .align 3
+console_base: .quad 0x0
+
+
+func console_init
+ adrp x3, console_base
+ str x0, [x3, :lo12:console_base]
+ b console_core_init
+endfunc console_init
+
+ /* -----------------------------------------------
+ * int console_core_init(uintptr_t base_addr)
+ * Function to initialize the console without a
+ * C Runtime to print debug information. This
+ * function will be accessed by console_init and
+ * crash reporting.
+ * We assume that the bootloader already set up
+ * the HW (baud, ...) and only enable the trans-
+ * mitter and receiver here.
+ * In: x0 - console base address
+ * Out: return 1 on success else 0 on error
+ * Clobber list : x1, x2, x3
+ * -----------------------------------------------
+ */
+func console_core_init
+ /* Check the input base address */
+ cbz x0, core_init_fail
+
+ /* RX/TX enabled & reset */
+ mov w3, #(R_UART_CR_TX_EN | R_UART_CR_RX_EN | R_UART_CR_TXRST | R_UART_CR_RXRST)
+ str w3, [x0, #R_UART_CR]
+
+ mov w0, #1
+ ret
+core_init_fail:
+ mov w0, wzr
+ ret
+endfunc console_core_init
+
+
+ /* --------------------------------------------------------
+ * int console_cdns_core_putc(int c, uintptr_t base_addr)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : w0 - character to be printed
+ * x1 - console base address
+ * Out : return -1 on error else return character.
+ * Clobber list : x2
+ * --------------------------------------------------------
+ */
+func console_core_putc
+ cbz x1, putc_error
+ /* Prepend '\r' to '\n' */
+ cmp w0, #0xA
+ b.ne 2f
+1:
+ /* Check if the transmit FIFO is empty */
+ ldr w2, [x1, #R_UART_SR]
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, 1b
+ mov w2, #0xD
+ str w2, [x1, #R_UART_TX]
+2:
+ /* Check if the transmit FIFO is empty */
+ ldr w2, [x1, #R_UART_SR]
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, 2b
+ str w0, [x1, #R_UART_TX]
+ ret
+putc_error:
+ mov w0, #ERROR_NO_VALID_CONSOLE
+ ret
+endfunc console_core_putc
+
+ /* --------------------------------------------------------
+ * int console_cdns_putc(int c, console_t *cdns)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : w0 - character to be printed
+ * x1 - pointer to console_t structure
+ * Out : return -1 on error else return character.
+ * Clobber list : x2
+ * --------------------------------------------------------
+ */
+func console_putc
+ adrp x1, console_base
+ ldr x1, [x1, :lo12:console_base]
+ b console_core_putc
+endfunc console_putc
+
+ /* ---------------------------------------------
+ * int console_cdns_core_getc(uintptr_t base_addr)
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 if no character is available.
+ * In : x0 - console base address
+ * Out: w0 - character if available, else -1
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_core_getc
+ adr x0, console_base
+ ldr x0, [x0]
+
+ /* Check if the receive FIFO is empty */
+ ldr w1, [x0, #R_UART_SR]
+ tbnz w1, #UART_SR_INTR_REMPTY_BIT, no_char
+ ldr w1, [x0, #R_UART_RX]
+ mov w0, w1
+ ret
+no_char:
+ mov w0, #ERROR_NO_PENDING_CHAR
+ ret
+endfunc console_core_getc
+
+ /* ---------------------------------------------
+ * int console_cdns_getc(console_t *console)
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 if no character is available.
+ * In : x0 - pointer to console_t structure
+ * Out: w0 - character if available, else -1
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_getc
+ adrp x0, console_base
+ ldr x0, [x0, :lo12:console_base]
+ b console_core_getc
+endfunc console_getc
+
+ /* ---------------------------------------------
+ * int console_cdns_core_flush(uintptr_t base_addr)
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : x0 - console base address
+ * Out : void
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_core_flush
+ cbz x0, flush_error
+ /* Loop until the transmit FIFO is empty */
+1:
+ ldr w2, [x1, #R_UART_SR]
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, 1b
+ str w0, [x1, #R_UART_TX]
+ ret
+flush_error:
+ mov w0, #ERROR_NO_VALID_CONSOLE
+ ret
+endfunc console_core_flush
+
+ /* ---------------------------------------------
+ * void console_cdns_flush(console_t *console)
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : x0 - pointer to console_t structure
+ * Out : void.
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_flush
+ adrp x0, console_base
+ ldr x0, [x0, :lo12:console_base]
+ b console_core_flush
+endfunc console_flush
diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h
new file mode 100644
index 0000000..87e98ea
--- /dev/null
+++ b/include/drivers/cadence/cdns_uart.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CDNS_UART_H
+#define CDNS_UART_H
+
+#include <drivers/console.h>
+#include <lib/utils_def.h>
+/* This is very minimalistic and will only work in QEMU. */
+
+/* CADENCE Registers */
+#define R_UART_CR 0
+#define R_UART_CR_RXRST (1 << 0) /* RX logic reset */
+#define R_UART_CR_TXRST (1 << 1) /* TX logic reset */
+#define R_UART_CR_RX_EN (1 << 2) /* RX enabled */
+#define R_UART_CR_TX_EN (1 << 4) /* TX enabled */
+
+#define R_UART_SR 0x2C
+#define UART_SR_INTR_REMPTY_BIT 1
+#define UART_SR_INTR_TFUL_BIT 4
+#define UART_SR_INTR_TEMPTY_BIT 3
+
+#define R_UART_TX 0x30
+#define R_UART_RX 0x30
+
+#define CONSOLE_T_BASE (U(5) * REGSZ)
+
+#endif /* CDNS_UART_H */
diff --git a/include/lib/extensions/pauth.h b/include/lib/extensions/pauth.h
index c8d577f..8816e18 100644
--- a/include/lib/extensions/pauth.h
+++ b/include/lib/extensions/pauth.h
@@ -11,6 +11,11 @@
#include <stdint.h>
#ifdef __aarch64__
+/* Number of ARMv8.3-PAuth keys */
+#define NUM_KEYS 5U
+
+static const char * const key_name[] = {"IA", "IB", "DA", "DB", "GA"};
+
/* Initialize 128-bit ARMv8.3-PAuth key */
uint128_t init_apkey(void);
@@ -24,13 +29,13 @@
* Fill Pauth Keys and template with random values if keys werenot initialized earlier,
* Else Copy PAuth key registers to template.
*/
-void pauth_test_lib_fill_regs_and_template(void);
+void pauth_test_lib_fill_regs_and_template(uint128_t *pauth_keys_arr);
/* Read and Compare PAuth registers with provided template values. */
-bool pauth_test_lib_compare_template(void);
+bool pauth_test_lib_compare_template(uint128_t *pauth_keys_before, uint128_t *pauth_keys_after);
/* Read and Store PAuth registers in template. */
-void pauth_test_lib_read_keys(void);
+void pauth_test_lib_read_keys(uint128_t *pauth_keys_arr);
/* Test PAuth instructions. */
void pauth_test_lib_test_intrs(void);
diff --git a/include/runtime_services/errata_abi.h b/include/runtime_services/errata_abi.h
index 363564e..dc50113 100644
--- a/include/runtime_services/errata_abi.h
+++ b/include/runtime_services/errata_abi.h
@@ -37,7 +37,7 @@
*/
#define TOTAL_ABI_CALLS (3U)
-#define ERRATA_COUNT (17U)
+#define ERRATA_COUNT (32U)
typedef struct {
uint32_t id;
diff --git a/include/runtime_services/host_realm_managment/host_shared_data.h b/include/runtime_services/host_realm_managment/host_shared_data.h
index fc0b030..632fdaa 100644
--- a/include/runtime_services/host_realm_managment/host_shared_data.h
+++ b/include/runtime_services/host_realm_managment/host_shared_data.h
@@ -67,6 +67,7 @@
REALM_PAUTH_SET_CMD,
REALM_PAUTH_CHECK_CMD,
REALM_PAUTH_FAULT,
+ REALM_DIT_CHECK_CMD,
REALM_SME_ID_REGISTERS,
REALM_SME_UNDEF_ABORT
};
diff --git a/lib/extensions/pauth/aarch64/pauth.c b/lib/extensions/pauth/aarch64/pauth.c
index 90e16d5..9608b97 100644
--- a/lib/extensions/pauth/aarch64/pauth.c
+++ b/lib/extensions/pauth/aarch64/pauth.c
@@ -11,14 +11,6 @@
#include <debug.h>
#include <pauth.h>
-/* Number of ARMv8.3-PAuth keys */
-#define NUM_KEYS 5U
-
-static const char * const key_name[] = {"IA", "IB", "DA", "DB", "GA"};
-
-static uint128_t pauth_keys_before[NUM_KEYS];
-static uint128_t pauth_keys_after[NUM_KEYS];
-
/*
* This is only a toy implementation to generate a seemingly random
* 128-bit key from sp, x30 and cntpct_el0 values.
@@ -49,11 +41,11 @@
return false;
}
-bool pauth_test_lib_compare_template(void)
+bool pauth_test_lib_compare_template(uint128_t *pauth_keys_before, uint128_t *pauth_keys_after)
{
bool result = true;
- pauth_test_lib_read_keys();
+ pauth_test_lib_read_keys(pauth_keys_after);
for (unsigned int i = 0U; i < NUM_KEYS; ++i) {
if (pauth_keys_before[i] != pauth_keys_after[i]) {
ERROR("AP%sKey_EL1 read 0x%llx:%llx "
@@ -73,7 +65,7 @@
* Program or read ARMv8.3-PAuth keys (if already enabled)
* and store them in <pauth_keys_before> buffer
*/
-void pauth_test_lib_fill_regs_and_template(void)
+void pauth_test_lib_fill_regs_and_template(uint128_t *pauth_keys_before)
{
uint128_t plat_key;
@@ -146,30 +138,30 @@
/*
* Read ARMv8.3-PAuth keys and store them in
- * <pauth_keys_after> buffer
+ * <pauth_keys_arr> buffer
*/
-void pauth_test_lib_read_keys(void)
+void pauth_test_lib_read_keys(uint128_t *pauth_keys_arr)
{
- (void)memset(pauth_keys_after, 0, NUM_KEYS * sizeof(uint128_t));
+ (void)memset(pauth_keys_arr, 0, NUM_KEYS * sizeof(uint128_t));
/* Read APIAKey_EL1 */
- pauth_keys_after[0] = read_apiakeylo_el1() |
+ pauth_keys_arr[0] = read_apiakeylo_el1() |
((uint128_t)(read_apiakeyhi_el1()) << 64U);
/* Read APIBKey_EL1 */
- pauth_keys_after[1] = read_apibkeylo_el1() |
+ pauth_keys_arr[1] = read_apibkeylo_el1() |
((uint128_t)(read_apibkeyhi_el1()) << 64U);
/* Read APDAKey_EL1 */
- pauth_keys_after[2] = read_apdakeylo_el1() |
+ pauth_keys_arr[2] = read_apdakeylo_el1() |
((uint128_t)(read_apdakeyhi_el1()) << 64U);
/* Read APDBKey_EL1 */
- pauth_keys_after[3] = read_apdbkeylo_el1() |
+ pauth_keys_arr[3] = read_apdbkeylo_el1() |
((uint128_t)(read_apdbkeyhi_el1()) << 64U);
/* Read APGAKey_EL1 */
- pauth_keys_after[4] = read_apgakeylo_el1() |
+ pauth_keys_arr[4] = read_apgakeylo_el1() |
((uint128_t)(read_apgakeyhi_el1()) << 64U);
}
diff --git a/plat/arm/common/arm_fwu_io_storage.c b/plat/arm/common/arm_fwu_io_storage.c
index 5af3e06..2f44a19 100644
--- a/plat/arm/common/arm_fwu_io_storage.c
+++ b/plat/arm/common/arm_fwu_io_storage.c
@@ -157,6 +157,9 @@
assert(image_id < ARRAY_SIZE(policies));
policy = &policies[image_id];
+ if (policy->check == NULL) {
+ return result;
+ }
result = policy->check(policy->image_spec);
if (result == IO_SUCCESS) {
*image_spec = policy->image_spec;
diff --git a/plat/arm/n1sdp/n1sdp_pwr_state.c b/plat/arm/n1sdp/n1sdp_pwr_state.c
index fcee7c4..d78f2ee 100644
--- a/plat/arm/n1sdp/n1sdp_pwr_state.c
+++ b/plat/arm/n1sdp/n1sdp_pwr_state.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#include <platform.h>
#include <psci.h>
-/* State IDs for local power states on SGI platforms. */
+/* State IDs for local power states on N1SDP platform. */
#define N1SDP_PS_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */
#define N1SDP_PS_RETENTION_STATE_ID 1 /* Valid for only CPUs */
#define N1SDP_PS_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */
diff --git a/plat/arm/sgi/common/aarch64/plat_helpers.S b/plat/arm/neoverse_rd/common/arch/aarch64/plat_helpers.S
similarity index 85%
rename from plat/arm/sgi/common/aarch64/plat_helpers.S
rename to plat/arm/neoverse_rd/common/arch/aarch64/plat_helpers.S
index e17c509..122d0b9 100644
--- a/plat/arm/sgi/common/aarch64/plat_helpers.S
+++ b/plat/arm/neoverse_rd/common/arch/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,15 +16,15 @@
/*----------------------------------------------------------------------
* unsigned int platform_get_core_pos(unsigned long mpid)
*
- * Function to calculate the core position on sgi platforms.
+ * Function to calculate the core position on Neoverse RD platforms.
*
- * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
- * (CPUId * CSS_SGI_MAX_PE_PER_CPU) +
+ * (ClusterId * NRD_MAX_CPUS_PER_CLUSTER * NRD_MAX_PE_PER_CPU) +
+ * (CPUId * NRD_MAX_PE_PER_CPU) +
* ThreadId
*
* which can be simplified as:
*
- * ((ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER + CPUId) * CSS_SGI_MAX_PE_PER_CPU)
+ * ((ClusterId * NRD_MAX_CPUS_PER_CLUSTER + CPUId) * NRD_MAX_PE_PER_CPU)
* + ThreadId
* ---------------------------------------------------------------------
*/
@@ -43,9 +43,9 @@
ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/* Compute linear position */
- mov x3, #CSS_SGI_MAX_CPUS_PER_CLUSTER
+ mov x3, #NRD_MAX_CPUS_PER_CLUSTER
madd x1, x2, x3, x1
- mov x3, #CSS_SGI_MAX_PE_PER_CPU
+ mov x3, #NRD_MAX_PE_PER_CPU
madd x0, x1, x3, x0
ret
endfunc platform_get_core_pos
diff --git a/plat/arm/sgi/common/include/sgi_base_platform_def.h b/plat/arm/neoverse_rd/common/include/nrd_base_platform_def.h
similarity index 84%
rename from plat/arm/sgi/common/include/sgi_base_platform_def.h
rename to plat/arm/neoverse_rd/common/include/nrd_base_platform_def.h
index 04673b3..6a7e487 100644
--- a/plat/arm/sgi/common/include/sgi_base_platform_def.h
+++ b/plat/arm/neoverse_rd/common/include/nrd_base_platform_def.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef SGI_BASE_PLATFORM_DEF_H
-#define SGI_BASE_PLATFORM_DEF_H
+#ifndef NRD_BASE_PLATFORM_DEF_H
+#define NRD_BASE_PLATFORM_DEF_H
#include <lib/utils_def.h>
@@ -14,19 +14,19 @@
#define PLATFORM_LINKER_ARCH aarch64
/* Sub-system Peripherals */
-#define SGI_DEVICE0_BASE UL(0x2A000000)
-#define SGI_DEVICE0_SIZE UL(0x26000000)
+#define NRD_DEVICE0_BASE UL(0x2A000000)
+#define NRD_DEVICE0_SIZE UL(0x26000000)
/* Peripherals and PCIe expansion area */
-#define SGI_DEVICE1_BASE UL(0x60000000)
-#define SGI_DEVICE1_SIZE UL(0x20000000)
+#define NRD_DEVICE1_BASE UL(0x60000000)
+#define NRD_DEVICE1_SIZE UL(0x20000000)
/* AP Non-Secure UART related constants */
-#define SGI_CSS_NSEC_UART_BASE UL(0x2A400000)
-#define SGI_CSS_NSEC_CLK_IN_HZ 7372800
+#define NRD_CSS_NSEC_UART_BASE UL(0x2A400000)
+#define NRD_CSS_NSEC_CLK_IN_HZ 7372800
-#define PLAT_ARM_UART_BASE SGI_CSS_NSEC_UART_BASE
-#define PLAT_ARM_UART_CLK_IN_HZ SGI_CSS_NSEC_CLK_IN_HZ
+#define PLAT_ARM_UART_BASE NRD_CSS_NSEC_UART_BASE
+#define PLAT_ARM_UART_CLK_IN_HZ NRD_CSS_NSEC_CLK_IN_HZ
/* Base address of trusted watchdog (SP805) */
#define SP805_TWDOG_BASE UL(0x2A480000)
@@ -69,7 +69,7 @@
#define PCPU_DV_MEM_STACK_SIZE 0x600
#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
- CSS_SGI_MAX_CPUS_PER_CLUSTER)
+ NRD_MAX_CPUS_PER_CLUSTER)
#define PLATFORM_NUM_AFFS (PLAT_ARM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
@@ -106,4 +106,4 @@
/* Per-CPU Hypervisor Timer Interrupt ID */
#define IRQ_PCPU_HP_TIMER 26
-#endif /* SGI_BASE_PLATFORM_DEF_H */
+#endif /* NRD_BASE_PLATFORM_DEF_H */
diff --git a/plat/arm/sgi/common/include/sgi_soc_css_def.h b/plat/arm/neoverse_rd/common/include/nrd_soc_css_def.h
similarity index 60%
rename from plat/arm/sgi/common/include/sgi_soc_css_def.h
rename to plat/arm/neoverse_rd/common/include/nrd_soc_css_def.h
index da73b3e..bffe189 100644
--- a/plat/arm/sgi/common/include/sgi_soc_css_def.h
+++ b/plat/arm/neoverse_rd/common/include/nrd_soc_css_def.h
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef SGI_SOC_CSS_DEF_H
-#define SGI_SOC_CSS_DEF_H
+#ifndef NRD_SOC_CSS_DEF_H
+#define NRD_SOC_CSS_DEF_H
/* Trusted watchdog (SP805) Interrupt ID */
#define IRQ_TWDOG_INTID 86
@@ -16,4 +16,4 @@
/* AP_REFCLK Generic Timer, Non-secure. */
#define IRQ_CNTPSIRQ1 92
-#endif /* SGI_SOC_CSS_DEF_H */
+#endif /* NRD_SOC_CSS_DEF_H */
diff --git a/plat/arm/neoverse_rd/common/include/nrd_soc_css_def_v2.h b/plat/arm/neoverse_rd/common/include/nrd_soc_css_def_v2.h
new file mode 100644
index 0000000..5d4f5e6
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd_soc_css_def_v2.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_SOC_CSS_DEF_V2_H
+#define NRD_SOC_CSS_DEF_V2_H
+
+/* Trusted watchdog (SP805) Interrupt ID */
+#define IRQ_TWDOG_INTID 107
+
+/* Maximum SPI */
+#define PLAT_MAX_SPI_OFFSET_ID 256
+
+/* AP_REFCLK Generic Timer, Non-secure. */
+#define IRQ_CNTPSIRQ1 109
+
+#endif /* NRD_SOC_CSS_DEF_V2_H */
+
diff --git a/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def.h b/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def.h
new file mode 100644
index 0000000..d329688
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_SOC_PLATFORM_H
+#define NRD_SOC_PLATFORM_H
+
+#include <nrd_base_platform_def.h>
+#include <nrd_soc_css_def.h>
+
+/* Base address of non-trusted watchdog (SP805) */
+#define SP805_WDOG_BASE UL(0x1C0F0000)
+
+#endif /* NRD_SOC_PLATFORM_H */
diff --git a/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def_v2.h b/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def_v2.h
new file mode 100644
index 0000000..7a23c51
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/include/nrd_soc_platform_def_v2.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NRD_SOC_PLATFORM_V2_H
+#define NRD_SOC_PLATFORM_V2_H
+
+#include <nrd_base_platform_def.h>
+#include <nrd_soc_css_def_v2.h>
+
+/* Base address of non-trusted watchdog (SP805) */
+#define SP805_WDOG_BASE UL(0x0C0F0000)
+
+#endif /* NRD_SOC_PLATFORM_V2_H */
diff --git a/plat/arm/neoverse_rd/common/nrd_common.mk b/plat/arm/neoverse_rd/common/nrd_common.mk
new file mode 100644
index 0000000..10ee08b
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/nrd_common.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PLAT_INCLUDES := -Iplat/arm/neoverse_rd/common/include/
+
+PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \
+ drivers/arm/gic/gic_v2.c \
+ drivers/arm/gic/gic_v3.c \
+ drivers/arm/sp805/sp805.c \
+ drivers/arm/timer/private_timer.c \
+ drivers/arm/timer/system_timer.c \
+ plat/arm/neoverse_rd/common/arch/${ARCH}/plat_helpers.S\
+ plat/arm/neoverse_rd/common/plat_setup.c \
+ plat/arm/neoverse_rd/common/nrd_mem_prot.c \
+ plat/arm/neoverse_rd/common/nrd_pwr_state.c
+
+include plat/arm/common/arm_common.mk
+
+ifeq (${USE_NVM},1)
+$(error "USE_NVM is not supported on Neoverse RD platforms")
+endif
+
+# Pass NRD_PLATFORM_VARIANT flag to the build system
+$(eval $(call add_define,TFTF_DEFINES,NRD_PLATFORM_VARIANT))
diff --git a/plat/arm/neoverse_rd/common/nrd_mem_prot.c b/plat/arm/neoverse_rd/common/nrd_mem_prot.c
new file mode 100644
index 0000000..9ea25e8
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/nrd_mem_prot.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform.h>
+
+#define NRD_DRAM1_NS_START (TFTF_BASE + 0x4000000)
+#define NRD_DRAM1_NS_SIZE 0x10000000
+
+static const mem_region_t nrd_ram_ranges[] = {
+ { NRD_DRAM1_NS_START, NRD_DRAM1_NS_SIZE },
+};
+
+const mem_region_t *plat_get_prot_regions(int *nelem)
+{
+ *nelem = ARRAY_SIZE(nrd_ram_ranges);
+ return nrd_ram_ranges;
+}
diff --git a/plat/arm/neoverse_rd/common/nrd_pwr_state.c b/plat/arm/neoverse_rd/common/nrd_pwr_state.c
new file mode 100644
index 0000000..31f81dd
--- /dev/null
+++ b/plat/arm/neoverse_rd/common/nrd_pwr_state.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform.h>
+#include <psci.h>
+
+/* State IDs for local power states on Neoverse RD platforms. */
+#define NRD_PS_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */
+#define NRD_PS_RETENTION_STATE_ID 1 /* Valid for only CPUs */
+#define NRD_PS_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */
+
+/* Suspend depth definitions for each power state */
+#define NRD_PS_RUN_DEPTH 0
+#define NRD_PS_RETENTION_DEPTH 1
+#define NRD_PS_OFF_DEPTH 2
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+ {NRD_PS_RETENTION_DEPTH, NRD_PS_RETENTION_STATE_ID,
+ PSTATE_TYPE_STANDBY},
+ {NRD_PS_OFF_DEPTH, NRD_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+/* The state property array with details of idle state possible for the cluster */
+static const plat_state_prop_t cluster_state_prop[] = {
+ {NRD_PS_OFF_DEPTH, NRD_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+ switch (level) {
+ case MPIDR_AFFLVL0:
+ return core_state_prop;
+ case MPIDR_AFFLVL1:
+ return cluster_state_prop;
+ default:
+ return NULL;
+ }
+}
diff --git a/plat/arm/sgi/common/plat_setup.c b/plat/arm/neoverse_rd/common/plat_setup.c
similarity index 72%
rename from plat/arm/sgi/common/plat_setup.c
rename to plat/arm/neoverse_rd/common/plat_setup.c
index f343f8d..4734bf0 100644
--- a/plat/arm/sgi/common/plat_setup.c
+++ b/plat/arm/neoverse_rd/common/plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,9 +8,9 @@
#include <xlat_tables_v2.h>
static const mmap_region_t mmap[] = {
- MAP_REGION_FLAT(SGI_DEVICE0_BASE, SGI_DEVICE0_SIZE,
+ MAP_REGION_FLAT(NRD_DEVICE0_BASE, NRD_DEVICE0_SIZE,
MT_DEVICE | MT_RW | MT_NS),
- MAP_REGION_FLAT(SGI_DEVICE1_BASE, SGI_DEVICE1_SIZE,
+ MAP_REGION_FLAT(NRD_DEVICE1_BASE, NRD_DEVICE1_SIZE,
MT_DEVICE | MT_RW | MT_NS),
MAP_REGION_FLAT(DRAM_BASE, TFTF_BASE - DRAM_BASE,
MT_MEMORY | MT_RW | MT_NS),
diff --git a/plat/arm/rdinfra/rdn1edge/include/platform_def.h b/plat/arm/neoverse_rd/platform/rdn1edge/include/platform_def.h
similarity index 72%
rename from plat/arm/rdinfra/rdn1edge/include/platform_def.h
rename to plat/arm/neoverse_rd/platform/rdn1edge/include/platform_def.h
index 0ae8ec5..2a3c7ac 100644
--- a/plat/arm/rdinfra/rdn1edge/include/platform_def.h
+++ b/plat/arm/neoverse_rd/platform/rdn1edge/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,11 +7,11 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#include "sgi_soc_platform_def.h"
+#include "nrd_soc_platform_def.h"
#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(4)
+#define NRD_MAX_PE_PER_CPU U(1)
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
diff --git a/plat/arm/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/neoverse_rd/platform/rdn1edge/platform.mk
new file mode 100644
index 0000000..9f92efd
--- /dev/null
+++ b/plat/arm/neoverse_rd/platform/rdn1edge/platform.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/neoverse_rd/common/nrd_common.mk
+
+PLAT_INCLUDES += -Iplat/arm/neoverse_rd/platform/rdn1edge/include/
+
+PLAT_SOURCES += plat/arm/neoverse_rd/platform/rdn1edge/topology.c
+
+PLAT_TESTS_SKIP_LIST := plat/arm/neoverse_rd/platform/rdn1edge/tests_to_skip.txt
+
+ifdef NRD_PLATFORM_VARIANT
+$(error "NRD_PLATFORM_VARIANT should not be set for RD-N1-Edge, \
+ currently set to ${NRD_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/rdinfra/rdn1edge/tests_to_skip.txt b/plat/arm/neoverse_rd/platform/rdn1edge/tests_to_skip.txt
similarity index 78%
rename from plat/arm/rdinfra/rdn1edge/tests_to_skip.txt
rename to plat/arm/neoverse_rd/platform/rdn1edge/tests_to_skip.txt
index 95360bc..6341809 100644
--- a/plat/arm/rdinfra/rdn1edge/tests_to_skip.txt
+++ b/plat/arm/neoverse_rd/platform/rdn1edge/tests_to_skip.txt
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/plat/arm/rdinfra/rdn1edge/topology.c b/plat/arm/neoverse_rd/platform/rdn1edge/topology.c
similarity index 89%
rename from plat/arm/rdinfra/rdn1edge/topology.c
rename to plat/arm/neoverse_rd/platform/rdn1edge/topology.c
index 6f20695..cb79ba6 100644
--- a/plat/arm/rdinfra/rdn1edge/topology.c
+++ b/plat/arm/neoverse_rd/platform/rdn1edge/topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -34,9 +34,9 @@
/* Number of root nodes */
PLAT_ARM_CLUSTER_COUNT,
/* Number of children for the 1st node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 2nd node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER
};
const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
diff --git a/plat/arm/rdinfra/rdn2/include/platform_def.h b/plat/arm/neoverse_rd/platform/rdn2/include/platform_def.h
similarity index 69%
rename from plat/arm/rdinfra/rdn2/include/platform_def.h
rename to plat/arm/neoverse_rd/platform/rdn2/include/platform_def.h
index ab4149d..177d911 100644
--- a/plat/arm/rdinfra/rdn2/include/platform_def.h
+++ b/plat/arm/neoverse_rd/platform/rdn2/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,25 +7,25 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#include <sgi_soc_platform_def_v2.h>
+#include <nrd_soc_platform_def_v2.h>
/*
* The RD-N2 Cfg1 platform is a variant of the RD-N2 platform with a
* reduced interconnect mesh size (3x3) and core count (8-cores).
*
- * The $CSS_SGI_PLATFORM_VARIANT flag is set to 1 for RD-N2-Cfg1 platform.
+ * The $NRD_PLATFORM_VARIANT flag is set to 1 for RD-N2-Cfg1 platform.
*/
-#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#if (NRD_PLATFORM_VARIANT == 1)
#define PLAT_ARM_CLUSTER_COUNT U(8)
#else
#define PLAT_ARM_CLUSTER_COUNT U(16)
#endif
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
/* GIC-600 & interrupt handling related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#if (NRD_PLATFORM_VARIANT == 1)
#define PLAT_ARM_GICR_BASE UL(0x30100000)
#else
#define PLAT_ARM_GICR_BASE UL(0x301C0000)
diff --git a/plat/arm/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/neoverse_rd/platform/rdn2/platform.mk
new file mode 100644
index 0000000..31d91a1
--- /dev/null
+++ b/plat/arm/neoverse_rd/platform/rdn2/platform.mk
@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/neoverse_rd/common/nrd_common.mk
+
+PLAT_INCLUDES += -Iplat/arm/neoverse_rd/platform/rdn2/include/
+
+PLAT_SOURCES += plat/arm/neoverse_rd/platform/rdn2/topology.c
+
+PLAT_TESTS_SKIP_LIST := plat/arm/neoverse_rd/platform/rdn2/tests_to_skip.txt
+
+RD_N2_VARIANTS := 0 1 3
+
+ifneq ($(NRD_PLATFORM_VARIANT), \
+ $(filter $(NRD_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
+ $(error "NRD_PLATFORM_VARIANT for RD-N2 should be 0 1 or 3, currently \
+ set to ${NRD_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/rdinfra/rdn2/tests_to_skip.txt b/plat/arm/neoverse_rd/platform/rdn2/tests_to_skip.txt
similarity index 84%
rename from plat/arm/rdinfra/rdn2/tests_to_skip.txt
rename to plat/arm/neoverse_rd/platform/rdn2/tests_to_skip.txt
index b8a433d..2c9acee 100644
--- a/plat/arm/rdinfra/rdn2/tests_to_skip.txt
+++ b/plat/arm/neoverse_rd/platform/rdn2/tests_to_skip.txt
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, Arm Limited. All rights reserved.
+# Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/plat/arm/rdinfra/rdv1/topology.c b/plat/arm/neoverse_rd/platform/rdn2/topology.c
similarity index 78%
copy from plat/arm/rdinfra/rdv1/topology.c
copy to plat/arm/neoverse_rd/platform/rdn2/topology.c
index ad13285..3cd3121 100644
--- a/plat/arm/rdinfra/rdv1/topology.c
+++ b/plat/arm/neoverse_rd/platform/rdn2/topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,7 @@
{ 6, 0 },
/* Cluster7: 1 core */
{ 7, 0 },
+#if (NRD_PLATFORM_VARIANT == 0)
/* Cluster8: 1 core */
{ 8, 0 },
/* Cluster9: 1 core */
@@ -44,6 +45,7 @@
{ 14, 0 },
/* Cluster15: 1 core */
{ 15, 0 },
+#endif
};
/*
@@ -56,37 +58,39 @@
/* Number of root nodes */
PLAT_ARM_CLUSTER_COUNT,
/* Number of children for the 1st node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 2nd node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 3rd node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 4th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 5th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 6th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 7th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 8th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
+#if (NRD_PLATFORM_VARIANT == 0)
/* Number of children for the 9th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 10th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 11th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 12th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 13th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 14th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 15th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 16th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER
+#endif
};
const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
diff --git a/plat/arm/rdinfra/rdv1/include/platform_def.h b/plat/arm/neoverse_rd/platform/rdv1/include/platform_def.h
similarity index 72%
rename from plat/arm/rdinfra/rdv1/include/platform_def.h
rename to plat/arm/neoverse_rd/platform/rdv1/include/platform_def.h
index 7869551..6b78d95 100644
--- a/plat/arm/rdinfra/rdv1/include/platform_def.h
+++ b/plat/arm/neoverse_rd/platform/rdv1/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,11 +7,11 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#include <sgi_soc_platform_def.h>
+#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(16)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(1)
+#define NRD_MAX_PE_PER_CPU U(1)
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
diff --git a/plat/arm/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/neoverse_rd/platform/rdv1/platform.mk
new file mode 100644
index 0000000..cfb8543
--- /dev/null
+++ b/plat/arm/neoverse_rd/platform/rdv1/platform.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/neoverse_rd/common/nrd_common.mk
+
+PLAT_INCLUDES += -Iplat/arm/neoverse_rd/platform/rdv1/include/
+
+PLAT_SOURCES += plat/arm/neoverse_rd/platform/rdv1/topology.c
+
+PLAT_TESTS_SKIP_LIST := plat/arm/neoverse_rd/platform/rdv1/tests_to_skip.txt
+
+ifdef NRD_PLATFORM_VARIANT
+$(error "NRD_PLATFORM_VARIANT should not be set for RD-V1, \
+ currently set to ${NRD_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/rdinfra/rdv1/tests_to_skip.txt b/plat/arm/neoverse_rd/platform/rdv1/tests_to_skip.txt
similarity index 89%
rename from plat/arm/rdinfra/rdv1/tests_to_skip.txt
rename to plat/arm/neoverse_rd/platform/rdv1/tests_to_skip.txt
index 9b3ff5f..d62b9dd 100644
--- a/plat/arm/rdinfra/rdv1/tests_to_skip.txt
+++ b/plat/arm/neoverse_rd/platform/rdv1/tests_to_skip.txt
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2022, Arm Limited. All rights reserved.
+# Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/plat/arm/rdinfra/rdv1/topology.c b/plat/arm/neoverse_rd/platform/rdv1/topology.c
similarity index 79%
rename from plat/arm/rdinfra/rdv1/topology.c
rename to plat/arm/neoverse_rd/platform/rdv1/topology.c
index ad13285..882bffb 100644
--- a/plat/arm/rdinfra/rdv1/topology.c
+++ b/plat/arm/neoverse_rd/platform/rdv1/topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -56,37 +56,37 @@
/* Number of root nodes */
PLAT_ARM_CLUSTER_COUNT,
/* Number of children for the 1st node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 2nd node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 3rd node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 4th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 5th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 6th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 7th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 8th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 9th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 10th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 11th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 12th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 13th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 14th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 15th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 16th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER
};
const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
diff --git a/plat/arm/rdinfra/rdn1edge/include/platform_def.h b/plat/arm/neoverse_rd/platform/sgi575/include/platform_def.h
similarity index 72%
copy from plat/arm/rdinfra/rdn1edge/include/platform_def.h
copy to plat/arm/neoverse_rd/platform/sgi575/include/platform_def.h
index 0ae8ec5..bdaecb9 100644
--- a/plat/arm/rdinfra/rdn1edge/include/platform_def.h
+++ b/plat/arm/neoverse_rd/platform/sgi575/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,11 +7,11 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#include "sgi_soc_platform_def.h"
+#include <nrd_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
+#define NRD_MAX_CPUS_PER_CLUSTER U(4)
+#define NRD_MAX_PE_PER_CPU U(1)
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
diff --git a/plat/arm/neoverse_rd/platform/sgi575/platform.mk b/plat/arm/neoverse_rd/platform/sgi575/platform.mk
new file mode 100644
index 0000000..5e81be5
--- /dev/null
+++ b/plat/arm/neoverse_rd/platform/sgi575/platform.mk
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/arm/neoverse_rd/common/nrd_common.mk
+
+PLAT_INCLUDES += -Iplat/arm/neoverse_rd/platform/sgi575/include/
+
+PLAT_SOURCES += plat/arm/neoverse_rd/platform/sgi575/sgi575_topology.c
+
+PLAT_TESTS_SKIP_LIST := plat/arm/neoverse_rd/platform/sgi575/tests_to_skip.txt
+
+ifdef NRD_PLATFORM_VARIANT
+$(error "NRD_PLATFORM_VARIANT should not be set for SGI-575, \
+ currently set to ${NRD_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/sgi/sgi575/sgi575_topology.c b/plat/arm/neoverse_rd/platform/sgi575/sgi575_topology.c
similarity index 89%
rename from plat/arm/sgi/sgi575/sgi575_topology.c
rename to plat/arm/neoverse_rd/platform/sgi575/sgi575_topology.c
index c01ad83..f38c197 100644
--- a/plat/arm/sgi/sgi575/sgi575_topology.c
+++ b/plat/arm/neoverse_rd/platform/sgi575/sgi575_topology.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -34,9 +34,9 @@
/* Number of root nodes */
PLAT_ARM_CLUSTER_COUNT,
/* Number of children for the 1st node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
+ NRD_MAX_CPUS_PER_CLUSTER,
/* Number of children for the 2nd node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER
+ NRD_MAX_CPUS_PER_CLUSTER
};
const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
diff --git a/plat/arm/sgi/sgi575/tests_to_skip.txt b/plat/arm/neoverse_rd/platform/sgi575/tests_to_skip.txt
similarity index 78%
rename from plat/arm/sgi/sgi575/tests_to_skip.txt
rename to plat/arm/neoverse_rd/platform/sgi575/tests_to_skip.txt
index 1af24d8..8817946 100644
--- a/plat/arm/sgi/sgi575/tests_to_skip.txt
+++ b/plat/arm/neoverse_rd/platform/sgi575/tests_to_skip.txt
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/plat/arm/rdinfra/rdn1edge/platform.mk b/plat/arm/rdinfra/rdn1edge/platform.mk
deleted file mode 100644
index d44e5a0..0000000
--- a/plat/arm/rdinfra/rdn1edge/platform.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/sgi/common/sgi_common.mk
-
-PLAT_INCLUDES += -Iplat/arm/rdinfra/rdn1edge/include/
-
-PLAT_SOURCES += plat/arm/rdinfra/rdn1edge/topology.c
-
-PLAT_TESTS_SKIP_LIST := plat/arm/rdinfra/rdn1edge/tests_to_skip.txt
-
-ifdef CSS_SGI_PLATFORM_VARIANT
-$(error "CSS_SGI_PLATFORM_VARIANT should not be set for RD-N1-Edge, \
- currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
-endif
diff --git a/plat/arm/rdinfra/rdn2/platform.mk b/plat/arm/rdinfra/rdn2/platform.mk
deleted file mode 100644
index 3d4ffe6..0000000
--- a/plat/arm/rdinfra/rdn2/platform.mk
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Copyright (c) 2022, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/sgi/common/sgi_common.mk
-
-PLAT_INCLUDES += -Iplat/arm/rdinfra/rdn2/include/
-
-PLAT_SOURCES += plat/arm/rdinfra/rdn2/topology.c
-
-PLAT_TESTS_SKIP_LIST := plat/arm/rdinfra/rdn2/tests_to_skip.txt
-
-RD_N2_VARIANTS := 0 1 3
-
-ifneq ($(CSS_SGI_PLATFORM_VARIANT), \
- $(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
- $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0 1 or 3, currently \
- set to ${CSS_SGI_PLATFORM_VARIANT}.")
-endif
diff --git a/plat/arm/rdinfra/rdn2/topology.c b/plat/arm/rdinfra/rdn2/topology.c
deleted file mode 100644
index 6918638..0000000
--- a/plat/arm/rdinfra/rdn2/topology.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <plat_topology.h>
-#include <tftf_lib.h>
-
-static const struct {
- unsigned int cluster_id;
- unsigned int cpu_id;
-} plat_cores[] = {
- /* Cluster0: 1 core */
- { 0, 0 },
- /* Cluster1: 1 core */
- { 1, 0 },
- /* Cluster2: 1 core */
- { 2, 0 },
- /* Cluster3: 1 core */
- { 3, 0 },
- /* Cluster4: 1 core */
- { 4, 0 },
- /* Cluster5: 1 core */
- { 5, 0 },
- /* Cluster6: 1 core */
- { 6, 0 },
- /* Cluster7: 1 core */
- { 7, 0 },
-#if (CSS_SGI_PLATFORM_VARIANT == 0)
- /* Cluster8: 1 core */
- { 8, 0 },
- /* Cluster9: 1 core */
- { 9, 0 },
- /* Cluster10: 1 core */
- { 10, 0 },
- /* Cluster11: 1 core */
- { 11, 0 },
- /* Cluster12: 1 core */
- { 12, 0 },
- /* Cluster13: 1 core */
- { 13, 0 },
- /* Cluster14: 1 core */
- { 14, 0 },
- /* Cluster15: 1 core */
- { 15, 0 },
-#endif
-};
-
-/*
- * The power domain tree descriptor. The cluster power domains are
- * arranged so that when the PSCI generic code creates the power domain tree,
- * the indices of the CPU power domain nodes it allocates match the linear
- * indices returned by plat_core_pos_by_mpidr().
- */
-const unsigned char plat_pd_tree_desc[] = {
- /* Number of root nodes */
- PLAT_ARM_CLUSTER_COUNT,
- /* Number of children for the 1st node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 2nd node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 3rd node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 4th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 5th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 6th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 7th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 8th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
-#if (CSS_SGI_PLATFORM_VARIANT == 0)
- /* Number of children for the 9th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 10th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 11th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 12th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 13th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 14th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 15th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER,
- /* Number of children for the 16th node */
- CSS_SGI_MAX_CPUS_PER_CLUSTER
-#endif
-};
-
-const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
-{
- return plat_pd_tree_desc;
-}
-
-uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
-{
- unsigned int mpid;
-
- assert(core_pos < PLATFORM_CORE_COUNT);
-
- mpid = make_mpid(plat_cores[core_pos].cluster_id,
- plat_cores[core_pos].cpu_id);
-
- return (uint64_t)mpid;
-}
diff --git a/plat/arm/rdinfra/rdv1/platform.mk b/plat/arm/rdinfra/rdv1/platform.mk
deleted file mode 100644
index 8001ec5..0000000
--- a/plat/arm/rdinfra/rdv1/platform.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (c) 2022, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/sgi/common/sgi_common.mk
-
-PLAT_INCLUDES += -Iplat/arm/rdinfra/rdv1/include/
-
-PLAT_SOURCES += plat/arm/rdinfra/rdv1/topology.c
-
-PLAT_TESTS_SKIP_LIST := plat/arm/rdinfra/rdv1/tests_to_skip.txt
-
-ifdef CSS_SGI_PLATFORM_VARIANT
-$(error "CSS_SGI_PLATFORM_VARIANT should not be set for RD-V1, \
- currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
-endif
diff --git a/plat/arm/sgi/common/include/sgi_soc_css_def_v2.h b/plat/arm/sgi/common/include/sgi_soc_css_def_v2.h
deleted file mode 100644
index e834386..0000000
--- a/plat/arm/sgi/common/include/sgi_soc_css_def_v2.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SGI_SOC_CSS_DEF_V2_H
-#define SGI_SOC_CSS_DEF_V2_H
-
-/* Trusted watchdog (SP805) Interrupt ID */
-#define IRQ_TWDOG_INTID 107
-
-/* Maximum SPI */
-#define PLAT_MAX_SPI_OFFSET_ID 256
-
-/* AP_REFCLK Generic Timer, Non-secure. */
-#define IRQ_CNTPSIRQ1 109
-
-#endif /* SGI_SOC_CSS_DEF_V2_H */
-
diff --git a/plat/arm/sgi/common/include/sgi_soc_platform_def.h b/plat/arm/sgi/common/include/sgi_soc_platform_def.h
deleted file mode 100644
index fc60999..0000000
--- a/plat/arm/sgi/common/include/sgi_soc_platform_def.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SGI_SOC_PLATFORM_H
-#define SGI_SOC_PLATFORM_H
-
-#include <sgi_base_platform_def.h>
-#include <sgi_soc_css_def.h>
-
-/* Base address of non-trusted watchdog (SP805) */
-#define SP805_WDOG_BASE UL(0x1C0F0000)
-
-#endif /* SGI_SOC_PLATFORM_H */
diff --git a/plat/arm/sgi/common/include/sgi_soc_platform_def_v2.h b/plat/arm/sgi/common/include/sgi_soc_platform_def_v2.h
deleted file mode 100644
index fad31ca..0000000
--- a/plat/arm/sgi/common/include/sgi_soc_platform_def_v2.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SGI_SOC_PLATFORM_V2_H
-#define SGI_SOC_PLATFORM_V2_H
-
-#include <sgi_base_platform_def.h>
-#include <sgi_soc_css_def_v2.h>
-
-/* Base address of non-trusted watchdog (SP805) */
-#define SP805_WDOG_BASE UL(0x0C0F0000)
-
-#endif /* SGI_SOC_PLATFORM_V2_H */
diff --git a/plat/arm/sgi/common/sgi_common.mk b/plat/arm/sgi/common/sgi_common.mk
deleted file mode 100644
index 45d8485..0000000
--- a/plat/arm/sgi/common/sgi_common.mk
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright (c) 2018-2022, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-PLAT_INCLUDES := -Iplat/arm/sgi/common/include/
-
-PLAT_SOURCES := drivers/arm/gic/arm_gic_v2v3.c \
- drivers/arm/gic/gic_v2.c \
- drivers/arm/gic/gic_v3.c \
- drivers/arm/sp805/sp805.c \
- drivers/arm/timer/private_timer.c \
- drivers/arm/timer/system_timer.c \
- plat/arm/sgi/common/${ARCH}/plat_helpers.S \
- plat/arm/sgi/common/plat_setup.c \
- plat/arm/sgi/common/sgi_mem_prot.c \
- plat/arm/sgi/common/sgi_pwr_state.c
-
-include plat/arm/common/arm_common.mk
-
-ifeq (${USE_NVM},1)
-$(error "USE_NVM is not supported on SGI platforms")
-endif
-
-# Pass CSS_SGI_PLATFORM_VARIANT flag to the build system
-$(eval $(call add_define,TFTF_DEFINES,CSS_SGI_PLATFORM_VARIANT))
diff --git a/plat/arm/sgi/common/sgi_mem_prot.c b/plat/arm/sgi/common/sgi_mem_prot.c
deleted file mode 100644
index 14da4cd..0000000
--- a/plat/arm/sgi/common/sgi_mem_prot.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform.h>
-
-#define SGI_DRAM1_NS_START (TFTF_BASE + 0x4000000)
-#define SGI_DRAM1_NS_SIZE 0x10000000
-
-static const mem_region_t sgi_ram_ranges[] = {
- { SGI_DRAM1_NS_START, SGI_DRAM1_NS_SIZE },
-};
-
-const mem_region_t *plat_get_prot_regions(int *nelem)
-{
- *nelem = ARRAY_SIZE(sgi_ram_ranges);
- return sgi_ram_ranges;
-}
diff --git a/plat/arm/sgi/common/sgi_pwr_state.c b/plat/arm/sgi/common/sgi_pwr_state.c
deleted file mode 100644
index 305d1f5..0000000
--- a/plat/arm/sgi/common/sgi_pwr_state.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform.h>
-#include <psci.h>
-
-/* State IDs for local power states on SGI platforms. */
-#define SGI_PS_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */
-#define SGI_PS_RETENTION_STATE_ID 1 /* Valid for only CPUs */
-#define SGI_PS_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */
-
-/* Suspend depth definitions for each power state */
-#define SGI_PS_RUN_DEPTH 0
-#define SGI_PS_RETENTION_DEPTH 1
-#define SGI_PS_OFF_DEPTH 2
-
-/* The state property array with details of idle state possible for the core */
-static const plat_state_prop_t core_state_prop[] = {
- {SGI_PS_RETENTION_DEPTH, SGI_PS_RETENTION_STATE_ID,
- PSTATE_TYPE_STANDBY},
- {SGI_PS_OFF_DEPTH, SGI_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
- {0},
-};
-
-/* The state property array with details of idle state possible for the cluster */
-static const plat_state_prop_t cluster_state_prop[] = {
- {SGI_PS_OFF_DEPTH, SGI_PS_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
- {0},
-};
-
-const plat_state_prop_t *plat_get_state_prop(unsigned int level)
-{
- switch (level) {
- case MPIDR_AFFLVL0:
- return core_state_prop;
- case MPIDR_AFFLVL1:
- return cluster_state_prop;
- default:
- return NULL;
- }
-}
diff --git a/plat/arm/sgi/sgi575/include/platform_def.h b/plat/arm/sgi/sgi575/include/platform_def.h
deleted file mode 100644
index 237978c..0000000
--- a/plat/arm/sgi/sgi575/include/platform_def.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <sgi_soc_platform_def.h>
-
-#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(4)
-#define CSS_SGI_MAX_PE_PER_CPU U(1)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICC_BASE UL(0x2C000000)
-#define PLAT_ARM_GICR_BASE UL(0x300C0000)
-
-/* Platform specific page table and MMU setup constants */
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/sgi/sgi575/platform.mk b/plat/arm/sgi/sgi575/platform.mk
deleted file mode 100644
index 7c8194f..0000000
--- a/plat/arm/sgi/sgi575/platform.mk
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Copyright (c) 2018-2022, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/sgi/common/sgi_common.mk
-
-PLAT_INCLUDES += -Iplat/arm/sgi/sgi575/include/
-
-PLAT_SOURCES += plat/arm/sgi/sgi575/sgi575_topology.c
-
-PLAT_TESTS_SKIP_LIST := plat/arm/sgi/sgi575/tests_to_skip.txt
-
-ifdef CSS_SGI_PLATFORM_VARIANT
-$(error "CSS_SGI_PLATFORM_VARIANT should not be set for SGI-575, \
- currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
-endif
diff --git a/plat/arm/tc/include/platform_def.h b/plat/arm/tc/include/platform_def.h
index 1f0c28d..82fa6c2 100644
--- a/plat/arm/tc/include/platform_def.h
+++ b/plat/arm/tc/include/platform_def.h
@@ -80,7 +80,7 @@
#define TC_GICC_BASE 0x2C000000
/* SoC's PL011 UART0 related constants */
-#define PL011_UART0_BASE 0x7FF70000
+#define PL011_UART0_BASE 0x2A400000
#define PL011_UART0_CLK_IN_HZ 7372800
/* SoC's PL011 UART1 related constants */
diff --git a/plat/arm/tc/tc_pwr_state.c b/plat/arm/tc/tc_pwr_state.c
index 46d952b..97fcd97 100644
--- a/plat/arm/tc/tc_pwr_state.c
+++ b/plat/arm/tc/tc_pwr_state.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#include <platform.h>
#include <psci.h>
-/* State IDs for local power states on SGI platforms. */
+/* State IDs for local power states on TC platform. */
#define TC_PS_RUN_STATE_ID 0 /* Valid for CPUs and Clusters */
#define TC_PS_RETENTION_STATE_ID 1 /* Valid for only CPUs */
#define TC_PS_OFF_STATE_ID 2 /* Valid for CPUs and Clusters */
diff --git a/plat/xilinx/common/timer/timers.c b/plat/xilinx/common/timer/timers.c
index a6e1afa..f53cd84 100644
--- a/plat/xilinx/common/timer/timers.c
+++ b/plat/xilinx/common/timer/timers.c
@@ -27,7 +27,6 @@
#define TTC_CNT_CNTRL_DISABLE_MASK BIT(0)
-#define TTC_CLK_SEL_OFFSET U(0x360)
#define TTC_CLK_SEL_MASK GENMASK(1, 0)
#define TTC_CLK_SEL_PS_REF BIT(0)
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 925825c..73b6db2 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -116,5 +116,6 @@
#define IRQ_TWDOG_INTID U(0x51)
#define TTC_TIMER_IRQ U(69)
+#define TTC_CLK_SEL_OFFSET U(0x360)
#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal/tests_to_skip.txt b/plat/xilinx/versal/tests_to_skip.txt
index b430058..87b9e41 100644
--- a/plat/xilinx/versal/tests_to_skip.txt
+++ b/plat/xilinx/versal/tests_to_skip.txt
@@ -13,6 +13,9 @@
Timer framework Validation/Target timer to a power down cpu
Timer framework Validation/Test scenario where multiple CPUs call same timeout
+#TESTS: Boot requirement tests
+Boot requirement tests
+
#TESTS: psci
PSCI Affinity Info/Affinity info level0 powerdown
PSCI CPU Suspend/CPU suspend to powerdown at level 0
@@ -21,8 +24,7 @@
PSCI CPU Suspend/CPU suspend to standby at level 0
PSCI CPU Suspend/CPU suspend to standby at level 1
PSCI CPU Suspend/CPU suspend to standby at level 2
-PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 0 in OSI mode
-PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 1 in OSI mode
+PSCI CPU Suspend in OSI mode
CPU Hotplug/Invalid entry point
PSCI System Suspend Validation/System suspend multiple times
PSCI System Suspend Validation/system suspend from all cores
diff --git a/plat/xilinx/versal_net/include/platform_def.h b/plat/xilinx/versal_net/include/platform_def.h
index 8431ca6..92a7ba0 100644
--- a/plat/xilinx/versal_net/include/platform_def.h
+++ b/plat/xilinx/versal_net/include/platform_def.h
@@ -122,5 +122,6 @@
#define IRQ_TWDOG_INTID U(0x51)
#define TTC_TIMER_IRQ U(75)
+#define TTC_CLK_SEL_OFFSET U(0x360)
#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal_net/tests_to_skip.txt b/plat/xilinx/versal_net/tests_to_skip.txt
index 46bc1a3..d5c3a39 100644
--- a/plat/xilinx/versal_net/tests_to_skip.txt
+++ b/plat/xilinx/versal_net/tests_to_skip.txt
@@ -53,8 +53,7 @@
PSCI CPU Suspend/CPU suspend to standby at level 0
PSCI CPU Suspend/CPU suspend to standby at level 1
PSCI CPU Suspend/CPU suspend to standby at level 2
-PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 0 in OSI mode
-PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 1 in OSI mode
+PSCI CPU Suspend in OSI mode
PSCI System Suspend Validation/System suspend multiple times
PSCI System Suspend Validation/system suspend from all cores
PSCI System Suspend Validation/Validate suspend to RAM functionality
diff --git a/plat/xilinx/zynqmp/aarch64/plat_helpers.S b/plat/xilinx/zynqmp/aarch64/plat_helpers.S
new file mode 100644
index 0000000..48155bb
--- /dev/null
+++ b/plat/xilinx/zynqmp/aarch64/plat_helpers.S
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+#include <drivers/console.h>
+
+ .globl platform_get_core_pos
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+ .globl plat_crash_console_flush
+
+/*----------------------------------------------------------------------
+ * unsigned int platform_get_core_pos(unsigned long mpid)
+ *
+ * Function to calculate the core position.
+ * Return 0 to 3 as logical CPU ID.
+*/
+func platform_get_core_pos
+ lsr x1, x0, #MPIDR_AFF0_SHIFT
+ and x1, x1, #MPIDR_AFFLVL_MASK /* core id */
+ lsr x2, x0, #MPIDR_AFF1_SHIFT
+ and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */
+
+ /* core_id > PLATFORM_CORES_CLUSTER */
+ mov x0, #-1
+ cmp x1, #(PLATFORM_CORES_PER_CLUSTER - 1)
+ b.hi 1f
+
+ /* cluster_id > PLATFORM_CLUSTER_COUNT */
+ cmp x2, #(PLATFORM_CLUSTER_COUNT - 1)
+ b.hi 1f
+
+ /* CorePos = CoreId + (ClusterId * cpus per cluster) */
+ mov x3, #PLATFORM_CORES_PER_CLUSTER
+ mul x3, x2, x3
+ add x0, x1, x3
+
+1:
+ ret
+endfunc platform_get_core_pos
+
+ /* ---------------------------------------------
+ * int plat_crash_console_init(void)
+ * Function to initialize the crash console
+ * without a C Runtime to print crash report.
+ * Clobber list : x0 - x4
+ * ---------------------------------------------
+ */
+func plat_crash_console_init
+ mov_imm x0, ZYNQMP_UART_BASE
+ mov_imm x1, ZYNQMP_CRASH_UART_CLK_IN_HZ
+ mov_imm x2, ZYNQMP_UART_BAUDRATE
+ b console_init
+endfunc plat_crash_console_init
+
+ /* ---------------------------------------------
+ * int plat_crash_console_putc(int c)
+ * Function to print a character on the crash
+ * console without a C Runtime.
+ * Clobber list : x1, x2
+ * ---------------------------------------------
+ */
+func plat_crash_console_putc
+ mov_imm x1, ZYNQMP_UART_BASE
+ b console_putc
+endfunc plat_crash_console_putc
+
+ /* ---------------------------------------------
+ * int plat_crash_console_flush()
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * Out : return -1 on error else return 0.
+ * Clobber list : r0 - r1
+ * ---------------------------------------------
+ */
+func plat_crash_console_flush
+ mov_imm x1, ZYNQMP_UART_BASE
+ b console_flush
+endfunc plat_crash_console_flush
diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h
new file mode 100644
index 0000000..cb3a707
--- /dev/null
+++ b/plat/xilinx/zynqmp/include/platform_def.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <utils_def.h>
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+#define TFTF_BASE U(0x8000000)
+
+#define DRAM_BASE 0x0
+#define DRAM_SIZE 0x80000000
+
+#define PLATFORM_CLUSTER_COUNT U(1)
+#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
+ PLATFORM_CORE_COUNT_PER_CLUSTER)
+#define PLATFORM_CORES_PER_CLUSTER PLATFORM_CORE_COUNT_PER_CLUSTER
+
+#define PLATFORM_NUM_AFFS (PLATFORM_CORE_COUNT + \
+ PLATFORM_CLUSTER_COUNT + 1)
+
+#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
+#define PLAT_MAX_PWR_LEVEL MPIDR_AFFLVL2
+
+#define PLAT_MAX_PWR_STATES_PER_LVL 2
+
+#define PLATFORM_STACK_SIZE 0x440
+#define PCPU_DV_MEM_STACK_SIZE 0x100
+
+#define TFTF_NVM_SIZE 0x600000
+#define TFTF_NVM_OFFSET 0x20000000
+
+/* total number of system nodes implemented by the platform */
+#define PLATFORM_SYSTEM_COUNT U(1)
+
+/* UG1085 - system interrupts table */
+#define PLAT_MAX_SPI_OFFSET_ID 229
+
+/* Local state bit width for each level in the state-ID field of power state */
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+
+#define PLAT_MAX_PWR_STATES_PER_LVL 2
+
+#define IRQ_PCPU_NS_TIMER 51
+
+#define IRQ_CNTPSIRQ1 80
+
+#define PLAT_SUSPEND_ENTRY_TIME 15
+#define PLAT_SUSPEND_ENTRY_EXIT_TIME 30
+
+#define IRQ_PCPU_HP_TIMER 26
+
+#define ZYNQMP_UART0_BASE 0xFF000000
+#define ZYNQMP_UART1_BASE 0xFF010000
+
+#define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE
+#define CRASH_CONSOLE_SIZE 0x1000
+
+#define ZYNQMP_CRASH_UART_CLK_IN_HZ 100000000
+#define ZYNQMP_UART_BAUDRATE 115200
+
+#define CACHE_WRITEBACK_SHIFT 6
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+/* Non-Secure Software Generated Interrupts IDs */
+
+#define IRQ_NS_SGI_0 0
+#define IRQ_NS_SGI_1 1
+#define IRQ_NS_SGI_2 2
+#define IRQ_NS_SGI_3 3
+#define IRQ_NS_SGI_4 4
+#define IRQ_NS_SGI_5 5
+#define IRQ_NS_SGI_6 6
+#define IRQ_NS_SGI_7 7
+
+/* Platform specific page table and MMU setup constants */
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
+
+/* Translation table constants */
+#define MAX_XLAT_TABLES 8
+#define MAX_MMAP_REGIONS 16
+
+/* ZYNQMP memory map related constants */
+
+/* Aggregate of all devices in the first GB */
+#define DEVICE0_BASE U(0xFF000000)
+#define DEVICE0_SIZE U(0x00E00000)
+#define DEVICE1_BASE U(0xF9000000)
+#define DEVICE1_SIZE U(0x00800000)
+
+/* GIC-400 & interrupt handling related constants */
+
+#define GIC_BASE DEVICE1_BASE
+#define GIC_SIZE 0x00080000
+#define BASE_GICD_BASE 0xF9010000
+#define BASE_GICC_BASE 0xF9020000
+#define BASE_GICH_BASE 0xF9040000
+#define BASE_GICV_BASE 0xF9060000
+
+#define TTC_BASE U(0xff140000)
+#define TTC_SIZE U(0x00010000)
+
+#define SYS_CNT_BASE1 TTC_BASE
+#define SYS_CNT_SIZE TTC_SIZE
+
+/* timer */
+#define LPD_IOU_SLCR U(0xff180000)
+#define LPD_IOU_SLCR_SIZE U(0x00010000)
+#define TTC_TIMER_IRQ U(77)
+#define TTC_CLK_SEL_OFFSET U(0x380)
+#define IRQ_TWDOG_INTID TTC_TIMER_IRQ
+#endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
new file mode 100644
index 0000000..201c2ee
--- /dev/null
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+XLNX_COMMON_PATH := plat/xilinx/common
+ZYNQMP_PATH := plat/xilinx/zynqmp
+
+PLAT_INCLUDES += -Iplat/xilinx/zynqmp/include/
+
+PLAT_SOURCES := drivers/arm/gic/arm_gic_v2.c \
+ drivers/arm/gic/gic_common.c \
+ drivers/arm/gic/gic_v2.c \
+ drivers/arm/timer/private_timer.c \
+ drivers/cadence/uart/aarch64/cdns_console.S \
+ plat/xilinx/zynqmp/aarch64/plat_helpers.S \
+ plat/xilinx/zynqmp/zynqmp_pwr_state.c \
+ plat/xilinx/zynqmp/zynqmp_topology.c \
+ plat/xilinx/zynqmp/zynqmp_setup.c \
+ ${XLNX_COMMON_PATH}/timer/timers.c
+
+PLAT_TESTS_SKIP_LIST := plat/xilinx/zynqmp/tests_to_skip.txt
+
+TFTF_CFLAGS += -Wno-maybe-uninitialized -Wno-unused-variable
+
+ENABLE_ASSERTIONS := 1
+
+PLAT_SUPPORTS_NS_RESET := 1
+
+# Process PLAT_SUPPORTS_NS_RESET flag
+$(eval $(call assert_boolean,PLAT_SUPPORTS_NS_RESET))
+$(eval $(call add_define,TFTF_DEFINES,PLAT_SUPPORTS_NS_RESET))
+
+ifeq ($(USE_NVM),1)
+$(error "zynqmp port of TFTF doesn't currently support USE_NVM=1")
+endif
diff --git a/plat/xilinx/zynqmp/tests_to_skip.txt b/plat/xilinx/zynqmp/tests_to_skip.txt
new file mode 100644
index 0000000..9c32ae2
--- /dev/null
+++ b/plat/xilinx/zynqmp/tests_to_skip.txt
@@ -0,0 +1,65 @@
+#
+# Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+################################################################################
+# Disable the listed tests for zynqmp platform
+################################################################################
+#TESTS: tftf-validation
+Framework Validation/IRQ handling
+Framework Validation/Events API
+
+#TESTS: Timer framework Validation
+Timer framework Validation/Target timer to a power down cpu
+Timer framework Validation/Test scenario where multiple CPUs call same timeout
+Timer framework Validation/Stress test the timer framework
+
+#TESTS: Boot requirement tests
+Boot requirement tests
+
+#TESTS: CPU Hotplug/
+CPU Hotplug
+
+#TESTS: PSCI System Suspend Validation
+PSCI System Suspend Validation
+
+#TESTS: psci
+PSCI Affinity Info/Affinity info level0 powerdown
+PSCI CPU Suspend/CPU suspend to powerdown at level 0
+PSCI CPU Suspend/CPU suspend to powerdown at level 1
+PSCI CPU Suspend/CPU suspend to powerdown at level 2
+PSCI CPU Suspend/CPU suspend to standby at level 0
+PSCI CPU Suspend/CPU suspend to standby at level 1
+PSCI CPU Suspend/CPU suspend to standby at level 2
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 0 in OSI mode
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 1 in OSI mode
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 2 in OSI mode
+PSCI CPU Suspend in OSI mode/CPU suspend to powerdown at level 3 in OSI mode
+PSCI CPU Suspend in OSI mode/CPU suspend to standby at level 0 in OSI mode
+PSCI CPU Suspend in OSI mode/CPU suspend to standby at level 1 in OSI mode
+PSCI CPU Suspend in OSI mode/CPU suspend to standby at level 2 in OSI mode
+PSCI System Suspend Validation/System suspend multiple times
+PSCI System Suspend Validation/system suspend from all cores
+PSCI System Suspend Validation/Validate suspend to RAM functionality
+
+#TESTS: psci stat
+PSCI STAT/Stats test cases for CPU OFF
+PSCI STAT/Stats test cases after system suspend
+
+#TESTS: el3-power-state
+EL3 power state parser validation
+
+#TESTS: SIMD
+SIMD,SVE Registers context/Check that SIMD registers context is preserved
+
+#TESTS: psci-extensive
+PSCI CPU ON OFF Stress Tests/Repeated shutdown of all cores to stress test CPU_ON, CPU_SUSPEND and CPU_OFF
+PSCI CPU ON OFF Stress Tests/PSCI CPU ON OFF stress test
+PSCI CPU ON OFF Stress Tests/Repeated hotplug of all cores to stress test CPU_ON and CPU_OFF
+PSCI CPU ON OFF Stress Tests/Random hotplug cores in a large iteration to stress boot path code
+
+#TESTS: SDEI
+SDEI
diff --git a/plat/xilinx/zynqmp/zynqmp_pwr_state.c b/plat/xilinx/zynqmp/zynqmp_pwr_state.c
new file mode 100644
index 0000000..4f3bc4b
--- /dev/null
+++ b/plat/xilinx/zynqmp/zynqmp_pwr_state.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <arch.h>
+#include <platform.h>
+#include <psci.h>
+
+/*
+ * State IDs for local power states.
+ */
+#define ZYNQMP_RETENTION_STATE_ID 1 /* Valid for only CPUs */
+#define ZYNQMP_OFF_STATE_ID 0 /* Valid for CPUs and Clusters */
+
+/*
+ * Suspend depth definitions for each power state
+ */
+typedef enum {
+ ZYNQMP_RUN_DEPTH = 0,
+ ZYNQMP_RETENTION_DEPTH,
+ ZYNQMP_OFF_DEPTH,
+} suspend_depth_t;
+
+/* The state property array with details of idle state possible for the core */
+static const plat_state_prop_t core_state_prop[] = {
+ {ZYNQMP_RETENTION_DEPTH, ZYNQMP_RETENTION_STATE_ID, PSTATE_TYPE_STANDBY},
+ {ZYNQMP_OFF_DEPTH, ZYNQMP_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+/* The state property array with details of idle state possible for the cluster */
+static const plat_state_prop_t cluster_state_prop[] = {
+ {ZYNQMP_OFF_DEPTH, ZYNQMP_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+/* The state property array with details of idle state possible for the system level */
+static const plat_state_prop_t system_state_prop[] = {
+ {ZYNQMP_OFF_DEPTH, ZYNQMP_OFF_STATE_ID, PSTATE_TYPE_POWERDOWN},
+ {0},
+};
+
+const plat_state_prop_t *plat_get_state_prop(unsigned int level)
+{
+ switch (level) {
+ case MPIDR_AFFLVL0:
+ return core_state_prop;
+ case MPIDR_AFFLVL1:
+ return cluster_state_prop;
+ case MPIDR_AFFLVL2:
+ return system_state_prop;
+ default:
+ return NULL;
+ }
+}
diff --git a/plat/xilinx/zynqmp/zynqmp_setup.c b/plat/xilinx/zynqmp/zynqmp_setup.c
new file mode 100644
index 0000000..4a7d371
--- /dev/null
+++ b/plat/xilinx/zynqmp/zynqmp_setup.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/console.h>
+#include <drivers/arm/gic_common.h>
+#include <drivers/arm/gic_v2.h>
+#include <platform.h>
+#include <platform_def.h>
+#include <xlat_tables_v2.h>
+#include <drivers/console.h>
+#include <debug.h>
+#include <drivers/arm/arm_gic.h>
+
+static const mmap_region_t zynqmp_mmap[] = {
+ MAP_REGION_FLAT(DRAM_BASE + TFTF_NVM_OFFSET, TFTF_NVM_SIZE, MT_MEMORY | MT_RW | MT_NS),
+ MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(ZYNQMP_UART_BASE, CRASH_CONSOLE_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(TTC_BASE, TTC_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ MAP_REGION_FLAT(LPD_IOU_SLCR, LPD_IOU_SLCR_SIZE, MT_DEVICE | MT_RW | MT_NS),
+ {0}
+};
+
+const mmap_region_t *tftf_platform_get_mmap(void)
+{
+ return zynqmp_mmap;
+}
+
+void tftf_plat_arch_setup(void)
+{
+ tftf_plat_configure_mmu();
+}
+
+void tftf_early_platform_setup(void)
+{
+ console_init(ZYNQMP_UART_BASE, ZYNQMP_CRASH_UART_CLK_IN_HZ,
+ ZYNQMP_UART_BAUDRATE);
+}
+
+void plat_arm_gic_init(void)
+{
+ arm_gic_init(BASE_GICC_BASE, BASE_GICD_BASE, 0);
+}
+
+void tftf_platform_setup(void)
+{
+ plat_arm_gic_init();
+ arm_gic_setup_global();
+ arm_gic_setup_local();
+}
diff --git a/plat/xilinx/zynqmp/zynqmp_topology.c b/plat/xilinx/zynqmp/zynqmp_topology.c
new file mode 100644
index 0000000..f8262a8
--- /dev/null
+++ b/plat/xilinx/zynqmp/zynqmp_topology.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <assert.h>
+#include <mmio.h>
+#include <plat_topology.h>
+#include <platform_def.h>
+#include <stddef.h>
+#include <tftf_lib.h>
+
+static const struct {
+ unsigned int cluster_id;
+ unsigned int cpu_id;
+} zynqmp_cores[PLATFORM_CORE_COUNT] = {
+ { 0, 0 },
+ { 0, 1 },
+ { 0, 2 },
+ { 0, 3 }
+};
+
+static const unsigned char zynqmp_power_domain_tree_desc[] = {
+ /* Number of root nodes */
+ PLATFORM_SYSTEM_COUNT,
+ /* Number of children of root node */
+ PLATFORM_CLUSTER_COUNT,
+ /* Number of children for the cluster */
+ PLATFORM_CORES_PER_CLUSTER
+};
+
+const unsigned char *tftf_plat_get_pwr_domain_tree_desc(void)
+{
+ return zynqmp_power_domain_tree_desc;
+}
+
+uint64_t tftf_plat_get_mpidr(unsigned int core_pos)
+{
+ assert(core_pos < PLATFORM_CORE_COUNT);
+
+ return make_mpid(zynqmp_cores[core_pos].cluster_id,
+ zynqmp_cores[core_pos].cpu_id);
+}
diff --git a/realm/realm_pauth.c b/realm/realm_pauth.c
index cf3bec3..31b26e7 100644
--- a/realm/realm_pauth.c
+++ b/realm/realm_pauth.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -7,12 +7,15 @@
#include <stdio.h>
#include <arch_features.h>
+#include <assert.h>
#include <debug.h>
#include <pauth.h>
#include <realm_rsi.h>
#include <sync.h>
-static volatile bool set_cmd_done;
+static volatile bool set_cmd_done[MAX_REC_COUNT];
+static uint128_t pauth_keys_before[MAX_REC_COUNT][NUM_KEYS];
+static uint128_t pauth_keys_after[MAX_REC_COUNT][NUM_KEYS];
static bool exception_handler(void)
{
@@ -68,19 +71,28 @@
*/
bool test_realm_pauth_set_cmd(void)
{
+ unsigned int rec = read_mpidr_el1() & MPID_MASK;
+
if (!is_armv8_3_pauth_present()) {
return false;
}
+ assert(rec < MAX_REC_COUNT);
pauth_test_lib_test_intrs();
- pauth_test_lib_fill_regs_and_template();
- set_cmd_done = true;
+ pauth_test_lib_fill_regs_and_template(pauth_keys_before[rec]);
+ set_cmd_done[rec] = true;
return true;
}
bool test_realm_pauth_check_cmd(void)
{
- if (!is_armv8_3_pauth_present() || !set_cmd_done) {
+ unsigned int rec = read_mpidr_el1() & MPID_MASK;
+ bool ret;
+
+ assert(rec < MAX_REC_COUNT);
+ if (!is_armv8_3_pauth_present() || !set_cmd_done[rec]) {
return false;
}
- return pauth_test_lib_compare_template();
+ ret = pauth_test_lib_compare_template(pauth_keys_before[rec], pauth_keys_after[rec]);
+ realm_printf("Pauth key comparison ret=%d\n", ret);
+ return ret;
}
diff --git a/realm/realm_payload_main.c b/realm/realm_payload_main.c
index 93e2404..ce25f43 100644
--- a/realm/realm_payload_main.c
+++ b/realm/realm_payload_main.c
@@ -130,6 +130,20 @@
return false;
}
+bool test_realm_dit_check_cmd(void)
+{
+ if (is_armv8_4_dit_present()) {
+ write_dit(DIT_BIT);
+ realm_printf("Testing DIT=0x%lx\n", read_dit());
+ /* Test if DIT is preserved after HOST_CALL */
+ if (read_dit() == DIT_BIT) {
+ return true;
+ }
+ }
+ return false;
+}
+
+
static bool test_realm_instr_fetch_cmd(void)
{
u_register_t base;
@@ -229,6 +243,9 @@
case REALM_PAUTH_FAULT:
test_succeed = test_realm_pauth_fault();
break;
+ case REALM_DIT_CHECK_CMD:
+ test_succeed = test_realm_dit_check_cmd();
+ break;
case REALM_GET_RSI_VERSION:
test_succeed = realm_get_rsi_version();
break;
diff --git a/tftf/tests/extensions/pauth/test_pauth.c b/tftf/tests/extensions/pauth/test_pauth.c
index b29e5d0..ada2f1d 100644
--- a/tftf/tests/extensions/pauth/test_pauth.c
+++ b/tftf/tests/extensions/pauth/test_pauth.c
@@ -13,6 +13,11 @@
#include <tsp.h>
#include <string.h>
+#ifdef __aarch64__
+static uint128_t pauth_keys_before[NUM_KEYS];
+static uint128_t pauth_keys_after[NUM_KEYS];
+#endif
+
/*
* TF-A is expected to allow access to key registers from lower EL's,
* reading the keys excercises this, on failure this will trap to
@@ -23,7 +28,7 @@
SKIP_TEST_IF_AARCH32();
#ifdef __aarch64__
SKIP_TEST_IF_PAUTH_NOT_SUPPORTED();
- pauth_test_lib_read_keys();
+ pauth_test_lib_read_keys(pauth_keys_before);
return TEST_RESULT_SUCCESS;
#endif /* __aarch64__ */
}
@@ -37,11 +42,11 @@
SKIP_TEST_IF_AARCH32();
#ifdef __aarch64__
SKIP_TEST_IF_PAUTH_NOT_SUPPORTED();
- pauth_test_lib_read_keys();
+ pauth_test_lib_read_keys(pauth_keys_before);
tftf_get_psci_version();
- return pauth_test_lib_compare_template();
+ return pauth_test_lib_compare_template(pauth_keys_before, pauth_keys_after);
#endif /* __aarch64__ */
}
@@ -84,7 +89,7 @@
SKIP_TEST_IF_PAUTH_NOT_SUPPORTED();
SKIP_TEST_IF_TSP_NOT_PRESENT();
- pauth_test_lib_fill_regs_and_template();
+ pauth_test_lib_fill_regs_and_template(pauth_keys_before);
/* Standard SMC to ADD two numbers */
tsp_svc_params.fid = TSP_STD_FID(TSP_ADD);
@@ -106,6 +111,6 @@
return TEST_RESULT_FAIL;
}
- return pauth_test_lib_compare_template();
+ return pauth_test_lib_compare_template(pauth_keys_before, pauth_keys_after);
#endif /* __aarch64__ */
}
diff --git a/tftf/tests/misc_tests/test_undef_injection.c b/tftf/tests/misc_tests/test_undef_injection.c
new file mode 100644
index 0000000..2d925a2
--- /dev/null
+++ b/tftf/tests/misc_tests/test_undef_injection.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2023, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <arm_arch_svc.h>
+#include <assert.h>
+#include <debug.h>
+#include <smccc.h>
+#include <sync.h>
+#include <tftf_lib.h>
+#include <platform_def.h>
+
+static volatile bool undef_injection_triggered;
+
+static bool undef_injection_handler(void)
+{
+ uint64_t esr_el2 = read_esr_el2();
+ if (EC_BITS(esr_el2) == EC_UNKNOWN) {
+ VERBOSE("UNDEF injection from EL3\n");
+ undef_injection_triggered = true;
+ return true;
+ }
+
+ return false;
+}
+
+/*
+ * Test to verify UNDEF injection support in TF-A
+ *
+ * This test tries to access FGT EL2 registers which traps to EL3 and then
+ * the error is injected back from EL3 to TFTF to ensure that injection
+ * logic in TF-A is working, it also ensures that EL3 is still functional
+ * after UNDEF injection.
+ *
+ * To trap FGT register access to EL3, we run this test on a model with
+ * FEAT_FGT present but the traps from EL3 are not disabled by setting
+ * ENABLE_FEAT_FGT = 0
+ */
+test_result_t test_undef_injection(void)
+{
+ undef_injection_triggered = false;
+
+ register_custom_sync_exception_handler(undef_injection_handler);
+
+ /* Try to access a register which traps to EL3 */
+ read_hfgitr_el2();
+
+ unregister_custom_sync_exception_handler();
+
+ /* Ensure that EL3 still functional */
+ smc_args args;
+ smc_ret_values smc_ret;
+ memset(&args, 0, sizeof(args));
+ args.fid = SMCCC_VERSION;
+ smc_ret = tftf_smc(&args);
+
+ tftf_testcase_printf("SMCCC Version = %d.%d\n",
+ (int)((smc_ret.ret0 >> SMCCC_VERSION_MAJOR_SHIFT) & SMCCC_VERSION_MAJOR_MASK),
+ (int)((smc_ret.ret0 >> SMCCC_VERSION_MINOR_SHIFT) & SMCCC_VERSION_MINOR_MASK));
+
+ if (undef_injection_triggered == false) {
+ return TEST_RESULT_FAIL;
+ }
+
+ return TEST_RESULT_SUCCESS;
+}
diff --git a/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c b/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c
index a424b09..682a699 100644
--- a/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c
+++ b/tftf/tests/runtime_services/host_realm_managment/host_realm_helper.c
@@ -215,6 +215,18 @@
}
}
+ /*
+ * At the moment, TFTF does not have support for FEAT_LPA2, so if
+ * S2SZ is larger than 48 bits, truncate it to ensure we don't surpass
+ * the maximum IPA size for a realm with no LPA2 support.
+ */
+ if (EXTRACT(RMI_FEATURE_REGISTER_0_S2SZ, realm_ptr->rmm_feat_reg0) > 48U) {
+ realm_ptr->rmm_feat_reg0 &=
+ ~MASK(RMI_FEATURE_REGISTER_0_S2SZ);
+ realm_ptr->rmm_feat_reg0 |=
+ INPLACE(RMI_FEATURE_REGISTER_0_S2SZ, 48U);
+ }
+
/* Create Realm */
if (host_realm_create(realm_ptr) != REALM_SUCCESS) {
ERROR("%s() failed\n", "host_realm_create");
diff --git a/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c b/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c
index 175dc04..ff69869 100644
--- a/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c
+++ b/tftf/tests/runtime_services/realm_payload/host_realm_payload_tests.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,6 +25,11 @@
extern const char *rmi_exit[];
+#if ENABLE_PAUTH
+static uint128_t pauth_keys_before[NUM_KEYS];
+static uint128_t pauth_keys_after[NUM_KEYS];
+#endif
+
/*
* @Test_Aim@ Test realm payload creation, execution and destruction iteratively
*/
@@ -97,7 +102,8 @@
}
/*
- * @Test_Aim@ Test PAuth in realm
+ * @Test_Aim@ Create realm with multiple rec
+ * Test PAuth registers are preserved for each rec
*/
test_result_t host_realm_enable_pauth(void)
{
@@ -105,16 +111,17 @@
return TEST_RESULT_SKIPPED;
#else
bool ret1, ret2;
- u_register_t rec_flag[1] = {RMI_RUNNABLE};
+ u_register_t rec_flag[MAX_REC_COUNT] = {RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE,
+ RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE,};
struct realm realm;
SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
- pauth_test_lib_fill_regs_and_template();
+ pauth_test_lib_fill_regs_and_template(pauth_keys_before);
if (!host_create_activate_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
(u_register_t)PAGE_POOL_BASE,
(u_register_t)PAGE_POOL_MAX_SIZE,
- 0UL, rec_flag, 1U)) {
+ 0UL, rec_flag, MAX_REC_COUNT)) {
return TEST_RESULT_FAIL;
}
@@ -123,24 +130,33 @@
return TEST_RESULT_FAIL;
}
- ret1 = host_enter_realm_execute(&realm, REALM_PAUTH_SET_CMD, RMI_EXIT_HOST_CALL, 0U);
+ for (unsigned int i = 0U; i < MAX_REC_COUNT; i++) {
+ ret1 = host_enter_realm_execute(&realm, REALM_PAUTH_SET_CMD,
+ RMI_EXIT_HOST_CALL, i);
- if (ret1) {
+ if (!ret1) {
+ ERROR("Pauth set cmd failed\n");
+ break;
+ }
/* Re-enter Realm to compare PAuth registers. */
ret1 = host_enter_realm_execute(&realm, REALM_PAUTH_CHECK_CMD,
- RMI_EXIT_HOST_CALL, 0U);
+ RMI_EXIT_HOST_CALL, i);
+ if (!ret1) {
+ ERROR("Pauth check cmd failed\n");
+ break;
+ }
}
ret2 = host_destroy_realm(&realm);
- if (!ret1) {
+ if (!ret1 || !ret2) {
ERROR("%s(): enter=%d destroy=%d\n",
__func__, ret1, ret2);
return TEST_RESULT_FAIL;
}
/* Check if PAuth keys are preserved. */
- if (!pauth_test_lib_compare_template()) {
+ if (!pauth_test_lib_compare_template(pauth_keys_before, pauth_keys_after)) {
ERROR("%s(): NS PAuth keys not preserved\n",
__func__);
return TEST_RESULT_FAIL;
@@ -1205,3 +1221,55 @@
return res;
}
+
+/*
+ * @Test_Aim@ Test to check if DIT bit is preserved across NS/RL switch
+ */
+test_result_t host_realm_enable_dit(void)
+{
+ bool ret1, ret2;
+ struct realm realm;
+ u_register_t rec_flag[] = {RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE,
+ RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE, RMI_RUNNABLE}, dit;
+
+ SKIP_TEST_IF_RME_NOT_SUPPORTED_OR_RMM_IS_TRP();
+
+ if (!host_create_activate_realm_payload(&realm, (u_register_t)REALM_IMAGE_BASE,
+ (u_register_t)PAGE_POOL_BASE,
+ (u_register_t)PAGE_POOL_MAX_SIZE,
+ 0UL, rec_flag, MAX_REC_COUNT)) {
+ return TEST_RESULT_FAIL;
+ }
+ if (!host_create_shared_mem(&realm, NS_REALM_SHARED_MEM_BASE,
+ NS_REALM_SHARED_MEM_SIZE)) {
+ return TEST_RESULT_FAIL;
+ }
+
+ /* Enable FEAT_DIT on Host */
+ write_dit(DIT_BIT);
+ for (unsigned int i = 0; i < MAX_REC_COUNT; i++) {
+ host_shared_data_set_host_val(&realm, i, HOST_ARG1_INDEX, 10U);
+ ret1 = host_enter_realm_execute(&realm, REALM_DIT_CHECK_CMD,
+ RMI_EXIT_HOST_CALL, i);
+ if (!ret1) {
+ break;
+ }
+ }
+
+ ret2 = host_destroy_realm(&realm);
+
+ dit = read_dit();
+ if (dit != DIT_BIT) {
+ ERROR("Host DIT bit not preserved\n");
+ return TEST_RESULT_FAIL;
+ }
+
+ write_dit(0U);
+ if (!ret1 || !ret2) {
+ ERROR("%s(): enter=%d destroy=%d\n",
+ __func__, ret1, ret2);
+ return TEST_RESULT_FAIL;
+ }
+
+ return TEST_RESULT_SUCCESS;
+}
diff --git a/tftf/tests/runtime_services/standard_service/errata_abi/api_tests/test_errata_abi_functionality.c b/tftf/tests/runtime_services/standard_service/errata_abi/api_tests/test_errata_abi_functionality.c
index 4619b20..0baf471 100644
--- a/tftf/tests/runtime_services/standard_service/errata_abi/api_tests/test_errata_abi_functionality.c
+++ b/tftf/tests/runtime_services/standard_service/errata_abi/api_tests/test_errata_abi_functionality.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -129,7 +129,9 @@
.cpu_pn = 0xD08,
.cpu_errata = {
{859971, 0x00, 0x03},
+ {1234567, 0x00, 0xFF},
{1319367, 0x00, 0xFF},
+ {9876543, 0x00, 0xFF},
{-1}
},
};
@@ -163,9 +165,11 @@
{1262606, 0x00, 0x30},
{1262888, 0x00, 0x30},
{1275112, 0x00, 0x30},
+ {1286807, 0x00, 0x30},
{1791580, 0x00, 0x40},
{1868343, 0x00, 0x40},
{1946160, 0x30, 0x41},
+ {2743102, 0x00, 0x41},
{-1}
},
};
@@ -188,10 +192,10 @@
.cpu_pn = 0xD42,
.cpu_errata = {
{1941500, 0x00, 0x01},
+ {1951502, 0x00, 0x01},
{2376748, 0x00, 0x01},
{2712574, 0x00, 0x02},
- {2376748, 0x00, 0x01},
- {1951502, 0x00, 0x01},
+ {2395408, 0x00, 0x01},
{-1}
},
};
@@ -219,11 +223,15 @@
em_cpu_t cortex_A78C_errata_list = {
.cpu_pn = 0xD4B,
.cpu_errata = {
+ {1827430, 0x00, 0x00},
+ {1827440, 0x00, 0x00},
{2132064, 0x01, 0x02},
{2242638, 0x01, 0x02},
{2376749, 0x01, 0x02},
{2395411, 0x01, 0x02},
+ {2683027, 0x01, 0x02},
{2712575, 0x01, 0x02},
+ {2743232, 0x01, 0x02},
{2772121, 0x00, 0x02},
{2779484, 0x01, 0x02},
{-1}
@@ -245,6 +253,7 @@
em_cpu_t neoverse_N1_errata_list = {
.cpu_pn = 0xD0C,
.cpu_errata = {
+ {1043202, 0x00, 0x10},
{1073348, 0x00, 0x10},
{1130799, 0x00, 0x20},
{1165347, 0x00, 0x20},
@@ -277,9 +286,11 @@
{2139242, 0x00, 0x11},
{2216392, 0x10, 0x11},
{2294912, 0x00, 0x11},
+ {2348377, 0x00, 0x11},
{2372203, 0x00, 0x11},
{2701953, 0x00, 0x11},
{2743093, 0x00, 0x12},
+ {2743233, 0x00, 0x12},
{2779461, 0x00, 0x12},
{-1}
},
@@ -303,7 +314,9 @@
{2291219, 0x00, 0x20},
{2371105, 0x00, 0x20},
{2701952, 0x00, 0x21},
+ {2742423, 0x00, 0x21},
{2768515, 0x00, 0x21},
+ {2778471, 0x00, 0x21},
{-1}
},
};
@@ -326,6 +339,7 @@
{2388450, 0x00, 0x00},
{2728475, 0x00, 0x02},
{2743089, 0x00, 0x02},
+ {2779511, 0x00, 0x02},
{-1}
},
};
@@ -343,7 +357,9 @@
{2282622, 0x00, 0x21},
{2371105, 0x00, 0x21},
{2701952, 0x00, 0x21},
+ {2742423, 0x00, 0x21},
{2768515, 0x00, 0x21},
+ {2778471, 0x00, 0x21},
{-1}
},
};
@@ -354,6 +370,7 @@
{1922240, 0x00, 0x00},
{2041909, 0x02, 0x02},
{2042739, 0x00, 0x02},
+ {2080326, 0x02, 0x02},
{2172148, 0x00, 0x10},
{2218950, 0x00, 0x10},
{2250311, 0x00, 0x10},
@@ -367,10 +384,18 @@
},
};
+em_cpu_t cortex_X4_errata_list = {
+ .cpu_pn = 0xD82,
+ .cpu_errata = {
+ {2701112, 0x00, 0x00},
+ {-1}
+ },
+};
+
em_cpu_t cortex_A715_errata_list = {
.cpu_pn = 0xD4D,
.cpu_errata = {
- {2701951, 0x00, 0x11},
+ {2561034, 0x10, 0x10},
{-1}
},
};
@@ -378,7 +403,41 @@
em_cpu_t neoverse_V2_errata_list = {
.cpu_pn = 0xD4F,
.cpu_errata = {
+ {2331132, 0x00, 0x02},
+ {2618597, 0x00, 0x01},
+ {2662553, 0x00, 0x01},
{2719103, 0x00, 0x01},
+ {2719103, 0x00, 0x01},
+ {2719105, 0x00, 0x01},
+ {2743011, 0x00, 0x01},
+ {2779510, 0x00, 0x01},
+ {2801372, 0x00, 0x01},
+ {-1}
+ },
+};
+
+em_cpu_t cortex_X3_errata_list = {
+ .cpu_pn = 0xD4E,
+ .cpu_errata = {
+ {2070301, 0x00, 0x12},
+ {2266875, 0x00, 0x10},
+ {2302506, 0x00, 0x11},
+ {2313909, 0x00, 0x10},
+ {2615812, 0x00, 0x11},
+ {2641945, 0x00, 0x10},
+ {2701951, 0x00, 0x11},
+ {2742421, 0x00, 0x11},
+ {2743088, 0x00, 0x11},
+ {2779509, 0x00, 0x11},
+ {-1}
+ },
+};
+
+em_cpu_t cortex_A520_errata_list = {
+ .cpu_pn = 0xD80,
+ .cpu_errata = {
+ {2630792, 0x00, 0x01},
+ {2858100, 0x00, 0x01},
{-1}
},
};
@@ -544,28 +603,46 @@
}
case 0xD44:
{
- VERBOSE("MIDR matches X1 > %x\n", midr_val);
+ VERBOSE("MIDR matches X1 -> %x\n", midr_val);
cpu_ptr = &cortex_X1_errata_list;
break;
}
case 0xD0A:
{
- VERBOSE("MIDR matches A75 > %x\n", midr_val);
+ VERBOSE("MIDR matches A75 -> %x\n", midr_val);
cpu_ptr = &cortex_A75_errata_list;
break;
}
case 0xD05:
{
- VERBOSE("MIDR matches A55 > %x\n", midr_val);
+ VERBOSE("MIDR matches A55 -> %x\n", midr_val);
cpu_ptr = &cortex_A55_errata_list;
break;
}
case 0xD42:
{
- VERBOSE("MIDR matches A78_AE > %x\n", midr_val);
+ VERBOSE("MIDR matches A78_AE -> %x\n", midr_val);
cpu_ptr = &cortex_A78_AE_errata_list;
break;
}
+ case 0xD82:
+ {
+ VERBOSE("MIDR matches Cortex-X4 -> %x\n", midr_val);
+ cpu_ptr = &cortex_X4_errata_list;
+ break;
+ }
+ case 0xD4E:
+ {
+ VERBOSE("MIDR matches Cortex-X3 -> %x\n", midr_val);
+ cpu_ptr = &cortex_X3_errata_list;
+ break;
+ }
+ case 0xD80:
+ {
+ VERBOSE("MIDR matches A520 -> %x\n", midr_val);
+ cpu_ptr = &cortex_A520_errata_list;
+ break;
+ }
default:
{
ERROR("MIDR did not match any cpu\n");
diff --git a/tftf/tests/runtime_services/standard_service/sdei/system_tests/test_sdei_pstate.c b/tftf/tests/runtime_services/standard_service/sdei/system_tests/test_sdei_pstate.c
index 024352e..339e4ba 100644
--- a/tftf/tests/runtime_services/standard_service/sdei/system_tests/test_sdei_pstate.c
+++ b/tftf/tests/runtime_services/standard_service/sdei/system_tests/test_sdei_pstate.c
@@ -100,111 +100,81 @@
if (is_armv8_1_pan_present()) {
printf("PAN Enabled so testing PAN PSTATE bit\n");
+
+ /* Test that the SPAN condition is met.
+ * Unset the SPAN bit
+ */
+ u_register_t old_sctlr = read_sctlr_el2();
+
+ write_sctlr_el2(old_sctlr & ~SCTLR_SPAN_BIT);
+
+ u_register_t old_hcr_el2 = read_hcr_el2();
+
/*
* Check that when the SPAN bit is 0
* the PAN PSTATE bit is maintained
*/
- /* When PAN bit is 0 */
- u_register_t expected_pan = 0;
+ if ((old_hcr_el2 & HCR_TGE_BIT) == 0U) {
+ /*
+ * Check that when the HCR_EL2.TGE != 1
+ * the PAN bit is maintained
+ */
- write_pan(expected_pan);
- ret = sdei_event_signal(read_mpidr_el1());
- if (ret < 0) {
- tftf_testcase_printf("SDEI event signal failed: " \
- "0x%llx\n", ret);
- goto err2;
- }
- sdei_handler_done();
- if (pan != expected_pan) {
- tftf_testcase_printf("PAN PSTATE bit not maintained " \
- "during SDEI event signal\n" \
- "Expected PAN: 0x%lx, " \
- "Actual PAN: 0x%lx\n",
- expected_pan, pan);
- ret = -1;
- goto err1;
- }
+ /* When PAN bit is 0 */
+ u_register_t expected_pan = 0;
+ write_pan(expected_pan);
- /* When PAN bit is 1 */
- expected_pan = PAN_BIT;
- write_pan(expected_pan);
- ret = sdei_event_signal(read_mpidr_el1());
- if (ret < 0) {
- tftf_testcase_printf("SDEI event signal failed: " \
- "0x%llx\n", ret);
- goto err2;
- }
- sdei_handler_done();
- if (pan != expected_pan) {
- tftf_testcase_printf("PAN PSTATE bit not maintained " \
- "during SDEI event signal\n" \
- "Expected PAN: 0x%lx, " \
- "Actual PAN: 0x%lx\n",
- expected_pan, pan);
- ret = -1;
- goto err1;
- }
+ ret = sdei_event_signal(read_mpidr_el1());
+ if (ret < 0) {
+ tftf_testcase_printf("SDEI event signal failed: " \
+ "0x%llx\n", ret);
+ goto err2;
+ }
+ sdei_handler_done();
+ if (pan != expected_pan) {
+ tftf_testcase_printf("PAN PSTATE bit not maintained" \
+ "during SDEI event signal " \
+ "when the SPAN bit is unset and " \
+ "HCR_EL2.TGE != 1 \n" \
+ "Expected PAN: 0x%lx, " \
+ "Actual PAN: 0x%lx\n",
+ expected_pan, pan);
+ ret = -1;
+ goto err1;
+ }
- /* Test that the SPAN condition is met */
- /* Set the SPAN bit */
- u_register_t old_sctlr = read_sctlr_el2();
+ /* When PAN Bit is 1 */
+ expected_pan = PAN_BIT;
+ write_pan(expected_pan);
+ ret = sdei_event_signal(read_mpidr_el1());
+ if (ret < 0) {
+ tftf_testcase_printf("SDEI event signal failed: " \
+ "0x%llx\n", ret);
+ goto err2;
+ }
+ sdei_handler_done();
+ if (pan != expected_pan) {
+ tftf_testcase_printf("PAN PSTATE bit not maintained" \
+ "during SDEI event signal " \
+ "when the SPAN bit is unset and " \
+ "HCR_EL2.TGE != 1 \n" \
+ "Expected PAN: 0x%lx, " \
+ "Actual PAN: 0x%lx\n",
+ expected_pan, pan);
+ ret = -1;
+ goto err1;
+ }
- write_sctlr_el2(old_sctlr & ~SCTLR_SPAN_BIT);
-
- expected_pan = 0;
- /*
- * Check that when the HCR_EL2.{E2H, TGE} != {1, 1}
- * the PAN bit is maintained
- */
- ret = sdei_event_signal(read_mpidr_el1());
- if (ret < 0) {
- tftf_testcase_printf("SDEI event signal failed: " \
- "0x%llx\n", ret);
- goto err2;
- }
- sdei_handler_done();
- if (pan != expected_pan) {
- tftf_testcase_printf("PAN PSTATE bit not maintained " \
- "during SDEI event signal " \
- "when the SPAN bit is set and " \
- "HCR_EL2.{E2H, TGE} != {1, 1}\n" \
- "Expected PAN: 0x%lx, " \
- "Actual PAN: 0x%lx\n",
- expected_pan, pan);
- ret = -1;
- goto err1;
- }
-
- expected_pan = PAN_BIT;
- write_pan(expected_pan);
- ret = sdei_event_signal(read_mpidr_el1());
- if (ret < 0) {
- tftf_testcase_printf("SDEI event signal failed: " \
- "0x%llx\n", ret);
- goto err2;
- }
- sdei_handler_done();
- if (pan != expected_pan) {
- tftf_testcase_printf("PAN PSTATE bit not maintained " \
- "during SDEI event signal " \
- "when the SPAN bit is set and " \
- "HCR_EL2.{E2H, TGE} != {1, 1}\n" \
- "Expected PAN: 0x%lx, " \
- "Actual PAN: 0x%lx\n",
- expected_pan, pan);
- ret = -1;
- goto err1;
}
/*
- * Check that when the HCR_EL2.{E2H, TGE} = {1, 1}
- * PAN bit is forced to 1
+ * Check that when the HCR_EL2.TGE = 1 and SPAN bit is unset,
+ * PAN bit is forced to 1.
+ * Set the TGE bit
*/
- /* Set E2H Bit */
- u_register_t old_hcr_el2 = read_hcr_el2();
- write_hcr_el2(old_hcr_el2 | HCR_E2H_BIT);
+ write_hcr_el2(old_hcr_el2 | HCR_TGE_BIT);
ret = sdei_event_signal(read_mpidr_el1());
if (ret < 0) {
@@ -215,9 +185,9 @@
sdei_handler_done();
if (pan != PAN_BIT) {
tftf_testcase_printf("PAN PSTATE bit was not forced " \
- "to 1 during SDEI event signal " \
- "when the SPAN bit is set and " \
- "HCR_EL2.{E2H, TGE} = {1, 1}\n");
+ "to 1 during SDEI event signal " \
+ "when the SPAN bit is unset and " \
+ "HCR_EL2.TGE = 1 \n");
ret = -1;
goto err1;
}
diff --git a/tftf/tests/tests-extensive.xml b/tftf/tests/tests-extensive.xml
index 5824967..e861b48 100644
--- a/tftf/tests/tests-extensive.xml
+++ b/tftf/tests/tests-extensive.xml
@@ -10,38 +10,12 @@
<!-- External references to all individual tests files. -->
<!DOCTYPE testsuites [
<!ENTITY tests-psci-extensive SYSTEM "tests-psci-extensive.xml">
-
- <!ENTITY tests-tftf-validation SYSTEM "tests-tftf-validation.xml">
- <!ENTITY tests-boot-req SYSTEM "tests-boot-req.xml">
- <!ENTITY tests-psci SYSTEM "tests-psci.xml">
- <!ENTITY tests-sdei SYSTEM "tests-sdei.xml">
- <!ENTITY tests-rt-instr SYSTEM "tests-runtime-instrumentation.xml">
- <!ENTITY tests-tsp SYSTEM "tests-tsp.xml">
- <!ENTITY tests-el3-pstate SYSTEM "tests-el3-power-state.xml">
- <!ENTITY tests-state-switch SYSTEM "tests-arm-state-switch.xml">
- <!ENTITY tests-cpu-extensions SYSTEM "tests-cpu-extensions.xml">
- <!ENTITY tests-performance SYSTEM "tests-performance.xml">
- <!ENTITY tests-smc SYSTEM "tests-smc.xml">
- <!ENTITY tests-pmu-leakage SYSTEM "tests-pmu-leakage.xml">
<!ENTITY tests-timer-stress SYSTEM "tests-timer-stress.xml">
]>
<testsuites>
&tests-psci-extensive;
-
- &tests-tftf-validation;
- &tests-boot-req;
- &tests-psci;
- &tests-sdei;
- &tests-rt-instr;
- &tests-tsp;
- &tests-el3-pstate;
- &tests-state-switch;
- &tests-cpu-extensions;
- &tests-performance;
- &tests-smc;
- &tests-pmu-leakage;
&tests-timer-stress;
</testsuites>
diff --git a/tftf/tests/tests-realm-payload.xml b/tftf/tests/tests-realm-payload.xml
index 06c4aa7..0ecefee 100644
--- a/tftf/tests/tests-realm-payload.xml
+++ b/tftf/tests/tests-realm-payload.xml
@@ -97,5 +97,7 @@
function="host_realm_enable_pauth" />
<testcase name="Generate PAuth Fault by overwriting LR"
function="host_realm_pauth_fault" />
+ <testcase name="Check if DIT Bit is preserved in RL/NS"
+ function="host_realm_enable_dit" />
</testsuite>
</testsuites>
diff --git a/tftf/tests/tests-undef-injection.mk b/tftf/tests/tests-undef-injection.mk
new file mode 100644
index 0000000..e13df17
--- /dev/null
+++ b/tftf/tests/tests-undef-injection.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+TESTS_SOURCES += tftf/tests/misc_tests/test_undef_injection.c
diff --git a/tftf/tests/tests-undef-injection.xml b/tftf/tests/tests-undef-injection.xml
new file mode 100644
index 0000000..0d43cdf
--- /dev/null
+++ b/tftf/tests/tests-undef-injection.xml
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="utf-8"?>
+
+<!--
+ Copyright (c) 2023, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-3-Clause
+-->
+
+<testsuites>
+ <testsuite name="UNDEF Injection" description="UNDEF injection from EL3 to lower EL">
+ <testcase name="UNDEF Injection to lower EL"
+ function="test_undef_injection" />
+ </testsuite>
+</testsuites>