diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 50cb5f9..d3d884e 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -430,8 +430,6 @@
 #define NV2_IMPLEMENTED			ULL(0x2)
 
 /* ID_AA64MMFR3_EL1 definitions */
-#define ID_AA64MMFR3_EL1			S3_0_C0_C7_3
-
 #define ID_AA64MMFR3_EL1_S2POE_SHIFT		U(20)
 #define ID_AA64MMFR3_EL1_S2POE_MASK		ULL(0xf)
 #define ID_AA64MMFR3_EL1_S2POE_WIDTH		U(4)
@@ -452,12 +450,19 @@
 #define ID_AA64MMFR3_EL1_S1PIE_WIDTH		U(4)
 #define ID_AA64MMFR3_EL1_S1PIE_SUPPORTED	ULL(0x1)
 
+#define ID_AA64MMFR3_EL1_SCTLRX_SHIFT		U(4)
+#define ID_AA64MMFR3_EL1_SCTLRX_WIDTH		ULL(0x4)
+
 #define ID_AA64MMFR3_EL1_TCRX_SHIFT		U(0)
 #define ID_AA64MMFR3_EL1_TCRX_MASK		ULL(0xf)
 #define ID_AA64MMFR3_EL1_TCRX_WIDTH		U(4)
 #define ID_AA64MMFR3_EL1_TCR2_SUPPORTED		ULL(0x1)
 
 /* ID_AA64PFR1_EL1 definitions */
+#define ID_AA64PFR1_EL1_DF2_SHIFT		U(56)
+#define ID_AA64PFR1_EL1_DF2_WIDTH		U(4)
+#define ID_AA64PFR1_EL1_DF2_MASK		(0xf << ID_AA64PFR1_EL1_DF2_SHIFT)
+
 #define ID_AA64PFR1_EL1_GCS_SHIFT		U(44)
 #define ID_AA64PFR1_EL1_GCS_MASK		ULL(0xf)
 #define ID_AA64PFR1_EL1_GCS_WIDTH		U(4)
@@ -484,6 +489,7 @@
 #define ID_AA64PFR1_MPAM_FRAC_SHIFT		U(16)
 #define ID_AA64PFR1_MPAM_FRAC_MASK		ULL(0xf)
 
+#define ID_AA64PFR1_RAS_FRAC_MASK		ULL(0xf)
 #define ID_AA64PFR1_RAS_FRAC_SHIFT		U(12)
 #define ID_AA64PFR1_RAS_FRAC_MASK		ULL(0xf)
 #define ID_AA64PFR1_RAS_FRAC_WIDTH		U(4)
@@ -504,6 +510,9 @@
 #define ID_AA64PFR1_EL1_BT_MASK			ULL(0xf)
 #define BTI_IMPLEMENTED				ULL(1)	/* The BTI mechanism is implemented */
 
+#define ID_AA64PFR1_DF2_SHIFT			U(56)
+#define ID_AA64PFR1_DF2_WIDTH			ULL(0x4)
+
 /* ID_PFR1_EL1 definitions */
 #define ID_PFR1_VIRTEXT_SHIFT	U(12)
 #define ID_PFR1_VIRTEXT_MASK	U(0xf)
@@ -553,6 +562,15 @@
 #define SCTLR_DSSBS_BIT		(ULL(1) << 44)
 #define SCTLR_RESET_VAL		SCTLR_EL3_RES1
 
+/* SCTLR2_EL1 register definitions */
+#define SCTLR2_EL1		S3_0_C1_C0_3
+
+#define SCTLR2_NMEA_BIT		(UL(1) << 2)
+#define SCTLR2_EnADERR_BIT	(UL(1) << 3)
+#define SCTLR2_EnANERR_BIT	(UL(1) << 4)
+#define SCTLR2_EASE_BIT		(UL(1) << 5)
+#define SCTLR2_EnIDCP128_BIT	(UL(1) << 6)
+
 /* CPACR_El1 definitions */
 #define CPACR_EL1_FPEN(x)	((x) << 20)
 #define CPACR_EL1_FP_TRAP_EL0	U(0x1)
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index c7d824a..96d899a 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -525,4 +525,11 @@
 	return EXTRACT(ID_AA64PFR1_EL1_MTE, read_id_aa64pfr1_el1())
 		>= MTE_IMPLEMENTED_ELX;
 }
+
+static inline bool is_feat_double_fault2_present(void)
+{
+	return (EXTRACT(ID_AA64PFR1_EL1_DF2,
+		read_id_aa64pfr1_el1()) == 1UL);
+}
+
 #endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index c906181..a765548 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -322,6 +322,8 @@
 DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
 DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
 
+DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1)
+
 DEFINE_SYSREG_RW_FUNCS(actlr_el1)
 DEFINE_SYSREG_RW_FUNCS(actlr_el2)
 DEFINE_SYSREG_RW_FUNCS(actlr_el3)