feat(afp): add a test for Advanced floating-point
This test is to ensure that TFTF is allowed to write the FPCR register
bits to control the floating-point operation when FEAT_AFP is
implemented.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I21ea288e698bbe706aac55740e28d5f6ccb700dc
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index 0881f00..05ecbb8 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -273,6 +273,14 @@
} \
} while (false)
+#define SKIP_TEST_IF_AFP_NOT_SUPPORTED() \
+ do { \
+ if (!get_feat_afp_present()) { \
+ tftf_testcase_printf("ARMv8.7-afp not supported"); \
+ return TEST_RESULT_SKIPPED; \
+ } \
+ } while (false)
+
/* Helper macro to verify if system suspend API is supported */
#define is_psci_sys_susp_supported() \
(tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND) \
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 75fdfcf..7596026 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -254,6 +254,9 @@
#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
+#define ID_AA64MMFR1_EL1_AFP_SHIFT U(44)
+#define ID_AA64MMFR1_EL1_AFP_MASK ULL(0xf)
+#define ID_AA64MMFR1_EL1_AFP_SUPPORTED ULL(0x1)
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@@ -641,6 +644,13 @@
#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
+/*
+ * FPCR definitions
+ */
+#define FPCR_FIZ_BIT (ULL(1) << 0)
+#define FPCR_AH_BIT (ULL(1) << 1)
+#define FPCR_NEP_BIT (ULL(1) << 2)
+
/* Physical timer control register bit fields shifts and masks */
#define CNTP_CTL_ENABLE_SHIFT U(0)
#define CNTP_CTL_IMASK_SHIFT U(1)
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index a111c2c..b0ec17a 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -142,4 +142,10 @@
ID_AA64MMFR1_EL1_HCX_MASK) == ID_AA64MMFR1_EL1_HCX_SUPPORTED);
}
+static inline bool get_feat_afp_present(void)
+{
+ return (((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_AFP_SHIFT) &
+ ID_AA64MMFR1_EL1_AFP_MASK) == ID_AA64MMFR1_EL1_AFP_SUPPORTED);
+}
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index f42f2f8..eac8b7c 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -544,6 +544,9 @@
/* FEAT_HCX HCRX_EL2 */
DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
+/* Control floating point behaviour */
+DEFINE_RENAME_SYSREG_RW_FUNCS(fpcr, FPCR)
+
#define IS_IN_EL(x) \
(GET_EL(read_CurrentEl()) == MODE_EL##x)