feat(fgt): add support for FEAT_FGT2 testing
This patch adds testcase that validates FEAT_FGT2 support
by reading Fine-grained trap registers that are part of FEAT_FGT2.
These registers are only present when FEAT_FGT2 is implemented
Change-Id: Ifc1106d12dbe03b956310d364600368d3f035491
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index ced1745..33d2db6 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -125,6 +125,15 @@
} \
} while (0)
+#define SKIP_TEST_IF_FGT2_NOT_SUPPORTED() \
+ do { \
+ if (!is_armv8_9_fgt2_present()) { \
+ tftf_testcase_printf( \
+ "Fine Grained Traps 2 not supported\n"); \
+ return TEST_RESULT_SKIPPED; \
+ } \
+ } while (0)
+
#define SKIP_TEST_IF_SVE_NOT_SUPPORTED() \
do { \
if (!is_armv8_2_sve_present()) { \
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index a57b8de..3c30c9d 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -303,6 +303,7 @@
#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
+#define ID_AA64MMFR0_EL1_FGT2_SUPPORTED ULL(0x2)
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
#define ID_AA64MMFR0_EL1_TGRAN4_WIDTH U(4)
@@ -1286,6 +1287,15 @@
#define HDFGWTR_EL2 S3_4_C3_C1_5
/*******************************************************************************
+ * Armv8.9 - Fine Grained Virtualization Traps 2 Registers
+ ******************************************************************************/
+#define HFGRTR2_EL2 S3_4_C3_C1_2
+#define HFGWTR2_EL2 S3_4_C3_C1_3
+#define HFGITR2_EL2 S3_4_C3_C1_7
+#define HDFGRTR2_EL2 S3_4_C3_C1_0
+#define HDFGWTR2_EL2 S3_4_C3_C1_1
+
+/*******************************************************************************
* Armv8.6 - Enhanced Counter Virtualization Registers
******************************************************************************/
#define CNTPOFF_EL2 S3_4_C14_C0_6
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index b6d0ce7..86cbec9 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -126,8 +126,14 @@
static inline bool is_armv8_6_fgt_present(void)
{
+ return (((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
+ ID_AA64MMFR0_EL1_FGT_MASK) != 0U);
+}
+
+static inline bool is_armv8_9_fgt2_present(void)
+{
return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
- ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED;
+ ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT2_SUPPORTED;
}
static inline unsigned long int get_armv8_6_ecv_support(void)
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index a91625c..076a9cd 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -572,6 +572,13 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2)
+/* Armv8.9 Fine Grained Virtualization Traps 2 Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr2_el2, HFGRTR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr2_el2, HFGWTR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr2_el2, HFGITR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr2_el2, HDFGRTR2_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr2_el2, HDFGWTR2_EL2)
+
/* Armv8.6 Enhanced Counter Virtualization Register */
DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2)