feat(cm): add el1-ctx register helper macros
Adding EL1 context registers related helper macros
necessary to test EL1 context entries.
Change-Id: Ifb0149ad78f951958990290b496e7c1b92c072ea
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index a641052..77878e6 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -385,7 +385,6 @@
#define ID_AA64MMFR1_EL1_LOR_NOT_SUPPORTED ULL(0x0)
#define ID_AA64MMFR1_EL1_LOR_SUPPORTED ULL(0x1)
-
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@@ -396,40 +395,49 @@
#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
/* ID_AA64MMFR3_EL1 definitions */
-#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
+#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
-#define ID_AA64MMFR3_TCR2_SHIFT U(0)
-#define ID_AA64MMFR3_TCR2_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20)
+#define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_S2POE_WIDTH U(4)
+#define ID_AA64MMFR3_EL1_S2POE_SUPPORTED ULL(0x1)
+
+#define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16)
+#define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_S1POE_WIDTH U(4)
+#define ID_AA64MMFR3_EL1_S1POE_SUPPORTED ULL(0x1)
+
+#define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12)
+#define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_S2PIE_WIDTH U(4)
+#define ID_AA64MMFR3_EL1_S2PIE_SUPPORTED ULL(0x1)
+
+#define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8)
+#define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_S1PIE_WIDTH U(4)
+#define ID_AA64MMFR3_EL1_S1PIE_SUPPORTED ULL(0x1)
+
+#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
+#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_TCRX_WIDTH U(4)
+#define ID_AA64MMFR3_EL1_TCR2_SUPPORTED ULL(0x1)
/* ID_AA64PFR1_EL1 definitions */
-#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
-#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
+#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_GCS_WIDTH U(4)
+#define ID_AA64PFR1_EL1_GCS_SUPPORTED ULL(1)
-#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
-
-#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
-#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
-
-#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
-
-#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
-#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
-
-#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
-#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK ULL(0xf)
-
-#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
-#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
-
-#define ID_AA64PFR1_CSV2_FRAC_MASK ULL(0xf)
#define ID_AA64PFR1_CSV2_FRAC_SHIFT U(32)
+#define ID_AA64PFR1_CSV2_FRAC_MASK ULL(0xf)
#define ID_AA64PFR1_CSV2_FRAC_WIDTH U(4)
#define ID_AA64PFR1_CSV2_1P1_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_CSV2_1P2_SUPPORTED ULL(0x2)
-#define MTE_UNIMPLEMENTED ULL(0)
-#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
-#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
+#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
+#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
+#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
@@ -438,13 +446,28 @@
#define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1)
#define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2)
-#define ID_AA64PFR1_RAS_FRAC_MASK ULL(0xf)
+#define ID_AA64PFR1_MPAM_FRAC_SHIFT U(16)
+#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
+
#define ID_AA64PFR1_RAS_FRAC_SHIFT U(12)
+#define ID_AA64PFR1_RAS_FRAC_MASK ULL(0xf)
#define ID_AA64PFR1_RAS_FRAC_WIDTH U(4)
#define ID_AA64PFR1_RASV1P1_SUPPORTED ULL(0x1)
-#define ID_AA64PFR1_MPAM_FRAC_SHIFT U(16)
-#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
+#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_MTE_WIDTH U(4)
+#define MTE_UNIMPLEMENTED ULL(0)
+#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
+#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
+
+#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
+#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
+#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
+
+#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
+#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
+#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
/* ID_PFR1_EL1 definitions */
#define ID_PFR1_VIRTEXT_SHIFT U(12)
@@ -1456,5 +1479,26 @@
#define HFGWTR_EL2_FEAT_PAUTH_MASK ULL(0x1f0)
#define HFGWTR_EL2_NON_FEAT_DEPENDENT_MASK ULL(0x7f2903380b)
+/*******************************************************************************
+ * Permission indirection and overlay Registers
+ ******************************************************************************/
+#define PIRE0_EL1 S3_0_C10_C2_2
+#define PIR_EL1 S3_0_C10_C2_3
+#define POR_EL1 S3_0_C10_C2_4
+#define S2POR_EL1 S3_0_C10_C2_5
+
+/*******************************************************************************
+ * FEAT_GCS - Guarded Control Stack Registers
+ ******************************************************************************/
+#define GCSCR_EL1 S3_0_C2_C5_0
+#define GCSCRE0_EL1 S3_0_C2_C5_2
+#define GCSPR_EL1 S3_0_C2_C5_1
+#define GCSPR_EL0 S3_3_C2_C5_1
+
+/*******************************************************************************
+ * Realm management extension register definitions
+ ******************************************************************************/
+#define SCXTNUM_EL1 S3_0_C13_C0_7
+#define SCXTNUM_EL0 S3_3_C13_C0_7
#endif /* ARCH_H */
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 8a6e4b7..0290e8f 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -258,8 +258,8 @@
static inline bool is_feat_tcr2_supported(void)
{
- return (((read_id_aa64mmfr3_el1() >> ID_AA64MMFR3_TCR2_SHIFT) &
- ID_AA64MMFR3_TCR2_MASK) != 0);
+ return (((read_id_aa64mmfr3_el1() >> ID_AA64MMFR3_EL1_TCRX_SHIFT) &
+ ID_AA64MMFR3_EL1_TCRX_MASK) >= ID_AA64MMFR3_EL1_TCR2_SUPPORTED);
}
static inline bool get_feat_pmuv3_supported(void)
@@ -394,7 +394,7 @@
static inline bool is_feat_ras_present(void)
{
return EXTRACT(ID_AA64PFR0_RAS, read_id_aa64pfr0_el1())
- == ID_AA64PFR0_RAS_SUPPORTED;
+ >= ID_AA64PFR0_RAS_SUPPORTED;
}
static inline bool is_feat_rasv1p1_present(void)
@@ -462,4 +462,34 @@
>= ID_AA64DFR0_TRACEBUFFER_SUPPORTED;
}
+static inline bool is_feat_gcs_present(void)
+{
+ return EXTRACT(ID_AA64PFR1_EL1_GCS, read_id_aa64pfr1_el1())
+ >= ID_AA64PFR1_EL1_GCS_SUPPORTED;
+}
+
+static inline bool is_feat_s1poe_present(void)
+{
+ return EXTRACT(ID_AA64MMFR3_EL1_S1POE, read_id_aa64mmfr3_el1())
+ >= ID_AA64MMFR3_EL1_S1POE_SUPPORTED;
+}
+
+static inline bool is_feat_s2poe_present(void)
+{
+ return EXTRACT(ID_AA64MMFR3_EL1_S2POE, read_id_aa64mmfr3_el1())
+ >= ID_AA64MMFR3_EL1_S2POE_SUPPORTED;
+}
+
+static inline bool is_feat_s1pie_present(void)
+{
+ return EXTRACT(ID_AA64MMFR3_EL1_S1PIE, read_id_aa64mmfr3_el1())
+ >= ID_AA64MMFR3_EL1_S1PIE_SUPPORTED;
+}
+
+static inline bool is_feat_mte2_present(void)
+{
+ return EXTRACT(ID_AA64PFR1_EL1_MTE, read_id_aa64pfr1_el1())
+ >= MTE_IMPLEMENTED_ELX;
+}
+
#endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 744bbe6..912b0f6 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -388,6 +388,24 @@
DEFINE_SYSREG_READ_FUNC(cntvct_el0)
DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
+DEFINE_SYSREG_RW_FUNCS(csselr_el1)
+DEFINE_SYSREG_RW_FUNCS(sp_el1)
+DEFINE_SYSREG_RW_FUNCS(tpidr_el0)
+DEFINE_SYSREG_RW_FUNCS(tpidr_el1)
+DEFINE_SYSREG_RW_FUNCS(tpidrro_el0)
+DEFINE_SYSREG_RW_FUNCS(contextidr_el1)
+DEFINE_SYSREG_RW_FUNCS(mdccint_el1)
+DEFINE_SYSREG_RW_FUNCS(mdscr_el1)
+DEFINE_SYSREG_RW_FUNCS(spsr_abt)
+DEFINE_SYSREG_RW_FUNCS(spsr_und)
+DEFINE_SYSREG_RW_FUNCS(spsr_irq)
+DEFINE_SYSREG_RW_FUNCS(spsr_fiq)
+DEFINE_SYSREG_RW_FUNCS(dacr32_el2)
+DEFINE_SYSREG_RW_FUNCS(ifsr32_el2)
+DEFINE_SYSREG_RW_FUNCS(cntv_ctl_el0)
+DEFINE_SYSREG_RW_FUNCS(cntv_cval_el0)
+DEFINE_SYSREG_RW_FUNCS(cntkctl_el1)
+
#define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
CNTP_CTL_ENABLE_MASK)
#define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
@@ -499,6 +517,9 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el1, SCXTNUM_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el0, SCXTNUM_EL0)
+
/* Static profiling control registers */
DEFINE_RENAME_SYSREG_RW_FUNCS(pmscr_el1, PMSCR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(pmsevfr_el1, PMSEVFR_EL1)
@@ -538,6 +559,7 @@
/* Armv8.2 Registers */
DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
+DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1)
/* Armv8.3 Pointer Authentication Registers */
/* Instruction keys A and B */
@@ -639,8 +661,22 @@
/* ID_PFR2_EL1 */
DEFINE_RENAME_SYSREG_READ_FUNC(id_pfr2_el1, ID_PFR2_EL1)
-/* ID_AA64MMFR3_EL1 */
-DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1)
+/* FEAT_SxPIE Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el1, PIRE0_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el1, PIR_EL1)
+
+/* Armv8.2 RAS Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(disr_el1, DISR_EL1)
+
+/* FEAT_SxPOE Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(por_el1, POR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(s2por_el1, S2POR_EL1)
+
+/* FEAT_GCS Registers */
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el1, GCSCR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcscre0_el1, GCSCRE0_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el1, GCSPR_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el0, GCSPR_EL0)
#define IS_IN_EL(x) \
(GET_EL(read_CurrentEl()) == MODE_EL##x)