feat: add tests to check SCTLR2, THE and D128 sysregs
This patch adds test cases for verifying that the system registers of
FEAT_SCTLR2, FEAT_THE and FEAT_D128 (FEAT_SYSREG128) are working
correctly by performing a series of reads and writes to the registers.
Change-Id: I5c102daa358a7ec5d1801395bc875e9850e83939
Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index 0580f8a..f0c10ef 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -432,6 +432,11 @@
/* ID_AA64MMFR3_EL1 definitions */
#define ID_AA64MMFR3_EL1 S3_0_C0_C7_3
+#define ID_AA64MMFR3_EL1_D128_SHIFT U(32)
+#define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf)
+#define ID_AA64MMFR3_EL1_D128_WIDTH U(4)
+#define ID_AA64MMFR3_EL1_D128_SUPPORTED ULL(0x1)
+
#define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20)
#define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf)
#define ID_AA64MMFR3_EL1_S2POE_WIDTH U(4)
@@ -453,7 +458,9 @@
#define ID_AA64MMFR3_EL1_S1PIE_SUPPORTED ULL(0x1)
#define ID_AA64MMFR3_EL1_SCTLRX_SHIFT U(4)
+#define ID_AA64MMFR3_EL1_SCTLRX_MASK ULL(0xf)
#define ID_AA64MMFR3_EL1_SCTLRX_WIDTH ULL(0x4)
+#define ID_AA64MMFR3_EL1_SCTLR2_SUPPORTED ULL(0x1)
#define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0)
#define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf)
@@ -465,6 +472,11 @@
#define ID_AA64PFR1_EL1_DF2_WIDTH U(4)
#define ID_AA64PFR1_EL1_DF2_MASK (0xf << ID_AA64PFR1_EL1_DF2_SHIFT)
+#define ID_AA64PFR1_EL1_THE_SHIFT U(48)
+#define ID_AA64PFR1_EL1_THE_MASK ULL(0xf)
+#define ID_AA64PFR1_EL1_THE_WIDTH U(4)
+#define ID_AA64PFR1_EL1_THE_SUPPORTED ULL(1)
+
#define ID_AA64PFR1_EL1_GCS_SHIFT U(44)
#define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf)
#define ID_AA64PFR1_EL1_GCS_WIDTH U(4)
@@ -571,7 +583,8 @@
#define SCTLR_DSSBS_BIT (ULL(1) << 44)
#define SCTLR_RESET_VAL SCTLR_EL3_RES1
-/* SCTLR2_EL1 register definitions */
+/* SCTLR2 register definitions */
+#define SCTLR2_EL2 S3_4_C1_C0_3
#define SCTLR2_EL1 S3_0_C1_C0_3
#define SCTLR2_NMEA_BIT (UL(1) << 2)
@@ -1418,6 +1431,12 @@
******************************************************************************/
#define MDSELR_EL1 S2_0_C0_C4_2
+/******************************************************************************
+ * Armv8.9 - Translation Hardening Extension Registers
+ ******************************************************************************/
+#define RCWMASK_EL1 S3_0_C13_C0_6
+#define RCWSMASK_EL1 S3_0_C13_C0_3
+
/*******************************************************************************
* Armv9.0 - Trace Buffer Extension System Registers
******************************************************************************/
diff --git a/include/lib/aarch64/arch_features.h b/include/lib/aarch64/arch_features.h
index 2c9ae80..27f5c82 100644
--- a/include/lib/aarch64/arch_features.h
+++ b/include/lib/aarch64/arch_features.h
@@ -537,4 +537,22 @@
return EXTRACT(ID_AA64PFR2_EL1_FPMR, read_id_aa64pfr2_el1())
== ID_AA64PFR2_EL1_FPMR_SUPPORTED;
}
+
+static inline bool is_feat_sctlr2_supported(void)
+{
+ return (((read_id_aa64mmfr3_el1() >> ID_AA64MMFR3_EL1_SCTLRX_SHIFT) &
+ ID_AA64MMFR3_EL1_SCTLRX_MASK) == ID_AA64MMFR3_EL1_SCTLR2_SUPPORTED);
+}
+
+static inline bool is_feat_the_supported(void)
+{
+ return (((read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_THE_SHIFT) &
+ ID_AA64PFR1_EL1_THE_MASK) == ID_AA64PFR1_EL1_THE_SUPPORTED);
+}
+
+static inline bool is_feat_d128_supported(void)
+{
+ return (((read_id_aa64mmfr3_el1() >> ID_AA64MMFR3_EL1_D128_SHIFT) &
+ ID_AA64MMFR3_EL1_D128_MASK) == ID_AA64MMFR3_EL1_D128_SUPPORTED);
+}
#endif /* ARCH_FEATURES_H */
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 0774e7b..35d2454 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -324,6 +324,7 @@
DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el1, SCTLR2_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(sctlr2_el2, SCTLR2_EL2)
DEFINE_SYSREG_RW_FUNCS(actlr_el1)
DEFINE_SYSREG_RW_FUNCS(actlr_el2)
@@ -648,6 +649,10 @@
DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2)
+/* Armv8.9 Translation Hardening Extension */
+DEFINE_RENAME_SYSREG_RW_FUNCS(rcwmask_el1, RCWMASK_EL1)
+DEFINE_RENAME_SYSREG_RW_FUNCS(rcwsmask_el1, RCWSMASK_EL1)
+
/* Armv9.4 Guarded Control Stack Extension */
DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)