fix(plat/arm/fvp): make address space configurable
Make FVP physical/virtual address space sizes configurable, with
default at 34-bit (previously hard-coded value).
Maximum tested value is 48-bit, FVP interconnect doesn't yet support
52-bit PA.
Increase MAX_XLAT_TABLE and consequently NS_BL1U_RW_SIZE and
NS_BLU2_LIMIT to accommodate the increased translation tables (based
on 48-bit max PA size).
Custom PA size is passed to build system through the PA_SIZE define.
FVP needs to be configured in a compatible way through the parameters:
* cluster0.PA_SIZE, for each cluster;
* bp.dram_size, setting a memory limit corresponding at least to
PA_SIZE;
* cci550.addr_width, interconnect address width should match PA_SIZE;
* pci.pci_smmuv3.mmu.SMMU_IDR5, SMMU has to be configured as well if
present.
Change-Id: I57bc898fb2c9696c01fc8e20d00b4a3d09e22326
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
diff --git a/include/common/test_helpers.h b/include/common/test_helpers.h
index c628ee8..78f1c58 100644
--- a/include/common/test_helpers.h
+++ b/include/common/test_helpers.h
@@ -290,6 +290,18 @@
} \
} while (false)
+#define SKIP_TEST_IF_PA_SIZE_LESS_THAN(n) \
+ do { \
+ static const unsigned int pa_range_bits_arr[] = { \
+ PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011,\
+ PARANGE_0100, PARANGE_0101, PARANGE_0110 \
+ }; \
+ if (pa_range_bits_arr[get_pa_range()] < n) { \
+ tftf_testcase_printf("PA size less than %d bit\n", n); \
+ return TEST_RESULT_SKIPPED; \
+ } \
+ } while (false)
+
/* Helper macro to verify if system suspend API is supported */
#define is_psci_sys_susp_supported() \
(tftf_get_psci_feature_info(SMC_PSCI_SYSTEM_SUSPEND) \