Aarch32: Secure PMU counter leak tests
This patch adds Aarch32 support to the PMU counter leak tests.
These tests attempt to profile the Secure world by configuring
EL0 system registers such that the PMU is told to increment
counters at Secure EL1, Secure EL2 and EL3. The tests fail if
useful information was leaked.
The Secure world defends against this type of attack with a
combination of configuring EL3 system registers and saving/restoring
EL0 PMU registers. Exactly which defense is employed depends on the
architecture version.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: I2dcc9e786a18d9859ac089f8008b060d277bee3a
diff --git a/include/lib/aarch32/arch_helpers.h b/include/lib/aarch32/arch_helpers.h
index e983554..f2e3e00 100644
--- a/include/lib/aarch32/arch_helpers.h
+++ b/include/lib/aarch32/arch_helpers.h
@@ -277,7 +277,13 @@
DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
-DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
+DEFINE_COPROCR_RW_FUNCS(pmcr, PMCR)
+DEFINE_COPROCR_RW_FUNCS(pmcntenset, PMCNTENSET)
+DEFINE_COPROCR_RW_FUNCS(pmccfiltr, PMCCFILTR)
+DEFINE_COPROCR_READ_FUNC(pmccntr, PMCCNTR)
+DEFINE_COPROCR_RW_FUNCS(pmevtyper0, PMEVTYPER0)
+DEFINE_COPROCR_READ_FUNC(pmevcntr0, PMEVCNTR0)
+DEFINE_COPROCR_READ_FUNC(dbgdidr, DBGDIDR)
/*
* Address translation
@@ -377,6 +383,22 @@
#define read_ctr_el0() read_ctr()
+#define read_pmcr_el0() read_pmcr()
+#define write_pmcr_el0(_v) write_pmcr(_v)
+
+#define read_pmcntenset_el0() read_pmcntenset()
+#define write_pmcntenset_el0(_v) write_pmcntenset(_v)
+
+#define read_pmccfiltr_el0() read_pmccfiltr()
+#define write_pmccfiltr_el0(_v) write_pmccfiltr(_v)
+
+#define read_pmevtyper0_el0() read_pmevtyper0()
+#define write_pmevtyper0_el0(_v) write_pmevtyper0(_v)
+
+#define read_pmccntr_el0 read_pmccntr
+
+#define read_pmevcntr0_el0 read_pmevcntr0
+
#define write_icc_sgi0r_el1(_v) write64_icc_sgi0r_el1(_v)
#define read_daif() read_cpsr()