commit f68ebdb9b45cc7a58f816f153f5e626c898dc0cf
author Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Wed Sep 18 16:13:00 2019 +0100
committer Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Fri Oct 04 09:35:00 2019 +0100
tree 8eb48a5843eb4acfa86c3066173aaa2b0f898d4b
parent 0012dbc2a841abeff25be8be1113f19073ee4d2c

Try to leak counter values from secure world.

This patch introduces a series of tests that try to leak PMU counter values
from EL3 and S_EL1.

PMU events used:
	- CPU cycles via PMU counter PMCCNTR_EL0
	- Retired writes to PC via PMU counter PMEVCNTR0_EL0

This AARCH64-specific patch is for security fix:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1789

The AARCH32 versions of these tests will be in a future patch.

Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: Ib27948edadde30272e59a9ab208543703fa078bd

include/lib/aarch64/arch_helpers.h

diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 151e5be..9d1ebb8 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -395,6 +395,12 @@
 DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
 DEFINE_SYSREG_RW_FUNCS(hstr_el2)
 DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
+DEFINE_SYSREG_RW_FUNCS(pmcntenset_el0)
+DEFINE_SYSREG_READ_FUNC(pmccntr_el0)
+DEFINE_SYSREG_RW_FUNCS(pmccfiltr_el0)
+
+DEFINE_SYSREG_RW_FUNCS(pmevtyper0_el0)
+DEFINE_SYSREG_READ_FUNC(pmevcntr0_el0)
 
 /* GICv3 System Registers */