diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 1de9999..78782d4 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -37,10 +37,6 @@
 #include <v2m_def.h>
 #include "../fvp_def.h"
 
-#if (FVP_USE_GIC_DRIVER == FVP_GICV2)
-extern gicv2_driver_data_t arm_gic_data;
-#endif
-
 /* Defines for GIC Driver build time selection */
 #define FVP_GICV2		1
 #define FVP_GICV3		2
@@ -159,26 +155,9 @@
 	 */
 	switch (bld) {
 	case BLD_GIC_VE_MMAP:
-#if IMAGE_BL31 || IMAGE_BL32
-#if FVP_USE_GIC_DRIVER == FVP_GICV2
-		/*
-		 * If the FVP implements the VE compatible memory map, then the
-		 * GICv2 driver must be included in the build. Update the platform
-		 * data with the correct GICv2 base addresses before it is used
-		 * to initialise the driver.
-		 *
-		 * This update of platform data is temporary and will be removed
-		 * once VE memory map for FVP is no longer supported by Trusted
-		 * Firmware.
-		 */
-		arm_gic_data.gicd_base = VE_GICD_BASE;
-		arm_gic_data.gicc_base = VE_GICC_BASE;
-
-#else
-		ERROR("Only GICv2 driver supported for VE memory map\n");
+		ERROR("Legacy Versatile Express memory map for GIC peripheral"
+				" is not supported\n");
 		panic();
-#endif /* __FVP_USE_GIC_DRIVER == FVP_GICV2__ */
-#endif /* __IMAGE_BL31 || IMAGE_BL32__ */
 		break;
 	case BLD_GIC_A53A57_MMAP:
 		break;
diff --git a/plat/arm/common/arm_gicv2.c b/plat/arm/common/arm_gicv2.c
index 76f04cd..2636d1c 100644
--- a/plat/arm/common/arm_gicv2.c
+++ b/plat/arm/common/arm_gicv2.c
@@ -47,17 +47,12 @@
  * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
  * interrupts.
  *****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
+static const unsigned int g0_interrupt_array[] = {
 	PLAT_ARM_G1S_IRQS,
 	PLAT_ARM_G0_IRQS
 };
 
-/*
- * Ideally `arm_gic_data` structure definition should be a `const` but it is
- * kept as modifiable for overwriting with different GICD and GICC base when
- * running on FVP with VE memory map.
- */
-gicv2_driver_data_t arm_gic_data = {
+static const gicv2_driver_data_t arm_gic_data = {
 	.gicd_base = PLAT_ARM_GICD_BASE,
 	.gicc_base = PLAT_ARM_GICC_BASE,
 	.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index 33f8018..a20fd56 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -45,15 +45,15 @@
 #pragma weak plat_arm_gic_pcpu_init
 
 /* The GICv3 driver only needs to be initialized in EL3 */
-uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
 
 /* Array of Group1 secure interrupts to be configured by the gic driver */
-const unsigned int g1s_interrupt_array[] = {
+static const unsigned int g1s_interrupt_array[] = {
 	PLAT_ARM_G1S_IRQS
 };
 
 /* Array of Group0 interrupts to be configured by the gic driver */
-const unsigned int g0_interrupt_array[] = {
+static const unsigned int g0_interrupt_array[] = {
 	PLAT_ARM_G0_IRQS
 };
 
diff --git a/plat/arm/common/arm_gicv3_legacy.c b/plat/arm/common/arm_gicv3_legacy.c
index 6170933..8396b60 100644
--- a/plat/arm/common/arm_gicv3_legacy.c
+++ b/plat/arm/common/arm_gicv3_legacy.c
@@ -48,7 +48,7 @@
  * In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group
  * 0 interrupts.
  */
-const unsigned int irq_sec_array[] = {
+static const unsigned int irq_sec_array[] = {
 	PLAT_ARM_G0_IRQS,
 	PLAT_ARM_G1S_IRQS
 };