fix(cpus): workaround for Cortex-X3 erratum 3213672
Cortex-X3 erratum 3213672 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2. It is still open.
This erratum can be worked around by setting CPUACTLR_EL1[36]
before enabling icache.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: Ia1c03217f4e1816b4e8754a090cf5bc17546be40
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index c9213c9..0d6a5dd 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -836,6 +836,10 @@
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU. It is fixed in r1p2.
+- ``ERRATA_X3_3213672``: This applies errata 3213672 workaround to Cortex-X3
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
+ of the CPU. It is still open.
+
- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3
CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
of the CPU. It is still open.