diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 03b3ee5..55e265c 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -280,6 +280,9 @@
  -  ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
     CPU. This needs to be enabled for revisions <= r1p1 of the CPU.
 
+ -  ``ERRATA_A77_2743100``: This applies errata 2743100 workaround to Cortex-A77
+    CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
+
 For Cortex-A78, the following errata build flags are defined :
 
 -  ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 8cafe4a..2882df7 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -227,6 +227,30 @@
 	b	cpu_rev_var_ls
 endfunc check_errata_2356587
 
+	/* -----------------------------------------------------------------
+	 * Errata Workaround for Cortex A77 Errata #2743100
+	 * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * -----------------------------------------------------------------
+	 */
+func errata_a77_2743100_wa
+	mov	x17, x30
+	bl	check_errata_2743100
+	cbz	x0, 1f
+
+	/* dsb before isb of power down sequence */
+	dsb	sy
+1:
+	ret	x17
+endfunc errata_a77_2743100_wa
+
+func check_errata_2743100
+	/* Applies to r0p0, r1p0, and r1p1 right now */
+	mov	x1, #0x11
+	b	cpu_rev_var_ls
+endfunc check_errata_2743100
+
 func check_errata_cve_2022_23960
 #if WORKAROUND_CVE_2022_23960
 	mov	x0, #ERRATA_APPLIES
@@ -330,6 +354,12 @@
 	mrs	x0, CORTEX_A77_CPUPWRCTLR_EL1
 	orr	x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
 	msr	CORTEX_A77_CPUPWRCTLR_EL1, x0
+#if ERRATA_A77_2743100
+	mov	x15, x30
+	bl	cpu_get_rev_var
+	bl	errata_a77_2743100_wa
+	mov	x30, x15
+#endif /* ERRATA_A77_2743100 */
 	isb
 	ret
 endfunc cortex_a77_core_pwr_dwn
@@ -354,6 +384,7 @@
 	report_errata ERRATA_A77_1925769, cortex_a77, 1925769
 	report_errata ERRATA_A77_1946167, cortex_a77, 1946167
 	report_errata ERRATA_A77_2356587, cortex_a77, 2356587
+	report_errata ERRATA_A77_2743100, cortex_a77, 2743100
 	report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960
 
 	ldp	x8, x30, [sp], #16
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index eb6d20f..f19c16e 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -315,6 +315,10 @@
 # to revisions <= r1p1 of the Cortex A77 cpu.
 ERRATA_A77_1800714	?=0
 
+# Flag to apply erratum 2743100 workaround during power down. This erratum
+# applies to revisions r0p0, r1p0, and r1p1, it is still open.
+ERRATA_A77_2743100	?=0
+
 # Flag to apply erratum 1688305 workaround during reset. This erratum applies
 # to revisions r0p0 - r1p0 of the A78 cpu.
 ERRATA_A78_1688305	?=0
@@ -948,6 +952,10 @@
 $(eval $(call assert_boolean,ERRATA_A77_1800714))
 $(eval $(call add_define,ERRATA_A77_1800714))
 
+# Process ERRATA_A77_2743100 flag
+$(eval $(call assert_boolean,ERRATA_A77_2743100))
+$(eval $(call add_define,ERRATA_A77_2743100))
+
 # Process ERRATA_A78_1688305 flag
 $(eval $(call assert_boolean,ERRATA_A78_1688305))
 $(eval $(call add_define,ERRATA_A78_1688305))