fix(cpus): workaround for Cortex-X925 erratum 3701747
Cortex-X925 erratum 3701747 that applies to r0p0, r0p1 and is still
Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/109180/latest/
Change-Id: I080296666f89276b3260686c2bdb8de63fc174c1
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index acb9fe3..7f025b4 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -18,6 +18,7 @@
#include <cortex_x2.h>
#include <cortex_x3.h>
#include <cortex_x4.h>
+#include <cortex_x925.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -107,6 +108,12 @@
break;
#endif /* ERRATA_X4_3701758 */
+#if ERRATA_X925_3701747
+ case EXTRACT_PARTNUM(CORTEX_X925_MIDR):
+ if (check_erratum_cortex_x925_3701747(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_X925_3701747 */
default:
break;
}