refactor(ast2700): adopt RESET_TO_BL31 boot flow
Revise the AST2700 boot flow to the RESET_TO_BL31 scheme.
The execution of BL1/2 can be saved from ARM CA35 while most
low level platform initialization are moved to a preceding MCU.
This patch updates the build configuration and also adds
the SMP mailbox setup code to hold secondary cores until
they are being waken up.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Change-Id: I7e0aa6416b92b97036153db1d9a26baaa41b7b18
diff --git a/plat/aspeed/ast2700/plat_helpers.S b/plat/aspeed/ast2700/plat_helpers.S
index 1457692..c6d987e 100644
--- a/plat/aspeed/ast2700/plat_helpers.S
+++ b/plat/aspeed/ast2700/plat_helpers.S
@@ -10,6 +10,7 @@
#include <cortex_a35.h>
#include <platform_def.h>
+ .globl platform_mem_init
.globl plat_is_my_cpu_primary
.globl plat_my_core_pos
.globl plat_secondary_cold_boot_setup
@@ -18,6 +19,12 @@
.globl plat_crash_console_putc
.globl plat_crash_console_flush
+/* void platform_mem_init(void); */
+func platform_mem_init
+ /* DRAM init. is done by preceding MCU */
+ ret
+endfunc platform_mem_init
+
/* unsigned int plat_is_my_cpu_primary(void); */
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
@@ -37,6 +44,21 @@
ret
endfunc plat_my_core_pos
+/* void plat_secondary_cold_boot_setup (void); */
+func plat_secondary_cold_boot_setup
+ mov x0, xzr
+ bl plat_my_core_pos
+ mov_imm x1, SCU_CPU_SMP_EP0
+ add x1, x1, x0, lsl #3
+
+poll_smp_mbox_go:
+ wfe
+ ldr x0, [x1]
+ cmp x0, xzr
+ beq poll_smp_mbox_go
+ br x0
+endfunc plat_secondary_cold_boot_setup
+
/* unsigned int plat_get_syscnt_freq2(void); */
func plat_get_syscnt_freq2
mov_imm w0, PLAT_SYSCNT_CLKIN_HZ