fix(cpus): workaround for Cortex-X3 erratum 3827463
Cortex-X3 erratum 3827463 is a Cat B erratum that applies to
r0p0, r1p0 and r1p1. It is fixed in r1p2.
This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I1d4a2b9641400d8b9061f7cb32a8312c3995613e
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 4ba8a43..c9213c9 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -844,6 +844,10 @@
CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2
of the CPU and it is still open.
+- ``ERRATA_X3_3827463``: This applies errata 3827463 workaround to Cortex-X3
+ CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of
+ the CPU. It is fixed in r1p2.
+
For Cortex-X4, the following errata build flags are defined :
- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4