feat(the): add support for FEAT_THE
Arm v8.9 introduces FEAT_THE, adding Translation Hardening Extension
Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.
Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.
Change-Id: I8775787f523639b39faf61d046ef482f73b2a562
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 6210356..f1c872b 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -260,6 +260,14 @@
*/
scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
#endif
+
+ if (is_feat_the_supported()) {
+ /* Set the RCWMASKEn bit in SCR_EL3 to enable access to
+ * RCWMASK_EL1 and RCWSMASK_EL1 registers.
+ */
+ scr_el3 |= SCR_RCWMASKEn_BIT;
+ }
+
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
/* Initialize EL2 context registers */
@@ -1712,6 +1720,12 @@
write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1());
write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0());
}
+
+ if (is_feat_the_supported()) {
+ write_el1_ctx_the(ctx, rcwmask_el1, read_rcwmask_el1());
+ write_el1_ctx_the(ctx, rcwsmask_el1, read_rcwsmask_el1());
+ }
+
}
static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
@@ -1807,6 +1821,11 @@
write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1));
write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0));
}
+
+ if (is_feat_the_supported()) {
+ write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1));
+ write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1));
+ }
}
/*******************************************************************************