diff --git a/docs/about/features.rst b/docs/about/features.rst
index cb8b552..4a2c77e 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -22,8 +22,8 @@
    Cache Coherent Network (CCN), Network Interconnect (NIC) and TrustZone
    Controller (TZC).
 
--  A generic |SCMI| driver to interface with conforming power controllers, for
-   example the Arm System Control Processor (SCP).
+-  Secure Monitor library code such as world switching, EL2/EL1 context
+   management and interrupt routing.
 
 -  SMC (Secure Monitor Call) handling, conforming to the `SMC Calling
    Convention`_ using an EL3 runtime services framework.
@@ -34,14 +34,22 @@
    is also suitable for integration with other AArch32 EL3 Runtime Software,
    for example an AArch32 Secure OS.
 
+-  A generic |SCMI| driver to interface with conforming power controllers, for
+   example the Arm System Control Processor (SCP).
+
 -  A minimal AArch32 Secure Payload (*SP_MIN*) to demonstrate |PSCI| library
    integration with AArch32 EL3 Runtime Software.
 
--  Secure Monitor library code such as world switching, EL1 context management
-   and interrupt routing.
-   When a Secure-EL1 Payload (SP) is present, for example a Secure OS, the
-   AArch64 EL3 Runtime Software must be integrated with a Secure Payload
-   Dispatcher (SPD) component to customize the interaction with the SP.
+-  Secure partition manager dispatcher(SPMD) with following two configurations:
+
+   -  S-EL2 SPMC implementation, widely compliant with FF-A v1.1 EAC0 and initial
+      support of FF-A v1.2.
+
+   -  EL3 SPMC implementation, compliant with a subset of FF-A v1.1 EAC0.
+
+-  Support for Arm CCA based on FEAT_RME which supports authenticated boot and
+   execution of RMM with the necessary routing of RMI commands as specified in
+   RMM Beta 0 Specification.
 
 -  A Test SP and SPD to demonstrate AArch64 Secure Monitor functionality and SP
    interaction with PSCI.
@@ -50,12 +58,20 @@
    `Trusty Secure OS`_ and `ProvenCore Secure OS`_.
 
 -  A Trusted Board Boot implementation, conforming to all mandatory TBBR
-   requirements. This includes image authentication, Firmware Update (or
-   recovery mode), and packaging of the various firmware images into a
+   requirements. This includes image authentication, Firmware recovery,
+   Firmware encryption and packaging of the various firmware images into a
    Firmware Image Package (FIP).
 
--  Pre-integration of TBB with the Arm CryptoCell product, to take advantage of
-   its hardware Root of Trust and crypto acceleration services.
+-  Measured boot support with PoC to showcase its interaction with firmware TPM
+   (fTPM) service implemneted on top of OP-TEE.
+
+-  Support for Dynamic Root of Trust for Measurement (DRTM).
+
+-  Following firmware update mechanisms available:
+
+   -  PSA Firmware Update (PSA FWU)
+
+   -  TBBR Firmware Update (TBBR FWU)
 
 -  Reliability, Availability, and Serviceability (RAS) functionality, including
 
@@ -81,6 +97,8 @@
    secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
    at EL3.
 
+-  Support for Errata management firmware interface.
+
 -  Support for the GCC, LLVM and Arm Compiler 6 toolchains.
 
 -  Support for combining several libraries into a "romlib" image that may be
@@ -88,27 +106,13 @@
    in ROM but is accessed through a jump-table that may be stored
    in read-write memory, allowing for the library code to be patched.
 
--  Support for the Secure Partition Manager Dispatcher (SPMD) component as a
-   new standard service.
-
--  Support for ARMv8.3 pointer authentication in the normal and secure worlds.
-   The use of pointer authentication in the normal world is enabled whenever
-   architectural support is available, without the need for additional build
-   flags.
-
--  Position-Independent Executable (PIE) support. Currently for BL2, BL31, and
-   TSP, with further support to be added in a future release.
+-  Position-Independent Executable (PIE) support.
 
 Still to come
 -------------
 
 -  Support for additional platforms.
 
--  Refinements to Position Independent Executable (PIE) support.
-
--  Continued support for the FF-A v1.0 (formally known as SPCI) specification, to enable the
-   use of secure partition management in the secure world.
-
 -  Documentation enhancements.
 
 -  Ongoing support for new architectural features, CPUs and System IP.
@@ -125,4 +129,4 @@
 
 --------------
 
-*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*