diff --git a/lib/cpus/aarch32/cortex_a32.S b/lib/cpus/aarch32/cortex_a32.S
index b51f997..f2b85a3 100644
--- a/lib/cpus/aarch32/cortex_a32.S
+++ b/lib/cpus/aarch32/cortex_a32.S
@@ -72,7 +72,8 @@
 	 * ----------------------------------------------------
 	 */
 func cortex_a32_core_pwr_dwn
-	push	{lr}
+	/* r12 is pushed to meet the 8 byte stack alignment requirement */
+	push	{r12, lr}
 
 	/* Assert if cache is enabled */
 #if ASM_ASSERTION
@@ -92,7 +93,7 @@
 	 * Come out of intra cluster coherency
 	 * ---------------------------------------------
 	 */
-	pop	{lr}
+	pop	{r12, lr}
 	b	cortex_a32_disable_smp
 endfunc cortex_a32_core_pwr_dwn
 
@@ -102,7 +103,8 @@
 	 * -------------------------------------------------------
 	 */
 func cortex_a32_cluster_pwr_dwn
-	push	{lr}
+	/* r12 is pushed to meet the 8 byte stack alignment requirement */
+	push	{r12, lr}
 
 	/* Assert if cache is enabled */
 #if ASM_ASSERTION
@@ -135,7 +137,7 @@
 	 * Come out of intra cluster coherency
 	 * ---------------------------------------------
 	 */
-	pop	{lr}
+	pop	{r12, lr}
 	b	cortex_a32_disable_smp
 endfunc cortex_a32_cluster_pwr_dwn
 
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index 042ffbd..a4dfe5f 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -76,9 +76,10 @@
 	 */
 	.globl	prepare_core_pwr_dwn
 func prepare_core_pwr_dwn
-	push	{lr}
+	/* r12 is pushed to meet the 8 byte stack alignment requirement */
+	push	{r12, lr}
 	bl	_cpu_data
-	pop	{lr}
+	pop	{r12, lr}
 
 	ldr	r1, [r0, #CPU_DATA_CPU_OPS_PTR]
 #if ASM_ASSERTION
@@ -98,9 +99,10 @@
 	 */
 	.globl	prepare_cluster_pwr_dwn
 func prepare_cluster_pwr_dwn
-	push	{lr}
+	/* r12 is pushed to meet the 8 byte stack alignment requirement */
+	push	{r12, lr}
 	bl	_cpu_data
-	pop	{lr}
+	pop	{r12, lr}
 
 	ldr	r1, [r0, #CPU_DATA_CPU_OPS_PTR]
 #if ASM_ASSERTION