fix(cpus): workaround for Cortex-X2 erratum 3701772
Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1
is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest/
Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index d9f8339..5dbc50d 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -15,6 +15,7 @@
#include <cortex_a720.h>
#include <cortex_a720_ae.h>
#include <cortex_a725.h>
+#include <cortex_x2.h>
#include <cortex_x4.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -83,6 +84,14 @@
return true;
break;
#endif /* ERRATA_A725_3699564 */
+
+#if ERRATA_X2_3701772
+ case EXTRACT_PARTNUM(CORTEX_X2_MIDR):
+ if (check_erratum_cortex_x2_3701772(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_X2_3701772 */
+
default:
break;
}