fix(cpus): workaround for Cortex-A710 erratum 1927200
Cortex-A710 erratum 1927200 is a Cat B erratum that applies
to revisions r0p0 and r1p0 and is fixed in r2p0.
The fix is to insert DMB ST before acquire atomic instructions
without release semantics via instruction patching.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775101
Change-Id: I53c4aa17c1c2dc85b68f17d58f93bb1ee6b3d488
Signed-off-by: John Powell <john.powell@arm.com>
(cherry picked from commit cb2702c4b72746b6ef4e2da8d04d3f4b56d85398)
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 978f4b5..5941922 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -585,6 +585,10 @@
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
It has been fixed in r2p0.
+- ``ERRATA_A710_1927200``: This applies errata 1927200 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0 and r1p0.
+ It has been fixed in r2p0.
+
- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU. It is still open.