tree 1f1807d453701b21cf7f346274fa545bc0ad40d6
parent ddf287000bd23f7c7640b661256821faa56e70f4
parent 5a22eb421d30093a44ca8ef04325ebb9c2472ca3
author Varun Wadekar <vwadekar@nvidia.com> 1598913997 +0000
committer TrustedFirmware Code Review <review@review.trustedfirmware.org> 1598913997 +0000

Merge changes from topic "tegra-downstream-08282020" into integration

* changes:
  Tegra: platform specific BL31_SIZE
  Tegra186: sanity check power state type
  Tegra: fixup CNTPS_TVAL_EL1 delay timer reads
  Tegra: add platform specific 'runtime_setup' handler
  Tegra: remove ENABLE_SVE_FOR_NS = 0
  lib: cpus: denver: add MIDR PN9 variant
  cpus: denver: introduce macro to declare cpu_ops