fix(cpus): workaround for Cortex-X3 erratum 3692984
Cortex-X3 erratum 3692984 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2 and is still open.
The erratum can be avoided by disabling the
affected prefetcher setting CPUACTLR6_EL1[41].
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I054b47d33fd1ff7bde3ae12e8ee3d99e9203965f
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index de85adb..4ba8a43 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -836,6 +836,10 @@
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU. It is fixed in r1p2.
+- ``ERRATA_X3_3692984``: This applies errata 3692984 workaround to Cortex-X3
+ CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2
+ of the CPU. It is still open.
+
- ``ERRATA_X3_3701769``: This applies errata 3701769 workaround to Cortex-X3
CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2
of the CPU and it is still open.