tree 0a4bdd798e26ca9e54018ce623252bb611ce6536
parent a738e1554c2daf7511af3543addd07c956268d14
author Joel Hutton <Joel.Hutton@Arm.com> 1554817534 +0100
committer Joel Hutton <Joel.Hutton@arm.com> 1554890278 +0100

Add note about erratum 814220 for A7

On Cortex-A7 an L2 set/way cache maintenance operation can overtake
an L1 set/way cache maintenance operation. The mitigation for this is
to use a `DSB` instruction before changing cache. The cache cleaning
code happens to already be doing this, so only a comment was added.

Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>