Platform: Add support for MPS3 AN524 FPGA board
Details:
1. Adds AN524 platform support files
2. Adds a new target platform to the build system: "AN524"
3. Updates the docs with details for AN524
Change-Id: I7c192e951253dfc72512d73ee5da3f94023a248f
Signed-off-by: Kevin Peng <kevin.peng@arm.com>
diff --git a/configs/ConfigCoreIPC.cmake b/configs/ConfigCoreIPC.cmake
index 0e943c6..69103c6 100644
--- a/configs/ConfigCoreIPC.cmake
+++ b/configs/ConfigCoreIPC.cmake
@@ -19,6 +19,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN521.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN519")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN519.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "AN524")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps3AN524.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_A")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_a.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
diff --git a/configs/ConfigCoreIPCTfmLevel2.cmake b/configs/ConfigCoreIPCTfmLevel2.cmake
index d835cfc..ddbc7d0 100644
--- a/configs/ConfigCoreIPCTfmLevel2.cmake
+++ b/configs/ConfigCoreIPCTfmLevel2.cmake
@@ -19,6 +19,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN521.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN519")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN519.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "AN524")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps3AN524.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_A")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_a.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
diff --git a/configs/ConfigDefault.cmake b/configs/ConfigDefault.cmake
index 3263860..3674803 100644
--- a/configs/ConfigDefault.cmake
+++ b/configs/ConfigDefault.cmake
@@ -19,6 +19,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN521.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN519")
set (PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN519.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "AN524")
+ set (PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps3AN524.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_A")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_a.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
diff --git a/configs/ConfigRegression.cmake b/configs/ConfigRegression.cmake
index 3f223ab..c18ba29 100644
--- a/configs/ConfigRegression.cmake
+++ b/configs/ConfigRegression.cmake
@@ -19,6 +19,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN521.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN519")
set (PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN519.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "AN524")
+ set (PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps3AN524.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_A")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_a.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
diff --git a/configs/ConfigRegressionIPC.cmake b/configs/ConfigRegressionIPC.cmake
index 0eb6c11..60b389b 100644
--- a/configs/ConfigRegressionIPC.cmake
+++ b/configs/ConfigRegressionIPC.cmake
@@ -19,6 +19,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN521.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN519")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN519.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "AN524")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps3AN524.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_A")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_a.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
diff --git a/configs/ConfigRegressionIPCTfmLevel2.cmake b/configs/ConfigRegressionIPCTfmLevel2.cmake
index 130e8ac..17d6d90 100644
--- a/configs/ConfigRegressionIPCTfmLevel2.cmake
+++ b/configs/ConfigRegressionIPCTfmLevel2.cmake
@@ -19,6 +19,8 @@
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN521.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "AN519")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps2AN519.cmake")
+elseif(${TARGET_PLATFORM} STREQUAL "AN524")
+ set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/Mps3AN524.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_A")
set(PLATFORM_CMAKE_FILE "${TFM_ROOT_DIR}/platform/ext/musca_a.cmake")
elseif(${TARGET_PLATFORM} STREQUAL "MUSCA_B1")
diff --git a/docs/user_guides/tfm_build_instruction.rst b/docs/user_guides/tfm_build_instruction.rst
index fd21f7b..6c89699 100644
--- a/docs/user_guides/tfm_build_instruction.rst
+++ b/docs/user_guides/tfm_build_instruction.rst
@@ -33,6 +33,8 @@
``-DTARGET_PLATFORM=MUSCA_A``
- Musca-B1 test chip board (Cortex-M33 SSE-200 subsystem)
``-DTARGET_PLATFORM=MUSCA_B1``
+ - Cortex-M33 SSE-200 subsystem for MPS3 (AN524)
+ ``-DTARGET_PLATFORM=AN524``
* - -DCOMPILER=<compiler name>
- Specifies the compiler toolchain
diff --git a/docs/user_guides/tfm_integration_guide.rst b/docs/user_guides/tfm_integration_guide.rst
index 30e2771..5d0e80d 100644
--- a/docs/user_guides/tfm_integration_guide.rst
+++ b/docs/user_guides/tfm_integration_guide.rst
@@ -23,6 +23,7 @@
- Cortex-M23 IoT Kit subsystem for MPS2+ (AN519)
- Musca-A test chip board (Cortex-M33 SSE-200 subsystem)
- Musca-B1 test chip board (Cortex-M33 SSE-200 subsystem)
+- CoreLink SSE-200 Subsystem for MPS3 (AN524)
The files related to the supported platforms are contained under the
``platform`` subfolder. The platform specific files are under
@@ -39,6 +40,9 @@
More information about the Musca-B1 test chip board can be found in:
`Musca-B1 homepage <https://www.arm.com/products/development-tools/development-boards/musca-b1-iot>`__
+More information about subsystems supported by the MPS3 board can be found in:
+`MPS3 homepage <https://www.arm.com/products/development-tools/development-boards/mps3>`__
+
Generic drivers and startup/scatter files
=========================================
The addition of a new platform means the creation of a new subfolder inside
diff --git a/docs/user_guides/tfm_secure_boot.rst b/docs/user_guides/tfm_secure_boot.rst
index c1119d7..bea6bda 100644
--- a/docs/user_guides/tfm_secure_boot.rst
+++ b/docs/user_guides/tfm_secure_boot.rst
@@ -175,6 +175,8 @@
+----------+-----------------+---------------+----------+-------------+-----------------+
| Musca-B1 | Yes | No | No | Yes | No |
+----------+-----------------+---------------+----------+-------------+-----------------+
+| AN524 | Yes | No | No | Yes | No |
++----------+-----------------+---------------+----------+-------------+-----------------+
.. [1] To disable BL2, please turn off the ``BL2`` compiler switch in the
top-level configuration file or in the command line
@@ -450,6 +452,26 @@
Running Test Suite PSA protected storage S interface tests (TFM_SST_TEST_2XXX)...
...
+Executing firmware upgrade on CoreLink SSE-200 Subsystem for MPS3 (AN524)
+-------------------------------------------------------------------------
+
+::
+
+ TITLE: Arm MPS3 FPGA prototyping board Images Configuration File
+
+ [IMAGES]
+ TOTALIMAGES: 3 ;Number of Images (Max: 32)
+
+ IMAGE0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+ IMAGE0ADDRESS: 0x00000000
+ IMAGE0FILE: \SOFTWARE\mcuboot.bin ;BL2 bootloader
+ IMAGE1UPDATE: AUTO
+ IMAGE1ADDRESS: 0x00040000
+ IMAGE1FILE: \SOFTWARE\tfm_sig0.bin ;TF-M example application binary blob
+ IMAGE2UPDATE: AUTO
+ IMAGE2ADDRESS: 0x000C0000
+ IMAGE2FILE: \SOFTWARE\tfm_sig1.bin ;TF-M regression test binary blob
+
RAM loading firmware upgrade
============================
To enable RAM loading, please set ``MCUBOOT_UPGRADE_STRATEGY`` to "RAM_LOADING"
diff --git a/docs/user_guides/tfm_user_guide.rst b/docs/user_guides/tfm_user_guide.rst
index 754a99f..3035400 100644
--- a/docs/user_guides/tfm_user_guide.rst
+++ b/docs/user_guides/tfm_user_guide.rst
@@ -310,6 +310,150 @@
srec_cat app/secure_fw/tfm_s.bin -Binary -offset 0xA000000 app/tfm_ns.bin -Binary -offset 0xA060000 -o tfm.hex -Intel
+********************************************************
+Execute TF-M example and regression tests on MPS3 boards
+********************************************************
+
+To run the example code on CoreLink SSE-200 Subsystem for MPS3 (AN524)
+======================================================================
+FPGA image is available to download `here <https://www.arm.com/products/development-tools/development-boards/mps3>`__
+
+To run BL2 bootloader and TF-M example application and tests in the MPS3 board,
+it is required to have SMM-SSE-200 for MPS3 (AN524) image in the MPS3 board
+SD card. The image should be located in
+``<MPS3 device name>/MB/HBI<BoardNumberBoardrevision>/AN524``
+
+And the current boot memory for AN524 is QSPI flash, so you need to set the
+correct REMAP option in
+``<MPS3 device name>/MB/HBI<BoardNumberBoardrevision>/AN524/an524_v1.txt``
+
+::
+
+ REMAP: QSPI ;REMAP boot device BRAM/QSPI. Must match REMAPVAL below.
+ REMAPVAL: 1 ;REMAP register value e.g. 0-BRAM. 1-QSPI
+
+The MPS3 board tested is HBI0309B.
+
+.. Note::
+ If you change the exe names, MPS3 expects file names in 8.3 format.
+
+Example application
+-------------------
+#. Copy ``mcuboot.bin`` and ``tfm_sign.bin`` files from
+ build dir to ``<MPS3 device name>/SOFTWARE/``
+#. Open ``<MPS3 device name>/MB/HBI0309B/AN524/images.txt``
+#. Update the ``images.txt`` file as follows::
+
+ TITLE: Arm MPS3 FPGA prototyping board Images Configuration File
+
+ [IMAGES]
+ TOTALIMAGES: 2 ;Number of Images (Max: 32)
+
+ IMAGE0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+ IMAGE0ADDRESS: 0x00000000 ;Please select the required executable program
+ IMAGE0FILE: \SOFTWARE\mcuboot.bin
+ IMAGE1UPDATE: AUTO
+ IMAGE1ADDRESS: 0x00040000
+ IMAGE1FILE: \SOFTWARE\tfm_sign.bin
+
+#. Close ``<MPS3 device name>/MB/HBI0309B/AN524/images.txt``
+#. Unmount/eject the ``<MPS3 device name>`` unit
+#. Reset the board to execute the TF-M example application
+#. After completing the procedure you should be able to visualize on the serial
+ port (baud 115200 8n1) the following messages::
+
+ [INF] Starting bootloader
+ [INF] Image 0: magic= good, copy_done=0xff, image_ok=0xff
+ [INF] Scratch: magic=unset, copy_done=0x43, image_ok=0xff
+ [INF] Boot source: slot 0
+ [INF] Swap type: none
+ [INF] Bootloader chainload address offset: 0x40000
+ [INF] Jumping to the first image slot
+ [Sec Thread] Secure image initializing!
+
+Regression tests
+----------------
+After completing the procedure you should be able to visualize on the serial
+port (baud 115200 8n1) the following messages::
+
+ [INF] Starting bootloader
+ [INF] Image 0: magic= good, copy_done=0xff, image_ok=0xff
+ [INF] Scratch: magic=unset, copy_done=0x9, image_ok=0xff
+ [INF] Boot source: slot 0
+ [INF] Swap type: none
+ [INF] Bootloader chainload address offset: 0x40000
+ [INF] Jumping to the first image slot
+ [Sec Thread] Secure image initializing!
+
+ #### Execute test suites for the Secure area ####
+ Running Test Suite PSA protected storage S interface tests (TFM_SST_TEST_2XXX)...
+ > Executing 'TFM_SST_TEST_2001'
+ Description: 'Set interface'
+ TEST PASSED!
+ > Executing 'TFM_SST_TEST_2002'
+ Description: 'Set interface with create flags'
+ TEST PASSED!
+ > Executing 'TFM_SST_TEST_2003'
+ Description: 'Set interface with NULL data pointer'
+ TEST PASSED!
+ > Executing 'TFM_SST_TEST_2004'
+ Description: 'Set interface with invalid data length'
+ TEST PASSED!
+ ....
+
+.. Note::
+ Some of the attestation tests take a few minutes to run on the MPS3.
+
+Example application without BL2 bootloader
+------------------------------------------
+#. Copy ``tfm_s.bin`` and ``tfm_ns.bin`` files from
+ build dir to ``<MPS3 device name>/SOFTWARE/``
+#. Open ``<MPS3 device name>/MB/HBI0309B/AN524/images.txt``
+#. Update the ``images.txt`` file as follows::
+
+ TITLE: Arm MPS3 FPGA prototyping board Images Configuration File
+
+ [IMAGES]
+ TOTALIMAGES: 2 ;Number of Images (Max: 32)
+
+ IMAGE0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+ IMAGE0ADDRESS: 0x00000000 ;Please select the required executable program
+ IMAGE0FILE: \SOFTWARE\tfm_s.bin
+ IMAGE1UPDATE: AUTO
+ IMAGE1ADDRESS: 0x00080000
+ IMAGE1FILE: \SOFTWARE\tfm_ns.bin
+
+#. Close ``<MPS3 device name>/MB/HBI0309B/AN521/images.txt``
+#. Unmount/eject the ``<MPS3 device name>`` unit
+#. Reset the board to execute the TF-M example application
+#. After completing the procedure you should be able to visualize on the serial
+ port (baud 115200 8n1) the following messages::
+
+ [Sec Thread] Secure image initializing!
+
+Regression tests without BL2 bootloader
+---------------------------------------
+After completing the procedure you should be able to visualize on the serial
+port (baud 115200 8n1) the following messages::
+
+ [Sec Thread] Secure image initializing!
+
+ #### Execute test suites for the Secure area ####
+ Running Test Suite PSA protected storage S interface tests (TFM_SST_TEST_2XXX)...
+ > Executing 'TFM_SST_TEST_2001'
+ Description: 'Set interface'
+ TEST PASSED!
+ > Executing 'TFM_SST_TEST_2002'
+ Description: 'Set interface with create flags'
+ TEST PASSED!
+ > Executing 'TFM_SST_TEST_2003'
+ Description: 'Set interface with NULL data pointer'
+ TEST PASSED!
+ > Executing 'TFM_SST_TEST_2004'
+ Description: 'Set interface with invalid data length'
+ TEST PASSED!
+ ....
+
Firmware upgrade and image validation with BL2 bootloader
=========================================================
High level operation of BL2 bootloader and instructions for testing firmware
diff --git a/platform/ext/Mps3AN524.cmake b/platform/ext/Mps3AN524.cmake
new file mode 100644
index 0000000..0230d2e
--- /dev/null
+++ b/platform/ext/Mps3AN524.cmake
@@ -0,0 +1,195 @@
+#-------------------------------------------------------------------------------
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-------------------------------------------------------------------------------
+
+#This file gathers all MPS3/AN524 specific files in the application.
+
+#MPS3/AN524 has a Cortex-M33 CPU.
+include("Common/CpuM33")
+
+#Remap option for MPS3, default is BRAM
+set(REMAP_QSPI True)
+if (REMAP_QSPI)
+ add_definitions(-DREMAP_QSPI)
+endif()
+
+set(PLATFORM_DIR ${CMAKE_CURRENT_LIST_DIR})
+
+set(AN524_DIR ${PLATFORM_DIR}/target/mps3/an524)
+
+#Specify the location of platform specific build dependencies.
+if(COMPILER STREQUAL "ARMCLANG")
+ set (BL2_SCATTER_FILE_NAME "${AN524_DIR}/device/source/armclang/mps3_an524_bl2.sct")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/armclang/tfm_common_s.sct")
+ set (NS_SCATTER_FILE_NAME "${AN524_DIR}/device/source/armclang/mps3_an524_ns.sct")
+ if (DEFINED CMSIS_5_DIR)
+ # not all project defines CMSIS_5_DIR, only the ones that use it.
+ set (RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/ARM/RTX_V8MMN.lib")
+ endif()
+elseif(COMPILER STREQUAL "GNUARM")
+ set (BL2_SCATTER_FILE_NAME "${AN524_DIR}/device/source/gcc/mps3_an524_bl2.ld")
+ set (S_SCATTER_FILE_NAME "${PLATFORM_DIR}/common/gcc/tfm_common_s.ld")
+ set (NS_SCATTER_FILE_NAME "${AN524_DIR}/device/source/gcc/mps3_an524_ns.ld")
+ if (DEFINED CMSIS_5_DIR)
+ # Not all projects define CMSIS_5_DIR, only the ones that use it.
+ set(RTX_LIB_PATH "${CMSIS_5_DIR}/CMSIS/RTOS2/RTX/Library/GCC/libRTX_V8MMN.a")
+ endif()
+else()
+ message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+endif()
+set (FLASH_LAYOUT "${AN524_DIR}/partition/flash_layout.h")
+set (PLATFORM_LINK_INCLUDES "${AN524_DIR}/partition/")
+set (SIGN_BIN_SIZE 0x80000)
+
+if (BL2)
+ set (BL2_LINKER_CONFIG ${BL2_SCATTER_FILE_NAME})
+ if (NOT ${MCUBOOT_UPGRADE_STRATEGY} STREQUAL "NO_SWAP")
+ message(WARNING "NO_SWAP upgrade strategy is mandatory on target '${TARGET_PLATFORM}'. Your choice was overriden.")
+ set(MCUBOOT_UPGRADE_STRATEGY "NO_SWAP")
+ endif()
+endif()
+
+embedded_include_directories(PATH "${PLATFORM_DIR}/cmsis" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/target/mps3/common" ABSOLUTE)
+embedded_include_directories(PATH "${PLATFORM_DIR}/../include" ABSOLUTE)
+embedded_include_directories(PATH "${AN524_DIR}" ABSOLUTE)
+embedded_include_directories(PATH "${AN524_DIR}/partition" ABSOLUTE)
+embedded_include_directories(PATH "${AN524_DIR}/device/include" ABSOLUTE)
+embedded_include_directories(PATH "${AN524_DIR}/device/config" ABSOLUTE)
+embedded_include_directories(PATH "${AN524_DIR}/cmsis_drivers/config" ABSOLUTE)
+embedded_include_directories(PATH "${AN524_DIR}/native_drivers" ABSOLUTE)
+
+#Gather all source files we need.
+if (NOT DEFINED BUILD_CMSIS_CORE)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_CORE (true|false) is undefined!")
+elseif(BUILD_CMSIS_CORE)
+ list(APPEND ALL_SRC_C "${AN524_DIR}/device/source/system_core_init.c")
+endif()
+
+if (NOT DEFINED BUILD_RETARGET)
+ message(FATAL_ERROR "Configuration variable BUILD_RETARGET (true|false) is undefined!")
+elseif(BUILD_RETARGET)
+ list(APPEND ALL_SRC_C "${AN524_DIR}/device/source/device_definition.c")
+endif()
+
+if (NOT DEFINED BUILD_UART_STDOUT)
+ message(FATAL_ERROR "Configuration variable BUILD_UART_STDOUT (true|false) is undefined!")
+elseif(BUILD_UART_STDOUT)
+ if (NOT DEFINED SECURE_UART1)
+ message(FATAL_ERROR "Configuration variable SECURE_UART1 (true|false) is undefined!")
+ elseif(SECURE_UART1)
+ message(FATAL_ERROR "Configuration SECURE_UART1 TRUE is invalid for this target!")
+ endif()
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/uart_stdout.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+ set(BUILD_NATIVE_DRIVERS true)
+ set(BUILD_CMSIS_DRIVERS true)
+endif()
+
+if (NOT DEFINED BUILD_NATIVE_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_NATIVE_DRIVERS (true|false) is undefined!")
+elseif(BUILD_NATIVE_DRIVERS)
+ list(APPEND ALL_SRC_C "${AN524_DIR}/native_drivers/uart_cmsdk_drv.c")
+
+ list(APPEND ALL_SRC_C_S "${AN524_DIR}/native_drivers/mpc_sie200_drv.c"
+ "${AN524_DIR}/native_drivers/ppc_sse200_drv.c")
+endif()
+
+if (NOT DEFINED BUILD_TIME)
+ message(FATAL_ERROR "Configuration variable BUILD_TIME (true|false) is undefined!")
+elseif(BUILD_TIME)
+ list(APPEND ALL_SRC_C "${AN524_DIR}/native_drivers/timer_cmsdk_drv.c")
+endif()
+
+if (NOT DEFINED BUILD_STARTUP)
+ message(FATAL_ERROR "Configuration variable BUILD_STARTUP (true|false) is undefined!")
+elseif(BUILD_STARTUP)
+ if(CMAKE_C_COMPILER_ID STREQUAL "ARMCLANG")
+ list(APPEND ALL_SRC_ASM_S "${AN524_DIR}/device/source/armclang/startup_cmsdk_mps3_an524_s.s")
+ list(APPEND ALL_SRC_ASM_NS "${AN524_DIR}/device/source/armclang/startup_cmsdk_mps3_an524_ns.s")
+ list(APPEND ALL_SRC_ASM_BL2 "${AN524_DIR}/device/source/armclang/startup_cmsdk_mps3_an524_bl2.s")
+ elseif(CMAKE_C_COMPILER_ID STREQUAL "GNUARM")
+ list(APPEND ALL_SRC_ASM_S "${AN524_DIR}/device/source/gcc/startup_cmsdk_mps3_an524_s.S")
+ list(APPEND ALL_SRC_ASM_NS "${AN524_DIR}/device/source/gcc/startup_cmsdk_mps3_an524_ns.S")
+ list(APPEND ALL_SRC_ASM_BL2 "${AN524_DIR}/device/source/gcc/startup_cmsdk_mps3_an524_bl2.S")
+ set_property(SOURCE "${ALL_SRC_ASM_S}" "${ALL_SRC_ASM_NS}" "${ALL_SRC_ASM_BL2}" APPEND
+ PROPERTY COMPILE_DEFINITIONS "__STARTUP_CLEAR_BSS_MULTIPLE" "__STARTUP_COPY_MULTIPLE")
+ else()
+ message(FATAL_ERROR "No startup file is available for compiler '${CMAKE_C_COMPILER_ID}'.")
+ endif()
+endif()
+
+if (NOT DEFINED BUILD_TARGET_CFG)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_CFG (true|false) is undefined!")
+elseif(BUILD_TARGET_CFG)
+ list(APPEND ALL_SRC_C "${AN524_DIR}/target_cfg.c")
+ list(APPEND ALL_SRC_C_S "${AN524_DIR}/spm_hal.c")
+ list(APPEND ALL_SRC_C_S "${AN524_DIR}/attest_hal.c")
+ list(APPEND ALL_SRC_C_S "${AN524_DIR}/native_drivers/mpu_armv8m_drv.c")
+ list(APPEND ALL_SRC_C_S "${AN524_DIR}/services/src/tfm_platform_system.c")
+ embedded_include_directories(PATH "${PLATFORM_DIR}/common" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_TARGET_HARDWARE_KEYS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_HARDWARE_KEYS (true|false) is undefined!")
+elseif(BUILD_TARGET_HARDWARE_KEYS)
+ list(APPEND ALL_SRC_C "${PLATFORM_DIR}/common/tfm_initial_attestation_key_material.c")
+ list(APPEND ALL_SRC_C "${AN524_DIR}/dummy_crypto_keys.c")
+endif()
+
+if (NOT DEFINED BUILD_TARGET_NV_COUNTERS)
+ message(FATAL_ERROR "Configuration variable BUILD_TARGET_NV_COUNTERS (true|false) is undefined!")
+elseif (BUILD_TARGET_NV_COUNTERS)
+ # NOTE: This non-volatile counters implementation is a dummy
+ # implementation. Platform vendors have to implement the
+ # API ONLY if the target has non-volatile counters.
+ list(APPEND ALL_SRC_C "${AN524_DIR}/dummy_nv_counters.c")
+ set(TARGET_NV_COUNTERS_ENABLE ON)
+ # Sets SST_ROLLBACK_PROTECTION flag to compile in the SST services
+ # rollback protection code as the target supports nv counters.
+ set(SST_ROLLBACK_PROTECTION ON)
+endif()
+
+if (NOT DEFINED BUILD_CMSIS_DRIVERS)
+ message(FATAL_ERROR "Configuration variable BUILD_CMSIS_DRIVERS (true|false) is undefined!")
+elseif(BUILD_CMSIS_DRIVERS)
+ list(APPEND ALL_SRC_C_S "${AN524_DIR}/cmsis_drivers/Driver_MPC.c"
+ "${AN524_DIR}/cmsis_drivers/Driver_PPC.c")
+ list(APPEND ALL_SRC_C "${AN524_DIR}/cmsis_drivers/Driver_USART.c")
+ embedded_include_directories(PATH "${AN524_DIR}/cmsis_drivers" ABSOLUTE)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/driver" ABSOLUTE)
+endif()
+
+if (NOT DEFINED BUILD_FLASH)
+ message(FATAL_ERROR "Configuration variable BUILD_FLASH (true|false) is undefined!")
+elseif(BUILD_FLASH)
+ list(APPEND ALL_SRC_C "${AN524_DIR}/cmsis_drivers/Driver_Flash.c")
+ # For AN524 currently BRAM is used for SST The Driver_Flash driver just emulates a flash
+ # interface and behaviour on top of the BRAM memory.
+ # As the SST area is going to be in RAM, it is required to set SST_CREATE_FLASH_LAYOUT
+ # to be sure the SST service knows that when it starts the SST area does not contain any
+ # valid SST flash layout and it needs to create one.
+ set(SST_CREATE_FLASH_LAYOUT ON)
+ set(SST_RAM_FS OFF)
+ embedded_include_directories(PATH "${AN524_DIR}/cmsis_drivers" ABSOLUTE)
+ embedded_include_directories(PATH "${PLATFORM_DIR}/driver" ABSOLUTE)
+endif()
+
+if (MCUBOOT_RAM_LOADING)
+ message (FATAL_ERROR "MCUBOOT_RAM_LOADING is not supported on " ${TARGET_PLATFORM})
+endif()
+
+if (NOT DEFINED BUILD_BOOT_SEED)
+ message(FATAL_ERROR "Configuration variable BUILD_BOOT_SEED (true|false) is undefined!")
+elseif(BUILD_BOOT_SEED)
+ list(APPEND ALL_SRC_C "${AN524_DIR}/dummy_boot_seed.c")
+endif()
+
+if (NOT DEFINED BUILD_DEVICE_ID)
+ message(FATAL_ERROR "Configuration variable BUILD_DEVICE_ID (true|false) is undefined!")
+elseif(BUILD_DEVICE_ID)
+ list(APPEND ALL_SRC_C "${AN524_DIR}/dummy_device_id.c")
+endif()
diff --git a/platform/ext/common/armclang/tfm_common_s.sct b/platform/ext/common/armclang/tfm_common_s.sct
index 141c6a9..318481d 100644
--- a/platform/ext/common/armclang/tfm_common_s.sct
+++ b/platform/ext/common/armclang/tfm_common_s.sct
@@ -86,6 +86,7 @@
*Driver_USART.* (+RO)
*arm_uart_drv.* (+RO)
*uart_pl011_drv.* (+RO)
+ *uart_cmsdk_drv* (+RO)
*secure_suites.* (+RO)
*attestation_s_interface_testsuite.* (+RO)
*(TFM_SP_SECURE_TEST_PARTITION_ATTR_FN)
@@ -252,6 +253,7 @@
*Driver_USART.* (+RW +ZI)
*arm_uart_drv.* (+RW +ZI)
*uart_pl011_drv.* (+RW +ZI)
+ *uart_cmsdk_drv* (+RW +ZI)
*secure_suites.* (+RW +ZI)
*attestation_s_interface_testsuite.* (+RW +ZI)
}
diff --git a/platform/ext/common/gcc/tfm_common_s.ld b/platform/ext/common/gcc/tfm_common_s.ld
index f790182..72211c6 100644
--- a/platform/ext/common/gcc/tfm_common_s.ld
+++ b/platform/ext/common/gcc/tfm_common_s.ld
@@ -321,6 +321,8 @@
*arm_uart_drv.*(.rodata*)
*uart_pl011_drv.*(.text*)
*uart_pl011_drv.*(.rodata*)
+ *uart_cmsdk_drv*(.text*)
+ *uart_cmsdk_drv*(.rodata*)
*secure_suites.*(.text*)
*secure_suites.*(.rodata*)
*attestation_s_interface_testsuite.*(.text*)
@@ -684,6 +686,7 @@
*Driver_USART.*(.data*)
*arm_uart_drv.*(.data*)
*uart_pl011_drv.*(.data*)
+ *uart_cmsdk_drv*(.data*)
*secure_suites.*(.data*)
*attestation_s_interface_testsuite.*(.data*)
. = ALIGN(32);
@@ -705,6 +708,8 @@
*arm_uart_drv.*(COMMON)
*uart_pl011_drv.*(.bss*)
*uart_pl011_drv.*(COMMON)
+ *uart_cmsdk_drv*(.bss*)
+ *uart_cmsdk_drv*(COMMON)
*secure_suites.*(.bss*)
*secure_suites.*(COMMON)
*attestation_s_interface_testsuite.*(.bss*)
diff --git a/platform/ext/target/mps3/an524/attest_hal.c b/platform/ext/target/mps3/an524/attest_hal.c
new file mode 100644
index 0000000..d4d2407
--- /dev/null
+++ b/platform/ext/target/mps3/an524/attest_hal.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "platform/include/tfm_attest_hal.h"
+#include <stdint.h>
+
+/* Example verification service URL for initial attestation token */
+static const char verification_service_url[] = "www.trustedfirmware.org";
+
+/* Example profile definition document for initial attestation token */
+static const char attestation_profile_definition[] = "PSA_IOT_PROFILE_1";
+
+enum tfm_security_lifecycle_t tfm_attest_hal_get_security_lifecycle(void)
+{
+ return TFM_SLC_SECURED;
+}
+
+const char *
+tfm_attest_hal_get_verification_service(uint32_t *size)
+{
+ *size = sizeof(verification_service_url) - 1;
+
+ return verification_service_url;
+}
+
+const char *
+tfm_attest_hal_get_profile_definition(uint32_t *size)
+{
+ *size = sizeof(attestation_profile_definition) - 1;
+
+ return attestation_profile_definition;
+}
diff --git a/platform/ext/target/mps3/an524/cmsis_drivers/Driver_Flash.c b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_Flash.c
new file mode 100644
index 0000000..623f943
--- /dev/null
+++ b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_Flash.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* This file is a derivative of a previous version of
+ * platform/ext/target/musca_b1/CMSIS_Driver/Driver_Flash.c
+ * Git SHA: 9f3da0b83e45e6d26ad0be45c090d2e4382fb04f
+ */
+
+/* FIXME: This interim flash driver uses BRAM to emulate flash for SST.
+ * Code is still running on QSPI, and only direct read is supported,
+ * write is not supported yet.
+ * It should be replaced with a real flash driver.
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include "Driver_Flash.h"
+#include "RTE_Device.h"
+#include "flash_layout.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) ((void)arg)
+#endif
+
+/* Driver version */
+#define ARM_FLASH_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)
+
+#define FLASH_REDIRECT_BASE SST_FLASH_AREA_ADDR
+#define FLASH_REDIRECT_LIMIT (FLASH_REDIRECT_BASE \
+ + SST_FLASH_AREA_SIZE \
+ + FLASH_NV_COUNTERS_AREA_SIZE)
+#define FLASH_REDIRECT_DEST 0x38000000
+
+#define FLASH0_BASE_S 0x10000000
+#define FLASH0_BASE_NS 0x00000000
+#define FLASH0_SIZE 0x00800000 /* 8 MB */
+#define FLASH0_SECTOR_SIZE 0x00001000 /* 4 kB */
+#define FLASH0_PAGE_SIZE 0x00001000 /* 4 kB */
+#define FLASH0_PROGRAM_UNIT 0x1 /* Minimum write size */
+
+/*
+ * ARM FLASH device structure
+ */
+struct arm_flash_dev_t {
+ const uint32_t memory_base; /*!< FLASH memory base address */
+ ARM_FLASH_INFO *data; /*!< FLASH data */
+};
+
+/* Flash Status */
+static ARM_FLASH_STATUS FlashStatus = {0, 0, 0};
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_FLASH_API_VERSION,
+ ARM_FLASH_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_FLASH_CAPABILITIES DriverCapabilities = {
+ 0, /* event_ready */
+ 2, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
+ 1 /* erase_chip */
+};
+
+static int32_t is_range_valid(struct arm_flash_dev_t *flash_dev,
+ uint32_t offset)
+{
+ uint32_t flash_limit = 0;
+ int32_t rc = 0;
+
+ flash_limit = (flash_dev->data->sector_count * flash_dev->data->sector_size)
+ - 1;
+
+ if (offset > flash_limit) {
+ rc = -1;
+ }
+ return rc;
+}
+
+static int32_t is_write_aligned(struct arm_flash_dev_t *flash_dev,
+ uint32_t param)
+{
+ int32_t rc = 0;
+
+ if ((param % flash_dev->data->program_unit) != 0) {
+ rc = -1;
+ }
+ return rc;
+}
+
+static int32_t is_sector_aligned(struct arm_flash_dev_t *flash_dev,
+ uint32_t offset)
+{
+ int32_t rc = 0;
+
+ if ((offset % flash_dev->data->sector_size) != 0) {
+ rc = -1;
+ }
+ return rc;
+}
+
+#if (RTE_FLASH0)
+static ARM_FLASH_INFO ARM_FLASH0_DEV_DATA = {
+ .sector_info = NULL, /* Uniform sector layout */
+ .sector_count = FLASH0_SIZE / FLASH0_SECTOR_SIZE,
+ .sector_size = FLASH0_SECTOR_SIZE,
+ .page_size = FLASH0_PAGE_SIZE,
+ .program_unit = FLASH0_PROGRAM_UNIT,
+ .erased_value = 0xFF};
+
+static struct arm_flash_dev_t ARM_FLASH0_DEV = {
+#if (__DOMAIN_NS == 1)
+ .memory_base = FLASH0_BASE_NS,
+#else
+ .memory_base = FLASH0_BASE_S,
+#endif /* __DOMAIN_NS == 1 */
+ .data = &(ARM_FLASH0_DEV_DATA)};
+
+struct arm_flash_dev_t *FLASH0_DEV = &ARM_FLASH0_DEV;
+
+/*
+ * Functions
+ */
+
+static ARM_DRIVER_VERSION ARM_Flash_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+static int32_t ARM_Flash_Initialize(ARM_Flash_SignalEvent_t cb_event)
+{
+ ARG_UNUSED(cb_event);
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_PowerControl(ARM_POWER_STATE state)
+{
+ switch (state) {
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ break;
+
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+}
+
+static int32_t ARM_Flash_ReadData(uint32_t addr, void *data, uint32_t cnt)
+{
+ volatile uint32_t mem_base = FLASH0_DEV->memory_base;
+ uint32_t start_addr = mem_base + addr;
+ int32_t rc = 0;
+
+ /* Check flash memory boundaries */
+ rc = is_range_valid(FLASH0_DEV, addr + cnt);
+ if (rc != 0) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Redirecting SST storage to BRAM */
+ if (addr >= FLASH_REDIRECT_BASE && addr <= FLASH_REDIRECT_LIMIT) {
+ start_addr = FLASH_REDIRECT_DEST + (addr - FLASH_REDIRECT_BASE);
+ }
+
+ memcpy(data, (void *)start_addr, cnt);
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_ProgramData(uint32_t addr, const void *data,
+ uint32_t cnt)
+{
+ volatile uint32_t mem_base = FLASH0_DEV->memory_base;
+ uint32_t start_addr = mem_base + addr;
+ int32_t rc = 0;
+
+ /* Check flash memory boundaries and alignment with minimal write size */
+ rc = is_range_valid(FLASH0_DEV, addr + cnt);
+ rc |= is_write_aligned(FLASH0_DEV, addr);
+ rc |= is_write_aligned(FLASH0_DEV, cnt);
+ if (rc != 0) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Redirecting SST storage to BRAM */
+ if (addr >= FLASH_REDIRECT_BASE && addr <= FLASH_REDIRECT_LIMIT) {
+ start_addr = FLASH_REDIRECT_DEST + (addr - FLASH_REDIRECT_BASE);
+ /* SST Flash is emulated over BRAM. use memcpy function. */
+ memcpy((void *)start_addr, data, cnt);
+ } else {
+ /* Flash driver for QSPI is not ready */
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_EraseSector(uint32_t addr)
+{
+ uint32_t rc = 0;
+
+ rc = is_range_valid(FLASH0_DEV, addr);
+ rc |= is_sector_aligned(FLASH0_DEV, addr);
+ if (rc != 0) {
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Redirecting SST storage to BRAM */
+ if (addr >= FLASH_REDIRECT_BASE && addr <= FLASH_REDIRECT_LIMIT) {
+ /* SST Flash IS emulated over BRAM. use memcpy function. */
+ memset((void *)(FLASH_REDIRECT_DEST
+ + (addr - FLASH_REDIRECT_BASE)),
+ FLASH0_DEV->data->erased_value,
+ FLASH0_DEV->data->sector_size);
+ } else {
+ /* Flash driver for QSPI is not ready */
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_Flash_EraseChip(void)
+{
+ uint32_t i;
+ uint32_t addr = FLASH0_DEV->memory_base;
+ int32_t rc = ARM_DRIVER_ERROR_UNSUPPORTED;
+
+ /* Check driver capability erase_chip bit */
+ if (DriverCapabilities.erase_chip == 1) {
+ for (i = 0; i < FLASH0_DEV->data->sector_count; i++) {
+ /* Redirecting SST storage to BRAM */
+ if (addr >= FLASH_REDIRECT_BASE && addr <= FLASH_REDIRECT_LIMIT) {
+ memset((void *)(FLASH_REDIRECT_DEST +
+ (addr - FLASH0_DEV->memory_base - FLASH_REDIRECT_BASE)),
+ FLASH0_DEV->data->erased_value,
+ FLASH0_DEV->data->sector_size);
+ }
+ /* else {
+ * Flash driver for QSPI is not ready, fall through.
+ * }
+ */
+
+ addr += FLASH0_DEV->data->sector_size;
+ rc = ARM_DRIVER_OK;
+ }
+ }
+ return rc;
+}
+
+static ARM_FLASH_STATUS ARM_Flash_GetStatus(void)
+{
+ return FlashStatus;
+}
+
+static ARM_FLASH_INFO *ARM_Flash_GetInfo(void)
+{
+ return FLASH0_DEV->data;
+}
+
+ARM_DRIVER_FLASH Driver_FLASH0 = {
+ ARM_Flash_GetVersion,
+ ARM_Flash_GetCapabilities,
+ ARM_Flash_Initialize,
+ ARM_Flash_Uninitialize,
+ ARM_Flash_PowerControl,
+ ARM_Flash_ReadData,
+ ARM_Flash_ProgramData,
+ ARM_Flash_EraseSector,
+ ARM_Flash_EraseChip,
+ ARM_Flash_GetStatus,
+ ARM_Flash_GetInfo
+};
+#endif /* RTE_FLASH0 */
diff --git a/platform/ext/target/mps3/an524/cmsis_drivers/Driver_MPC.c b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_MPC.c
new file mode 100644
index 0000000..5894ad8
--- /dev/null
+++ b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_MPC.c
@@ -0,0 +1,1750 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_MPC.h"
+
+#include "cmsis_driver_config.h"
+#include "RTE_Device.h"
+
+/* driver version */
+#define ARM_MPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_MPC_API_VERSION,
+ ARM_MPC_DRV_VERSION
+};
+
+static ARM_DRIVER_VERSION ARM_MPC_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+/*
+ * \brief Translates error codes from native API to CMSIS API.
+ *
+ * \param[in] err Error code to translate (\ref mpc_sie200_error_t).
+ *
+ * \return Returns CMSIS error code.
+ */
+static int32_t error_trans(enum mpc_sie200_error_t err)
+{
+ switch(err) {
+ case MPC_SIE200_ERR_NONE:
+ return ARM_DRIVER_OK;
+ case MPC_SIE200_INVALID_ARG:
+ return ARM_DRIVER_ERROR_PARAMETER;
+ case MPC_SIE200_NOT_INIT:
+ return ARM_MPC_ERR_NOT_INIT;
+ case MPC_SIE200_ERR_NOT_IN_RANGE:
+ return ARM_MPC_ERR_NOT_IN_RANGE;
+ case MPC_SIE200_ERR_NOT_ALIGNED:
+ return ARM_MPC_ERR_NOT_ALIGNED;
+ case MPC_SIE200_ERR_INVALID_RANGE:
+ return ARM_MPC_ERR_INVALID_RANGE;
+ case MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE:
+ return ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE;
+ default:
+ return ARM_MPC_ERR_UNSPECIFIED;
+ }
+}
+
+#if (RTE_ISRAM0_MPC)
+/* Ranges controlled by this ISRAM0_MPC */
+static const struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_S = {
+ .base = MPC_ISRAM0_RANGE_BASE_S,
+ .limit = MPC_ISRAM0_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_NS = {
+ .base = MPC_ISRAM0_RANGE_BASE_NS,
+ .limit = MPC_ISRAM0_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM0_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_ISRAM0_RANGE_LIST[MPC_ISRAM0_RANGE_LIST_LEN] = {
+ &MPC_ISRAM0_RANGE_S,
+ &MPC_ISRAM0_RANGE_NS
+ };
+
+/* ISRAM0_MPC Driver wrapper functions */
+static int32_t ISRAM0_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM0_DEV,
+ MPC_ISRAM0_RANGE_LIST,
+ MPC_ISRAM0_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM0_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM0_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM0_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM0_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t*)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM0_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM0_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM0_DEV);
+
+ return error_trans(ret);
+}
+
+static void ISRAM0_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM0_DEV);
+}
+
+
+static void ISRAM0_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM0_DEV);
+}
+
+static uint32_t ISRAM0_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM0_DEV);
+}
+
+static int32_t ISRAM0_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM0_DEV);
+}
+
+/* ISRAM0_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM0_MPC;
+ARM_DRIVER_MPC Driver_ISRAM0_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM0_MPC_Initialize,
+ .Uninitialize = ISRAM0_MPC_Uninitialize,
+ .GetBlockSize = ISRAM0_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM0_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM0_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM0_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM0_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM0_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM0_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM0_MPC_ClearInterrupt,
+ .InterruptState = ISRAM0_MPC_InterruptState,
+ .LockDown = ISRAM0_MPC_LockDown,
+};
+#endif /* RTE_ISRAM0_MPC */
+
+#if (RTE_ISRAM1_MPC)
+/* Ranges controlled by this ISRAM1_MPC */
+static const struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_S = {
+ .base = MPC_ISRAM1_RANGE_BASE_S,
+ .limit = MPC_ISRAM1_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_NS = {
+ .base = MPC_ISRAM1_RANGE_BASE_NS,
+ .limit = MPC_ISRAM1_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_ISRAM1_RANGE_LIST[MPC_ISRAM1_RANGE_LIST_LEN] = {
+ &MPC_ISRAM1_RANGE_S,
+ &MPC_ISRAM1_RANGE_NS
+ };
+
+/* ISRAM1_MPC Driver wrapper functions */
+static int32_t ISRAM1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM1_DEV,
+ MPC_ISRAM1_RANGE_LIST,
+ MPC_ISRAM1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM1_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM1_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM1_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM1_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM1_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM1_DEV);
+
+ return error_trans(ret);
+}
+
+static void ISRAM1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM1_DEV);
+}
+
+
+static void ISRAM1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM1_DEV);
+}
+
+static uint32_t ISRAM1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM1_DEV);
+}
+
+static int32_t ISRAM1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM1_DEV);
+}
+
+/* ISRAM1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM1_MPC;
+ARM_DRIVER_MPC Driver_ISRAM1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM1_MPC_Initialize,
+ .Uninitialize = ISRAM1_MPC_Uninitialize,
+ .GetBlockSize = ISRAM1_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM1_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM1_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM1_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM1_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM1_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM1_MPC_ClearInterrupt,
+ .InterruptState = ISRAM1_MPC_InterruptState,
+ .LockDown = ISRAM1_MPC_LockDown,
+};
+#endif /* RTE_ISRAM1_MPC */
+
+#if (RTE_ISRAM2_MPC)
+/* Ranges controlled by this ISRAM2_MPC */
+static const struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_S = {
+ .base = MPC_ISRAM2_RANGE_BASE_S,
+ .limit = MPC_ISRAM2_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_NS = {
+ .base = MPC_ISRAM2_RANGE_BASE_NS,
+ .limit = MPC_ISRAM2_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM2_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_ISRAM2_RANGE_LIST[MPC_ISRAM2_RANGE_LIST_LEN] = {
+ &MPC_ISRAM2_RANGE_S,
+ &MPC_ISRAM2_RANGE_NS
+ };
+
+/* ISRAM2_MPC Driver wrapper functions */
+static int32_t ISRAM2_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM2_DEV,
+ MPC_ISRAM2_RANGE_LIST,
+ MPC_ISRAM2_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM2_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM2_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM2_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM2_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM2_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM2_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM2_DEV);
+
+ return error_trans(ret);
+}
+
+static void ISRAM2_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM2_DEV);
+}
+
+static void ISRAM2_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM2_DEV);
+}
+
+static uint32_t ISRAM2_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM2_DEV);
+}
+
+static int32_t ISRAM2_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM2_DEV);
+}
+
+/* ISRAM2_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM2_MPC;
+ARM_DRIVER_MPC Driver_ISRAM2_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM2_MPC_Initialize,
+ .Uninitialize = ISRAM2_MPC_Uninitialize,
+ .GetBlockSize = ISRAM2_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM2_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM2_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM2_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM2_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM2_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM2_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM2_MPC_ClearInterrupt,
+ .InterruptState = ISRAM2_MPC_InterruptState,
+ .LockDown = ISRAM2_MPC_LockDown,
+};
+#endif /* RTE_ISRAM2_MPC */
+
+#if (RTE_ISRAM3_MPC)
+/* Ranges controlled by this ISRAM3_MPC */
+static const struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_S = {
+ .base = MPC_ISRAM3_RANGE_BASE_S,
+ .limit = MPC_ISRAM3_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_NS = {
+ .base = MPC_ISRAM3_RANGE_BASE_NS,
+ .limit = MPC_ISRAM3_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_ISRAM3_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_ISRAM3_RANGE_LIST[MPC_ISRAM3_RANGE_LIST_LEN] = {
+ &MPC_ISRAM3_RANGE_S,
+ &MPC_ISRAM3_RANGE_NS
+ };
+
+/* ISRAM3_MPC Driver wrapper functions */
+static int32_t ISRAM3_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_ISRAM3_DEV,
+ MPC_ISRAM3_RANGE_LIST,
+ MPC_ISRAM3_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ISRAM3_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_ISRAM3_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_ISRAM3_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_ISRAM3_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_ISRAM3_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t ISRAM3_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_ISRAM3_DEV);
+
+ return error_trans(ret);
+}
+
+static void ISRAM3_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_ISRAM3_DEV);
+}
+
+
+static void ISRAM3_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_ISRAM3_DEV);
+}
+
+static uint32_t ISRAM3_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_ISRAM3_DEV);
+}
+
+static int32_t ISRAM3_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_ISRAM3_DEV);
+}
+
+/* ISRAM3_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_ISRAM3_MPC;
+ARM_DRIVER_MPC Driver_ISRAM3_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = ISRAM3_MPC_Initialize,
+ .Uninitialize = ISRAM3_MPC_Uninitialize,
+ .GetBlockSize = ISRAM3_MPC_GetBlockSize,
+ .GetCtrlConfig = ISRAM3_MPC_GetCtrlConfig,
+ .SetCtrlConfig = ISRAM3_MPC_SetCtrlConfig,
+ .ConfigRegion = ISRAM3_MPC_ConfigRegion,
+ .GetRegionConfig = ISRAM3_MPC_GetRegionConfig,
+ .EnableInterrupt = ISRAM3_MPC_EnableInterrupt,
+ .DisableInterrupt = ISRAM3_MPC_DisableInterrupt,
+ .ClearInterrupt = ISRAM3_MPC_ClearInterrupt,
+ .InterruptState = ISRAM3_MPC_InterruptState,
+ .LockDown = ISRAM3_MPC_LockDown,
+};
+#endif /* RTE_ISRAM3_MPC */
+
+#if (RTE_CODE_SRAM_MPC)
+/* Ranges controlled by this CODE_SRAM_MPC */
+static const struct mpc_sie200_memory_range_t MPC_CODE_SRAM_RANGE_S = {
+ .base = MPC_CODE_SRAM_RANGE_BASE_S,
+ .limit = MPC_CODE_SRAM_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_CODE_SRAM_RANGE_NS = {
+ .base = MPC_CODE_SRAM_RANGE_BASE_NS,
+ .limit = MPC_CODE_SRAM_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_CODE_SRAM_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_CODE_SRAM_RANGE_LIST[MPC_CODE_SRAM_RANGE_LIST_LEN] = {
+ &MPC_CODE_SRAM_RANGE_S,
+ &MPC_CODE_SRAM_RANGE_NS
+ };
+
+/* CODE_SRAM_MPC Driver wrapper functions */
+static int32_t CODE_SRAM_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_CODE_SRAM_DEV,
+ MPC_CODE_SRAM_RANGE_LIST,
+ MPC_CODE_SRAM_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t CODE_SRAM_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t CODE_SRAM_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t CODE_SRAM_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t CODE_SRAM_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t CODE_SRAM_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t CODE_SRAM_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_CODE_SRAM_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t CODE_SRAM_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM_DEV);
+
+ return error_trans(ret);
+}
+
+static void CODE_SRAM_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_CODE_SRAM_DEV);
+}
+
+
+static void CODE_SRAM_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_CODE_SRAM_DEV);
+}
+
+static uint32_t CODE_SRAM_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_CODE_SRAM_DEV);
+}
+
+static int32_t CODE_SRAM_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_CODE_SRAM_DEV);
+}
+
+/* CODE_SRAM_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_CODE_SRAM_MPC;
+ARM_DRIVER_MPC Driver_CODE_SRAM_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = CODE_SRAM_MPC_Initialize,
+ .Uninitialize = CODE_SRAM_MPC_Uninitialize,
+ .GetBlockSize = CODE_SRAM_MPC_GetBlockSize,
+ .GetCtrlConfig = CODE_SRAM_MPC_GetCtrlConfig,
+ .SetCtrlConfig = CODE_SRAM_MPC_SetCtrlConfig,
+ .ConfigRegion = CODE_SRAM_MPC_ConfigRegion,
+ .GetRegionConfig = CODE_SRAM_MPC_GetRegionConfig,
+ .EnableInterrupt = CODE_SRAM_MPC_EnableInterrupt,
+ .DisableInterrupt = CODE_SRAM_MPC_DisableInterrupt,
+ .ClearInterrupt = CODE_SRAM_MPC_ClearInterrupt,
+ .InterruptState = CODE_SRAM_MPC_InterruptState,
+ .LockDown = CODE_SRAM_MPC_LockDown,
+};
+#endif /* RTE_CODE_SRAM_MPC */
+
+#if (RTE_SSRAM1_MPC)
+/* Ranges controlled by this SSRAM1_MPC */
+static const struct mpc_sie200_memory_range_t MPC_SSRAM1_RANGE_S = {
+ .base = MPC_SSRAM1_RANGE_BASE_S,
+ .limit = MPC_SSRAM1_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_SSRAM1_RANGE_NS = {
+ .base = MPC_SSRAM1_RANGE_BASE_NS,
+ .limit = MPC_SSRAM1_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_SSRAM1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_SSRAM1_RANGE_LIST[MPC_SSRAM1_RANGE_LIST_LEN] = {
+ &MPC_SSRAM1_RANGE_S,
+ &MPC_SSRAM1_RANGE_NS
+ };
+
+/* SSRAM1_MPC Driver wrapper functions */
+static int32_t SSRAM1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_SSRAM1_DEV,
+ MPC_SSRAM1_RANGE_LIST,
+ MPC_SSRAM1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SSRAM1_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_SSRAM1_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_SSRAM1_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_SSRAM1_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_SSRAM1_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_SSRAM1_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_SSRAM1_DEV);
+
+ return error_trans(ret);
+}
+
+static void SSRAM1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_SSRAM1_DEV);
+}
+
+
+static void SSRAM1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_SSRAM1_DEV);
+}
+
+static uint32_t SSRAM1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_SSRAM1_DEV);
+}
+
+static int32_t SSRAM1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_SSRAM1_DEV);
+}
+
+/* SSRAM1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
+ARM_DRIVER_MPC Driver_SRAM1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SSRAM1_MPC_Initialize,
+ .Uninitialize = SSRAM1_MPC_Uninitialize,
+ .GetBlockSize = SSRAM1_MPC_GetBlockSize,
+ .GetCtrlConfig = SSRAM1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SSRAM1_MPC_SetCtrlConfig,
+ .ConfigRegion = SSRAM1_MPC_ConfigRegion,
+ .GetRegionConfig = SSRAM1_MPC_GetRegionConfig,
+ .EnableInterrupt = SSRAM1_MPC_EnableInterrupt,
+ .DisableInterrupt = SSRAM1_MPC_DisableInterrupt,
+ .ClearInterrupt = SSRAM1_MPC_ClearInterrupt,
+ .InterruptState = SSRAM1_MPC_InterruptState,
+ .LockDown = SSRAM1_MPC_LockDown,
+};
+#endif /* RTE_SSRAM1_MPC */
+
+#if (RTE_SSRAM2_MPC)
+/* Ranges controlled by this SSRAM2_MPC */
+static const struct mpc_sie200_memory_range_t MPC_SSRAM2_RANGE_S = {
+ .base = MPC_SSRAM2_RANGE_BASE_S,
+ .limit = MPC_SSRAM2_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_SSRAM2_RANGE_NS = {
+ .base = MPC_SSRAM2_RANGE_BASE_NS,
+ .limit = MPC_SSRAM2_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_SSRAM2_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_SSRAM2_RANGE_LIST[MPC_SSRAM2_RANGE_LIST_LEN] = {
+ &MPC_SSRAM2_RANGE_S,
+ &MPC_SSRAM2_RANGE_NS
+ };
+
+/* SSRAM2_MPC Driver wrapper functions */
+static int32_t SSRAM2_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_SSRAM2_DEV,
+ MPC_SSRAM2_RANGE_LIST,
+ MPC_SSRAM2_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM2_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SSRAM2_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_SSRAM2_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM2_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_SSRAM2_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM2_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_SSRAM2_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM2_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_SSRAM2_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM2_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_SSRAM2_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM2_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_SSRAM2_DEV);
+
+ return error_trans(ret);
+}
+
+static void SSRAM2_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_SSRAM2_DEV);
+}
+
+
+static void SSRAM2_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_SSRAM2_DEV);
+}
+
+static uint32_t SSRAM2_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_SSRAM2_DEV);
+}
+
+static int32_t SSRAM2_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_SSRAM2_DEV);
+}
+
+/* SSRAM2_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SRAM2_MPC;
+ARM_DRIVER_MPC Driver_SRAM2_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SSRAM2_MPC_Initialize,
+ .Uninitialize = SSRAM2_MPC_Uninitialize,
+ .GetBlockSize = SSRAM2_MPC_GetBlockSize,
+ .GetCtrlConfig = SSRAM2_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SSRAM2_MPC_SetCtrlConfig,
+ .ConfigRegion = SSRAM2_MPC_ConfigRegion,
+ .GetRegionConfig = SSRAM2_MPC_GetRegionConfig,
+ .EnableInterrupt = SSRAM2_MPC_EnableInterrupt,
+ .DisableInterrupt = SSRAM2_MPC_DisableInterrupt,
+ .ClearInterrupt = SSRAM2_MPC_ClearInterrupt,
+ .InterruptState = SSRAM2_MPC_InterruptState,
+ .LockDown = SSRAM2_MPC_LockDown,
+};
+#endif /* RTE_SSRAM2_MPC */
+
+#if (RTE_SSRAM3_MPC)
+/* Ranges controlled by this SSRAM3_MPC */
+static const struct mpc_sie200_memory_range_t MPC_SSRAM3_RANGE_S = {
+ .base = MPC_SSRAM3_RANGE_BASE_S,
+ .limit = MPC_SSRAM3_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_SSRAM3_RANGE_NS = {
+ .base = MPC_SSRAM3_RANGE_BASE_NS,
+ .limit = MPC_SSRAM3_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_SSRAM3_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_SSRAM3_RANGE_LIST[MPC_SSRAM3_RANGE_LIST_LEN] = {
+ &MPC_SSRAM3_RANGE_S,
+ &MPC_SSRAM3_RANGE_NS
+ };
+
+/* SSRAM3_MPC Driver wrapper functions */
+static int32_t SSRAM3_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_SSRAM3_DEV,
+ MPC_SSRAM3_RANGE_LIST,
+ MPC_SSRAM3_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM3_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t SSRAM3_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_SSRAM3_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM3_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_SSRAM3_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM3_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_SSRAM3_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM3_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_SSRAM3_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM3_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_SSRAM3_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t SSRAM3_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_SSRAM3_DEV);
+
+ return error_trans(ret);
+}
+
+static void SSRAM3_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_SSRAM3_DEV);
+}
+
+
+static void SSRAM3_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_SSRAM3_DEV);
+}
+
+static uint32_t SSRAM3_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_SSRAM3_DEV);
+}
+
+static int32_t SSRAM3_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_SSRAM3_DEV);
+}
+
+/* SSRAM3_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_SSRAM3_MPC;
+ARM_DRIVER_MPC Driver_SSRAM3_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = SSRAM3_MPC_Initialize,
+ .Uninitialize = SSRAM3_MPC_Uninitialize,
+ .GetBlockSize = SSRAM3_MPC_GetBlockSize,
+ .GetCtrlConfig = SSRAM3_MPC_GetCtrlConfig,
+ .SetCtrlConfig = SSRAM3_MPC_SetCtrlConfig,
+ .ConfigRegion = SSRAM3_MPC_ConfigRegion,
+ .GetRegionConfig = SSRAM3_MPC_GetRegionConfig,
+ .EnableInterrupt = SSRAM3_MPC_EnableInterrupt,
+ .DisableInterrupt = SSRAM3_MPC_DisableInterrupt,
+ .ClearInterrupt = SSRAM3_MPC_ClearInterrupt,
+ .InterruptState = SSRAM3_MPC_InterruptState,
+ .LockDown = SSRAM3_MPC_LockDown,
+};
+#endif /* RTE_SSRAM3_MPC */
+
+#if (RTE_QSPI_MPC)
+/* Ranges controlled by this QSPI_MPC */
+static const struct mpc_sie200_memory_range_t MPC_QSPI_RANGE_S = {
+ .base = MPC_QSPI_RANGE_BASE_S,
+ .limit = MPC_QSPI_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_QSPI_RANGE_NS = {
+ .base = MPC_QSPI_RANGE_BASE_NS,
+ .limit = MPC_QSPI_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_QSPI_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_QSPI_RANGE_LIST[MPC_QSPI_RANGE_LIST_LEN] = {
+ &MPC_QSPI_RANGE_S,
+ &MPC_QSPI_RANGE_NS
+ };
+
+/* QSPI_MPC Driver wrapper functions */
+static int32_t QSPI_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_QSPI_DEV,
+ MPC_QSPI_RANGE_LIST,
+ MPC_QSPI_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t QSPI_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_QSPI_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_QSPI_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_QSPI_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_QSPI_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_QSPI_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t QSPI_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_QSPI_DEV);
+
+ return error_trans(ret);
+}
+
+static void QSPI_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_QSPI_DEV);
+}
+
+
+static void QSPI_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_QSPI_DEV);
+}
+
+static uint32_t QSPI_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_QSPI_DEV);
+}
+
+static int32_t QSPI_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_QSPI_DEV);
+}
+
+/* QSPI1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_QSPI_MPC;
+ARM_DRIVER_MPC Driver_QSPI_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = QSPI_MPC_Initialize,
+ .Uninitialize = QSPI_MPC_Uninitialize,
+ .GetBlockSize = QSPI_MPC_GetBlockSize,
+ .GetCtrlConfig = QSPI_MPC_GetCtrlConfig,
+ .SetCtrlConfig = QSPI_MPC_SetCtrlConfig,
+ .ConfigRegion = QSPI_MPC_ConfigRegion,
+ .GetRegionConfig = QSPI_MPC_GetRegionConfig,
+ .EnableInterrupt = QSPI_MPC_EnableInterrupt,
+ .DisableInterrupt = QSPI_MPC_DisableInterrupt,
+ .ClearInterrupt = QSPI_MPC_ClearInterrupt,
+ .InterruptState = QSPI_MPC_InterruptState,
+ .LockDown = QSPI_MPC_LockDown,
+};
+#endif /* RTE_QSPI_MPC */
+
+#if (RTE_EFLASH0_MPC)
+/* Ranges controlled by this EFLASH0_MPC */
+static const struct mpc_sie200_memory_range_t MPC_EFLASH0_RANGE_S = {
+ .base = MPC_EFLASH0_RANGE_BASE_S,
+ .limit = MPC_EFLASH0_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_EFLASH0_RANGE_NS = {
+ .base = MPC_EFLASH0_RANGE_BASE_NS,
+ .limit = MPC_EFLASH0_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_EFLASH0_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_EFLASH0_RANGE_LIST[MPC_EFLASH0_RANGE_LIST_LEN]=
+ {&MPC_EFLASH0_RANGE_S, &MPC_EFLASH0_RANGE_NS};
+
+/* EFLASH0_MPC Driver wrapper functions */
+static int32_t EFLASH0_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_EFLASH0_DEV,
+ MPC_EFLASH0_RANGE_LIST,
+ MPC_EFLASH0_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH0_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t EFLASH0_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_EFLASH0_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH0_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_EFLASH0_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH0_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_EFLASH0_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH0_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_EFLASH0_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH0_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_EFLASH0_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH0_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_EFLASH0_DEV);
+
+ return error_trans(ret);
+}
+
+static void EFLASH0_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_EFLASH0_DEV);
+}
+
+
+static void EFLASH0_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_EFLASH0_DEV);
+}
+
+static uint32_t EFLASH0_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_EFLASH0_DEV);
+}
+
+static int32_t EFLASH0_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_EFLASH0_DEV);
+}
+
+/* EFLASH0_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_EFLASH0_MPC;
+ARM_DRIVER_MPC Driver_EFLASH0_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = EFLASH0_MPC_Initialize,
+ .Uninitialize = EFLASH0_MPC_Uninitialize,
+ .GetBlockSize = EFLASH0_MPC_GetBlockSize,
+ .GetCtrlConfig = EFLASH0_MPC_GetCtrlConfig,
+ .SetCtrlConfig = EFLASH0_MPC_SetCtrlConfig,
+ .ConfigRegion = EFLASH0_MPC_ConfigRegion,
+ .GetRegionConfig = EFLASH0_MPC_GetRegionConfig,
+ .EnableInterrupt = EFLASH0_MPC_EnableInterrupt,
+ .DisableInterrupt = EFLASH0_MPC_DisableInterrupt,
+ .ClearInterrupt = EFLASH0_MPC_ClearInterrupt,
+ .InterruptState = EFLASH0_MPC_InterruptState,
+ .LockDown = EFLASH0_MPC_LockDown,
+};
+#endif /* RTE_EFLASH0_MPC */
+
+#if (RTE_EFLASH1_MPC)
+/* Ranges controlled by this EFLASH1_MPC */
+static const struct mpc_sie200_memory_range_t MPC_EFLASH1_RANGE_S = {
+ .base = MPC_EFLASH1_RANGE_BASE_S,
+ .limit = MPC_EFLASH1_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_EFLASH1_RANGE_NS = {
+ .base = MPC_EFLASH1_RANGE_BASE_NS,
+ .limit = MPC_EFLASH1_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_EFLASH1_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_EFLASH1_RANGE_LIST[MPC_EFLASH1_RANGE_LIST_LEN]=
+ {&MPC_EFLASH1_RANGE_S, &MPC_EFLASH1_RANGE_NS};
+
+/* EFLASH1_MPC Driver wrapper functions */
+static int32_t EFLASH1_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_EFLASH1_DEV,
+ MPC_EFLASH1_RANGE_LIST,
+ MPC_EFLASH1_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH1_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t EFLASH1_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_EFLASH1_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH1_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_EFLASH1_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH1_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_EFLASH1_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH1_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_EFLASH1_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH1_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_EFLASH1_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t EFLASH1_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_EFLASH1_DEV);
+
+ return error_trans(ret);
+}
+
+static void EFLASH1_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_EFLASH1_DEV);
+}
+
+
+static void EFLASH1_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_EFLASH1_DEV);
+}
+
+static uint32_t EFLASH1_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_EFLASH1_DEV);
+}
+
+static int32_t EFLASH1_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_EFLASH1_DEV);
+}
+
+/* EFLASH1_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_EFLASH1_MPC;
+ARM_DRIVER_MPC Driver_EFLASH1_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = EFLASH1_MPC_Initialize,
+ .Uninitialize = EFLASH1_MPC_Uninitialize,
+ .GetBlockSize = EFLASH1_MPC_GetBlockSize,
+ .GetCtrlConfig = EFLASH1_MPC_GetCtrlConfig,
+ .SetCtrlConfig = EFLASH1_MPC_SetCtrlConfig,
+ .ConfigRegion = EFLASH1_MPC_ConfigRegion,
+ .GetRegionConfig = EFLASH1_MPC_GetRegionConfig,
+ .EnableInterrupt = EFLASH1_MPC_EnableInterrupt,
+ .DisableInterrupt = EFLASH1_MPC_DisableInterrupt,
+ .ClearInterrupt = EFLASH1_MPC_ClearInterrupt,
+ .InterruptState = EFLASH1_MPC_InterruptState,
+ .LockDown = EFLASH1_MPC_LockDown,
+};
+#endif /* RTE_EFLASH1_MPC */
+
+#if (RTE_BRAM_MPC)
+/* Ranges controlled by this BRAM_MPC */
+static const struct mpc_sie200_memory_range_t MPC_BRAM_RANGE_S = {
+ .base = MPC_BRAM_RANGE_BASE_S,
+ .limit = MPC_BRAM_RANGE_LIMIT_S,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_SECURE
+};
+
+static const struct mpc_sie200_memory_range_t MPC_BRAM_RANGE_NS = {
+ .base = MPC_BRAM_RANGE_BASE_NS,
+ .limit = MPC_BRAM_RANGE_LIMIT_NS,
+ .range_offset = 0,
+ .attr = MPC_SIE200_SEC_ATTR_NONSECURE
+};
+
+#define MPC_BRAM_RANGE_LIST_LEN 2u
+static const struct mpc_sie200_memory_range_t*
+ MPC_BRAM_RANGE_LIST[MPC_BRAM_RANGE_LIST_LEN]= {
+ &MPC_BRAM_RANGE_S,
+ &MPC_BRAM_RANGE_NS
+ };
+
+/* BRAM_MPC Driver wrapper functions */
+static int32_t BRAM_MPC_Initialize(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_init(&MPC_BRAM_DEV,
+ MPC_BRAM_RANGE_LIST,
+ MPC_BRAM_RANGE_LIST_LEN);
+
+ return error_trans(ret);
+}
+
+static int32_t BRAM_MPC_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t BRAM_MPC_GetBlockSize(uint32_t *blk_size)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_block_size(&MPC_BRAM_DEV, blk_size);
+
+ return error_trans(ret);
+}
+
+static int32_t BRAM_MPC_GetCtrlConfig(uint32_t *ctrl_val)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_ctrl(&MPC_BRAM_DEV, ctrl_val);
+
+ return error_trans(ret);
+}
+
+static int32_t BRAM_MPC_SetCtrlConfig(uint32_t ctrl)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_set_ctrl(&MPC_BRAM_DEV, ctrl);
+
+ return error_trans(ret);
+}
+
+static int32_t BRAM_MPC_GetRegionConfig(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR *attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_get_region_config(&MPC_BRAM_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t *)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t BRAM_MPC_ConfigRegion(uintptr_t base,
+ uintptr_t limit,
+ ARM_MPC_SEC_ATTR attr)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_config_region(&MPC_BRAM_DEV, base, limit,
+ (enum mpc_sie200_sec_attr_t)attr);
+
+ return error_trans(ret);
+}
+
+static int32_t BRAM_MPC_EnableInterrupt(void)
+{
+ enum mpc_sie200_error_t ret;
+
+ ret = mpc_sie200_irq_enable(&MPC_BRAM_DEV);
+
+ return error_trans(ret);
+}
+
+static void BRAM_MPC_DisableInterrupt(void)
+{
+ mpc_sie200_irq_disable(&MPC_BRAM_DEV);
+}
+
+
+static void BRAM_MPC_ClearInterrupt(void)
+{
+ mpc_sie200_clear_irq(&MPC_BRAM_DEV);
+}
+
+static uint32_t BRAM_MPC_InterruptState(void)
+{
+ return mpc_sie200_irq_state(&MPC_BRAM_DEV);
+}
+
+static int32_t BRAM_MPC_LockDown(void)
+{
+ return mpc_sie200_lock_down(&MPC_BRAM_DEV);
+}
+
+/* BRAM_MPC Driver CMSIS access structure */
+extern ARM_DRIVER_MPC Driver_BRAM_MPC;
+ARM_DRIVER_MPC Driver_BRAM_MPC = {
+ .GetVersion = ARM_MPC_GetVersion,
+ .Initialize = BRAM_MPC_Initialize,
+ .Uninitialize = BRAM_MPC_Uninitialize,
+ .GetBlockSize = BRAM_MPC_GetBlockSize,
+ .GetCtrlConfig = BRAM_MPC_GetCtrlConfig,
+ .SetCtrlConfig = BRAM_MPC_SetCtrlConfig,
+ .ConfigRegion = BRAM_MPC_ConfigRegion,
+ .GetRegionConfig = BRAM_MPC_GetRegionConfig,
+ .EnableInterrupt = BRAM_MPC_EnableInterrupt,
+ .DisableInterrupt = BRAM_MPC_DisableInterrupt,
+ .ClearInterrupt = BRAM_MPC_ClearInterrupt,
+ .InterruptState = BRAM_MPC_InterruptState,
+ .LockDown = BRAM_MPC_LockDown,
+};
+#endif /* RTE_BRAM_MPC */
diff --git a/platform/ext/target/mps3/an524/cmsis_drivers/Driver_PPC.c b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_PPC.c
new file mode 100644
index 0000000..a17e157
--- /dev/null
+++ b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_PPC.c
@@ -0,0 +1,967 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_PPC.h"
+
+#include "cmsis_driver_config.h"
+#include "RTE_Device.h"
+
+/* Driver version */
+#define ARM_PPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_PPC_API_VERSION,
+ ARM_PPC_DRV_VERSION
+};
+
+static ARM_DRIVER_VERSION ARM_PPC_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+#if (RTE_AHB_PPC0)
+/* AHB PPC0 Driver wrapper functions */
+static int32_t AHB_PPC0_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPC0_DEV, AHB_PPC0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPC0_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPC0_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPC0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPC0_DEV, periph);
+}
+
+static uint32_t AHB_PPC0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPC0_DEV, periph);
+}
+
+static int32_t AHB_PPC0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPC0_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPC0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPC0_DEV);
+}
+
+static void AHB_PPC0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPC0_DEV);
+}
+
+static uint32_t AHB_PPC0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPC0_DEV);
+}
+
+/* AHB PPC0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPC0;
+ARM_DRIVER_PPC Driver_AHB_PPC0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPC0_Initialize,
+ .Uninitialize = AHB_PPC0_Uninitialize,
+ .ConfigPeriph = AHB_PPC0_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPC0_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPC0_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPC0_EnableInterrupt,
+ .DisableInterrupt = AHB_PPC0_DisableInterrupt,
+ .ClearInterrupt = AHB_PPC0_ClearInterrupt,
+ .InterruptState = AHB_PPC0_InterruptState
+};
+#endif /* RTE_AHB_PPC0 */
+
+#if (RTE_AHB_PPCEXP0)
+/* AHB PPCEXP0 Driver wrapper functions */
+static int32_t AHB_PPCEXP0_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP0_DEV, AHB_PPC_EXP0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP0_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP0_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP0_DEV, periph);
+}
+
+static uint32_t AHB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP0_DEV, periph);
+}
+
+static int32_t AHB_PPCEXP0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP0_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP0_DEV);
+}
+
+static void AHB_PPCEXP0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP0_DEV);
+}
+
+static uint32_t AHB_PPCEXP0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP0_DEV);
+}
+
+/* AHB PPCEXP0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP0;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP0_Initialize,
+ .Uninitialize = AHB_PPCEXP0_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP0_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP0_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP0_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP0_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP0_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP0_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP0_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP0 */
+
+#if (RTE_AHB_PPCEXP1)
+/* AHB PPCEXP1 Driver wrapper functions */
+static int32_t AHB_PPCEXP1_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP1_DEV, AHB_PPC_EXP1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP1_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP1_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP1_DEV, periph);
+}
+
+static uint32_t AHB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP1_DEV, periph);
+}
+
+static int32_t AHB_PPCEXP1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP1_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP1_DEV);
+}
+
+static void AHB_PPCEXP1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP1_DEV);
+}
+
+static uint32_t AHB_PPCEXP1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP1_DEV);
+}
+
+/* AHB PPCEXP1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP1;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP1_Initialize,
+ .Uninitialize = AHB_PPCEXP1_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP1_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP1_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP1_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP1_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP1_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP1_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP1_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP1 */
+
+#if (RTE_AHB_PPCEXP2)
+/* AHB PPCEXP2 Driver wrapper functions */
+static int32_t AHB_PPCEXP2_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP2_DEV, AHB_PPC_EXP2);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP2_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP2_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP2_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP2_DEV, periph);
+}
+
+static uint32_t AHB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP2_DEV, periph);
+}
+
+static int32_t AHB_PPCEXP2_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP2_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP2_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP2_DEV);
+}
+
+static void AHB_PPCEXP2_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP2_DEV);
+}
+
+static uint32_t AHB_PPCEXP2_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP2_DEV);
+}
+
+/* AHB PPCEXP2 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP2;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP2 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP2_Initialize,
+ .Uninitialize = AHB_PPCEXP2_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP2_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP2_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP2_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP2_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP2_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP2_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP2_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP2 */
+
+#if (RTE_AHB_PPCEXP3)
+/* AHB PPCEXP3 Driver wrapper functions */
+static int32_t AHB_PPCEXP3_Initialize(void)
+{
+ ppc_sse200_init(&AHB_PPCEXP3_DEV, AHB_PPC_EXP3);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t AHB_PPCEXP3_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&AHB_PPCEXP3_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t AHB_PPCEXP3_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&AHB_PPCEXP3_DEV, periph);
+}
+
+static uint32_t AHB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&AHB_PPCEXP3_DEV, periph);
+}
+
+static int32_t AHB_PPCEXP3_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&AHB_PPCEXP3_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void AHB_PPCEXP3_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&AHB_PPCEXP3_DEV);
+}
+
+static void AHB_PPCEXP3_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&AHB_PPCEXP3_DEV);
+}
+
+static uint32_t AHB_PPCEXP3_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&AHB_PPCEXP3_DEV);
+}
+
+/* AHB PPCEXP3 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP3;
+ARM_DRIVER_PPC Driver_AHB_PPCEXP3 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = AHB_PPCEXP3_Initialize,
+ .Uninitialize = AHB_PPCEXP3_Uninitialize,
+ .ConfigPeriph = AHB_PPCEXP3_ConfigPeriph,
+ .IsPeriphSecure = AHB_PPCEXP3_IsPeriphSecure,
+ .IsPeriphPrivOnly = AHB_PPCEXP3_IsPeriphPrivOnly,
+ .EnableInterrupt = AHB_PPCEXP3_EnableInterrupt,
+ .DisableInterrupt = AHB_PPCEXP3_DisableInterrupt,
+ .ClearInterrupt = AHB_PPCEXP3_ClearInterrupt,
+ .InterruptState = AHB_PPCEXP3_InterruptState
+};
+#endif /* RTE_AHB_PPCEXP3 */
+
+#if (RTE_APB_PPC0)
+/* APB PPC0 Driver wrapper functions */
+static int32_t APB_PPC0_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPC0_DEV, APB_PPC0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC0_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC0_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPC0_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPC0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPC0_DEV, periph);
+}
+
+static uint32_t APB_PPC0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPC0_DEV, periph);
+}
+
+static int32_t APB_PPC0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPC0_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPC0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPC0_DEV);
+}
+
+static void APB_PPC0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPC0_DEV);
+}
+
+static uint32_t APB_PPC0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPC0_DEV);
+}
+
+/* APB PPC0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPC0;
+ARM_DRIVER_PPC Driver_APB_PPC0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPC0_Initialize,
+ .Uninitialize = APB_PPC0_Uninitialize,
+ .ConfigPeriph = APB_PPC0_ConfigPeriph,
+ .IsPeriphSecure = APB_PPC0_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPC0_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPC0_EnableInterrupt,
+ .DisableInterrupt = APB_PPC0_DisableInterrupt,
+ .ClearInterrupt = APB_PPC0_ClearInterrupt,
+ .InterruptState = APB_PPC0_InterruptState
+};
+#endif /* RTE_APB_PPC0 */
+
+#if (RTE_APB_PPC1)
+/* APB PPC1 Driver wrapper functions */
+static int32_t APB_PPC1_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPC1_DEV, APB_PPC1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC1_Uninitialize(void)
+{
+ /* Nothing to be done*/
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPC1_ConfigPeriph(uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPC1_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPC1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPC1_DEV, periph);
+}
+
+static uint32_t APB_PPC1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPC1_DEV, periph);
+}
+static int32_t APB_PPC1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPC1_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPC1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPC1_DEV);
+}
+
+static void APB_PPC1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPC1_DEV);
+}
+
+static uint32_t APB_PPC1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPC1_DEV);
+}
+
+/* APB PPC1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPC1;
+ARM_DRIVER_PPC Driver_APB_PPC1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPC1_Initialize,
+ .Uninitialize = APB_PPC1_Uninitialize,
+ .ConfigPeriph = APB_PPC1_ConfigPeriph,
+ .IsPeriphSecure = APB_PPC1_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPC1_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPC1_EnableInterrupt,
+ .DisableInterrupt = APB_PPC1_DisableInterrupt,
+ .ClearInterrupt = APB_PPC1_ClearInterrupt,
+ .InterruptState = APB_PPC1_InterruptState
+};
+#endif /* RTE_APB_PPC1 */
+
+#if (RTE_APB_PPCEXP0)
+/* APB PPCEXP0 Driver wrapper functions */
+static int32_t APB_PPCEXP0_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP0_DEV, APB_PPC_EXP0);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP0_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP0_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP0_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP0_DEV, periph);
+}
+
+static uint32_t APB_PPCEXP0_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP0_DEV, periph);
+}
+
+static int32_t APB_PPCEXP0_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP0_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP0_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP0_DEV);
+}
+
+static void APB_PPCEXP0_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP0_DEV);
+}
+
+static uint32_t APB_PPCEXP0_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP0_DEV);
+}
+
+/* APB PPCEXP0 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP0;
+ARM_DRIVER_PPC Driver_APB_PPCEXP0 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP0_Initialize,
+ .Uninitialize = APB_PPCEXP0_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP0_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP0_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP0_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP0_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP0_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP0_ClearInterrupt,
+ .InterruptState = APB_PPCEXP0_InterruptState
+};
+#endif /* RTE_APB_PPCEXP0 */
+
+#if (RTE_APB_PPCEXP1)
+/* APB PPCEXP1 Driver wrapper functions */
+static int32_t APB_PPCEXP1_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP1_DEV, APB_PPC_EXP1);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP1_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP1_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP1_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP1_DEV, periph);
+}
+
+static uint32_t APB_PPCEXP1_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP1_DEV, periph);
+}
+
+static int32_t APB_PPCEXP1_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP1_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP1_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP1_DEV);
+}
+
+static void APB_PPCEXP1_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP1_DEV);
+}
+
+static uint32_t APB_PPCEXP1_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP1_DEV);
+}
+
+/* APB PPCEXP1 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP1;
+ARM_DRIVER_PPC Driver_APB_PPCEXP1 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP1_Initialize,
+ .Uninitialize = APB_PPCEXP1_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP1_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP1_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP1_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP1_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP1_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP1_ClearInterrupt,
+ .InterruptState = APB_PPCEXP1_InterruptState
+};
+#endif /* RTE_APB_PPCEXP1 */
+
+#if (RTE_APB_PPCEXP2)
+/* APB PPCEXP2 Driver wrapper functions */
+static int32_t APB_PPCEXP2_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP2_DEV, APB_PPC_EXP2);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP2_ConfigPeriph(uint8_t periph,
+ ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP2_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP2_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP2_DEV, periph);
+}
+
+static uint32_t APB_PPCEXP2_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP2_DEV, periph);
+}
+
+static int32_t APB_PPCEXP2_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP2_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP2_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP2_DEV);
+}
+
+static void APB_PPCEXP2_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP2_DEV);
+}
+
+static uint32_t APB_PPCEXP2_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP2_DEV);
+}
+
+/* APB PPCEXP2 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP2;
+ARM_DRIVER_PPC Driver_APB_PPCEXP2 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP2_Initialize,
+ .Uninitialize = APB_PPCEXP2_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP2_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP2_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP2_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP2_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP2_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP2_ClearInterrupt,
+ .InterruptState = APB_PPCEXP2_InterruptState
+};
+#endif /* RTE_APB_PPCEXP2 */
+
+#if (RTE_APB_PPCEXP3)
+/* APB PPCEXP3 Driver wrapper functions */
+static int32_t APB_PPCEXP3_Initialize(void)
+{
+ ppc_sse200_init(&APB_PPCEXP3_DEV, APB_PPC_EXP3);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t APB_PPCEXP3_ConfigPeriph(
+ uint8_t periph, ARM_PPC_SecAttr sec_attr,
+ ARM_PPC_PrivAttr priv_attr)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_config_peripheral(&APB_PPCEXP3_DEV, periph,
+ (enum ppc_sse200_sec_attr_t)sec_attr,
+ (enum ppc_sse200_priv_attr_t)priv_attr);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t APB_PPCEXP3_IsPeriphSecure(uint8_t periph)
+{
+ return ppc_sse200_is_periph_secure(&APB_PPCEXP3_DEV, periph);
+}
+
+static uint32_t APB_PPCEXP3_IsPeriphPrivOnly(uint8_t periph)
+{
+ return ppc_sse200_is_periph_priv_only(&APB_PPCEXP3_DEV, periph);
+}
+
+static int32_t APB_PPCEXP3_EnableInterrupt(void)
+{
+ enum ppc_sse200_error_t ret;
+
+ ret = ppc_sse200_irq_enable(&APB_PPCEXP3_DEV);
+
+ if (ret != PPC_SSE200_ERR_NONE) {
+ return ARM_DRIVER_ERROR;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static void APB_PPCEXP3_DisableInterrupt(void)
+{
+ ppc_sse200_irq_disable(&APB_PPCEXP3_DEV);
+}
+
+static void APB_PPCEXP3_ClearInterrupt(void)
+{
+ ppc_sse200_clear_irq(&APB_PPCEXP3_DEV);
+}
+
+static uint32_t APB_PPCEXP3_InterruptState(void)
+{
+ return ppc_sse200_irq_state(&APB_PPCEXP3_DEV);
+}
+
+/* APB PPCEXP3 Driver CMSIS access structure */
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP3;
+ARM_DRIVER_PPC Driver_APB_PPCEXP3 = {
+ .GetVersion = ARM_PPC_GetVersion,
+ .Initialize = APB_PPCEXP3_Initialize,
+ .Uninitialize = APB_PPCEXP3_Uninitialize,
+ .ConfigPeriph = APB_PPCEXP3_ConfigPeriph,
+ .IsPeriphSecure = APB_PPCEXP3_IsPeriphSecure,
+ .IsPeriphPrivOnly = APB_PPCEXP3_IsPeriphPrivOnly,
+ .EnableInterrupt = APB_PPCEXP3_EnableInterrupt,
+ .DisableInterrupt = APB_PPCEXP3_DisableInterrupt,
+ .ClearInterrupt = APB_PPCEXP3_ClearInterrupt,
+ .InterruptState = APB_PPCEXP3_InterruptState
+};
+#endif /* RTE_APB_PPCEXP3 */
diff --git a/platform/ext/target/mps3/an524/cmsis_drivers/Driver_USART.c b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_USART.c
new file mode 100644
index 0000000..f127e76
--- /dev/null
+++ b/platform/ext/target/mps3/an524/cmsis_drivers/Driver_USART.c
@@ -0,0 +1,701 @@
+/*
+ * Copyright (c) 2013-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "Driver_USART.h"
+
+#include "cmsis_driver_config.h"
+#include "RTE_Device.h"
+
+#ifndef ARG_UNUSED
+#define ARG_UNUSED(arg) (void)arg
+#endif
+
+/* Driver version */
+#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2)
+
+/* Driver Version */
+static const ARM_DRIVER_VERSION DriverVersion = {
+ ARM_USART_API_VERSION,
+ ARM_USART_DRV_VERSION
+};
+
+/* Driver Capabilities */
+static const ARM_USART_CAPABILITIES DriverCapabilities = {
+ 1, /* supports UART (Asynchronous) mode */
+ 0, /* supports Synchronous Master mode */
+ 0, /* supports Synchronous Slave mode */
+ 0, /* supports UART Single-wire mode */
+ 0, /* supports UART IrDA mode */
+ 0, /* supports UART Smart Card mode */
+ 0, /* Smart Card Clock generator available */
+ 0, /* RTS Flow Control available */
+ 0, /* CTS Flow Control available */
+ 0, /* Transmit completed event: \ref ARM_USARTx_EVENT_TX_COMPLETE */
+ 0, /* Signal receive character timeout event: \ref ARM_USARTx_EVENT_RX_TIMEOUT */
+ 0, /* RTS Line: 0=not available, 1=available */
+ 0, /* CTS Line: 0=not available, 1=available */
+ 0, /* DTR Line: 0=not available, 1=available */
+ 0, /* DSR Line: 0=not available, 1=available */
+ 0, /* DCD Line: 0=not available, 1=available */
+ 0, /* RI Line: 0=not available, 1=available */
+ 0, /* Signal CTS change event: \ref ARM_USARTx_EVENT_CTS */
+ 0, /* Signal DSR change event: \ref ARM_USARTx_EVENT_DSR */
+ 0, /* Signal DCD change event: \ref ARM_USARTx_EVENT_DCD */
+ 0, /* Signal RI change event: \ref ARM_USARTx_EVENT_RI */
+ 0 /* Reserved */
+};
+
+static ARM_DRIVER_VERSION ARM_USART_GetVersion(void)
+{
+ return DriverVersion;
+}
+
+static ARM_USART_CAPABILITIES ARM_USART_GetCapabilities(void)
+{
+ return DriverCapabilities;
+}
+
+typedef struct {
+ struct uart_cmsdk_dev_t *dev; /* UART device structure */
+ uint32_t tx_nbr_bytes; /* Number of bytes transfered */
+ uint32_t rx_nbr_bytes; /* Number of bytes recevied */
+ ARM_USART_SignalEvent_t cb_event; /* Callback function for events */
+} UARTx_Resources;
+
+static int32_t ARM_USARTx_Initialize(UARTx_Resources *uart_dev)
+{
+ /* Initializes generic UART driver */
+ uart_cmsdk_init(uart_dev->dev, PeripheralClock);
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_PowerControl(UARTx_Resources *uart_dev,
+ ARM_POWER_STATE state)
+{
+ ARG_UNUSED(uart_dev);
+
+ switch (state) {
+ case ARM_POWER_OFF:
+ case ARM_POWER_LOW:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ case ARM_POWER_FULL:
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all the enumeration values are
+ * covered in the switch.*/
+ }
+}
+
+static int32_t ARM_USARTx_Send(UARTx_Resources *uart_dev, const void *data,
+ uint32_t num)
+{
+ const uint8_t *p_data = (const uint8_t *)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ /* Invalid parameters */
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Resets previous TX counter */
+ uart_dev->tx_nbr_bytes = 0;
+
+ while (uart_dev->tx_nbr_bytes != num) {
+ /* Waits until UART is ready to transmit */
+ while (!uart_cmsdk_tx_ready(uart_dev->dev)) {
+ };
+
+ /* As UART is ready to transmit at this point, the write function can
+ * not return any transmit error */
+ (void)uart_cmsdk_write(uart_dev->dev, *p_data);
+
+ uart_dev->tx_nbr_bytes++;
+ p_data++;
+ }
+
+ /* Waits until character is transmited */
+ while (!uart_cmsdk_tx_ready(uart_dev->dev)) {
+ };
+
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USARTx_Receive(UARTx_Resources *uart_dev,
+ void *data, uint32_t num)
+{
+ uint8_t *p_data = (uint8_t *)data;
+
+ if ((data == NULL) || (num == 0U)) {
+ // Invalid parameters
+ return ARM_DRIVER_ERROR_PARAMETER;
+ }
+
+ /* Resets previous RX counter */
+ uart_dev->rx_nbr_bytes = 0;
+
+ while (uart_dev->rx_nbr_bytes != num) {
+ /* Waits until one character is received */
+ while (!uart_cmsdk_rx_ready(uart_dev->dev)){};
+
+ /* As UART has received one byte, the read can not
+ * return any receive error at this point */
+ (void)uart_cmsdk_read(uart_dev->dev, p_data);
+
+ uart_dev->rx_nbr_bytes++;
+ p_data++;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+static uint32_t ARM_USARTx_GetTxCount(UARTx_Resources *uart_dev)
+{
+ return uart_dev->tx_nbr_bytes;
+}
+
+static uint32_t ARM_USARTx_GetRxCount(UARTx_Resources *uart_dev)
+{
+ return uart_dev->rx_nbr_bytes;
+}
+
+static int32_t ARM_USARTx_Control(UARTx_Resources *uart_dev, uint32_t control,
+ uint32_t arg)
+{
+ switch (control & ARM_USART_CONTROL_Msk) {
+ case ARM_USART_MODE_ASYNCHRONOUS:
+ if (uart_cmsdk_set_baudrate(uart_dev->dev, arg)
+ != UART_CMSDK_ERR_NONE) {
+ return ARM_USART_ERROR_BAUDRATE;
+ }
+ break;
+ /* Unsupported command */
+ default:
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Data bits */
+ if (control & ARM_USART_DATA_BITS_Msk) {
+ /* Data bit is not configurable */
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+ }
+
+ /* UART Parity */
+ if (control & ARM_USART_PARITY_Msk) {
+ /* Parity is not configurable */
+ return ARM_USART_ERROR_PARITY;
+ }
+
+ /* USART Stop bits */
+ if (control & ARM_USART_STOP_BITS_Msk) {
+ /* Stop bit is not configurable */
+ return ARM_USART_ERROR_STOP_BITS;
+ }
+
+ return ARM_DRIVER_OK;
+}
+
+#if (RTE_USART0)
+/* USART0 Driver wrapper functions */
+static UARTx_Resources USART0_DEV = {
+ .dev = &UART0_CMSDK_DEV,
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART0_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART0_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART0_DEV);
+}
+
+static int32_t ARM_USART0_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART0_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART0_DEV, state);
+}
+
+static int32_t ARM_USART0_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART0_DEV, data, num);
+}
+
+static int32_t ARM_USART0_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART0_DEV, data, num);
+}
+
+static int32_t ARM_USART0_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART0_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART0_DEV);
+}
+
+static uint32_t ARM_USART0_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART0_DEV);
+}
+static int32_t ARM_USART0_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART0_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART0_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART0_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART0_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART0;
+ARM_DRIVER_USART Driver_USART0 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART0_Initialize,
+ ARM_USART0_Uninitialize,
+ ARM_USART0_PowerControl,
+ ARM_USART0_Send,
+ ARM_USART0_Receive,
+ ARM_USART0_Transfer,
+ ARM_USART0_GetTxCount,
+ ARM_USART0_GetRxCount,
+ ARM_USART0_Control,
+ ARM_USART0_GetStatus,
+ ARM_USART0_SetModemControl,
+ ARM_USART0_GetModemStatus
+};
+#endif /* RTE_USART0 */
+
+#if (RTE_USART1)
+/* USART1 Driver wrapper functions */
+static UARTx_Resources USART1_DEV = {
+ .dev = &UART1_CMSDK_DEV,
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART1_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART1_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART1_DEV);
+}
+
+static int32_t ARM_USART1_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART1_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART1_DEV, state);
+}
+
+static int32_t ARM_USART1_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART1_DEV, data, num);
+}
+
+static int32_t ARM_USART1_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART1_DEV, data, num);
+}
+
+static int32_t ARM_USART1_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART1_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART1_DEV);
+}
+
+static uint32_t ARM_USART1_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART1_DEV);
+}
+static int32_t ARM_USART1_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART1_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART1_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART1_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART1_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART1;
+ARM_DRIVER_USART Driver_USART1 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART1_Initialize,
+ ARM_USART1_Uninitialize,
+ ARM_USART1_PowerControl,
+ ARM_USART1_Send,
+ ARM_USART1_Receive,
+ ARM_USART1_Transfer,
+ ARM_USART1_GetTxCount,
+ ARM_USART1_GetRxCount,
+ ARM_USART1_Control,
+ ARM_USART1_GetStatus,
+ ARM_USART1_SetModemControl,
+ ARM_USART1_GetModemStatus
+};
+#endif /* RTE_USART1 */
+
+#if (RTE_USART2)
+/* USART2 Driver wrapper functions */
+static UARTx_Resources USART2_DEV = {
+ .dev = &UART2_CMSDK_DEV,
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART2_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART2_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART2_DEV);
+}
+
+static int32_t ARM_USART2_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART2_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART2_DEV, state);
+}
+
+static int32_t ARM_USART2_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART2_DEV, data, num);
+}
+
+static int32_t ARM_USART2_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART2_DEV, data, num);
+}
+
+static int32_t ARM_USART2_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART2_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART2_DEV);
+}
+
+static uint32_t ARM_USART2_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART2_DEV);
+}
+static int32_t ARM_USART2_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART2_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART2_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART2_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART2_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART2;
+ARM_DRIVER_USART Driver_USART2 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART2_Initialize,
+ ARM_USART2_Uninitialize,
+ ARM_USART2_PowerControl,
+ ARM_USART2_Send,
+ ARM_USART2_Receive,
+ ARM_USART2_Transfer,
+ ARM_USART2_GetTxCount,
+ ARM_USART2_GetRxCount,
+ ARM_USART2_Control,
+ ARM_USART2_GetStatus,
+ ARM_USART2_SetModemControl,
+ ARM_USART2_GetModemStatus
+};
+#endif /* RTE_USART2 */
+
+#if (RTE_USART3)
+/* USART3 Driver wrapper functions */
+static UARTx_Resources USART3_DEV = {
+ .dev = &UART3_CMSDK_DEV,
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART3_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART3_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART3_DEV);
+}
+
+static int32_t ARM_USART3_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART3_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART3_DEV, state);
+}
+
+static int32_t ARM_USART3_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART3_DEV, data, num);
+}
+
+static int32_t ARM_USART3_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART3_DEV, data, num);
+}
+
+static int32_t ARM_USART3_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART3_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART3_DEV);
+}
+
+static uint32_t ARM_USART3_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART3_DEV);
+}
+static int32_t ARM_USART3_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART3_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART3_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART3_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART3_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART3;
+ARM_DRIVER_USART Driver_USART3 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART3_Initialize,
+ ARM_USART3_Uninitialize,
+ ARM_USART3_PowerControl,
+ ARM_USART3_Send,
+ ARM_USART3_Receive,
+ ARM_USART3_Transfer,
+ ARM_USART3_GetTxCount,
+ ARM_USART3_GetRxCount,
+ ARM_USART3_Control,
+ ARM_USART3_GetStatus,
+ ARM_USART3_SetModemControl,
+ ARM_USART3_GetModemStatus
+};
+#endif /* RTE_USART3 */
+
+#if (RTE_USART4)
+/* USART4 Driver wrapper functions */
+static UARTx_Resources USART4_DEV = {
+ .dev = &UART4_CMSDK_DEV,
+ .tx_nbr_bytes = 0,
+ .rx_nbr_bytes = 0,
+ .cb_event = NULL,
+};
+
+static int32_t ARM_USART4_Initialize(ARM_USART_SignalEvent_t cb_event)
+{
+ USART4_DEV.cb_event = cb_event;
+
+ return ARM_USARTx_Initialize(&USART4_DEV);
+}
+
+static int32_t ARM_USART4_Uninitialize(void)
+{
+ /* Nothing to be done */
+ return ARM_DRIVER_OK;
+}
+
+static int32_t ARM_USART4_PowerControl(ARM_POWER_STATE state)
+{
+ return ARM_USARTx_PowerControl(&USART4_DEV, state);
+}
+
+static int32_t ARM_USART4_Send(const void *data, uint32_t num)
+{
+ return ARM_USARTx_Send(&USART4_DEV, data, num);
+}
+
+static int32_t ARM_USART4_Receive(void *data, uint32_t num)
+{
+ return ARM_USARTx_Receive(&USART4_DEV, data, num);
+}
+
+static int32_t ARM_USART4_Transfer(const void *data_out, void *data_in,
+ uint32_t num)
+{
+ ARG_UNUSED(data_out);
+ ARG_UNUSED(data_in);
+ ARG_UNUSED(num);
+
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static uint32_t ARM_USART4_GetTxCount(void)
+{
+ return ARM_USARTx_GetTxCount(&USART4_DEV);
+}
+
+static uint32_t ARM_USART4_GetRxCount(void)
+{
+ return ARM_USARTx_GetRxCount(&USART4_DEV);
+}
+static int32_t ARM_USART4_Control(uint32_t control, uint32_t arg)
+{
+ return ARM_USARTx_Control(&USART4_DEV, control, arg);
+}
+
+static ARM_USART_STATUS ARM_USART4_GetStatus(void)
+{
+ ARM_USART_STATUS status = {0, 0, 0, 0, 0, 0, 0, 0};
+ return status;
+}
+
+static int32_t ARM_USART4_SetModemControl(ARM_USART_MODEM_CONTROL control)
+{
+ ARG_UNUSED(control);
+ return ARM_DRIVER_ERROR_UNSUPPORTED;
+}
+
+static ARM_USART_MODEM_STATUS ARM_USART4_GetModemStatus(void)
+{
+ ARM_USART_MODEM_STATUS modem_status = {0, 0, 0, 0, 0};
+ return modem_status;
+}
+
+extern ARM_DRIVER_USART Driver_USART4;
+ARM_DRIVER_USART Driver_USART4 = {
+ ARM_USART_GetVersion,
+ ARM_USART_GetCapabilities,
+ ARM_USART4_Initialize,
+ ARM_USART4_Uninitialize,
+ ARM_USART4_PowerControl,
+ ARM_USART4_Send,
+ ARM_USART4_Receive,
+ ARM_USART4_Transfer,
+ ARM_USART4_GetTxCount,
+ ARM_USART4_GetRxCount,
+ ARM_USART4_Control,
+ ARM_USART4_GetStatus,
+ ARM_USART4_SetModemControl,
+ ARM_USART4_GetModemStatus
+};
+#endif /* RTE_USART4 */
diff --git a/platform/ext/target/mps3/an524/cmsis_drivers/config/RTE_Device.h b/platform/ext/target/mps3/an524/cmsis_drivers/config/RTE_Device.h
new file mode 100644
index 0000000..0f11064
--- /dev/null
+++ b/platform/ext/target/mps3/an524/cmsis_drivers/config/RTE_Device.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+// <i> Configuration settings for Driver_USART0 in component ::Drivers:USART
+#define RTE_USART0 1
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART0]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+// <i> Configuration settings for Driver_USART1 in component ::Drivers:USART
+#define RTE_USART1 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART1]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+// <i> Configuration settings for Driver_USART2 in component ::Drivers:USART
+#define RTE_USART2 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART2]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+// <i> Configuration settings for Driver_USART3 in component ::Drivers:USART
+#define RTE_USART3 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART3]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+// <i> Configuration settings for Driver_USART4 in component ::Drivers:USART
+#define RTE_USART4 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART4]
+
+// <e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART5]
+// <i> Configuration settings for Driver_USART5 in component ::Drivers:USART
+#define RTE_USART5 0
+// </e> USART (Universal synchronous - asynchronous receiver transmitter) [Driver_USART5]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+// <i> Configuration settings for Driver_ISRAM0_MPC in component ::Drivers:MPC
+#define RTE_ISRAM0_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM0_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+// <i> Configuration settings for Driver_ISRAM1_MPC in component ::Drivers:MPC
+#define RTE_ISRAM1_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM1_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC]
+// <i> Configuration settings for Driver_ISRAM2_MPC in component ::Drivers:MPC
+#define RTE_ISRAM2_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM2_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_ISRAM3_MPC]
+// <i> Configuration settings for Driver_ISRAM3_MPC in component ::Drivers:MPC
+#define RTE_ISRAM3_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_ISRAM3_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_BRAM_MPC]
+// <i> Configuration settings for Driver_BRAM_MPC in component ::Drivers:MPC
+#define RTE_BRAM_MPC 0
+// </e> MPC (Memory Protection Controller) [Driver_SRAM1_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
+// <i> Configuration settings for Driver_QSPI_MPC in component ::Drivers:MPC
+#define RTE_QSPI_MPC 1
+// </e> MPC (Memory Protection Controller) [Driver_QSPI_MPC]
+
+// <e> MPC (Memory Protection Controller) [Driver_DDR4_MPC]
+// <i> Configuration settings for Driver_DDR4_MPC in component ::Drivers:MPC
+#define RTE_DDR4_MPC 0
+// </e> MPC (Memory Protection Controller) [Driver_DDR4_MPC]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0]
+// <i> Configuration settings for Driver_AHB_PPCEXP0 in component ::Drivers:MPC
+#define RTE_AHB_PPCEXP0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_AHB_PPCEXP0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0]
+// <i> Configuration settings for Driver_APB_PPC0 in component ::Drivers:MPC
+#define RTE_APB_PPC0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1]
+// <i> Configuration settings for Driver_APB_PPC1 in component ::Drivers:MPC
+#define RTE_APB_PPC1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPC1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0]
+// <i> Configuration settings for Driver_APB_PPCEXP0 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP0 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP0]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1]
+// <i> Configuration settings for Driver_APB_PPCEXP1 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP1 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP1]
+
+// <e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2]
+// <i> Configuration settings for Driver_APB_PPCEXP2 in component ::Drivers:MPC
+#define RTE_APB_PPCEXP2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_APB_PPCEXP2]
+
+// <e> Flash device emulated by BRAM [Driver_Flash0]
+// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
+#define RTE_FLASH0 1
+// </e> Flash device emulated by BRAM [Driver_Flash0]
+
+#endif /* __RTE_DEVICE_H */
diff --git a/platform/ext/target/mps3/an524/cmsis_drivers/config/cmsis_driver_config.h b/platform/ext/target/mps3/an524/cmsis_drivers/config/cmsis_driver_config.h
new file mode 100644
index 0000000..0644561
--- /dev/null
+++ b/platform/ext/target/mps3/an524/cmsis_drivers/config/cmsis_driver_config.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_DRIVER_CONFIG_H__
+#define __CMSIS_DRIVER_CONFIG_H__
+
+#include "platform_description.h"
+#include "device_definition.h"
+
+#define UART0_CMSDK_DEV ARM_UART0_DEV_NS
+
+#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S
+#define MPC_ISRAM1_DEV MPC_ISRAM1_DEV_S
+#define MPC_ISRAM2_DEV MPC_ISRAM2_DEV_S
+#define MPC_ISRAM3_DEV MPC_ISRAM3_DEV_S
+#define MPC_QSPI_DEV MPC_QSPI_DEV_S
+
+#define AHB_PPCEXP0_DEV AHB_PPCEXP0_DEV_S
+#define APB_PPC0_DEV APB_PPC0_DEV_S
+#define APB_PPC1_DEV APB_PPC1_DEV_S
+#define APB_PPCEXP0_DEV APB_PPCEXP0_DEV_S
+#define APB_PPCEXP1_DEV APB_PPCEXP1_DEV_S
+#define APB_PPCEXP2_DEV APB_PPCEXP2_DEV_S
+
+#endif /* __CMSIS_DRIVER_CONFIG_H__ */
diff --git a/platform/ext/target/mps3/an524/device/config/device_cfg.h b/platform/ext/target/mps3/an524/device/config/device_cfg.h
new file mode 100644
index 0000000..9e7c8af
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/config/device_cfg.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_DEVICE_CFG_H__
+#define __ARM_LTD_DEVICE_CFG_H__
+
+/**
+ * \file device_cfg.h
+ * \brief
+ * This is the device configuration file with only used peripherals
+ * defined and configured via the secure and/or non-secure base address.
+ */
+
+/* ARM Memory Protection Controller (MPC) */
+#define MPC_ISRAM0_S
+#define MPC_ISRAM1_S
+#define MPC_ISRAM2_S
+#define MPC_ISRAM3_S
+#define MPC_QSPI_S
+
+/* ARM Peripheral Protection Controllers (PPC) */
+#define AHB_PPCEXP0_S
+#define APB_PPC0_S
+#define APB_PPC1_S
+#define APB_PPCEXP0_S
+#define APB_PPCEXP1_S
+#define APB_PPCEXP2_S
+
+/* ARM UART CMSDK */
+#define DEFAULT_UART_BAUDRATE 115200
+#define UART0_CMSDK_S
+#define UART0_CMSDK_NS
+#define UART1_CMSDK_S
+#define UART1_CMSDK_NS
+
+#endif /* __ARM_LTD_DEVICE_CFG_H__ */
diff --git a/platform/ext/target/mps3/an524/device/include/cmsis.h b/platform/ext/target/mps3/an524/device/include/cmsis.h
new file mode 100644
index 0000000..44068a1
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/include/cmsis.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __AN524_CMSIS_H__
+#define __AN524_CMSIS_H__
+
+/* ================== Start of section using anonymous unions ============ */
+#if defined (__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined (__ICCARM__)
+ #pragma language = extended
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #pragma clang diagnostic ignored "-Wc11-extensions"
+ #pragma clang diagnostic ignored "-Wreserved-id-macro"
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning 586
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+/*Setting shared by the two cores.*/
+#define __CM33_REV 0x02U /* Core revision r0p2 */
+#define __SAUREGION_PRESENT 1U /* SAU regions present */
+#define __MPU_PRESENT 1U /* MPU present */
+#define __VTOR_PRESENT 1U /* VTOR present */
+#define __NVIC_PRIO_BITS 4U /* Number of Bits used for
+ * Priority Levels */
+#define __Vendor_SysTickConfig 0U /* Set to 1 if different
+ * SysTick Config is used */
+
+#ifdef DUAL_CORE
+/* Both cores are used */
+#if defined CORE0
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+#elif defined CORE1
+#define __FPU_PRESENT 1U /* FPU present */
+#define __DSP_PRESENT 1U /* DSP extension present */
+#else
+#error "Either CORE0 or CORE1 must be defined for DUAL_CORE builds"
+#endif /* CORE0/1 */
+
+#else /* DUAL_CORE */
+/* Single core is used */
+#define __FPU_PRESENT 0U /* no FPU present */
+#define __DSP_PRESENT 0U /* no DSP extension present */
+#endif /* DUAL_CORE */
+
+#include "system_core_init.h"
+#include "platform_irq.h"
+#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
+
+/* ================== End of section using anonymous unions ============= */
+#if defined (__CC_ARM)
+ #pragma pop
+#elif defined (__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+#elif defined (__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined (__TASKING__)
+ #pragma warning restore
+#elif defined (__CSMC__)
+ /* anonymous unions are enabled by default */
+#else
+ #warning Not supported compiler type
+#endif
+
+#endif /* __AN524_CMSIS_H__ */
diff --git a/platform/ext/target/mps3/an524/device/include/device_definition.h b/platform/ext/target/mps3/an524/device/include/device_definition.h
new file mode 100644
index 0000000..a978ac9
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/include/device_definition.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file device_definition.h
+ * \brief The structure definitions in this file are exported based on the
+ * peripheral definitions from device_cfg.h.
+ * This file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#ifndef __DEVICE_DEFINITION_H__
+#define __DEVICE_DEFINITION_H__
+
+#include "device_cfg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ======= Defines peripheral configuration structures ======= */
+/* UART CMSDK driver structures */
+#ifdef UART0_CMSDK_S
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART0_DEV_S;
+#endif
+#ifdef UART0_CMSDK_NS
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART0_DEV_NS;
+#endif
+
+#ifdef UART1_CMSDK_S
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART1_DEV_S;
+#endif
+#ifdef UART1_CMSDK_NS
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART1_DEV_NS;
+#endif
+
+#ifdef UART2_CMSDK_S
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART2_DEV_S;
+#endif
+#ifdef UART2_CMSDK_NS
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART2_DEV_NS;
+#endif
+
+#ifdef UART3_CMSDK_S
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART3_DEV_S;
+#endif
+#ifdef UART3_CMSDK_NS
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART3_DEV_NS;
+#endif
+
+#ifdef UART4_CMSDK_S
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART4_DEV_S;
+#endif
+#ifdef UART4_CMSDK_NS
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART4_DEV_NS;
+#endif
+
+#ifdef UART5_CMSDK_S
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART5_DEV_S;
+#endif
+#ifdef UART5_CMSDK_NS
+#include "uart_cmsdk_drv.h"
+extern struct uart_cmsdk_dev_t ARM_UART5_DEV_NS;
+#endif
+
+/* ARM PPC driver structures */
+#ifdef AHB_PPC0_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t AHB_PPC0_DEV_S;
+#endif
+
+#ifdef AHB_PPCEXP0_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S;
+#endif
+
+#ifdef APB_PPC0_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPC0_DEV_S;
+#endif
+
+#ifdef APB_PPC1_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPC1_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP0_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP1_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S;
+#endif
+
+#ifdef APB_PPCEXP2_S
+#include "ppc_sse200_drv.h"
+extern struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S;
+#endif
+
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S;
+#endif
+#ifdef CMSDK_TIMER0_NS
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS;
+#endif
+
+#ifdef CMSDK_TIMER1_S
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S;
+#endif
+#ifdef CMSDK_TIMER1_NS
+#include "timer_cmsdk_drv.h"
+extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS;
+#endif
+
+/* ARM MPC SSE 200 driver structures */
+#ifdef MPC_ISRAM0_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S;
+#endif
+
+#ifdef MPC_ISRAM1_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S;
+#endif
+
+#ifdef MPC_ISRAM2_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S;
+#endif
+
+#ifdef MPC_ISRAM3_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S;
+#endif
+
+#ifdef MPC_BRAM_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_BRAM_DEV_S;
+#endif
+
+#ifdef MPC_QSPI_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_QSPI_DEV_S;
+#endif
+
+#ifdef MPC_DDR4_S
+#include "mpc_sie200_drv.h"
+extern struct mpc_sie200_dev_t MPC_DDR4_DEV_S;
+#endif
+
+#ifdef MPS3_IO_S
+#include "arm_mps3_io_drv.h"
+extern struct arm_mps3_io_dev_t MPS3_IO_DEV_S;
+#endif
+
+#ifdef MPS3_IO_NS
+#include "arm_mps3_io_drv.h"
+extern struct arm_mps3_io_dev_t MPS3_IO_DEV_NS;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DEVICE_DEFINITION_H__ */
diff --git a/platform/ext/target/mps3/an524/device/include/platform_base_address.h b/platform/ext/target/mps3/an524/device/include/platform_base_address.h
new file mode 100644
index 0000000..168a45f
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/include/platform_base_address.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_base_address.h
+ * \brief This file defines all the peripheral base addresses for MPS3 SSE-200
+ * AN524 platform.
+ */
+
+#ifndef __PLATFORM_BASE_ADDRESS_H_
+#define __PLATFORM_BASE_ADDRESS_H_
+
+/* ======= Defines peripherals memory map addresses ======= */
+/* Non-secure memory map addresses */
+#define CMSDK_TIMER0_BASE_NS 0x40000000
+#define CMSDK_TIMER1_BASE_NS 0x40001000
+#define CMSDK_DUALTIMER_BASE_NS 0x40002000
+#define CMSDK_SYSINFO_BASE_NS 0x40020000
+#define S32K_TIMER_BASE_NS 0x4002F000
+#define CMSDK_NSPCTRL_BASE_NS 0x40080000
+#define APB_WATCHDOG_BASE_NS 0x40081000
+#define GPIO0_BASE_NS 0x41100000
+#define GPIO1_BASE_NS 0x41101000
+#define GPIO2_BASE_NS 0x41102000
+#define GPIO3_BASE_NS 0x41103000
+#define I2C0_SBCON_BASE_NS 0x41200000 /* Touchscreen I2C Base Address */
+#define I2C1_SBCON_BASE_NS 0x41201000 /* Audio I2C Base Address */
+#define SSP0_BASE_NS 0x41202000 /* ADC SPI PL022 Base Address */
+#define SSP1_BASE_NS 0x41203000 /* Shield 0 SPI PL022 Base Address */
+#define SSP2_BASE_NS 0x41204000 /* Shield 1 SPI PL022 Base Address */
+#define I2C2_SBCON_BASE_NS 0x41205000 /* Shield 0 SBCon Base Address */
+#define I2C3_SBCON_BASE_NS 0x41206000 /* Shield 1 SBCon Base Address */
+#define I2C4_SBCON_BASE_NS 0x41208000 /* DDR4 EEPROM I2C Base Address */
+#define MPS3_IO_SCC_BASE_NS 0x41300000
+#define I2S_BASE_NS 0x41301000 /* Audio I2S Base Address */
+#define MPS3_IO_FPGAIO_BASE_NS 0x41302000
+#define UART0_BASE_NS 0x41303000
+#define UART1_BASE_NS 0x41304000
+#define UART2_BASE_NS 0x41305000
+#define UART3_BASE_NS 0x41306000
+#define UART4_BASE_NS 0x41307000
+#define UART5_BASE_NS 0x41308000
+#define CLCD_CONFIG_BASE_NS 0x4130A000
+#define RTC_BASE_NS 0x4130B000
+#define ETHERNET_BASE_NS 0x41400000
+
+/* Secure memory map addresses */
+#define CMSDK_TIMER0_BASE_S 0x50000000
+#define CMSDK_TIMER1_BASE_S 0x50001000
+#define CMSDK_DUALTIMER_BASE_S 0x50002000
+#define CMSDK_SYSINFO_BASE_S 0x50020000
+#define CMSDK_SYSCTRL_BASE_S 0x50021000
+#define S32K_WATCHDOG_BASE_S 0x5002E000
+#define S32K_TIMER_BASE_S 0x5002F000
+#define CMSDK_SPCTRL_BASE_S 0x50080000
+#define APB_WATCHDOG_BASE_S 0x50081000
+#define GPIO0_BASE_S 0x51100000
+#define GPIO1_BASE_S 0x51101000
+#define GPIO2_BASE_S 0x51102000
+#define GPIO3_BASE_S 0x51103000
+#define I2C0_SBCON_BASE_S 0x51200000
+#define I2C1_SBCON_BASE_S 0x51201000
+#define SSP0_BASE_S 0x51202000
+#define SSP1_BASE_S 0x51203000
+#define SSP2_BASE_S 0x51204000
+#define I2C2_SBCON_BASE_S 0x51205000
+#define I2C3_SBCON_BASE_S 0x51206000
+#define I2C4_SBCON_BASE_S 0x51208000
+#define MPS3_IO_SCC_BASE_S 0x51300000
+#define I2S_BASE_S 0x51301000
+#define MPS3_IO_FPGAIO_BASE_S 0x51302000
+#define UART0_BASE_S 0x51303000
+#define UART1_BASE_S 0x51304000
+#define UART2_BASE_S 0x51305000
+#define UART3_BASE_S 0x51306000
+#define UART4_BASE_S 0x51307000
+#define UART5_BASE_S 0x51308000
+#define CLCD_CONFIG_BASE_S 0x5130A000
+#define RTC_BASE_S 0x5130B000
+#define ETHERNET_BASE_S 0x51400000
+#define MPC_ISRAM0_BASE_S 0x50083000
+#define MPC_ISRAM1_BASE_S 0x50084000
+#define MPC_ISRAM2_BASE_S 0x50085000
+#define MPC_ISRAM3_BASE_S 0x50086000
+#define MPC_BRAM_BASE_S 0x58007000
+#define MPC_QSPI_BASE_S 0x58008000
+#define MPC_DDR4_BASE_S 0x58009000
+
+/* SRAM MPC ranges and limits */
+/* Internal memory */
+#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000
+#define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF
+#define MPC_ISRAM0_RANGE_BASE_S 0x30000000
+#define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF
+
+#define MPC_ISRAM1_RANGE_BASE_NS 0x20008000
+#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2000FFFF
+#define MPC_ISRAM1_RANGE_BASE_S 0x30008000
+#define MPC_ISRAM1_RANGE_LIMIT_S 0x3000FFFF
+
+#define MPC_ISRAM2_RANGE_BASE_NS 0x20010000
+#define MPC_ISRAM2_RANGE_LIMIT_NS 0x20017FFF
+#define MPC_ISRAM2_RANGE_BASE_S 0x30010000
+#define MPC_ISRAM2_RANGE_LIMIT_S 0x30017FFF
+
+#define MPC_ISRAM3_RANGE_BASE_NS 0x20018000
+#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2001FFFF
+#define MPC_ISRAM3_RANGE_BASE_S 0x30018000
+#define MPC_ISRAM3_RANGE_LIMIT_S 0x3001FFFF
+
+#ifdef REMAP_QSPI
+/* REMAP: QSPI memory map */
+/* FPGA BRAM memory */
+#define MPC_BRAM_RANGE_BASE_NS 0x28000000
+#define MPC_BRAM_RANGE_LIMIT_NS 0x2807FFFF
+#define MPC_BRAM_RANGE_BASE_S 0x38000000
+#define MPC_BRAM_RANGE_LIMIT_S 0x3807FFFF
+
+/* QSPI flash memory */
+#define MPC_QSPI_RANGE_BASE_NS 0x00000000
+#define MPC_QSPI_RANGE_LIMIT_NS 0x007FFFFF
+#define MPC_QSPI_RANGE_BASE_S 0x10000000
+#define MPC_QSPI_RANGE_LIMIT_S 0x107FFFFF
+
+#else
+/* Default BRAM remap memory map*/
+/* BRAM memory */
+#define MPC_BRAM_RANGE_BASE_NS 0x00000000
+#define MPC_BRAM_RANGE_LIMIT_NS 0x0007FFFF
+#define MPC_BRAM_RANGE_BASE_S 0x10000000
+#define MPC_BRAM_RANGE_LIMIT_S 0x1007FFFF
+
+/* QSPI flash memory */
+#define MPC_QSPI_RANGE_BASE_NS 0x28000000
+#define MPC_QSPI_RANGE_LIMIT_NS 0x287FFFFF
+#define MPC_QSPI_RANGE_BASE_S 0x38000000
+#define MPC_QSPI_RANGE_LIMIT_S 0x387FFFFF
+
+#endif /* REMAP_QSPI */
+
+/* DDR4 memory */
+#define MPC_DDR4_RANGE0_BASE_NS 0x60000000
+#define MPC_DDR4_RANGE0_LIMIT_NS 0x6FFFFFFF
+#define MPC_DDR4_RANGE0_BASE_S 0x70000000
+#define MPC_DDR4_RANGE0_LIMIT_S 0x7FFFFFFF
+
+#endif /* __PLATFORM_BASE_ADDRESS_H_ */
diff --git a/platform/ext/target/mps3/an524/device/include/platform_description.h b/platform/ext/target/mps3/an524/device/include/platform_description.h
new file mode 100644
index 0000000..85fc440
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/include/platform_description.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_AN524_DESCRIPTION_H__
+#define __ARM_LTD_AN524_DESCRIPTION_H__
+
+#include "platform_base_address.h"
+#include "platform_pins.h"
+#include "platform_regs.h"
+#include "cmsis.h"
+
+#endif /* __ARM_LTD_AN524_DESCRIPTION_H__ */
diff --git a/platform/ext/target/mps3/an524/device/include/platform_irq.h b/platform/ext/target/mps3/an524/device/include/platform_irq.h
new file mode 100644
index 0000000..c84684c
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/include/platform_irq.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_AN524_IRQ_H__
+#define __ARM_LTD_AN524_IRQ_H__
+
+typedef enum _IRQn_Type {
+ NonMaskableInt_IRQn = -14, /* Non Maskable Interrupt */
+ HardFault_IRQn = -13, /* HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /* Memory Management Interrupt */
+ BusFault_IRQn = -11, /* Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /* Usage Fault Interrupt */
+ SecureFault_IRQn = -9, /* Secure Fault Interrupt */
+ SVCall_IRQn = -5, /* SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /* Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /* Pend SV Interrupt */
+ SysTick_IRQn = -1, /* System Tick Interrupt */
+ NONSEC_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset
+ * Interrupt
+ */
+ NONSEC_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */
+ S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */
+ TIMER0_IRQn = 3, /* TIMER 0 Interrupt */
+ TIMER1_IRQn = 4, /* TIMER 1 Interrupt */
+ DUALTIMER_IRQn = 5, /* Dual Timer Interrupt */
+ MHU0_IRQn = 6, /* Message Handling Unit 0 */
+ MHU1_IRQn = 7, /* Message Handling Unit 1 */
+ MPC_IRQn = 9, /* MPC Combined (Secure) Interrupt */
+ PPC_IRQn = 10, /* PPC Combined (Secure) Interrupt */
+ MSC_IRQn = 11, /* MSC Combined (Secure) Interrput */
+ BRIDGE_ERROR_IRQn = 12, /* Bridge Error Combined
+ * (Secure) Interrupt
+ */
+ INVALID_INSTR_CACHE_IRQn = 13, /* CPU Instruction Cache Invalidation
+ * Interrupt
+ */
+ SYS_PPU_IRQn = 15, /* SYS PPU */
+ CPU0_PPU_IRQn = 16, /* CPU0 PPU */
+ CPU1_PPU_IRQn = 17, /* CPU1 PPU */
+ CPU0_DBG_PPU_IRQn = 18, /* CPU0 DBG PPU */
+ CPU1_DBG_PPU_IRQn = 19, /* CPU1 DBG PPU */
+ /* Reserved = 20, Reserved */
+ RAM0_PPU_IRQn = 22, /* RAM0 PPU */
+ RAM1_PPU_IRQn = 23, /* RAM1 PPU */
+ RAM2_PPU_IRQn = 24, /* RAM2 PPU */
+ RAM3_PPU_IRQn = 25, /* RAM3 PPU */
+ DEBUG_PPU_IRQn = 26, /* DEBUG PPU */
+ CPUx_CTI_IRQ0 = 28, /* CPUx CTI 0 */
+ CPUx_CTI_IRQ1 = 29, /* CPUx CTI 1 */
+ /* Reserved = 30, Reserved */
+ /* Reserved = 31, Reserved */
+ UARTRX0_IRQn = 32, /* UART 0 RX Interrupt */
+ UARTTX0_IRQn = 33, /* UART 0 TX Interrupt */
+ UARTRX1_IRQn = 34, /* UART 1 RX Interrupt */
+ UARTTX1_IRQn = 35, /* UART 1 TX Interrupt */
+ UARTRX2_IRQn = 36, /* UART 2 RX Interrupt */
+ UARTTX2_IRQn = 37, /* UART 2 TX Interrupt */
+ UARTRX3_IRQn = 38, /* UART 3 RX Interrupt */
+ UARTTX3_IRQn = 39, /* UART 3 TX Interrupt */
+ UARTRX4_IRQn = 40, /* UART 4 RX Interrupt */
+ UARTTX4_IRQn = 41, /* UART 4 TX Interrupt */
+ UART0_IRQn = 42, /* UART 0 combined Interrupt */
+ UART1_IRQn = 43, /* UART 1 combined Interrupt */
+ UART2_IRQn = 44, /* UART 2 combined Interrupt */
+ UART3_IRQn = 45, /* UART 3 combined Interrupt */
+ UART4_IRQn = 46, /* UART 4 combined Interrupt */
+ UARTOVF_IRQn = 47, /* UART 012345 Overflow Interrupt */
+ ETHERNET_IRQn = 48, /* Ethernet Interrupt */
+ I2S_IRQn = 49, /* I2S Interrupt */
+ TSC_IRQn = 50, /* Touch Screen Interrupt */
+ SPI0_IRQn = 52, /* SPI 0 Interrupt */
+ SPI1_IRQn = 53, /* SPI 1 Interrupt */
+ SPI2_IRQn = 54, /* SPI 2 Interrupt */
+ GPIO0_IRQn = 68, /* GPIO 0 Combined Interrupt */
+ GPIO1_IRQn = 69, /* GPIO 1 Combined Interrupt */
+ GPIO2_IRQn = 70, /* GPIO 2 Combined Interrupt */
+ GPIO3_IRQn = 71, /* GPIO 3 Combined Interrupt */
+ GPIO0_0_IRQn = 72, /* GPIO0 has 16 pins with IRQs */
+ GPIO0_1_IRQn = 73,
+ GPIO0_2_IRQn = 74,
+ GPIO0_3_IRQn = 75,
+ GPIO0_4_IRQn = 76,
+ GPIO0_5_IRQn = 77,
+ GPIO0_6_IRQn = 78,
+ GPIO0_7_IRQn = 79,
+ GPIO0_8_IRQn = 80,
+ GPIO0_9_IRQn = 81,
+ GPIO0_10_IRQn = 82,
+ GPIO0_11_IRQn = 83,
+ GPIO0_12_IRQn = 84,
+ GPIO0_13_IRQn = 85,
+ GPIO0_14_IRQn = 86,
+ GPIO0_15_IRQn = 87,
+ GPIO1_0_IRQn = 88, /* GPIO1 has 16 pins with IRQs */
+ GPIO1_1_IRQn = 89,
+ GPIO1_2_IRQn = 90,
+ GPIO1_3_IRQn = 91,
+ GPIO1_4_IRQn = 92,
+ GPIO1_5_IRQn = 93,
+ GPIO1_6_IRQn = 94,
+ GPIO1_7_IRQn = 95,
+ GPIO1_8_IRQn = 96,
+ GPIO1_9_IRQn = 97,
+ GPIO1_10_IRQn = 98,
+ GPIO1_11_IRQn = 99,
+ GPIO1_12_IRQn = 100,
+ GPIO1_13_IRQn = 101,
+ GPIO1_14_IRQn = 102,
+ GPIO1_15_IRQn = 103,
+ GPIO2_0_IRQn = 104, /* GPIO2 has 16 pins with IRQs */
+ GPIO2_1_IRQn = 105,
+ GPIO2_2_IRQn = 106,
+ GPIO2_3_IRQn = 107,
+ GPIO2_4_IRQn = 108,
+ GPIO2_5_IRQn = 109,
+ GPIO2_6_IRQn = 110,
+ GPIO2_7_IRQn = 111,
+ GPIO2_8_IRQn = 112,
+ GPIO2_9_IRQn = 113,
+ GPIO2_10_IRQn = 114,
+ GPIO2_11_IRQn = 115,
+ GPIO2_12_IRQn = 116,
+ GPIO2_13_IRQn = 117,
+ GPIO2_14_IRQn = 118,
+ GPIO2_15_IRQn = 119,
+ GPIO3_0_IRQn = 120, /* GPIO3 has 4 pins with IRQs */
+ GPIO3_1_IRQn = 121,
+ GPIO3_2_IRQn = 122,
+ GPIO3_3_IRQn = 123,
+ UARTRX5_IRQn = 124, /* UART 5 RX Interrupt */
+ UARTTX5_IRQn = 125, /* UART 5 TX Interrupt */
+ UART5_IRQn = 126, /* UART 5 combined Interrupt */
+ HDCLCD_IRQn = 127, /* HDCLCD Interrupt */
+} IRQn_Type;
+
+#endif /* __ARM_LTD_AN524_IRQ_H__ */
diff --git a/platform/ext/target/mps3/an524/device/include/platform_pins.h b/platform/ext/target/mps3/an524/device/include/platform_pins.h
new file mode 100644
index 0000000..e5fcfcc
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/include/platform_pins.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_pins.h
+ * \brief This file defines all the pins for this platform.
+ */
+
+#ifndef __ARM_LTD_AN524_PINS_H__
+#define __ARM_LTD_AN524_PINS_H__
+
+/* AHB GPIO pin names */
+enum arm_gpio_pin_name_t {
+ AHB_GPIO0_0 = 0U,
+ AHB_GPIO0_1,
+ AHB_GPIO0_2,
+ AHB_GPIO0_3,
+ AHB_GPIO0_4,
+ AHB_GPIO0_5,
+ AHB_GPIO0_6,
+ AHB_GPIO0_7,
+ AHB_GPIO0_8,
+ AHB_GPIO0_9,
+ AHB_GPIO0_10,
+ AHB_GPIO0_11,
+ AHB_GPIO0_12,
+ AHB_GPIO0_13,
+ AHB_GPIO0_14,
+ AHB_GPIO0_15,
+ AHB_GPIO1_0 = 0U,
+ AHB_GPIO1_1,
+ AHB_GPIO1_2,
+ AHB_GPIO1_3,
+ AHB_GPIO1_4,
+ AHB_GPIO1_5,
+ AHB_GPIO1_6,
+ AHB_GPIO1_7,
+ AHB_GPIO1_8,
+ AHB_GPIO1_9,
+ AHB_GPIO1_10,
+ AHB_GPIO1_11,
+ AHB_GPIO1_12,
+ AHB_GPIO1_13,
+ AHB_GPIO1_14,
+ AHB_GPIO1_15,
+ AHB_GPIO2_0 = 0U,
+ AHB_GPIO2_1,
+ AHB_GPIO2_2,
+ AHB_GPIO2_3,
+ AHB_GPIO2_4,
+ AHB_GPIO2_5,
+ AHB_GPIO2_6,
+ AHB_GPIO2_7,
+ AHB_GPIO2_8,
+ AHB_GPIO2_9,
+ AHB_GPIO2_10,
+ AHB_GPIO2_11,
+ AHB_GPIO2_12,
+ AHB_GPIO2_13,
+ AHB_GPIO2_14,
+ AHB_GPIO2_15,
+ AHB_GPIO3_0 = 0U,
+ AHB_GPIO3_1,
+ AHB_GPIO3_2,
+ AHB_GPIO3_3,
+ AHB_GPIO3_4,
+ AHB_GPIO3_5,
+ AHB_GPIO3_6,
+ AHB_GPIO3_7,
+ AHB_GPIO3_8,
+ AHB_GPIO3_9,
+ AHB_GPIO3_10,
+ AHB_GPIO3_11,
+ AHB_GPIO3_12,
+ AHB_GPIO3_13,
+ AHB_GPIO3_14,
+ AHB_GPIO3_15,
+};
+
+/*
+ * Pin definitions for the MPS3 Arduino adapter shields.
+ * Reference: Application Note AN524
+ */
+
+/* GPIO shield 0 definition */
+#define SH0_UART_RX AHB_GPIO0_0
+#define SH0_UART_TX AHB_GPIO0_1
+#define SH0_SPI_SS AHB_GPIO0_10
+#define SH0_SPI_MOSI AHB_GPIO0_11
+#define SH0_SPI_MISO AHB_GPIO0_12
+#define SH0_SPI_SCK AHB_GPIO0_13
+#define SH0_I2C_SDA AHB_GPIO0_14
+#define SH0_I2C_SCL AHB_GPIO0_15
+
+/* GPIO shield 1 definition */
+#define SH1_UART_RX AHB_GPIO1_0
+#define SH1_UART_TX AHB_GPIO1_1
+
+#define SH1_SPI_SS AHB_GPIO1_10
+#define SH1_SPI_MOSI AHB_GPIO1_11
+#define SH1_SPI_MISO AHB_GPIO1_12
+#define SH1_SPI_SCK AHB_GPIO1_13
+#define SH1_I2C_SDA AHB_GPIO1_14
+#define SH1_I2C_SCL AHB_GPIO1_15
+
+#endif /* __ARM_LTD_AN524_PINS_H__ */
diff --git a/platform/ext/target/mps3/an524/device/include/platform_regs.h b/platform/ext/target/mps3/an524/device/include/platform_regs.h
new file mode 100644
index 0000000..1e5e92f
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/include/platform_regs.h
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_AN524_REGS_H__
+#define __ARM_LTD_AN524_REGS_H__
+
+#include <stdint.h>
+
+/* System info memory mapped register access structure */
+struct sysinfo_t {
+ volatile uint32_t sys_version; /* (R/ ) System version */
+ volatile uint32_t sys_config; /* (R/ ) System configuration */
+ volatile uint32_t reserved0[1008];
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t reserved1[3];
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/* System control memory mapped register access structure */
+struct sysctrl_t {
+ volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
+ * Status Register
+ */
+ volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
+ * Set Register
+ */
+ volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
+ * Clear Register
+ */
+ volatile uint32_t scsecctrl; /* (R/W) System Control Security
+ * Control Register
+ */
+ volatile uint32_t fclk_div; /* (R/W) Fast Clock Divider
+ * Configuration Register
+ */
+ volatile uint32_t sysclk_div; /* (R/W) System Clock Divider
+ * Configuration Register
+ */
+ volatile uint32_t clockforce; /* (R/W) Clock Forces */
+ volatile uint32_t reserved0[57];
+ volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */
+ volatile uint32_t resetmask; /* (R/W) Reset MASK */
+ volatile uint32_t swreset; /* ( /W) Software Reset */
+ volatile uint32_t gretreg; /* (R/W) General Purpose Retention
+ * Register
+ */
+ volatile uint32_t initsvtor0; /* (R/W) Initial Secure Reset Vector
+ * Register For CPU 0
+ */
+ volatile uint32_t initsvtor1; /* (R/W) Initial Secure Reset
+ * Vector Register For CPU 1
+ */
+ volatile uint32_t cpuwait; /* (R/W) CPU Boot wait control
+ * after reset
+ */
+ volatile uint32_t nmi_enable; /* (R/W) NMI Enable Register */
+ volatile uint32_t wicctrl; /* (R/W) CPU WIC Request and
+ * Acknowledgment
+ */
+ volatile uint32_t ewctrl; /* (R/W) External Wakeup Control */
+ volatile uint32_t reserved1[54];
+ volatile uint32_t pdcm_pd_sys_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SYS
+ * Power Domain Sensitivity.
+ */
+ volatile uint32_t reserved2[2]; /* Reserved */
+ volatile uint32_t pdcm_pd_sram0_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM0 Power
+ * Domain Sensitivity.
+ */
+ volatile uint32_t pdcm_pd_sram1_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM1 Power
+ * Domain Sensitivity.
+ */
+ volatile uint32_t pdcm_pd_sram2_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM2 Power
+ * Domain Sensitivity.
+ */
+ volatile uint32_t pdcm_pd_sram3_sense; /* (R/W) Power Control Dependency
+ * Matrix PD_SRAM3 Power
+ * Domain Sensitivity.
+ */
+ volatile uint32_t reserved3[877]; /* Reserved */
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t reserved4[3];
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/* Secure Privilege Control */
+#define CMSDK_SPCTRL ((struct spctrl_def *)CMSDK_SPCTRL_BASE_S)
+
+/* SPCTRL memory mapped register access structure */
+struct spctrl_def {
+ volatile uint32_t spcsecctrl;
+ volatile uint32_t buswait;
+ volatile uint32_t reserved[2];
+ volatile uint32_t secrespcfg;
+ volatile uint32_t nsccfg;
+ volatile uint32_t reserved2;
+ volatile uint32_t secmpcintstat;
+ volatile uint32_t secppcintstat;
+ volatile uint32_t secppcintclr;
+ volatile uint32_t secppcinten;
+ volatile uint32_t reserved3;
+ volatile uint32_t secmscintstat;
+ volatile uint32_t secmscintclr;
+ volatile uint32_t secmscinten;
+ volatile uint32_t reserved4;
+ volatile uint32_t brgintstat;
+ volatile uint32_t brgintclr;
+ volatile uint32_t brginten;
+ volatile uint32_t reserved5;
+ volatile uint32_t ahbnsppc0;
+ volatile uint32_t reserved6[3];
+ volatile uint32_t ahbnsppcexp0;
+ volatile uint32_t ahbnsppcexp1;
+ volatile uint32_t ahbnsppcexp2;
+ volatile uint32_t ahbnsppcexp3;
+ volatile uint32_t apbnsppc0;
+ volatile uint32_t apbnsppc1;
+ volatile uint32_t reserved7[2];
+ volatile uint32_t apbnsppcexp0;
+ volatile uint32_t apbnsppcexp1;
+ volatile uint32_t apbnsppcexp2;
+ volatile uint32_t apbnsppcexp3;
+ volatile uint32_t ahbspppc0;
+ volatile uint32_t reserved8[3];
+ volatile uint32_t ahbspppcexp0;
+ volatile uint32_t ahbspppcexp1;
+ volatile uint32_t ahbspppcexp2;
+ volatile uint32_t ahbspppcexp3;
+ volatile uint32_t apbspppc0;
+ volatile uint32_t apbspppc1;
+ volatile uint32_t reserved9[2];
+ volatile uint32_t apbspppcexp0;
+ volatile uint32_t apbspppcexp1;
+ volatile uint32_t apbspppcexp2;
+ volatile uint32_t apbspppcexp3;
+ volatile uint32_t nsmscexp;
+ volatile uint32_t reserved10[959];
+ volatile uint32_t pid4;
+ volatile uint32_t pid5;
+ volatile uint32_t pid6;
+ volatile uint32_t pid7;
+ volatile uint32_t pid0;
+ volatile uint32_t pid1;
+ volatile uint32_t pid2;
+ volatile uint32_t pid3;
+ volatile uint32_t cid0;
+ volatile uint32_t cid1;
+ volatile uint32_t cid2;
+ volatile uint32_t cid3;
+};
+
+/* Throw out bus error when an access causes security violation */
+#define CMSDK_SECRESPCFG_BUS_ERR_MASK (1UL << 0)
+
+/* PPC interrupt position mask */
+#define CMSDK_APB_PPC0_INT_POS_MASK (1UL << 0)
+#define CMSDK_APB_PPC1_INT_POS_MASK (1UL << 1)
+#define CMSDK_APB_PPCEXP0_INT_POS_MASK (1UL << 4)
+#define CMSDK_APB_PPCEXP1_INT_POS_MASK (1UL << 5)
+#define CMSDK_APB_PPCEXP2_INT_POS_MASK (1UL << 6)
+#define CMSDK_APB_PPCEXP3_INT_POS_MASK (1UL << 7)
+#define CMSDK_AHB_PPCEXP0_INT_POS_MASK (1UL << 20)
+#define CMSDK_AHB_PPCEXP1_INT_POS_MASK (1UL << 21)
+#define CMSDK_AHB_PPCEXP2_INT_POS_MASK (1UL << 22)
+#define CMSDK_AHB_PPCEXP3_INT_POS_MASK (1UL << 23)
+
+/* Non-Secure Privilege Control */
+#define CMSDK_NSPCTRL ((struct nspctrl_def *)CMSDK_NSPCTRL_BASE_NS)
+
+/* NSPCTRL memory mapped register access structure */
+struct nspctrl_def {
+ volatile uint32_t reserved[36];
+ volatile uint32_t ahbnspppc0;
+ volatile uint32_t reserved3[3];
+ volatile uint32_t ahbnspppcexp0;
+ volatile uint32_t ahbnspppcexp1;
+ volatile uint32_t ahbnspppcexp2;
+ volatile uint32_t ahbnspppcexp3;
+ volatile uint32_t apbnspppc0;
+ volatile uint32_t apbnspppc1;
+ volatile uint32_t reserved4[2];
+ volatile uint32_t apbnspppcexp0;
+ volatile uint32_t apbnspppcexp1;
+ volatile uint32_t apbnspppcexp2;
+ volatile uint32_t apbnspppcexp3;
+ volatile uint32_t reserved5[960];
+ volatile uint32_t pidr4;
+ volatile uint32_t reserved7; /* pidr5 */
+ volatile uint32_t reserved8; /* pidr6 */
+ volatile uint32_t reserved9; /* pidr7 */
+ volatile uint32_t pidr0;
+ volatile uint32_t pidr1;
+ volatile uint32_t pidr2;
+ volatile uint32_t pidr3;
+ volatile uint32_t cidr0;
+ volatile uint32_t cidr1;
+ volatile uint32_t cidr2;
+ volatile uint32_t cidr3;
+};
+
+/* ARM APB PPC0 peripherals definition */
+#define CMSDK_TIMER0_APB_PPC_POS 0U
+#define CMSDK_TIMER1_APB_PPC_POS 1U
+#define CMSDK_DTIMER_APB_PPC_POS 2U
+#define CMSDK_MHU0_APB_PPC_POS 3U
+#define CMSDK_MHU1_APB_PPC_POS 4U
+/* The bits 31:5 are reserved */
+/* End ARM APB PPC0 peripherals definition */
+
+/* ARM APB PPC1 peripherals definition */
+#define CMSDK_S32K_TIMER_PPC_POS 0U
+/* The bits 31:1 are reserved */
+/* End ARM APB PPC1 peripherals definition */
+
+/* ARM APB PPCEXP0 peripherals definition */
+#define CMSDK_BRAM_MPC_APB_PPC_POS 0U
+#define CMSDK_QSPI_MPC_APB_PPC_POS 1U
+#define CMSDK_DDR4_MPC_APB_PPC_POS 2U
+/* The bits 31:3 are reserved */
+/* End ARM APB PPCEXP0 peripherals definition */
+
+/* ARM APB PPCEXP1 peripherals definition */
+#define CMSDK_I2C0_APB_PPC_POS 0U
+#define CMSDK_I2C1_APB_PPC_POS 1U
+#define CMSDK_SPI0_APB_PPC_POS 2U
+#define CMSDK_SPI1_APB_PPC_POS 3U
+#define CMSDK_SPI2_APB_PPC_POS 4U
+#define CMSDK_I2C2_APB_PPC_POS 5U
+#define CMSDK_I2C3_APB_PPC_POS 6U
+#define CMSDK_I2C4_APB_PPC_POS 8U
+/* The bits 7 and 31:9 are reserved */
+/* End ARM APB PPCEXP1 peripherals definition */
+
+/* ARM APB PPCEXP2 peripherals definition */
+#define CMSDK_FPGA_SCC_PPC_POS 0U
+#define CMSDK_FPGA_AUDIO_PPC_POS 1U
+#define CMSDK_FPGA_IO_PPC_POS 2U
+#define CMSDK_UART0_APB_PPC_POS 3U
+#define CMSDK_UART1_APB_PPC_POS 4U
+#define CMSDK_UART2_APB_PPC_POS 5U
+#define CMSDK_UART3_APB_PPC_POS 6U
+#define CMSDK_UART4_APB_PPC_POS 7U
+#define CMSDK_UART5_APB_PPC_POS 8U
+#define CMSDK_CLCD_APB_PPC_POS 10U
+#define CMSDK_RTC_APB_PPC_POS 11U
+/* The bits 9 and 31:12 are reserved */
+/* End ARM APB PPCEXP2 peripherals definition */
+
+/* ARM APB PPCEXP3 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End ARM APB PPCEXP3 peripherals definition */
+
+/* ARM AHB PPC0 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPC0 peripherals definition */
+
+/* ARM AHB PPCEXP0 peripherals definition */
+#define CMSDK_GPIO0_PPC_POS 0U
+#define CMSDK_GPIO1_PPC_POS 1U
+#define CMSDK_GPIO2_PPC_POS 2U
+#define CMSDK_GPIO3_PPC_POS 3U
+#define CMSDK_USB_ETHERNET_PPC_POS 4U
+#define CMSDK_USER0_PPC_POS 5U
+#define CMSDK_USER1_PPC_POS 6U
+#define CMSDK_USER2_PPC_POS 7U
+/* The bits 31:8 are reserved */
+/* End of ARM AHB PPCEXP0 peripherals definition */
+
+/* ARM AHB PPCEXP1 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPCEXP1 peripherals definition */
+
+/* ARM AHB PPCEXP2 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPCEXP2 peripherals definition */
+
+/* ARM AHB PPCEXP3 peripherals definition */
+/* The bits 31:0 are reserved */
+/* End of ARM AHB PPCEXP3 peripherals definition */
+
+#endif /* __ARM_LTD_AN524_REGS_H__ */
diff --git a/platform/ext/target/mps3/an524/device/include/system_core_init.h b/platform/ext/target/mps3/an524/device/include/system_core_init.h
new file mode 100644
index 0000000..ab59ce5
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/include/system_core_init.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_CORE_INIT_H__
+#define __SYSTEM_CORE_INIT_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */
+
+/**
+ * \brief Initializes the system
+ */
+extern void SystemInit(void);
+
+/**
+ * \brief Restores system core clock
+ */
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_CORE_INIT_H__ */
diff --git a/platform/ext/target/mps3/an524/device/source/armclang/mps3_an524_bl2.sct b/platform/ext/target/mps3/an524/device/source/armclang/mps3_an524_bl2.sct
new file mode 100644
index 0000000..ab80d66
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/armclang/mps3_an524_bl2.sct
@@ -0,0 +1,40 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "region_defs.h"
+
+LR_CODE BL2_CODE_START {
+ ER_CODE BL2_CODE_START BL2_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ TFM_SHARED_DATA BL2_DATA_START ALIGN 32 EMPTY BOOT_TFM_SHARED_DATA_SIZE {
+ }
+
+ ER_DATA +0 BL2_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+
+ /* MSP */
+ ARM_LIB_STACK +0 ALIGN 32 EMPTY BL2_MSP_STACK_SIZE {
+ }
+
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY BL2_HEAP_SIZE {
+ }
+}
diff --git a/platform/ext/target/mps3/an524/device/source/armclang/mps3_an524_ns.sct b/platform/ext/target/mps3/an524/device/source/armclang/mps3_an524_ns.sct
new file mode 100644
index 0000000..270d423
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/armclang/mps3_an524_ns.sct
@@ -0,0 +1,41 @@
+#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
+
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "region_defs.h"
+
+LR_CODE NS_CODE_START {
+ ER_CODE NS_CODE_START NS_CODE_SIZE {
+ *.o (RESET +First)
+ .ANY (+RO)
+ }
+
+ ER_DATA NS_DATA_START NS_DATA_SIZE {
+ .ANY (+ZI +RW)
+ }
+
+ /* MSP */
+ ARM_LIB_STACK_MSP +0 ALIGN 32 EMPTY NS_MSP_STACK_SIZE {
+ }
+
+ /* PSP */
+ ARM_LIB_STACK +0 ALIGN 32 EMPTY NS_PSP_STACK_SIZE {
+ }
+
+ ARM_LIB_HEAP +0 ALIGN 8 EMPTY NS_HEAP_SIZE {
+ }
+}
diff --git a/platform/ext/target/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_bl2.s b/platform/ext/target/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_bl2.s
new file mode 100644
index 0000000..98d325e
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_bl2.s
@@ -0,0 +1,514 @@
+;/*
+; * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Process Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors
+ DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; 2 S32K Timer Handler
+ DCD TIMER0_Handler ; 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; 5 Dual Timer Handler
+ DCD 0 ; 6 Reserved
+ DCD 0 ; 7 Reserved
+ DCD 0 ; 8 Reserved
+ DCD MPC_Handler ; 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; 10 PPC Combined (Secure) Handler
+ DCD MSC_Handler ; 11 MSC Combined (Secure) Handler
+ DCD BRIDGE_ERROR_Handler ; 12 Bridge Error Combined (Secure)
+ ; Handler
+ DCD 0 ; 13 Reserved
+ DCD 0 ; 14 Reserved
+ DCD 0 ; 15 Reserved
+ DCD 0 ; 16 Reserved
+ DCD 0 ; 17 Reserved
+ DCD 0 ; 18 Reserved
+ DCD 0 ; 19 Reserved
+ DCD 0 ; 20 Reserved
+ DCD 0 ; 21 Reserved
+ DCD 0 ; 22 Reserved
+ DCD 0 ; 23 Reserved
+ DCD 0 ; 24 Reserved
+ DCD 0 ; 25 Reserved
+ DCD 0 ; 26 Reserved
+ DCD 0 ; 27 Reserved
+ DCD CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+ DCD CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+ DCD 0 ; 30 Reserved
+ DCD 0 ; 31 Reserved
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 2 combined Handler
+ DCD UART3_Handler ; 45 UART 3 combined Handler
+ DCD UART4_Handler ; 46 UART 4 combined Handler
+ DCD UARTOVF_Handler ; 47 UART Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD 0 ; 51 Reserved
+ DCD SPI0_Handler ; 52 SPI ADC Handler
+ DCD SPI1_Handler ; 53 SPI (Shield 0) Handler
+ DCD SPI2_Handler ; 54 SPI (Shield 1) Handler
+ DCD 0 ; 55 Reserved
+ DCD 0 ; 56 Reserved
+ DCD 0 ; 57 Reserved
+ DCD 0 ; 58 Reserved
+ DCD 0 ; 59 Reserved
+ DCD 0 ; 60 Reserved
+ DCD 0 ; 61 Reserved
+ DCD 0 ; 62 Reserved
+ DCD 0 ; 63 Reserved
+ DCD 0 ; 64 Reserved
+ DCD 0 ; 65 Reserved
+ DCD 0 ; 66 Reserved
+ DCD 0 ; 67 Reserved
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72 GPIO0_0 Handler
+ DCD GPIO0_1_Handler ; 73 GPIO0_1 Handler
+ DCD GPIO0_2_Handler ; 74 GPIO0_2 Handler
+ DCD GPIO0_3_Handler ; 75 GPIO0_3 Handler
+ DCD GPIO0_4_Handler ; 76 GPIO0_4 Handler
+ DCD GPIO0_5_Handler ; 77 GPIO0_5 Handler
+ DCD GPIO0_6_Handler ; 78 GPIO0_6 Handler
+ DCD GPIO0_7_Handler ; 79 GPIO0_7 Handler
+ DCD GPIO0_8_Handler ; 80 GPIO0_8 Handler
+ DCD GPIO0_9_Handler ; 81 GPIO0_9 Handler
+ DCD GPIO0_10_Handler ; 82 GPIO0_10 Handler
+ DCD GPIO0_11_Handler ; 83 GPIO0_11 Handler
+ DCD GPIO0_12_Handler ; 84 GPIO0_12 Handler
+ DCD GPIO0_13_Handler ; 85 GPIO0_13 Handler
+ DCD GPIO0_14_Handler ; 86 GPIO0_14 Handler
+ DCD GPIO0_15_Handler ; 87 GPIO0_15 Handler
+ DCD GPIO1_0_Handler ; 88 GPIO1_0 Handler
+ DCD GPIO1_1_Handler ; 89 GPIO1_1 Handler
+ DCD GPIO1_2_Handler ; 90 GPIO1_2 Handler
+ DCD GPIO1_3_Handler ; 91 GPIO1_3 Handler
+ DCD GPIO1_4_Handler ; 92 GPIO1_4 Handler
+ DCD GPIO1_5_Handler ; 93 GPIO1_5 Handler
+ DCD GPIO1_6_Handler ; 94 GPIO1_6 Handler
+ DCD GPIO1_7_Handler ; 95 GPIO1_7 Handler
+ DCD GPIO1_8_Handler ; 96 GPIO1_8 Handler
+ DCD GPIO1_9_Handler ; 97 GPIO1_0 Handler
+ DCD GPIO1_10_Handler ; 98 GPIO1_10 Handler
+ DCD GPIO1_11_Handler ; 99 GPIO1_11 Handler
+ DCD GPIO1_12_Handler ; 100 GPIO1_12 Handler
+ DCD GPIO1_13_Handler ; 101 GPIO1_13 Handler
+ DCD GPIO1_14_Handler ; 102 GPIO1_14 Handler
+ DCD GPIO1_15_Handler ; 103 GPIO1_15 Handler
+ DCD GPIO2_0_Handler ; 104 GPIO2_0 Handler
+ DCD GPIO2_1_Handler ; 105 GPIO2_1 Handler
+ DCD GPIO2_2_Handler ; 106 GPIO2_2 Handler
+ DCD GPIO2_3_Handler ; 107 GPIO2_3 Handler
+ DCD GPIO2_4_Handler ; 108 GPIO2_4 Handler
+ DCD GPIO2_5_Handler ; 109 GPIO2_5 Handler
+ DCD GPIO2_6_Handler ; 110 GPIO2_6 Handler
+ DCD GPIO2_7_Handler ; 111 GPIO2_7 Handler
+ DCD GPIO2_8_Handler ; 112 GPIO2_8 Handler
+ DCD GPIO2_9_Handler ; 113 GPIO2_9 Handler
+ DCD GPIO2_10_Handler ; 114 GPIO2_10 Handler
+ DCD GPIO2_11_Handler ; 115 GPIO2_11 Handler
+ DCD GPIO2_12_Handler ; 116 GPIO2_12 Handler
+ DCD GPIO2_13_Handler ; 117 GPIO2_13 Handler
+ DCD GPIO2_14_Handler ; 118 GPIO2_14 Handler
+ DCD GPIO2_15_Handler ; 119 GPIO2_15 Handler
+ DCD GPIO3_0_Handler ; 120 GPIO2_16 Handler
+ DCD GPIO3_1_Handler ; 121 GPIO3_0 Handler
+ DCD GPIO3_2_Handler ; 122 GPIO3_1 Handler
+ DCD GPIO3_3_Handler ; 123 GPIO3_3 Handler
+ DCD UARTRX5_Handler ; 124 UART 5 RX Handler
+ DCD UARTTX5_Handler ; 125 UART 5 TX Handler
+ DCD UART5_Handler ; 126 UART 5 combined Handler
+ DCD HDLCD_Handler ; 127 HDCLCD interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler \
+ PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler \
+ PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+
+HardFault_Handler \
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+MemManage_Handler \
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+
+BusFault_Handler \
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+
+UsageFault_Handler \
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SecureFault_Handler \
+ PROC
+ EXPORT SecureFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler \
+ PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+
+DebugMon_Handler \
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+
+PendSV_Handler \
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+
+SysTick_Handler \
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+MPC_Handler \
+ PROC
+ EXPORT MPC_Handler [WEAK]
+ B .
+ ENDP
+
+PPC_Handler \
+ PROC
+ EXPORT PPC_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler \
+ PROC
+ ; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; 0 Non-Secure Watchdog
+ ; Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; 5 Dual Timer Handler
+ EXPORT MHU0_Handler [WEAK] ; 6 Message Handling Unit 0
+ EXPORT MHU1_Handler [WEAK] ; 7 Message Handling Unit 1
+ EXPORT MPC_Handler [WEAK] ; 9 MPC Combined (Secure)
+ ; Handler
+ EXPORT PPC_Handler [WEAK] ; 10 PPC Combined (Secure)
+ ; Handler
+ EXPORT MSC_Handler [WEAK] ; 11 MSC Combined (Secure)
+ ; Handler
+ EXPORT BRIDGE_ERROR_Handler [WEAK] ; 12 Bridge Error Combined
+ ; (Secure) Handler
+ EXPORT INVALID_INSTR_CACHE_Handler [WEAK] ; 13 CPU Instruction Cache
+ ; Invalidation Handler
+ EXPORT SYS_PPU_Handler [WEAK] ; 15 SYS PPU Handler
+ EXPORT CPU0_PPU_Handler [WEAK] ; 16 CPU0 PPU Handler
+ EXPORT CPU1_PPU_Handler [WEAK] ; 17 CPU1 PPU Handler
+ EXPORT CPU0_DBG_PPU_Handler [WEAK] ; 18 CPU0 DBG PPU_Handler
+ EXPORT CPU1_DBG_PPU_Handler [WEAK] ; 19 CPU1 DBG PPU_Handler
+ EXPORT CRYPT_PPU_Handler [WEAK] ; 20 CRYPT PPU Handler
+ EXPORT CORDIO_PPU_Handler [WEAK] ; 21 CORDIO PPU Handler
+ EXPORT RAM0_PPU_Handler [WEAK] ; 22 RAM0 PPU Handler
+ EXPORT RAM1_PPU_Handler [WEAK] ; 23 RAM1 PPU Handler
+ EXPORT RAM2_PPU_Handler [WEAK] ; 24 RAM2 PPU Handler
+ EXPORT RAM3_PPU_Handler [WEAK] ; 25 RAM3 PPU Handler
+ EXPORT CPU0_CTI_Handler [WEAK] ; 28 CPU0 CTI Handler
+ EXPORT CPU1_CTI_Handler [WEAK] ; 29 CPU1 CTI Handler
+ ; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+ EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
+ EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
+ EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
+ EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
+ EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
+ EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
+ EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
+ EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
+ EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
+ EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
+ EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
+ EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
+ EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
+ EXPORT UARTOVF_Handler [WEAK] ; 47 UART Overflow Handler
+ EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
+ EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
+ EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
+ EXPORT SPI0_Handler [WEAK] ; 52 SPI ADC Handler
+ EXPORT SPI1_Handler [WEAK] ; 53 SPI (Shield 0) Handler
+ EXPORT SPI2_Handler [WEAK] ; 54 SPI (Shield 1) Handler
+ EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
+ EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
+ EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
+ EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
+ EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO0_0 Handlers
+ EXPORT GPIO0_1_Handler [WEAK] ; 73 GPIO0_1 Handler
+ EXPORT GPIO0_2_Handler [WEAK] ; 74 GPIO0_2 Handler
+ EXPORT GPIO0_3_Handler [WEAK] ; 75 GPIO0_3 Handler
+ EXPORT GPIO0_4_Handler [WEAK] ; 76 GPIO0_4 Handler
+ EXPORT GPIO0_5_Handler [WEAK] ; 77 GPIO0_5 Handler
+ EXPORT GPIO0_6_Handler [WEAK] ; 78 GPIO0_6 Handler
+ EXPORT GPIO0_7_Handler [WEAK] ; 79 GPIO0_7 Handler
+ EXPORT GPIO0_8_Handler [WEAK] ; 80 GPIO0_8 Handler
+ EXPORT GPIO0_9_Handler [WEAK] ; 81 GPIO0_9 Handler
+ EXPORT GPIO0_10_Handler [WEAK] ; 82 GPIO0_10 Handler
+ EXPORT GPIO0_11_Handler [WEAK] ; 83 GPIO0_11 Handler
+ EXPORT GPIO0_12_Handler [WEAK] ; 84 GPIO0_12 Handler
+ EXPORT GPIO0_13_Handler [WEAK] ; 85 GPIO0_13 Handler
+ EXPORT GPIO0_14_Handler [WEAK] ; 86 GPIO0_14 Handler
+ EXPORT GPIO0_15_Handler [WEAK] ; 87 GPIO0_15 Handler
+ EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO1_0 Handler
+ EXPORT GPIO1_1_Handler [WEAK] ; 89 GPIO1_1 Handler
+ EXPORT GPIO1_2_Handler [WEAK] ; 90 GPIO1_2 Handler
+ EXPORT GPIO1_3_Handler [WEAK] ; 91 GPIO1_3 Handler
+ EXPORT GPIO1_4_Handler [WEAK] ; 92 GPIO1_4 Handler
+ EXPORT GPIO1_5_Handler [WEAK] ; 93 GPIO1_5 Handler
+ EXPORT GPIO1_6_Handler [WEAK] ; 94 GPIO1_6 Handler
+ EXPORT GPIO1_7_Handler [WEAK] ; 95 GPIO1_7 Handler
+ EXPORT GPIO1_8_Handler [WEAK] ; 96 GPIO1_8 Handler
+ EXPORT GPIO1_9_Handler [WEAK] ; 97 GPIO1_9 Handler
+ EXPORT GPIO1_10_Handler [WEAK] ; 98 GPIO1_10 Handler
+ EXPORT GPIO1_11_Handler [WEAK] ; 99 GPIO1_11 Handler
+ EXPORT GPIO1_12_Handler [WEAK] ; 100 GPIO1_12 Handler
+ EXPORT GPIO1_13_Handler [WEAK] ; 101 GPIO1_13 Handler
+ EXPORT GPIO1_14_Handler [WEAK] ; 102 GPIO1_14 Handler
+ EXPORT GPIO1_15_Handler [WEAK] ; 103 GPIO1_15 Handler
+ EXPORT GPIO2_0_Handler [WEAK] ; 104 GPIO2_0 Handler
+ EXPORT GPIO2_1_Handler [WEAK] ; 105 GPIO2_1 Handler
+ EXPORT GPIO2_2_Handler [WEAK] ; 106 GPIO2_2 Handler
+ EXPORT GPIO2_3_Handler [WEAK] ; 107 GPIO2_3 Handler
+ EXPORT GPIO2_4_Handler [WEAK] ; 108 GPIO2_4 Handler
+ EXPORT GPIO2_5_Handler [WEAK] ; 109 GPIO2_5 Handler
+ EXPORT GPIO2_6_Handler [WEAK] ; 110 GPIO2_6 Handler
+ EXPORT GPIO2_7_Handler [WEAK] ; 111 GPIO2_7 Handler
+ EXPORT GPIO2_8_Handler [WEAK] ; 112 GPIO2_8 Handler
+ EXPORT GPIO2_9_Handler [WEAK] ; 113 GPIO2_9 Handler
+ EXPORT GPIO2_10_Handler [WEAK] ; 114 GPIO2_10 Handler
+ EXPORT GPIO2_11_Handler [WEAK] ; 115 GPIO2_11 Handler
+ EXPORT GPIO2_12_Handler [WEAK] ; 116 GPIO2_12 Handler
+ EXPORT GPIO2_13_Handler [WEAK] ; 117 GPIO2_13 Handler
+ EXPORT GPIO2_14_Handler [WEAK] ; 118 GPIO2_14 Handler
+ EXPORT GPIO2_15_Handler [WEAK] ; 119 GPIO2_15 Handler
+ EXPORT GPIO3_0_Handler [WEAK] ; 120 GPIO3_0 Handler
+ EXPORT GPIO3_1_Handler [WEAK] ; 121 GPIO3_1 Handler
+ EXPORT GPIO3_2_Handler [WEAK] ; 122 GPIO3_2 Handler
+ EXPORT GPIO3_3_Handler [WEAK] ; 123 GPIO3_3 Handler
+ EXPORT UARTRX5_Handler [WEAK] ; 124 UART 5 RX Handler
+ EXPORT UARTTX5_Handler [WEAK] ; 125 UART 5 TX Handler
+ EXPORT UART5_Handler [WEAK] ; 126 UART 5 combined Handler
+ EXPORT HDLCD_Handler [WEAK] ; 127 HDCLCD interrupt
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; 2 S32K Timer Handler
+TIMER0_Handler ; 3 TIMER 0 Handler
+TIMER1_Handler ; 4 TIMER 1 Handler
+DUALTIMER_Handler ; 5 Dual Timer Handler
+MHU0_Handler ; 6 Message Handling Unit 0
+MHU1_Handler ; 7 Message Handling Unit 1
+MSC_Handler ; 11 MSC Combined (Secure) Handler
+BRIDGE_ERROR_Handler ; 12 Bridge Error Combined (Secure) Handler
+INVALID_INSTR_CACHE_Handler ; 13 CPU Instruction Cache Invalidation Handler
+SYS_PPU_Handler ; 15 SYS PPU Handler
+CPU0_PPU_Handler ; 16 CPU0 PPU Handler
+CPU1_PPU_Handler ; 17 CPU1 PPU Handler
+CPU0_DBG_PPU_Handler ; 18 CPU0 DBG PPU_Handler
+CPU1_DBG_PPU_Handler ; 19 CPU1 DBG PPU_Handler
+CRYPT_PPU_Handler ; 20 CRYPT PPU Handler
+CORDIO_PPU_Handler ; 21 CORDIO PPU Handler
+RAM0_PPU_Handler ; 22 RAM0 PPU Handler
+RAM1_PPU_Handler ; 23 RAM1 PPU Handler
+RAM2_PPU_Handler ; 24 RAM2 PPU Handler
+RAM3_PPU_Handler ; 25 RAM3 PPU Handler
+CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 52 SPI ADC Handler
+SPI1_Handler ; 53 SPI (Shield 0) Handler
+SPI2_Handler ; 54 SPI (Shield 1) Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO0_0 Handler
+GPIO0_1_Handler ; 73 GPIO0_1 Handler
+GPIO0_2_Handler ; 74 GPIO0_2 Handler
+GPIO0_3_Handler ; 75 GPIO0_3 Handler
+GPIO0_4_Handler ; 76 GPIO0_4 Handler
+GPIO0_5_Handler ; 77 GPIO0_5 Handler
+GPIO0_6_Handler ; 78 GPIO0_6 Handler
+GPIO0_7_Handler ; 79 GPIO0_7 Handler
+GPIO0_8_Handler ; 80 GPIO0_8 Handler
+GPIO0_9_Handler ; 81 GPIO0_9 Handler
+GPIO0_10_Handler ; 82 GPIO0_10 Handler
+GPIO0_11_Handler ; 83 GPIO0_11 Handler
+GPIO0_12_Handler ; 84 GPIO0_12 Handler
+GPIO0_13_Handler ; 85 GPIO0_13 Handler
+GPIO0_14_Handler ; 86 GPIO0_14 Handler
+GPIO0_15_Handler ; 87 GPIO0_15 Handler
+GPIO1_0_Handler ; 88 GPIO1_0 Handler
+GPIO1_1_Handler ; 89 GPIO1_1 Handler
+GPIO1_2_Handler ; 90 GPIO1_2 Handler
+GPIO1_3_Handler ; 91 GPIO1_3 Handler
+GPIO1_4_Handler ; 92 GPIO1_4 Handler
+GPIO1_5_Handler ; 93 GPIO1_5 Handler
+GPIO1_6_Handler ; 94 GPIO1_6 Handler
+GPIO1_7_Handler ; 95 GPIO1_7 Handler
+GPIO1_8_Handler ; 96 GPIO1_8 Handler
+GPIO1_9_Handler ; 97 GPIO1_9 Handler
+GPIO1_10_Handler ; 98 GPIO1_10 Handler
+GPIO1_11_Handler ; 99 GPIO1_11 Handler
+GPIO1_12_Handler ; 100 GPIO1_12 Handler
+GPIO1_13_Handler ; 101 GPIO1_13 Handler
+GPIO1_14_Handler ; 102 GPIO1_14 Handler
+GPIO1_15_Handler ; 103 GPIO1_15 Handler
+GPIO2_0_Handler ; 104 GPIO2_0 Handler
+GPIO2_1_Handler ; 105 GPIO2_1 Handler
+GPIO2_2_Handler ; 106 GPIO2_2 Handler
+GPIO2_3_Handler ; 107 GPIO2_3 Handler
+GPIO2_4_Handler ; 108 GPIO2_4 Handler
+GPIO2_5_Handler ; 109 GPIO2_5 Handler
+GPIO2_6_Handler ; 110 GPIO2_6 Handler
+GPIO2_7_Handler ; 111 GPIO2_7 Handler
+GPIO2_8_Handler ; 112 GPIO2_8 Handler
+GPIO2_9_Handler ; 113 GPIO2_9 Handler
+GPIO2_10_Handler ; 114 GPIO2_10 Handler
+GPIO2_11_Handler ; 115 GPIO2_11 Handler
+GPIO2_12_Handler ; 116 GPIO2_12 Handler
+GPIO2_13_Handler ; 117 GPIO2_13 Handler
+GPIO2_14_Handler ; 118 GPIO2_14 Handler
+GPIO2_15_Handler ; 119 GPIO2_15 Handler
+GPIO3_0_Handler ; 120 GPIO3_0 Handler
+GPIO3_1_Handler ; 121 GPIO2_1 Handler
+GPIO3_2_Handler ; 122 GPIO2_2 Handler
+GPIO3_3_Handler ; 123 GPIO2_3 Handler
+UARTRX5_Handler ; 124 UART 5 RX Handler
+UARTTX5_Handler ; 125 UART 5 TX Handler
+UART5_Handler ; 125 UART 5 combined Handler
+HDLCD_Handler ; 127 HDCLCD interrupt Handler
+ B .
+
+ ENDP
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_ns.s b/platform/ext/target/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_ns.s
new file mode 100644
index 0000000..d39259e
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_ns.s
@@ -0,0 +1,486 @@
+;/*
+; * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Process Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors
+ DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; 2 S32K Timer Handler
+ DCD TIMER0_Handler ; 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; 5 Dual Timer Handler
+ DCD 0 ; 6 Reserved
+ DCD 0 ; 7 Reserved
+ DCD 0 ; 8 Reserved
+ DCD 0 ; 9 Reserved
+ DCD 0 ; 10 Reserved
+ DCD 0 ; 11 Reserved
+ DCD 0 ; 12 Reserved
+ DCD 0 ; 13 Reserved
+ DCD 0 ; 14 Reserved
+ DCD 0 ; 15 Reserved
+ DCD 0 ; 16 Reserved
+ DCD 0 ; 17 Reserved
+ DCD 0 ; 18 Reserved
+ DCD 0 ; 19 Reserved
+ DCD 0 ; 20 Reserved
+ DCD 0 ; 21 Reserved
+ DCD 0 ; 22 Reserved
+ DCD 0 ; 23 Reserved
+ DCD 0 ; 24 Reserved
+ DCD 0 ; 25 Reserved
+ DCD 0 ; 26 Reserved
+ DCD 0 ; 27 Reserved
+ DCD CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+ DCD CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+ DCD 0 ; 30 Reserved
+ DCD 0 ; 31 Reserved
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 2 combined Handler
+ DCD UART3_Handler ; 45 UART 3 combined Handler
+ DCD UART4_Handler ; 46 UART 4 combined Handler
+ DCD UARTOVF_Handler ; 47 UART Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD 0 ; 51 Reserved
+ DCD SPI0_Handler ; 52 SPI ADC Handler
+ DCD SPI1_Handler ; 53 SPI (Shield 0) Handler
+ DCD SPI2_Handler ; 54 SPI (Shield 1) Handler
+ DCD 0 ; 55 Reserved
+ DCD 0 ; 56 Reserved
+ DCD 0 ; 57 Reserved
+ DCD 0 ; 58 Reserved
+ DCD 0 ; 59 Reserved
+ DCD 0 ; 60 Reserved
+ DCD 0 ; 61 Reserved
+ DCD 0 ; 62 Reserved
+ DCD 0 ; 63 Reserved
+ DCD 0 ; 64 Reserved
+ DCD 0 ; 65 Reserved
+ DCD 0 ; 66 Reserved
+ DCD 0 ; 67 Reserved
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72 GPIO0_0 Handler
+ DCD GPIO0_1_Handler ; 73 GPIO0_1 Handler
+ DCD GPIO0_2_Handler ; 74 GPIO0_2 Handler
+ DCD GPIO0_3_Handler ; 75 GPIO0_3 Handler
+ DCD GPIO0_4_Handler ; 76 GPIO0_4 Handler
+ DCD GPIO0_5_Handler ; 77 GPIO0_5 Handler
+ DCD GPIO0_6_Handler ; 78 GPIO0_6 Handler
+ DCD GPIO0_7_Handler ; 79 GPIO0_7 Handler
+ DCD GPIO0_8_Handler ; 80 GPIO0_8 Handler
+ DCD GPIO0_9_Handler ; 81 GPIO0_9 Handler
+ DCD GPIO0_10_Handler ; 82 GPIO0_10 Handler
+ DCD GPIO0_11_Handler ; 83 GPIO0_11 Handler
+ DCD GPIO0_12_Handler ; 84 GPIO0_12 Handler
+ DCD GPIO0_13_Handler ; 85 GPIO0_13 Handler
+ DCD GPIO0_14_Handler ; 86 GPIO0_14 Handler
+ DCD GPIO0_15_Handler ; 87 GPIO0_15 Handler
+ DCD GPIO1_0_Handler ; 88 GPIO1_0 Handler
+ DCD GPIO1_1_Handler ; 89 GPIO1_1 Handler
+ DCD GPIO1_2_Handler ; 90 GPIO1_2 Handler
+ DCD GPIO1_3_Handler ; 91 GPIO1_3 Handler
+ DCD GPIO1_4_Handler ; 92 GPIO1_4 Handler
+ DCD GPIO1_5_Handler ; 93 GPIO1_5 Handler
+ DCD GPIO1_6_Handler ; 94 GPIO1_6 Handler
+ DCD GPIO1_7_Handler ; 95 GPIO1_7 Handler
+ DCD GPIO1_8_Handler ; 96 GPIO1_8 Handler
+ DCD GPIO1_9_Handler ; 97 GPIO1_0 Handler
+ DCD GPIO1_10_Handler ; 98 GPIO1_10 Handler
+ DCD GPIO1_11_Handler ; 99 GPIO1_11 Handler
+ DCD GPIO1_12_Handler ; 100 GPIO1_12 Handler
+ DCD GPIO1_13_Handler ; 101 GPIO1_13 Handler
+ DCD GPIO1_14_Handler ; 102 GPIO1_14 Handler
+ DCD GPIO1_15_Handler ; 103 GPIO1_15 Handler
+ DCD GPIO2_0_Handler ; 104 GPIO2_0 Handler
+ DCD GPIO2_1_Handler ; 105 GPIO2_1 Handler
+ DCD GPIO2_2_Handler ; 106 GPIO2_2 Handler
+ DCD GPIO2_3_Handler ; 107 GPIO2_3 Handler
+ DCD GPIO2_4_Handler ; 108 GPIO2_4 Handler
+ DCD GPIO2_5_Handler ; 109 GPIO2_5 Handler
+ DCD GPIO2_6_Handler ; 110 GPIO2_6 Handler
+ DCD GPIO2_7_Handler ; 111 GPIO2_7 Handler
+ DCD GPIO2_8_Handler ; 112 GPIO2_8 Handler
+ DCD GPIO2_9_Handler ; 113 GPIO2_9 Handler
+ DCD GPIO2_10_Handler ; 114 GPIO2_10 Handler
+ DCD GPIO2_11_Handler ; 115 GPIO2_11 Handler
+ DCD GPIO2_12_Handler ; 116 GPIO2_12 Handler
+ DCD GPIO2_13_Handler ; 117 GPIO2_13 Handler
+ DCD GPIO2_14_Handler ; 118 GPIO2_14 Handler
+ DCD GPIO2_15_Handler ; 119 GPIO2_15 Handler
+ DCD GPIO3_0_Handler ; 120 GPIO2_16 Handler
+ DCD GPIO3_1_Handler ; 121 GPIO3_0 Handler
+ DCD GPIO3_2_Handler ; 122 GPIO3_1 Handler
+ DCD GPIO3_3_Handler ; 123 GPIO3_3 Handler
+ DCD UARTRX5_Handler ; 124 UART 5 RX Handler
+ DCD UARTTX5_Handler ; 125 UART 5 TX Handler
+ DCD UART5_Handler ; 126 UART 5 combined Handler
+ DCD HDLCD_Handler ; 127 HDCLCD interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler \
+ PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT __main
+ MRS R0, control ; Get control value
+ ORR R0, R0, #1 ; Select switch to unprivilage mode
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler \
+ PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+
+HardFault_Handler \
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+MemManage_Handler \
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+
+BusFault_Handler \
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+
+UsageFault_Handler \
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler \
+ PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+
+DebugMon_Handler \
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+
+PendSV_Handler \
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+
+SysTick_Handler \
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler \
+ PROC
+ ; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; 0 Non-Secure Watchdog
+ ; Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; 5 Dual Timer Handler
+ EXPORT MHU0_Handler [WEAK] ; 6 Message Handling Unit 0
+ EXPORT MHU1_Handler [WEAK] ; 7 Message Handling Unit 1
+ EXPORT INVALID_INSTR_CACHE_Handler [WEAK] ; 13 CPU Instruction Cache
+ ; Invalidation Handler
+ EXPORT SYS_PPU_Handler [WEAK] ; 15 SYS PPU Handler
+ EXPORT CPU0_PPU_Handler [WEAK] ; 16 CPU0 PPU Handler
+ EXPORT CPU1_PPU_Handler [WEAK] ; 17 CPU1 PPU Handler
+ EXPORT CPU0_DBG_PPU_Handler [WEAK] ; 18 CPU0 DBG PPU_Handler
+ EXPORT CPU1_DBG_PPU_Handler [WEAK] ; 19 CPU1 DBG PPU_Handler
+ EXPORT CRYPT_PPU_Handler [WEAK] ; 20 CRYPT PPU Handler
+ EXPORT CORDIO_PPU_Handler [WEAK] ; 21 CORDIO PPU Handler
+ EXPORT RAM0_PPU_Handler [WEAK] ; 22 RAM0 PPU Handler
+ EXPORT RAM1_PPU_Handler [WEAK] ; 23 RAM1 PPU Handler
+ EXPORT RAM2_PPU_Handler [WEAK] ; 24 RAM2 PPU Handler
+ EXPORT RAM3_PPU_Handler [WEAK] ; 25 RAM3 PPU Handler
+ EXPORT CPU0_CTI_Handler [WEAK] ; 28 CPU0 CTI Handler
+ EXPORT CPU1_CTI_Handler [WEAK] ; 29 CPU1 CTI Handler
+ ; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+ EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
+ EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
+ EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
+ EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
+ EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
+ EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
+ EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
+ EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
+ EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
+ EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
+ EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
+ EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
+ EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
+ EXPORT UARTOVF_Handler [WEAK] ; 47 UART Overflow Handler
+ EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
+ EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
+ EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
+ EXPORT SPI0_Handler [WEAK] ; 52 SPI ADC Handler
+ EXPORT SPI1_Handler [WEAK] ; 53 SPI (Shield 0) Handler
+ EXPORT SPI2_Handler [WEAK] ; 54 SPI (Shield 1) Handler
+ EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
+ EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
+ EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
+ EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
+ EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO0_0 Handlers
+ EXPORT GPIO0_1_Handler [WEAK] ; 73 GPIO0_1 Handler
+ EXPORT GPIO0_2_Handler [WEAK] ; 74 GPIO0_2 Handler
+ EXPORT GPIO0_3_Handler [WEAK] ; 75 GPIO0_3 Handler
+ EXPORT GPIO0_4_Handler [WEAK] ; 76 GPIO0_4 Handler
+ EXPORT GPIO0_5_Handler [WEAK] ; 77 GPIO0_5 Handler
+ EXPORT GPIO0_6_Handler [WEAK] ; 78 GPIO0_6 Handler
+ EXPORT GPIO0_7_Handler [WEAK] ; 79 GPIO0_7 Handler
+ EXPORT GPIO0_8_Handler [WEAK] ; 80 GPIO0_8 Handler
+ EXPORT GPIO0_9_Handler [WEAK] ; 81 GPIO0_9 Handler
+ EXPORT GPIO0_10_Handler [WEAK] ; 82 GPIO0_10 Handler
+ EXPORT GPIO0_11_Handler [WEAK] ; 83 GPIO0_11 Handler
+ EXPORT GPIO0_12_Handler [WEAK] ; 84 GPIO0_12 Handler
+ EXPORT GPIO0_13_Handler [WEAK] ; 85 GPIO0_13 Handler
+ EXPORT GPIO0_14_Handler [WEAK] ; 86 GPIO0_14 Handler
+ EXPORT GPIO0_15_Handler [WEAK] ; 87 GPIO0_15 Handler
+ EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO1_0 Handler
+ EXPORT GPIO1_1_Handler [WEAK] ; 89 GPIO1_1 Handler
+ EXPORT GPIO1_2_Handler [WEAK] ; 90 GPIO1_2 Handler
+ EXPORT GPIO1_3_Handler [WEAK] ; 91 GPIO1_3 Handler
+ EXPORT GPIO1_4_Handler [WEAK] ; 92 GPIO1_4 Handler
+ EXPORT GPIO1_5_Handler [WEAK] ; 93 GPIO1_5 Handler
+ EXPORT GPIO1_6_Handler [WEAK] ; 94 GPIO1_6 Handler
+ EXPORT GPIO1_7_Handler [WEAK] ; 95 GPIO1_7 Handler
+ EXPORT GPIO1_8_Handler [WEAK] ; 96 GPIO1_8 Handler
+ EXPORT GPIO1_9_Handler [WEAK] ; 97 GPIO1_9 Handler
+ EXPORT GPIO1_10_Handler [WEAK] ; 98 GPIO1_10 Handler
+ EXPORT GPIO1_11_Handler [WEAK] ; 99 GPIO1_11 Handler
+ EXPORT GPIO1_12_Handler [WEAK] ; 100 GPIO1_12 Handler
+ EXPORT GPIO1_13_Handler [WEAK] ; 101 GPIO1_13 Handler
+ EXPORT GPIO1_14_Handler [WEAK] ; 102 GPIO1_14 Handler
+ EXPORT GPIO1_15_Handler [WEAK] ; 103 GPIO1_15 Handler
+ EXPORT GPIO2_0_Handler [WEAK] ; 104 GPIO2_0 Handler
+ EXPORT GPIO2_1_Handler [WEAK] ; 105 GPIO2_1 Handler
+ EXPORT GPIO2_2_Handler [WEAK] ; 106 GPIO2_2 Handler
+ EXPORT GPIO2_3_Handler [WEAK] ; 107 GPIO2_3 Handler
+ EXPORT GPIO2_4_Handler [WEAK] ; 108 GPIO2_4 Handler
+ EXPORT GPIO2_5_Handler [WEAK] ; 109 GPIO2_5 Handler
+ EXPORT GPIO2_6_Handler [WEAK] ; 110 GPIO2_6 Handler
+ EXPORT GPIO2_7_Handler [WEAK] ; 111 GPIO2_7 Handler
+ EXPORT GPIO2_8_Handler [WEAK] ; 112 GPIO2_8 Handler
+ EXPORT GPIO2_9_Handler [WEAK] ; 113 GPIO2_9 Handler
+ EXPORT GPIO2_10_Handler [WEAK] ; 114 GPIO2_10 Handler
+ EXPORT GPIO2_11_Handler [WEAK] ; 115 GPIO2_11 Handler
+ EXPORT GPIO2_12_Handler [WEAK] ; 116 GPIO2_12 Handler
+ EXPORT GPIO2_13_Handler [WEAK] ; 117 GPIO2_13 Handler
+ EXPORT GPIO2_14_Handler [WEAK] ; 118 GPIO2_14 Handler
+ EXPORT GPIO2_15_Handler [WEAK] ; 119 GPIO2_15 Handler
+ EXPORT GPIO3_0_Handler [WEAK] ; 120 GPIO3_0 Handler
+ EXPORT GPIO3_1_Handler [WEAK] ; 121 GPIO3_1 Handler
+ EXPORT GPIO3_2_Handler [WEAK] ; 122 GPIO3_2 Handler
+ EXPORT GPIO3_3_Handler [WEAK] ; 123 GPIO3_3 Handler
+ EXPORT UARTRX5_Handler [WEAK] ; 124 UART 5 RX Handler
+ EXPORT UARTTX5_Handler [WEAK] ; 125 UART 5 TX Handler
+ EXPORT UART5_Handler [WEAK] ; 126 UART 5 combined Handler
+ EXPORT HDLCD_Handler [WEAK] ; 127 HDCLCD interrupt
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; 2 S32K Timer Handler
+TIMER0_Handler ; 3 TIMER 0 Handler
+TIMER1_Handler ; 4 TIMER 1 Handler
+DUALTIMER_Handler ; 5 Dual Timer Handler
+MHU0_Handler ; 6 Message Handling Unit 0
+MHU1_Handler ; 7 Message Handling Unit 1
+INVALID_INSTR_CACHE_Handler ; 13 CPU Instruction Cache Invalidation Handler
+SYS_PPU_Handler ; 15 SYS PPU Handler
+CPU0_PPU_Handler ; 16 CPU0 PPU Handler
+CPU1_PPU_Handler ; 17 CPU1 PPU Handler
+CPU0_DBG_PPU_Handler ; 18 CPU0 DBG PPU_Handler
+CPU1_DBG_PPU_Handler ; 19 CPU1 DBG PPU_Handler
+CRYPT_PPU_Handler ; 20 CRYPT PPU Handler
+CORDIO_PPU_Handler ; 21 CORDIO PPU Handler
+RAM0_PPU_Handler ; 22 RAM0 PPU Handler
+RAM1_PPU_Handler ; 23 RAM1 PPU Handler
+RAM2_PPU_Handler ; 24 RAM2 PPU Handler
+RAM3_PPU_Handler ; 25 RAM3 PPU Handler
+CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 52 SPI ADC Handler
+SPI1_Handler ; 53 SPI (Shield 0) Handler
+SPI2_Handler ; 54 SPI (Shield 1) Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO0_0 Handler
+GPIO0_1_Handler ; 73 GPIO0_1 Handler
+GPIO0_2_Handler ; 74 GPIO0_2 Handler
+GPIO0_3_Handler ; 75 GPIO0_3 Handler
+GPIO0_4_Handler ; 76 GPIO0_4 Handler
+GPIO0_5_Handler ; 77 GPIO0_5 Handler
+GPIO0_6_Handler ; 78 GPIO0_6 Handler
+GPIO0_7_Handler ; 79 GPIO0_7 Handler
+GPIO0_8_Handler ; 80 GPIO0_8 Handler
+GPIO0_9_Handler ; 81 GPIO0_9 Handler
+GPIO0_10_Handler ; 82 GPIO0_10 Handler
+GPIO0_11_Handler ; 83 GPIO0_11 Handler
+GPIO0_12_Handler ; 84 GPIO0_12 Handler
+GPIO0_13_Handler ; 85 GPIO0_13 Handler
+GPIO0_14_Handler ; 86 GPIO0_14 Handler
+GPIO0_15_Handler ; 87 GPIO0_15 Handler
+GPIO1_0_Handler ; 88 GPIO1_0 Handler
+GPIO1_1_Handler ; 89 GPIO1_1 Handler
+GPIO1_2_Handler ; 90 GPIO1_2 Handler
+GPIO1_3_Handler ; 91 GPIO1_3 Handler
+GPIO1_4_Handler ; 92 GPIO1_4 Handler
+GPIO1_5_Handler ; 93 GPIO1_5 Handler
+GPIO1_6_Handler ; 94 GPIO1_6 Handler
+GPIO1_7_Handler ; 95 GPIO1_7 Handler
+GPIO1_8_Handler ; 96 GPIO1_8 Handler
+GPIO1_9_Handler ; 97 GPIO1_9 Handler
+GPIO1_10_Handler ; 98 GPIO1_10 Handler
+GPIO1_11_Handler ; 99 GPIO1_11 Handler
+GPIO1_12_Handler ; 100 GPIO1_12 Handler
+GPIO1_13_Handler ; 101 GPIO1_13 Handler
+GPIO1_14_Handler ; 102 GPIO1_14 Handler
+GPIO1_15_Handler ; 103 GPIO1_15 Handler
+GPIO2_0_Handler ; 104 GPIO2_0 Handler
+GPIO2_1_Handler ; 105 GPIO2_1 Handler
+GPIO2_2_Handler ; 106 GPIO2_2 Handler
+GPIO2_3_Handler ; 107 GPIO2_3 Handler
+GPIO2_4_Handler ; 108 GPIO2_4 Handler
+GPIO2_5_Handler ; 109 GPIO2_5 Handler
+GPIO2_6_Handler ; 110 GPIO2_6 Handler
+GPIO2_7_Handler ; 111 GPIO2_7 Handler
+GPIO2_8_Handler ; 112 GPIO2_8 Handler
+GPIO2_9_Handler ; 113 GPIO2_9 Handler
+GPIO2_10_Handler ; 114 GPIO2_10 Handler
+GPIO2_11_Handler ; 115 GPIO2_11 Handler
+GPIO2_12_Handler ; 116 GPIO2_12 Handler
+GPIO2_13_Handler ; 117 GPIO2_13 Handler
+GPIO2_14_Handler ; 118 GPIO2_14 Handler
+GPIO2_15_Handler ; 119 GPIO2_15 Handler
+GPIO3_0_Handler ; 120 GPIO3_0 Handler
+GPIO3_1_Handler ; 121 GPIO2_1 Handler
+GPIO3_2_Handler ; 122 GPIO2_2 Handler
+GPIO3_3_Handler ; 123 GPIO2_3 Handler
+UARTRX5_Handler ; 124 UART 5 RX Handler
+UARTTX5_Handler ; 125 UART 5 TX Handler
+UART5_Handler ; 125 UART 5 combined Handler
+HDLCD_Handler ; 127 HDCLCD interrupt Handler
+ B .
+
+ ENDP
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s b/platform/ext/target/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s
new file mode 100644
index 0000000..84d4d9d
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/armclang/startup_cmsdk_mps3_an524_s.s
@@ -0,0 +1,518 @@
+;/*
+; * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+;
+; This file is derivative of CMSIS V5.00 startup_ARMv8MML.s
+
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Process Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+ IMPORT |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit|
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors
+ DCD |Image$$ARM_LIB_STACK_MSP$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD SecureFault_Handler ; Secure Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; Core IoT Interrupts
+ DCD NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+ DCD NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+ DCD S32K_TIMER_Handler ; 2 S32K Timer Handler
+ DCD TIMER0_Handler ; 3 TIMER 0 Handler
+ DCD TIMER1_Handler ; 4 TIMER 1 Handler
+ DCD DUALTIMER_Handler ; 5 Dual Timer Handler
+ DCD 0 ; 6 Reserved
+ DCD 0 ; 7 Reserved
+ DCD 0 ; 8 Reserved
+ DCD MPC_Handler ; 9 MPC Combined (Secure) Handler
+ DCD PPC_Handler ; 10 PPC Combined (Secure) Handler
+ DCD MSC_Handler ; 11 MSC Combined (Secure) Handler
+ DCD BRIDGE_ERROR_Handler ; 12 Bridge Error Combined (Secure)
+ ; Handler
+ DCD 0 ; 13 Reserved
+ DCD 0 ; 14 Reserved
+ DCD 0 ; 15 Reserved
+ DCD 0 ; 16 Reserved
+ DCD 0 ; 17 Reserved
+ DCD 0 ; 18 Reserved
+ DCD 0 ; 19 Reserved
+ DCD 0 ; 20 Reserved
+ DCD 0 ; 21 Reserved
+ DCD 0 ; 22 Reserved
+ DCD 0 ; 23 Reserved
+ DCD 0 ; 24 Reserved
+ DCD 0 ; 25 Reserved
+ DCD 0 ; 26 Reserved
+ DCD 0 ; 27 Reserved
+ DCD CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+ DCD CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+ DCD 0 ; 30 Reserved
+ DCD 0 ; 31 Reserved
+ ; External Interrupts
+ DCD UARTRX0_Handler ; 32 UART 0 RX Handler
+ DCD UARTTX0_Handler ; 33 UART 0 TX Handler
+ DCD UARTRX1_Handler ; 34 UART 1 RX Handler
+ DCD UARTTX1_Handler ; 35 UART 1 TX Handler
+ DCD UARTRX2_Handler ; 36 UART 2 RX Handler
+ DCD UARTTX2_Handler ; 37 UART 2 TX Handler
+ DCD UARTRX3_Handler ; 38 UART 3 RX Handler
+ DCD UARTTX3_Handler ; 39 UART 3 TX Handler
+ DCD UARTRX4_Handler ; 40 UART 4 RX Handler
+ DCD UARTTX4_Handler ; 41 UART 4 TX Handler
+ DCD UART0_Handler ; 42 UART 0 combined Handler
+ DCD UART1_Handler ; 43 UART 1 combined Handler
+ DCD UART2_Handler ; 44 UART 2 combined Handler
+ DCD UART3_Handler ; 45 UART 3 combined Handler
+ DCD UART4_Handler ; 46 UART 4 combined Handler
+ DCD UARTOVF_Handler ; 47 UART Overflow Handler
+ DCD ETHERNET_Handler ; 48 Ethernet Handler
+ DCD I2S_Handler ; 49 I2S Handler
+ DCD TSC_Handler ; 50 Touch Screen Handler
+ DCD 0 ; 51 Reserved
+ DCD SPI0_Handler ; 52 SPI ADC Handler
+ DCD SPI1_Handler ; 53 SPI (Shield 0) Handler
+ DCD SPI2_Handler ; 54 SPI (Shield 1) Handler
+ DCD 0 ; 55 Reserved
+ DCD 0 ; 56 Reserved
+ DCD 0 ; 57 Reserved
+ DCD 0 ; 58 Reserved
+ DCD 0 ; 59 Reserved
+ DCD 0 ; 60 Reserved
+ DCD 0 ; 61 Reserved
+ DCD 0 ; 62 Reserved
+ DCD 0 ; 63 Reserved
+ DCD 0 ; 64 Reserved
+ DCD 0 ; 65 Reserved
+ DCD 0 ; 66 Reserved
+ DCD 0 ; 67 Reserved
+ DCD GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+ DCD GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+ DCD GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+ DCD GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+ DCD GPIO0_0_Handler ; 72 GPIO0_0 Handler
+ DCD GPIO0_1_Handler ; 73 GPIO0_1 Handler
+ DCD GPIO0_2_Handler ; 74 GPIO0_2 Handler
+ DCD GPIO0_3_Handler ; 75 GPIO0_3 Handler
+ DCD GPIO0_4_Handler ; 76 GPIO0_4 Handler
+ DCD GPIO0_5_Handler ; 77 GPIO0_5 Handler
+ DCD GPIO0_6_Handler ; 78 GPIO0_6 Handler
+ DCD GPIO0_7_Handler ; 79 GPIO0_7 Handler
+ DCD GPIO0_8_Handler ; 80 GPIO0_8 Handler
+ DCD GPIO0_9_Handler ; 81 GPIO0_9 Handler
+ DCD GPIO0_10_Handler ; 82 GPIO0_10 Handler
+ DCD GPIO0_11_Handler ; 83 GPIO0_11 Handler
+ DCD GPIO0_12_Handler ; 84 GPIO0_12 Handler
+ DCD GPIO0_13_Handler ; 85 GPIO0_13 Handler
+ DCD GPIO0_14_Handler ; 86 GPIO0_14 Handler
+ DCD GPIO0_15_Handler ; 87 GPIO0_15 Handler
+ DCD GPIO1_0_Handler ; 88 GPIO1_0 Handler
+ DCD GPIO1_1_Handler ; 89 GPIO1_1 Handler
+ DCD GPIO1_2_Handler ; 90 GPIO1_2 Handler
+ DCD GPIO1_3_Handler ; 91 GPIO1_3 Handler
+ DCD GPIO1_4_Handler ; 92 GPIO1_4 Handler
+ DCD GPIO1_5_Handler ; 93 GPIO1_5 Handler
+ DCD GPIO1_6_Handler ; 94 GPIO1_6 Handler
+ DCD GPIO1_7_Handler ; 95 GPIO1_7 Handler
+ DCD GPIO1_8_Handler ; 96 GPIO1_8 Handler
+ DCD GPIO1_9_Handler ; 97 GPIO1_0 Handler
+ DCD GPIO1_10_Handler ; 98 GPIO1_10 Handler
+ DCD GPIO1_11_Handler ; 99 GPIO1_11 Handler
+ DCD GPIO1_12_Handler ; 100 GPIO1_12 Handler
+ DCD GPIO1_13_Handler ; 101 GPIO1_13 Handler
+ DCD GPIO1_14_Handler ; 102 GPIO1_14 Handler
+ DCD GPIO1_15_Handler ; 103 GPIO1_15 Handler
+ DCD GPIO2_0_Handler ; 104 GPIO2_0 Handler
+ DCD GPIO2_1_Handler ; 105 GPIO2_1 Handler
+ DCD GPIO2_2_Handler ; 106 GPIO2_2 Handler
+ DCD GPIO2_3_Handler ; 107 GPIO2_3 Handler
+ DCD GPIO2_4_Handler ; 108 GPIO2_4 Handler
+ DCD GPIO2_5_Handler ; 109 GPIO2_5 Handler
+ DCD GPIO2_6_Handler ; 110 GPIO2_6 Handler
+ DCD GPIO2_7_Handler ; 111 GPIO2_7 Handler
+ DCD GPIO2_8_Handler ; 112 GPIO2_8 Handler
+ DCD GPIO2_9_Handler ; 113 GPIO2_9 Handler
+ DCD GPIO2_10_Handler ; 114 GPIO2_10 Handler
+ DCD GPIO2_11_Handler ; 115 GPIO2_11 Handler
+ DCD GPIO2_12_Handler ; 116 GPIO2_12 Handler
+ DCD GPIO2_13_Handler ; 117 GPIO2_13 Handler
+ DCD GPIO2_14_Handler ; 118 GPIO2_14 Handler
+ DCD GPIO2_15_Handler ; 119 GPIO2_15 Handler
+ DCD GPIO3_0_Handler ; 120 GPIO2_16 Handler
+ DCD GPIO3_1_Handler ; 121 GPIO3_0 Handler
+ DCD GPIO3_2_Handler ; 122 GPIO3_1 Handler
+ DCD GPIO3_3_Handler ; 123 GPIO3_3 Handler
+ DCD UARTRX5_Handler ; 124 UART 5 RX Handler
+ DCD UARTTX5_Handler ; 125 UART 5 TX Handler
+ DCD UART5_Handler ; 126 UART 5 combined Handler
+ DCD HDLCD_Handler ; 127 HDCLCD interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler \
+ PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ CPSID i ; Disable IRQs
+ LDR R0, =SystemInit
+ BLX R0
+ MRS R0, control ; Get control value
+ ORR R0, R0, #2 ; Select switch to PSP
+ MSR control, R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler \
+ PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+
+HardFault_Handler \
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+
+MemManage_Handler \
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+
+BusFault_Handler \
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+
+UsageFault_Handler \
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+
+SecureFault_Handler \
+ PROC
+ EXPORT SecureFault_Handler [WEAK]
+ B .
+ ENDP
+
+SVC_Handler \
+ PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+
+DebugMon_Handler \
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+
+PendSV_Handler \
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+
+SysTick_Handler \
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+MPC_Handler \
+ PROC
+ EXPORT MPC_Handler [WEAK]
+ B .
+ ENDP
+
+PPC_Handler \
+ PROC
+ EXPORT PPC_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler \
+ PROC
+ ; Core IoT Interrupts
+ EXPORT NONSEC_WATCHDOG_RESET_Handler [WEAK] ; 0 Non-Secure Watchdog
+ ; Reset Handler
+ EXPORT NONSEC_WATCHDOG_Handler [WEAK] ; 1 Non-Secure Watchdog Handler
+ EXPORT S32K_TIMER_Handler [WEAK] ; 2 S32K Timer Handler
+ EXPORT TIMER0_Handler [WEAK] ; 3 TIMER 0 Handler
+ EXPORT TIMER1_Handler [WEAK] ; 4 TIMER 1 Handler
+ EXPORT DUALTIMER_Handler [WEAK] ; 5 Dual Timer Handler
+ EXPORT MHU0_Handler [WEAK] ; 6 Message Handling Unit 0
+ EXPORT MHU1_Handler [WEAK] ; 7 Message Handling Unit 1
+ EXPORT MPC_Handler [WEAK] ; 9 MPC Combined (Secure)
+ ; Handler
+ EXPORT PPC_Handler [WEAK] ; 10 PPC Combined (Secure)
+ ; Handler
+ EXPORT MSC_Handler [WEAK] ; 11 MSC Combined (Secure)
+ ; Handler
+ EXPORT BRIDGE_ERROR_Handler [WEAK] ; 12 Bridge Error Combined
+ ; (Secure) Handler
+ EXPORT INVALID_INSTR_CACHE_Handler [WEAK] ; 13 CPU Instruction Cache
+ ; Invalidation Handler
+ EXPORT SYS_PPU_Handler [WEAK] ; 15 SYS PPU Handler
+ EXPORT CPU0_PPU_Handler [WEAK] ; 16 CPU0 PPU Handler
+ EXPORT CPU1_PPU_Handler [WEAK] ; 17 CPU1 PPU Handler
+ EXPORT CPU0_DBG_PPU_Handler [WEAK] ; 18 CPU0 DBG PPU_Handler
+ EXPORT CPU1_DBG_PPU_Handler [WEAK] ; 19 CPU1 DBG PPU_Handler
+ EXPORT CRYPT_PPU_Handler [WEAK] ; 20 CRYPT PPU Handler
+ EXPORT CORDIO_PPU_Handler [WEAK] ; 21 CORDIO PPU Handler
+ EXPORT RAM0_PPU_Handler [WEAK] ; 22 RAM0 PPU Handler
+ EXPORT RAM1_PPU_Handler [WEAK] ; 23 RAM1 PPU Handler
+ EXPORT RAM2_PPU_Handler [WEAK] ; 24 RAM2 PPU Handler
+ EXPORT RAM3_PPU_Handler [WEAK] ; 25 RAM3 PPU Handler
+ EXPORT CPU0_CTI_Handler [WEAK] ; 28 CPU0 CTI Handler
+ EXPORT CPU1_CTI_Handler [WEAK] ; 29 CPU1 CTI Handler
+ ; External Interrupts
+ EXPORT UARTRX0_Handler [WEAK] ; 32 UART 0 RX Handler
+ EXPORT UARTTX0_Handler [WEAK] ; 33 UART 0 TX Handler
+ EXPORT UARTRX1_Handler [WEAK] ; 34 UART 1 RX Handler
+ EXPORT UARTTX1_Handler [WEAK] ; 35 UART 1 TX Handler
+ EXPORT UARTRX2_Handler [WEAK] ; 36 UART 2 RX Handler
+ EXPORT UARTTX2_Handler [WEAK] ; 37 UART 2 TX Handler
+ EXPORT UARTRX3_Handler [WEAK] ; 38 UART 3 RX Handler
+ EXPORT UARTTX3_Handler [WEAK] ; 39 UART 3 TX Handler
+ EXPORT UARTRX4_Handler [WEAK] ; 40 UART 4 RX Handler
+ EXPORT UARTTX4_Handler [WEAK] ; 41 UART 4 TX Handler
+ EXPORT UART0_Handler [WEAK] ; 42 UART 0 combined Handler
+ EXPORT UART1_Handler [WEAK] ; 43 UART 1 combined Handler
+ EXPORT UART2_Handler [WEAK] ; 44 UART 2 combined Handler
+ EXPORT UART3_Handler [WEAK] ; 45 UART 3 combined Handler
+ EXPORT UART4_Handler [WEAK] ; 46 UART 4 combined Handler
+ EXPORT UARTOVF_Handler [WEAK] ; 47 UART Overflow Handler
+ EXPORT ETHERNET_Handler [WEAK] ; 48 Ethernet Handler
+ EXPORT I2S_Handler [WEAK] ; 49 I2S Handler
+ EXPORT TSC_Handler [WEAK] ; 50 Touch Screen Handler
+ EXPORT SPI0_Handler [WEAK] ; 52 SPI ADC Handler
+ EXPORT SPI1_Handler [WEAK] ; 53 SPI (Shield 0) Handler
+ EXPORT SPI2_Handler [WEAK] ; 54 SPI (Shield 1) Handler
+ EXPORT GPIO0_Handler [WEAK] ; 68 GPIO 0 Comboned Handler
+ EXPORT GPIO1_Handler [WEAK] ; 69 GPIO 1 Comboned Handler
+ EXPORT GPIO2_Handler [WEAK] ; 70 GPIO 2 Comboned Handler
+ EXPORT GPIO3_Handler [WEAK] ; 71 GPIO 3 Comboned Handler
+ EXPORT GPIO0_0_Handler [WEAK] ; 72 GPIO0_0 Handlers
+ EXPORT GPIO0_1_Handler [WEAK] ; 73 GPIO0_1 Handler
+ EXPORT GPIO0_2_Handler [WEAK] ; 74 GPIO0_2 Handler
+ EXPORT GPIO0_3_Handler [WEAK] ; 75 GPIO0_3 Handler
+ EXPORT GPIO0_4_Handler [WEAK] ; 76 GPIO0_4 Handler
+ EXPORT GPIO0_5_Handler [WEAK] ; 77 GPIO0_5 Handler
+ EXPORT GPIO0_6_Handler [WEAK] ; 78 GPIO0_6 Handler
+ EXPORT GPIO0_7_Handler [WEAK] ; 79 GPIO0_7 Handler
+ EXPORT GPIO0_8_Handler [WEAK] ; 80 GPIO0_8 Handler
+ EXPORT GPIO0_9_Handler [WEAK] ; 81 GPIO0_9 Handler
+ EXPORT GPIO0_10_Handler [WEAK] ; 82 GPIO0_10 Handler
+ EXPORT GPIO0_11_Handler [WEAK] ; 83 GPIO0_11 Handler
+ EXPORT GPIO0_12_Handler [WEAK] ; 84 GPIO0_12 Handler
+ EXPORT GPIO0_13_Handler [WEAK] ; 85 GPIO0_13 Handler
+ EXPORT GPIO0_14_Handler [WEAK] ; 86 GPIO0_14 Handler
+ EXPORT GPIO0_15_Handler [WEAK] ; 87 GPIO0_15 Handler
+ EXPORT GPIO1_0_Handler [WEAK] ; 88 GPIO1_0 Handler
+ EXPORT GPIO1_1_Handler [WEAK] ; 89 GPIO1_1 Handler
+ EXPORT GPIO1_2_Handler [WEAK] ; 90 GPIO1_2 Handler
+ EXPORT GPIO1_3_Handler [WEAK] ; 91 GPIO1_3 Handler
+ EXPORT GPIO1_4_Handler [WEAK] ; 92 GPIO1_4 Handler
+ EXPORT GPIO1_5_Handler [WEAK] ; 93 GPIO1_5 Handler
+ EXPORT GPIO1_6_Handler [WEAK] ; 94 GPIO1_6 Handler
+ EXPORT GPIO1_7_Handler [WEAK] ; 95 GPIO1_7 Handler
+ EXPORT GPIO1_8_Handler [WEAK] ; 96 GPIO1_8 Handler
+ EXPORT GPIO1_9_Handler [WEAK] ; 97 GPIO1_9 Handler
+ EXPORT GPIO1_10_Handler [WEAK] ; 98 GPIO1_10 Handler
+ EXPORT GPIO1_11_Handler [WEAK] ; 99 GPIO1_11 Handler
+ EXPORT GPIO1_12_Handler [WEAK] ; 100 GPIO1_12 Handler
+ EXPORT GPIO1_13_Handler [WEAK] ; 101 GPIO1_13 Handler
+ EXPORT GPIO1_14_Handler [WEAK] ; 102 GPIO1_14 Handler
+ EXPORT GPIO1_15_Handler [WEAK] ; 103 GPIO1_15 Handler
+ EXPORT GPIO2_0_Handler [WEAK] ; 104 GPIO2_0 Handler
+ EXPORT GPIO2_1_Handler [WEAK] ; 105 GPIO2_1 Handler
+ EXPORT GPIO2_2_Handler [WEAK] ; 106 GPIO2_2 Handler
+ EXPORT GPIO2_3_Handler [WEAK] ; 107 GPIO2_3 Handler
+ EXPORT GPIO2_4_Handler [WEAK] ; 108 GPIO2_4 Handler
+ EXPORT GPIO2_5_Handler [WEAK] ; 109 GPIO2_5 Handler
+ EXPORT GPIO2_6_Handler [WEAK] ; 110 GPIO2_6 Handler
+ EXPORT GPIO2_7_Handler [WEAK] ; 111 GPIO2_7 Handler
+ EXPORT GPIO2_8_Handler [WEAK] ; 112 GPIO2_8 Handler
+ EXPORT GPIO2_9_Handler [WEAK] ; 113 GPIO2_9 Handler
+ EXPORT GPIO2_10_Handler [WEAK] ; 114 GPIO2_10 Handler
+ EXPORT GPIO2_11_Handler [WEAK] ; 115 GPIO2_11 Handler
+ EXPORT GPIO2_12_Handler [WEAK] ; 116 GPIO2_12 Handler
+ EXPORT GPIO2_13_Handler [WEAK] ; 117 GPIO2_13 Handler
+ EXPORT GPIO2_14_Handler [WEAK] ; 118 GPIO2_14 Handler
+ EXPORT GPIO2_15_Handler [WEAK] ; 119 GPIO2_15 Handler
+ EXPORT GPIO3_0_Handler [WEAK] ; 120 GPIO3_0 Handler
+ EXPORT GPIO3_1_Handler [WEAK] ; 121 GPIO3_1 Handler
+ EXPORT GPIO3_2_Handler [WEAK] ; 122 GPIO3_2 Handler
+ EXPORT GPIO3_3_Handler [WEAK] ; 123 GPIO3_3 Handler
+ EXPORT UARTRX5_Handler [WEAK] ; 124 UART 5 RX Handler
+ EXPORT UARTTX5_Handler [WEAK] ; 125 UART 5 TX Handler
+ EXPORT UART5_Handler [WEAK] ; 126 UART 5 combined Handler
+ EXPORT HDLCD_Handler [WEAK] ; 127 HDCLCD interrupt
+
+; Core IoT Interrupts
+NONSEC_WATCHDOG_RESET_Handler ; 0 Non-Secure Watchdog Reset Handler
+NONSEC_WATCHDOG_Handler ; 1 Non-Secure Watchdog Handler
+S32K_TIMER_Handler ; 2 S32K Timer Handler
+TIMER0_Handler ; 3 TIMER 0 Handler
+TIMER1_Handler ; 4 TIMER 1 Handler
+DUALTIMER_Handler ; 5 Dual Timer Handler
+MHU0_Handler ; 6 Message Handling Unit 0
+MHU1_Handler ; 7 Message Handling Unit 1
+MSC_Handler ; 11 MSC Combined (Secure) Handler
+BRIDGE_ERROR_Handler ; 12 Bridge Error Combined (Secure) Handler
+INVALID_INSTR_CACHE_Handler ; 13 CPU Instruction Cache Invalidation Handler
+SYS_PPU_Handler ; 15 SYS PPU Handler
+CPU0_PPU_Handler ; 16 CPU0 PPU Handler
+CPU1_PPU_Handler ; 17 CPU1 PPU Handler
+CPU0_DBG_PPU_Handler ; 18 CPU0 DBG PPU_Handler
+CPU1_DBG_PPU_Handler ; 19 CPU1 DBG PPU_Handler
+CRYPT_PPU_Handler ; 20 CRYPT PPU Handler
+CORDIO_PPU_Handler ; 21 CORDIO PPU Handler
+RAM0_PPU_Handler ; 22 RAM0 PPU Handler
+RAM1_PPU_Handler ; 23 RAM1 PPU Handler
+RAM2_PPU_Handler ; 24 RAM2 PPU Handler
+RAM3_PPU_Handler ; 25 RAM3 PPU Handler
+CPU0_CTI_Handler ; 28 CPU0 CTI Handler
+CPU1_CTI_Handler ; 29 CPU1 CTI Handler
+; External Interrupts
+UARTRX0_Handler ; 32 UART 0 RX Handler
+UARTTX0_Handler ; 33 UART 0 TX Handler
+UARTRX1_Handler ; 34 UART 1 RX Handler
+UARTTX1_Handler ; 35 UART 1 TX Handler
+UARTRX2_Handler ; 36 UART 2 RX Handler
+UARTTX2_Handler ; 37 UART 2 TX Handler
+UARTRX3_Handler ; 38 UART 3 RX Handler
+UARTTX3_Handler ; 39 UART 3 TX Handler
+UARTRX4_Handler ; 40 UART 4 RX Handler
+UARTTX4_Handler ; 41 UART 4 TX Handler
+UART0_Handler ; 42 UART 0 combined Handler
+UART1_Handler ; 43 UART 1 combined Handler
+UART2_Handler ; 44 UART 2 combined Handler
+UART3_Handler ; 45 UART 3 combined Handler
+UART4_Handler ; 46 UART 4 combined Handler
+UARTOVF_Handler ; 47 UART Overflow Handler
+ETHERNET_Handler ; 48 Ethernet Handler
+I2S_Handler ; 49 I2S Handler
+TSC_Handler ; 50 Touch Screen Handler
+SPI0_Handler ; 52 SPI ADC Handler
+SPI1_Handler ; 53 SPI (Shield 0) Handler
+SPI2_Handler ; 54 SPI (Shield 1) Handler
+GPIO0_Handler ; 68 GPIO 0 Comboned Handler
+GPIO1_Handler ; 69 GPIO 1 Comboned Handler
+GPIO2_Handler ; 70 GPIO 2 Comboned Handler
+GPIO3_Handler ; 71 GPIO 3 Comboned Handler
+GPIO0_0_Handler ; 72 GPIO0_0 Handler
+GPIO0_1_Handler ; 73 GPIO0_1 Handler
+GPIO0_2_Handler ; 74 GPIO0_2 Handler
+GPIO0_3_Handler ; 75 GPIO0_3 Handler
+GPIO0_4_Handler ; 76 GPIO0_4 Handler
+GPIO0_5_Handler ; 77 GPIO0_5 Handler
+GPIO0_6_Handler ; 78 GPIO0_6 Handler
+GPIO0_7_Handler ; 79 GPIO0_7 Handler
+GPIO0_8_Handler ; 80 GPIO0_8 Handler
+GPIO0_9_Handler ; 81 GPIO0_9 Handler
+GPIO0_10_Handler ; 82 GPIO0_10 Handler
+GPIO0_11_Handler ; 83 GPIO0_11 Handler
+GPIO0_12_Handler ; 84 GPIO0_12 Handler
+GPIO0_13_Handler ; 85 GPIO0_13 Handler
+GPIO0_14_Handler ; 86 GPIO0_14 Handler
+GPIO0_15_Handler ; 87 GPIO0_15 Handler
+GPIO1_0_Handler ; 88 GPIO1_0 Handler
+GPIO1_1_Handler ; 89 GPIO1_1 Handler
+GPIO1_2_Handler ; 90 GPIO1_2 Handler
+GPIO1_3_Handler ; 91 GPIO1_3 Handler
+GPIO1_4_Handler ; 92 GPIO1_4 Handler
+GPIO1_5_Handler ; 93 GPIO1_5 Handler
+GPIO1_6_Handler ; 94 GPIO1_6 Handler
+GPIO1_7_Handler ; 95 GPIO1_7 Handler
+GPIO1_8_Handler ; 96 GPIO1_8 Handler
+GPIO1_9_Handler ; 97 GPIO1_9 Handler
+GPIO1_10_Handler ; 98 GPIO1_10 Handler
+GPIO1_11_Handler ; 99 GPIO1_11 Handler
+GPIO1_12_Handler ; 100 GPIO1_12 Handler
+GPIO1_13_Handler ; 101 GPIO1_13 Handler
+GPIO1_14_Handler ; 102 GPIO1_14 Handler
+GPIO1_15_Handler ; 103 GPIO1_15 Handler
+GPIO2_0_Handler ; 104 GPIO2_0 Handler
+GPIO2_1_Handler ; 105 GPIO2_1 Handler
+GPIO2_2_Handler ; 106 GPIO2_2 Handler
+GPIO2_3_Handler ; 107 GPIO2_3 Handler
+GPIO2_4_Handler ; 108 GPIO2_4 Handler
+GPIO2_5_Handler ; 109 GPIO2_5 Handler
+GPIO2_6_Handler ; 110 GPIO2_6 Handler
+GPIO2_7_Handler ; 111 GPIO2_7 Handler
+GPIO2_8_Handler ; 112 GPIO2_8 Handler
+GPIO2_9_Handler ; 113 GPIO2_9 Handler
+GPIO2_10_Handler ; 114 GPIO2_10 Handler
+GPIO2_11_Handler ; 115 GPIO2_11 Handler
+GPIO2_12_Handler ; 116 GPIO2_12 Handler
+GPIO2_13_Handler ; 117 GPIO2_13 Handler
+GPIO2_14_Handler ; 118 GPIO2_14 Handler
+GPIO2_15_Handler ; 119 GPIO2_15 Handler
+GPIO3_0_Handler ; 120 GPIO3_0 Handler
+GPIO3_1_Handler ; 121 GPIO2_1 Handler
+GPIO3_2_Handler ; 122 GPIO2_2 Handler
+GPIO3_3_Handler ; 123 GPIO2_3 Handler
+UARTRX5_Handler ; 124 UART 5 RX Handler
+UARTTX5_Handler ; 125 UART 5 TX Handler
+UART5_Handler ; 125 UART 5 combined Handler
+HDLCD_Handler ; 127 HDCLCD interrupt Handler
+ B .
+
+ ENDP
+
+ ALIGN
+
+ END
diff --git a/platform/ext/target/mps3/an524/device/source/device_definition.c b/platform/ext/target/mps3/an524/device/source/device_definition.c
new file mode 100644
index 0000000..3f1e81e
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/device_definition.c
@@ -0,0 +1,523 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file device_definition.c
+ * \brief This file defines exports the structures based on the peripheral
+ * definitions from device_cfg.h.
+ * This file is meant to be used as a helper for baremetal
+ * applications and/or as an example of how to configure the generic
+ * driver structures.
+ */
+
+#include "device_definition.h"
+#include "platform_base_address.h"
+
+/* UART CMSDK driver structures */
+#ifdef UART0_CMSDK_S
+static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_S = {
+ .base = UART0_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART0_DEV_S = {
+ &(UART0_CMSDK_DEV_CFG_S),
+ &(UART0_CMSDK_DEV_DATA_S)
+};
+#endif
+#ifdef UART0_CMSDK_NS
+static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_NS = {
+ .base = UART0_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART0_DEV_NS = {
+ &(UART0_CMSDK_DEV_CFG_NS),
+ &(UART0_CMSDK_DEV_DATA_NS)
+};
+#endif
+
+#ifdef UART1_CMSDK_S
+static const struct uart_cmsdk_dev_cfg_t UART1_CMSDK_DEV_CFG_S = {
+ .base = UART1_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART1_DEV_S = {
+ &(UART1_CMSDK_DEV_CFG_S),
+ &(UART1_CMSDK_DEV_DATA_S)
+};
+#endif
+#ifdef UART1_CMSDK_NS
+static const struct uart_cmsdk_dev_cfg_t UART1_CMSDK_DEV_CFG_NS = {
+ .base = UART1_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART1_DEV_NS = {
+ &(UART1_CMSDK_DEV_CFG_NS),
+ &(UART1_CMSDK_DEV_DATA_NS)
+};
+#endif
+
+#ifdef UART2_CMSDK_S
+static const struct uart_cmsdk_dev_cfg_t UART2_CMSDK_DEV_CFG_S = {
+ .base = UART2_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART2_DEV_S = {
+ &(UART2_CMSDK_DEV_CFG_S),
+ &(UART2_CMSDK_DEV_DATA_S)
+};
+#endif
+#ifdef UART2_CMSDK_NS
+static const struct uart_cmsdk_dev_cfg_t UART2_CMSDK_DEV_CFG_NS = {
+ .base = UART2_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART2_DEV_NS = {
+ &(UART2_CMSDK_DEV_CFG_NS),
+ &(UART2_CMSDK_DEV_DATA_NS)
+};
+#endif
+
+#ifdef UART3_CMSDK_S
+static const struct uart_cmsdk_dev_cfg_t UART3_CMSDK_DEV_CFG_S = {
+ .base = UART3_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART3_DEV_S = {
+ &(UART3_CMSDK_DEV_CFG_S),
+ &(UART3_CMSDK_DEV_DATA_S)
+};
+#endif
+#ifdef UART3_CMSDK_NS
+static const struct uart_cmsdk_dev_cfg_t UART3_CMSDK_DEV_CFG_NS = {
+ .base = UART3_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART3_DEV_NS = {
+ &(UART3_CMSDK_DEV_CFG_NS),
+ &(UART3_CMSDK_DEV_DATA_NS)
+};
+#endif
+
+#ifdef UART4_CMSDK_S
+static const struct uart_cmsdk_dev_cfg_t UART4_CMSDK_DEV_CFG_S = {
+ .base = UART4_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART4_DEV_S = {
+ &(UART4_CMSDK_DEV_CFG_S),
+ &(UART4_CMSDK_DEV_DATA_S)
+};
+#endif
+#ifdef UART4_CMSDK_NS
+static const struct uart_cmsdk_dev_cfg_t UART4_CMSDK_DEV_CFG_NS = {
+ .base = UART4_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART4_DEV_NS = {
+ &(UART4_CMSDK_DEV_CFG_NS),
+ &(UART4_CMSDK_DEV_DATA_NS)
+};
+#endif
+
+#ifdef UART5_CMSDK_S
+static const struct uart_cmsdk_dev_cfg_t UART5_CMSDK_DEV_CFG_S = {
+ .base = UART5_BASE_S,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_S = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART5_DEV_S = {
+ &(UART5_CMSDK_DEV_CFG_S),
+ &(UART5_CMSDK_DEV_DATA_S)
+};
+#endif
+#ifdef UART5_CMSDK_NS
+static const struct uart_cmsdk_dev_cfg_t UART5_CMSDK_DEV_CFG_NS = {
+ .base = UART5_BASE_NS,
+ .default_baudrate = DEFAULT_UART_BAUDRATE
+};
+static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_NS = {
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
+};
+struct uart_cmsdk_dev_t ARM_UART5_DEV_NS = {
+ &(UART5_CMSDK_DEV_CFG_NS),
+ &(UART5_CMSDK_DEV_DATA_NS)
+};
+#endif
+
+/* ARM PPC SIE 200 driver structures */
+#ifdef AHB_PPC0_S
+static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS
+};
+static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0
+};
+struct ppc_sse200_dev_t AHB_PPC0_DEV_S = {
+ &AHB_PPC0_DEV_CFG_S,
+ &AHB_PPC0_DEV_DATA_S
+};
+#endif
+
+#ifdef AHB_PPCEXP0_S
+static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS
+};
+static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0
+};
+struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = {
+ &AHB_PPCEXP0_DEV_CFG_S,
+ &AHB_PPCEXP0_DEV_DATA_S
+};
+#endif
+
+#ifdef APB_PPC0_S
+static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS
+};
+static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0
+};
+struct ppc_sse200_dev_t APB_PPC0_DEV_S = {
+ &APB_PPC0_DEV_CFG_S,
+ &APB_PPC0_DEV_DATA_S
+};
+#endif
+
+#ifdef APB_PPC1_S
+static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS
+};
+static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0
+};
+struct ppc_sse200_dev_t APB_PPC1_DEV_S = {
+ &APB_PPC1_DEV_CFG_S,
+ &APB_PPC1_DEV_DATA_S
+};
+#endif
+
+#ifdef APB_PPCEXP0_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS
+};
+static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0
+};
+struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = {
+ &APB_PPCEXP0_DEV_CFG_S,
+ &APB_PPCEXP0_DEV_DATA_S
+};
+#endif
+
+#ifdef APB_PPCEXP1_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS
+};
+static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0
+};
+struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = {
+ &APB_PPCEXP1_DEV_CFG,
+ &APB_PPCEXP1_DEV_DATA_S
+};
+#endif
+
+#ifdef APB_PPCEXP2_S
+static struct ppc_sse200_dev_cfg_t APB_PPCEXP2_DEV_CFG = {
+ .spctrl_base = CMSDK_SPCTRL_BASE_S,
+ .nspctrl_base = CMSDK_NSPCTRL_BASE_NS
+};
+static struct ppc_sse200_dev_data_t APB_PPCEXP2_DEV_DATA_S = {
+ .p_ns_ppc = 0,
+ .p_sp_ppc = 0,
+ .p_nsp_ppc = 0,
+ .int_bit_mask = 0,
+ .state = 0
+};
+struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S = {
+ &APB_PPCEXP2_DEV_CFG,
+ &APB_PPCEXP2_DEV_DATA_S
+};
+#endif
+
+/* CMSDK Timer driver structures */
+#ifdef CMSDK_TIMER0_S
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = {
+ .base = CMSDK_TIMER0_BASE_S
+};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S = {
+ .is_initialized = 0
+};
+struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S = {
+ &(CMSDK_TIMER0_DEV_CFG_S),
+ &(CMSDK_TIMER0_DEV_DATA_S)
+};
+#endif
+#ifdef CMSDK_TIMER0_NS
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = {
+ .base = CMSDK_TIMER0_BASE_NS
+};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = {
+ .is_initialized = 0
+};
+struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = {
+ &(CMSDK_TIMER0_DEV_CFG_NS),
+ &(CMSDK_TIMER0_DEV_DATA_NS)
+};
+#endif
+
+#ifdef CMSDK_TIMER1_S
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = {
+ .base = CMSDK_TIMER1_BASE_S
+};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = {
+ .is_initialized = 0
+};
+struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = {
+ &(CMSDK_TIMER1_DEV_CFG_S),
+ &(CMSDK_TIMER1_DEV_DATA_S)
+};
+#endif
+#ifdef CMSDK_TIMER1_NS
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = {
+ .base = CMSDK_TIMER1_BASE_NS
+};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = {
+ .is_initialized = 0
+};
+struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = {
+ &(CMSDK_TIMER1_DEV_CFG_NS),
+ &(CMSDK_TIMER1_DEV_DATA_NS)
+};
+#endif
+
+/* ARM MPC SSE 200 driver structures */
+#ifdef MPC_ISRAM0_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = {
+ .base = MPC_ISRAM0_BASE_S
+};
+static struct mpc_sie200_dev_data_t MPC_ISRAM0_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0
+};
+struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S = {
+ &(MPC_ISRAM0_DEV_CFG_S),
+ &(MPC_ISRAM0_DEV_DATA_S)
+};
+#endif
+
+#ifdef MPC_ISRAM1_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = {
+ .base = MPC_ISRAM1_BASE_S
+};
+static struct mpc_sie200_dev_data_t MPC_ISRAM1_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0
+};
+struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S = {
+ &(MPC_ISRAM1_DEV_CFG_S),
+ &(MPC_ISRAM1_DEV_DATA_S)
+};
+#endif
+
+#ifdef MPC_ISRAM2_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = {
+ .base = MPC_ISRAM2_BASE_S
+};
+static struct mpc_sie200_dev_data_t MPC_ISRAM2_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0
+};
+struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S = {
+ &(MPC_ISRAM2_DEV_CFG_S),
+ &(MPC_ISRAM2_DEV_DATA_S)
+};
+#endif
+
+#ifdef MPC_ISRAM3_S
+static const struct mpc_sie200_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = {
+ .base = MPC_ISRAM3_BASE_S
+};
+static struct mpc_sie200_dev_data_t MPC_ISRAM3_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0
+};
+struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S = {
+ &(MPC_ISRAM3_DEV_CFG_S),
+ &(MPC_ISRAM3_DEV_DATA_S)
+};
+#endif
+
+#ifdef MPC_BRAM_S
+static const struct mpc_sie200_dev_cfg_t MPC_BRAM_DEV_CFG_S = {
+ .base = MPC_BRAM_BASE_S
+};
+static struct mpc_sie200_dev_data_t MPC_BRAM_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0
+};
+struct mpc_sie200_dev_t MPC_BRAM_DEV_S = {
+ &(MPC_BRAM_DEV_CFG_S),
+ &(MPC_BRAM_DEV_DATA_S)
+};
+#endif
+
+#ifdef MPC_QSPI_S
+static const struct mpc_sie200_dev_cfg_t MPC_QSPI_DEV_CFG_S = {
+ .base = MPC_QSPI_BASE_S
+};
+static struct mpc_sie200_dev_data_t MPC_QSPI_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0
+};
+struct mpc_sie200_dev_t MPC_QSPI_DEV_S = {
+ &(MPC_QSPI_DEV_CFG_S),
+ &(MPC_QSPI_DEV_DATA_S)
+};
+#endif
+
+#ifdef MPC_DDR4_S
+static const struct mpc_sie200_dev_cfg_t MPC_DDR4_DEV_CFG_S = {
+ .base = MPC_DDR4_BASE_S
+};
+static struct mpc_sie200_dev_data_t MPC_DDR4_DEV_DATA_S = {
+ .range_list = 0,
+ .nbr_of_ranges = 0,
+ .state = 0,
+ .reserved = 0
+};
+struct mpc_sie200_dev_t MPC_DDR4_DEV_S = {
+ &(MPC_DDR4_DEV_CFG_S),
+ &(MPC_DDR4_DEV_DATA_S)
+};
+#endif
+
+#ifdef MPS3_IO_S
+static struct arm_mps3_io_dev_cfg_t MPS3_IO_DEV_CFG_S = {
+ .base = MPS3_IO_FPGAIO_BASE_S
+};
+struct arm_mps3_io_dev_t MPS3_IO_DEV_S = {
+ .cfg = &(MPS3_IO_DEV_CFG_S)
+};
+#endif
+
+#ifdef MPS3_IO_NS
+static struct arm_mps3_io_dev_cfg_t MPS3_IO_DEV_CFG_NS = {
+ .base = MPS3_IO_FPGAIO_BASE_NS
+};
+struct arm_mps3_io_dev_t MPS3_IO_DEV_NS = {
+ .cfg = &(MPS3_IO_DEV_CFG_NS)
+};
+#endif
diff --git a/platform/ext/target/mps3/an524/device/source/gcc/mps3_an524_bl2.ld b/platform/ext/target/mps3/an524/device/source/gcc/mps3_an524_bl2.ld
new file mode 100644
index 0000000..06c91ae
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/gcc/mps3_an524_bl2.ld
@@ -0,0 +1,189 @@
+;/*
+; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = BL2_CODE_START, LENGTH = BL2_CODE_SIZE
+ RAM (rwx) : ORIGIN = BL2_DATA_START, LENGTH = BL2_DATA_SIZE
+}
+
+__heap_size__ = BL2_HEAP_SIZE;
+__msp_stack_size__ = BL2_MSP_STACK_SIZE;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * define etext2/data2_start/data2_end and
+ * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps3_an524_bl2.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (DEFINED(__etext2) ? __etext2 : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
+ __copy_table_end__ = .;
+ } > FLASH
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_mps3_an524_bl2.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
+ LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
+ __zero_table_end__ = .;
+ } > FLASH
+
+ __etext = .;
+
+ .tfm_bl2_shared_data : ALIGN(32)
+ {
+ . += BOOT_TFM_SHARED_DATA_SIZE;
+ } > RAM
+ Image$$SHARED_DATA$$RW$$Base = ADDR(.tfm_bl2_shared_data);
+ Image$$SHARED_DATA$$RW$$Limit = ADDR(.tfm_bl2_shared_data) + SIZEOF(.tfm_bl2_shared_data);
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ bss_size = __bss_end__ - __bss_start__;
+
+ .msp_stack : ALIGN(32)
+ {
+ . += __msp_stack_size__;
+ } > RAM
+ Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.msp_stack);
+ Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .heap : ALIGN(8)
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > RAM
+
+ PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
+}
diff --git a/platform/ext/target/mps3/an524/device/source/gcc/mps3_an524_ns.ld b/platform/ext/target/mps3/an524/device/source/gcc/mps3_an524_ns.ld
new file mode 100644
index 0000000..1b998e7
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/gcc/mps3_an524_ns.ld
@@ -0,0 +1,189 @@
+;/*
+; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+; *
+; * Licensed under the Apache License, Version 2.0 (the "License");
+; * you may not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * http://www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an "AS IS" BASIS,
+; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; *
+; *
+; * This file is derivative of CMSIS V5.00 gcc_arm.ld
+; */
+
+/* Linker script to configure memory regions. */
+/* This file will be run trough the pre-processor. */
+
+#include "region_defs.h"
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
+ RAM (rwx) : ORIGIN = NS_DATA_START, LENGTH = NS_DATA_SIZE
+}
+
+__heap_size__ = NS_HEAP_SIZE;
+__psp_stack_size__ = NS_PSP_STACK_SIZE;
+__msp_stack_size__ = NS_MSP_STACK_SIZE;
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.vectors))
+ __Vectors_End = .;
+ __Vectors_Size = __Vectors_End - __Vectors;
+ __end__ = .;
+
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * define etext2/data2_start/data2_end and
+ * define __STARTUP_COPY_MULTIPLE in startup_cmsdk_mps3_an524_ns.S */
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (DEFINED(__etext2) ? __etext2 : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
+ LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
+ __copy_table_end__ = .;
+ } > FLASH
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_mps3_an524_ns.S */
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
+ LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
+ __zero_table_end__ = .;
+ } > FLASH
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ bss_size = __bss_end__ - __bss_start__;
+
+ .msp_stack : ALIGN(32)
+ {
+ . += __msp_stack_size__;
+ } > RAM
+ Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
+
+ .psp_stack : ALIGN(32)
+ {
+ . += __psp_stack_size__;
+ } > RAM
+ Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);
+ Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
+
+ .heap : ALIGN(8)
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += __heap_size__;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > RAM
+
+ PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
+}
diff --git a/platform/ext/target/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_bl2.S b/platform/ext/target/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_bl2.S
new file mode 100644
index 0000000..93328a3
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_bl2.S
@@ -0,0 +1,455 @@
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.01 startup_ARMCM33.S
+ * Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+ */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
+
+ /* Core interrupts */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ .long TIMER0_Handler /* 3: TIMER 0 Handler */
+ .long TIMER1_Handler /* 4: TIMER 1 Handler */
+ .long DUALTIMER_Handler /* 5: Dual Timer Handler */
+ .long MHU0_Handler /* 6: Message Handling Unit 0 */
+ .long MHU1_Handler /* 7: Message Handling Unit 1 */
+ .long 0 /* 8: Reserved */
+ .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
+ .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
+ .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
+ .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
+ .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_Handler /* 15: SYS PPU Handler */
+ .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */
+ .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */
+ .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */
+ .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */
+ .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */
+ .long CORDIO_PPU_Handler /* 21: CORDIO PPU Handler */
+ .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */
+ .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */
+ .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */
+ .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */
+ .long DBG_PPU_Handler /* 26: DEBUG_PPU Handler */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+ /* External Interrupts */
+ .long UARTRX0_Handler /* 32: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 33: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 34: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 35: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 36: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 37: UART 2 TX Handler */
+ .long UARTRX3_Handler /* 38: UART 3 RX Handler */
+ .long UARTTX3_Handler /* 39: UART 3 TX Handler */
+ .long UARTRX4_Handler /* 40: UART 4 RX Handler */
+ .long UARTTX4_Handler /* 41: UART 4 TX Handler */
+ .long UART0_Handler /* 42: UART 0 combined Handler */
+ .long UART1_Handler /* 43: UART 1 combined Handler */
+ .long UART2_Handler /* 44: UART 2 combined Handler */
+ .long UART3_Handler /* 45: UART 3 combined Handler */
+ .long UART4_Handler /* 46: UART 4 combined Handler */
+ .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ .long ETHERNET_Handler /* 48: Ethernet Handler */
+ .long I2S_Handler /* 49: I2S Handler */
+ .long TSC_Handler /* 50: Touch Screen Handler */
+ .long 0 /* 51: Reserved */
+ .long SPI0_Handler /* 52: SPI ADC Handler */
+ .long SPI1_Handler /* 53: SPI (Shield 0) Handler */
+ .long SPI2_Handler /* 54: SPI (Shield 1) Handler */
+ .long 0 /* 55: Reserved */
+ .long 0 /* 56: Reserved */
+ .long 0 /* 57: Reserved */
+ .long 0 /* 58: Reserved */
+ .long 0 /* 59: Reserved */
+ .long 0 /* 50: Reserved */
+ .long 0 /* 61: Reserved */
+ .long 0 /* 62: Reserved */
+ .long 0 /* 63: Reserved */
+ .long 0 /* 64: Reserved */
+ .long 0 /* 65: Reserved */
+ .long 0 /* 66: Reserved */
+ .long 0 /* 67: Reserved */
+ .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ .long GPIO2_0_Handler /* 104: All P2 I/O pins used as irq source */
+ .long GPIO2_1_Handler /* 105 There are 15 pins in total */
+ .long GPIO2_2_Handler /* 106 */
+ .long GPIO2_3_Handler /* 107 */
+ .long GPIO2_4_Handler /* 108 */
+ .long GPIO2_5_Handler /* 109 */
+ .long GPIO2_6_Handler /* 110 */
+ .long GPIO2_7_Handler /* 111 */
+ .long GPIO2_8_Handler /* 112 */
+ .long GPIO2_9_Handler /* 113 */
+ .long GPIO2_10_Handler /* 114 */
+ .long GPIO2_11_Handler /* 115 */
+ .long GPIO2_12_Handler /* 116 */
+ .long GPIO2_13_Handler /* 117 */
+ .long GPIO2_14_Handler /* 118 */
+ .long GPIO2_15_Handler /* 119 */
+ .long GPIO3_0_Handler /* 120: All P3 I/O pins used as irq source */
+ .long GPIO3_1_Handler /* 121 There are 4 pins in total */
+ .long GPIO3_2_Handler /* 122 */
+ .long GPIO3_3_Handler /* 123 */
+ .long UARTRX5_Handler /* 124 */
+ .long UARTTX5_Handler /* 125 */
+ .long UART5_Handler /* 126 */
+ .long HDLCD_Handler /* 127 */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+ /* Only run on core 0 */
+ mov r0, #0x50000000
+ add r0, #0x0001F000
+ ldr r0, [r0]
+ cmp r0,#0
+not_the_core_to_run_on:
+ bne not_the_core_to_run_on
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ bl SystemInit
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ /* Core interrupts */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
+ def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
+ def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
+ def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */
+ def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */
+ def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
+ def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
+ def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
+ def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
+ def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */
+ def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */
+ def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */
+ def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */
+ def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */
+ def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */
+ def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */
+ def_irq_handler CORDIO_PPU_Handler /* 21 CORDIO PPU Handler */
+ def_irq_handler RAM0_PPU_Handler /* 22 RAM1 PPU Handler */
+ def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */
+ def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */
+ def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */
+ def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */
+ def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ /* External interrupts */
+ def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
+ def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
+ def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
+ def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
+ def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
+ def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
+ def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
+ def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
+ def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
+ def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
+ def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
+ def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
+ def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
+ def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
+ def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
+ def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
+ def_irq_handler I2S_Handler /* 49: I2S Handler */
+ def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
+ def_irq_handler SPI0_Handler /* 52: SPI ADC Handler */
+ def_irq_handler SPI1_Handler /* 53: SPI (Shield 0) Handler */
+ def_irq_handler SPI2_Handler /* 54: SPI (Shield 1) Handler */
+ def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
+ def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
+ def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
+ def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
+ def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
+ def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
+ def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
+ def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
+ def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
+ def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
+ def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
+ def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
+ def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
+ def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
+ def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
+ def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
+ def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_0 Handler */
+ def_irq_handler UARTRX5_Handler /* 124: */
+ def_irq_handler UARTTX5_Handler /* 125: */
+ def_irq_handler UART5_Handler /* 126: */
+ def_irq_handler HDLCD_Handler /* 127: */
+
+ .end
diff --git a/platform/ext/target/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_ns.S b/platform/ext/target/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_ns.S
new file mode 100644
index 0000000..d9e4dfe
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_ns.S
@@ -0,0 +1,451 @@
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.01 startup_ARMCM33.S
+ * Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+ */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+
+ /* Core interrupts */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ .long TIMER0_Handler /* 3: TIMER 0 Handler */
+ .long TIMER1_Handler /* 4: TIMER 1 Handler */
+ .long DUALTIMER_Handler /* 5: Dual Timer Handler */
+ .long MHU0_Handler /* 6: Message Handling Unit 0 */
+ .long MHU1_Handler /* 7: Message Handling Unit 1 */
+ .long 0 /* 8: Reserved */
+ .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
+ .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
+ .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
+ .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
+ .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_Handler /* 15: SYS PPU Handler */
+ .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */
+ .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */
+ .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */
+ .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */
+ .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */
+ .long CORDIO_PPU_Handler /* 21: CORDIO PPU Handler */
+ .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */
+ .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */
+ .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */
+ .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */
+ .long DBG_PPU_Handler /* 26: DEBUG_PPU Handler */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+ /* External Interrupts */
+ .long UARTRX0_Handler /* 32: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 33: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 34: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 35: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 36: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 37: UART 2 TX Handler */
+ .long UARTRX3_Handler /* 38: UART 3 RX Handler */
+ .long UARTTX3_Handler /* 39: UART 3 TX Handler */
+ .long UARTRX4_Handler /* 40: UART 4 RX Handler */
+ .long UARTTX4_Handler /* 41: UART 4 TX Handler */
+ .long UART0_Handler /* 42: UART 0 combined Handler */
+ .long UART1_Handler /* 43: UART 1 combined Handler */
+ .long UART2_Handler /* 44: UART 2 combined Handler */
+ .long UART3_Handler /* 45: UART 3 combined Handler */
+ .long UART4_Handler /* 46: UART 4 combined Handler */
+ .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ .long ETHERNET_Handler /* 48: Ethernet Handler */
+ .long I2S_Handler /* 49: I2S Handler */
+ .long TSC_Handler /* 50: Touch Screen Handler */
+ .long 0 /* 51: Reserved */
+ .long SPI0_Handler /* 52: SPI ADC Handler */
+ .long SPI1_Handler /* 53: SPI (Shield 0) Handler */
+ .long SPI2_Handler /* 54: SPI (Shield 1) Handler */
+ .long 0 /* 55: Reserved */
+ .long 0 /* 56: Reserved */
+ .long 0 /* 57: Reserved */
+ .long 0 /* 58: Reserved */
+ .long 0 /* 59: Reserved */
+ .long 0 /* 50: Reserved */
+ .long 0 /* 61: Reserved */
+ .long 0 /* 62: Reserved */
+ .long 0 /* 63: Reserved */
+ .long 0 /* 64: Reserved */
+ .long 0 /* 65: Reserved */
+ .long 0 /* 66: Reserved */
+ .long 0 /* 67: Reserved */
+ .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ .long GPIO2_0_Handler /* 104: All P2 I/O pins used as irq source */
+ .long GPIO2_1_Handler /* 105 There are 15 pins in total */
+ .long GPIO2_2_Handler /* 106 */
+ .long GPIO2_3_Handler /* 107 */
+ .long GPIO2_4_Handler /* 108 */
+ .long GPIO2_5_Handler /* 109 */
+ .long GPIO2_6_Handler /* 110 */
+ .long GPIO2_7_Handler /* 111 */
+ .long GPIO2_8_Handler /* 112 */
+ .long GPIO2_9_Handler /* 113 */
+ .long GPIO2_10_Handler /* 114 */
+ .long GPIO2_11_Handler /* 115 */
+ .long GPIO2_12_Handler /* 116 */
+ .long GPIO2_13_Handler /* 117 */
+ .long GPIO2_14_Handler /* 118 */
+ .long GPIO2_15_Handler /* 119 */
+ .long GPIO3_0_Handler /* 120: All P3 I/O pins used as irq source */
+ .long GPIO3_1_Handler /* 121 There are 4 pins in total */
+ .long GPIO3_2_Handler /* 122 */
+ .long GPIO3_3_Handler /* 123 */
+ .long UARTRX5_Handler /* 124 */
+ .long UARTTX5_Handler /* 125 */
+ .long UART5_Handler /* 126 */
+ .long HDLCD_Handler /* 127 */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+ mrs r0, control /* Get control value */
+ orr r0, r0, #1 /* Select switch to unprivilage mode */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ /* Core interrupts */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
+ def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
+ def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
+ def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */
+ def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */
+ def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
+ def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
+ def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
+ def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
+ def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */
+ def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */
+ def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */
+ def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */
+ def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */
+ def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */
+ def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */
+ def_irq_handler CORDIO_PPU_Handler /* 21 CORDIO PPU Handler */
+ def_irq_handler RAM0_PPU_Handler /* 22 RAM1 PPU Handler */
+ def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */
+ def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */
+ def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */
+ def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */
+ def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ /* External interrupts */
+ def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
+ def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
+ def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
+ def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
+ def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
+ def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
+ def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
+ def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
+ def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
+ def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
+ def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
+ def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
+ def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
+ def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
+ def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
+ def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
+ def_irq_handler I2S_Handler /* 49: I2S Handler */
+ def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
+ def_irq_handler SPI0_Handler /* 52: SPI ADC Handler */
+ def_irq_handler SPI1_Handler /* 53: SPI (Shield 0) Handler */
+ def_irq_handler SPI2_Handler /* 54: SPI (Shield 1) Handler */
+ def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
+ def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
+ def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
+ def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
+ def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
+ def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
+ def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
+ def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
+ def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
+ def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
+ def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
+ def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
+ def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
+ def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
+ def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
+ def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
+ def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_0 Handler */
+ def_irq_handler UARTRX5_Handler /* 124: */
+ def_irq_handler UARTTX5_Handler /* 125: */
+ def_irq_handler UART5_Handler /* 126: */
+ def_irq_handler HDLCD_Handler /* 127: */
+
+ .end
diff --git a/platform/ext/target/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S b/platform/ext/target/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S
new file mode 100644
index 0000000..d7be1ab
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/gcc/startup_cmsdk_mps3_an524_s.S
@@ -0,0 +1,454 @@
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.01 startup_ARMCM33.S
+ * Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
+ */
+
+ .syntax unified
+ .arch armv8-m.main
+
+ .section .vectors
+ .align 2
+ .globl __Vectors
+__Vectors:
+ .long Image$$ARM_LIB_STACK_MSP$$ZI$$Limit /* Top of Stack */
+
+ /* Core interrupts */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long SecureFault_Handler /* Secure Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ .long NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ .long NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ .long S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ .long TIMER0_Handler /* 3: TIMER 0 Handler */
+ .long TIMER1_Handler /* 4: TIMER 1 Handler */
+ .long DUALTIMER_Handler /* 5: Dual Timer Handler */
+ .long MHU0_Handler /* 6: Message Handling Unit 0 */
+ .long MHU1_Handler /* 7: Message Handling Unit 1 */
+ .long 0 /* 8: Reserved */
+ .long MPC_Handler /* 9: MPC Combined (Secure) Handler */
+ .long PPC_Handler /* 10: PPC Combined (Secure) Handler */
+ .long MSC_Handler /* 11: MSC Combined (Secure) Handler */
+ .long BRIDGE_ERROR_Handler /* 12: Bridge Error Combined (Secure) Handler */
+ .long INVALID_INSTR_CACHE_Handler /* 13: CPU Instruction Cache Invalidation Handler */
+ .long 0 /* 14: Reserved */
+ .long SYS_PPU_Handler /* 15: SYS PPU Handler */
+ .long CPU0_PPU_Handler /* 16: CPU0 PPU Handler */
+ .long CPU1_PPU_Handler /* 17: CPU1 PPU Handler */
+ .long CPU0_DBG_PPU_Handler /* 18: CPU0 DBG PPU_Handler */
+ .long CPU1_DBG_PPU_Handler /* 19: CPU1 DBG PPU_Handler */
+ .long CRYPT_PPU_Handler /* 20: CRYPT PPU Handler */
+ .long CORDIO_PPU_Handler /* 21: CORDIO PPU Handler */
+ .long RAM0_PPU_Handler /* 22: RAM0 PPU Handler */
+ .long RAM1_PPU_Handler /* 23: RAM1 PPU Handler */
+ .long RAM2_PPU_Handler /* 24: RAM2 PPU Handler */
+ .long RAM3_PPU_Handler /* 25: RAM3 PPU Handler */
+ .long DBG_PPU_Handler /* 26: DEBUG_PPU Handler */
+ .long 0 /* 27: Reserved */
+ .long CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ .long CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ .long 0 /* 30: Reserved */
+ .long 0 /* 31: Reserved */
+ /* External Interrupts */
+ .long UARTRX0_Handler /* 32: UART 0 RX Handler */
+ .long UARTTX0_Handler /* 33: UART 0 TX Handler */
+ .long UARTRX1_Handler /* 34: UART 1 RX Handler */
+ .long UARTTX1_Handler /* 35: UART 1 TX Handler */
+ .long UARTRX2_Handler /* 36: UART 2 RX Handler */
+ .long UARTTX2_Handler /* 37: UART 2 TX Handler */
+ .long UARTRX3_Handler /* 38: UART 3 RX Handler */
+ .long UARTTX3_Handler /* 39: UART 3 TX Handler */
+ .long UARTRX4_Handler /* 40: UART 4 RX Handler */
+ .long UARTTX4_Handler /* 41: UART 4 TX Handler */
+ .long UART0_Handler /* 42: UART 0 combined Handler */
+ .long UART1_Handler /* 43: UART 1 combined Handler */
+ .long UART2_Handler /* 44: UART 2 combined Handler */
+ .long UART3_Handler /* 45: UART 3 combined Handler */
+ .long UART4_Handler /* 46: UART 4 combined Handler */
+ .long UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ .long ETHERNET_Handler /* 48: Ethernet Handler */
+ .long I2S_Handler /* 49: I2S Handler */
+ .long TSC_Handler /* 50: Touch Screen Handler */
+ .long 0 /* 51: Reserved */
+ .long SPI0_Handler /* 52: SPI ADC Handler */
+ .long SPI1_Handler /* 53: SPI (Shield 0) Handler */
+ .long SPI2_Handler /* 54: SPI (Shield 1) Handler */
+ .long 0 /* 55: Reserved */
+ .long 0 /* 56: Reserved */
+ .long 0 /* 57: Reserved */
+ .long 0 /* 58: Reserved */
+ .long 0 /* 59: Reserved */
+ .long 0 /* 50: Reserved */
+ .long 0 /* 61: Reserved */
+ .long 0 /* 62: Reserved */
+ .long 0 /* 63: Reserved */
+ .long 0 /* 64: Reserved */
+ .long 0 /* 65: Reserved */
+ .long 0 /* 66: Reserved */
+ .long 0 /* 67: Reserved */
+ .long GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ .long GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ .long GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ .long GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ .long GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ .long GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ .long GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ .long GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ .long GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ .long GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ .long GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ .long GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ .long GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ .long GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ .long GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ .long GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ .long GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ .long GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ .long GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ .long GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ .long GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ .long GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ .long GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ .long GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ .long GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ .long GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ .long GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ .long GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ .long GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ .long GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ .long GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ .long GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ .long GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ .long GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ .long GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ .long GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ .long GPIO2_0_Handler /* 104: All P2 I/O pins used as irq source */
+ .long GPIO2_1_Handler /* 105 There are 15 pins in total */
+ .long GPIO2_2_Handler /* 106 */
+ .long GPIO2_3_Handler /* 107 */
+ .long GPIO2_4_Handler /* 108 */
+ .long GPIO2_5_Handler /* 109 */
+ .long GPIO2_6_Handler /* 110 */
+ .long GPIO2_7_Handler /* 111 */
+ .long GPIO2_8_Handler /* 112 */
+ .long GPIO2_9_Handler /* 113 */
+ .long GPIO2_10_Handler /* 114 */
+ .long GPIO2_11_Handler /* 115 */
+ .long GPIO2_12_Handler /* 116 */
+ .long GPIO2_13_Handler /* 117 */
+ .long GPIO2_14_Handler /* 118 */
+ .long GPIO2_15_Handler /* 119 */
+ .long GPIO3_0_Handler /* 120: All P3 I/O pins used as irq source */
+ .long GPIO3_1_Handler /* 121 There are 4 pins in total */
+ .long GPIO3_2_Handler /* 122 */
+ .long GPIO3_3_Handler /* 123 */
+ .long UARTRX5_Handler /* 124 */
+ .long UARTTX5_Handler /* 125 */
+ .long UART5_Handler /* 126 */
+ .long HDLCD_Handler /* 127 */
+
+ .size __Vectors, . - __Vectors
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+ cpsid i /* Disable IRQs */
+ bl SystemInit
+
+ mrs r0, control /* Get control value */
+ orr r0, r0, #2 /* Select switch to PSP */
+ msr control, r0
+ ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Limit
+ msr psp, r0
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+
+/* Macro to define default handlers. */
+ .macro def_irq_handler handler_name
+ .thumb_func
+ .weak \handler_name
+ \handler_name:
+ b \handler_name
+ .endm
+
+ /* Core interrupts */
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SecureFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler NONSEC_WATCHDOG_RESET_Handler /* 0: Non-Secure Watchdog Reset Handler */
+ def_irq_handler NONSEC_WATCHDOG_Handler /* 1: Non-Secure Watchdog Handler */
+ def_irq_handler S32K_TIMER_Handler /* 2: S32K Timer Handler */
+ def_irq_handler TIMER0_Handler /* 3: TIMER 0 Handler */
+ def_irq_handler TIMER1_Handler /* 4: TIMER 1 Handler */
+ def_irq_handler DUALTIMER_Handler /* 5: Dual Timer Handler */
+ def_irq_handler MHU0_Handler /* 6: Message Handling Unit 0 */
+ def_irq_handler MHU1_Handler /* 7: Message Handling Unit 1 */
+ def_irq_handler MPC_Handler /* 9 MPC Combined (Secure) Handler */
+ def_irq_handler PPC_Handler /* 10 PPC Combined (Secure) Handler */
+ def_irq_handler MSC_Handler /* 11 MSC Combined (Secure) Handler */
+ def_irq_handler BRIDGE_ERROR_Handler /* 12 Bridge Error Combined (Secure) Handler */
+ def_irq_handler INVALID_INSTR_CACHE_Handler /* 13 CPU Instruction Cache Invalidation Handler */
+ def_irq_handler SYS_PPU_Handler /* 15 SYS PPU Handler */
+ def_irq_handler CPU0_PPU_Handler /* 16 CPU0 PPU Handler */
+ def_irq_handler CPU1_PPU_Handler /* 17 CPU1 PPU Handler */
+ def_irq_handler CPU0_DBG_PPU_Handler /* 18 CPU0 DBG PPU_Handler */
+ def_irq_handler CPU1_DBG_PPU_Handler /* 19 CPU1 DBG PPU_Handler */
+ def_irq_handler CRYPT_PPU_Handler /* 20 CRYPT PPU Handler */
+ def_irq_handler CORDIO_PPU_Handler /* 21 CORDIO PPU Handler */
+ def_irq_handler RAM0_PPU_Handler /* 22 RAM1 PPU Handler */
+ def_irq_handler RAM1_PPU_Handler /* 23 RAM1 PPU Handler */
+ def_irq_handler RAM2_PPU_Handler /* 24 RAM2 PPU Handler */
+ def_irq_handler RAM3_PPU_Handler /* 25 RAM3 PPU Handler */
+ def_irq_handler DBG_PPU_Handler /* 26 DBG PPU Handler */
+ def_irq_handler CPU0_CTI_Handler /* 28: CPU0 CTI Handler */
+ def_irq_handler CPU1_CTI_Handler /* 29: CPU1 CTI Handler */
+ /* External interrupts */
+ def_irq_handler UARTRX0_Handler /* 32: UART 0 RX Handler */
+ def_irq_handler UARTTX0_Handler /* 33: UART 0 TX Handler */
+ def_irq_handler UARTRX1_Handler /* 34: UART 1 RX Handler */
+ def_irq_handler UARTTX1_Handler /* 35: UART 1 TX Handler */
+ def_irq_handler UARTRX2_Handler /* 36: UART 2 RX Handler */
+ def_irq_handler UARTTX2_Handler /* 37: UART 2 TX Handler */
+ def_irq_handler UARTRX3_Handler /* 38: UART 3 RX Handler */
+ def_irq_handler UARTTX3_Handler /* 39: UART 3 TX Handler */
+ def_irq_handler UARTRX4_Handler /* 40: UART 4 RX Handler */
+ def_irq_handler UARTTX4_Handler /* 41: UART 4 TX Handler */
+ def_irq_handler UART0_Handler /* 42: UART 0 combined Handler */
+ def_irq_handler UART1_Handler /* 43: UART 1 combined Handler */
+ def_irq_handler UART2_Handler /* 44: UART 2 combined Handler */
+ def_irq_handler UART3_Handler /* 45: UART 3 combined Handler */
+ def_irq_handler UART4_Handler /* 46: UART 4 combined Handler */
+ def_irq_handler UARTOVF_Handler /* 47: UART 0,1,2,3,4 Overflow Handler */
+ def_irq_handler ETHERNET_Handler /* 48: Ethernet Handler */
+ def_irq_handler I2S_Handler /* 49: I2S Handler */
+ def_irq_handler TSC_Handler /* 50: Touch Screen Handler */
+ def_irq_handler SPI0_Handler /* 52: SPI ADC Handler */
+ def_irq_handler SPI1_Handler /* 53: SPI (Shield 0) Handler */
+ def_irq_handler SPI2_Handler /* 54: SPI (Shield 1) Handler */
+ def_irq_handler GPIO0_Handler /* 68: GPIO 0 Combined Handler */
+ def_irq_handler GPIO1_Handler /* 69: GPIO 1 Combined Handler */
+ def_irq_handler GPIO2_Handler /* 70: GPIO 2 Combined Handler */
+ def_irq_handler GPIO3_Handler /* 71: GPIO 3 Combined Handler */
+ def_irq_handler GPIO0_0_Handler /* 72: GPIO 0_0 Handler */
+ def_irq_handler GPIO0_1_Handler /* 73: GPIO 0_1 Handler */
+ def_irq_handler GPIO0_2_Handler /* 74: GPIO 0_2 Handler */
+ def_irq_handler GPIO0_3_Handler /* 75: GPIO 0_3 Handler */
+ def_irq_handler GPIO0_4_Handler /* 76: GPIO 0_4 Handler */
+ def_irq_handler GPIO0_5_Handler /* 77: GPIO 0_5 Handler */
+ def_irq_handler GPIO0_6_Handler /* 78: GPIO 0_6 Handler */
+ def_irq_handler GPIO0_7_Handler /* 79: GPIO 0_7 Handler */
+ def_irq_handler GPIO0_8_Handler /* 80: GPIO 0_8 Handler */
+ def_irq_handler GPIO0_9_Handler /* 81: GPIO 0_9 Handler */
+ def_irq_handler GPIO0_10_Handler /* 82: GPIO 0_10 Handler */
+ def_irq_handler GPIO0_11_Handler /* 83: GPIO 0_11 Handler */
+ def_irq_handler GPIO0_12_Handler /* 84: GPIO 0_12 Handler */
+ def_irq_handler GPIO0_13_Handler /* 85: GPIO 0_13 Handler */
+ def_irq_handler GPIO0_14_Handler /* 86: GPIO 0_14 Handler */
+ def_irq_handler GPIO0_15_Handler /* 87: GPIO 0_15 Handler */
+ def_irq_handler GPIO1_0_Handler /* 88: GPIO 1_0 Handler */
+ def_irq_handler GPIO1_1_Handler /* 89: GPIO 1_1 Handler */
+ def_irq_handler GPIO1_2_Handler /* 90: GPIO 1_2 Handler */
+ def_irq_handler GPIO1_3_Handler /* 91: GPIO 1_3 Handler */
+ def_irq_handler GPIO1_4_Handler /* 92: GPIO 1_4 Handler */
+ def_irq_handler GPIO1_5_Handler /* 93: GPIO 1_5 Handler */
+ def_irq_handler GPIO1_6_Handler /* 94: GPIO 1_6 Handler */
+ def_irq_handler GPIO1_7_Handler /* 95: GPIO 1_7 Handler */
+ def_irq_handler GPIO1_8_Handler /* 96: GPIO 1_8 Handler */
+ def_irq_handler GPIO1_9_Handler /* 97: GPIO 1_9 Handler */
+ def_irq_handler GPIO1_10_Handler /* 98: GPIO 1_10 Handler */
+ def_irq_handler GPIO1_11_Handler /* 99: GPIO 1_11 Handler */
+ def_irq_handler GPIO1_12_Handler /* 100: GPIO 1_12 Handler */
+ def_irq_handler GPIO1_13_Handler /* 101: GPIO 1_13 Handler */
+ def_irq_handler GPIO1_14_Handler /* 102: GPIO 1_14 Handler */
+ def_irq_handler GPIO1_15_Handler /* 103: GPIO 1_15 Handler */
+ def_irq_handler GPIO2_0_Handler /* 104: GPIO 2_0 Handler */
+ def_irq_handler GPIO2_1_Handler /* 105: GPIO 2_1 Handler */
+ def_irq_handler GPIO2_2_Handler /* 106: GPIO 2_2 Handler */
+ def_irq_handler GPIO2_3_Handler /* 107: GPIO 2_3 Handler */
+ def_irq_handler GPIO2_4_Handler /* 108: GPIO 2_4 Handler */
+ def_irq_handler GPIO2_5_Handler /* 109: GPIO 2_5 Handler */
+ def_irq_handler GPIO2_6_Handler /* 110: GPIO 2_6 Handler */
+ def_irq_handler GPIO2_7_Handler /* 111: GPIO 2_7 Handler */
+ def_irq_handler GPIO2_8_Handler /* 112: GPIO 2_8 Handler */
+ def_irq_handler GPIO2_9_Handler /* 113: GPIO 2_9 Handler */
+ def_irq_handler GPIO2_10_Handler /* 114: GPIO 2_10 Handler */
+ def_irq_handler GPIO2_11_Handler /* 115: GPIO 2_11 Handler */
+ def_irq_handler GPIO2_12_Handler /* 116: GPIO 2_12 Handler */
+ def_irq_handler GPIO2_13_Handler /* 117: GPIO 2_13 Handler */
+ def_irq_handler GPIO2_14_Handler /* 118: GPIO 2_14 Handler */
+ def_irq_handler GPIO2_15_Handler /* 119: GPIO 2_15 Handler */
+ def_irq_handler GPIO3_0_Handler /* 120: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_1_Handler /* 121: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_2_Handler /* 122: GPIO 3_0 Handler */
+ def_irq_handler GPIO3_3_Handler /* 123: GPIO 3_0 Handler */
+ def_irq_handler UARTRX5_Handler /* 124: */
+ def_irq_handler UARTTX5_Handler /* 125: */
+ def_irq_handler UART5_Handler /* 126: */
+ def_irq_handler HDLCD_Handler /* 127: */
+
+ .end
diff --git a/platform/ext/target/mps3/an524/device/source/system_core_init.c b/platform/ext/target/mps3/an524/device/source/system_core_init.c
new file mode 100644
index 0000000..9aba910
--- /dev/null
+++ b/platform/ext/target/mps3/an524/device/source/system_core_init.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include "system_core_init.h"
+#include "platform_description.h"
+
+ /* Define clocks */
+#define XTAL (32000000UL)
+#define PERIPHERAL_XTAL (32000000UL)
+#define SYSTEM_CLOCK (XTAL)
+#define PERIPHERAL_CLOCK (PERIPHERAL_XTAL)
+
+/* System Core Clock Variable */
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+uint32_t PeripheralClock = PERIPHERAL_CLOCK;
+
+/* System Core Clock update function */
+void SystemCoreClockUpdate(void)
+{
+ SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/* System initialization function */
+void SystemInit(void)
+{
+#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+ extern uint32_t __Vectors;
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = SYSTEM_CLOCK;
+ PeripheralClock = PERIPHERAL_CLOCK;
+}
diff --git a/platform/ext/target/mps3/an524/dummy_boot_seed.c b/platform/ext/target/mps3/an524/dummy_boot_seed.c
new file mode 100644
index 0000000..f4cbb5c
--- /dev/null
+++ b/platform/ext/target/mps3/an524/dummy_boot_seed.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/tfm_plat_boot_seed.h"
+
+/*!
+ * \def BOOT_SEED
+ *
+ * \brief Fixed value for boot seed used for test.
+ */
+#define BOOT_SEED 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, \
+ 0xA8, 0xA9, 0xAA, 0xAB, 0xAC, 0xAD, 0xAE, 0xAF, \
+ 0xB0, 0xB1, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, \
+ 0xB8, 0xB9, 0xBA, 0xBB, 0xBC, 0xBD, 0xBE, 0xBF
+
+static const uint8_t boot_seed[BOOT_SEED_SIZE] = {BOOT_SEED};
+
+enum tfm_plat_err_t tfm_plat_get_boot_seed(uint32_t size, uint8_t *buf)
+{
+ /* FixMe: - This getter function must be ported per target platform.
+ * - Platform service shall provide an API to further interact this
+ * getter function to retrieve the boot seed.
+ */
+
+ uint32_t i;
+ uint8_t *p_dst = buf;
+ const uint8_t *p_src = boot_seed;
+
+ if (size != BOOT_SEED_SIZE) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ for (i = size; i > 0; i--) {
+ *p_dst = *p_src;
+ p_src++;
+ p_dst++;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
diff --git a/platform/ext/target/mps3/an524/dummy_crypto_keys.c b/platform/ext/target/mps3/an524/dummy_crypto_keys.c
new file mode 100644
index 0000000..1db8646
--- /dev/null
+++ b/platform/ext/target/mps3/an524/dummy_crypto_keys.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2017-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/tfm_plat_crypto_keys.h"
+#include <stddef.h>
+
+/* FIXME: Functions in this file should be implemented by platform vendor. For
+ * the security of the storage system, it is critical to use a hardware unique
+ * key. For the security of the attestation, it is critical to use a unique key
+ * pair and keep the private key is secret.
+ */
+
+#define TFM_KEY_LEN_BYTES 16
+
+static const uint8_t sample_tfm_key[TFM_KEY_LEN_BYTES] =
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F};
+
+extern const enum ecc_curve_t initial_attestation_curve_type;
+extern const uint8_t initial_attestation_private_key[];
+extern const uint32_t initial_attestation_private_key_size;
+extern const uint8_t initial_attestation_public_x_key[];
+extern const uint32_t initial_attestation_public_x_key_size;
+extern const uint8_t initial_attestation_public_y_key[];
+extern const uint32_t initial_attestation_public_y_key_size;
+
+/**
+ * \brief Copy the key to the destination buffer
+ *
+ * \param[out] p_dst Pointer to buffer where to store the key
+ * \param[in] p_src Pointer to the key
+ * \param[in] size Length of the key
+ */
+static inline void copy_key(uint8_t *p_dst, const uint8_t *p_src, size_t size)
+{
+ uint32_t i;
+
+ for (i = size; i > 0; i--) {
+ *p_dst = *p_src;
+ p_src++;
+ p_dst++;
+ }
+}
+
+enum tfm_plat_err_t tfm_plat_get_crypto_huk(uint8_t *key, uint32_t size)
+{
+ if(size > TFM_KEY_LEN_BYTES) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ copy_key(key, sample_tfm_key, size);
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t
+tfm_plat_get_initial_attest_key(uint8_t *key_buf,
+ uint32_t size,
+ struct ecc_key_t *ecc_key,
+ enum ecc_curve_t *curve_type)
+{
+ uint8_t *key_dst;
+ const uint8_t *key_src;
+ uint32_t key_size;
+ uint32_t full_key_size = initial_attestation_private_key_size +
+ initial_attestation_public_x_key_size +
+ initial_attestation_public_y_key_size;
+
+ if (size < full_key_size) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Set the EC curve type which the key belongs to */
+ *curve_type = initial_attestation_curve_type;
+
+ /* Copy the private key to the buffer, it MUST be present */
+ key_dst = key_buf;
+ key_src = initial_attestation_private_key;
+ key_size = initial_attestation_private_key_size;
+ copy_key(key_dst, key_src, key_size);
+ ecc_key->priv_key = key_dst;
+ ecc_key->priv_key_size = key_size;
+
+ /* Copy the x-coordinate of public key to the buffer, it MIGHT be present */
+ if (initial_attestation_public_x_key_size != 0) {
+ key_dst = key_dst + key_size;
+ key_src = initial_attestation_public_x_key;
+ key_size = initial_attestation_public_x_key_size;
+ copy_key(key_dst, key_src, key_size);
+ ecc_key->pubx_key = key_dst;
+ ecc_key->pubx_key_size = key_size;
+ } else {
+ ecc_key->pubx_key = NULL;
+ ecc_key->pubx_key_size = 0;
+ }
+
+ /* Copy the y-coordinate of public key to the buffer, it MIGHT be present */
+ if (initial_attestation_public_y_key_size != 0) {
+ key_dst = key_dst + key_size;
+ key_src = initial_attestation_public_y_key;
+ key_size = initial_attestation_public_y_key_size;
+ copy_key(key_dst, key_src, key_size);
+ ecc_key->puby_key = key_dst;
+ ecc_key->puby_key_size = key_size;
+ } else {
+ ecc_key->puby_key = NULL;
+ ecc_key->puby_key_size = 0;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
diff --git a/platform/ext/target/mps3/an524/dummy_device_id.c b/platform/ext/target/mps3/an524/dummy_device_id.c
new file mode 100644
index 0000000..d282385
--- /dev/null
+++ b/platform/ext/target/mps3/an524/dummy_device_id.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2018-2019 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform/include/tfm_plat_device_id.h"
+#include <stddef.h>
+/*
+ * NOTE: Functions in this file must be ported per target platform.
+ */
+
+extern const uint8_t initial_attestation_raw_public_key_hash[];
+extern const uint32_t initial_attestation_raw_public_key_hash_size;
+
+static const uint8_t implementation_id[] = {
+ 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
+ 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
+ 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
+ 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
+};
+
+static const uint8_t example_ean_13[] = "060456527282910010";
+/**
+ * \brief Copy the device specific ID to the destination buffer
+ *
+ * \param[out] p_dst Pointer to buffer where to store ID
+ * \param[in] p_src Pointer to the ID
+ * \param[in] size Length of the ID
+ */
+static inline void copy_id(uint8_t *p_dst, const uint8_t *p_src, size_t size)
+{
+ uint32_t i;
+
+ for (i = size; i > 0; i--) {
+ *p_dst = *p_src;
+ p_src++;
+ p_dst++;
+ }
+}
+
+/**
+ * Instance ID is mapped to EAT Universal Entity ID (UEID)
+ * This implementation creates the instance ID as follows:
+ * - byte 0: 0x01 indicates the type of UEID to be GUID
+ * - byte 1-32: Hash of attestation public key. Public key is hashed in raw
+ * format without any encoding.
+ */
+enum tfm_plat_err_t tfm_plat_get_instance_id(uint32_t *size, uint8_t *buf)
+{
+ uint8_t *p_dst;
+ const uint8_t *p_src = initial_attestation_raw_public_key_hash;
+
+ if (*size < INSTANCE_ID_MAX_SIZE) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ buf[0] = 0x01; /* First byte is type byte: 0x01 indicates GUID */
+ p_dst = &buf[1];
+
+ copy_id(p_dst, p_src, initial_attestation_raw_public_key_hash_size);
+
+ /* Instance ID size: 1 type byte + size of public key hash */
+ *size = initial_attestation_raw_public_key_hash_size + 1;
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_get_implementation_id(uint32_t *size,
+ uint8_t *buf)
+{
+ const uint8_t *p_impl_id = implementation_id;
+ uint32_t impl_id_size = sizeof(implementation_id);
+
+ if (*size < impl_id_size) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ copy_id(buf, p_impl_id, impl_id_size);
+ *size = impl_id_size;
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_get_hw_version(uint32_t *size, uint8_t *buf)
+{
+ const uint8_t *p_hw_version = example_ean_13;
+ uint32_t hw_version_size = sizeof(example_ean_13) - 1;
+
+ if (*size < hw_version_size) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ copy_id(buf, p_hw_version, hw_version_size);
+ *size = hw_version_size;
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
diff --git a/platform/ext/target/mps3/an524/dummy_nv_counters.c b/platform/ext/target/mps3/an524/dummy_nv_counters.c
new file mode 100644
index 0000000..63c2778
--- /dev/null
+++ b/platform/ext/target/mps3/an524/dummy_nv_counters.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/* NOTE: This API should be implemented by platform vendor. For the security of
+ * the secure storage system's and the bootloader's rollback protection etc. it
+ * is CRITICAL to use a internal (in-die) persistent memory for multiple time
+ * programmable (MTP) non-volatile counters or use a One-time Programmable (OTP)
+ * non-volatile counters solution.
+ *
+ * The current software dummy implementation is not resistant to asynchronous
+ * power failures and should not be used in production code. It is exclusively
+ * for testing purposes.
+ */
+
+#include "platform/include/tfm_plat_nv_counters.h"
+
+#include <limits.h>
+#include "Driver_Flash.h"
+#include "flash_layout.h"
+
+/* Compilation time checks to be sure the defines are well defined */
+#ifndef TFM_NV_COUNTERS_AREA_ADDR
+#error "TFM_NV_COUNTERS_AREA_ADDR must be defined in flash_layout.h"
+#endif
+
+#ifndef TFM_NV_COUNTERS_AREA_SIZE
+#error "TFM_NV_COUNTERS_AREA_SIZE must be defined in flash_layout.h"
+#endif
+
+#ifndef TFM_NV_COUNTERS_SECTOR_ADDR
+#error "TFM_NV_COUNTERS_SECTOR_ADDR must be defined in flash_layout.h"
+#endif
+
+#ifndef TFM_NV_COUNTERS_SECTOR_SIZE
+#error "TFM_NV_COUNTERS_SECTOR_SIZE must be defined in flash_layout.h"
+#endif
+
+#ifndef FLASH_DEV_NAME
+#error "FLASH_DEV_NAME must be defined in flash_layout.h"
+#endif
+/* End of compilation time checks to be sure the defines are well defined */
+
+#define SECTOR_OFFSET 0
+#define NV_COUNTER_SIZE sizeof(uint32_t)
+#define INIT_VALUE_SIZE NV_COUNTER_SIZE
+#define NV_COUNTERS_AREA_OFFSET (TFM_NV_COUNTERS_AREA_ADDR - \
+ TFM_NV_COUNTERS_SECTOR_ADDR)
+
+#define NV_COUNTERS_INITIALIZED 0xC0DE0042
+
+/* Import the CMSIS flash device driver */
+extern ARM_DRIVER_FLASH FLASH_DEV_NAME;
+
+enum tfm_plat_err_t tfm_plat_init_nv_counter(void)
+{
+ int32_t err;
+ uint32_t i;
+ uint32_t nbr_counters = ((TFM_NV_COUNTERS_AREA_SIZE - INIT_VALUE_SIZE)
+ / NV_COUNTER_SIZE);
+ uint32_t *p_nv_counter;
+ uint8_t sector_data[TFM_NV_COUNTERS_SECTOR_SIZE] = {0};
+
+ err = FLASH_DEV_NAME.Initialize(NULL);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Read the whole sector to be able to erase and write later in the flash */
+ err = FLASH_DEV_NAME.ReadData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Set the pointer to nv counters position */
+ p_nv_counter = (uint32_t *)(sector_data + NV_COUNTERS_AREA_OFFSET);
+
+ if (p_nv_counter[nbr_counters] == NV_COUNTERS_INITIALIZED) {
+ return TFM_PLAT_ERR_SUCCESS;
+ }
+
+ /* Add watermark, at the end of the NV counters area, to indicate that NV
+ * counters have been initialized.
+ */
+ p_nv_counter[nbr_counters] = NV_COUNTERS_INITIALIZED;
+
+ /* Initialize all counters to 0 */
+ for (i = 0; i < nbr_counters; i++) {
+ p_nv_counter[i] = 0;
+ }
+
+ /* Erase sector before write in it */
+ err = FLASH_DEV_NAME.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Write in flash the in-memory block content after modification */
+ err = FLASH_DEV_NAME.ProgramData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_read_nv_counter(enum tfm_nv_counter_t counter_id,
+ uint32_t size, uint8_t *val)
+{
+ int32_t err;
+ uint32_t flash_addr;
+
+ if (size != NV_COUNTER_SIZE) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ flash_addr = TFM_NV_COUNTERS_AREA_ADDR + (counter_id * NV_COUNTER_SIZE);
+
+ err = FLASH_DEV_NAME.ReadData(flash_addr, val, NV_COUNTER_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_set_nv_counter(enum tfm_nv_counter_t counter_id,
+ uint32_t value)
+{
+ int32_t err;
+ uint32_t *p_nv_counter;
+ uint8_t sector_data[TFM_NV_COUNTERS_SECTOR_SIZE];
+
+ /* Read the whole sector to be able to erase and write later in the flash */
+ err = FLASH_DEV_NAME.ReadData(TFM_NV_COUNTERS_SECTOR_ADDR, sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Set the pointer to nv counter position */
+ p_nv_counter = (uint32_t *)(sector_data + NV_COUNTERS_AREA_OFFSET +
+ (counter_id * NV_COUNTER_SIZE));
+
+ if (value != *p_nv_counter) {
+
+ if (value > *p_nv_counter) {
+ *p_nv_counter = value;
+ } else {
+ return TFM_PLAT_ERR_INVALID_INPUT;
+ }
+
+ /* Erase sector before write in it */
+ err = FLASH_DEV_NAME.EraseSector(TFM_NV_COUNTERS_SECTOR_ADDR);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+
+ /* Write in flash the in-memory block content after modification */
+ err = FLASH_DEV_NAME.ProgramData(TFM_NV_COUNTERS_SECTOR_ADDR,
+ sector_data,
+ TFM_NV_COUNTERS_SECTOR_SIZE);
+ if (err != ARM_DRIVER_OK) {
+ return TFM_PLAT_ERR_SYSTEM_ERR;
+ }
+ }
+
+ return TFM_PLAT_ERR_SUCCESS;
+}
+
+enum tfm_plat_err_t tfm_plat_increment_nv_counter(
+ enum tfm_nv_counter_t counter_id)
+{
+ uint32_t security_cnt;
+ enum tfm_plat_err_t err;
+
+ err = tfm_plat_read_nv_counter(counter_id,
+ sizeof(security_cnt),
+ (uint8_t *)&security_cnt);
+ if (err != TFM_PLAT_ERR_SUCCESS) {
+ return err;
+ }
+
+ if (security_cnt == UINT32_MAX) {
+ return TFM_PLAT_ERR_MAX_VALUE;
+ }
+
+ return tfm_plat_set_nv_counter(counter_id, security_cnt + 1u);
+}
diff --git a/platform/ext/target/mps3/an524/native_drivers/mpc_sie200_drv.c b/platform/ext/target/mps3/an524/native_drivers/mpc_sie200_drv.c
new file mode 100644
index 0000000..b6dd8e9
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/mpc_sie200_drv.c
@@ -0,0 +1,655 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mpc_sie200_drv.h"
+
+#include <stddef.h>
+
+#include "cmsis_compiler.h"
+
+#define MPC_SIE200_BLK_CFG_OFFSET 5U
+
+#define MPC_SIE200_CTRL_SEC_RESP (1UL << 4UL) /* MPC fault triggers a
+ * bus error
+ */
+#define MPC_SIE200_CTRL_AUTOINCREMENT (1UL << 8UL) /* BLK_IDX auto increment */
+#define MPC_SIE200_CTRL_SEC_LOCK_DOWN (1UL << 31UL) /* MPC Security lock down */
+
+/* ARM MPC interrupt */
+#define MPC_SIE200_INT_EN 1UL
+#define MPC_SIE200_INT_STAT 1UL
+
+/* ARM MPC state definitions */
+#define MPC_SIE200_INITIALIZED (1 << 0)
+
+/* Error code returned by the internal driver functions */
+enum mpc_sie200_intern_error_t {
+ MPC_SIE200_INTERN_ERR_NONE = MPC_SIE200_ERR_NONE,
+ MPC_SIE200_INTERN_ERR_NOT_IN_RANGE = MPC_SIE200_ERR_NOT_IN_RANGE,
+ MPC_SIE200_INTERN_ERR_NOT_ALIGNED = MPC_SIE200_ERR_NOT_ALIGNED,
+ MPC_SIE200_INTERN_ERR_INVALID_RANGE = MPC_SIE200_ERR_INVALID_RANGE,
+ MPC_INTERN_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE =
+ MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE,
+ /* Calculated block index
+ * is higher than the maximum allowed by the MPC. It should never
+ * happen unless the controlled ranges of the MPC are misconfigured
+ * in the driver or if the IP has not enough LUTs to cover the
+ * range, due to wrong reported block size for example.
+ */
+ MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH = -1,
+
+};
+
+/* ARM MPC memory mapped register access structure */
+struct mpc_sie200_reg_map_t {
+ volatile uint32_t ctrl; /* (R/W) MPC Control */
+ volatile uint32_t reserved[3];/* Reserved */
+ volatile uint32_t blk_max; /* (R/ ) Maximum value of block based index */
+ volatile uint32_t blk_cfg; /* (R/ ) Block configuration */
+ volatile uint32_t blk_idx; /* (R/W) Index value for accessing block
+ * based look up table
+ */
+ volatile uint32_t blk_lutn; /* (R/W) Block based gating
+ * Look Up Table (LUT)
+ */
+ volatile uint32_t int_stat; /* (R/ ) Interrupt state */
+ volatile uint32_t int_clear; /* ( /W) Interrupt clear */
+ volatile uint32_t int_en; /* (R/W) Interrupt enable */
+ volatile uint32_t int_info1; /* (R/ ) Interrupt information 1 */
+ volatile uint32_t int_info2; /* (R/ ) Interrupt information 2 */
+ volatile uint32_t int_set; /* ( /W) Interrupt set. Debug purpose only */
+ volatile uint32_t reserved2[997]; /* Reserved */
+ volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
+ volatile uint32_t pidr5; /* (R/ ) Peripheral ID 5 */
+ volatile uint32_t pidr6; /* (R/ ) Peripheral ID 6 */
+ volatile uint32_t pidr7; /* (R/ ) Peripheral ID 7 */
+ volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
+ volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
+ volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
+ volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
+ volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
+ volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
+ volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
+ volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
+};
+
+/*
+ * Checks if the address is controlled by the MPC and returns
+ * the range index in which it is contained.
+ *
+ * \param[in] dev MPC device to initialize \ref mpc_sie200_dev_t
+ * \param[in] addr Address to check if it is controlled by MPC.
+ * \param[out] addr_range Range index in which it is contained.
+ *
+ * \return True if the base is controller by the range list, false otherwise.
+ */
+static uint32_t is_ctrl_by_range_list(
+ struct mpc_sie200_dev_t* dev,
+ uint32_t addr,
+ const struct mpc_sie200_memory_range_t** addr_range)
+{
+ uint32_t i;
+ const struct mpc_sie200_memory_range_t* range;
+
+ for(i = 0; i < dev->data->nbr_of_ranges; i++) {
+ range = dev->data->range_list[i];
+ if(addr >= range->base && addr <= range->limit) {
+ *addr_range = range;
+ return 1;
+ }
+ }
+ return 0;
+}
+
+/*
+ * Gets the masks selecting the bits in the LUT of the MPC corresponding
+ * to the base address (included) up to the limit address (included)
+ *
+ * \param[in] mpc_dev The MPC device.
+ * \param[in] base Address in a range controlled by this MPC
+ * (included), aligned on block size.
+ * \param[in] limit Address in a range controlled by this MPC
+ * (included), aligned on block size.
+ * \param[out] range Memory range in which the base address and
+ * limit are.
+ * \param[out] first_word_idx Index of the first touched word in the LUT.
+ * \param[out] nr_words Number of words used in the LUT. If 1, only
+ * first_word_mask is valid and limit_word_mask
+ * must not be used.
+ * \param[out] first_word_mask First word mask in the LUT will be stored here.
+ * \param[out] limit_word_mask Limit word mask in the LUT will be stored here.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_intern_error_t
+ */
+static enum mpc_sie200_intern_error_t get_lut_masks(
+ struct mpc_sie200_dev_t* dev,
+ const uint32_t base, const uint32_t limit,
+ const struct mpc_sie200_memory_range_t** range,
+ uint32_t *first_word_idx,
+ uint32_t *nr_words,
+ uint32_t *first_word_mask,
+ uint32_t *limit_word_mask)
+{
+ const struct mpc_sie200_memory_range_t* base_range;
+ uint32_t block_size;
+ uint32_t base_block_idx;
+ uint32_t base_word_idx;
+ uint32_t blk_max;
+ const struct mpc_sie200_memory_range_t* limit_range;
+ uint32_t limit_block_idx;
+ uint32_t limit_word_idx;
+ uint32_t mask;
+ uint32_t norm_base;
+ uint32_t norm_limit;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ /*
+ * Check that the addresses are within the controlled regions
+ * of this MPC
+ */
+ if(!is_ctrl_by_range_list(dev, base, &base_range) ||
+ !is_ctrl_by_range_list(dev, limit, &limit_range)) {
+ return MPC_SIE200_INTERN_ERR_NOT_IN_RANGE;
+ }
+
+ /* Base and limit should be part of the same range */
+ if(base_range != limit_range) {
+ return MPC_SIE200_INTERN_ERR_INVALID_RANGE;
+ }
+ *range = base_range;
+
+ block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ /* Base and limit+1 addresses must be aligned on the MPC block size */
+ if(base % block_size || (limit+1) % block_size) {
+ return MPC_SIE200_INTERN_ERR_NOT_ALIGNED;
+ }
+
+ /*
+ * Get a normalized address that is an offset from the beginning
+ * of the lowest range controlled by the MPC
+ */
+ norm_base = (base - base_range->base) + base_range->range_offset;
+ norm_limit = (limit - base_range->base) + base_range->range_offset;
+
+ /*
+ * Calculate block index and to which 32 bits word it belongs
+ */
+ limit_block_idx = norm_limit/block_size;
+ limit_word_idx = limit_block_idx/32;
+
+ base_block_idx = norm_base/block_size;
+ base_word_idx = base_block_idx/32;
+
+ if(base_block_idx > limit_block_idx) {
+ return MPC_SIE200_INTERN_ERR_INVALID_RANGE;
+ }
+
+ /* Transmit the information to the caller */
+ *nr_words = limit_word_idx - base_word_idx + 1;
+ *first_word_idx = base_word_idx;
+
+ /* Limit to the highest block that can be configured */
+ blk_max = p_mpc->blk_max;
+
+ if((limit_word_idx > blk_max) || (base_word_idx > blk_max)) {
+ return MPC_SIE200_INTERN_ERR_BLK_IDX_TOO_HIGH;
+ }
+
+ /*
+ * Create the mask for the first word to only select the limit N bits
+ */
+ *first_word_mask = ~((1 << (base_block_idx % 32)) - 1);
+
+ /*
+ * Create the mask for the limit word to select only the first M bits.
+ */
+ *limit_word_mask = (1 << ((limit_block_idx+1) % 32)) - 1;
+ /*
+ * If limit_word_mask is 0, it means that the limit touched block index is
+ * the limit in its word, so the limit word mask has all its bits selected
+ */
+ if(*limit_word_mask == 0) {
+ *limit_word_mask = 0xFFFFFFFF;
+ }
+
+ /*
+ * If the blocks to configure are all packed in one word, only
+ * touch this word.
+ * Code using the computed masks should test if this mask
+ * is non-zero, and if so, only use this one instead of the limit_word_mask
+ * and first_word_mask.
+ * As the only bits that are the same in both masks are the 1 that we want
+ * to select, just use XOR to extract them.
+ */
+ if(base_word_idx == limit_word_idx) {
+ mask = ~(*first_word_mask ^ *limit_word_mask);
+ *first_word_mask = mask;
+ *limit_word_mask = mask;
+ }
+
+ return MPC_SIE200_INTERN_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev,
+ const struct mpc_sie200_memory_range_t** range_list,
+ uint8_t nbr_of_ranges)
+{
+ if((range_list == NULL) || (nbr_of_ranges == 0)) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ dev->data->range_list = range_list;
+ dev->data->nbr_of_ranges = nbr_of_ranges;
+ dev->data->state = MPC_SIE200_INITIALIZED;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev,
+ uint32_t* blk_size)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(blk_size == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ /* Calculate the block size in byte according to the manual */
+ *blk_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev,
+ const uint32_t base,
+ const uint32_t limit,
+ enum mpc_sie200_sec_attr_t attr)
+{
+ enum mpc_sie200_intern_error_t error;
+ uint32_t first_word_idx;
+ uint32_t first_word_mask;
+ uint32_t i;
+ uint32_t limit_word_mask;
+ uint32_t limit_word_idx;
+ uint32_t nr_words;
+ const struct mpc_sie200_memory_range_t* range;
+ uint32_t word_value;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ /* Get the bitmasks used to select the bits in the LUT */
+ error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words,
+ &first_word_mask, &limit_word_mask);
+
+ limit_word_idx = first_word_idx + nr_words - 1;
+
+ if(error != MPC_SIE200_INTERN_ERR_NONE) {
+ /* Map internal error code lower than 0 to a generic errpr */
+ if(error < 0) {
+ return MPC_SIE200_ERR_INVALID_RANGE;
+ }
+ return (enum mpc_sie200_error_t)error;
+ }
+
+ /*
+ * The memory range should allow accesses in with the wanted security
+ * attribute if it requires special attribute for successful accesses
+ */
+ if(range->attr != attr) {
+ return MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE;
+ }
+
+ /*
+ * Starts changing actual configuration so issue DMB to ensure every
+ * transaction has completed by now
+ */
+ __DMB();
+
+ /* Set the block index to the first word that will be updated */
+ p_mpc->blk_idx = first_word_idx;
+
+ /* If only one word needs to be touched in the LUT */
+ if(nr_words == 1) {
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= first_word_mask;
+ } else {
+ word_value &= ~first_word_mask;
+ }
+
+ /*
+ * Set the index again because full word read or write could have
+ * incremented it
+ */
+ p_mpc->blk_idx = first_word_idx;
+ p_mpc->blk_lutn = word_value;
+
+ /* Commit the configuration change */
+ __DSB();
+ __ISB();
+
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* First word */
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= first_word_mask;
+ } else {
+ word_value &= ~first_word_mask;
+ }
+ /*
+ * Set the index again because full word read or write could have
+ * incremented it
+ */
+ p_mpc->blk_idx = first_word_idx;
+ /* Partially configure the first word */
+ p_mpc->blk_lutn = word_value;
+
+ /* Fully configure the intermediate words if there are any */
+ for(i=first_word_idx+1; i<limit_word_idx; i++) {
+ p_mpc->blk_idx = i;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ p_mpc->blk_lutn = 0xFFFFFFFF;
+ } else {
+ p_mpc->blk_lutn = 0x00000000;
+ }
+ }
+
+ /* Partially configure the limit word */
+ p_mpc->blk_idx = limit_word_idx;
+ word_value = p_mpc->blk_lutn;
+ if(attr == MPC_SIE200_SEC_ATTR_NONSECURE) {
+ word_value |= limit_word_mask;
+ } else {
+ word_value &= ~limit_word_mask;
+ }
+ p_mpc->blk_idx = limit_word_idx;
+ p_mpc->blk_lutn = word_value;
+
+ /* Commit the configuration change */
+ __DSB();
+ __ISB();
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_region_config(
+ struct mpc_sie200_dev_t* dev,
+ uint32_t base, uint32_t limit,
+ enum mpc_sie200_sec_attr_t* attr)
+{
+ enum mpc_sie200_sec_attr_t attr_prev;
+ uint32_t block_size;
+ uint32_t block_size_mask;
+ enum mpc_sie200_intern_error_t error;
+ uint32_t first_word_idx;
+ uint32_t first_word_mask;
+ uint32_t i;
+ uint32_t limit_word_idx;
+ uint32_t limit_word_mask;
+ uint32_t nr_words;
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+ const struct mpc_sie200_memory_range_t* range;
+ uint32_t word_value;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(attr == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ /*
+ * Initialize the security attribute to mixed in case of early
+ * termination of this function. A caller that does not check the
+ * returned error will act as if it does not know anything about the
+ * region queried, which is the safest bet
+ */
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+
+ /*
+ * If the base and limit are not aligned, align them and make sure
+ * that the resulting region fully includes the original region
+ */
+ block_size = (1 << (p_mpc->blk_cfg + MPC_SIE200_BLK_CFG_OFFSET));
+
+ block_size_mask = block_size - 1;
+ base &= ~(block_size_mask);
+ limit &= ~(block_size_mask);
+ limit += block_size - 1; /* Round to the upper block address,
+ * and then remove one to get the preceding
+ * address.
+ */
+
+ /* Get the bitmasks used to select the bits in the LUT */
+ error = get_lut_masks(dev, base, limit, &range, &first_word_idx, &nr_words,
+ &first_word_mask, &limit_word_mask);
+
+ limit_word_idx = first_word_idx+nr_words - 1;
+
+ if(error != MPC_SIE200_INTERN_ERR_NONE) {
+ /* Map internal error code lower than 0 to generic error */
+ if(error < 0) {
+ return MPC_SIE200_ERR_INVALID_RANGE;
+ }
+ return (enum mpc_sie200_error_t)error;
+ }
+
+ /* Set the block index to the first word that will be updated */
+ p_mpc->blk_idx = first_word_idx;
+
+ /* If only one word needs to be touched in the LUT */
+ if(nr_words == 1) {
+ word_value = p_mpc->blk_lutn;
+ word_value &= first_word_mask;
+ if(word_value == 0) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ /*
+ * If there are differences between the mask and the word value,
+ * it means that the security attributes of blocks are mixed
+ */
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* Get the partial configuration of the first word */
+ word_value = p_mpc->blk_lutn & first_word_mask;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ /*
+ * Bail out as the security attribute will be the same regardless
+ * of the configuration of other blocks
+ */
+ return MPC_SIE200_ERR_NONE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+ /*
+ * Store the current found attribute, to check that all the blocks indeed
+ * have the same security attribute.
+ */
+ attr_prev = *attr;
+
+ /* Get the configuration of the intermediate words if there are any */
+ for(i=first_word_idx+1; i<limit_word_idx; i++) {
+ p_mpc->blk_idx = i;
+ word_value = p_mpc->blk_lutn;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value == 0xFFFFFFFF) {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ /* If the attribute is different than the one found before, bail out */
+ if(*attr != attr_prev) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+ attr_prev = *attr;
+ }
+
+ /* Get the partial configuration of the limit word */
+ p_mpc->blk_idx = limit_word_idx;
+ word_value = p_mpc->blk_lutn & limit_word_mask;
+ if(word_value == 0x00000000) {
+ *attr = MPC_SIE200_SEC_ATTR_SECURE;
+ } else if(word_value ^ first_word_mask) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ } else {
+ *attr = MPC_SIE200_SEC_ATTR_NONSECURE;
+ }
+
+ if(*attr != attr_prev) {
+ *attr = MPC_SIE200_SEC_ATTR_MIXED;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t* ctrl_val)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(ctrl_val == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ *ctrl_val = p_mpc->ctrl;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t mpc_ctrl)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->ctrl = mpc_ctrl;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev,
+ enum mpc_sie200_sec_resp_t* sec_rep)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ if(sec_rep == 0) {
+ return MPC_SIE200_INVALID_ARG;
+ }
+
+ if(p_mpc->ctrl & MPC_SIE200_CTRL_SEC_RESP) {
+ *sec_rep = MPC_SIE200_RESP_BUS_ERROR;
+ return MPC_SIE200_ERR_NONE;
+ }
+
+ *sec_rep = MPC_SIE200_RESP_RAZ_WI;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->int_en |= MPC_SIE200_INT_EN;
+
+ return MPC_SIE200_ERR_NONE;
+}
+
+void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ p_mpc->int_en &= ~MPC_SIE200_INT_EN;
+}
+
+void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ p_mpc->int_clear = MPC_SIE200_INT_EN;
+}
+
+uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ return (p_mpc->int_stat & MPC_SIE200_INT_STAT);
+}
+
+enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev)
+{
+ struct mpc_sie200_reg_map_t* p_mpc =
+ (struct mpc_sie200_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & MPC_SIE200_INITIALIZED)) {
+ return MPC_SIE200_NOT_INIT;
+ }
+
+ p_mpc->ctrl |= (MPC_SIE200_CTRL_AUTOINCREMENT
+ | MPC_SIE200_CTRL_SEC_LOCK_DOWN);
+
+ return MPC_SIE200_ERR_NONE;
+}
diff --git a/platform/ext/target/mps3/an524/native_drivers/mpc_sie200_drv.h b/platform/ext/target/mps3/an524/native_drivers/mpc_sie200_drv.h
new file mode 100644
index 0000000..998a5f1
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/mpc_sie200_drv.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file mpc_sie200_drv.h
+ * \brief Generic driver for ARM SIE 200 Memory Protection
+ * Controllers (MPC).
+ */
+
+#ifndef __MPC_SIE_200_DRV_H__
+#define __MPC_SIE_200_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Error code returned by the driver functions */
+enum mpc_sie200_error_t {
+ MPC_SIE200_ERR_NONE, /*!< No error */
+ MPC_SIE200_INVALID_ARG, /*!< MPC invalid input arguments */
+ MPC_SIE200_NOT_INIT, /*!< MPC not initialized */
+ MPC_SIE200_ERR_NOT_IN_RANGE, /*!< Address does not belong to a range
+ * controlled by the MPC */
+ MPC_SIE200_ERR_NOT_ALIGNED, /*!< Address is not aligned on the block size
+ * of this MPC
+ */
+ MPC_SIE200_ERR_INVALID_RANGE, /*!< The given address range to configure
+ * is invalid. This could be because:
+ * - The base and limit swapped
+ * - The base and limit addresses
+ * are in different ranges
+ */
+ MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE, /*!< The given range cannot be
+ * accessed with the wanted
+ * security attributes
+ */
+};
+
+/* Security attribute used in various place of the API */
+enum mpc_sie200_sec_attr_t {
+ MPC_SIE200_SEC_ATTR_SECURE, /*!< Secure attribute */
+ MPC_SIE200_SEC_ATTR_NONSECURE, /*!< Non-secure attribute */
+ /*!< Used when getting the configuration of a memory range and some blocks
+ * are secure whereas some other are non secure
+ */
+ MPC_SIE200_SEC_ATTR_MIXED,
+};
+
+/* What can happen when trying to do an illegal memory access */
+enum mpc_sie200_sec_resp_t {
+ MPC_SIE200_RESP_RAZ_WI, /*!< Read As Zero, Write Ignored */
+ MPC_SIE200_RESP_BUS_ERROR /*!< Bus error */
+};
+
+/* Description of a memory range controlled by the MPC */
+struct mpc_sie200_memory_range_t {
+ const uint32_t base; /*!< Base address (included in the range) */
+ const uint32_t limit; /*!< Limit address (included in the range) */
+ const uint32_t range_offset; /*!< Offset of current range area to the 0
+ * point of the whole area (the sum of the
+ * sizes of the previous memory ranges
+ * covered by the same MPC)
+ */
+ const enum mpc_sie200_sec_attr_t attr; /*!< Optional security attribute
+ * needed to be matched when
+ * accessing this range.
+ * For example, the non-secure
+ * alias of a memory region can not
+ * be accessed using secure access,
+ * and configuring the MPC to
+ * secure using that range will not
+ * be permitted by the driver.
+ */
+};
+
+/* ARM MPC SIE 200 device configuration structure */
+struct mpc_sie200_dev_cfg_t {
+ const uint32_t base; /*!< MPC base address */
+};
+
+/* ARM MPC SIE 200 device data structure */
+struct mpc_sie200_dev_data_t {
+ /*!< Array of pointers to memory ranges controlled by the MPC */
+ const struct mpc_sie200_memory_range_t** range_list;
+ uint8_t nbr_of_ranges; /*!< Number of memory ranges in the list */
+ uint8_t state; /*!< Indicates if the MPC driver
+ * is initialized and enabled
+ */
+ uint16_t reserved; /*!< 32 bits alignment */
+};
+
+/* ARM MPC SIE 200 device structure */
+struct mpc_sie200_dev_t {
+ const struct mpc_sie200_dev_cfg_t* const cfg; /*!< MPC configuration */
+ struct mpc_sie200_dev_data_t* const data; /*!< MPC data */
+};
+
+/**
+ * \brief Initializes a MPC device.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] range_list List of memory ranges controller by the MPC
+ * (\ref mpc_sie200_memory_range_t). This list can not
+ * freed after the initializations.
+ * \param[in] nbr_of_ranges Number of memory ranges
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_init(struct mpc_sie200_dev_t* dev,
+ const struct mpc_sie200_memory_range_t** range_list,
+ uint8_t nbr_of_ranges);
+
+/**
+ * \brief Gets MPC block size. All regions must be aligned on this block
+ * size (base address and limit+1 address).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] blk_size MPC block size
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_block_size(struct mpc_sie200_dev_t* dev,
+ uint32_t* blk_size);
+
+/**
+ * \brief Configures a memory region (base and limit included).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] base Base address of the region to poll. This bound is
+ * included. It does not need to be aligned in any way.
+ *
+ * \param[in] limit Limit address of the region to poll. This bound is
+ * included. (limit+1) does not need to be aligned
+ * in any way.
+ * \param[in] attr Security attribute of the region. If the region has mixed
+ * secure/non-secure, a special value is returned
+ * (\ref mpc_sie200_sec_attr_t).
+ *
+ * In case base and limit+1 addresses are not aligned on
+ * the block size, the enclosing region with base and
+ * limit+1 aligned on block size will be queried.
+ * In case of early termination of the function (error), the
+ * security attribute will be set to MPC_SIE200_ATTR_MIXED.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_config_region(struct mpc_sie200_dev_t* dev,
+ const uint32_t base,
+ const uint32_t limit,
+ enum mpc_sie200_sec_attr_t attr);
+
+/**
+ * \brief Gets a memory region configuration(base and limit included).
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] base Base address of the region to get the configuration.
+ * \param[in] limit Limit address of the region to get the configuration.
+ * \param[out] attr Security attribute of the region
+ * \ref mpc_sie200_sec_attr_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_region_config(
+ struct mpc_sie200_dev_t* dev,
+ uint32_t base,
+ uint32_t limit,
+ enum mpc_sie200_sec_attr_t* attr);
+
+/**
+ * \brief Gets the MPC control value.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] ctrl_val Current MPC control value.
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t* ctrl_val);
+
+/**
+ * \brief Sets the MPC control value.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[in] mpc_ctrl New MPC control value
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_set_ctrl(struct mpc_sie200_dev_t* dev,
+ uint32_t mpc_ctrl);
+
+/**
+ * \brief Gets the configured secure response.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ * \param[out] sec_rep Configured secure response (\ref mpc_sie200_sec_resp_t).
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_get_sec_resp(struct mpc_sie200_dev_t* dev,
+ enum mpc_sie200_sec_resp_t* sec_rep);
+
+/**
+ * \brief Enables MPC interrupt.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_irq_enable(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Disables MPC interrupt
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void mpc_sie200_irq_disable(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Clears MPC interrupt.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void mpc_sie200_clear_irq(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Returns the MPC interrupt state.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns 1 if the interrupt is active, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t mpc_sie200_irq_state(struct mpc_sie200_dev_t* dev);
+
+/**
+ * \brief Locks down the MPC configuration.
+ *
+ * \param[in] dev MPC device \ref mpc_sie200_dev_t
+ *
+ * \return Returns error code as specified in \ref mpc_sie200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpc_sie200_error_t mpc_sie200_lock_down(struct mpc_sie200_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __MPC_SIE_200_DRV_H__ */
diff --git a/platform/ext/target/mps3/an524/native_drivers/mpu_armv8m_drv.c b/platform/ext/target/mps3/an524/native_drivers/mpu_armv8m_drv.c
new file mode 100644
index 0000000..8b49297
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/mpu_armv8m_drv.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2017-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "mpu_armv8m_drv.h"
+#include "cmsis.h"
+
+/*
+ * FixMe:
+ * This is a beta quality driver for MPU in v8M. To be finalized.
+ */
+
+enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev,
+ uint32_t privdef_en,
+ uint32_t hfnmi_en)
+{
+ /*No error checking*/
+
+ MPU_Type *mpu = (MPU_Type *)dev->base;
+
+ /*
+ * FixMe: Set 3 pre-defined MAIR_ATTR for memory. The attributes come
+ * from default memory map, need to check if fine-tune is necessary.
+ *
+ * MAIR0_0: Peripheral, Device-nGnRE.
+ * MAIR0_1: Code, WT RA. Same attr for Outer and Inner.
+ * MAIR0_2: SRAM, WBWA RA. Same attr for Outer and Inner.
+ */
+ mpu->MAIR0 = (MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL << MPU_MAIR0_Attr0_Pos) |
+ (MPU_ARMV8M_MAIR_ATTR_CODE_VAL << MPU_MAIR0_Attr1_Pos) |
+ (MPU_ARMV8M_MAIR_ATTR_DATA_VAL << MPU_MAIR0_Attr2_Pos);
+
+ mpu->CTRL =
+ (privdef_en ? MPU_CTRL_PRIVDEFENA_Msk : 0) |
+ (hfnmi_en ? MPU_CTRL_HFNMIENA_Msk : 0);
+
+ /*Ensure all configuration is written before enable*/
+
+ mpu->CTRL |= MPU_CTRL_ENABLE_Msk;
+
+ /* Enable MPU before next instruction */
+ __DSB();
+ __ISB();
+ return MPU_ARMV8M_OK;
+}
+
+enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev)
+{
+ MPU_Type *mpu = (MPU_Type *)dev->base;
+
+ /* Reset all fields as enable does full setup */
+ mpu->CTRL = 0;
+
+ return MPU_ARMV8M_OK;
+}
+
+
+enum mpu_armv8m_error_t mpu_armv8m_region_enable(
+ struct mpu_armv8m_dev_t *dev,
+ struct mpu_armv8m_region_cfg_t *region_cfg)
+{
+ MPU_Type *mpu = (MPU_Type *)dev->base;
+
+ enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK;
+ uint32_t ctrl_before;
+ uint32_t base_cfg;
+ uint32_t limit_cfg;
+
+ /*FIXME : Add complete error checking*/
+ if ((region_cfg->region_base & ~MPU_RBAR_ADDR_Msk) != 0) {
+ return MPU_ARMV8M_ERROR;
+ }
+ /* region_limit doesn't need to be aligned but the scatter
+ * file needs to be setup to ensure that partitions do not overlap.
+ */
+
+ ctrl_before = mpu->CTRL;
+ mpu->CTRL = 0;
+
+ mpu->RNR = region_cfg->region_nr & MPU_RNR_REGION_Msk;
+
+ /* This 0s the lower bits of the base address */
+ base_cfg = region_cfg->region_base & MPU_RBAR_ADDR_Msk;
+ base_cfg |= (region_cfg->attr_sh << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk;
+ base_cfg |= (region_cfg->attr_access << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk;
+ base_cfg |= (region_cfg->attr_exec << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk;
+
+ mpu->RBAR = base_cfg;
+
+ /*This 0s the lower bits of base address but they are treated as 1 */
+ limit_cfg = (region_cfg->region_limit-1) & MPU_RLAR_LIMIT_Msk;
+
+ limit_cfg |= (region_cfg->region_attridx << MPU_RLAR_AttrIndx_Pos) &
+ MPU_RLAR_AttrIndx_Msk;
+
+ limit_cfg |= MPU_RLAR_EN_Msk;
+
+ mpu->RLAR = limit_cfg;
+
+ /*Restore main MPU control*/
+ mpu->CTRL = ctrl_before;
+
+ /* Enable MPU before the next instruction */
+ __DSB();
+ __ISB();
+
+ return ret_val;
+}
+
+
+enum mpu_armv8m_error_t mpu_armv8m_region_disable(
+ struct mpu_armv8m_dev_t *dev,
+ uint32_t region_nr)
+{
+
+ MPU_Type *mpu = (MPU_Type *)dev->base;
+
+ enum mpu_armv8m_error_t ret_val = MPU_ARMV8M_OK;
+ uint32_t ctrl_before;
+
+ /*FIXME : Add complete error checking*/
+
+ ctrl_before = mpu->CTRL;
+ mpu->CTRL = 0;
+
+ mpu->RNR = region_nr & MPU_RNR_REGION_Msk;
+
+ mpu->RBAR = 0;
+ mpu->RLAR = 0;
+
+ /*Restore main MPU control*/
+ mpu->CTRL = ctrl_before;
+
+ return ret_val;
+}
+
+enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev)
+{
+ MPU_Type *mpu = (MPU_Type *)dev->base;
+ uint32_t i = (mpu->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos;
+
+ while (i > 0) {
+ mpu_armv8m_region_disable(dev, i-1);
+ i--;
+ }
+
+ return MPU_ARMV8M_OK;
+
+}
diff --git a/platform/ext/target/mps3/an524/native_drivers/mpu_armv8m_drv.h b/platform/ext/target/mps3/an524/native_drivers/mpu_armv8m_drv.h
new file mode 100644
index 0000000..d427604
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/mpu_armv8m_drv.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2017-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __MPU_ARMV8M_DRV_H__
+#define __MPU_ARMV8M_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PRIVILEGED_DEFAULT_ENABLE 1
+#define HARDFAULT_NMI_ENABLE 1
+
+/* MAIR_ATTR */
+#define MPU_ARMV8M_MAIR_ATTR_DEVICE_VAL 0x04
+#define MPU_ARMV8M_MAIR_ATTR_DEVICE_IDX 0
+#define MPU_ARMV8M_MAIR_ATTR_CODE_VAL 0xAA
+#define MPU_ARMV8M_MAIR_ATTR_CODE_IDX 1
+#define MPU_ARMV8M_MAIR_ATTR_DATA_VAL 0xFF
+#define MPU_ARMV8M_MAIR_ATTR_DATA_IDX 2
+
+struct mpu_armv8m_dev_t {
+ const uint32_t base;
+};
+
+enum mpu_armv8m_error_t {
+ MPU_ARMV8M_OK,
+ MPU_ARMV8M_ERROR
+};
+
+enum mpu_armv8m_attr_exec_t {
+ MPU_ARMV8M_XN_EXEC_OK,
+ MPU_ARMV8M_XN_EXEC_NEVER
+};
+
+enum mpu_armv8m_attr_access_t {
+ MPU_ARMV8M_AP_RW_PRIV_ONLY,
+ MPU_ARMV8M_AP_RW_PRIV_UNPRIV,
+ MPU_ARMV8M_AP_RO_PRIV_ONLY,
+ MPU_ARMV8M_AP_RO_PRIV_UNPRIV
+};
+
+enum mpu_armv8m_attr_shared_t {
+ MPU_ARMV8M_SH_NONE,
+ MPU_ARMV8M_SH_UNUSED,
+ MPU_ARMV8M_SH_OUTER,
+ MPU_ARMV8M_SH_INNER
+};
+
+struct mpu_armv8m_region_cfg_t {
+ uint32_t region_nr;
+ uint32_t region_base;
+ uint32_t region_limit;
+ uint32_t region_attridx;
+ enum mpu_armv8m_attr_exec_t attr_exec;
+ enum mpu_armv8m_attr_access_t attr_access;
+ enum mpu_armv8m_attr_shared_t attr_sh;
+};
+
+struct mpu_armv8m_region_cfg_raw_t {
+ uint32_t region_nr;
+ uint32_t region_base;
+ uint32_t region_limit;
+};
+
+
+/**
+ * \brief Enable MPU
+ *
+ * \param[in] dev MPU device \ref mpu_armv8m_dev_t
+ * \param[in] privdef_en privilege default region 1:enable 0:disable
+ * \param[in] hfnmi_en mpu for hard fault & nmi 1:enable 0:disable
+ *
+ * \return Error code \ref mpu_armv8m_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+
+enum mpu_armv8m_error_t mpu_armv8m_enable(struct mpu_armv8m_dev_t *dev,
+ uint32_t privdef_en,
+ uint32_t hfnmi_en);
+
+/**
+ * \brief Disable MPU
+ *
+ * \param[in] dev MPU device \ref mpu_armv8m_dev_t
+ *
+ * \return Error code \ref arm_mpu_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpu_armv8m_error_t mpu_armv8m_disable(struct mpu_armv8m_dev_t *dev);
+
+/**
+ * \brief Disable MPU and clean all regions
+ *
+ * \param[in] dev MPU device \ref mpu_armv8m_dev_t
+ *
+ * \return Error code \ref arm_mpu_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpu_armv8m_error_t mpu_armv8m_clean(struct mpu_armv8m_dev_t *dev);
+
+/**
+ * \brief Enable MPU Region
+ *
+ * \param[in] dev MPU device \ref mpu_armv8m_dev_t
+ * \param[in] region_cfg MPU region config \ref mpu_armv8m_region_cfg_t
+ *
+ * \return Error code \ref arm_mpu_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpu_armv8m_error_t mpu_armv8m_region_enable(
+ struct mpu_armv8m_dev_t *dev,
+ struct mpu_armv8m_region_cfg_t *region_cfg);
+
+/**
+ * \brief Disable MPU Region
+ *
+ * \param[in] dev MPU device \ref mpu_armv8m_dev_t
+ * \param[in] region_nr Region number
+ *
+ * \return Error code \ref arm_mpu_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum mpu_armv8m_error_t mpu_armv8m_region_disable(
+ struct mpu_armv8m_dev_t *dev,
+ uint32_t region_nr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MPU_ARMV8M_DRV_H__ */
diff --git a/platform/ext/target/mps3/an524/native_drivers/ppc_sse200_drv.c b/platform/ext/target/mps3/an524/native_drivers/ppc_sse200_drv.c
new file mode 100644
index 0000000..dda0550
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/ppc_sse200_drv.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ppc_sse200_drv.h"
+
+/* SPCTRL PPCs control memory mapped registers access structure */
+struct arm_spctrl_ppc_sse200_t {
+ volatile uint32_t reserved[8];
+ volatile uint32_t secppcintstat; /* Secure PPC Interrupt Status */
+ volatile uint32_t secppcintclr; /* Secure PPC Interrupt Clear */
+ volatile uint32_t secppcinten; /* Secure PPC Interrupt Enable */
+ volatile uint32_t reserved1[9];
+ volatile uint32_t ahbnsppc0; /* Non-Secure Access AHB slave Peripheral
+ * Protection Control #0
+ */
+ volatile uint32_t reserved2[3]; /* Reserved for Future Non-secure Access
+ * AHB Slave Peripheral Protection Control
+ */
+ volatile uint32_t ahbnsppcexp0; /* Expansion 0 Non_Secure Access AHB
+ * slave Peripheral Protection Control
+ */
+ volatile uint32_t ahbnsppcexp1; /* Expansion 1 Non_Secure Access AHB
+ * slave Peripheral Protection Control
+ */
+ volatile uint32_t ahbnsppcexp2; /* Expansion 2 Non_Secure Access AHB
+ * slave Peripheral Protection Control
+ */
+ volatile uint32_t ahbnsppcexp3; /* Expansion 3 Non_Secure Access AHB
+ * slave Peripheral Protection Control
+ */
+ volatile uint32_t apbnsppc0; /* Non-Secure Access APB slave Peripheral
+ * Protection Control 0
+ */
+ volatile uint32_t apbnsppc1; /* Non-Secure Access APB slave Peripheral
+ * Protection Control 1
+ */
+ volatile uint32_t reserved3[2]; /* Non-Secure Access APB slave Peripheral
+ * Protection Control [3:1]
+ */
+ volatile uint32_t apbnsppcexp0; /* Expansion 0 Non_Secure Access APB
+ * slave Peripheral Protection Control
+ */
+ volatile uint32_t apbnsppcexp1; /* Expansion 1 Non_Secure Access APB
+ * slave Peripheral Protection Control
+ */
+ volatile uint32_t apbnsppcexp2; /* Expansion 2 Non_Secure Access APB
+ * slave Peripheral Protection Control
+ */
+ volatile uint32_t apbnsppcexp3; /* Expansion 3 Non_Secure Access APB
+ * slave Peripheral Protection Control
+ */
+ volatile uint32_t ahbspppc0; /* Secure Unprivileged Access AHB slave
+ * Peripheral Protection Control 0
+ */
+ volatile uint32_t reserved4[3]; /* Reserved for Future Secure Unprivileged
+ * Access AHB slave Peripheral Protection
+ * Control
+ */
+ volatile uint32_t ahbspppcexp0; /* Expansion 0 Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control
+ */
+ volatile uint32_t ahbspppcexp1; /* Expansion 1 Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control
+ */
+ volatile uint32_t ahbspppcexp2; /* Expansion 2 Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control
+ */
+ volatile uint32_t ahbspppcexp3; /* Expansion 3 Secure Unprivileged Access
+ * AHB slave Peripheral Protection Control
+ */
+ volatile uint32_t apbspppc0; /* Secure Unprivileged Access APB slave
+ * Peripheral 0
+ */
+ volatile uint32_t apbspppc1; /* Secure Unprivileged Access APB slave
+ * Peripheral 1
+ */
+ volatile uint32_t reserved5[2]; /* Reserved for Future Secure Unprivileged
+ * Access APB slave Peripheral Protection
+ * Control
+ */
+ volatile uint32_t apbspppcexp0; /* Expansion 0 Secure Unprivileged Access
+ * APB slave Peripheral Protection
+ * Control
+ */
+ volatile uint32_t apbspppcexp1; /* Expansion 1 Secure Unprivileged Access
+ * APB slave Peripheral Protection
+ * Control
+ */
+ volatile uint32_t apbspppcexp2; /* Expansion 2 Secure Unprivileged Access
+ * APB slave Peripheral Protection
+ * Control
+ */
+ volatile uint32_t apbspppcexp3; /* Expansion 3 Secure Unprivileged Access
+ * APB slave Peripheral Protection
+ * Control
+ */
+};
+
+/* NSPCTRL PPCs memory mapped register access structure */
+struct arm_nspctrl_ppc_sse200_t {
+ volatile uint32_t reserved[36];
+ volatile uint32_t ahbnspppc0;
+ volatile uint32_t reserved1[3];
+ volatile uint32_t ahbnspppcexp0;
+ volatile uint32_t ahbnspppcexp1;
+ volatile uint32_t ahbnspppcexp2;
+ volatile uint32_t ahbnspppcexp3;
+ volatile uint32_t apbnspppc0;
+ volatile uint32_t apbnspppc1;
+ volatile uint32_t reserved2[2];
+ volatile uint32_t apbnspppcexp0;
+ volatile uint32_t apbnspppcexp1;
+ volatile uint32_t apbnspppcexp2;
+ volatile uint32_t apbnspppcexp3;
+};
+
+/* PPC interrupt position mask */
+#define APB_PPC0_INT_POS_MASK (1UL << 0)
+#define APB_PPC1_INT_POS_MASK (1UL << 1)
+/* Reserved bits 2:3 */
+#define APB_PPCEXP0_INT_POS_MASK (1UL << 4)
+#define APB_PPCEXP1_INT_POS_MASK (1UL << 5)
+#define APB_PPCEXP2_INT_POS_MASK (1UL << 6)
+#define APB_PPCEXP3_INT_POS_MASK (1UL << 7)
+/* Reserved bits 8:15 */
+#define AHB_PPC0_INT_POS_MASK (1UL << 16)
+/* Reserved bits 17:19 */
+#define AHB_PPCEXP0_INT_POS_MASK (1UL << 20)
+#define AHB_PPCEXP1_INT_POS_MASK (1UL << 21)
+#define AHB_PPCEXP2_INT_POS_MASK (1UL << 22)
+#define AHB_PPCEXP3_INT_POS_MASK (1UL << 23)
+/* Reserved bits 24:31 */
+
+/* ARM PPC state definitions */
+#define PPC_SSE200_INITIALIZED (1 << 0)
+
+/* Default peripheral states */
+#define SECURE_AS_DEFAULT_PERIPHERAL_STATE 1
+#define PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE 1
+
+void ppc_sse200_init(struct ppc_sse200_dev_t* dev,
+ enum ppc_sse200_name_t ppc_name)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+ struct arm_nspctrl_ppc_sse200_t* p_nspctrl =
+ (struct arm_nspctrl_ppc_sse200_t*)dev->cfg->nspctrl_base;
+
+ switch(ppc_name) {
+ case AHB_PPC0:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppc0;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppc0;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppc0;
+ dev->data->int_bit_mask = AHB_PPC0_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP0:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp0;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp0;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp0;
+ dev->data->int_bit_mask = AHB_PPCEXP0_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP1:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp1;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp1;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp1;
+ dev->data->int_bit_mask = AHB_PPCEXP1_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP2:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp2;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp2;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp2;
+ dev->data->int_bit_mask = AHB_PPCEXP2_INT_POS_MASK;
+ break;
+ case AHB_PPC_EXP3:
+ dev->data->p_ns_ppc = &p_spctrl->ahbnsppcexp3;
+ dev->data->p_sp_ppc = &p_spctrl->ahbspppcexp3;
+ dev->data->p_nsp_ppc = &p_nspctrl->ahbnspppcexp3;
+ dev->data->int_bit_mask = AHB_PPCEXP3_INT_POS_MASK;
+ break;
+ case APB_PPC0:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppc0;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppc0;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc0;
+ dev->data->int_bit_mask = APB_PPC0_INT_POS_MASK;
+ break;
+ case APB_PPC1:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppc1;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppc1;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppc1;
+ dev->data->int_bit_mask = APB_PPC1_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP0:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp0;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp0;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp0;
+ dev->data->int_bit_mask = APB_PPCEXP0_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP1:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp1;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp1;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp1;
+ dev->data->int_bit_mask = APB_PPCEXP1_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP2:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp2;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp2;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp2;
+ dev->data->int_bit_mask = APB_PPCEXP2_INT_POS_MASK;
+ break;
+ case APB_PPC_EXP3:
+ dev->data->p_ns_ppc = &p_spctrl->apbnsppcexp3;
+ dev->data->p_sp_ppc = &p_spctrl->apbspppcexp3;
+ dev->data->p_nsp_ppc = &p_nspctrl->apbnspppcexp3;
+ dev->data->int_bit_mask = APB_PPCEXP3_INT_POS_MASK;
+ break;
+ /* default: The default is not defined intentionally to force the
+ * compiler to check that all enumeration values are
+ * covered in the switch.
+ */
+ }
+
+ dev->data->state = PPC_SSE200_INITIALIZED;
+}
+
+enum ppc_sse200_error_t ppc_sse200_config_peripheral(
+ struct ppc_sse200_dev_t* dev,
+ uint8_t periph,
+ enum ppc_sse200_sec_attr_t sec_attr,
+ enum ppc_sse200_priv_attr_t priv_attr)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PPC_SSE200_NOT_INIT;
+ }
+
+ if(sec_attr == PPC_SSE200_SECURE_ONLY) {
+ /* Sets secure attribute */
+ *(dev->data->p_ns_ppc) &= ~(1U << periph);
+
+ /* Uses secure unprivileged access address (SPCTRL) to set privilege
+ * attribute
+ */
+ if(priv_attr == PPC_SSE200_PRIV_ONLY) {
+ *(dev->data->p_sp_ppc) &= ~(1U << periph);
+ } else {
+ *(dev->data->p_sp_ppc) |= (1U << periph);
+ }
+ } else {
+ /* Sets secure attribute */
+ *(dev->data->p_ns_ppc) |= (1U << periph);
+
+ /* Uses non-secure unprivileged access address (NSPCTRL) to set
+ * privilege attribute
+ */
+ if(priv_attr == PPC_SSE200_PRIV_ONLY) {
+ *(dev->data->p_nsp_ppc) &= ~(1U << periph);
+ } else {
+ *(dev->data->p_nsp_ppc) |= (1U << periph);
+ }
+ }
+
+ return PPC_SSE200_ERR_NONE;
+}
+
+uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev,
+ uint8_t periph)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return SECURE_AS_DEFAULT_PERIPHERAL_STATE;
+ }
+
+ return ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0);
+}
+
+uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev,
+ uint8_t periph)
+{
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PRIVILEGE_ONLY_AS_DEFAULT_PERIPHERAL_STATE;
+ }
+
+ if ((*(dev->data->p_ns_ppc) & (1U << periph)) == 0) {
+ /* Returns secure unprivileged access address (SPCTRL) */
+ return ((*(dev->data->p_sp_ppc) & (1U << periph)) == 0);
+ } else {
+ /* Returns non-secure unprivileged access address (NSPCTRL) */
+ return ((*(dev->data->p_nsp_ppc) & (1U << periph)) == 0);
+ }
+}
+
+enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return PPC_SSE200_NOT_INIT;
+ }
+
+ p_spctrl->secppcinten |= dev->data->int_bit_mask;
+
+ return PPC_SSE200_ERR_NONE;
+}
+
+void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state == PPC_SSE200_INITIALIZED) {
+ p_spctrl->secppcinten &= ~(dev->data->int_bit_mask);
+ }
+}
+
+void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state == PPC_SSE200_INITIALIZED) {
+ p_spctrl->secppcintclr = dev->data->int_bit_mask;
+ }
+}
+
+uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev)
+{
+ struct arm_spctrl_ppc_sse200_t* p_spctrl =
+ (struct arm_spctrl_ppc_sse200_t*)dev->cfg->spctrl_base;
+
+ if(dev->data->state != PPC_SSE200_INITIALIZED) {
+ return 0;
+ }
+
+ return ((p_spctrl->secppcintstat & dev->data->int_bit_mask) != 0);
+}
diff --git a/platform/ext/target/mps3/an524/native_drivers/ppc_sse200_drv.h b/platform/ext/target/mps3/an524/native_drivers/ppc_sse200_drv.h
new file mode 100644
index 0000000..7a08a8f
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/ppc_sse200_drv.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file ppc_sse200_drv.h
+ * \brief Generic driver for ARM SEE 200 Peripheral Protection
+ * Controllers (PPC).
+ */
+
+#ifndef __PPC_SSE_200_DRV_H__
+#define __PPC_SSE_200_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Secure Privilege Control Block aka SPCTRL */
+/* Non-Secure Privilege Control Block aka NSPCTRL */
+
+/* ARM TrustZone PPC device configuration structure */
+struct ppc_sse200_dev_cfg_t {
+ uint32_t const spctrl_base; /*!< SPCTRL base address */
+ uint32_t const nspctrl_base; /*!< NSPCTRL base address */
+};
+
+/* ARM TrustZone PPC device data structure */
+struct ppc_sse200_dev_data_t {
+ volatile uint32_t* p_ns_ppc; /*!< Pointer to non-secure register */
+ volatile uint32_t* p_sp_ppc; /*!< Pointer to secure unprivileged
+ * register
+ */
+ volatile uint32_t* p_nsp_ppc; /*!< Pointer to non-secure unprivileged
+ * register
+ */
+ uint32_t int_bit_mask; /*!< Interrupt bit mask */
+ uint8_t state; /*!< Indicates if the PPC driver
+ * is initialized
+ */
+ uint8_t reserved[3]; /*!< 32 bits alignment */
+};
+
+/* ARM PPC device structure */
+struct ppc_sse200_dev_t {
+ const struct ppc_sse200_dev_cfg_t* const cfg; /*!< PPC configuration */
+ struct ppc_sse200_dev_data_t* const data; /*!< PPC data */
+};
+
+/* Security attribute used to configure the peripheral */
+enum ppc_sse200_sec_attr_t {
+ PPC_SSE200_SECURE_ONLY, /*! Secure access */
+ PPC_SSE200_NONSECURE_ONLY, /*! Non-secure access */
+};
+
+/* Privilege attribute used to configure the peripheral */
+enum ppc_sse200_priv_attr_t {
+ PPC_SSE200_PRIV_AND_NONPRIV, /*! Privilege and non-Privilege access */
+ PPC_SSE200_PRIV_ONLY, /*! Privilege only access */
+};
+
+/* ARM PPC error codes */
+enum ppc_sse200_error_t {
+ PPC_SSE200_ERR_NONE = 0, /*!< No error */
+ PPC_SSE200_NOT_INIT, /*!< PPC not initialized */
+};
+
+/* ARM PPC names */
+enum ppc_sse200_name_t {
+ AHB_PPC0 = 0, /*!< AHB PPC0 */
+ AHB_PPC_EXP0, /*!< Expansion 0 AHB PPC */
+ AHB_PPC_EXP1, /*!< Expansion 1 AHB PPC */
+ AHB_PPC_EXP2, /*!< Expansion 2 AHB PPC */
+ AHB_PPC_EXP3, /*!< Expansion 3 AHB PPC */
+ APB_PPC0, /*!< APB PPC0 */
+ APB_PPC1, /*!< APB PPC1 */
+ APB_PPC_EXP0, /*!< Expansion 0 APB PPC */
+ APB_PPC_EXP1, /*!< Expansion 1 APB PPC */
+ APB_PPC_EXP2, /*!< Expansion 2 APB PPC */
+ APB_PPC_EXP3 /*!< Expansion 3 APB PPC */
+};
+
+/**
+ * \brief Initialize the PPC device.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] ppc_name PPC name \ref ppc_sse200_name_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_init(struct ppc_sse200_dev_t* dev,
+ enum ppc_sse200_name_t ppc_name);
+
+/**
+ * \brief Configures the PPC device.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ * \param[in] sec_attr Secure attribute value.
+ * \param[in] priv_attr Privilege attribute value.
+ *
+ * \return Returns error code as specified in \ref ppc_sse200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum ppc_sse200_error_t ppc_sse200_config_peripheral(
+ struct ppc_sse200_dev_t* dev,
+ uint8_t periph,
+ enum ppc_sse200_sec_attr_t sec_attr,
+ enum ppc_sse200_priv_attr_t priv_attr);
+/**
+ * \brief Checks if the peripheral is configured as secure or non-secure.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ *
+ * \return Returns 1 for secure and 0 for non-secure.
+ * If the driver is not initialized the return value is 1 (secure) as
+ * it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_is_periph_secure(struct ppc_sse200_dev_t* dev,
+ uint8_t periph);
+
+/**
+ * \brief Checks if the peripheral is configured as Privilege only or
+ * Privilege and non-Privilege access mode.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ * \param[in] periph Peripheral position in the PPC.
+ *
+ * \return Returns 1 for Privilege only configuration and 0 for Privilege and
+ * non-Privilege access.
+ * If the driver is not initialized the return of this function is
+ * 1 (Privilege only) as it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_is_periph_priv_only(struct ppc_sse200_dev_t* dev,
+ uint8_t periph);
+/**
+ * \brief Enables PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \return Returns error code as specified in \ref ppc_sse200_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum ppc_sse200_error_t ppc_sse200_irq_enable(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Disables PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_irq_disable(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Clears PPC interrupt.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void ppc_sse200_clear_irq(struct ppc_sse200_dev_t* dev);
+
+/**
+ * \brief Returns the PPC interrupt state.
+ *
+ * \param[in] dev PPC device \ref ppc_sse200_dev_t
+ *
+ * \return Returns 1 if the interrupt is active and otherwise 0.
+ * If the driver is not initialized the return of this function is
+ * 0 (not active) as it is the default system configuration.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t ppc_sse200_irq_state(struct ppc_sse200_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PPC_SSE_200_DRV_H__ */
diff --git a/platform/ext/target/mps3/an524/native_drivers/timer_cmsdk_drv.c b/platform/ext/target/mps3/an524/native_drivers/timer_cmsdk_drv.c
new file mode 100644
index 0000000..b051909
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/timer_cmsdk_drv.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk_drv.c
+ * \brief Generic driver for CMSDK APB Timers.
+ * The timer is a 32-bit down-counter with the following features:
+ * - optional programmable external clock source
+ * - programmable interrupt source, triggered if counter reaches 0
+ * - automatic reload if counter reaches 0
+ */
+
+#include "timer_cmsdk_drv.h"
+
+/** Setter bit manipulation macro */
+#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX)))
+/** Clearing bit manipulation macro */
+#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX)))
+/** Getter bit manipulation macro */
+#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX))))
+
+/**
+ * \brief Timer register map structure
+ *
+ */
+struct timer_cmsdk_reg_map_t {
+ volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */
+ volatile uint32_t value; /* Offset: 0x004 (R/W) current value register */
+ volatile uint32_t reload; /* Offset: 0x008 (R/W) reload value register */
+ union {
+ volatile uint32_t intstatus; /* Offset: 0x00C (R/ ) interrupt
+ * status register
+ */
+ volatile uint32_t intclear; /* Offset: 0x00C ( /W) interrupt
+ * clear register
+ */
+ }intreg;
+};
+
+/**
+ * \brief CTRL register bit definitions
+ *
+ */
+enum ctrl_reg_bits_t {
+ CTRL_REG_ENUM_ENABLE_INDEX = 0,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX = 1,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX = 2,
+ CTRL_REG_ENUM_IRQ_ENABLE_INDEX = 3
+};
+
+/**
+ * \brief INTSTATUS/INTCLEAR register bit definitions
+ *
+ */
+enum interrupt_reg_bits_t {
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX = 0
+};
+
+void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if (dev->data->is_initialized == 0) {
+ register_map->ctrl = 0;
+ register_map->reload = TIMER_CMSDK_DEFAULT_RELOAD;
+ dev->data->is_initialized = 1;
+ }
+}
+
+bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev)
+{
+ return dev->data->is_initialized;
+}
+
+void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl,
+ CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ return GET_BIT(register_map->intreg.intstatus,
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ SET_BIT(register_map->intreg.intclear,
+ INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ return register_map->value;
+}
+
+void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev,
+ uint32_t reload)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ register_map->reload = reload;
+}
+
+void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ register_map->value = register_map->reload;
+}
+
+uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ return register_map->reload;
+}
+
+uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev)
+{
+ struct timer_cmsdk_reg_map_t* register_map =
+ (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+ return register_map->reload - register_map->value;
+}
diff --git a/platform/ext/target/mps3/an524/native_drivers/timer_cmsdk_drv.h b/platform/ext/target/mps3/an524/native_drivers/timer_cmsdk_drv.h
new file mode 100644
index 0000000..a374e63
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/timer_cmsdk_drv.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk_drv.h
+ * \brief Generic driver for CMSDK APB Timers.
+ * The timer is a 32-bit down-counter with the following features:
+ * - optional programmable external clock source
+ * - programmable interrupt source, triggered if counter reaches 0
+ * - automatic reload if counter reaches 0
+ */
+
+#ifndef __TIMER_CMSDK_DRV_H__
+#define __TIMER_CMSDK_DRV_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Maximum reload value */
+#define TIMER_CMSDK_MAX_RELOAD UINT32_MAX /* max of 32-bit */
+#define TIMER_CMSDK_DEFAULT_RELOAD TIMER_CMSDK_MAX_RELOAD
+
+/** CMSDK timer device configuration structure */
+struct timer_cmsdk_dev_cfg_t {
+ const uintptr_t base; /*!< Timer base address */
+};
+
+/** CMSDK timer device data structure */
+struct timer_cmsdk_dev_data_t {
+ bool is_initialized; /*!< Indicates if the timer is initialized */
+};
+
+/* CMSDK timer device structure */
+struct timer_cmsdk_dev_t {
+ const struct timer_cmsdk_dev_cfg_t* const cfg; /*!< Timer configuration */
+ struct timer_cmsdk_dev_data_t* const data; /*!< Timer data */
+};
+
+/**
+ * \brief Initializes timer to a known default state, which is:
+ * - timer disabled
+ * - timer interrupt disabled
+ * - clock source set to internal
+ * - external input disabled
+ * - reload value maxed out
+ * Init should be called prior to any other process and
+ * it's the caller's responsibility to follow proper call order.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is initialized.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if initialized, false otherwise
+ */
+bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Enables external input, which could be used as clock source
+ * by calling \ref timer_cmsdk_set_clock_to_external.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Disables external input.
+ * Make sure if the timer is explicitly wanted to be stopped or set
+ * the clock source to internal by \ref timer_cmsdk_set_clock_to_internal
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if external input is enabled.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to internal.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to external.
+ * Make sure external input is enabled correspondingly
+ * by \ref timer_cmsdk_enable_external_input.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if clock source is external input.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if external, false if internal
+ */
+bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Enables timer operation.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Disables the given hardware timer.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is enabled.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Enables timer interrupt.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Disables timer interrupt.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if a timer interrupt is enabled.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Gets timer interrupt status
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * * \return true if active, false otherwise
+ */
+bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Clears timer interrupt
+ * The interrupt request is held until it is cleared.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Reads timer current value.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return Timer value
+ */
+uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Sets the reload value of the selected timer.
+ *
+ * New reload value takes effect when:
+ * - timer is restarted
+ * - on timer underflow
+ * - when timer_cmsdk_reset is called
+ *
+ * \note In r1p0 technical reference manual it's incorrectly stated
+ * writing the reload value automatically sets the current value also.
+ * r1p1 technical reference manual includes the fix.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ * \param[in] reload Timer reload value to set.
+ * This is the start value of the 32-bit down counter,
+ * which automatically reloaded if 0 is reached.
+ */
+void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev,
+ uint32_t reload);
+
+/**
+ * \brief Resets the timer counter to the reload value instantly
+ * (i.e. without waiting for underflow).
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Gets the reload value of the selected timer.
+ * This is the start value of the 32-bit down counter,
+ * which is automatically reloaded if 0 is reached by the counter.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return Reload value of the selected timer.
+ */
+uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Reads the number of ticks elapsed in the current cycle.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return Get elapsed number of ticks since last reload was set.
+ * Elapsed = (Reload value - Current value)
+ */
+uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __TIMER_CMSDK_DRV_H__ */
diff --git a/platform/ext/target/mps3/an524/native_drivers/uart_cmsdk_drv.c b/platform/ext/target/mps3/an524/native_drivers/uart_cmsdk_drv.c
new file mode 100644
index 0000000..c3d1230
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/uart_cmsdk_drv.c
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "uart_cmsdk_drv.h"
+
+#include <stddef.h>
+
+/* UART register map structure */
+struct _uart_cmsdk_reg_map_t {
+ volatile uint32_t data; /* Offset: 0x000 (R/W) data register */
+ volatile uint32_t state; /* Offset: 0x004 (R/W) status register */
+ volatile uint32_t ctrl; /* Offset: 0x008 (R/W) control register */
+ union {
+ volatile uint32_t intrstatus; /* Offset: 0x00c (R/ ) interrupt status
+ * register
+ */
+ volatile uint32_t intrclear; /* Offset: 0x00c ( /W) interrupt clear
+ * register
+ */
+ }intr_reg;
+ volatile uint32_t bauddiv; /* Offset: 0x010 (R/W) Baudrate divider
+ * register
+ */
+};
+
+/* CTRL Register */
+#define UART_CMSDK_TX_EN (1ul << 0)
+#define UART_CMSDK_RX_EN (1ul << 1)
+#define UART_CMSDK_TX_INTR_EN (1ul << 2)
+#define UART_CMSDK_RX_INTR_EN (1ul << 3)
+
+/* STATE Register */
+#define UART_CMSDK_TX_BF (1ul << 0)
+#define UART_CMSDK_RX_BF (1ul << 1)
+
+/* INTSTATUS Register */
+#define UART_CMSDK_TX_INTR (1ul << 0)
+#define UART_CMSDK_RX_INTR (1ul << 1)
+
+/* UART state definitions */
+#define UART_CMSDK_INITIALIZED (1ul << 0)
+
+enum uart_cmsdk_error_t uart_cmsdk_init(struct uart_cmsdk_dev_t* dev,
+ uint32_t system_clk)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+ if(system_clk == 0) {
+ return UART_CMSDK_ERR_INVALID_ARG;
+ }
+
+ /* Sets baudrate and system clock */
+ dev->data->system_clk = system_clk;
+ dev->data->baudrate = dev->cfg->default_baudrate;
+
+ /* Sets baudrate */
+ p_uart->bauddiv = (dev->data->system_clk / dev->cfg->default_baudrate);
+
+ /* Enables receiver and transmitter */
+ p_uart->ctrl = UART_CMSDK_RX_EN | UART_CMSDK_TX_EN;
+
+ dev->data->state = UART_CMSDK_INITIALIZED;
+
+ return UART_CMSDK_ERR_NONE;
+}
+
+enum uart_cmsdk_error_t uart_cmsdk_set_baudrate(struct uart_cmsdk_dev_t* dev,
+ uint32_t baudrate)
+{
+ uint32_t bauddiv;
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(baudrate == 0) {
+ return UART_CMSDK_ERR_INVALID_BAUD;
+ }
+
+ if(!(dev->data->state & UART_CMSDK_INITIALIZED)) {
+ return UART_CMSDK_ERR_NOT_INIT;
+ }
+
+ /* Sets baudrate */
+ bauddiv = (dev->data->system_clk / baudrate);
+ dev->data->baudrate = baudrate;
+
+ /* Minimum bauddiv value */
+ if(bauddiv < 16) {
+ return UART_CMSDK_ERR_INVALID_BAUD;
+ }
+
+ p_uart->bauddiv = bauddiv;
+
+ return UART_CMSDK_ERR_NONE;
+}
+
+uint32_t uart_cmsdk_get_baudrate(struct uart_cmsdk_dev_t* dev)
+{
+ return dev->data->baudrate;
+}
+
+enum uart_cmsdk_error_t uart_cmsdk_set_clock(struct uart_cmsdk_dev_t* dev,
+ uint32_t system_clk)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(system_clk == 0) {
+ return UART_CMSDK_ERR_INVALID_ARG;
+ }
+
+ if(!(dev->data->state & UART_CMSDK_INITIALIZED)) {
+ return UART_CMSDK_ERR_NOT_INIT;
+ }
+
+ /* Sets system clock */
+ dev->data->system_clk = system_clk;
+
+ /* Updates baudrate divider */
+ p_uart->bauddiv = (dev->data->system_clk / dev->data->baudrate);
+
+ /* Enables receiver and transmitter */
+ return UART_CMSDK_ERR_NONE;
+}
+
+enum uart_cmsdk_error_t uart_cmsdk_read(struct uart_cmsdk_dev_t* dev,
+ uint8_t* byte)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(!(p_uart->state & UART_CMSDK_RX_BF)) {
+ return UART_CMSDK_ERR_NOT_READY;
+ }
+
+ /* Reads data */
+ *byte = (uint8_t)p_uart->data;
+
+ return UART_CMSDK_ERR_NONE;
+}
+
+enum uart_cmsdk_error_t uart_cmsdk_write(struct uart_cmsdk_dev_t* dev,
+ uint8_t byte)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(p_uart->state & UART_CMSDK_TX_BF) {
+ return UART_CMSDK_ERR_NOT_READY;
+ }
+
+ /* Sends data */
+ p_uart->data = byte;
+
+ return UART_CMSDK_ERR_NONE;
+}
+
+enum uart_cmsdk_error_t uart_cmsdk_irq_tx_enable(struct uart_cmsdk_dev_t* dev)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & UART_CMSDK_INITIALIZED)) {
+ return UART_CMSDK_ERR_NOT_INIT;
+ }
+
+ p_uart->ctrl |= UART_CMSDK_TX_INTR_EN;
+
+ return UART_CMSDK_ERR_NONE;
+}
+
+void uart_cmsdk_irq_tx_disable(struct uart_cmsdk_dev_t* dev)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state & UART_CMSDK_INITIALIZED ) {
+ p_uart->ctrl &= ~UART_CMSDK_TX_INTR_EN;
+ }
+}
+
+uint32_t uart_cmsdk_tx_ready(struct uart_cmsdk_dev_t* dev)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & UART_CMSDK_INITIALIZED)) {
+ return 0;
+ }
+
+ return !(p_uart->state & UART_CMSDK_TX_BF);
+}
+
+enum uart_cmsdk_error_t uart_cmsdk_irq_rx_enable(struct uart_cmsdk_dev_t* dev)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & UART_CMSDK_INITIALIZED)) {
+ return UART_CMSDK_ERR_NOT_INIT;
+ }
+
+ p_uart->ctrl |= UART_CMSDK_RX_INTR_EN;
+
+ return UART_CMSDK_ERR_NONE;
+}
+
+void uart_cmsdk_irq_rx_disable(struct uart_cmsdk_dev_t* dev)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state & UART_CMSDK_INITIALIZED) {
+ p_uart->ctrl &= ~UART_CMSDK_RX_INTR_EN;
+ }
+}
+
+uint32_t uart_cmsdk_rx_ready(struct uart_cmsdk_dev_t* dev)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(!(dev->data->state & UART_CMSDK_INITIALIZED)) {
+ return 0;
+ }
+
+ return (p_uart->state & UART_CMSDK_RX_BF);
+}
+
+void uart_cmsdk_clear_interrupt(struct uart_cmsdk_dev_t* dev,
+ enum uart_cmsdk_irq_t irq)
+{
+ struct _uart_cmsdk_reg_map_t* p_uart =
+ (struct _uart_cmsdk_reg_map_t*)dev->cfg->base;
+
+ if(dev->data->state & UART_CMSDK_INITIALIZED) {
+ /* Clears pending interrupts */
+ switch(irq) {
+ case UART_CMSDK_IRQ_RX:
+ p_uart->intr_reg.intrclear = UART_CMSDK_RX_INTR;
+ break;
+ case UART_CMSDK_IRQ_TX:
+ p_uart->intr_reg.intrclear = UART_CMSDK_TX_INTR;
+ break;
+ case UART_CMSDK_IRQ_COMBINED:
+ p_uart->intr_reg.intrclear =
+ (UART_CMSDK_RX_INTR | UART_CMSDK_TX_INTR);
+ break;
+ /* default: not defined to force all cases to be handled */
+ }
+ }
+}
diff --git a/platform/ext/target/mps3/an524/native_drivers/uart_cmsdk_drv.h b/platform/ext/target/mps3/an524/native_drivers/uart_cmsdk_drv.h
new file mode 100644
index 0000000..2d3278e
--- /dev/null
+++ b/platform/ext/target/mps3/an524/native_drivers/uart_cmsdk_drv.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file uart_cmsdk_drv.h
+ * \brief Generic driver for ARM UART.
+ */
+
+#ifndef __UART_CMSDK_DRV_H__
+#define __UART_CMSDK_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ARM UART device configuration structure */
+struct uart_cmsdk_dev_cfg_t {
+ const uint32_t base; /*!< UART base address */
+ const uint32_t default_baudrate; /*!< Default baudrate */
+};
+
+/* ARM UART device data structure */
+struct uart_cmsdk_dev_data_t {
+ uint32_t state; /*!< Indicates if the uart driver
+ * is initialized and enabled
+ */
+ uint32_t system_clk; /*!< System clock */
+ uint32_t baudrate; /*!< Baudrate */
+};
+
+/* ARM UART device structure */
+struct uart_cmsdk_dev_t {
+ const struct uart_cmsdk_dev_cfg_t* const cfg; /*!< UART configuration */
+ struct uart_cmsdk_dev_data_t* const data; /*!< UART data */
+};
+
+/* ARM UART enumeration types */
+enum uart_cmsdk_error_t {
+ UART_CMSDK_ERR_NONE = 0, /*!< No error */
+ UART_CMSDK_ERR_INVALID_ARG, /*!< Error invalid input argument */
+ UART_CMSDK_ERR_INVALID_BAUD, /*!< Invalid baudrate */
+ UART_CMSDK_ERR_NOT_INIT, /*!< Error UART not initialized */
+ UART_CMSDK_ERR_NOT_READY, /*!< Error UART not ready */
+};
+
+enum uart_cmsdk_irq_t {
+ UART_CMSDK_IRQ_RX, /*!< RX interrupt source */
+ UART_CMSDK_IRQ_TX, /*!< TX interrupt source */
+ UART_CMSDK_IRQ_COMBINED /*!< RX-TX combined interrupt source */
+};
+
+/**
+ * \brief Initializes UART. It uses the default baudrate to configure
+ * the peripheral at this point.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ * \param[in] system_clk System clock used by the device.
+ *
+ * \return Returns error code as specified in \ref uart_cmsdk_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_cmsdk_error_t uart_cmsdk_init(struct uart_cmsdk_dev_t* dev,
+ uint32_t system_clk);
+
+/**
+ * \brief Sets the UART baudrate.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ * \param[in] baudrate New baudrate.
+ *
+ * \return Returns error code as specified in \ref uart_cmsdk_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_cmsdk_error_t uart_cmsdk_set_baudrate(struct uart_cmsdk_dev_t* dev,
+ uint32_t baudrate);
+
+/**
+ * \brief Gets the UART baudrate.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ *
+ * \return Returns the UART baudrate.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t uart_cmsdk_get_baudrate(struct uart_cmsdk_dev_t* dev);
+
+/**
+ * \brief Sets system clock.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ * \param[in] system_clk System clock used by the device.
+ *
+ * \return Returns error code as specified in \ref uart_cmsdk_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_cmsdk_error_t uart_cmsdk_set_clock(struct uart_cmsdk_dev_t* dev,
+ uint32_t system_clk);
+/**
+ * \brief Reads one byte from UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ * \param[in] byte Pointer to byte.
+ *
+ * \return Returns error code as specified in \ref uart_cmsdk_error_t
+ *
+ * \note For better performance, this function doesn't check if dev and byte
+ * pointer are NULL, and if the driver is initialized.
+ */
+enum uart_cmsdk_error_t uart_cmsdk_read(struct uart_cmsdk_dev_t* dev,
+ uint8_t* byte);
+
+/**
+ * \brief Writes a byte to UART dev.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ * \param[in] byte Byte to write.
+ *
+ * \return Returns error code as specified in \ref uart_cmsdk_error_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+enum uart_cmsdk_error_t uart_cmsdk_write(struct uart_cmsdk_dev_t* dev,
+ uint8_t byte);
+
+/**
+ * \brief Enables TX interrupt.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ *
+ * \return Returns error code as specified in \ref uart_cmsdk_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_cmsdk_error_t uart_cmsdk_irq_tx_enable(struct uart_cmsdk_dev_t* dev);
+
+/**
+ * \brief Disables TX interrupt.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_cmsdk_irq_tx_disable(struct uart_cmsdk_dev_t* dev);
+
+/**
+ * \brief Verifies if Tx is ready to send more data.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ *
+ * \return 1 if TX is ready, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t uart_cmsdk_tx_ready(struct uart_cmsdk_dev_t* dev);
+
+/**
+ * \brief Enables RX interrupt.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ *
+ * \return Returns error code as specified in \ref uart_cmsdk_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum uart_cmsdk_error_t uart_cmsdk_irq_rx_enable(struct uart_cmsdk_dev_t* dev);
+
+/**
+ * \brief Disables RX interrupt
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_cmsdk_irq_rx_disable(struct uart_cmsdk_dev_t* dev);
+
+/**
+ * \brief Verifies if Rx has data.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ *
+ * \return 1 if RX has data, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t uart_cmsdk_rx_ready(struct uart_cmsdk_dev_t* dev);
+
+/**
+ * \brief Clears UART interrupt.
+ *
+ * \param[in] dev UART device struct \ref uart_cmsdk_dev_t
+ * \param[in] irq IRQ source to clean \ref uart_cmsdk_irq_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void uart_cmsdk_clear_interrupt(struct uart_cmsdk_dev_t* dev,
+ enum uart_cmsdk_irq_t irq);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __UART_CMSDK_DRV_H__ */
diff --git a/platform/ext/target/mps3/an524/partition/flash_layout.h b/platform/ext/target/mps3/an524/partition/flash_layout.h
new file mode 100644
index 0000000..6c9739b
--- /dev/null
+++ b/platform/ext/target/mps3/an524/partition/flash_layout.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __FLASH_LAYOUT_H__
+#define __FLASH_LAYOUT_H__
+
+/*
+ * Use the QSPI as boot flash
+ *
+ * QSPI MPC BLK_CFG register value is 0xD.
+ * Thus QSPI MPC Block size is 256 KB = 2 ^ (0xD + 5).
+ */
+
+/*
+ * The addresses used in the following layout are all NS alias
+ * Flash layout with BL2:
+ * 0x0000_0000 BL2 - MCUBoot (256 KB)
+ * Flash_area_image_0
+ * 0x0004_0000 Secure image (256 KB)
+ * 0x0008_0000 Non-secure image (256 KB)
+ * Flash_area_image_1:
+ * 0x000C_0000 Secure image (256 KB)
+ * 0x0010_0000 Non-secure image (256 KB)
+ * 0x0014_0000 Scratch area (512 KB)
+ * 0x001C_0000 SST area (20 KB)
+ * 0x001C_5000 NV counters (20 B)
+ * 0x001C_5014 Unused
+ *
+ * Flash layout without BL2
+ * 0x0000_0000 Secure image (256 KB)
+ * 0x0008_0000 Non-secure image (256 KB)
+ * 0x001C_0000 SST area (20 KB)
+ * 0x001C_5000 NV counter (20 B)
+ * 0x001C_5014 Unused
+ */
+
+/* Flash base info for BL2 bootloader */
+#define FLASH_BASE_ADDRESS 0x10000000
+/*
+ * Flash device name used by BL2
+ * Name is defined in flash driver file: Driver_Flash.c
+ */
+#define FLASH_DEV_NAME Driver_FLASH0
+
+/*
+ * Flash device name used by SST
+ * Name is defined in flash driver file: Driver_Flash.c
+ */
+#define SST_FLASH_DEV_NAME Driver_FLASH0
+
+
+#define FLASH_AREA_IMAGE_SECTOR_SIZE 0x1000 /* 4 KB */
+#define FLASH_TOTAL_SIZE 0x800000 /* 8 MB */
+
+#define FLASH_AREA_S_IMAGE_SIZE 0x40000 /* 256 KB */
+#define FLASH_AREA_NS_IMAGE_SIZE 0x40000 /* 256 KB */
+
+#define FLASH_AREA_IMAGE_SLOT_SIZE (FLASH_AREA_S_IMAGE_SIZE + \
+ FLASH_AREA_NS_IMAGE_SIZE)
+
+/* offset to QSPI base */
+#define FLASH_AREA_BL2_OFFSET 0x0
+#define FLASH_AREA_BL2_SIZE 0x40000 /* 256 KB */
+
+#define FLASH_AREA_IMAGE_0_OFFSET (FLASH_AREA_BL2_OFFSET + \
+ FLASH_AREA_BL2_SIZE)
+#define FLASH_AREA_IMAGE_0_SIZE FLASH_AREA_IMAGE_SLOT_SIZE
+
+#define FLASH_AREA_IMAGE_1_OFFSET (FLASH_AREA_IMAGE_0_OFFSET + \
+ FLASH_AREA_IMAGE_0_SIZE)
+#define FLASH_AREA_IMAGE_1_SIZE FLASH_AREA_IMAGE_SLOT_SIZE
+
+#define FLASH_AREA_IMAGE_SCRATCH_OFFSET (FLASH_AREA_IMAGE_1_OFFSET + \
+ FLASH_AREA_IMAGE_1_SIZE)
+#define FLASH_AREA_IMAGE_SCRATCH_SIZE FLASH_AREA_IMAGE_SLOT_SIZE
+
+/* Maximum number of status entries supported by the bootloader. */
+#define BOOT_STATUS_MAX_ENTRIES (FLASH_AREA_IMAGE_SLOT_SIZE / \
+ FLASH_AREA_IMAGE_SCRATCH_SIZE)
+
+/* Maximum number of image sectors supported by the bootloader. */
+#define BOOT_MAX_IMG_SECTORS (FLASH_AREA_IMAGE_SLOT_SIZE / \
+ FLASH_AREA_IMAGE_SECTOR_SIZE)
+
+/*
+ * Secure Storage (SST) Service definitions
+ */
+#define SST_FLASH_AREA_OFFSET (FLASH_AREA_IMAGE_SCRATCH_OFFSET + \
+ FLASH_AREA_IMAGE_SCRATCH_SIZE)
+
+/*
+ * In this target the CMSIS driver requires only the offset from the
+ * flash base address instead of the full flash address.
+ */
+#define SST_FLASH_AREA_SIZE 0x5000 /* 20 KB */
+#define SST_FLASH_AREA_ADDR SST_FLASH_AREA_OFFSET
+
+/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */
+#define SST_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE /* 4 KB */
+/* The sectors must be in consecutive memory location */
+#define SST_NBR_OF_SECTORS (SST_FLASH_AREA_SIZE / SST_SECTOR_SIZE)
+/* Specifies the smallest flash programmable unit in bytes */
+#define SST_FLASH_PROGRAM_UNIT 0x1
+/* The maximum asset size to be stored in the SST area */
+#define SST_MAX_ASSET_SIZE 2048
+/* The maximum number of assets to be stored in the SST area */
+#define SST_NUM_ASSETS 10
+
+/* NV Counters definitions */
+#define FLASH_NV_COUNTERS_AREA_SIZE (0x14) /* 20 Bytes */
+#define FLASH_NV_COUNTERS_AREA_OFFSET (SST_FLASH_AREA_OFFSET + \
+ SST_FLASH_AREA_SIZE)
+
+#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_AREA_SIZE FLASH_NV_COUNTERS_AREA_SIZE
+#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
+#define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
+
+/*
+ * Offset and size definition in flash area, used by BL2 MCUboot assemble.py
+ * assemble.py is unable to handle the nested macros.
+ * Only immediate data is valid here.
+ */
+#define SECURE_IMAGE_OFFSET 0x0
+/* FLASH_AREA_S_IMAGE_SIZE */
+#define SECURE_IMAGE_MAX_SIZE 0x40000
+
+/* SECURE_IMAGE_OFFSET + SECURE_IMAGE_MAX_SIZE */
+#define NON_SECURE_IMAGE_OFFSET 0x40000
+/* FLASH_AREA_NS_IMAGE_SIZE */
+#define NON_SECURE_IMAGE_MAX_SIZE 0x40000
+
+/*
+ * Use Internal SRAM0~3 to store RW data
+ * ISRAM0 and ISRAM1 for Secure Data
+ * ISRAM2 and ISRAM3 for Non-Secure Data
+ */
+#define S_RAM_ALIAS_BASE 0x30000000
+#define NS_RAM_ALIAS_BASE 0x20000000
+
+/* Shared data area between bootloader and runtime firmware.
+ * Shared data area is allocated at the beginning of the RAM, it is overlapping
+ * with TF-M Secure code's MSP stack
+ */
+#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE
+#define BOOT_TFM_SHARED_DATA_SIZE 0x400
+
+#endif /* __FLASH_LAYOUT_H__ */
diff --git a/platform/ext/target/mps3/an524/partition/region_defs.h b/platform/ext/target/mps3/an524/partition/region_defs.h
new file mode 100644
index 0000000..dfeade0
--- /dev/null
+++ b/platform/ext/target/mps3/an524/partition/region_defs.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __REGION_DEFS_H__
+#define __REGION_DEFS_H__
+
+#include "flash_layout.h"
+
+#define BL2_HEAP_SIZE 0x0001000
+#define BL2_MSP_STACK_SIZE 0x0001800
+
+#define S_HEAP_SIZE 0x0001000
+#define S_MSP_STACK_SIZE_INIT 0x0000400
+#define S_MSP_STACK_SIZE 0x0000800
+#define S_PSP_STACK_SIZE 0x0000800
+
+#define NS_HEAP_SIZE 0x0001000
+#define NS_MSP_STACK_SIZE 0x0000400
+#define NS_PSP_STACK_SIZE 0x0000C00
+
+/*
+ * This size of buffer is big enough to store an attestation
+ * token produced by initial attestation service
+ */
+#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE 0x200
+
+/*
+ * This configuration uses QSPI for code memory and ISRAM0-3 as data
+ * memory.
+ */
+
+#ifdef BL2
+#ifndef LINK_TO_SECONDARY_PARTITION
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET FLASH_AREA_IMAGE_0_OFFSET
+#define S_IMAGE_SECONDARY_PARTITION_OFFSET FLASH_AREA_IMAGE_1_OFFSET
+#else
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET FLASH_AREA_IMAGE_1_OFFSET
+#define S_IMAGE_SECONDARY_PARTITION_OFFSET FLASH_AREA_IMAGE_0_OFFSET
+#endif /* LINK_TO_SECONDARY_PARTITION */
+#else
+#define S_IMAGE_PRIMARY_PARTITION_OFFSET 0x0
+#endif /* BL2 */
+
+#ifndef LINK_TO_SECONDARY_PARTITION
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_0_OFFSET \
+ + FLASH_AREA_S_IMAGE_SIZE)
+#else
+#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_IMAGE_1_OFFSET \
+ + FLASH_AREA_S_IMAGE_SIZE)
+#endif /* !LINK_TO_SECONDARY_PARTITION */
+
+
+#ifdef BL2
+/*
+ * Boot partition structure if MCUBoot is used:
+ * 1. Bootloader header
+ * 2. Image area
+ * 3. Trailer
+ */
+#define BL2_HEADER_SIZE 0x400 /* 1 KB */
+#define BL2_TRAILER_SIZE 0x400 /* 1 KB */
+#else /* BL2 */
+/* No header if no bootloader, but keep IMAGE_CODE_SIZE the same */
+#define BL2_HEADER_SIZE 0x0
+#define BL2_TRAILER_SIZE 0x800
+#endif /* BL2 */
+
+#define S_IMAGE_CODE_SIZE \
+ (FLASH_AREA_S_IMAGE_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+#define NS_IMAGE_CODE_SIZE \
+ (FLASH_AREA_NS_IMAGE_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
+
+#define CMSE_VENEER_REGION_SIZE 0x300
+
+#define S_ROM_ALIAS_BASE 0x10000000
+#define NS_ROM_ALIAS_BASE 0x00000000
+
+/* RAM ALIAS BASES are defined in flash_layout.h */
+#define TOTAL_RAM_SIZE 0x20000 /* 128 KB */
+
+/* Alias definitions for secure and non-secure areas*/
+#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x))
+#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
+
+#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x))
+#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
+
+/* Secure regions */
+#define S_IMAGE_PRIMARY_AREA_OFFSET (S_IMAGE_PRIMARY_PARTITION_OFFSET + \
+ BL2_HEADER_SIZE)
+#define S_CODE_START S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)
+#define S_CODE_SIZE (S_IMAGE_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
+#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
+
+/* ISRAM0 and ISRAM1 are assigned to Secure data */
+#define S_DATA_START S_RAM_ALIAS(0x0)
+#define S_DATA_SIZE (TOTAL_RAM_SIZE / 2 + (TOTAL_RAM_SIZE / 4))
+#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
+
+/* CMSE Veneers region */
+#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
+#define CMSE_VENEER_REGION_LIMIT (CMSE_VENEER_REGION_START + \
+ CMSE_VENEER_REGION_SIZE - 1)
+
+/* Non-secure regions */
+#define NS_IMAGE_PRIMARY_AREA_OFFSET (NS_IMAGE_PRIMARY_PARTITION_OFFSET + \
+ BL2_HEADER_SIZE)
+#define NS_CODE_START NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)
+#define NS_CODE_SIZE NS_IMAGE_CODE_SIZE
+#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
+
+/* NS partition information is used for MPC configuration */
+#define NS_PARTITION_START NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)
+#define NS_PARTITION_SIZE FLASH_AREA_NS_IMAGE_SIZE
+#define NS_PARTITION_LIMIT (NS_PARTITION_START + NS_PARTITION_SIZE - 1)
+
+/* ISRAM2 and ISRAM3 are assigned to Secure data */
+#define NS_DATA_START NS_RAM_ALIAS(S_DATA_SIZE)
+#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE)
+#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1)
+
+#ifdef BL2
+#define SECONDARY_PARTITION_START \
+ (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET))
+#define SECONDARY_PARTITION_SIZE FLASH_AREA_IMAGE_1_SIZE
+#define SECONDARY_PARTITION_LIMIT (SECONDARY_PARTITION_START + \
+ SECONDARY_PARTITION_SIZE - 1)
+
+#define BL2_ROM_ALIAS_BASE 0x0
+#define BL2_ROM_ALIAS(x) (BL2_ROM_ALIAS_BASE + (x))
+
+/* Bootloader regions */
+#define BL2_CODE_START BL2_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)
+#define BL2_CODE_SIZE FLASH_AREA_BL2_SIZE
+#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1)
+
+#define BL2_DATA_START S_RAM_ALIAS(0x0)
+#define BL2_DATA_SIZE TOTAL_RAM_SIZE
+#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1)
+#endif /* BL2 */
+
+#endif /* __REGION_DEFS_H__ */
diff --git a/platform/ext/target/mps3/an524/services/src/tfm_platform_system.c b/platform/ext/target/mps3/an524/services/src/tfm_platform_system.c
new file mode 100644
index 0000000..78d8f38
--- /dev/null
+++ b/platform/ext/target/mps3/an524/services/src/tfm_platform_system.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include "platform/include/tfm_platform_system.h"
+#include "platform_description.h"
+
+void tfm_platform_hal_system_reset(void)
+{
+ /* Reset the system */
+ NVIC_SystemReset();
+}
+
+enum tfm_platform_err_t tfm_platform_hal_ioctl(tfm_platform_ioctl_req_t request,
+ psa_invec *in_vec,
+ psa_outvec *out_vec)
+{
+ (void)request;
+ (void)in_vec;
+ (void)out_vec;
+
+ /* Not needed for this platform */
+ return TFM_PLATFORM_ERR_NOT_SUPPORTED;
+}
+
diff --git a/platform/ext/target/mps3/an524/spm_hal.c b/platform/ext/target/mps3/an524/spm_hal.c
new file mode 100644
index 0000000..05753d2
--- /dev/null
+++ b/platform/ext/target/mps3/an524/spm_hal.c
@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdio.h>
+#include "tfm_spm_hal.h"
+#include "tfm_platform_core_api.h"
+#include "spm_db.h"
+#include "target_cfg.h"
+#include "mpu_armv8m_drv.h"
+#include "region_defs.h"
+#include "platform_description.h"
+
+/* Debug configuration flags */
+#define SPNIDEN_SEL_STATUS (0x01u << 7)
+#define SPNIDEN_STATUS (0x01u << 6)
+#define SPIDEN_SEL_STATUS (0x01u << 5)
+#define SPIDEN_STATUS (0x01u << 4)
+#define NIDEN_SEL_STATUS (0x01u << 3)
+#define NIDEN_STATUS (0x01u << 2)
+#define DBGEN_SEL_STATUS (0x01u << 1)
+#define DBGEN_STATUS (0x01u << 0)
+
+#define All_SEL_STATUS (SPNIDEN_SEL_STATUS | SPIDEN_SEL_STATUS | \
+ NIDEN_SEL_STATUS | DBGEN_SEL_STATUS)
+
+/* Get address of memory regions to configure MPU */
+extern const struct memory_region_limits memory_regions;
+
+void tfm_spm_hal_init_isolation_hw(void)
+{
+ /* Configures non-secure memory spaces in the target */
+ sau_and_idau_cfg();
+ mpc_init_cfg();
+ ppc_init_cfg();
+}
+
+void tfm_spm_hal_configure_default_isolation(
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ if (platform_data) {
+ if (platform_data->periph_ppc_bank != PPC_SP_DO_NOT_CONFIGURE) {
+ ppc_configure_to_secure_priv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+ }
+}
+
+#if TFM_LVL != 1
+
+#define MPU_REGION_VENEERS 0
+#define MPU_REGION_TFM_UNPRIV_CODE 1
+#define MPU_REGION_TFM_UNPRIV_DATA 2
+#define PARTITION_REGION_RO 4
+#define PARTITION_REGION_RW_STACK 5
+#define PARTITION_REGION_PERIPH 6
+#define PARTITION_REGION_SHARE 7
+
+#if TFM_LVL == 2
+#define MPU_REGION_NS_STACK 3
+#elif TFM_LVL == 3
+#define MPU_REGION_NS_DATA 3
+#endif
+
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+REGION_DECLARE(Image$$, TFM_UNPRIV_DATA, $$RW$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_DATA, $$ZI$$Limit);
+#ifndef TFM_PSA_API
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+REGION_DECLARE(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+#endif
+#if TFM_LVL == 2
+REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base);
+REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
+REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
+REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
+REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Base);
+REGION_DECLARE(Image$$, ARM_LIB_STACK, $$ZI$$Limit);
+#endif
+
+static enum spm_err_t tfm_spm_mpu_init(void)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_clean();
+
+ /* Veneer region */
+ region_cfg.region_nr = MPU_REGION_VENEERS;
+ region_cfg.region_base = memory_regions.veneer_base;
+ region_cfg.region_limit = memory_regions.veneer_limit;
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_CODE_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged code region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_CODE;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_CODE_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* TFM Core unprivileged data region */
+ region_cfg.region_nr = MPU_REGION_TFM_UNPRIV_DATA;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_DATA, $$RW$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_DATA, $$ZI$$Limit);
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+#if TFM_LVL == 3
+ /* TFM Core unprivileged non-secure data region */
+ region_cfg.region_nr = MPU_REGION_NS_DATA;
+ region_cfg.region_base = NS_DATA_START;
+ region_cfg.region_limit = NS_DATA_LIMIT;
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+#endif
+
+#if TFM_LVL == 2
+ /* NSPM PSP */
+ region_cfg.region_nr = MPU_REGION_NS_STACK;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, ARM_LIB_STACK, $$ZI$$Limit);
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* RO region */
+ region_cfg.region_nr = PARTITION_REGION_RO;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_APP_CODE_START, $$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_APP_CODE_END, $$Base);
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_CODE_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ /* RW, ZI and stack as one region */
+ region_cfg.region_nr = PARTITION_REGION_RW_STACK;
+ region_cfg.region_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_START, $$Base);
+ region_cfg.region_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_APP_RW_STACK_END, $$Base);
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+#endif
+
+ mpu_enable(PRIVILEGED_DEFAULT_ENABLE, HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_config(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and enables the
+ * SPM partition for that partition
+ */
+
+ struct mpu_armv8m_region_cfg_t region_cfg;
+
+ mpu_disable();
+
+ /* Configure Regions */
+ if (memory_data->ro_start) {
+ /* RO region */
+ region_cfg.region_nr = PARTITION_REGION_RO;
+ region_cfg.region_base = memory_data->ro_start;
+ region_cfg.region_limit = memory_data->ro_limit;
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_CODE_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_OK;
+
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+ }
+
+ /* RW, ZI and stack as one region */
+ region_cfg.region_nr = PARTITION_REGION_RW_STACK;
+ region_cfg.region_base = memory_data->rw_start;
+ region_cfg.region_limit = memory_data->stack_top;
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ if (platform_data) {
+ /* Peripheral */
+ region_cfg.region_nr = PARTITION_REGION_PERIPH;
+ region_cfg.region_base = platform_data->periph_start;
+ region_cfg.region_limit = platform_data->periph_limit;
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DEVICE_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ if (mpu_region_enable(®ion_cfg) != MPU_ARMV8M_OK) {
+ return SPM_ERR_INVALID_CONFIG;
+ }
+
+ ppc_en_secure_unpriv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_enable(PRIVILEGED_DEFAULT_ENABLE, HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+enum spm_err_t tfm_spm_hal_partition_sandbox_deconfig(
+ const struct tfm_spm_partition_memory_data_t *memory_data,
+ const struct tfm_spm_partition_platform_data_t *platform_data)
+{
+ /* This function takes a partition id and disables the
+ * SPM partition for that partition
+ */
+
+ if (platform_data) {
+ /* Peripheral */
+ ppc_configure_to_secure_priv(platform_data->periph_ppc_bank,
+ platform_data->periph_ppc_loc);
+ }
+
+ mpu_disable();
+ mpu_region_disable(PARTITION_REGION_RO);
+ mpu_region_disable(PARTITION_REGION_RW_STACK);
+ mpu_region_disable(PARTITION_REGION_PERIPH);
+ mpu_region_disable(PARTITION_REGION_SHARE);
+ mpu_enable(PRIVILEGED_DEFAULT_ENABLE, HARDFAULT_NMI_ENABLE);
+
+ return SPM_ERR_OK;
+}
+
+#if !defined(TFM_PSA_API)
+/* Set share region to which the partition needs access */
+enum spm_err_t tfm_spm_hal_set_share_region(
+ enum tfm_buffer_share_region_e share)
+{
+ struct mpu_armv8m_region_cfg_t region_cfg;
+ enum spm_err_t res = SPM_ERR_INVALID_CONFIG;
+ uint32_t scratch_base =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Base);
+ uint32_t scratch_limit =
+ (uint32_t)®ION_NAME(Image$$, TFM_UNPRIV_SCRATCH, $$ZI$$Limit);
+
+ mpu_disable();
+
+ if (share == TFM_BUFFER_SHARE_DISABLE) {
+ mpu_region_disable(PARTITION_REGION_SHARE);
+ } else {
+ region_cfg.region_nr = PARTITION_REGION_SHARE;
+ region_cfg.region_attridx = MPU_ARMV8M_MAIR_ATTR_DATA_IDX;
+ region_cfg.attr_access = MPU_ARMV8M_AP_RW_PRIV_UNPRIV;
+ region_cfg.attr_sh = MPU_ARMV8M_SH_NONE;
+ region_cfg.attr_exec = MPU_ARMV8M_XN_EXEC_NEVER;
+ switch (share) {
+ case TFM_BUFFER_SHARE_SCRATCH:
+ /* Use scratch area for SP-to-SP data sharing */
+ region_cfg.region_base = scratch_base;
+ region_cfg.region_limit = scratch_limit;
+ res = SPM_ERR_OK;
+ break;
+ case TFM_BUFFER_SHARE_NS_CODE:
+ region_cfg.region_base = memory_regions.non_secure_partition_base;
+ region_cfg.region_limit = memory_regions.non_secure_partition_limit;
+ /* Only allow read access to NS code region and keep
+ * exec.never attribute
+ */
+ region_cfg.attr_access = MPU_ARMV8M_AP_RO_PRIV_UNPRIV;
+ res = SPM_ERR_OK;
+ break;
+ default:
+ /* Leave res to be set to SPM_ERR_INVALID_CONFIG */
+ break;
+ }
+ if (res == SPM_ERR_OK) {
+ mpu_region_enable(®ion_cfg);
+ }
+ }
+ mpu_enable(PRIVILEGED_DEFAULT_ENABLE, HARDFAULT_NMI_ENABLE);
+
+ return res;
+}
+#endif /* !defined(TFM_PSA_API) */
+#endif /* TFM_LVL != 1 */
+
+void tfm_spm_hal_setup_isolation_hw(void)
+{
+#if TFM_LVL != 1
+ if (tfm_spm_mpu_init() != SPM_ERR_OK) {
+ ERROR_MSG("Failed to set up initial MPU configuration! Halting.");
+ while (1) {
+ ;
+ }
+ }
+#endif
+}
+
+void MPC_Handler(void)
+{
+ /* Clear MPC interrupt flag and pending MPC IRQ */
+ mpc_clear_irq();
+ NVIC_ClearPendingIRQ(MPC_IRQn);
+
+ /* Print fault message and block execution */
+ LOG_MSG("Oops... MPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+void PPC_Handler(void)
+{
+ /* Clear PPC interrupt flag and pending PPC IRQ */
+ ppc_clear_irq();
+ NVIC_ClearPendingIRQ(PPC_IRQn);
+
+ /* Print fault message*/
+ LOG_MSG("Oops... PPC fault!!!");
+
+ /* Inform TF-M core that isolation boundary has been violated */
+ tfm_access_violation_handler();
+}
+
+uint32_t tfm_spm_hal_get_ns_VTOR(void)
+{
+ return memory_regions.non_secure_code_start;
+}
+
+uint32_t tfm_spm_hal_get_ns_MSP(void)
+{
+ return *((uint32_t *)memory_regions.non_secure_code_start);
+}
+
+uint32_t tfm_spm_hal_get_ns_entry_point(void)
+{
+ return *((uint32_t *)(memory_regions.non_secure_code_start + 4));
+}
+
+void tfm_spm_hal_init_debug(void)
+{
+ volatile struct sysctrl_t *sys_ctrl =
+ (struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S;
+
+#if defined(DAUTH_NONE)
+ /* Set all the debug enable selector bits to 1 */
+ sys_ctrl->secdbgset = All_SEL_STATUS;
+ /* Set all the debug enable bits to 0 */
+ sys_ctrl->secdbgclr =
+ DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS;
+#elif defined(DAUTH_NS_ONLY)
+ /* Set all the debug enable selector bits to 1 */
+ sys_ctrl->secdbgset = All_SEL_STATUS;
+ /* Set the debug enable bits to 1 for NS, and 0 for S mode */
+ sys_ctrl->secdbgset = DBGEN_STATUS | NIDEN_STATUS;
+ sys_ctrl->secdbgclr = SPIDEN_STATUS | SPNIDEN_STATUS;
+#elif defined(DAUTH_FULL)
+ /* Set all the debug enable selector bits to 1 */
+ sys_ctrl->secdbgset = All_SEL_STATUS;
+ /* Set all the debug enable bits to 1 */
+ sys_ctrl->secdbgset =
+ DBGEN_STATUS | NIDEN_STATUS | SPIDEN_STATUS | SPNIDEN_STATUS;
+#else
+
+#if !defined(DAUTH_CHIP_DEFAULT)
+#error "No debug authentication setting is provided."
+#endif
+
+ /* Set all the debug enable selector bits to 0 */
+ sys_ctrl->secdbgclr = All_SEL_STATUS;
+
+ /* No need to set any enable bits because the value depends on
+ * input signals.
+ */
+#endif
+}
diff --git a/platform/ext/target/mps3/an524/target_cfg.c b/platform/ext/target/mps3/an524/target_cfg.c
new file mode 100644
index 0000000..34f0f72
--- /dev/null
+++ b/platform/ext/target/mps3/an524/target_cfg.c
@@ -0,0 +1,482 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "target_cfg.h"
+#include "Driver_MPC.h"
+#include "Driver_PPC.h"
+#include "device_definition.h"
+#include "platform_description.h"
+#include "region_defs.h"
+#include "tfm_secure_api.h"
+#include "mpu_armv8m_drv.h"
+
+/* Macros to pick linker symbols */
+#define REGION(a, b, c) a##b##c
+#define REGION_NAME(a, b, c) REGION(a, b, c)
+#define REGION_DECLARE(a, b, c) extern uint32_t REGION_NAME(a, b, c)
+
+/* The section names come from the scatter file */
+REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
+REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
+REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Limit);
+#ifdef BL2
+REGION_DECLARE(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base);
+#endif /* BL2 */
+
+const struct memory_region_limits memory_regions = {
+ .non_secure_code_start =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
+ BL2_HEADER_SIZE,
+
+ .non_secure_partition_base =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base),
+
+ .non_secure_partition_limit =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_NS_PARTITION, $$Base) +
+ NS_PARTITION_SIZE - 1,
+
+ .veneer_base =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Base),
+
+ .veneer_limit =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_VENEER, $$Limit),
+
+#ifdef BL2
+ .secondary_partition_base =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base),
+
+ .secondary_partition_limit =
+ (uint32_t)®ION_NAME(Load$$LR$$, LR_SECONDARY_PARTITION, $$Base) +
+ SECONDARY_PARTITION_SIZE - 1,
+#endif /* BL2 */
+};
+
+static struct mpu_armv8m_dev_t dev_mpu = { MPU_BASE };
+
+/* Allows software, via SAU, to define the code region as a NSC */
+#define NSCCFG_CODENSC 1
+
+/* Import MPC drivers */
+extern ARM_DRIVER_MPC Driver_QSPI_MPC;
+extern ARM_DRIVER_MPC Driver_ISRAM0_MPC;
+extern ARM_DRIVER_MPC Driver_ISRAM1_MPC;
+extern ARM_DRIVER_MPC Driver_ISRAM2_MPC;
+extern ARM_DRIVER_MPC Driver_ISRAM3_MPC;
+
+/* Import PPC drivers */
+extern ARM_DRIVER_PPC Driver_AHB_PPCEXP0;
+extern ARM_DRIVER_PPC Driver_APB_PPC0;
+extern ARM_DRIVER_PPC Driver_APB_PPC1;
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP0;
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP1;
+extern ARM_DRIVER_PPC Driver_APB_PPCEXP2;
+
+/* Define Peripherals NS address range for the platform */
+#define PERIPHERALS_BASE_NS_START (0x40000000)
+#define PERIPHERALS_BASE_NS_END (0x4FFFFFFF)
+
+/* Enable system reset request for CPU 0 */
+#define ENABLE_CPU0_SYSTEM_RESET_REQUEST (1U << 4U)
+
+/* To write into AIRCR register, 0x5FA value must be write to the VECTKEY field,
+ * otherwise the processor ignores the write.
+ */
+#define SCB_AIRCR_WRITE_MASK ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos))
+
+struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart = {
+ UART1_BASE_S,
+ UART1_BASE_S + 0xFFF,
+ PPC_SP_APB_PPC_EXP2,
+ CMSDK_UART1_APB_PPC_POS
+};
+
+static ARM_DRIVER_PPC *const ppc_bank_drivers[] = {
+ 0, /* AHB PPC0 */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ &Driver_AHB_PPCEXP0, /* AHB PPCEXP0 */
+ 0, /* AHB PPCEXP1 */
+ 0, /* AHB PPCEXP2 */
+ 0, /* AHB PPCEXP3 */
+ &Driver_APB_PPC0, /* APB PPC0 */
+ &Driver_APB_PPC1, /* APB PPC1 */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ &Driver_APB_PPCEXP0, /* APB PPCEXP0 */
+ &Driver_APB_PPCEXP1, /* APB PPCEXP1 */
+ &Driver_APB_PPCEXP2, /* APB PPCEXP2 */
+};
+
+#define PPC_BANK_COUNT (sizeof(ppc_bank_drivers)/sizeof(ppc_bank_drivers[0]))
+
+void enable_fault_handlers(void)
+{
+ /* Enables BUS, MEM, USG and Secure faults */
+ SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk |
+ SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk);
+}
+
+void system_reset_cfg(void)
+{
+ struct sysctrl_t *sysctrl = (struct sysctrl_t *)CMSDK_SYSCTRL_BASE_S;
+ uint32_t reg_value = SCB->AIRCR;
+
+ /* Enable system reset request for CPU 0, to be triggered via
+ * NVIC_SystemReset function.
+ */
+ sysctrl->resetmask |= ENABLE_CPU0_SYSTEM_RESET_REQUEST;
+
+ /* Clear SCB_AIRCR_VECTKEY value */
+ reg_value &= ~(uint32_t)(SCB_AIRCR_VECTKEY_Msk);
+
+ /* Enable system reset request only to the secure world */
+ reg_value |= (uint32_t)(SCB_AIRCR_WRITE_MASK | SCB_AIRCR_SYSRESETREQS_Msk);
+
+ SCB->AIRCR = reg_value;
+}
+
+/*--------------------- NVIC interrupt NS/S configuration --------------------*/
+void nvic_interrupt_target_state_cfg(void)
+{
+ uint8_t i;
+
+ /* Target every interrupt to NS; unimplemented interrupts will be WI */
+ for (i = 0; i < (sizeof(NVIC->ITNS) / sizeof(NVIC->ITNS[0])); i++) {
+ NVIC->ITNS[i] = 0xFFFFFFFF;
+ }
+
+ /* Make sure that MPC and PPC are targeted to S state */
+ NVIC_ClearTargetState(MPC_IRQn);
+ NVIC_ClearTargetState(PPC_IRQn);
+}
+
+enum mpu_armv8m_error_t mpu_enable(uint32_t privdef_en, uint32_t hfnmi_en)
+{
+ return mpu_armv8m_enable(&dev_mpu, privdef_en, hfnmi_en);
+}
+
+enum mpu_armv8m_error_t mpu_disable(void)
+{
+ return mpu_armv8m_disable(&dev_mpu);
+}
+
+enum mpu_armv8m_error_t mpu_region_enable(
+ struct mpu_armv8m_region_cfg_t *region_cfg)
+{
+ if (!region_cfg) {
+ return MPU_ARMV8M_ERROR;
+ }
+
+ return mpu_armv8m_region_enable(&dev_mpu, region_cfg);
+}
+
+enum mpu_armv8m_error_t mpu_region_disable(uint32_t region_nr)
+{
+ return mpu_armv8m_region_disable(&dev_mpu, region_nr);
+}
+
+enum mpu_armv8m_error_t mpu_clean(void)
+{
+ return mpu_armv8m_clean(&dev_mpu);
+}
+
+/*----------------- NVIC interrupt enabling for S peripherals ----------------*/
+void nvic_interrupt_enable(void)
+{
+ /* MPC interrupt enabling */
+ Driver_QSPI_MPC.EnableInterrupt();
+ Driver_ISRAM2_MPC.EnableInterrupt();
+ Driver_ISRAM3_MPC.EnableInterrupt();
+ NVIC_EnableIRQ(MPC_IRQn);
+
+ /* PPC interrupt enabling */
+ /* Clear pending PPC interrupts */
+ /* In the PPC configuration function, we have used the Non-Secure
+ * Privilege Control Block to grant unprivilged NS access to some
+ * peripherals used by NS. That triggers a PPC0 exception as that
+ * register is meant for NS privileged access only. Clear it here
+ */
+ Driver_APB_PPC0.ClearInterrupt();
+
+ /* Enable PPC interrupts for APB PPC */
+ Driver_APB_PPC0.EnableInterrupt();
+ Driver_APB_PPC1.EnableInterrupt();
+ Driver_APB_PPCEXP0.EnableInterrupt();
+ Driver_APB_PPCEXP1.EnableInterrupt();
+ Driver_APB_PPCEXP2.EnableInterrupt();
+
+ NVIC_EnableIRQ(PPC_IRQn);
+}
+
+/*------------------- SAU/IDAU configuration functions -----------------------*/
+void sau_and_idau_cfg(void)
+{
+ struct spctrl_def *spctrl = CMSDK_SPCTRL;
+
+ /* Enables SAU */
+ TZ_SAU_Enable();
+
+ /* Configures SAU regions to be non-secure */
+ SAU->RNR = TFM_NS_REGION_CODE;
+ SAU->RBAR = (memory_regions.non_secure_partition_base
+ & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (memory_regions.non_secure_partition_limit
+ & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
+
+ SAU->RNR = TFM_NS_REGION_DATA;
+ SAU->RBAR = (NS_DATA_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (NS_DATA_LIMIT & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
+
+ /* Configures veneers region to be non-secure callable */
+ SAU->RNR = TFM_NS_REGION_VENEER;
+ SAU->RBAR = (memory_regions.veneer_base & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (memory_regions.veneer_limit & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk | SAU_RLAR_NSC_Msk;
+
+ /* Configure the peripherals space */
+ SAU->RNR = TFM_NS_REGION_PERIPH_1;
+ SAU->RBAR = (PERIPHERALS_BASE_NS_START & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (PERIPHERALS_BASE_NS_END & SAU_RLAR_LADDR_Msk)
+ | SAU_RLAR_ENABLE_Msk;
+#ifdef BL2
+ /* Secondary image partition */
+ SAU->RNR = TFM_NS_SECONDARY_IMAGE_REGION;
+ /* TODO */
+ SAU->RBAR = (memory_regions.secondary_partition_base
+ & SAU_RBAR_BADDR_Msk);
+ SAU->RLAR = (memory_regions.secondary_partition_limit
+ & SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
+#endif /* BL2 */
+
+ /* Allows SAU to define the code region as a NSC */
+ spctrl->nsccfg |= NSCCFG_CODENSC;
+}
+
+/*------------------- Memory configuration functions -------------------------*/
+void mpc_init_cfg(void)
+{
+ Driver_QSPI_MPC.Initialize();
+
+ Driver_QSPI_MPC.ConfigRegion(
+ memory_regions.non_secure_partition_base,
+ memory_regions.non_secure_partition_limit,
+ ARM_MPC_ATTR_NONSECURE);
+#ifdef BL2
+ Driver_QSPI_MPC.ConfigRegion(
+ memory_regions.secondary_partition_base,
+ memory_regions.secondary_partition_limit,
+ ARM_MPC_ATTR_NONSECURE);
+#endif /* BL2 */
+
+ /* NSPE use the last 32KB(ISARM 3) */
+ Driver_ISRAM3_MPC.Initialize();
+ Driver_ISRAM3_MPC.ConfigRegion(
+ MPC_ISRAM3_RANGE_BASE_NS,
+ MPC_ISRAM3_RANGE_LIMIT_NS,
+ ARM_MPC_ATTR_NONSECURE);
+
+ /* Lock down the MPC configuration */
+ Driver_QSPI_MPC.LockDown();
+ Driver_ISRAM2_MPC.LockDown();
+ Driver_ISRAM3_MPC.LockDown();
+
+ /* Add barriers to assure the MPC configuration is done before continue
+ * the execution.
+ */
+ __DSB();
+ __ISB();
+}
+
+void mpc_clear_irq(void)
+{
+ Driver_QSPI_MPC.ClearInterrupt();
+ Driver_ISRAM0_MPC.ClearInterrupt();
+ Driver_ISRAM1_MPC.ClearInterrupt();
+ Driver_ISRAM2_MPC.ClearInterrupt();
+ Driver_ISRAM3_MPC.ClearInterrupt();
+}
+
+/*------------------- PPC configuration functions -------------------------*/
+void ppc_init_cfg(void)
+{
+ struct spctrl_def *spctrl = CMSDK_SPCTRL;
+
+ /* Grant non-secure access to peripherals in the PPC0
+ * (timer0 and 1, dualtimer, watchdog, mhu 0 and 1)
+ */
+ Driver_APB_PPC0.Initialize();
+ Driver_APB_PPC0.ConfigPeriph(CMSDK_TIMER0_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPC0.ConfigPeriph(CMSDK_TIMER1_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPC0.ConfigPeriph(CMSDK_DTIMER_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPC0.ConfigPeriph(CMSDK_MHU0_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPC0.ConfigPeriph(CMSDK_MHU0_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+
+ /* Grant non-secure access to S32K Timer in PPC1*/
+ Driver_APB_PPC1.Initialize();
+ Driver_APB_PPC1.ConfigPeriph(CMSDK_S32K_TIMER_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+
+ /* Grant non-secure access for APB peripherals on EXP1 */
+ Driver_APB_PPCEXP1.Initialize();
+ Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C0_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C1_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_SPI0_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_SPI1_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_SPI2_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C2_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C3_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP1.ConfigPeriph(CMSDK_I2C4_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+
+ /* Grant non-secure access for APB peripherals on EXP2 */
+ Driver_APB_PPCEXP2.Initialize();
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_FPGA_SCC_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_FPGA_AUDIO_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_FPGA_IO_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_AND_NONPRIV);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART0_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART1_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART2_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART3_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART4_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_UART5_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_CLCD_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_APB_PPCEXP2.ConfigPeriph(CMSDK_RTC_APB_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+
+ /*
+ * Grant non-secure access to all peripherals on AHB EXP0:
+ * Make sure that all possible peripherals are enabled by default
+ */
+ Driver_AHB_PPCEXP0.Initialize();
+ Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_GPIO0_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_GPIO1_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_GPIO2_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_GPIO3_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_USB_ETHERNET_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_USER0_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_USER1_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ Driver_AHB_PPCEXP0.ConfigPeriph(CMSDK_USER2_PPC_POS,
+ ARM_PPC_NONSECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+
+ /*
+ * Configure the response to a security violation as a
+ * bus error instead of RAZ/WI
+ */
+ spctrl->secrespcfg |= CMSDK_SECRESPCFG_BUS_ERR_MASK;
+}
+
+void ppc_configure_to_secure_priv(enum ppc_bank_e bank, uint16_t pos)
+{
+ ARM_DRIVER_PPC *ppc_driver;
+
+ if (bank >= PPC_BANK_COUNT) {
+ return;
+ }
+
+ ppc_driver = ppc_bank_drivers[bank];
+ if (ppc_driver) {
+ ppc_driver->ConfigPeriph(pos, ARM_PPC_SECURE_ONLY,
+ ARM_PPC_PRIV_ONLY);
+ }
+}
+
+void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos)
+{
+ ARM_DRIVER_PPC *ppc_driver;
+
+ if (bank >= PPC_BANK_COUNT) {
+ return;
+ }
+
+ ppc_driver = ppc_bank_drivers[bank];
+ if (ppc_driver) {
+ ppc_driver->ConfigPeriph(pos, ARM_PPC_SECURE_ONLY,
+ ARM_PPC_PRIV_AND_NONPRIV);
+ }
+}
+
+void ppc_clear_irq(void)
+{
+ Driver_AHB_PPCEXP0.ClearInterrupt();
+ Driver_APB_PPC0.ClearInterrupt();
+ Driver_APB_PPC1.ClearInterrupt();
+ Driver_APB_PPCEXP0.ClearInterrupt();
+ Driver_APB_PPCEXP1.ClearInterrupt();
+ Driver_APB_PPCEXP2.ClearInterrupt();
+}
diff --git a/platform/ext/target/mps3/an524/target_cfg.h b/platform/ext/target/mps3/an524/target_cfg.h
new file mode 100644
index 0000000..d057861
--- /dev/null
+++ b/platform/ext/target/mps3/an524/target_cfg.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2019 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __TARGET_CFG_H__
+#define __TARGET_CFG_H__
+
+#include <stdint.h>
+
+#define TFM_DRIVER_STDIO Driver_USART0
+#define NS_DRIVER_STDIO Driver_USART0
+
+enum ppc_bank_e {
+ PPC_SP_DO_NOT_CONFIGURE = -1,
+ PPC_SP_AHB_PPC0 = 0,
+ PPC_SP_AHB_PPC_EXP0 = 4,
+ PPC_SP_APB_PPC0 = 8,
+ PPC_SP_APB_PPC1 = 9,
+ PPC_SP_APB_PPC_EXP0 = 12,
+ PPC_SP_APB_PPC_EXP1 = 13,
+ PPC_SP_APB_PPC_EXP2 = 14,
+};
+
+/**
+ * \brief MPU configs
+ */
+#define PRIVILEGED_DEFAULT_ENABLE 1
+#define HARDFAULT_NMI_ENABLE 1
+
+/**
+ * \brief Store the addresses of memory regions
+ */
+struct memory_region_limits {
+ uint32_t non_secure_code_start;
+ uint32_t non_secure_partition_base;
+ uint32_t non_secure_partition_limit;
+ uint32_t veneer_base;
+ uint32_t veneer_limit;
+#ifdef BL2
+ uint32_t secondary_partition_base;
+ uint32_t secondary_partition_limit;
+#endif /* BL2 */
+};
+
+/**
+ * \brief Holds the data necessary to do isolation for a specific peripheral.
+ */
+struct tfm_spm_partition_platform_data_t {
+ uint32_t periph_start;
+ uint32_t periph_limit;
+ int16_t periph_ppc_bank;
+ int16_t periph_ppc_loc;
+};
+
+/**
+ * \brief Forward declaration
+ */
+struct mpu_armv8m_region_cfg_t;
+
+/**
+ * \brief Enables the fault handlers BusFault, UsageFault,
+ * MemManageFault and SecureFault.
+ */
+void enable_fault_handlers(void);
+
+/**
+ * \brief Configures all external interrupts to target the
+ * NS state, apart for the ones associated to secure
+ * peripherals (plus MPC and PPC)
+ */
+void nvic_interrupt_target_state_cfg(void);
+
+/**
+ * \brief This function enable the interrupts associated
+ * to the secure peripherals (plus MPC and PPC)
+ */
+void nvic_interrupt_enable(void);
+
+/**
+ * \brief This function enables the MPU
+ */
+enum mpu_armv8m_error_t mpu_enable(uint32_t privdef_en, uint32_t hfnmi_en);
+
+/**
+ * \brief This function disables the MPU
+ */
+enum mpu_armv8m_error_t mpu_disable(void);
+
+/**
+ * \brief This function enables the given MPU region
+ */
+enum mpu_armv8m_error_t mpu_region_enable(
+ struct mpu_armv8m_region_cfg_t *region_cfg);
+
+/**
+ * \brief This function dsables the given MPU region
+ */
+enum mpu_armv8m_error_t mpu_region_disable(uint32_t region_nr);
+
+/**
+ * \brief This function cleans all the MPU regions configs
+ */
+enum mpu_armv8m_error_t mpu_clean(void);
+
+/**
+ * \brief Configures the Memory Protection Controller.
+ */
+void mpc_init_cfg(void);
+
+/**
+ * \brief Clear MPC interrupt.
+ */
+void mpc_clear_irq(void);
+
+/**
+ * \brief Configures the Peripheral Protection Controller.
+ */
+void ppc_init_cfg(void);
+
+/**
+ * \brief Restict access to peripheral to secure privileged
+ */
+void ppc_configure_to_secure_priv(enum ppc_bank_e bank, uint16_t loc);
+
+/**
+ * \brief Allow non-secure access to peripheral
+ */
+void ppc_configure_to_non_secure(enum ppc_bank_e bank, uint16_t loc);
+
+/**
+ * \brief Enable secure unprivileged access to peripheral
+ */
+void ppc_en_secure_unpriv(enum ppc_bank_e bank, uint16_t pos);
+
+/**
+ * \brief Clears PPC interrupt.
+ */
+void ppc_clear_irq(void);
+
+/**
+ * \brief Configures SAU and IDAU.
+ */
+void sau_and_idau_cfg(void);
+
+#endif /* __TARGET_CFG_H__ */
diff --git a/platform/ext/target/mps3/an524/tfm_peripherals_def.h b/platform/ext/target/mps3/an524/tfm_peripherals_def.h
new file mode 100644
index 0000000..7966756
--- /dev/null
+++ b/platform/ext/target/mps3/an524/tfm_peripherals_def.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __TFM_PERIPHERALS_DEF_H__
+#define __TFM_PERIPHERALS_DEF_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct tfm_spm_partition_platform_data_t;
+
+extern struct tfm_spm_partition_platform_data_t tfm_peripheral_std_uart;
+
+#define TFM_PERIPHERAL_STD_UART (&tfm_peripheral_std_uart)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TFM_PERIPHERALS_DEF_H__ */
diff --git a/readme.rst b/readme.rst
index 8ec61f9..f63f9b9 100644
--- a/readme.rst
+++ b/readme.rst
@@ -94,6 +94,8 @@
<https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board>`__
- `Musca-B1 test chip board.
<https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-b-test-chip-board>`__
+ - `FPGA image loaded on MPS3 board.
+ <https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3>`__
- Cortex M23 based IoT Kit system:
diff --git a/test/suites/sst/CMakeLists.inc b/test/suites/sst/CMakeLists.inc
index 407f16b..5dee18f 100644
--- a/test/suites/sst/CMakeLists.inc
+++ b/test/suites/sst/CMakeLists.inc
@@ -45,10 +45,10 @@
set_property(SOURCE ${ALL_SRC_C_NS} APPEND PROPERTY COMPILE_DEFINITIONS TFM_NS_CLIENT_IDENTIFICATION)
endif()
- if (NOT SST_RAM_FS AND NOT REFERENCE_PLATFORM)
+ if (NOT SST_RAM_FS AND NOT (REFERENCE_PLATFORM OR ${TARGET_PLATFORM} STREQUAL "AN524"))
# Show flash warning message only when the RAM FS is not in use or the tests are compiled to
- # be executed in the reference plaforms (AN519 and AN521). The reference platforms use RAM
- # memory to emulated a flash device as they do not have one.
+ # be executed in the reference plaforms (AN519 and AN521) & AN524. The reference platforms and AN524
+ # use RAM memory to emulated a flash device as they do not have one.
set_property(SOURCE ${ALL_SRC_C_S} APPEND PROPERTY COMPILE_DEFINITIONS SST_SHOW_FLASH_WARNING)
set_property(SOURCE ${ALL_SRC_C_NS} APPEND PROPERTY COMPILE_DEFINITIONS SST_SHOW_FLASH_WARNING)
endif()
diff --git a/test/test_services/tfm_secure_client_service/manifest.yaml b/test/test_services/tfm_secure_client_service/manifest.yaml
index ca3cb0e..3293643 100644
--- a/test/test_services/tfm_secure_client_service/manifest.yaml
+++ b/test/test_services/tfm_secure_client_service/manifest.yaml
@@ -54,6 +54,7 @@
"*Driver_USART.*",
"*arm_uart_drv.*", # MPS2-AN521, MPS2-AN519
"*uart_pl011_drv.*", # Musca-A, Musca-B1
+ "*uart_cmsdk_drv*", # MPS3-AN524
"*secure_suites.*",
"*attestation_s_interface_testsuite.*"
]