SPM: Rename partition metadata config
Rename partition metadata config from TFM_SP_META_PTR_ENABLE to
CONFIG_TFM_PARTITION_META to align with tfm config pattern.
Signed-off-by: Summer Qin <summer.qin@arm.com>
Change-Id: If269c672029c91c466be8a8bae92aa44a6f3ed9a
diff --git a/config/check_config.cmake b/config/check_config.cmake
index af0fae7..f18ef40 100644
--- a/config/check_config.cmake
+++ b/config/check_config.cmake
@@ -81,7 +81,7 @@
####################### SP META Pointer ########################################
-tfm_invalid_config(TFM_SP_META_PTR_ENABLE AND TFM_LIB_MODEL)
+tfm_invalid_config(CONFIG_TFM_PARTITION_META AND TFM_LIB_MODEL)
####################### Firmware Update Parttion ###############################
diff --git a/config/config_default.cmake b/config/config_default.cmake
index d233475..719dea7 100755
--- a/config/config_default.cmake
+++ b/config/config_default.cmake
@@ -46,7 +46,7 @@
set(TFM_DEBUG_SYMBOLS ON CACHE BOOL "Add debug symbols. Note that setting CMAKE_BUILD_TYPE to Debug or RelWithDebInfo will also add debug symbols.")
set(TFM_CODE_COVERAGE OFF CACHE BOOL "Whether to build the binary for lcov tools")
-set(TFM_SP_META_PTR_ENABLE OFF CACHE BOOL "Use Partition Metadata Pointer")
+set(CONFIG_TFM_PARTITION_META OFF CACHE BOOL "Use Partition Metadata Pointer")
set(TFM_PXN_ENABLE OFF CACHE BOOL "Use Privileged execute never (PXN)")
diff --git a/interface/CMakeLists.txt b/interface/CMakeLists.txt
index 14594ce..65e01ec 100644
--- a/interface/CMakeLists.txt
+++ b/interface/CMakeLists.txt
@@ -51,7 +51,7 @@
$<$<BOOL:${TFM_ISOLATION_LEVEL}>:TFM_LVL=${TFM_ISOLATION_LEVEL}>
$<$<BOOL:${TFM_MULTI_CORE_TOPOLOGY}>:TFM_MULTI_CORE_TOPOLOGY>
$<$<BOOL:${FORWARD_PROT_MSG}>:FORWARD_PROT_MSG=${FORWARD_PROT_MSG}>
- $<$<BOOL:${TFM_SP_META_PTR_ENABLE}>:TFM_SP_META_PTR_ENABLE>
+ $<$<BOOL:${CONFIG_TFM_PARTITION_META}>:CONFIG_TFM_PARTITION_META>
$<$<BOOL:${CONFIG_TFM_PSA_API_SUPERVISOR_CALL}>:CONFIG_TFM_PSA_API_SUPERVISOR_CALL>
$<$<BOOL:${CONFIG_TFM_PSA_API_CROSS_CALL}>:CONFIG_TFM_PSA_API_CROSS_CALL>
$<$<BOOL:${CONFIG_TFM_PSA_API_SFN_CALL}>:CONFIG_TFM_PSA_API_SFN_CALL>
diff --git a/platform/ext/common/armclang/tfm_common_s.sct b/platform/ext/common/armclang/tfm_common_s.sct
index 6b6398b..9590685 100644
--- a/platform/ext/common/armclang/tfm_common_s.sct
+++ b/platform/ext/common/armclang/tfm_common_s.sct
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -156,7 +156,7 @@
}
#endif /* !defined(TFM_PSA_API) */
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
TFM_SP_META_PTR +0 ALIGN 32 {
*(SP_META_PTR_SPRTL_INST)
}
diff --git a/platform/ext/common/gcc/tfm_common_s.ld b/platform/ext/common/gcc/tfm_common_s.ld
index 894c525..88456f0 100644
--- a/platform/ext/common/gcc/tfm_common_s.ld
+++ b/platform/ext/common/gcc/tfm_common_s.ld
@@ -125,7 +125,7 @@
LONG (PSA_PROXY_SHARED_MEMORY_BASE)
LONG (PSA_PROXY_SHARED_MEMORY_SIZE)
#endif
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
LONG (ADDR(.TFM_SP_META_PTR))
LONG (SIZEOF(.TFM_SP_META_PTR))
#endif
@@ -304,7 +304,7 @@
} > RAM
#endif /* TFM_LVL == 1 */
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
.TFM_SP_META_PTR : ALIGN(32)
{
*(SP_META_PTR_SPRTL_INST)
diff --git a/platform/ext/common/iar/tfm_common_s.icf b/platform/ext/common/iar/tfm_common_s.icf
index c9ea5a3..50f90c6 100644
--- a/platform/ext/common/iar/tfm_common_s.icf
+++ b/platform/ext/common/iar/tfm_common_s.icf
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
* Copyright (c) 2020-2021 IAR Systems AB
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -126,8 +126,8 @@
keep {block TFM_SECURE_STACK};
#endif /* !defined(TFM_PSA_API) */
-#if defined(TFM_SP_META_PTR_ENABLE)
-define block TFM_SP_META_PTR_ENABLE with alignment = 32 {
+#if defined(CONFIG_TFM_PARTITION_META)
+define block CONFIG_TFM_PARTITION_META with alignment = 32 {
section SP_META_PTR_SPRTL_INST
};
#endif
@@ -301,7 +301,7 @@
block TFM_SECURE_STACK,
#endif /* !defined(TFM_PSA_API) */
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
block TFM_SP_META_PTR,
#endif
diff --git a/platform/ext/common/tfm_hal_memory_symbols.c b/platform/ext/common/tfm_hal_memory_symbols.c
index dcd632b..3cbea4d 100644
--- a/platform/ext/common/tfm_hal_memory_symbols.c
+++ b/platform/ext/common/tfm_hal_memory_symbols.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -8,7 +8,7 @@
#include <stdint.h>
#include "region.h"
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
diff --git a/platform/ext/target/arm/corstone1000/tfm_hal_isolation.c b/platform/ext/target/arm/corstone1000/tfm_hal_isolation.c
index 8cb0895..95d50c7 100644
--- a/platform/ext/target/arm/corstone1000/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/corstone1000/tfm_hal_isolation.c
@@ -20,10 +20,10 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
static void configure_mpu(uint32_t rnr, uint32_t base, uint32_t limit,
@@ -71,7 +71,7 @@
configure_mpu(rnr++, base, limit, XN_EXEC_NOT_OK, AP_RW_PRIV_UNPRIV);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
base = (uint32_t)®ION_NAME(Image$$, TFM_SP_META_PTR, $$RW$$Base);
limit = (uint32_t)®ION_NAME(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
diff --git a/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c
index 1759d86..3134a6b 100644
--- a/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps2/an519/tfm_hal_isolation.c
@@ -34,10 +34,10 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
const struct mpu_armv8m_region_cfg_t region_cfg[] = {
/* Veneer region */
@@ -80,7 +80,7 @@
MPU_ARMV8M_AP_RW_PRIV_UNPRIV,
MPU_ARMV8M_SH_NONE
},
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
{
0, /* will be updated before using */
diff --git a/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c b/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c
index 16cb768..c2ab2c5 100644
--- a/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps2/an521/tfm_hal_isolation.c
@@ -65,10 +65,10 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
const struct mpu_armv8m_region_cfg_t region_cfg[] = {
/* Veneer region */
@@ -111,7 +111,7 @@
MPU_ARMV8M_AP_RW_PRIV_UNPRIV,
MPU_ARMV8M_SH_NONE
},
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
{
0, /* will be updated before using */
diff --git a/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c
index 0838290..c926e5a 100644
--- a/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps3/an524/tfm_hal_isolation.c
@@ -31,10 +31,10 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
#endif /* CONFIG_TFM_ENABLE_MEMORY_PROTECT */
enum tfm_hal_status_t tfm_hal_set_up_static_boundaries(void)
@@ -115,7 +115,7 @@
}
n_configured_regions++;
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
region_cfg.region_nr = n_configured_regions;
region_cfg.region_base =
diff --git a/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c
index 7e5d85c..43cf52f 100644
--- a/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps3/an547/tfm_hal_isolation.c
@@ -35,10 +35,10 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
const struct mpu_armv8m_region_cfg_t region_cfg[] = {
/* Veneer region */
@@ -97,7 +97,7 @@
MPU_ARMV8M_PRIV_EXEC_NEVER
#endif
},
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
{
0, /* will be updated before using */
diff --git a/platform/ext/target/arm/mps3/an552/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/an552/tfm_hal_isolation.c
index a094ac5..6b2cd39 100644
--- a/platform/ext/target/arm/mps3/an552/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps3/an552/tfm_hal_isolation.c
@@ -35,10 +35,10 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
const struct mpu_armv8m_region_cfg_t region_cfg[] = {
/* Veneer region */
@@ -97,7 +97,7 @@
MPU_ARMV8M_PRIV_EXEC_NEVER
#endif
},
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
{
0, /* will be updated before using */
diff --git a/platform/ext/target/arm/mps3/corstone_polaris/tfm_hal_isolation.c b/platform/ext/target/arm/mps3/corstone_polaris/tfm_hal_isolation.c
index 657e725..28b5123 100644
--- a/platform/ext/target/arm/mps3/corstone_polaris/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/mps3/corstone_polaris/tfm_hal_isolation.c
@@ -35,10 +35,10 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
const struct mpu_armv8m_region_cfg_t region_cfg[] = {
/* Veneer region */
@@ -97,7 +97,7 @@
MPU_ARMV8M_PRIV_EXEC_NEVER
#endif
},
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
{
0, /* will be updated before using */
diff --git a/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c b/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c
index d59e93b..f43c5c5 100644
--- a/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/musca_b1/sse_200/tfm_hal_isolation.c
@@ -65,7 +65,7 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
#endif
@@ -173,7 +173,7 @@
}
n_configured_regions++;
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
region_cfg.region_nr = n_configured_regions;
region_cfg.region_base =
@@ -188,7 +188,7 @@
return TFM_HAL_ERROR_GENERIC;
}
n_configured_regions++;
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
#endif /* TFM_LVL == 3 */
/* Enable MPU */
diff --git a/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c b/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c
index 207a2bb..df23f56 100644
--- a/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c
+++ b/platform/ext/target/arm/musca_s1/tfm_hal_isolation.c
@@ -34,7 +34,7 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
#endif
@@ -119,7 +119,7 @@
}
n_configured_regions++;
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
region_cfg.region_nr = n_configured_regions;
region_cfg.region_base =
diff --git a/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld b/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld
index 05079d0..b68fdb0 100644
--- a/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld
+++ b/platform/ext/target/nordic_nrf/common/core/gcc/nordic_nrf_s.ld
@@ -167,7 +167,7 @@
LONG (PSA_PROXY_SHARED_MEMORY_BASE)
LONG (PSA_PROXY_SHARED_MEMORY_SIZE)
#endif
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
LONG (ADDR(.TFM_SP_META_PTR))
LONG (SIZEOF(.TFM_SP_META_PTR))
#endif
@@ -397,7 +397,7 @@
} > RAM
#endif /* TFM_LVL == 1 */
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
.TFM_SP_META_PTR : ALIGN(32)
{
*(SP_META_PTR_SPRTL_INST)
diff --git a/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c b/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c
index f6820b9..8ed81db 100644
--- a/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c
+++ b/platform/ext/target/nordic_nrf/common/core/tfm_hal_isolation.c
@@ -24,10 +24,10 @@
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
/* Get address of memory regions to configure MPU */
extern const struct memory_region_limits memory_regions;
@@ -360,7 +360,7 @@
return TFM_HAL_ERROR_GENERIC;
}
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata poniter region */
region_cfg.region_nr = n_configured_regions++;
@@ -378,7 +378,7 @@
if (err != MPU_ARMV8M_OK) {
return TFM_HAL_ERROR_GENERIC;
}
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
mpu_armv8m_enable(&dev_mpu_s, PRIVILEGED_DEFAULT_ENABLE,
HARDFAULT_NMI_ENABLE);
diff --git a/platform/ext/target/nuvoton/common/tfm_hal_isolation.c b/platform/ext/target/nuvoton/common/tfm_hal_isolation.c
index a1cffc0..d2c4778 100644
--- a/platform/ext/target/nuvoton/common/tfm_hal_isolation.c
+++ b/platform/ext/target/nuvoton/common/tfm_hal_isolation.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -21,9 +21,9 @@
#define MPU_REGION_NS_STACK 2
#define PARTITION_REGION_RO 3
#define PARTITION_REGION_RW_STACK 4
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
#define MPU_REGION_SP_META_PTR 7
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
REGION_DECLARE(Image$$, ER_VENEER, $$Base);
REGION_DECLARE(Image$$, VENEER_ALIGN, $$Limit);
@@ -33,10 +33,10 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
const struct mpu_armv8m_region_cfg_t region_cfg[] = {
/* Veneer region */
@@ -79,7 +79,7 @@
MPU_ARMV8M_AP_RW_PRIV_UNPRIV,
MPU_ARMV8M_SH_NONE
},
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
{
MPU_REGION_SP_META_PTR,
diff --git a/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct b/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct
index 017432c..98bd964 100644
--- a/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct
+++ b/platform/ext/target/nuvoton/m2351/device/source/armclang/m2351_s.sct
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -226,7 +226,7 @@
}
#endif /* !defined(TFM_PSA_API) */
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
TFM_SP_META_PTR +0 ALIGN 32 {
*(SP_META_PTR_SPRTL_INST)
}
diff --git a/platform/ext/target/nxp/common/tfm_hal_isolation.c b/platform/ext/target/nxp/common/tfm_hal_isolation.c
index 3f1f0c2..e652a7c 100644
--- a/platform/ext/target/nxp/common/tfm_hal_isolation.c
+++ b/platform/ext/target/nxp/common/tfm_hal_isolation.c
@@ -67,7 +67,7 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
#endif
@@ -219,7 +219,7 @@
region_cfg.region_limit);
#endif
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
region_cfg.region_nr = n_configured_regions;
region_cfg.region_base =
@@ -235,7 +235,7 @@
}
n_configured_regions++;
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
#endif /* TFM_LVL == 3 */
/* Enable MPU */
diff --git a/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c b/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c
index 4f9095d..325f243 100644
--- a/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c
+++ b/platform/ext/target/stm/common/stm32l5xx/secure/tfm_hal_isolation.c
@@ -65,10 +65,10 @@
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_END, $$Base);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
const struct mpu_armv8m_region_cfg_t region_cfg[] = {
/* Veneer region */
@@ -111,7 +111,7 @@
MPU_ARMV8M_AP_RW_PRIV_UNPRIV,
MPU_ARMV8M_SH_NONE
},
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
{
0, /* will be updated before using */
diff --git a/platform/ext/target/stm/common/stm32u5xx/Device/Source/armclang/tfm_common_s.sct b/platform/ext/target/stm/common/stm32u5xx/Device/Source/armclang/tfm_common_s.sct
index 29d55e6..3ebdbd5 100644
--- a/platform/ext/target/stm/common/stm32u5xx/Device/Source/armclang/tfm_common_s.sct
+++ b/platform/ext/target/stm/common/stm32u5xx/Device/Source/armclang/tfm_common_s.sct
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -103,7 +103,7 @@
}
#endif /* !defined(TFM_PSA_API) */
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
TFM_SP_META_PTR +0 ALIGN 32 {
*(SP_META_PTR_SPRTL_INST)
}
diff --git a/platform/ext/target/stm/common/stm32u5xx/Device/Source/gcc/tfm_common_s.ld b/platform/ext/target/stm/common/stm32u5xx/Device/Source/gcc/tfm_common_s.ld
index 840cfdc..807ff6e 100644
--- a/platform/ext/target/stm/common/stm32u5xx/Device/Source/gcc/tfm_common_s.ld
+++ b/platform/ext/target/stm/common/stm32u5xx/Device/Source/gcc/tfm_common_s.ld
@@ -91,7 +91,7 @@
LONG (PSA_PROXY_SHARED_MEMORY_BASE)
LONG (PSA_PROXY_SHARED_MEMORY_SIZE)
#endif
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
LONG (ADDR(.TFM_SP_META_PTR))
LONG (SIZEOF(.TFM_SP_META_PTR))
#endif
@@ -167,7 +167,7 @@
Image$$ER_INITIAL_PSP_SEAL$$ZI$$Base = ADDR(.psp_stack_seal_res);
Image$$ER_INITIAL_PSP_SEAL$$ZI$$Limit = ADDR(.psp_stack_seal_res) + SIZEOF(.psp_stack_seal_res);
# endif
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
.TFM_SP_META_PTR : ALIGN(32)
{
*(SP_META_PTR_SPRTL_INST)
diff --git a/platform/ext/target/stm/common/stm32u5xx/Device/Source/iar/tfm_common_s.icf b/platform/ext/target/stm/common/stm32u5xx/Device/Source/iar/tfm_common_s.icf
index 84e501c..bc17c73 100644
--- a/platform/ext/target/stm/common/stm32u5xx/Device/Source/iar/tfm_common_s.icf
+++ b/platform/ext/target/stm/common/stm32u5xx/Device/Source/iar/tfm_common_s.icf
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2022 Arm Limited. All rights reserved.
* Copyright (c) 2020-2021 IAR Systems AB
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -94,8 +94,8 @@
keep {block TFM_SECURE_STACK};
#endif /* !defined(TFM_PSA_API) */
-#if defined(TFM_SP_META_PTR_ENABLE)
-define block TFM_SP_META_PTR_ENABLE with alignment = 32 {
+#if defined(CONFIG_TFM_PARTITION_META)
+define block CONFIG_TFM_PARTITION_META with alignment = 32 {
section SP_META_PTR_SPRTL_INST
};
#endif
@@ -222,7 +222,7 @@
block TFM_SECURE_STACK,
#endif /* !defined(TFM_PSA_API) */
-#if defined(TFM_SP_META_PTR_ENABLE)
+#if defined(CONFIG_TFM_PARTITION_META)
block TFM_SP_META_PTR,
#endif
diff --git a/platform/include/tfm_hal_memory_symbols.h b/platform/include/tfm_hal_memory_symbols.h
index 6862549..3271329 100644
--- a/platform/include/tfm_hal_memory_symbols.h
+++ b/platform/include/tfm_hal_memory_symbols.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -10,7 +10,7 @@
#include <stdint.h>
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
extern uintptr_t hal_mem_sp_meta_start;
extern uintptr_t hal_mem_sp_meta_end;
#endif
diff --git a/secure_fw/partitions/lib/sprt/CMakeLists.txt b/secure_fw/partitions/lib/sprt/CMakeLists.txt
index a895d26..a76bd05 100644
--- a/secure_fw/partitions/lib/sprt/CMakeLists.txt
+++ b/secure_fw/partitions/lib/sprt/CMakeLists.txt
@@ -1,5 +1,5 @@
#-------------------------------------------------------------------------------
-# Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+# Copyright (c) 2020-2022, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -23,7 +23,7 @@
./crt_memset.c
./crt_strnlen.c
./service_api.c
- $<$<BOOL:${TFM_SP_META_PTR_ENABLE}>:./sprt_partition_metadata_indicator.c>
+ $<$<BOOL:${CONFIG_TFM_PARTITION_META}>:./sprt_partition_metadata_indicator.c>
)
target_link_libraries(tfm_sprt
diff --git a/secure_fw/spm/cmsis_psa/tfm_multi_core_mem_check.c b/secure_fw/spm/cmsis_psa/tfm_multi_core_mem_check.c
index d0ebd81..9752d66 100644
--- a/secure_fw/spm/cmsis_psa/tfm_multi_core_mem_check.c
+++ b/secure_fw/spm/cmsis_psa/tfm_multi_core_mem_check.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -97,10 +97,10 @@
#if TFM_LVL == 2
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Base);
REGION_DECLARE(Image$$, TFM_UNPRIV_CODE, $$RO$$Limit);
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Base);
REGION_DECLARE(Image$$, TFM_SP_META_PTR, $$RW$$Limit);
-#endif /* TFM_SP_META_PTR_ENABLE */
+#endif /* CONFIG_TFM_PARTITION_META */
REGION_DECLARE(Image$$, TFM_APP_CODE_START, $$Base);
REGION_DECLARE(Image$$, TFM_APP_CODE_END, $$Base);
REGION_DECLARE(Image$$, TFM_APP_RW_STACK_START, $$Base);
@@ -151,7 +151,7 @@
return;
}
-#ifdef TFM_SP_META_PTR_ENABLE
+#ifdef CONFIG_TFM_PARTITION_META
/* TFM partition metadata pointer region */
base = (uintptr_t)®ION_NAME(Image$$, TFM_SP_META_PTR, $$RW$$Base);
limit = (uintptr_t)®ION_NAME(Image$$, TFM_SP_META_PTR, $$RW$$Limit) - 1;