Platform: Add mps3/an547 platform
Add support for AN547, an MPS3 FPGA platform based on Corstone SSE-300
with Ethos-U55, and unify it with the already existing support of
Corstone-300 Ethos-U55 Ecosystem FVP.
Change-Id: I9cbb0167e61244214a8eeb5a55165c296af03ef7
Signed-off-by: Gabor Toth <gabor.toth@arm.com>
diff --git a/docs/getting_started/tfm_integration_guide.rst b/docs/getting_started/tfm_integration_guide.rst
index 9c95856..6ab7a19 100644
--- a/docs/getting_started/tfm_integration_guide.rst
+++ b/docs/getting_started/tfm_integration_guide.rst
@@ -27,6 +27,7 @@
- Musca-B1 test chip board (Cortex-M33 SSE-200 subsystem)
- Musca-S1 test chip board (Cortex-M33 SSE-200 subsystem)
- CoreLink SSE-200 Subsystem for MPS3 (AN524)
+- Corstone SSE-300 with Ethos-U55 Example Subsystem for MPS3 (AN547)
- STM32L5xx: Cortex-M33 based platform (STM32L562 and STM32L552 socs)
- nRF9160 DK (Cortex-M33)
- nRF5340 PDK/DK (Cortex-M33 Application MCU)
@@ -40,6 +41,9 @@
More information about subsystems supported by the MPS2+ board can be found in:
`MPS2+ homepage <https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2>`__
+More information about subsystems supported by the MPS3 board can be found in:
+`MPS3 homepage <https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps3>`__
+
More information about the Musca-A test chip board can be found in:
`Musca-A homepage <https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board>`__
diff --git a/docs/getting_started/tfm_secure_boot.rst b/docs/getting_started/tfm_secure_boot.rst
index 82c1381..3b1d8b7 100644
--- a/docs/getting_started/tfm_secure_boot.rst
+++ b/docs/getting_started/tfm_secure_boot.rst
@@ -246,6 +246,8 @@
+---------------------+-----------------+---------------+----------+----------------+--------------+
| AN524 | Yes | No | No | Yes | No |
+---------------------+-----------------+---------------+----------+----------------+--------------+
+| AN547 | No | Yes | Yes | Yes | No |
++---------------------+-----------------+---------------+----------+----------------+--------------+
| PSoC64 | Yes | No | No | No | No |
+---------------------+-----------------+---------------+----------+----------------+--------------+
| STM_DISCO_L562QE | No | Yes | No | No | No |
diff --git a/docs/introduction/readme.rst b/docs/introduction/readme.rst
index 3f0cc85..10c30cc 100644
--- a/docs/introduction/readme.rst
+++ b/docs/introduction/readme.rst
@@ -116,6 +116,8 @@
###################
- Cortex-M55 system:
+ - `FPGA image loaded on MPS3 board (AN547).
+ <https://developer.arm.com/products/system-design/development-boards/cortex-m-prototyping-systems/mps3>`_
- `Fast model FVP_SSE300_MPS2.
<https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps>`_
diff --git a/platform/ext/target/mps3/fvp_sse300/CMakeLists.txt b/platform/ext/target/mps3/an547/CMakeLists.txt
similarity index 91%
rename from platform/ext/target/mps3/fvp_sse300/CMakeLists.txt
rename to platform/ext/target/mps3/an547/CMakeLists.txt
index 838981d..51e36be 100644
--- a/platform/ext/target/mps3/fvp_sse300/CMakeLists.txt
+++ b/platform/ext/target/mps3/an547/CMakeLists.txt
@@ -18,11 +18,11 @@
#========================= Platform common defs ===============================#
if (${CMAKE_C_COMPILER_ID} STREQUAL GNU)
- message(FATAL_ERROR "GCC is currently not supported on the mps3/fvp_sse300_mps3 because TFM build system does not support the Coretex-M55 with GNUARM")
+ message(FATAL_ERROR "GCC is currently not supported on the mps3/an547 because TFM build system does not support the Coretex-M55 with GNUARM")
endif()
if (${CMAKE_C_COMPILER_ID} STREQUAL IAR)
- message(FATAL_ERROR "IAR is currently not supported on the mps3/fvp_sse300_mps3 due to a lack of scatter files")
+ message(FATAL_ERROR "IAR is currently not supported on the mps3/an547 due to a lack of scatter files")
endif()
if (${CMAKE_C_COMPILER_ID} STREQUAL ARMClang)
@@ -34,7 +34,7 @@
# Specify the location of platform specific build dependencies.
target_sources(tfm_s
PRIVATE
- $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/startup_fvp_sse300_mps3_s.c>
+ $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/startup_an547_s.c>
)
target_add_scatter_file(tfm_s
$<$<C_COMPILER_ID:ARMClang>:${CMAKE_SOURCE_DIR}/platform/ext/common/armclang/tfm_common_s.sct>
@@ -43,10 +43,10 @@
if(NS)
target_sources(tfm_ns
PRIVATE
- $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/startup_fvp_sse300_mps3_ns.c>
+ $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/startup_an547_ns.c>
)
target_add_scatter_file(tfm_ns
- $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/fvp_sse300_mps3_ns.sct>
+ $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/an547_ns.sct>
)
target_link_libraries(CMSIS_5_tfm_ns
INTERFACE
@@ -57,10 +57,10 @@
if(BL2)
target_sources(bl2
PRIVATE
- $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/startup_fvp_sse300_mps3_bl2.c>
+ $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/startup_an547_bl2.c>
)
target_add_scatter_file(bl2
- $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/fvp_sse300_mps3_bl2.sct>
+ $<$<C_COMPILER_ID:ARMClang>:${CMAKE_CURRENT_SOURCE_DIR}/device/source/armclang/an547_bl2.sct>
)
endif()
@@ -85,7 +85,7 @@
target_sources(platform_s
PRIVATE
cmsis_drivers/Driver_Flash.c
- cmsis_drivers/Driver_FVP_SSE300_MPC.c
+ cmsis_drivers/Driver_AN547_MPC.c
cmsis_drivers/Driver_SSE300_PPC.c
cmsis_drivers/Driver_USART.c
device/source/device_definition.c
diff --git a/platform/ext/target/mps3/an547/README.rst b/platform/ext/target/mps3/an547/README.rst
new file mode 100644
index 0000000..65c47ad
--- /dev/null
+++ b/platform/ext/target/mps3/an547/README.rst
@@ -0,0 +1,95 @@
+Corstone-300 Ethos-U55 FPGA and FVP
+===================================
+
+Building TF-M
+-------------
+
+Follow the instructions in Getting started guide / 2. Build instructions with platform name: mps3/an547 (-DTFM_PLATFORM=mps3/an547).
+
+Note
+----
+
+This platform support does not provide software for Ethos-U55 IP, only contains base address and interrupt number for it.
+
+Note
+----
+
+The built binaries can be run on both the Corstone-300 Ethos-U55 Ecosystem FVP (FVP_SSE300_MPS3) and Corstone SSE-300 with
+Ethos-U55 Example Subsystem for MPS3 (AN547).
+
+To run the example code on Corstone SSE-300 with Ethos-U55 Example Subsystem for MPS3 (AN547)
+---------------------------------------------------------------------------------------------
+FPGA image is available to download `here <https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/download-fpga-images>`__
+
+To run BL2 bootloader and TF-M example application and tests in the MPS3 board,
+it is required to have AN547 image in the MPS3 board SD card. The image should
+be located in ``<MPS3 device name>/MB/HBI<BoardNumberBoardrevision>/AN547``
+
+The MPS3 board tested is HBI0309C.
+
+#. Copy ``bl2.bin`` and ``tfm_s_ns_signed.bin`` files from
+ build dir to ``<MPS3 device name>/SOFTWARE/``
+#. Rename ``tfm_s_ns_signed.bin`` to ``tfm.bin`` (Filename should not be longer
+ than 8 charachters.)
+#. Open ``<MPS3 device name>/MB/HBI0309C/AN547/images.txt``
+#. Update the ``images.txt`` file as follows::
+
+ TITLE: Arm MPS3 FPGA prototyping board Images Configuration File
+
+ [IMAGES]
+ TOTALIMAGES: 2 ;Number of Images (Max: 32)
+
+ IMAGE0UPDATE: AUTO ;Image Update:NONE/AUTO/FORCE
+ IMAGE0ADDRESS: 0x00000000 ;Please select the required executable program
+ IMAGE0FILE: \SOFTWARE\bl2.bin
+ IMAGE1UPDATE: AUTO
+ IMAGE1ADDRESS: 0x02000000
+ IMAGE1FILE: \SOFTWARE\tfm.bin
+
+#. Close ``<MPS3 device name>/MB/HBI0309C/AN547/images.txt``
+#. Unmount/eject the ``<MPS3 device name>`` unit
+#. Reset the board to execute the TF-M example application
+#. After completing the procedure you should be able to visualize on the serial
+ port (baud 115200 8n1) the following messages::
+
+ [INF] Swap type: none
+ [INF] Swap type: none
+ [INF] Bootloader chainload address offset: 0x0
+ [INF] Jumping to the first image slot
+ [Sec Thread] Secure image initializing!
+ TF-M isolation level is: 0x00000001
+ Booting TFM v1.2.0
+ Jumping to non-secure code...
+ Non-Secure system starting...
+
+To run the example code on Corstone-300 Ethos-U55 Ecosystem FVP
+---------------------------------------------------------------
+FVP is available to download `here <https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps>`__
+
+#. Install the FVP
+#. Copy ``bl2.axf`` and ``tfm_s_ns_signed.bin`` files from
+ build dir to ``<FVP installation path>/models/Linux64_GCC-6.4/``
+#. Navigate to the same directory and execute the following command to start FVP:
+
+ ./FVP_MPS3_Corstone_SSE-300 -a cpu0*="bl2.axf" --data "tfm_s_ns_signed.bin"@0x01000000
+
+#. After completing the procedure you should be able to visualize on the serial
+ port the following messages::
+
+ Trying 127.0.0.1...
+ Connected to localhost.
+ Escape character is '^]'.
+ [INF] Starting bootloader
+ [INF] Swap type: none
+ [INF] Swap type: none
+ [INF] Bootloader chainload address offset: 0x0
+ [INF] Jumping to the first image slot
+ [Sec Thread] Secure image initializing!
+ TF-M isolation level is: 0x00000001
+ Booting TFM v1.2.0
+ Jumping to non-secure code...
+ Non-Secure system starting...
+
+-------------
+
+*Copyright (c) 2020-2021, Arm Limited. All rights reserved.*
diff --git a/platform/ext/target/mps3/fvp_sse300/boot_hal.c b/platform/ext/target/mps3/an547/boot_hal.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/boot_hal.c
rename to platform/ext/target/mps3/an547/boot_hal.c
diff --git a/platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_FVP_SSE300_MPC.c b/platform/ext/target/mps3/an547/cmsis_drivers/Driver_AN547_MPC.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_FVP_SSE300_MPC.c
rename to platform/ext/target/mps3/an547/cmsis_drivers/Driver_AN547_MPC.c
diff --git a/platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_Flash.c b/platform/ext/target/mps3/an547/cmsis_drivers/Driver_Flash.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_Flash.c
rename to platform/ext/target/mps3/an547/cmsis_drivers/Driver_Flash.c
diff --git a/platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_SSE300_PPC.c b/platform/ext/target/mps3/an547/cmsis_drivers/Driver_SSE300_PPC.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_SSE300_PPC.c
rename to platform/ext/target/mps3/an547/cmsis_drivers/Driver_SSE300_PPC.c
diff --git a/platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_SSE300_PPC.h b/platform/ext/target/mps3/an547/cmsis_drivers/Driver_SSE300_PPC.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_SSE300_PPC.h
rename to platform/ext/target/mps3/an547/cmsis_drivers/Driver_SSE300_PPC.h
diff --git a/platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_USART.c b/platform/ext/target/mps3/an547/cmsis_drivers/Driver_USART.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/cmsis_drivers/Driver_USART.c
rename to platform/ext/target/mps3/an547/cmsis_drivers/Driver_USART.c
diff --git a/platform/ext/target/mps3/fvp_sse300/cmsis_drivers/config/RTE_Device.h b/platform/ext/target/mps3/an547/cmsis_drivers/config/RTE_Device.h
similarity index 83%
rename from platform/ext/target/mps3/fvp_sse300/cmsis_drivers/config/RTE_Device.h
rename to platform/ext/target/mps3/an547/cmsis_drivers/config/RTE_Device.h
index 9d9d143..ef808ce 100644
--- a/platform/ext/target/mps3/fvp_sse300/cmsis_drivers/config/RTE_Device.h
+++ b/platform/ext/target/mps3/an547/cmsis_drivers/config/RTE_Device.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -62,6 +62,16 @@
#define RTE_PPC_SSE300_MAIN_EXP1 1
// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP1]
+// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP2]
+// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP2 in component ::Drivers:PPC
+#define RTE_PPC_SSE300_MAIN_EXP2 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP2]
+
+// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_MAIN_EXP3]
+// <i> Configuration settings for Driver_PPC_SSE300_MAIN_EXP3 in component ::Drivers:PPC
+#define RTE_PPC_SSE300_MAIN_EXP3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_MAIN_EXP3]
+
// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH0]
// <i> Configuration settings for Driver_PPC_SSE300_PERIPH0 in component ::Drivers:PPC
#define RTE_PPC_SSE300_PERIPH0 1
@@ -87,6 +97,10 @@
#define RTE_PPC_SSE300_PERIPH_EXP2 1
// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP2]
+// <e> PPC (Peripheral Protection Controller) [PPC_SSE300_PERIPH_EXP3]
+// <i> Configuration settings for Driver_PPC_SSE300_PERIPH_EXP3 in component ::Drivers:PPC
+#define RTE_PPC_SSE300_PERIPH_EXP3 1
+// </e> PPC (Peripheral Protection Controller) [Driver_PPC_SSE300_PERIPH_EXP3]
// <e> Flash device emulated by SRAM [Driver_Flash0]
// <i> Configuration settings for Driver_Flash0 in component ::Drivers:Flash
#define RTE_FLASH0 1
diff --git a/platform/ext/target/mps3/fvp_sse300/cmsis_drivers/config/cmsis_driver_config.h b/platform/ext/target/mps3/an547/cmsis_drivers/config/cmsis_driver_config.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/cmsis_drivers/config/cmsis_driver_config.h
rename to platform/ext/target/mps3/an547/cmsis_drivers/config/cmsis_driver_config.h
diff --git a/platform/ext/target/mps3/fvp_sse300/config.cmake b/platform/ext/target/mps3/an547/config.cmake
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/config.cmake
rename to platform/ext/target/mps3/an547/config.cmake
diff --git a/platform/ext/target/mps3/fvp_sse300/device/config/device_cfg.h b/platform/ext/target/mps3/an547/device/config/device_cfg.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/device/config/device_cfg.h
rename to platform/ext/target/mps3/an547/device/config/device_cfg.h
diff --git a/platform/ext/target/mps3/fvp_sse300/device/include/cmsis.h b/platform/ext/target/mps3/an547/device/include/cmsis.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/device/include/cmsis.h
rename to platform/ext/target/mps3/an547/device/include/cmsis.h
diff --git a/platform/ext/target/mps3/fvp_sse300/device/include/device_definition.h b/platform/ext/target/mps3/an547/device/include/device_definition.h
similarity index 91%
rename from platform/ext/target/mps3/fvp_sse300/device/include/device_definition.h
rename to platform/ext/target/mps3/an547/device/include/device_definition.h
index cd93365..754f8dd 100644
--- a/platform/ext/target/mps3/fvp_sse300/device/include/device_definition.h
+++ b/platform/ext/target/mps3/an547/device/include/device_definition.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -45,47 +45,47 @@
#ifdef UART1_CMSDK_S
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART1_DEV_S;
+extern struct uart_cmsdk_dev_t UART1_CMSDK_DEV_S;
#endif
#ifdef UART1_CMSDK_NS
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART1_DEV_NS;
+extern struct uart_cmsdk_dev_t UART1_CMSDK_DEV_NS;
#endif
#ifdef UART2_CMSDK_S
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART2_DEV_S;
+extern struct uart_cmsdk_dev_t UART2_CMSDK_DEV_S;
#endif
#ifdef UART2_CMSDK_NS
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART2_DEV_NS;
+extern struct uart_cmsdk_dev_t UART2_CMSDK_DEV_NS;
#endif
#ifdef UART3_CMSDK_S
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART3_DEV_S;
+extern struct uart_cmsdk_dev_t UART3_CMSDK_DEV_S;
#endif
#ifdef UART3_CMSDK_NS
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART3_DEV_NS;
+extern struct uart_cmsdk_dev_t UART3_CMSDK_DEV_NS;
#endif
#ifdef UART4_CMSDK_S
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART4_DEV_S;
+extern struct uart_cmsdk_dev_t UART4_CMSDK_DEV_S;
#endif
#ifdef UART4_CMSDK_NS
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART4_DEV_NS;
+extern struct uart_cmsdk_dev_t UART4_CMSDK_DEV_NS;
#endif
#ifdef UART5_CMSDK_S
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART5_DEV_S;
+extern struct uart_cmsdk_dev_t UART5_CMSDK_DEV_S;
#endif
#ifdef UART5_CMSDK_NS
#include "uart_cmsdk_drv.h"
-extern struct uart_cmsdk_dev_t ARM_UART5_DEV_NS;
+extern struct uart_cmsdk_dev_t UART5_CMSDK_DEV_NS;
#endif
/* ARM PPC driver structures */
diff --git a/platform/ext/target/mps3/fvp_sse300/device/include/platform_description.h b/platform/ext/target/mps3/an547/device/include/platform_description.h
similarity index 92%
rename from platform/ext/target/mps3/fvp_sse300/device/include/platform_description.h
rename to platform/ext/target/mps3/an547/device/include/platform_description.h
index 8ec0197..6800c05 100644
--- a/platform/ext/target/mps3/fvp_sse300/device/include/platform_description.h
+++ b/platform/ext/target/mps3/an547/device/include/platform_description.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited
+ * Copyright (c) 2019-2021 Arm Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -20,6 +20,7 @@
#include "cmsis.h"
#include "platform_base_address.h"
#include "platform_regs.h"
+#include "platform_pins.h"
#include "system_core_init.h"
#endif /* __PLATFORM_DESCRIPTION_H__ */
diff --git a/platform/ext/target/mps3/fvp_sse300/device/include/platform_irq.h b/platform/ext/target/mps3/an547/device/include/platform_irq.h
similarity index 84%
rename from platform/ext/target/mps3/fvp_sse300/device/include/platform_irq.h
rename to platform/ext/target/mps3/an547/device/include/platform_irq.h
index 8a64ea7..ae706ba 100644
--- a/platform/ext/target/mps3/fvp_sse300/device/include/platform_irq.h
+++ b/platform/ext/target/mps3/an547/device/include/platform_irq.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -28,38 +28,40 @@
DebugMonitor_IRQn = -4, /* Debug Monitor Interrupt */
PendSV_IRQn = -2, /* Pend SV Interrupt */
SysTick_IRQn = -1, /* System Tick Interrupt */
- NONSEC_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset
- * Interrupt
+ NONSEC_WATCHDOG_RESET_REQ_IRQn = 0, /* Non-Secure Watchdog Reset
+ * Request Interrupt
*/
NONSEC_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */
- S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */
+ SLOWCLK_TIMER_IRQn = 2, /* SLOWCLK Timer Interrupt */
TIMER0_IRQn = 3, /* TIMER 0 Interrupt */
TIMER1_IRQn = 4, /* TIMER 1 Interrupt */
- DUALTIMER_IRQn = 5, /* Dual Timer Interrupt */
- MHU0_IRQn = 6, /* Message Handling Unit 0 */
- MHU1_IRQn = 7, /* Message Handling Unit 1 */
+ TIMER2_IRQn = 5, /* TIMER 2 Interrupt */
+ /* Reserved = 6, Reserved */
+ /* Reserved = 7, Reserved */
+ /* Reserved = 8, Reserved */
MPC_IRQn = 9, /* MPC Combined (Secure) Interrupt */
PPC_IRQn = 10, /* PPC Combined (Secure) Interrupt */
MSC_IRQn = 11, /* MSC Combined (Secure) Interrput */
BRIDGE_ERROR_IRQn = 12, /* Bridge Error Combined
* (Secure) Interrupt
*/
- INVALID_INSTR_CACHE_IRQn = 13, /* CPU Instruction Cache Invalidation
- * Interrupt
- */
+ /* Reserved = 13, Reserved */
+ MGMT_PPU_IRQn = 14, /* MGMT PPU */
SYS_PPU_IRQn = 15, /* SYS PPU */
CPU0_PPU_IRQn = 16, /* CPU0 PPU */
- CPU1_PPU_IRQn = 17, /* CPU1 PPU */
- CPU0_DBG_PPU_IRQn = 18, /* CPU0 DBG PPU */
- CPU1_DBG_PPU_IRQn = 19, /* CPU1 DBG PPU */
+ /* Reserved = 17, Reserved */
+ /* Reserved = 18, Reserved */
+ /* Reserved = 19, Reserved */
/* Reserved = 20, Reserved */
- RAM0_PPU_IRQn = 22, /* RAM0 PPU */
- RAM1_PPU_IRQn = 23, /* RAM1 PPU */
- RAM2_PPU_IRQn = 24, /* RAM2 PPU */
- RAM3_PPU_IRQn = 25, /* RAM3 PPU */
+ /* Reserved = 21, Reserved */
+ /* Reserved = 22, Reserved */
+ /* Reserved = 23, Reserved */
+ /* Reserved = 24, Reserved */
+ /* Reserved = 25, Reserved */
DEBUG_PPU_IRQn = 26, /* DEBUG PPU */
- CPUx_CTI_IRQ0 = 28, /* CPUx CTI 0 */
- CPUx_CTI_IRQ1 = 29, /* CPUx CTI 1 */
+ TIMER3_AON_IRQn = 27, /* TIMER 3 AON Interrupt */
+ CPU0_CTI_0_IRQn = 28, /* CPU0 CTI IRQ 0 */
+ CPU0_CTI_1_IRQn = 29, /* CPU0 CTI IRQ 1 */
/* Reserved = 30, Reserved */
/* Reserved = 31, Reserved */
System_Timestamp_Counter_IRQn = 32, /* System timestamp counter Interrupt */
diff --git a/platform/ext/target/mps3/an547/device/include/platform_pins.h b/platform/ext/target/mps3/an547/device/include/platform_pins.h
new file mode 100644
index 0000000..f5eda8c
--- /dev/null
+++ b/platform/ext/target/mps3/an547/device/include/platform_pins.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file platform_pins.h
+ * \brief This file defines all the pins for this platform.
+ */
+
+#ifndef __PLATFORM_PINS_H__
+#define __PLATFORM_PINS_H__
+
+/* AHB GPIO pin names */
+enum arm_gpio_pin_name_t {
+ AHB_GPIO0_0 = 0U,
+ AHB_GPIO0_1,
+ AHB_GPIO0_2,
+ AHB_GPIO0_3,
+ AHB_GPIO0_4,
+ AHB_GPIO0_5,
+ AHB_GPIO0_6,
+ AHB_GPIO0_7,
+ AHB_GPIO0_8,
+ AHB_GPIO0_9,
+ AHB_GPIO0_10,
+ AHB_GPIO0_11,
+ AHB_GPIO0_12,
+ AHB_GPIO0_13,
+ AHB_GPIO0_14,
+ AHB_GPIO0_15,
+ AHB_GPIO1_0 = 0U,
+ AHB_GPIO1_1,
+ AHB_GPIO1_2,
+ AHB_GPIO1_3,
+ AHB_GPIO1_4,
+ AHB_GPIO1_5,
+ AHB_GPIO1_6,
+ AHB_GPIO1_7,
+ AHB_GPIO1_8,
+ AHB_GPIO1_9,
+ AHB_GPIO1_10,
+ AHB_GPIO1_11,
+ AHB_GPIO1_12,
+ AHB_GPIO1_13,
+ AHB_GPIO1_14,
+ AHB_GPIO1_15,
+ AHB_GPIO2_0 = 0U,
+ AHB_GPIO2_1,
+ AHB_GPIO2_2,
+ AHB_GPIO2_3,
+ AHB_GPIO2_4,
+ AHB_GPIO2_5,
+ AHB_GPIO2_6,
+ AHB_GPIO2_7,
+ AHB_GPIO2_8,
+ AHB_GPIO2_9,
+ AHB_GPIO2_10,
+ AHB_GPIO2_11,
+ AHB_GPIO2_12,
+ AHB_GPIO2_13,
+ AHB_GPIO2_14,
+ AHB_GPIO2_15,
+ AHB_GPIO3_0 = 0U,
+ AHB_GPIO3_1,
+ AHB_GPIO3_2,
+ AHB_GPIO3_3,
+ AHB_GPIO3_4,
+ AHB_GPIO3_5,
+ AHB_GPIO3_6,
+ AHB_GPIO3_7,
+ AHB_GPIO3_8,
+ AHB_GPIO3_9,
+ AHB_GPIO3_10,
+ AHB_GPIO3_11,
+ AHB_GPIO3_12,
+ AHB_GPIO3_13,
+ AHB_GPIO3_14,
+ AHB_GPIO3_15,
+};
+
+/* GPIO shield 0 definition */
+#define SH0_UART_RX AHB_GPIO0_0
+#define SH0_UART_TX AHB_GPIO0_1
+#define SH0_SPI_SS AHB_GPIO0_10
+#define SH0_SPI_MOSI AHB_GPIO0_11
+#define SH0_SPI_MISO AHB_GPIO0_12
+#define SH0_SPI_SCK AHB_GPIO0_13
+#define SH0_I2C_SDA AHB_GPIO0_14
+#define SH0_I2C_SCL AHB_GPIO0_15
+
+/* GPIO shield 1 definition */
+#define SH1_UART_RX AHB_GPIO1_0
+#define SH1_UART_TX AHB_GPIO1_1
+
+#define SH1_SPI_SS AHB_GPIO1_10
+#define SH1_SPI_MOSI AHB_GPIO1_11
+#define SH1_SPI_MISO AHB_GPIO1_12
+#define SH1_SPI_SCK AHB_GPIO1_13
+#define SH1_I2C_SDA AHB_GPIO1_14
+#define SH1_I2C_SCL AHB_GPIO1_15
+
+#endif /* __PLATFORM_PINS_H__ */
diff --git a/platform/ext/target/mps3/fvp_sse300/device/include/platform_regs.h b/platform/ext/target/mps3/an547/device/include/platform_regs.h
similarity index 96%
rename from platform/ext/target/mps3/fvp_sse300/device/include/platform_regs.h
rename to platform/ext/target/mps3/an547/device/include/platform_regs.h
index 4c0f522..696d95f 100644
--- a/platform/ext/target/mps3/fvp_sse300/device/include/platform_regs.h
+++ b/platform/ext/target/mps3/an547/device/include/platform_regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited
+ * Copyright (c) 2019-2021 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -21,8 +21,9 @@
/* Secure Access Configuration Register Block */
struct sse300_sacfg_t {
- volatile uint32_t spcsecctrl; /* 0x000 (R/W) Secure Configuration
- * Control Register */
+ volatile uint32_t spcsecctrl; /* 0x000 (R/W) Secure Privilege Controller
+ Secure Configuration Control
+ register */
volatile uint32_t buswait; /* 0x004 (R/W) Bus Access wait control */
volatile uint32_t reserved0[2];
volatile uint32_t secrespcfg; /* 0x010 (R/W) Security Violation Response
@@ -450,17 +451,25 @@
volatile uint32_t ewic_maska; /* 0x200 (R/W) Set which internal events
* cause wakeup */
volatile uint32_t ewic_mask[15]; /* 0x204 (R/W) Set which external
- * interrupts cause wakeup */
+ * interrupts cause wakeup
+ * Only the first (total
+ * system IRQ number)/32
+ * registers are implemented
+ * in array */
volatile uint32_t reserved1[112];
volatile uint32_t ewic_penda; /* 0x400 (R/ ) Shows which internal
* interrupts were pended
* while the EWIC was
* enabled */
- volatile uint32_t ewic_pend[15]; /* 0x404 (R/W) Shows which external
+ volatile uint32_t ewic_pend[15]; /* 0x404 (R/W) Shows which external
* interrupts were pended
* while the EWIC was
- * enabled */
+ * enabled
+ * Only the first (total
+ * system IRQ number)/32
+ * registers are implemented
+ * in array */
volatile uint32_t reserved2[112];
volatile uint32_t ewic_psr; /* 0x600 (R/ ) Pending Summary */
volatile uint32_t reserved3[575];
diff --git a/platform/ext/target/mps3/fvp_sse300/device/include/system_core_init.h b/platform/ext/target/mps3/an547/device/include/system_core_init.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/device/include/system_core_init.h
rename to platform/ext/target/mps3/an547/device/include/system_core_init.h
diff --git a/platform/ext/target/mps3/fvp_sse300/device/source/armclang/fvp_sse300_mps3_bl2.sct b/platform/ext/target/mps3/an547/device/source/armclang/an547_bl2.sct
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/device/source/armclang/fvp_sse300_mps3_bl2.sct
rename to platform/ext/target/mps3/an547/device/source/armclang/an547_bl2.sct
diff --git a/platform/ext/target/mps3/fvp_sse300/device/source/armclang/fvp_sse300_mps3_ns.sct b/platform/ext/target/mps3/an547/device/source/armclang/an547_ns.sct
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/device/source/armclang/fvp_sse300_mps3_ns.sct
rename to platform/ext/target/mps3/an547/device/source/armclang/an547_ns.sct
diff --git a/platform/ext/target/mps3/fvp_sse300/device/source/device_definition.c b/platform/ext/target/mps3/an547/device/source/device_definition.c
similarity index 81%
rename from platform/ext/target/mps3/fvp_sse300/device/source/device_definition.c
rename to platform/ext/target/mps3/an547/device/source/device_definition.c
index 8249e92..4a18c1c 100644
--- a/platform/ext/target/mps3/fvp_sse300/device/source/device_definition.c
+++ b/platform/ext/target/mps3/an547/device/source/device_definition.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -26,8 +26,6 @@
#include "device_definition.h"
#include "platform_base_address.h"
-#define INIT_TO_ZERO_VALUE 0
-
/* UART CMSDK driver structures */
#ifdef UART0_CMSDK_S
static const struct uart_cmsdk_dev_cfg_t UART0_CMSDK_DEV_CFG_S = {
@@ -35,9 +33,9 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_S = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
struct uart_cmsdk_dev_t UART0_CMSDK_DEV_S = {
&(UART0_CMSDK_DEV_CFG_S),
@@ -50,9 +48,9 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART0_CMSDK_DEV_DATA_NS = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
struct uart_cmsdk_dev_t UART0_CMSDK_DEV_NS = {
&(UART0_CMSDK_DEV_CFG_NS),
@@ -66,11 +64,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_S = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART1_DEV_S = {
+struct uart_cmsdk_dev_t UART1_CMSDK_DEV_S = {
&(UART1_CMSDK_DEV_CFG_S),
&(UART1_CMSDK_DEV_DATA_S)
};
@@ -81,11 +79,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART1_CMSDK_DEV_DATA_NS = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART1_DEV_NS = {
+struct uart_cmsdk_dev_t UART1_CMSDK_DEV_NS = {
&(UART1_CMSDK_DEV_CFG_NS),
&(UART1_CMSDK_DEV_DATA_NS)
};
@@ -97,11 +95,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_S = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART2_DEV_S = {
+struct uart_cmsdk_dev_t UART2_CMSDK_DEV_S = {
&(UART2_CMSDK_DEV_CFG_S),
&(UART2_CMSDK_DEV_DATA_S)
};
@@ -112,11 +110,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART2_CMSDK_DEV_DATA_NS = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART2_DEV_NS = {
+struct uart_cmsdk_dev_t UART2_CMSDK_DEV_NS = {
&(UART2_CMSDK_DEV_CFG_NS),
&(UART2_CMSDK_DEV_DATA_NS)
};
@@ -128,11 +126,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_S = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART3_DEV_S = {
+struct uart_cmsdk_dev_t UART3_CMSDK_DEV_S = {
&(UART3_CMSDK_DEV_CFG_S),
&(UART3_CMSDK_DEV_DATA_S)
};
@@ -143,11 +141,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART3_CMSDK_DEV_DATA_NS = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART3_DEV_NS = {
+struct uart_cmsdk_dev_t UART3_CMSDK_DEV_NS = {
&(UART3_CMSDK_DEV_CFG_NS),
&(UART3_CMSDK_DEV_DATA_NS)
};
@@ -159,11 +157,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_S = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART4_DEV_S = {
+struct uart_cmsdk_dev_t UART4_CMSDK_DEV_S = {
&(UART4_CMSDK_DEV_CFG_S),
&(UART4_CMSDK_DEV_DATA_S)
};
@@ -174,11 +172,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART4_CMSDK_DEV_DATA_NS = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART4_DEV_NS = {
+struct uart_cmsdk_dev_t UART4_CMSDK_DEV_NS = {
&(UART4_CMSDK_DEV_CFG_NS),
&(UART4_CMSDK_DEV_DATA_NS)
};
@@ -190,11 +188,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_S = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART5_DEV_S = {
+struct uart_cmsdk_dev_t UART5_CMSDK_DEV_S = {
&(UART5_CMSDK_DEV_CFG_S),
&(UART5_CMSDK_DEV_DATA_S)
};
@@ -205,11 +203,11 @@
.default_baudrate = DEFAULT_UART_BAUDRATE
};
static struct uart_cmsdk_dev_data_t UART5_CMSDK_DEV_DATA_NS = {
- .state = INIT_TO_ZERO_VALUE,
- .system_clk = INIT_TO_ZERO_VALUE,
- .baudrate = INIT_TO_ZERO_VALUE
+ .state = 0,
+ .system_clk = 0,
+ .baudrate = 0
};
-struct uart_cmsdk_dev_t ARM_UART5_DEV_NS = {
+struct uart_cmsdk_dev_t UART5_CMSDK_DEV_NS = {
&(UART5_CMSDK_DEV_CFG_NS),
&(UART5_CMSDK_DEV_DATA_NS)
};
@@ -222,10 +220,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_MAIN0};
static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN0_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_MAIN0_DEV_S = {
&PPC_SSE300_MAIN0_CFG_S,
@@ -238,10 +236,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_MAIN_EXP0};
static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN_EXP0_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_MAIN_EXP0_DEV_S = {
&PPC_SSE300_MAIN_EXP0_CFG_S,
@@ -254,10 +252,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_MAIN_EXP1};
static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN_EXP1_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_MAIN_EXP1_DEV_S = {
&PPC_SSE300_MAIN_EXP1_CFG_S,
@@ -270,10 +268,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_MAIN_EXP2};
static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN_EXP2_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_MAIN_EXP2_DEV_S = {
&PPC_SSE300_MAIN_EXP2_CFG_S,
@@ -286,10 +284,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_MAIN_EXP3};
static struct ppc_sse300_dev_data_t PPC_SSE300_MAIN_EXP3_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_MAIN_EXP3_DEV_S = {
&PPC_SSE300_MAIN_EXP3_CFG_S,
@@ -302,10 +300,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_PERIPH0};
static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH0_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_PERIPH0_DEV_S = {
&PPC_SSE300_PERIPH0_CFG_S,
@@ -318,10 +316,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_PERIPH1};
static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH1_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_PERIPH1_DEV_S = {
&PPC_SSE300_PERIPH1_CFG_S,
@@ -334,10 +332,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_PERIPH_EXP0};
static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH_EXP0_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_PERIPH_EXP0_DEV_S = {
&PPC_SSE300_PERIPH_EXP0_CFG_S,
@@ -350,10 +348,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_PERIPH_EXP1};
static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH_EXP1_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_PERIPH_EXP1_DEV_S = {
&PPC_SSE300_PERIPH_EXP1_CFG_S,
@@ -366,10 +364,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_PERIPH_EXP2};
static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH_EXP2_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_PERIPH_EXP2_DEV_S = {
&PPC_SSE300_PERIPH_EXP2_CFG_S,
@@ -382,10 +380,10 @@
.nsacfg_base = SSE300_NSACFG_BASE_NS,
.ppc_name = PPC_SSE300_PERIPH_EXP3};
static struct ppc_sse300_dev_data_t PPC_SSE300_PERIPH_EXP3_DATA_S = {
- .sacfg_ns_ppc = INIT_TO_ZERO_VALUE,
- .sacfg_sp_ppc = INIT_TO_ZERO_VALUE,
- .nsacfg_nsp_ppc = INIT_TO_ZERO_VALUE,
- .int_bit_mask = INIT_TO_ZERO_VALUE,
+ .sacfg_ns_ppc = 0,
+ .sacfg_sp_ppc = 0,
+ .nsacfg_nsp_ppc = 0,
+ .int_bit_mask = 0,
.is_initialized = false };
struct ppc_sse300_dev_t PPC_SSE300_PERIPH_EXP3_DEV_S = {
&PPC_SSE300_PERIPH_EXP3_CFG_S,
@@ -604,8 +602,8 @@
static const struct mpc_sie_dev_cfg_t MPC_SRAM_DEV_CFG_S = {
.base = MPC_SRAM_BASE_S};
static struct mpc_sie_dev_data_t MPC_SRAM_DEV_DATA_S = {
- .range_list = INIT_TO_ZERO_VALUE,
- .nbr_of_ranges = INIT_TO_ZERO_VALUE,
+ .range_list = 0,
+ .nbr_of_ranges = 0,
.is_initialized = false };
struct mpc_sie_dev_t MPC_SRAM_DEV_S = {
&(MPC_SRAM_DEV_CFG_S),
@@ -616,8 +614,8 @@
static const struct mpc_sie_dev_cfg_t MPC_QSPI_DEV_CFG_S = {
.base = MPC_QSPI_BASE_S};
static struct mpc_sie_dev_data_t MPC_QSPI_DEV_DATA_S = {
- .range_list = INIT_TO_ZERO_VALUE,
- .nbr_of_ranges = INIT_TO_ZERO_VALUE,
+ .range_list = 0,
+ .nbr_of_ranges = 0,
.is_initialized = false };
struct mpc_sie_dev_t MPC_QSPI_DEV_S = {
&(MPC_QSPI_DEV_CFG_S),
@@ -628,8 +626,8 @@
static const struct mpc_sie_dev_cfg_t MPC_DDR4_DEV_CFG_S = {
.base = MPC_DDR4_BASE_S};
static struct mpc_sie_dev_data_t MPC_DDR4_DEV_DATA_S = {
- .range_list = INIT_TO_ZERO_VALUE,
- .nbr_of_ranges = INIT_TO_ZERO_VALUE,
+ .range_list = 0,
+ .nbr_of_ranges = 0,
.is_initialized = false };
struct mpc_sie_dev_t MPC_DDR4_DEV_S = {
&(MPC_DDR4_DEV_CFG_S),
@@ -640,8 +638,8 @@
static const struct mpc_sie_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = {
.base = MPC_ISRAM0_BASE_S};
static struct mpc_sie_dev_data_t MPC_ISRAM0_DEV_DATA_S = {
- .range_list = INIT_TO_ZERO_VALUE,
- .nbr_of_ranges = INIT_TO_ZERO_VALUE,
+ .range_list = 0,
+ .nbr_of_ranges = 0,
.is_initialized = false };
struct mpc_sie_dev_t MPC_ISRAM0_DEV_S = {
&(MPC_ISRAM0_DEV_CFG_S),
@@ -652,8 +650,8 @@
static const struct mpc_sie_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = {
.base = MPC_ISRAM1_BASE_S};
static struct mpc_sie_dev_data_t MPC_ISRAM1_DEV_DATA_S = {
- .range_list = INIT_TO_ZERO_VALUE,
- .nbr_of_ranges = INIT_TO_ZERO_VALUE,
+ .range_list = 0,
+ .nbr_of_ranges = 0,
.is_initialized = false };
struct mpc_sie_dev_t MPC_ISRAM1_DEV_S = {
&(MPC_ISRAM1_DEV_CFG_S),
diff --git a/platform/ext/target/mps3/an547/device/source/startup_an547_bl2.c b/platform/ext/target/mps3/an547/device/source/startup_an547_bl2.c
new file mode 100644
index 0000000..b64ffa0
--- /dev/null
+++ b/platform/ext/target/mps3/an547/device/source/startup_an547_bl2.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "cmsis.h"
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+#define DEFAULT_IRQ_HANDLER(handler_name) \
+void __WEAK handler_name(void); \
+void handler_name(void) { \
+ while(1); \
+}
+
+/* Exceptions */
+DEFAULT_IRQ_HANDLER(NMI_Handler)
+DEFAULT_IRQ_HANDLER(HardFault_Handler)
+DEFAULT_IRQ_HANDLER(MemManage_Handler)
+DEFAULT_IRQ_HANDLER(BusFault_Handler)
+DEFAULT_IRQ_HANDLER(UsageFault_Handler)
+DEFAULT_IRQ_HANDLER(SecureFault_Handler)
+DEFAULT_IRQ_HANDLER(SVC_Handler)
+DEFAULT_IRQ_HANDLER(DebugMon_Handler)
+DEFAULT_IRQ_HANDLER(PendSV_Handler)
+DEFAULT_IRQ_HANDLER(SysTick_Handler)
+
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler)
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
+DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
+DEFAULT_IRQ_HANDLER(TIMER0_Handler)
+DEFAULT_IRQ_HANDLER(TIMER1_Handler)
+DEFAULT_IRQ_HANDLER(TIMER2_Handler)
+DEFAULT_IRQ_HANDLER(MPC_Handler)
+DEFAULT_IRQ_HANDLER(PPC_Handler)
+DEFAULT_IRQ_HANDLER(MSC_Handler)
+DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
+DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
+DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
+DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
+DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler)
+
+DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
+DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
+DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
+DEFAULT_IRQ_HANDLER(I2S_Handler)
+DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
+DEFAULT_IRQ_HANDLER(USB_Handler)
+DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
+DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
+DEFAULT_IRQ_HANDLER(UART5_Handler)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const pFunc __VECTOR_TABLE[496];
+ const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14: NMI Handler */
+ HardFault_Handler, /* -13: Hard Fault Handler */
+ MemManage_Handler, /* -12: MPU Fault Handler */
+ BusFault_Handler, /* -11: Bus Fault Handler */
+ UsageFault_Handler, /* -10: Usage Fault Handler */
+ SecureFault_Handler, /* -9: Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5: SVCall Handler */
+ DebugMon_Handler, /* -4: Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2: PendSV Handler */
+ SysTick_Handler, /* -1: SysTick Handler */
+
+ NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */
+ NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
+ SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
+ TIMER0_Handler, /* 3: TIMER 0 Handler */
+ TIMER1_Handler, /* 4: TIMER 1 Handler */
+ TIMER2_Handler, /* 5: TIMER 2 Handler */
+ 0, /* 6: Reserved */
+ 0, /* 7: Reserved */
+ 0, /* 8: Reserved */
+ MPC_Handler, /* 9: MPC Combined (Secure) Handler */
+ PPC_Handler, /* 10: PPC Combined (Secure) Handler */
+ MSC_Handler, /* 11: MSC Combined (Secure) Handler */
+ BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
+ 0, /* 13: Reserved */
+ MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
+ SYS_PPU_Handler, /* 15: SYS PPU Handler */
+ CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
+ 0, /* 17: Reserved */
+ 0, /* 18: Reserved */
+ 0, /* 19: Reserved */
+ 0, /* 20: Reserved */
+ 0, /* 21: Reserved */
+ 0, /* 22: Reserved */
+ 0, /* 23: Reserved */
+ 0, /* 24: Reserved */
+ 0, /* 25: Reserved */
+ DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
+ TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */
+ CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */
+ CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */
+ 0, /* 30: Reserved */
+ 0, /* 31: Reserved */
+
+ /* External interrupts */
+ System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
+ UARTRX0_Handler, /* 33: UART 0 RX Handler */
+ UARTTX0_Handler, /* 34: UART 0 TX Handler */
+ UARTRX1_Handler, /* 35: UART 1 RX Handler */
+ UARTTX1_Handler, /* 36: UART 1 TX Handler */
+ UARTRX2_Handler, /* 37: UART 2 RX Handler */
+ UARTTX2_Handler, /* 38: UART 2 TX Handler */
+ UARTRX3_Handler, /* 39: UART 3 RX Handler */
+ UARTTX3_Handler, /* 40: UART 3 TX Handler */
+ UARTRX4_Handler, /* 41: UART 4 RX Handler */
+ UARTTX4_Handler, /* 42: UART 4 TX Handler */
+ UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
+ UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
+ UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
+ UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
+ UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
+ UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
+ ETHERNET_Handler, /* 49: Ethernet Handler */
+ I2S_Handler, /* 50: Audio I2S Handler */
+ TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
+ USB_Handler, /* 52: USB Handler */
+ SPI_ADC_Handler, /* 53: SPI ADC Handler */
+ SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
+ SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
+ ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
+ 0, /* 57: Reserved */
+ 0, /* 58: Reserved */
+ 0, /* 59: Reserved */
+ 0, /* 60: Reserved */
+ 0, /* 61: Reserved */
+ 0, /* 62: Reserved */
+ 0, /* 63: Reserved */
+ 0, /* 64: Reserved */
+ 0, /* 65: Reserved */
+ 0, /* 66: Reserved */
+ 0, /* 67: Reserved */
+ 0, /* 68: Reserved */
+ GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
+ GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
+ GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
+ GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
+ GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
+ GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
+ GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
+ GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
+ GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
+ GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
+ GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
+ GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
+ GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
+ GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
+ GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
+ GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
+ GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
+ GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
+ GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
+ GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
+ GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
+ GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
+ GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
+ GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
+ GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
+ GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
+ GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
+ GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
+ GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
+ GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
+ GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
+ GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
+ GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
+ GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
+ GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
+ GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
+ GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
+ GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
+ GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
+ GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
+ GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
+ GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
+ GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
+ GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
+ GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
+ GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
+ GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
+ GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
+ GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
+ GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
+ GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
+ GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
+ GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
+ GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
+ GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
+ GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
+ UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
+ UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
+ UART5_Handler, /* 127: UART 5 combined Interrupt */
+ 0, /* 128: Reserved */
+ 0, /* 129: Reserved */
+ 0, /* 130: Reserved */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
+
+ SystemInit(); /* CMSIS System Initialization */
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
diff --git a/platform/ext/target/mps3/an547/device/source/startup_an547_ns.c b/platform/ext/target/mps3/an547/device/source/startup_an547_ns.c
new file mode 100644
index 0000000..be5d47f
--- /dev/null
+++ b/platform/ext/target/mps3/an547/device/source/startup_an547_ns.c
@@ -0,0 +1,359 @@
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "cmsis.h"
+#include "region.h"
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+
+#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit)
+#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base)
+
+extern uint32_t __MSP_INITIAL_SP;
+extern uint32_t __MSP_STACK_LIMIT;
+
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+#define DEFAULT_IRQ_HANDLER(handler_name) \
+void __WEAK handler_name(void); \
+void handler_name(void) { \
+ while(1); \
+}
+
+/* Exceptions */
+DEFAULT_IRQ_HANDLER(NMI_Handler)
+DEFAULT_IRQ_HANDLER(HardFault_Handler)
+DEFAULT_IRQ_HANDLER(MemManage_Handler)
+DEFAULT_IRQ_HANDLER(BusFault_Handler)
+DEFAULT_IRQ_HANDLER(UsageFault_Handler)
+DEFAULT_IRQ_HANDLER(SecureFault_Handler)
+DEFAULT_IRQ_HANDLER(SVC_Handler)
+DEFAULT_IRQ_HANDLER(DebugMon_Handler)
+DEFAULT_IRQ_HANDLER(PendSV_Handler)
+DEFAULT_IRQ_HANDLER(SysTick_Handler)
+
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler)
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
+DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
+DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler)
+DEFAULT_IRQ_HANDLER(TIMER1_Handler)
+DEFAULT_IRQ_HANDLER(TIMER2_Handler)
+DEFAULT_IRQ_HANDLER(MPC_Handler)
+DEFAULT_IRQ_HANDLER(PPC_Handler)
+DEFAULT_IRQ_HANDLER(MSC_Handler)
+DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
+DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
+DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
+DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
+DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler)
+
+DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
+DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
+DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
+DEFAULT_IRQ_HANDLER(I2S_Handler)
+DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
+DEFAULT_IRQ_HANDLER(USB_Handler)
+DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
+DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
+DEFAULT_IRQ_HANDLER(UART5_Handler)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const pFunc __VECTOR_TABLE[496];
+ const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14: NMI Handler */
+ HardFault_Handler, /* -13: Hard Fault Handler */
+ MemManage_Handler, /* -12: MPU Fault Handler */
+ BusFault_Handler, /* -11: Bus Fault Handler */
+ UsageFault_Handler, /* -10: Usage Fault Handler */
+ SecureFault_Handler, /* -9: Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5: SVCall Handler */
+ DebugMon_Handler, /* -4: Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2: PendSV Handler */
+ SysTick_Handler, /* -1: SysTick Handler */
+
+ NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */
+ NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
+ SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
+ TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */
+ TIMER1_Handler, /* 4: TIMER 1 Handler */
+ TIMER2_Handler, /* 5: TIMER 2 Handler */
+ 0, /* 6: Reserved */
+ 0, /* 7: Reserved */
+ 0, /* 8: Reserved */
+ MPC_Handler, /* 9: MPC Combined (Secure) Handler */
+ PPC_Handler, /* 10: PPC Combined (Secure) Handler */
+ MSC_Handler, /* 11: MSC Combined (Secure) Handler */
+ BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
+ 0, /* 13: Reserved */
+ MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
+ SYS_PPU_Handler, /* 15: SYS PPU Handler */
+ CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
+ 0, /* 17: Reserved */
+ 0, /* 18: Reserved */
+ 0, /* 19: Reserved */
+ 0, /* 20: Reserved */
+ 0, /* 21: Reserved */
+ 0, /* 22: Reserved */
+ 0, /* 23: Reserved */
+ 0, /* 24: Reserved */
+ 0, /* 25: Reserved */
+ DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
+ TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */
+ CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */
+ CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */
+ 0, /* 30: Reserved */
+ 0, /* 31: Reserved */
+
+ /* External interrupts */
+ System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
+ UARTRX0_Handler, /* 33: UART 0 RX Handler */
+ UARTTX0_Handler, /* 34: UART 0 TX Handler */
+ UARTRX1_Handler, /* 35: UART 1 RX Handler */
+ UARTTX1_Handler, /* 36: UART 1 TX Handler */
+ UARTRX2_Handler, /* 37: UART 2 RX Handler */
+ UARTTX2_Handler, /* 38: UART 2 TX Handler */
+ UARTRX3_Handler, /* 39: UART 3 RX Handler */
+ UARTTX3_Handler, /* 40: UART 3 TX Handler */
+ UARTRX4_Handler, /* 41: UART 4 RX Handler */
+ UARTTX4_Handler, /* 42: UART 4 TX Handler */
+ UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
+ UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
+ UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
+ UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
+ UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
+ UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
+ ETHERNET_Handler, /* 49: Ethernet Handler */
+ I2S_Handler, /* 50: Audio I2S Handler */
+ TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
+ USB_Handler, /* 52: USB Handler */
+ SPI_ADC_Handler, /* 53: SPI ADC Handler */
+ SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
+ SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
+ ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
+ 0, /* 57: Reserved */
+ 0, /* 58: Reserved */
+ 0, /* 59: Reserved */
+ 0, /* 60: Reserved */
+ 0, /* 61: Reserved */
+ 0, /* 62: Reserved */
+ 0, /* 63: Reserved */
+ 0, /* 64: Reserved */
+ 0, /* 65: Reserved */
+ 0, /* 66: Reserved */
+ 0, /* 67: Reserved */
+ 0, /* 68: Reserved */
+ GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
+ GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
+ GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
+ GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
+ GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
+ GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
+ GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
+ GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
+ GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
+ GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
+ GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
+ GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
+ GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
+ GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
+ GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
+ GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
+ GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
+ GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
+ GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
+ GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
+ GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
+ GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
+ GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
+ GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
+ GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
+ GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
+ GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
+ GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
+ GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
+ GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
+ GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
+ GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
+ GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
+ GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
+ GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
+ GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
+ GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
+ GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
+ GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
+ GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
+ GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
+ GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
+ GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
+ GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
+ GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
+ GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
+ GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
+ GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
+ GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
+ GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
+ GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
+ GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
+ GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
+ GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
+ GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
+ GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
+ UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
+ UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
+ UART5_Handler, /* 127: UART 5 combined Interrupt */
+ 0, /* 128: Reserved */
+ 0, /* 129: Reserved */
+ 0, /* 130: Reserved */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT));
+
+ SystemInit(); /* CMSIS System Initialization */
+ __ASM volatile("MRS R0, control\n" /* Get control value */
+ "ORR R0, R0, #1\n" /* Select switch to unprivilage mode */
+ "ORR R0, R0, #2\n" /* Select switch to PSP */
+ "MSR control, R0\n" /* Load control register */
+ :
+ :
+ : "r0");
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
diff --git a/platform/ext/target/mps3/an547/device/source/startup_an547_s.c b/platform/ext/target/mps3/an547/device/source/startup_an547_s.c
new file mode 100644
index 0000000..5edddb0
--- /dev/null
+++ b/platform/ext/target/mps3/an547/device/source/startup_an547_s.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
+ * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
+ */
+
+#include "cmsis.h"
+#include "region.h"
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler Function Prototype
+ *----------------------------------------------------------------------------*/
+typedef void( *pFunc )( void );
+
+/*----------------------------------------------------------------------------
+ External References
+ *----------------------------------------------------------------------------*/
+
+#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit)
+#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base)
+
+extern uint32_t __MSP_INITIAL_SP;
+extern uint32_t __MSP_STACK_LIMIT;
+
+extern uint32_t __INITIAL_SP;
+extern uint32_t __STACK_LIMIT;
+
+extern void __PROGRAM_START(void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Internal References
+ *----------------------------------------------------------------------------*/
+void Reset_Handler (void) __NO_RETURN;
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+#define DEFAULT_IRQ_HANDLER(handler_name) \
+void __WEAK handler_name(void); \
+void handler_name(void) { \
+ while(1); \
+}
+
+/* Exceptions */
+DEFAULT_IRQ_HANDLER(NMI_Handler)
+DEFAULT_IRQ_HANDLER(HardFault_Handler)
+DEFAULT_IRQ_HANDLER(MemManage_Handler)
+DEFAULT_IRQ_HANDLER(BusFault_Handler)
+DEFAULT_IRQ_HANDLER(UsageFault_Handler)
+DEFAULT_IRQ_HANDLER(SecureFault_Handler)
+DEFAULT_IRQ_HANDLER(SVC_Handler)
+DEFAULT_IRQ_HANDLER(DebugMon_Handler)
+DEFAULT_IRQ_HANDLER(PendSV_Handler)
+DEFAULT_IRQ_HANDLER(SysTick_Handler)
+
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler)
+DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
+DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
+DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler)
+DEFAULT_IRQ_HANDLER(TIMER1_Handler)
+DEFAULT_IRQ_HANDLER(TIMER2_Handler)
+DEFAULT_IRQ_HANDLER(MPC_Handler)
+DEFAULT_IRQ_HANDLER(PPC_Handler)
+DEFAULT_IRQ_HANDLER(MSC_Handler)
+DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
+DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
+DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
+DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
+DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler)
+DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler)
+
+DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
+DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
+DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
+DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
+DEFAULT_IRQ_HANDLER(I2S_Handler)
+DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
+DEFAULT_IRQ_HANDLER(USB_Handler)
+DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
+DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
+DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
+DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
+DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
+DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
+DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
+DEFAULT_IRQ_HANDLER(UART5_Handler)
+
+/*----------------------------------------------------------------------------
+ Exception / Interrupt Vector table
+ *----------------------------------------------------------------------------*/
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+
+extern const pFunc __VECTOR_TABLE[496];
+ const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
+ (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* -14: NMI Handler */
+ HardFault_Handler, /* -13: Hard Fault Handler */
+ MemManage_Handler, /* -12: MPU Fault Handler */
+ BusFault_Handler, /* -11: Bus Fault Handler */
+ UsageFault_Handler, /* -10: Usage Fault Handler */
+ SecureFault_Handler, /* -9: Secure Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* -5: SVCall Handler */
+ DebugMon_Handler, /* -4: Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* -2: PendSV Handler */
+ SysTick_Handler, /* -1: SysTick Handler */
+
+ NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */
+ NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
+ SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
+ TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */
+ TIMER1_Handler, /* 4: TIMER 1 Handler */
+ TIMER2_Handler, /* 5: TIMER 2 Handler */
+ 0, /* 6: Reserved */
+ 0, /* 7: Reserved */
+ 0, /* 8: Reserved */
+ MPC_Handler, /* 9: MPC Combined (Secure) Handler */
+ PPC_Handler, /* 10: PPC Combined (Secure) Handler */
+ MSC_Handler, /* 11: MSC Combined (Secure) Handler */
+ BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
+ 0, /* 13: Reserved */
+ MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
+ SYS_PPU_Handler, /* 15: SYS PPU Handler */
+ CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
+ 0, /* 17: Reserved */
+ 0, /* 18: Reserved */
+ 0, /* 19: Reserved */
+ 0, /* 20: Reserved */
+ 0, /* 21: Reserved */
+ 0, /* 22: Reserved */
+ 0, /* 23: Reserved */
+ 0, /* 24: Reserved */
+ 0, /* 25: Reserved */
+ DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
+ TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */
+ CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */
+ CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */
+ 0, /* 30: Reserved */
+ 0, /* 31: Reserved */
+
+ /* External interrupts */
+ System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
+ UARTRX0_Handler, /* 33: UART 0 RX Handler */
+ UARTTX0_Handler, /* 34: UART 0 TX Handler */
+ UARTRX1_Handler, /* 35: UART 1 RX Handler */
+ UARTTX1_Handler, /* 36: UART 1 TX Handler */
+ UARTRX2_Handler, /* 37: UART 2 RX Handler */
+ UARTTX2_Handler, /* 38: UART 2 TX Handler */
+ UARTRX3_Handler, /* 39: UART 3 RX Handler */
+ UARTTX3_Handler, /* 40: UART 3 TX Handler */
+ UARTRX4_Handler, /* 41: UART 4 RX Handler */
+ UARTTX4_Handler, /* 42: UART 4 TX Handler */
+ UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
+ UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
+ UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
+ UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
+ UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
+ UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
+ ETHERNET_Handler, /* 49: Ethernet Handler */
+ I2S_Handler, /* 50: Audio I2S Handler */
+ TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
+ USB_Handler, /* 52: USB Handler */
+ SPI_ADC_Handler, /* 53: SPI ADC Handler */
+ SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
+ SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
+ ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
+ 0, /* 57: Reserved */
+ 0, /* 58: Reserved */
+ 0, /* 59: Reserved */
+ 0, /* 60: Reserved */
+ 0, /* 61: Reserved */
+ 0, /* 62: Reserved */
+ 0, /* 63: Reserved */
+ 0, /* 64: Reserved */
+ 0, /* 65: Reserved */
+ 0, /* 66: Reserved */
+ 0, /* 67: Reserved */
+ 0, /* 68: Reserved */
+ GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
+ GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
+ GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
+ GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
+ GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
+ GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
+ GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
+ GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
+ GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
+ GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
+ GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
+ GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
+ GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
+ GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
+ GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
+ GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
+ GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
+ GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
+ GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
+ GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
+ GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
+ GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
+ GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
+ GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
+ GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
+ GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
+ GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
+ GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
+ GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
+ GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
+ GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
+ GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
+ GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
+ GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
+ GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
+ GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
+ GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
+ GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
+ GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
+ GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
+ GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
+ GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
+ GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
+ GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
+ GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
+ GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
+ GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
+ GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
+ GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
+ GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
+ GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
+ GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
+ GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
+ GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
+ GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
+ GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
+ UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
+ UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
+ UART5_Handler, /* 127: UART 5 combined Interrupt */
+ 0, /* 128: Reserved */
+ 0, /* 129: Reserved */
+ 0, /* 130: Reserved */
+};
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/*----------------------------------------------------------------------------
+ Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+void Reset_Handler(void)
+{
+ __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT));
+
+ SystemInit(); /* CMSIS System Initialization */
+ __ASM volatile("MRS R0, control\n" /* Get control value */
+ "ORR R0, R0, #2\n" /* Select switch to PSP */
+ "MSR control, R0\n" /* Load control register */
+ :
+ :
+ : "r0");
+ __PROGRAM_START(); /* Enter PreMain (C library entry point) */
+}
diff --git a/platform/ext/target/mps3/fvp_sse300/device/source/system_core_init.c b/platform/ext/target/mps3/an547/device/source/system_core_init.c
similarity index 86%
rename from platform/ext/target/mps3/fvp_sse300/device/source/system_core_init.c
rename to platform/ext/target/mps3/an547/device/source/system_core_init.c
index e8e9e4c..6fe49b3 100644
--- a/platform/ext/target/mps3/fvp_sse300/device/source/system_core_init.c
+++ b/platform/ext/target/mps3/an547/device/source/system_core_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -62,6 +62,12 @@
SCB->VTOR = (uint32_t)(&__VECTOR_TABLE);
#endif
+#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
+ (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE == 1U))
+ SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
+ (3U << 11U*2U) ); /* enable CP11 Full Access */
+#endif
+
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/mpc_sie_drv.c b/platform/ext/target/mps3/an547/native_drivers/mpc_sie_drv.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/mpc_sie_drv.c
rename to platform/ext/target/mps3/an547/native_drivers/mpc_sie_drv.c
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/mpc_sie_drv.h b/platform/ext/target/mps3/an547/native_drivers/mpc_sie_drv.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/mpc_sie_drv.h
rename to platform/ext/target/mps3/an547/native_drivers/mpc_sie_drv.h
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/mpu_armv8m_drv.c b/platform/ext/target/mps3/an547/native_drivers/mpu_armv8m_drv.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/mpu_armv8m_drv.c
rename to platform/ext/target/mps3/an547/native_drivers/mpu_armv8m_drv.c
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/mpu_armv8m_drv.h b/platform/ext/target/mps3/an547/native_drivers/mpu_armv8m_drv.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/mpu_armv8m_drv.h
rename to platform/ext/target/mps3/an547/native_drivers/mpu_armv8m_drv.h
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/ppc_sse300_drv.c b/platform/ext/target/mps3/an547/native_drivers/ppc_sse300_drv.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/ppc_sse300_drv.c
rename to platform/ext/target/mps3/an547/native_drivers/ppc_sse300_drv.c
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/ppc_sse300_drv.h b/platform/ext/target/mps3/an547/native_drivers/ppc_sse300_drv.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/ppc_sse300_drv.h
rename to platform/ext/target/mps3/an547/native_drivers/ppc_sse300_drv.h
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/syscounter_armv8-m_cntrl_drv.c b/platform/ext/target/mps3/an547/native_drivers/syscounter_armv8-m_cntrl_drv.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/syscounter_armv8-m_cntrl_drv.c
rename to platform/ext/target/mps3/an547/native_drivers/syscounter_armv8-m_cntrl_drv.c
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/syscounter_armv8-m_cntrl_drv.h b/platform/ext/target/mps3/an547/native_drivers/syscounter_armv8-m_cntrl_drv.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/syscounter_armv8-m_cntrl_drv.h
rename to platform/ext/target/mps3/an547/native_drivers/syscounter_armv8-m_cntrl_drv.h
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/systimer_armv8-m_drv.c b/platform/ext/target/mps3/an547/native_drivers/systimer_armv8-m_drv.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/systimer_armv8-m_drv.c
rename to platform/ext/target/mps3/an547/native_drivers/systimer_armv8-m_drv.c
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/systimer_armv8-m_drv.h b/platform/ext/target/mps3/an547/native_drivers/systimer_armv8-m_drv.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/systimer_armv8-m_drv.h
rename to platform/ext/target/mps3/an547/native_drivers/systimer_armv8-m_drv.h
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/uart_cmsdk_drv.c b/platform/ext/target/mps3/an547/native_drivers/uart_cmsdk_drv.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/uart_cmsdk_drv.c
rename to platform/ext/target/mps3/an547/native_drivers/uart_cmsdk_drv.c
diff --git a/platform/ext/target/mps3/fvp_sse300/native_drivers/uart_cmsdk_drv.h b/platform/ext/target/mps3/an547/native_drivers/uart_cmsdk_drv.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/native_drivers/uart_cmsdk_drv.h
rename to platform/ext/target/mps3/an547/native_drivers/uart_cmsdk_drv.h
diff --git a/platform/ext/target/mps3/fvp_sse300/partition/flash_layout.h b/platform/ext/target/mps3/an547/partition/flash_layout.h
similarity index 96%
rename from platform/ext/target/mps3/fvp_sse300/partition/flash_layout.h
rename to platform/ext/target/mps3/an547/partition/flash_layout.h
index 93c9cf8..a571b07 100644
--- a/platform/ext/target/mps3/fvp_sse300/partition/flash_layout.h
+++ b/platform/ext/target/mps3/an547/partition/flash_layout.h
@@ -19,7 +19,7 @@
#include "platform_base_address.h"
-/* Flash layout on fvp_sse300_mps3 with BL2 (multiple image boot):
+/* Flash layout on AN547 with BL2 (multiple image boot):
*
* 0x0000_0000 Secure image primary slot (384 KB)
* 0x0006_0000 Non-secure image primary slot (384 KB)
@@ -27,11 +27,11 @@
* 0x0012_0000 Non-secure image secondary slot (384 KB)
* 0x0018_0000 Scratch area (384 KB)
* 0x001E_0000 Protected Storage Area (20 KB)
- * 0x001E_8000 Internal Trusted Storage Area (16 KB)
- * 0x001E_D800 NV counters area (4 KB)
+ * 0x001E_5000 Internal Trusted Storage Area (16 KB)
+ * 0x001E_9000 NV counters area (4 KB)
* 0x001E_E800 Unused
*
- * Flash layout on fvp_sse300_mps3 with BL2 (single image boot):
+ * Flash layout on AN547 with BL2 (single image boot):
*
* 0x0000_0000 Primary image area (768 KB):
* 0x0000_0000 Secure image primary (384 KB)
@@ -134,9 +134,9 @@
#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!"
#endif /* MCUBOOT_IMAGE_NUMBER */
-/* mpc_init_cfg function in target_cfg.c expects that all the images are located
- * in SSRAM2 device, and those do not overlap to SSRAM3. */
-#if ( FLASH_AREA_SCRATCH_OFFSET > SRAM_SIZE)
+/* mpc_init_cfg function in target_cfg.c expects that all the images can fit
+ * in SRAM area. */
+#if ( FLASH_AREA_SCRATCH_OFFSET + FLASH_AREA_SCRATCH_SIZE > SRAM_SIZE)
#error "Out of SRAM memory!"
#endif
diff --git a/platform/ext/target/mps3/fvp_sse300/partition/platform_base_address.h b/platform/ext/target/mps3/an547/partition/platform_base_address.h
similarity index 79%
rename from platform/ext/target/mps3/fvp_sse300/partition/platform_base_address.h
rename to platform/ext/target/mps3/an547/partition/platform_base_address.h
index 3634416..ba39235 100644
--- a/platform/ext/target/mps3/fvp_sse300/partition/platform_base_address.h
+++ b/platform/ext/target/mps3/an547/partition/platform_base_address.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited
+ * Copyright (c) 2019-2021 Arm Limited
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -16,8 +16,8 @@
/**
* \file platform_base_address.h
- * \brief This file defines all the peripheral base addresses for MPS3 SSE-300
- * Ethos-U55 FVP platform.
+ * \brief This file defines all the peripheral base addresses for AN547 MPS3 SSE-300 +
+ * Ethos-U55 platform.
*/
#ifndef __PLATFORM_BASE_ADDRESS_H__
@@ -28,11 +28,11 @@
#define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */
#define SRAM_BASE_NS 0x01000000 /* CODE SRAM Non-Secure base address */
#define DTCM0_BASE_NS 0x20000000 /* Data TCM block 0 Non-Secure base address */
-#define DTCM1_BASE_NS 0x20100000 /* Data TCM block 1 Non-Secure base address */
-#define DTCM2_BASE_NS 0x20200000 /* Data TCM block 2 Non-Secure base address */
-#define DTCM3_BASE_NS 0x20300000 /* Data TCM block 3 Non-Secure base address */
+#define DTCM1_BASE_NS 0x20020000 /* Data TCM block 1 Non-Secure base address */
+#define DTCM2_BASE_NS 0x20040000 /* Data TCM block 2 Non-Secure base address */
+#define DTCM3_BASE_NS 0x20060000 /* Data TCM block 3 Non-Secure base address */
#define ISRAM0_BASE_NS 0x21000000 /* Internal SRAM Area Non-Secure base address */
-#define ISRAM1_BASE_NS 0x21040000 /* Internal SRAM Area Non-Secure base address */
+#define ISRAM1_BASE_NS 0x21200000 /* Internal SRAM Area Non-Secure base address */
#define QSPI_SRAM_BASE_NS 0x28000000 /* QSPI SRAM Non-Secure base address */
/* Non-Secure Subsystem peripheral region */
#define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */
@@ -71,7 +71,8 @@
#define SYSCNTR_READ_BASE_NS 0x48101000 /* System Counter Read Secure base address */
/* Non-Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_NS 0x48102000 /* Ethos-U55 APB Non-Secure base address */
-#define U55_TIMING_ADAPTER_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter registers Non-Secure base address */
+#define U55_TIMING_ADAPTER_0_BASE_NS 0x48103000 /* Ethos-U55 Timing Adapter 0 APB registers Non-Secure base address */
+#define U55_TIMING_ADAPTER_1_BASE_NS 0x48103200 /* Ethos-U55 Timing Adapter 1 APB registers Non-Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_NS 0x49200000 /* FPGA - SBCon I2C (Touch) Non-Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_NS 0x49201000 /* FPGA - SBCon I2C (Audio Conf) Non-Secure base address */
#define FPGA_SPI_ADC_BASE_NS 0x49202000 /* FPGA - PL022 (SPI ADC) Non-Secure base address */
@@ -93,19 +94,19 @@
#define CLCD_Config_Reg_BASE_NS 0x4930A000 /* CLCD Config Reg Non-Secure base address */
#define RTC_BASE_NS 0x4930B000 /* RTC Non-Secure base address */
#define DDR4_BLK0_BASE_NS 0x60000000 /* DDR4 block 0 Non-Secure base address */
-#define DDR4_BLK1_BASE_NS 0x80000000 /* DDR4 block 1 Non-Secure base address */
-#define DDR4_BLK2_BASE_NS 0xA0000000 /* DDR4 block 2 Non-Secure base address */
-#define DDR4_BLK3_BASE_NS 0xC0000000 /* DDR4 block 3 Non-Secure base address */
+#define DDR4_BLK2_BASE_NS 0x80000000 /* DDR4 block 2 Non-Secure base address */
+#define DDR4_BLK4_BASE_NS 0xA0000000 /* DDR4 block 4 Non-Secure base address */
+#define DDR4_BLK6_BASE_NS 0xC0000000 /* DDR4 block 6 Non-Secure base address */
/* Secure memory map addresses */
#define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */
#define SRAM_BASE_S 0x11000000 /* CODE SRAM Secure base address */
#define DTCM0_BASE_S 0x30000000 /* Data TCM block 0 Secure base address */
-#define DTCM1_BASE_S 0x30100000 /* Data TCM block 1 Secure base address */
-#define DTCM2_BASE_S 0x30200000 /* Data TCM block 2 Secure base address */
-#define DTCM3_BASE_S 0x30300000 /* Data TCM block 3 Secure base address */
+#define DTCM1_BASE_S 0x30020000 /* Data TCM block 1 Secure base address */
+#define DTCM2_BASE_S 0x30040000 /* Data TCM block 2 Secure base address */
+#define DTCM3_BASE_S 0x30060000 /* Data TCM block 3 Secure base address */
#define ISRAM0_BASE_S 0x31000000 /* Internal SRAM Area Secure base address */
-#define ISRAM1_BASE_S 0x31040000 /* Internal SRAM Area Secure base address */
+#define ISRAM1_BASE_S 0x31200000 /* Internal SRAM Area Secure base address */
#define QSPI_SRAM_BASE_S 0x38000000 /* QSPI SRAM Secure base address */
/* Secure Subsystem peripheral region */
#define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */
@@ -157,7 +158,8 @@
#define SYSCNTR_READ_BASE_S 0x58101000 /* System Counter Read Secure base address */
/* Secure MSTEXPPIHL Peripheral region */
#define ETHOS_U55_APB_BASE_S 0x58102000 /* Ethos-U55 APB Secure base address */
-#define U55_TIMING_ADAPTER_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter registers Secure base address */
+#define U55_TIMING_ADAPTER_0_BASE_S 0x58103000 /* Ethos-U55 Timing Adapter 0 APB registers Secure base address */
+#define U55_TIMING_ADAPTER_1_BASE_S 0x58103200 /* Ethos-U55 Timing Adapter 1 APB registers Secure base address */
#define FPGA_SBCon_I2C_TOUCH_BASE_S 0x59200000 /* FPGA - SBCon I2C (Touch) Secure base address */
#define FPGA_SBCon_I2C_AUDIO_BASE_S 0x59201000 /* FPGA - SBCon I2C (Audio Conf) Secure base address */
#define FPGA_SPI_ADC_BASE_S 0x59202000 /* FPGA - PL022 (SPI ADC) Secure base address */
@@ -178,10 +180,10 @@
#define UART5_BASE_S 0x59308000 /* UART 5 Secure base address */
#define CLCD_Config_Reg_BASE_S 0x5930A000 /* CLCD Config Reg Secure base address */
#define RTC_BASE_S 0x5930B000 /* RTC Secure base address */
-#define DDR4_BLK0_BASE_S 0x70000000 /* DDR4 block 0 Secure base address */
-#define DDR4_BLK1_BASE_S 0x90000000 /* DDR4 block 1 Secure base address */
-#define DDR4_BLK2_BASE_S 0xB0000000 /* DDR4 block 2 Secure base address */
-#define DDR4_BLK3_BASE_S 0xD0000000 /* DDR4 block 3 Secure base address */
+#define DDR4_BLK1_BASE_S 0x70000000 /* DDR4 block 1 Secure base address */
+#define DDR4_BLK3_BASE_S 0x90000000 /* DDR4 block 3 Secure base address */
+#define DDR4_BLK5_BASE_S 0xB0000000 /* DDR4 block 5 Secure base address */
+#define DDR4_BLK7_BASE_S 0xD0000000 /* DDR4 block 7 Secure base address */
/* Memory map addresses exempt from memory attribution by both the SAU and IDAU */
#define SSE300_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller
@@ -189,43 +191,73 @@
* if AIRCR.BFHFNMINS is set to 1 */
/* Memory size definitions */
-#define ITCM_SIZE (0x00100000) /* 1 MB */
-#define DTCM_BLK_SIZE (0x00100000) /* 1 MB */
+#define ITCM_SIZE (0x00080000) /* 512 kB */
+#define DTCM_BLK_SIZE (0x00020000) /* 128 kB */
+#define DTCM_BLK_NUM (0x4) /* Number of DTCM blocks */
#define SRAM_SIZE (0x00200000) /* 2 MB */
-#define ISRAM0_SIZE (0x00040000) /* 256 kB */
-#define ISRAM1_SIZE (0x00040000) /* 256 kB */
+#define ISRAM0_SIZE (0x00200000) /* 2 MB */
+#define ISRAM1_SIZE (0x00200000) /* 2 MB */
#define QSPI_SRAM_SIZE (0x00800000) /* 8 MB */
#define DDR4_BLK_SIZE (0x10000000) /* 256 MB */
+#define DDR4_BLK_NUM (0x8) /* Number of DDR4 blocks */
/* Defines for Driver MPC's */
/* SRAM -- 2 MB */
#define MPC_SRAM_RANGE_BASE_NS (SRAM_BASE_NS)
#define MPC_SRAM_RANGE_LIMIT_NS (SRAM_BASE_NS + SRAM_SIZE-1)
+#define MPC_SRAM_RANGE_OFFSET_NS (0x0)
#define MPC_SRAM_RANGE_BASE_S (SRAM_BASE_S)
#define MPC_SRAM_RANGE_LIMIT_S (SRAM_BASE_S + SRAM_SIZE-1)
+#define MPC_SRAM_RANGE_OFFSET_S (0x0)
/* QSPI -- 8 MB*/
#define MPC_QSPI_RANGE_BASE_NS (QSPI_SRAM_BASE_NS)
#define MPC_QSPI_RANGE_LIMIT_NS (QSPI_SRAM_BASE_NS + QSPI_SRAM_SIZE-1)
+#define MPC_QSPI_RANGE_OFFSET_NS (0x0)
#define MPC_QSPI_RANGE_BASE_S (QSPI_SRAM_BASE_S)
#define MPC_QSPI_RANGE_LIMIT_S (QSPI_SRAM_BASE_S + QSPI_SRAM_SIZE-1)
+#define MPC_QSPI_RANGE_OFFSET_S (0x0)
-/* ISRAM0 -- 256 kB*/
+/* ISRAM0 -- 2 MB*/
#define MPC_ISRAM0_RANGE_BASE_NS (ISRAM0_BASE_NS)
#define MPC_ISRAM0_RANGE_LIMIT_NS (ISRAM0_BASE_NS + ISRAM0_SIZE-1)
+#define MPC_ISRAM0_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM0_RANGE_BASE_S (ISRAM0_BASE_S)
#define MPC_ISRAM0_RANGE_LIMIT_S (ISRAM0_BASE_S + ISRAM0_SIZE-1)
+#define MPC_ISRAM0_RANGE_OFFSET_S (0x0)
-/* ISRAM1 -- 256 kB*/
+/* ISRAM1 -- 2 MB*/
#define MPC_ISRAM1_RANGE_BASE_NS (ISRAM1_BASE_NS)
#define MPC_ISRAM1_RANGE_LIMIT_NS (ISRAM1_BASE_NS + ISRAM1_SIZE-1)
+#define MPC_ISRAM1_RANGE_OFFSET_NS (0x0)
#define MPC_ISRAM1_RANGE_BASE_S (ISRAM1_BASE_S)
#define MPC_ISRAM1_RANGE_LIMIT_S (ISRAM1_BASE_S + ISRAM1_SIZE-1)
+#define MPC_ISRAM1_RANGE_OFFSET_S (0x0)
-/* DDR4_BLK0 -- 256 MB */
-#define MPC_DDR4_RANGE_BASE_NS (DDR4_BLK0_BASE_NS)
-#define MPC_DDR4_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
-#define MPC_DDR4_RANGE_BASE_S (DDR4_BLK0_BASE_S)
-#define MPC_DDR4_RANGE_LIMIT_S (DDR4_BLK0_BASE_S + ((DDR4_BLK_SIZE)-1))
+/* DDR4 -- 2GB (8 * 256 MB) */
+#define MPC_DDR4_BLK0_RANGE_BASE_NS (DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK0_RANGE_LIMIT_NS (DDR4_BLK0_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK0_RANGE_OFFSET_NS (0x0)
+#define MPC_DDR4_BLK1_RANGE_BASE_S (DDR4_BLK1_BASE_S)
+#define MPC_DDR4_BLK1_RANGE_LIMIT_S (DDR4_BLK1_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK1_RANGE_OFFSET_S (DDR4_BLK1_BASE_S - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK2_RANGE_BASE_NS (DDR4_BLK2_BASE_NS)
+#define MPC_DDR4_BLK2_RANGE_LIMIT_NS (DDR4_BLK2_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK2_RANGE_OFFSET_NS (DDR4_BLK2_BASE_NS - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK3_RANGE_BASE_S (DDR4_BLK3_BASE_S)
+#define MPC_DDR4_BLK3_RANGE_LIMIT_S (DDR4_BLK3_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK3_RANGE_OFFSET_S (DDR4_BLK3_BASE_S - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK4_RANGE_BASE_NS (DDR4_BLK4_BASE_NS)
+#define MPC_DDR4_BLK4_RANGE_LIMIT_NS (DDR4_BLK4_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK4_RANGE_OFFSET_NS (DDR4_BLK4_BASE_NS - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK5_RANGE_BASE_S (DDR4_BLK5_BASE_S)
+#define MPC_DDR4_BLK5_RANGE_LIMIT_S (DDR4_BLK5_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK5_RANGE_OFFSET_S (DDR4_BLK5_BASE_S - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK6_RANGE_BASE_NS (DDR4_BLK6_BASE_NS)
+#define MPC_DDR4_BLK6_RANGE_LIMIT_NS (DDR4_BLK6_BASE_NS + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK6_RANGE_OFFSET_NS (DDR4_BLK6_BASE_NS - DDR4_BLK0_BASE_NS)
+#define MPC_DDR4_BLK7_RANGE_BASE_S (DDR4_BLK7_BASE_S)
+#define MPC_DDR4_BLK7_RANGE_LIMIT_S (DDR4_BLK7_BASE_S + ((DDR4_BLK_SIZE)-1))
+#define MPC_DDR4_BLK7_RANGE_OFFSET_S (DDR4_BLK7_BASE_S - DDR4_BLK0_BASE_NS)
#endif /* __PLATFORM_BASE_ADDRESS_H__ */
diff --git a/platform/ext/target/mps3/fvp_sse300/partition/region_defs.h b/platform/ext/target/mps3/an547/partition/region_defs.h
similarity index 94%
rename from platform/ext/target/mps3/fvp_sse300/partition/region_defs.h
rename to platform/ext/target/mps3/an547/partition/region_defs.h
index ca225ea..bf747de 100644
--- a/platform/ext/target/mps3/fvp_sse300/partition/region_defs.h
+++ b/platform/ext/target/mps3/an547/partition/region_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -37,11 +37,6 @@
*/
#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE (0x250)
-/*
- * MPC granularity is 4 KB on SSE300_MPS3 FVP. Alignment
- * of partitions is defined in accordance with this constraint.
- */
-
#ifdef BL2
#ifndef LINK_TO_SECONDARY_PARTITION
#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
@@ -91,14 +86,14 @@
/* Secure regions */
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
-/* Secure Code stored in SSRAM2 */
+/* Secure Code stored in Code SRAM */
#define S_CODE_START ((SRAM_BASE_S) + (S_IMAGE_PRIMARY_AREA_OFFSET))
#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
/* Secure Data stored in DTCM */
#define S_DATA_START (DTCM0_BASE_S)
-#define S_DATA_SIZE (DTCM_BLK_SIZE)
+#define S_DATA_SIZE (DTCM_BLK_SIZE * DTCM_BLK_NUM)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
/* CMSE Veneers region */
@@ -107,7 +102,7 @@
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
(NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
-/* Non-Secure Code stored in SSRAM2 memory */
+/* Non-Secure Code stored in Code SRAM memory */
#define NS_CODE_START (SRAM_BASE_NS + (NS_IMAGE_PRIMARY_AREA_OFFSET))
#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE)
#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
diff --git a/platform/ext/target/mps3/fvp_sse300/plat_test.c b/platform/ext/target/mps3/an547/plat_test.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/plat_test.c
rename to platform/ext/target/mps3/an547/plat_test.c
diff --git a/platform/ext/target/mps3/fvp_sse300/preload.cmake b/platform/ext/target/mps3/an547/preload.cmake
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/preload.cmake
rename to platform/ext/target/mps3/an547/preload.cmake
diff --git a/platform/ext/target/mps3/fvp_sse300/services/src/tfm_platform_system.c b/platform/ext/target/mps3/an547/services/src/tfm_platform_system.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/services/src/tfm_platform_system.c
rename to platform/ext/target/mps3/an547/services/src/tfm_platform_system.c
diff --git a/platform/ext/target/mps3/fvp_sse300/spm_hal.c b/platform/ext/target/mps3/an547/spm_hal.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/spm_hal.c
rename to platform/ext/target/mps3/an547/spm_hal.c
diff --git a/platform/ext/target/mps3/fvp_sse300/target_cfg.c b/platform/ext/target/mps3/an547/target_cfg.c
similarity index 93%
rename from platform/ext/target/mps3/fvp_sse300/target_cfg.c
rename to platform/ext/target/mps3/an547/target_cfg.c
index 3059772..ef9c023 100644
--- a/platform/ext/target/mps3/fvp_sse300/target_cfg.c
+++ b/platform/ext/target/mps3/an547/target_cfg.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -27,11 +27,6 @@
/* Throw out bus error when an access causes security violation */
#define CMSDK_SECRESPCFG_BUS_ERR_MASK (1UL << 0)
-/* Macros to pick linker symbols */
-#define REGION(a, b, c) a##b##c
-#define REGION_NAME(a, b, c) REGION(a, b, c)
-#define REGION_DECLARE(a, b, c) extern uint32_t REGION_NAME(a, b, c)
-
/* The section names come from the scatter file */
REGION_DECLARE(Load$$LR$$, LR_NS_PARTITION, $$Base);
REGION_DECLARE(Load$$LR$$, LR_VENEER, $$Base);
@@ -67,6 +62,8 @@
/* Configures the RAM region to NS callable in sacfg block's nsccfg register */
#define RAMNSC 0x2
+/* Configures the CODE region to NS callable in sacfg block's nsccfg register */
+#define CODENSC 0x1
/* Import MPC drivers */
extern ARM_DRIVER_MPC Driver_ISRAM0_MPC;
@@ -78,11 +75,14 @@
extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_MAIN0;
extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_MAIN_EXP0;
extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_MAIN_EXP1;
+extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_MAIN_EXP2;
+extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_MAIN_EXP3;
extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_PERIPH0;
extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_PERIPH1;
extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_PERIPH_EXP0;
extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_PERIPH_EXP1;
extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_PERIPH_EXP2;
+extern DRIVER_PPC_SSE300 Driver_PPC_SSE300_PERIPH_EXP3;
/* Define Peripherals NS address range for the platform */
#define PERIPHERALS_BASE_NS_START (0x40000000)
@@ -134,11 +134,14 @@
&Driver_PPC_SSE300_MAIN0,
&Driver_PPC_SSE300_MAIN_EXP0,
&Driver_PPC_SSE300_MAIN_EXP1,
+ &Driver_PPC_SSE300_MAIN_EXP2,
+ &Driver_PPC_SSE300_MAIN_EXP3,
&Driver_PPC_SSE300_PERIPH0,
&Driver_PPC_SSE300_PERIPH1,
&Driver_PPC_SSE300_PERIPH_EXP0,
&Driver_PPC_SSE300_PERIPH_EXP1,
&Driver_PPC_SSE300_PERIPH_EXP2,
+ &Driver_PPC_SSE300_PERIPH_EXP3,
};
#define PPC_BANK_COUNT (sizeof(ppc_bank_drivers)/sizeof(ppc_bank_drivers[0]))
@@ -214,11 +217,7 @@
ERROR_MSG("Failed to Enable MPC interrupt for ISRAM0!");
return TFM_PLAT_ERR_SYSTEM_ERR;
}
- ret = Driver_ISRAM1_MPC.EnableInterrupt();
- if (ret != ARM_DRIVER_OK) {
- ERROR_MSG("Failed to Enable MPC interrupt for ISRAM1!");
- return TFM_PLAT_ERR_SYSTEM_ERR;
- }
+
ret = Driver_SRAM_MPC.EnableInterrupt();
if (ret != ARM_DRIVER_OK) {
ERROR_MSG("Failed to Enable MPC interrupt for SRAM!");
@@ -234,7 +233,7 @@
for (i = 0; i < PPC_BANK_COUNT; i++) {
ret = ppc_bank_drivers[i]->EnableInterrupt();
if (ret != ARM_DRIVER_OK) {
- //ERROR_MSG("Failed to Enable interrupt on PPC bank number %d!", i);
+ ERROR_MSG("Failed to Enable interrupt on PPC");
return TFM_PLAT_ERR_SYSTEM_ERR;
}
}
@@ -325,8 +324,8 @@
SAU->RLAR = (memory_regions.secondary_partition_limit
& SAU_RLAR_LADDR_Msk) | SAU_RLAR_ENABLE_Msk;
- /* Allows SAU to define the RAM region as a NSC */
- sacfg->nsccfg |= RAMNSC;
+ /* Allows SAU to define the CODE region as a NSC */
+ sacfg->nsccfg |= CODENSC;
}
/*------------------- Memory configuration functions -------------------------*/
@@ -334,8 +333,8 @@
{
int32_t ret = ARM_DRIVER_OK;
- /* ISRAM0 and ISRAM1 memories allocated for NS data, so whole range set to
- * non-secure accesible. */
+ /* ISRAM0 is allocated for NS data, so whole range is set to non-secure
+ * accesible. */
ret = Driver_ISRAM0_MPC.Initialize();
if (ret != ARM_DRIVER_OK) {
ERROR_MSG("Failed to Initialize MPC for ISRAM0!");
@@ -349,19 +348,6 @@
return TFM_PLAT_ERR_SYSTEM_ERR;
}
- ret = Driver_ISRAM1_MPC.Initialize();
- if (ret != ARM_DRIVER_OK) {
- ERROR_MSG("Failed to Initialize MPC for ISRAM1!");
- return TFM_PLAT_ERR_SYSTEM_ERR;
- }
- ret = Driver_ISRAM1_MPC.ConfigRegion(MPC_ISRAM1_RANGE_BASE_NS,
- MPC_ISRAM1_RANGE_LIMIT_NS,
- ARM_MPC_ATTR_NONSECURE);
- if (ret != ARM_DRIVER_OK) {
- ERROR_MSG("Failed to Configure MPC for ISRAM1!");
- return TFM_PLAT_ERR_SYSTEM_ERR;
- }
-
/* Configuring primary and secondary non-secure partition.
* It is ensured in flash_layout.h that these memory regions are located in
* SRAM SRAM device. */
@@ -393,11 +379,7 @@
ERROR_MSG("Failed to Lock down MPC for ISRAM0!");
return TFM_PLAT_ERR_SYSTEM_ERR;
}
- ret = Driver_ISRAM1_MPC.LockDown();
- if (ret != ARM_DRIVER_OK) {
- ERROR_MSG("Failed to Lock down MPC for ISRAM1!");
- return TFM_PLAT_ERR_SYSTEM_ERR;
- }
+
ret = Driver_SRAM_MPC.LockDown();
if (ret != ARM_DRIVER_OK) {
ERROR_MSG("Failed to Lock down MPC for SRAM!");
@@ -406,6 +388,7 @@
/* Lock down not used MPC's */
Driver_QSPI_MPC.LockDown();
+ Driver_ISRAM1_MPC.LockDown();
/* Add barriers to assure the MPC configuration is done before continue
* the execution.
@@ -419,7 +402,6 @@
void mpc_clear_irq(void)
{
Driver_ISRAM0_MPC.ClearInterrupt();
- Driver_ISRAM1_MPC.ClearInterrupt();
Driver_SRAM_MPC.ClearInterrupt();
}
@@ -526,8 +508,11 @@
/* Initialize not used PPC drivers */
err |= Driver_PPC_SSE300_MAIN0.Initialize();
+ err |= Driver_PPC_SSE300_MAIN_EXP2.Initialize();
+ err |= Driver_PPC_SSE300_MAIN_EXP3.Initialize();
err |= Driver_PPC_SSE300_PERIPH_EXP0.Initialize();
err |= Driver_PPC_SSE300_PERIPH_EXP1.Initialize();
+ err |= Driver_PPC_SSE300_PERIPH_EXP3.Initialize();
/*
* Configure the response to a security violation as a
diff --git a/platform/ext/target/mps3/fvp_sse300/target_cfg.h b/platform/ext/target/mps3/an547/target_cfg.h
similarity index 92%
rename from platform/ext/target/mps3/fvp_sse300/target_cfg.h
rename to platform/ext/target/mps3/an547/target_cfg.h
index 711e4f3..6f0e4f8 100644
--- a/platform/ext/target/mps3/fvp_sse300/target_cfg.h
+++ b/platform/ext/target/mps3/an547/target_cfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021 Arm Limited. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -34,11 +34,14 @@
PPC_SP_MAIN0 = 0,
PPC_SP_MAIN_EXP0 = 1,
PPC_SP_MAIN_EXP1 = 2,
- PPC_SP_PERIPH0 = 3,
- PPC_SP_PERIPH1 = 4,
- PPC_SP_PERIPH_EXP0 = 5,
- PPC_SP_PERIPH_EXP1 = 6,
- PPC_SP_PERIPH_EXP2 = 7,
+ PPC_SP_MAIN_EXP2 = 3,
+ PPC_SP_MAIN_EXP3 = 4,
+ PPC_SP_PERIPH0 = 5,
+ PPC_SP_PERIPH1 = 6,
+ PPC_SP_PERIPH_EXP0 = 7,
+ PPC_SP_PERIPH_EXP1 = 8,
+ PPC_SP_PERIPH_EXP2 = 9,
+ PPC_SP_PERIPH_EXP3 = 10,
};
/**
diff --git a/platform/ext/target/mps3/fvp_sse300/tfm_hal_isolation.c b/platform/ext/target/mps3/an547/tfm_hal_isolation.c
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/tfm_hal_isolation.c
rename to platform/ext/target/mps3/an547/tfm_hal_isolation.c
diff --git a/platform/ext/target/mps3/fvp_sse300/tfm_peripherals_def.h b/platform/ext/target/mps3/an547/tfm_peripherals_def.h
similarity index 100%
rename from platform/ext/target/mps3/fvp_sse300/tfm_peripherals_def.h
rename to platform/ext/target/mps3/an547/tfm_peripherals_def.h
diff --git a/platform/ext/target/mps3/fvp_sse300/README.rst b/platform/ext/target/mps3/fvp_sse300/README.rst
deleted file mode 100644
index e27cfb8..0000000
--- a/platform/ext/target/mps3/fvp_sse300/README.rst
+++ /dev/null
@@ -1,16 +0,0 @@
-Corstone-300 Ethos-U55 FVP
-==========================
-
-Building TF-M
--------------
-
-Follow the instructions in Getting started guide / 2. Build instructions with platform name: mps3/fvp_sse300 (-DTFM_PLATFORM=mps3/fvp_sse300).
-
-Note
-----
-
-This platform support does not provide software for Ethos-U55 IP, only contains base address and interrupt number for it.
-
--------------
-
-*Copyright (c) 2020, Arm Limited. All rights reserved.*
diff --git a/platform/ext/target/mps3/fvp_sse300/device/source/startup_fvp_sse300_mps3_bl2.c b/platform/ext/target/mps3/fvp_sse300/device/source/startup_fvp_sse300_mps3_bl2.c
deleted file mode 100644
index 53e367c..0000000
--- a/platform/ext/target/mps3/fvp_sse300/device/source/startup_fvp_sse300_mps3_bl2.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*
- * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
- * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
- */
-
-#include "cmsis.h"
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler Function Prototype
- *----------------------------------------------------------------------------*/
-typedef void( *pFunc )( void );
-
-/*----------------------------------------------------------------------------
- External References
- *----------------------------------------------------------------------------*/
-extern uint32_t __INITIAL_SP;
-extern uint32_t __STACK_LIMIT;
-
-extern void __PROGRAM_START(void) __NO_RETURN;
-
-/*----------------------------------------------------------------------------
- Internal References
- *----------------------------------------------------------------------------*/
-void Reset_Handler (void) __NO_RETURN;
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-#define DEFAULT_IRQ_HANDLER(handler_name) \
-void __WEAK handler_name(void); \
-void handler_name(void) { \
- while(1); \
-}
-
-/* Exceptions */
-DEFAULT_IRQ_HANDLER(NMI_Handler)
-DEFAULT_IRQ_HANDLER(HardFault_Handler)
-DEFAULT_IRQ_HANDLER(MemManage_Handler)
-DEFAULT_IRQ_HANDLER(BusFault_Handler)
-DEFAULT_IRQ_HANDLER(UsageFault_Handler)
-DEFAULT_IRQ_HANDLER(SecureFault_Handler)
-DEFAULT_IRQ_HANDLER(SVC_Handler)
-DEFAULT_IRQ_HANDLER(DebugMon_Handler)
-DEFAULT_IRQ_HANDLER(PendSV_Handler)
-DEFAULT_IRQ_HANDLER(SysTick_Handler)
-
-DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
-DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
-DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
-DEFAULT_IRQ_HANDLER(TIMER0_Handler)
-DEFAULT_IRQ_HANDLER(TIMER1_Handler)
-DEFAULT_IRQ_HANDLER(TIMER2_Handler)
-DEFAULT_IRQ_HANDLER(MPC_Handler)
-DEFAULT_IRQ_HANDLER(PPC_Handler)
-DEFAULT_IRQ_HANDLER(MSC_Handler)
-DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
-DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
-DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
-DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
-DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
-DEFAULT_IRQ_HANDLER(TIMER3_Handler)
-DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
-DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
-
-DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
-DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
-DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
-DEFAULT_IRQ_HANDLER(I2S_Handler)
-DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
-DEFAULT_IRQ_HANDLER(USB_Handler)
-DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
-DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
-DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
-DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
-DEFAULT_IRQ_HANDLER(UART5_Handler)
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Vector table
- *----------------------------------------------------------------------------*/
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpedantic"
-#endif
-
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
- (pFunc)(&__INITIAL_SP), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* -14: NMI Handler */
- HardFault_Handler, /* -13: Hard Fault Handler */
- MemManage_Handler, /* -12: MPU Fault Handler */
- BusFault_Handler, /* -11: Bus Fault Handler */
- UsageFault_Handler, /* -10: Usage Fault Handler */
- SecureFault_Handler, /* -9: Secure Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* -5: SVCall Handler */
- DebugMon_Handler, /* -4: Debug Monitor Handler */
- 0, /* Reserved */
- PendSV_Handler, /* -2: PendSV Handler */
- SysTick_Handler, /* -1: SysTick Handler */
-
- NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */
- NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
- SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
- TIMER0_Handler, /* 3: TIMER 0 Handler */
- TIMER1_Handler, /* 4: TIMER 1 Handler */
- TIMER2_Handler, /* 5: TIMER 2 Handler */
- 0, /* 6: Reserved */
- 0, /* 7: Reserved */
- 0, /* 8: Reserved */
- MPC_Handler, /* 9: MPC Combined (Secure) Handler */
- PPC_Handler, /* 10: PPC Combined (Secure) Handler */
- MSC_Handler, /* 11: MSC Combined (Secure) Handler */
- BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
- 0, /* 13: Reserved */
- MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
- SYS_PPU_Handler, /* 15: SYS PPU Handler */
- CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
- 0, /* 17: Reserved */
- 0, /* 18: Reserved */
- 0, /* 19: Reserved */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
- TIMER3_Handler, /* 27: TIMER 3 Handler */
- CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */
- CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */
- 0, /* 30: Reserved */
- 0, /* 31: Reserved */
-
- /* External interrupts */
- System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
- UARTRX0_Handler, /* 33: UART 0 RX Handler */
- UARTTX0_Handler, /* 34: UART 0 TX Handler */
- UARTRX1_Handler, /* 35: UART 1 RX Handler */
- UARTTX1_Handler, /* 36: UART 1 TX Handler */
- UARTRX2_Handler, /* 37: UART 2 RX Handler */
- UARTTX2_Handler, /* 38: UART 2 TX Handler */
- UARTRX3_Handler, /* 39: UART 3 RX Handler */
- UARTTX3_Handler, /* 40: UART 3 TX Handler */
- UARTRX4_Handler, /* 41: UART 4 RX Handler */
- UARTTX4_Handler, /* 42: UART 4 TX Handler */
- UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
- UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
- UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
- UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
- UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
- UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
- ETHERNET_Handler, /* 49: Ethernet Handler */
- I2S_Handler, /* 50: Audio I2S Handler */
- TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
- USB_Handler, /* 52: USB Handler */
- SPI_ADC_Handler, /* 53: SPI ADC Handler */
- SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
- SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
- ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
- 0, /* 57: Reserved */
- 0, /* 58: Reserved */
- 0, /* 59: Reserved */
- 0, /* 60: Reserved */
- 0, /* 61: Reserved */
- 0, /* 62: Reserved */
- 0, /* 63: Reserved */
- 0, /* 64: Reserved */
- 0, /* 65: Reserved */
- 0, /* 66: Reserved */
- 0, /* 67: Reserved */
- 0, /* 68: Reserved */
- GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
- GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
- GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
- GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
- GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
- GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
- GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
- GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
- GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
- GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
- GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
- GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
- GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
- GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
- GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
- GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
- GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
- GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
- GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
- GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
- GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
- GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
- GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
- GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
- GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
- GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
- GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
- GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
- GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
- GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
- GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
- GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
- GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
- GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
- GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
- GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
- GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
- GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
- GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
- GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
- GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
- GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
- GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
- GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
- GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
- GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
- GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
- GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
- GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
- GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
- GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
- GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
- GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
- GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
- GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
- GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
- UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
- UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
- UART5_Handler, /* 127: UART 5 combined Interrupt */
- 0, /* 128: Reserved */
- 0, /* 129: Reserved */
- 0, /* 130: Reserved */
-};
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-/*----------------------------------------------------------------------------
- Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void)
-{
- __set_MSPLIM((uint32_t)(&__STACK_LIMIT));
-
- SystemInit(); /* CMSIS System Initialization */
- __PROGRAM_START(); /* Enter PreMain (C library entry point) */
-}
diff --git a/platform/ext/target/mps3/fvp_sse300/device/source/startup_fvp_sse300_mps3_ns.c b/platform/ext/target/mps3/fvp_sse300/device/source/startup_fvp_sse300_mps3_ns.c
deleted file mode 100644
index 0d4cb52..0000000
--- a/platform/ext/target/mps3/fvp_sse300/device/source/startup_fvp_sse300_mps3_ns.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*
- * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
- * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
- */
-
-#include "cmsis.h"
-#include "region.h"
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler Function Prototype
- *----------------------------------------------------------------------------*/
-typedef void( *pFunc )( void );
-
-/*----------------------------------------------------------------------------
- External References
- *----------------------------------------------------------------------------*/
-
-#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit)
-#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base)
-
-extern uint32_t __MSP_INITIAL_SP;
-extern uint32_t __MSP_STACK_LIMIT;
-
-extern uint32_t __INITIAL_SP;
-extern uint32_t __STACK_LIMIT;
-
-extern void __PROGRAM_START(void) __NO_RETURN;
-
-/*----------------------------------------------------------------------------
- Internal References
- *----------------------------------------------------------------------------*/
-void Reset_Handler (void) __NO_RETURN;
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-#define DEFAULT_IRQ_HANDLER(handler_name) \
-void __WEAK handler_name(void); \
-void handler_name(void) { \
- while(1); \
-}
-
-/* Exceptions */
-DEFAULT_IRQ_HANDLER(NMI_Handler)
-DEFAULT_IRQ_HANDLER(HardFault_Handler)
-DEFAULT_IRQ_HANDLER(MemManage_Handler)
-DEFAULT_IRQ_HANDLER(BusFault_Handler)
-DEFAULT_IRQ_HANDLER(UsageFault_Handler)
-DEFAULT_IRQ_HANDLER(SecureFault_Handler)
-DEFAULT_IRQ_HANDLER(SVC_Handler)
-DEFAULT_IRQ_HANDLER(DebugMon_Handler)
-DEFAULT_IRQ_HANDLER(PendSV_Handler)
-DEFAULT_IRQ_HANDLER(SysTick_Handler)
-
-DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
-DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
-DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
-DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler)
-DEFAULT_IRQ_HANDLER(TIMER1_Handler)
-DEFAULT_IRQ_HANDLER(TIMER2_Handler)
-DEFAULT_IRQ_HANDLER(MPC_Handler)
-DEFAULT_IRQ_HANDLER(PPC_Handler)
-DEFAULT_IRQ_HANDLER(MSC_Handler)
-DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
-DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
-DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
-DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
-DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
-DEFAULT_IRQ_HANDLER(TIMER3_Handler)
-DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
-DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
-
-DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
-DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
-DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
-DEFAULT_IRQ_HANDLER(I2S_Handler)
-DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
-DEFAULT_IRQ_HANDLER(USB_Handler)
-DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
-DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
-DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
-DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
-DEFAULT_IRQ_HANDLER(UART5_Handler)
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Vector table
- *----------------------------------------------------------------------------*/
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpedantic"
-#endif
-
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
- (pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* -14: NMI Handler */
- HardFault_Handler, /* -13: Hard Fault Handler */
- MemManage_Handler, /* -12: MPU Fault Handler */
- BusFault_Handler, /* -11: Bus Fault Handler */
- UsageFault_Handler, /* -10: Usage Fault Handler */
- SecureFault_Handler, /* -9: Secure Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* -5: SVCall Handler */
- DebugMon_Handler, /* -4: Debug Monitor Handler */
- 0, /* Reserved */
- PendSV_Handler, /* -2: PendSV Handler */
- SysTick_Handler, /* -1: SysTick Handler */
-
- NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */
- NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
- SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
- TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */
- TIMER1_Handler, /* 4: TIMER 1 Handler */
- TIMER2_Handler, /* 5: TIMER 2 Handler */
- 0, /* 6: Reserved */
- 0, /* 7: Reserved */
- 0, /* 8: Reserved */
- MPC_Handler, /* 9: MPC Combined (Secure) Handler */
- PPC_Handler, /* 10: PPC Combined (Secure) Handler */
- MSC_Handler, /* 11: MSC Combined (Secure) Handler */
- BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
- 0, /* 13: Reserved */
- MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
- SYS_PPU_Handler, /* 15: SYS PPU Handler */
- CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
- 0, /* 17: Reserved */
- 0, /* 18: Reserved */
- 0, /* 19: Reserved */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
- TIMER3_Handler, /* 27: TIMER 3 Handler */
- CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */
- CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */
- 0, /* 30: Reserved */
- 0, /* 31: Reserved */
-
- /* External interrupts */
- System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
- UARTRX0_Handler, /* 33: UART 0 RX Handler */
- UARTTX0_Handler, /* 34: UART 0 TX Handler */
- UARTRX1_Handler, /* 35: UART 1 RX Handler */
- UARTTX1_Handler, /* 36: UART 1 TX Handler */
- UARTRX2_Handler, /* 37: UART 2 RX Handler */
- UARTTX2_Handler, /* 38: UART 2 TX Handler */
- UARTRX3_Handler, /* 39: UART 3 RX Handler */
- UARTTX3_Handler, /* 40: UART 3 TX Handler */
- UARTRX4_Handler, /* 41: UART 4 RX Handler */
- UARTTX4_Handler, /* 42: UART 4 TX Handler */
- UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
- UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
- UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
- UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
- UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
- UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
- ETHERNET_Handler, /* 49: Ethernet Handler */
- I2S_Handler, /* 50: Audio I2S Handler */
- TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
- USB_Handler, /* 52: USB Handler */
- SPI_ADC_Handler, /* 53: SPI ADC Handler */
- SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
- SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
- ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
- 0, /* 57: Reserved */
- 0, /* 58: Reserved */
- 0, /* 59: Reserved */
- 0, /* 60: Reserved */
- 0, /* 61: Reserved */
- 0, /* 62: Reserved */
- 0, /* 63: Reserved */
- 0, /* 64: Reserved */
- 0, /* 65: Reserved */
- 0, /* 66: Reserved */
- 0, /* 67: Reserved */
- 0, /* 68: Reserved */
- GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
- GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
- GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
- GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
- GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
- GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
- GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
- GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
- GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
- GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
- GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
- GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
- GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
- GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
- GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
- GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
- GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
- GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
- GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
- GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
- GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
- GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
- GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
- GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
- GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
- GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
- GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
- GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
- GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
- GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
- GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
- GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
- GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
- GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
- GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
- GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
- GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
- GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
- GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
- GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
- GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
- GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
- GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
- GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
- GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
- GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
- GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
- GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
- GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
- GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
- GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
- GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
- GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
- GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
- GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
- GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
- UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
- UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
- UART5_Handler, /* 127: UART 5 combined Interrupt */
- 0, /* 128: Reserved */
- 0, /* 129: Reserved */
- 0, /* 130: Reserved */
-};
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-/*----------------------------------------------------------------------------
- Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void)
-{
- __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT));
-
- SystemInit(); /* CMSIS System Initialization */
- __ASM volatile("MRS R0, control\n" /* Get control value */
- "ORR R0, R0, #1\n" /* Select switch to unprivilage mode */
- "ORR R0, R0, #2\n" /* Select switch to PSP */
- "MSR control, R0\n" /* Load control register */
- :
- :
- : "r0");
- __PROGRAM_START(); /* Enter PreMain (C library entry point) */
-}
diff --git a/platform/ext/target/mps3/fvp_sse300/device/source/startup_fvp_sse300_mps3_s.c b/platform/ext/target/mps3/fvp_sse300/device/source/startup_fvp_sse300_mps3_s.c
deleted file mode 100644
index 3624024..0000000
--- a/platform/ext/target/mps3/fvp_sse300/device/source/startup_fvp_sse300_mps3_s.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*
- * This file is derivative of CMSIS V5.6.0 startup_ARMv81MML.c
- * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b
- */
-
-#include "cmsis.h"
-#include "region.h"
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler Function Prototype
- *----------------------------------------------------------------------------*/
-typedef void( *pFunc )( void );
-
-/*----------------------------------------------------------------------------
- External References
- *----------------------------------------------------------------------------*/
-
-#define __MSP_INITIAL_SP REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Limit)
-#define __MSP_STACK_LIMIT REGION_NAME(Image$$, ARM_LIB_STACK_MSP, $$ZI$$Base)
-
-extern uint32_t __MSP_INITIAL_SP;
-extern uint32_t __MSP_STACK_LIMIT;
-
-extern uint32_t __INITIAL_SP;
-extern uint32_t __STACK_LIMIT;
-
-extern void __PROGRAM_START(void) __NO_RETURN;
-
-/*----------------------------------------------------------------------------
- Internal References
- *----------------------------------------------------------------------------*/
-void Reset_Handler (void) __NO_RETURN;
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Handler
- *----------------------------------------------------------------------------*/
-#define DEFAULT_IRQ_HANDLER(handler_name) \
-void __WEAK handler_name(void); \
-void handler_name(void) { \
- while(1); \
-}
-
-/* Exceptions */
-DEFAULT_IRQ_HANDLER(NMI_Handler)
-DEFAULT_IRQ_HANDLER(HardFault_Handler)
-DEFAULT_IRQ_HANDLER(MemManage_Handler)
-DEFAULT_IRQ_HANDLER(BusFault_Handler)
-DEFAULT_IRQ_HANDLER(UsageFault_Handler)
-DEFAULT_IRQ_HANDLER(SecureFault_Handler)
-DEFAULT_IRQ_HANDLER(SVC_Handler)
-DEFAULT_IRQ_HANDLER(DebugMon_Handler)
-DEFAULT_IRQ_HANDLER(PendSV_Handler)
-DEFAULT_IRQ_HANDLER(SysTick_Handler)
-
-DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_Handler)
-DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler)
-DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler)
-DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler)
-DEFAULT_IRQ_HANDLER(TIMER1_Handler)
-DEFAULT_IRQ_HANDLER(TIMER2_Handler)
-DEFAULT_IRQ_HANDLER(MPC_Handler)
-DEFAULT_IRQ_HANDLER(PPC_Handler)
-DEFAULT_IRQ_HANDLER(MSC_Handler)
-DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler)
-DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler)
-DEFAULT_IRQ_HANDLER(SYS_PPU_Handler)
-DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler)
-DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler)
-DEFAULT_IRQ_HANDLER(TIMER3_Handler)
-DEFAULT_IRQ_HANDLER(CTI_REQ0_IRQHandler)
-DEFAULT_IRQ_HANDLER(CTI_REQ1_IRQHandler)
-
-DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX0_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX0_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX1_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX1_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX2_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX2_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX3_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX3_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX4_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX4_Handler)
-DEFAULT_IRQ_HANDLER(UART0_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART1_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART2_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART3_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UART4_Combined_Handler)
-DEFAULT_IRQ_HANDLER(UARTOVF_Handler)
-DEFAULT_IRQ_HANDLER(ETHERNET_Handler)
-DEFAULT_IRQ_HANDLER(I2S_Handler)
-DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler)
-DEFAULT_IRQ_HANDLER(USB_Handler)
-DEFAULT_IRQ_HANDLER(SPI_ADC_Handler)
-DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler)
-DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler)
-DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO0_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO1_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_3_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_4_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_5_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_6_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_7_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_8_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_9_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_10_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_11_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_12_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_13_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_14_Handler)
-DEFAULT_IRQ_HANDLER(GPIO2_15_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_0_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_1_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_2_Handler)
-DEFAULT_IRQ_HANDLER(GPIO3_3_Handler)
-DEFAULT_IRQ_HANDLER(UARTRX5_Handler)
-DEFAULT_IRQ_HANDLER(UARTTX5_Handler)
-DEFAULT_IRQ_HANDLER(UART5_Handler)
-
-/*----------------------------------------------------------------------------
- Exception / Interrupt Vector table
- *----------------------------------------------------------------------------*/
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpedantic"
-#endif
-
-extern const pFunc __VECTOR_TABLE[496];
- const pFunc __VECTOR_TABLE[496] __VECTOR_TABLE_ATTRIBUTE = {
- (pFunc)(&__MSP_INITIAL_SP), /* Initial Stack Pointer */
- Reset_Handler, /* Reset Handler */
- NMI_Handler, /* -14: NMI Handler */
- HardFault_Handler, /* -13: Hard Fault Handler */
- MemManage_Handler, /* -12: MPU Fault Handler */
- BusFault_Handler, /* -11: Bus Fault Handler */
- UsageFault_Handler, /* -10: Usage Fault Handler */
- SecureFault_Handler, /* -9: Secure Fault Handler */
- 0, /* Reserved */
- 0, /* Reserved */
- 0, /* Reserved */
- SVC_Handler, /* -5: SVCall Handler */
- DebugMon_Handler, /* -4: Debug Monitor Handler */
- 0, /* Reserved */
- PendSV_Handler, /* -2: PendSV Handler */
- SysTick_Handler, /* -1: SysTick Handler */
-
- NONSEC_WATCHDOG_RESET_Handler, /* 0: Non-Secure Watchdog Reset Handler */
- NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */
- SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */
- TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */
- TIMER1_Handler, /* 4: TIMER 1 Handler */
- TIMER2_Handler, /* 5: TIMER 2 Handler */
- 0, /* 6: Reserved */
- 0, /* 7: Reserved */
- 0, /* 8: Reserved */
- MPC_Handler, /* 9: MPC Combined (Secure) Handler */
- PPC_Handler, /* 10: PPC Combined (Secure) Handler */
- MSC_Handler, /* 11: MSC Combined (Secure) Handler */
- BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */
- 0, /* 13: Reserved */
- MGMT_PPU_Handler, /* 14: MGMT PPU Handler */
- SYS_PPU_Handler, /* 15: SYS PPU Handler */
- CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */
- 0, /* 17: Reserved */
- 0, /* 18: Reserved */
- 0, /* 19: Reserved */
- 0, /* 20: Reserved */
- 0, /* 21: Reserved */
- 0, /* 22: Reserved */
- 0, /* 23: Reserved */
- 0, /* 24: Reserved */
- 0, /* 25: Reserved */
- DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */
- TIMER3_Handler, /* 27: TIMER 3 Handler */
- CTI_REQ0_IRQHandler, /* 28: CTI request 0 IRQ Handler */
- CTI_REQ1_IRQHandler, /* 29: CTI request 1 IRQ Handler */
- 0, /* 30: Reserved */
- 0, /* 31: Reserved */
-
- /* External interrupts */
- System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */
- UARTRX0_Handler, /* 33: UART 0 RX Handler */
- UARTTX0_Handler, /* 34: UART 0 TX Handler */
- UARTRX1_Handler, /* 35: UART 1 RX Handler */
- UARTTX1_Handler, /* 36: UART 1 TX Handler */
- UARTRX2_Handler, /* 37: UART 2 RX Handler */
- UARTTX2_Handler, /* 38: UART 2 TX Handler */
- UARTRX3_Handler, /* 39: UART 3 RX Handler */
- UARTTX3_Handler, /* 40: UART 3 TX Handler */
- UARTRX4_Handler, /* 41: UART 4 RX Handler */
- UARTTX4_Handler, /* 42: UART 4 TX Handler */
- UART0_Combined_Handler, /* 43: UART 0 Combined Handler */
- UART1_Combined_Handler, /* 44: UART 1 Combined Handler */
- UART2_Combined_Handler, /* 45: UART 2 Combined Handler */
- UART3_Combined_Handler, /* 46: UART 3 Combined Handler */
- UART4_Combined_Handler, /* 47: UART 4 Combined Handler */
- UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */
- ETHERNET_Handler, /* 49: Ethernet Handler */
- I2S_Handler, /* 50: Audio I2S Handler */
- TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */
- USB_Handler, /* 52: USB Handler */
- SPI_ADC_Handler, /* 53: SPI ADC Handler */
- SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */
- SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */
- ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */
- 0, /* 56: Reserved */
- 0, /* 57: Reserved */
- 0, /* 58: Reserved */
- 0, /* 59: Reserved */
- 0, /* 60: Reserved */
- 0, /* 61: Reserved */
- 0, /* 62: Reserved */
- 0, /* 63: Reserved */
- 0, /* 64: Reserved */
- 0, /* 65: Reserved */
- 0, /* 66: Reserved */
- 0, /* 67: Reserved */
- 0, /* 68: Reserved */
- GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */
- GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */
- GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */
- GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */
- GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */
- GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */
- GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */
- GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */
- GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */
- GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */
- GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */
- GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */
- GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */
- GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */
- GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */
- GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */
- GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */
- GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */
- GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */
- GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */
- GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */
- GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */
- GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */
- GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */
- GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */
- GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */
- GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */
- GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */
- GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */
- GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */
- GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */
- GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */
- GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */
- GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */
- GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */
- GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */
- GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */
- GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */
- GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */
- GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */
- GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */
- GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */
- GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */
- GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */
- GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */
- GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */
- GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */
- GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */
- GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */
- GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */
- GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */
- GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */
- GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */
- GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */
- GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */
- GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */
- UARTRX5_Handler, /* 125: UART 5 RX Interrupt */
- UARTTX5_Handler, /* 126: UART 5 TX Interrupt */
- UART5_Handler, /* 127: UART 5 combined Interrupt */
- 0, /* 128: Reserved */
- 0, /* 129: Reserved */
- 0, /* 130: Reserved */
-};
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-/*----------------------------------------------------------------------------
- Reset Handler called on controller reset
- *----------------------------------------------------------------------------*/
-void Reset_Handler(void)
-{
- __set_MSPLIM((uint32_t)(&__MSP_STACK_LIMIT));
-
- SystemInit(); /* CMSIS System Initialization */
- __ASM volatile("MRS R0, control\n" /* Get control value */
- "ORR R0, R0, #2\n" /* Select switch to PSP */
- "MSR control, R0\n" /* Load control register */
- :
- :
- : "r0");
- __PROGRAM_START(); /* Enter PreMain (C library entry point) */
-}