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Galanakis, Minos41f85972019-09-30 15:56:40 +01001#################
2Integration guide
3#################
Gyorgy Szingdb9783c2019-04-17 21:08:48 +02004The purpose of this document is to provide a guide on how to integrate TF-M
5with other hardware platforms and operating systems.
6
7*****************
8How to build TF-M
9*****************
10Follow the :doc:`Build instructions <tfm_build_instruction>`.
11
12********************************************************
13How to export files for building non-secure applications
14********************************************************
15Explained in the :doc:`Build instructions <tfm_build_instruction>`.
16
17*************************
18How to add a new platform
19*************************
20The hardware platforms currently supported are:
21
22- Soft Macro Model (SMM) Cortex-M33 SSE-200 subsystem for MPS2+ (AN521)
23- Cortex-M23 IoT Kit subsystem for MPS2+ (AN519)
Marton Berke8aae06f2019-11-25 16:46:12 +010024- Arm SSE-123 Example Subsystem for MPS2+ (AN539)
Jamie Foxb8a92702019-06-05 17:19:31 +010025- Musca-A test chip board (Cortex-M33 SSE-200 subsystem)
Gyorgy Szingdb9783c2019-04-17 21:08:48 +020026- Musca-B1 test chip board (Cortex-M33 SSE-200 subsystem)
Marton Berke8aae06f2019-11-25 16:46:12 +010027- Musca-S1 test chip board (Cortex-M33 SSE-200 subsystem)
Kevin Peng0a142112018-09-21 10:42:22 +080028- CoreLink SSE-200 Subsystem for MPS3 (AN524)
Marton Berkee9803662019-11-11 14:11:05 +010029- DesignStart FPGA on Cloud: Cortex-M33 based platform (SSE-200_AWS)
Gyorgy Szingdb9783c2019-04-17 21:08:48 +020030
31The files related to the supported platforms are contained under the
32``platform`` subfolder. The platform specific files are under
33``platform/ext/target``, which is organised by boards
34(e.g. ``platform/ext/target/mps2``), while the folder ``platform/ext/common``
35is used to store source and header files which are platform generic.
36
37More information about subsystems supported by the MPS2+ board can be found in:
38`MPS2+ homepage <https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2>`__
39
Jamie Foxb8a92702019-06-05 17:19:31 +010040More information about the Musca-A test chip board can be found in:
Gyorgy Szingdb9783c2019-04-17 21:08:48 +020041`Musca-A homepage <https://developer.arm.com/products/system-design/development-boards/iot-test-chips-and-boards/musca-a-test-chip-board>`__
42
43More information about the Musca-B1 test chip board can be found in:
44`Musca-B1 homepage <https://www.arm.com/products/development-tools/development-boards/musca-b1-iot>`__
45
Marton Berke8aae06f2019-11-25 16:46:12 +010046More information about the Musca-S1 test chip board can be found in:
47`Musca-S1 homepage <https://www.arm.com/company/news/2019/05/arm-demonstrates-new-iot-test-chip-and-board>`__
48
Kevin Peng0a142112018-09-21 10:42:22 +080049More information about subsystems supported by the MPS3 board can be found in:
50`MPS3 homepage <https://www.arm.com/products/development-tools/development-boards/mps3>`__
51
Marton Berkee9803662019-11-11 14:11:05 +010052More information about the SSE-200_AWS platform can be found in:
53`SSE-200_AWS product page <https://aws.amazon.com/marketplace/pp/ARM-DesignStart-FPGA-on-Cloud-Cortex-M33-based-pla/B082DMMTLW>`__
54
Gyorgy Szingdb9783c2019-04-17 21:08:48 +020055Generic drivers and startup/scatter files
56=========================================
57The addition of a new platform means the creation of a new subfolder inside
58``target/<board_name>`` to provide an implementation of the drivers currently
59used by TF-M, in particular MPC, PPC, and USART drivers. In addition to the
60drivers, startup and scatter files need to be provided for the supported
61toolchains.
62
63There are also board specific drivers which are used by the board
64platform to interact with the external world, for example during tests, that
65have to be provided, e.g. to blink LEDs or count time in the MPS2 board.
66
67.. Note::
68
69 Currently SST and BL2 bootloader use different flash interface
70
71Target configuration files
72==========================
73Inside the base root folder of the selected target, each implementation has to
74provide its own copy of ``target_cfg.c/.h``. This file has target specific
75configuration functions and settings that are called by the TF-M during the
76platform configuration step during TF-M boot. Examples of the configurations
77performed during this phase are the MPC configuration, the SAU configuration,
78or eventually PPC configuration if supported by the hardware platform.
79Similarly, the ``uart_stdout.c`` is used to provide functions needed to redirect
80the stdout on UART (this is currently used by TF-M to log messages).
81
82Platform retarget files
83=======================
84An important part that each new platform has to provide is the set of retarget
85files which are contained inside the ``retarget`` folder. These files define the
86peripheral base addresses for the platform, both for the secure and non-secure
87aliases (when available), and bind those addresses to the base addresses used by
88the devices available in the hardware platform.
89
90***************************
91How to integrate another OS
92***************************
93To work with TF-M, the OS needs to support the Armv8-M architecture and, in
94particular, it needs to be able to run in the non-secure world. More
95information about OS migration to the Armv8-M architecture can be found in the
96:doc:`OS requirements <os_migration_guide_armv8m>`. Depending upon the system
97configuration this may require configuring drivers to use appropriate address
98ranges.
99
100Interface with TF-M
101===================
102The files needed for the interface with TF-M are exported at the
103``<build_dir>/install/export/tfm`` path. The NS side is only allowed to call
104TF-M secure functions (veneers) from the NS Thread mode. For this reason, the
105API is a collection of functions in the ``<build_dir>/install/export/tfm/inc``
106directory. For example, the interface for the Secure STorage (SST) service
107is described in the file ``psa_sst_api.h`` as a collection of functions that
108call service veneer functions. This API is a wrapper for the secure veneers,
109and returns the return value from the service to the caller.
110
111The secure storage service uses a numerical ID, to identify the clients that use
112the service. For details see
113:doc:`ns client identification documentation <tfm_ns_client_identification>`.
114
115Interface with non-secure world regression tests
116================================================
117A non-secure application that wants to run the non-secure regression tests
118needs to call the ``tfm_non_secure_client_run_tests()``. This function is
119exported into the header file ``test_framework_integ_test.h`` inside the
120``<build_dir>/install`` folder structure in the test specific files,
121i.e. ``<build_dir>/install/export/tfm/test/inc``. The non-secure regression
122tests are precompiled and delivered as a static library which is available in
123``<build_dir>/install/export/tfm/test/lib``, so that the non-secure application
124needs to link against the library to be able to invoke the
125``tfm_non_secure_client_run_tests()`` function. The SST non-secure side
126regression tests rely on some OS functionality e.g. threads, mutexes etc. These
127functions comply with CMSIS RTOS2 standard and have been exported as thin
128wrappers defined in ``os_wrapper.h`` contained in
129``<build_dir>/install/export/tfm/test/inc``. OS needs to provide the
130implementation of these wrappers to be able to run the tests.
131
132NS client Identification
133========================
134See
135:doc:`ns client identification documentation <tfm_ns_client_identification>`.
136
Mate Toth-Pal12d7a182019-04-28 14:05:21 +0200137*********************
138Non-secure interrupts
139*********************
140Non-secure interrupts are allowed to preempt Secure thread mode.
141With the current implementation, a NSPE task can spoof the identity of another
142NSPE task. This is an issue only when NSPE has provisions for task isolation.
143Note, that ``AIRCR.PRIS`` is still set to restrict the priority range available
144to NS interrupts to the lower half of available priorities so that it wouldn't
145be possible for any non-secure interrupt to preempt a higher-priority secure
146interrupt.
147
Gyorgy Szingdb9783c2019-04-17 21:08:48 +0200148--------------
149
150*Copyright (c) 2017-2019, Arm Limited. All rights reserved.*