commit 041e48a9200e1578ecb3d47da642120455296036
author Akshay Belsare <akshay.belsare@amd.com> Fri Jul 14 14:20:31 2023 +0530
committer Manish V Badarkhe <manish.badarkhe@arm.com> Thu Jul 20 10:13:41 2023 +0200
tree 714ec777c3f629b081c09175a6c188c6e3d2764c
parent 6dafb5f6006eaf2a41fc4e2be80144d29f037226

build(versal): update config for ddr

A build time parameter XILINX_OF_BOARD_DTB_ADDR is introduced
for Versal platform which provides the DTB address.
When the TF_A is placed and executed from DDR and DTB load address
is provided in above param, TF-A will update the DTB, at runtime,
adding a reserved memory node for its address range in ddr.

Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
Change-Id: I7d79cd37efeb4a3382cafd302461b876f1732277

tf_config/versal-ddr

diff --git a/tf_config/versal-ddr b/tf_config/versal-ddr
index 711ae38..87abac1 100644
--- a/tf_config/versal-ddr
+++ b/tf_config/versal-ddr
@@ -1,5 +1,6 @@
 CROSS_COMPILE=aarch64-none-elf-
 PLAT=versal
 RESET_TO_BL31=1
-VERSAL_ATF_MEM_BASE=0x50000000
+VERSAL_ATF_MEM_BASE=0x70000000
 VERSAL_ATF_MEM_SIZE=0x80000
+XILINX_OF_BOARD_DTB_ADDR=0x1000