spm: enable pointer authentication and BTI
Use romlib in tbb/dualroot secure boot configurations. The debug build
is bigger when PAuth+BTI is enabled and BL2/BL31 no longer fit Trusted
SRAM. Update related run configs such that they call the rom lib shell
functions.
Update to arch version v8.5 in run configs such that BTI can be enabled.
Add has_branch_target_exception=1 to run configs such that BTI is
enabled.
Add restriction_on_speculative_execution option to base-aemva-common.sh.
Add restriction_on_speculative_execution=2 to run configs such that
SCXTNUM_ELx registers are supported in the EL2 context switch routine.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ib9f9996fd4d4d6e7b5975a5f7b64760169b76a6a
diff --git a/model/base-aemva-common.sh b/model/base-aemva-common.sh
index d1c1024..d1ac356 100644
--- a/model/base-aemva-common.sh
+++ b/model/base-aemva-common.sh
@@ -133,6 +133,8 @@
${has_branch_target_exception+-C cluster0.has_branch_target_exception=$has_branch_target_exception}
+${restriction_on_speculative_execution+-C cluster0.restriction_on_speculative_execution=$restriction_on_speculative_execution}
+
${gicv3_ext_interrupt_range+-C cluster0.gicv3.extended-interrupt-range-support=$gicv3_ext_interrupt_range}
EOF
@@ -230,6 +232,8 @@
${has_branch_target_exception+-C cluster1.has_branch_target_exception=$has_branch_target_exception}
+${restriction_on_speculative_execution+-C cluster1.restriction_on_speculative_execution=$restriction_on_speculative_execution}
+
${gicv3_ext_interrupt_range+-C cluster1.gicv3.extended-interrupt-range-support=$gicv3_ext_interrupt_range}
EOF